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nishtahir/arty-blaze
|
src/bd/system/ip/system_lmb_bram_0/system_lmb_bram_0_sim_netlist.vhdl
| 1 | 202,895 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:45:44 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_lmb_bram_0/system_lmb_bram_0_sim_netlist.vhdl
-- Design : system_lmb_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_lmb_bram_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_lmb_bram_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end system_lmb_bram_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of system_lmb_bram_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "INDEPENDENT";
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[3:0][0:8191]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 2) => addrb(12 downto 0),
ADDRBWRADDR(1 downto 0) => B"11",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 4) => B"0000000000000000000000000000",
DIBDI(3 downto 0) => dinb(3 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 4),
DOBDO(3 downto 0) => doutb(3 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "INDEPENDENT";
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[7:4][0:8191]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 2) => addrb(12 downto 0),
ADDRBWRADDR(1 downto 0) => B"11",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 4) => B"0000000000000000000000000000",
DIBDI(3 downto 0) => dinb(3 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 4),
DOBDO(3 downto 0) => doutb(3 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "INDEPENDENT";
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[11:8][0:8191]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 2) => addrb(12 downto 0),
ADDRBWRADDR(1 downto 0) => B"11",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 4) => B"0000000000000000000000000000",
DIBDI(3 downto 0) => dinb(3 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 4),
DOBDO(3 downto 0) => doutb(3 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "INDEPENDENT";
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:12][0:8191]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 2) => addrb(12 downto 0),
ADDRBWRADDR(1 downto 0) => B"11",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 4) => B"0000000000000000000000000000",
DIBDI(3 downto 0) => dinb(3 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 4),
DOBDO(3 downto 0) => doutb(3 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "INDEPENDENT";
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[19:16][0:8191]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 2) => addrb(12 downto 0),
ADDRBWRADDR(1 downto 0) => B"11",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 4) => B"0000000000000000000000000000",
DIBDI(3 downto 0) => dinb(3 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 4),
DOBDO(3 downto 0) => doutb(3 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "INDEPENDENT";
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[23:20][0:8191]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 2) => addrb(12 downto 0),
ADDRBWRADDR(1 downto 0) => B"11",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 4) => B"0000000000000000000000000000",
DIBDI(3 downto 0) => dinb(3 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 4),
DOBDO(3 downto 0) => doutb(3 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "INDEPENDENT";
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[27:24][0:8191]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 2) => addrb(12 downto 0),
ADDRBWRADDR(1 downto 0) => B"11",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 4) => B"0000000000000000000000000000",
DIBDI(3 downto 0) => dinb(3 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 4),
DOBDO(3 downto 0) => doutb(3 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "INDEPENDENT";
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:28][0:8191]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 2) => addra(12 downto 0),
ADDRARDADDR(1 downto 0) => B"11",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 2) => addrb(12 downto 0),
ADDRBWRADDR(1 downto 0) => B"11",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 4) => B"0000000000000000000000000000",
DIBDI(3 downto 0) => dinb(3 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 4) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 4),
DOBDO(3 downto 0) => doutb(3 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_lmb_bram_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_lmb_bram_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end system_lmb_bram_0_blk_mem_gen_prim_width;
architecture STRUCTURE of system_lmb_bram_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.system_lmb_bram_0_blk_mem_gen_prim_wrapper
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \system_lmb_bram_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_lmb_bram_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_lmb_bram_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end system_lmb_bram_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of system_lmb_bram_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.system_lmb_bram_0_blk_mem_gen_prim_width
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
dinb(3 downto 0) => dinb(3 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[1].ram.r\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(7 downto 4),
dinb(3 downto 0) => dinb(7 downto 4),
douta(3 downto 0) => douta(7 downto 4),
doutb(3 downto 0) => doutb(7 downto 4),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_width__parameterized1\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(11 downto 8),
dinb(3 downto 0) => dinb(11 downto 8),
douta(3 downto 0) => douta(11 downto 8),
doutb(3 downto 0) => doutb(11 downto 8),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[3].ram.r\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_width__parameterized2\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(15 downto 12),
dinb(3 downto 0) => dinb(15 downto 12),
douta(3 downto 0) => douta(15 downto 12),
doutb(3 downto 0) => doutb(15 downto 12),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[4].ram.r\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(19 downto 16),
dinb(3 downto 0) => dinb(19 downto 16),
douta(3 downto 0) => douta(19 downto 16),
doutb(3 downto 0) => doutb(19 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[5].ram.r\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_width__parameterized4\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(23 downto 20),
dinb(3 downto 0) => dinb(23 downto 20),
douta(3 downto 0) => douta(23 downto 20),
doutb(3 downto 0) => doutb(23 downto 20),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[6].ram.r\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(27 downto 24),
dinb(3 downto 0) => dinb(27 downto 24),
douta(3 downto 0) => douta(27 downto 24),
doutb(3 downto 0) => doutb(27 downto 24),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[7].ram.r\: entity work.\system_lmb_bram_0_blk_mem_gen_prim_width__parameterized6\
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(31 downto 28),
dinb(3 downto 0) => dinb(31 downto 28),
douta(3 downto 0) => douta(31 downto 28),
doutb(3 downto 0) => doutb(31 downto 28),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_lmb_bram_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_lmb_bram_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end system_lmb_bram_0_blk_mem_gen_top;
architecture STRUCTURE of system_lmb_bram_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.system_lmb_bram_0_blk_mem_gen_generic_cstr
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_lmb_bram_0_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_lmb_bram_0_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end system_lmb_bram_0_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of system_lmb_bram_0_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.system_lmb_bram_0_blk_mem_gen_top
port map (
addra(12 downto 0) => addra(12 downto 0),
addrb(12 downto 0) => addrb(12 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_lmb_bram_0_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "8";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 19.3686 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "system_lmb_bram_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 8192;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 8192;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 8192;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 8192;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_lmb_bram_0_blk_mem_gen_v8_3_5 : entity is "yes";
end system_lmb_bram_0_blk_mem_gen_v8_3_5;
architecture STRUCTURE of system_lmb_bram_0_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.system_lmb_bram_0_blk_mem_gen_v8_3_5_synth
port map (
addra(12 downto 0) => addra(14 downto 2),
addrb(12 downto 0) => addrb(14 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_lmb_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_lmb_bram_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_lmb_bram_0 : entity is "system_lmb_bram_0,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_lmb_bram_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_lmb_bram_0 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end system_lmb_bram_0;
architecture STRUCTURE of system_lmb_bram_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "8";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 19.3686 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "system_lmb_bram_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 8192;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 8192;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 8192;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 8192;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_lmb_bram_0_blk_mem_gen_v8_3_5
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
|
apache-2.0
|
eab94a0626a2c4865efcd0fa060cad1e
| 0.734626 | 4.497783 | false | false | false | false |
daniw/add
|
floppy/mcu/ram.vhd
| 2 | 1,423 |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: (2**AW)*DW + DW (or equivalent BRAM/distr. memory)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity ram is
port(clk : in std_logic;
-- RAM bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus
);
end ram;
architecture rtl of ram is
type t_ram is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
signal ram_array : t_ram := (others => (others => '0'));
begin
-----------------------------------------------------------------------------
-- sequential process: RAM (read before write)
-----------------------------------------------------------------------------
P_ram: process(clk)
begin
if rising_edge(clk) then
if bus_in.we = '1' then
ram_array(to_integer(unsigned(bus_in.addr))) <= bus_in.data;
end if;
bus_out.data <= ram_array(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
gpl-2.0
|
74828942ca403bacdd461fd20a0ce672
| 0.413212 | 4.433022 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/PSRModifier_tb.vhd
| 2 | 3,138 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PSRModifier_tb IS
END PSRModifier_tb;
ARCHITECTURE behavior OF PSRModifier_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PSRModifier
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Oper1 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
NZVC : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal ALURESULT : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal NZVC : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PSRModifier PORT MAP (
ALUOP => ALUOP,
Oper2 => Oper2,
Oper1 => Oper1,
ALURESULT => ALURESULT,
NZVC => NZVC
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Oper1<="00000000000000000000000000001111";
Oper2<="00000000000000000000000000010000";
ALUOP<="001011"; --ANDcc
ALURESULT<="00000000000000000000000000000000";
wait for 20 ns;
Oper1<="00000000001111111000000000011111";
Oper2<="00000000000000000000000000000000";
ALUOP<="001100"; --ANDNcc
ALURESULT<="00000000000111111100000000001111";
wait for 20 ns;
Oper1<="11100000000000000000000000000000";
Oper2<="00111111111111111111111111100000";
ALUOP<="001101"; --ORcc
ALURESULT<="11111111111111111111111111100000";
wait for 20 ns;
Oper1<="00000000000000011111100000000000";
Oper2<="00000000000000000000000011111111";
ALUOP<="001110"; --ORNcc
ALURESULT<="11111111111111111111111100000000";
wait for 20 ns;
Oper1<="10000000000000000000000000001111";
Oper2<="00000000000000000000000000010000";
ALUOP<="001111"; --XORcc
ALURESULT<="10000000000000000000000000011111";
wait for 20 ns;
Oper1<="00000111111111100000000000000000";
Oper2<="11111000000000011111111111111111";
ALUOP<="010000"; --XNORcc
ALURESULT<="00000000000000000000000000000000";
wait for 20 ns;
Oper1<="10000000000000000000000000001111";
Oper2<="10000000000000000000000000010000";
ALUOP<="010001"; --ADDcc
ALURESULT<="00000000000000000000000000011111";
wait for 20 ns;
Oper1<="11000000000000000000000000001111";
Oper2<="11000000000000000000000000010000";
ALUOP<="010011"; --ADDXcc
ALURESULT<="10000000000000000000000000011111";
wait for 20 ns;
Oper1<="10000000000000000000000000001111";
Oper2<="01111000000000000000000000000000";
ALUOP<="010100"; --SUBcc
ALURESULT<="00001000000000000000000000001111";
wait for 20 ns;
Oper1<="00000000000000000000000000001111";
Oper2<="10000000000000000000000000010000";
ALUOP<="010110"; --SUBXcc
ALURESULT<="01111111111111111111111111111111";
wait for 20 ns;
wait;
end process;
END;
|
mit
|
b30f11b576a25024a119fe6693439640
| 0.687699 | 4.382682 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_0_0/synth/system_axi_gpio_0_0.vhd
| 1 | 10,187 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END system_axi_gpio_0_0;
ARCHITECTURE system_axi_gpio_0_0_arch OF system_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_0_0_arch : ARCHITECTURE IS "system_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "system_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=20,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 20,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_0_arch;
|
apache-2.0
|
e6f3e3ce5b9c586d907fed245359c457
| 0.688132 | 3.166615 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/Sumador32bits_tb.vhd
| 1 | 1,388 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Sumador32bits_tb IS
END Sumador32bits_tb;
ARCHITECTURE behavior OF Sumador32bits_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sumador32bits
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Result : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sumador32bits PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
Oper1<="11110000000000000000000000000000";
Oper2<="00000000000000000000000000000100";
wait for 20 ns;
Oper1<="01110000000000000000000000000111";
Oper2<="10000000000000000000000000000101";
wait for 20 ns;
Oper1<="11111111110000101100000011000111";
Oper2<="11100000100011111111111000001111";
wait for 20 ns;
Oper1<="00000000000000000000000011000111";
Oper2<="00000000111100001111000011111111";
wait;
end process;
END;
|
mit
|
279a8fb8e9acc077775b4e3226b7dea9
| 0.638329 | 4.118694 | false | false | false | false |
kaott/16-bit-risc
|
vhdl/alu4.vhd
| 4 | 1,318 |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity alu4 is
port( A, B : in std_logic_vector(3 downto 0);
LESS, CIN : in std_logic;
SEL : in std_logic_vector(2 downto 0);
F : out std_logic_vector(3 downto 0);
COUT, OVERFLOW, SET, ZERO : out std_logic
);
end alu4;
architecture logic of alu4 is
signal s0, s1, s2, s3, s4, s5, s6, s7 : std_logic_vector(3 downto 0);
signal c0, c1 : std_logic;
begin
cADD: ADD4 port map(A, B, CIN, s0, c0);
cOR: BWOR4 port map(A, B, s1);
cAND: BWAND4 port map(A, B, s2);
cINV1: PINV4 port map(B, SEL(2), s4);
cSUB: ADD4 port map(A, s4, CIN, s3, c1);
process(LESS, s3, s6)
begin
if LESS = '1' then
s6 <= "0001";
SET <= s3(3);
else
s6 <= "0000";
set <= s3(3);
end if;
end process;
MUX0: MUX4X4 port map(SEL(1) & (SEL(2) or SEL(0)), s2, s1, s0, s3, s5);
MUX1: MUX4X4 port map('0' & (SEL(2) and SEL(0)), s5, s6, "0000", "0000", s7);
process(SEL, c0, c1)
begin
if SEL = "010" then
COUT <= c0;
elsif SEL = "110" then
COUT <= c1;
end if;
end process;
process(s7, A, B)
begin
if s7 = "0000" then
ZERO <= '1';
else
ZERO <= '0';
end if;
if ((A(3) = B(3)) and (s7(3) /= B(3))) then
OVERFLOW <= '1';
else
OVERFLOW <= '0';
end if;
end process;
F <= s7;
end logic;
|
mit
|
44fc8cdba9b66c9460787149b93e9749
| 0.564492 | 2.204013 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/PSR_tb.vhd
| 1 | 1,665 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PSR_tb IS
END PSR_tb;
ARCHITECTURE behavior OF PSR_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PSR
PORT(
NZVC : IN std_logic_vector(3 downto 0);
nCWP : IN std_logic;
CLK : IN std_logic;
rst : IN std_logic;
CWP : OUT std_logic;
icc: OUT STD_LOGIC_VECTOR(3 downto 0);
C : OUT std_logic
);
END COMPONENT;
--Inputs
signal NZVC : std_logic_vector(3 downto 0) := (others => '0');
signal nCWP : std_logic := '0';
signal CLK : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal CWP : std_logic;
signal icc: std_logic_vector(3 downto 0);
signal C : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PSR PORT MAP (
NZVC => NZVC,
nCWP => nCWP,
CLK => CLK,
rst => rst,
CWP => CWP,
icc => icc,
C => C
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
NZVC<="1000";
wait for 40 ns;
NZVC<="0100";
wait for 40 ns;
NZVC<="1001";
nCWP<='1';
wait for 40 ns;
NZVC<="0000";
wait for 40 ns;
NZVC<="0011";
wait for 40 ns;
nCWP<='0';
wait for 40 ns;
rst<='1';
wait;
end process;
END;
|
mit
|
0f2d725faee4f34c954faf9831e87700
| 0.515315 | 3.46875 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/proc_common_v3_30_a/hdl/src/vhdl/system_xadc_wiz_0_0_conv_funs_pkg.vhd
| 1 | 15,251 |
----------------------------------------------------------------------------
-- conv_funs_pkg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
----------------------------------------------------------------------------
-- Filename: conv_funs_pkg.vhd
--
-- Description:
-- Various string conversion functions.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- conv_funs_pkg.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: unknown
-- Revision: $Revision: 1.1.4.1 $
-- Date: $1/1/2002$
--
-- History:
-- XXX 1/1/2002 Initial Version
--
-- DET 1/17/2008 v3_30_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package system_xadc_wiz_0_0_conv_funs_pkg is
-- hex string to std_logic_vector
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- octal string to std_logic_vector
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- binary string to std_logic_vector
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- string to std_logic_vector
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
end system_xadc_wiz_0_0_conv_funs_pkg;
--
--------------------------------------------------------------------------------
--
package body system_xadc_wiz_0_0_conv_funs_pkg is
type basetype is (binary, octal, decimal, hex);
function max(x, y : INTEGER) return INTEGER is
begin
if x > y then return x; else return y; end if;
end max;
function MIN(x, y : INTEGER) return INTEGER is
begin
if x < y then return x; else return y; end if;
end MIN;
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*4, result will be truncated on the left
-- if instring is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*4, return_length);
variable char_ptr : INTEGER range -3 to max(instring'LENGTH*4, return_length) := max(instring'LENGTH*4, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*4, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-3 to char_ptr) := "0000";
when '1' => return_vector(char_ptr-3 to char_ptr) := "0001";
when '2' => return_vector(char_ptr-3 to char_ptr) := "0010";
when '3' => return_vector(char_ptr-3 to char_ptr) := "0011";
when '4' => return_vector(char_ptr-3 to char_ptr) := "0100";
when '5' => return_vector(char_ptr-3 to char_ptr) := "0101";
when '6' => return_vector(char_ptr-3 to char_ptr) := "0110";
when '7' => return_vector(char_ptr-3 to char_ptr) := "0111";
when '8' => return_vector(char_ptr-3 to char_ptr) := "1000";
when '9' => return_vector(char_ptr-3 to char_ptr) := "1001";
when 'a'|'A' => return_vector(char_ptr-3 to char_ptr) := "1010";
when 'b'|'B' => return_vector(char_ptr-3 to char_ptr) := "1011";
when 'c'|'C' => return_vector(char_ptr-3 to char_ptr) := "1100";
when 'd'|'D' => return_vector(char_ptr-3 to char_ptr) := "1101";
when 'e'|'E' => return_vector(char_ptr-3 to char_ptr) := "1110";
when 'f'|'F' => return_vector(char_ptr-3 to char_ptr) := "1111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-3 to char_ptr) := "UUUU";
-- when 'X' => return_vector(char_ptr-3 to char_ptr) := "XXXX";
-- when 'Z' => return_vector(char_ptr-3 to char_ptr) := "ZZZZ";
-- when 'W' => return_vector(char_ptr-3 to char_ptr) := "WWWW";
-- when 'H' => return_vector(char_ptr-3 to char_ptr) := "HHHH";
-- when 'L' => return_vector(char_ptr-3 to char_ptr) := "LLLL";
-- when '-' => return_vector(char_ptr-3 to char_ptr) := "----";
-- but synplicity does
when '_' => char_ptr := char_ptr + 4;
when others =>
assert FALSE
report lf &
"hex_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '----'"
severity WARNING;
return_vector(char_ptr-3 to char_ptr) := "----";
end case;
char_ptr := char_ptr - 4;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end hex_string_to_slv;
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*3, result will be truncated on the left
-- if instring is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*3, return_length);
variable char_ptr : INTEGER range -2 to max(instring'LENGTH*3, return_length) := max(instring'LENGTH*3, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*3, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-2 to char_ptr) := "000";
when '1' => return_vector(char_ptr-2 to char_ptr) := "001";
when '2' => return_vector(char_ptr-2 to char_ptr) := "010";
when '3' => return_vector(char_ptr-2 to char_ptr) := "011";
when '4' => return_vector(char_ptr-2 to char_ptr) := "100";
when '5' => return_vector(char_ptr-2 to char_ptr) := "101";
when '6' => return_vector(char_ptr-2 to char_ptr) := "110";
when '7' => return_vector(char_ptr-2 to char_ptr) := "111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-2 to char_ptr) := "UUU";
-- when 'X' => return_vector(char_ptr-2 to char_ptr) := "XXX";
-- when 'Z' => return_vector(char_ptr-2 to char_ptr) := "ZZZ";
-- when 'W' => return_vector(char_ptr-2 to char_ptr) := "WWW";
-- when 'H' => return_vector(char_ptr-2 to char_ptr) := "HHH";
-- when 'L' => return_vector(char_ptr-2 to char_ptr) := "LLL";
-- when '-' => return_vector(char_ptr-2 to char_ptr) := "---";
-- but synplicity does
when '_' => char_ptr := char_ptr + 3;
when others =>
assert FALSE
report lf &
"oct_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '---'"
severity WARNING;
return_vector(char_ptr-2 to char_ptr) := "---";
end case;
char_ptr := char_ptr - 3;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end oct_string_to_slv;
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length, result will be truncated on the left
-- if instring is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH, return_length);
variable char_ptr : INTEGER range 0 to max(instring'LENGTH, return_length)+1 := max(instring'LENGTH, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr) := '0';
when '1' => return_vector(char_ptr) := '1';
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr) := 'U';
-- when 'X' => return_vector(char_ptr) := 'X';
-- when 'Z' => return_vector(char_ptr) := 'Z';
-- when 'W' => return_vector(char_ptr) := 'W';
-- when 'H' => return_vector(char_ptr) := 'H';
-- when 'L' => return_vector(char_ptr) := 'L';
-- when '-' => return_vector(char_ptr) := '-';
-- but synplicity does
when '_' => char_ptr := char_ptr + 1;
when others =>
assert FALSE
report lf &
"bin_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '-'"
severity WARNING;
return_vector(char_ptr) := '-';
end case;
char_ptr := char_ptr - 1;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end bin_string_to_slv;
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
variable instring_length : POSITIVE := instring'LENGTH;
variable temp_string : STRING(1 to instring'LENGTH-2);
begin -- function string_to_std_logic_vector
if instring(1) = '0' and (instring(2) = 'x' or instring(2) = 'X') then
temp_string := instring(3 to instring_length);
return hex_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'o' or instring(2) = 'O') then
temp_string := instring(3 to instring_length);
return oct_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'b' or instring(2) = 'B') then
temp_string := instring(3 to instring_length);
return bin_string_to_slv(temp_string, return_length);
else
return bin_string_to_slv(instring, return_length);
end if;
end function string_to_std_logic_vector;
end system_xadc_wiz_0_0_conv_funs_pkg;
|
apache-2.0
|
7b65ec90541687b7f11b6fb7583277d1
| 0.505213 | 4.058276 | false | false | false | false |
eaglewyng/FPGA2048
|
randomGenerator.vhd
| 1 | 1,148 |
----------------------------------------------------------------------------------
-- Engineer: Parker Ridd and Travis Chambers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity randomGenerator is
generic ( width : integer := 4);
Port (
clk : in STD_LOGIC;
random_num : out STD_LOGIC_VECTOR(width-1 downto 0) --output vector
);
end randomGenerator;
architecture Behavioral of randomGenerator is
begin
process(clk)
variable rand_temp : std_logic_vector(width-1 downto 0):=("1000");
variable temp : std_logic := '0';
begin
if(rising_edge(clk)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
random_num <= rand_temp;
end process;
end Behavioral;
|
mit
|
4d666c53b164dec4392d6fec8f34081e
| 0.618467 | 3.918089 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_rst_clk_wiz_1_100M_0/sim/system_rst_clk_wiz_1_100M_0.vhd
| 1 | 5,865 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY system_rst_clk_wiz_1_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_clk_wiz_1_100M_0;
ARCHITECTURE system_rst_clk_wiz_1_100M_0_arch OF system_rst_clk_wiz_1_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_clk_wiz_1_100M_0_arch;
|
apache-2.0
|
3a61137d519e775b59aff3be1b0059c1
| 0.706394 | 3.56102 | false | false | false | false |
jeffmagina/ECE368
|
Project1/RISC_MACHINE/RISC_MACHINE.vhd
| 1 | 3,308 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:23:34 03/25/2015
-- Design Name:
-- Module Name: RISC_MACHINE - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RISC_MACHINE is
Port( CLK : IN STD_LOGIC;
PC_RESET: IN STD_LOGIC;
RISC_INST_ENB : IN STD_LOGIC;
CCR_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT: OUT STD_LOGIC_VECTOR (15 downto 0)
);
end RISC_MACHINE;
architecture Structural of RISC_MACHINE is
signal instruction_in, FETCH_out, fpu_out, OP1_out, OP2_out, s_Bank_Data, s_OPA_REG_A, EX_Forward_out: STD_LOGIC_VECTOR(15 downto 0);
signal pc : STD_LOGIC_VECTOR (9 downto 0);
signal DEC_immediate : STD_LOGIC_VECTOR (7 downto 0);
signal write_address, OPA_OPCODE, DEC_opcode, DEC_reg_a, s_Dec_REG_A,s_DEC_OPCODE_OUT : STD_LOGIC_VECTOR(3 downto 0);
signal OP1_SEL, OP2_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal bank_RW, WB_MEM_WE, WB_MUX_SEL : STD_LOGIC;
begin
U1: entity work.FETCH
Port Map ( CLK => CLK,
DATAIN => instruction_in,
INST_ENB => RISC_INST_ENB,
INST_OUT => FETCH_out,
PC_OUT => pc,
WE => '0'
);
U2: entity work.decode
Port Map ( CLK => CLK,
INST_IN => FETCH_out,
OPCODE => DEC_opcode,
REG_A => DEC_reg_a,
IMMEDIATE => DEC_immediate
);
U3: entity work.op_access
Port Map ( CLK => CLK,
OPCODE_IN => DEC_opcode,
REG_A => DEC_reg_a,
IMMEDIATE => DEC_immediate,
W_ADDR => Write_Address,
OP1_MUX_SEL => OP1_SEL,
OP2_MUX_SEL => OP2_SEL,
BANK_R_W => bank_RW,
BANK_ENB => '1',
BANK_DATA => s_Bank_Data,
DEC_REG_ADDR => s_Dec_REG_A,
OPCODE_OUT => OPA_OPCODE,
EX_FWD_IN => EX_Forward_out,
EX_FWD_ADDR => s_Dec_REG_A,
WB_FWD_IN => s_Bank_Data,
WB_FWD_ADDR => Write_Address,
OP1_OUT => OP1_out,
OP2_OUT => OP2_out
);
U4: entity work.execute
Port Map ( CLK => CLK,
OPCODE => OPA_OPCODE,
OP1 => OP1_out,
OP2 => OP2_out,
Dec_Reg_A_IN => s_Dec_REG_A,
OPA_REG_A => s_OPA_REG_A,
Dec_Reg_A_OUT => Write_Address,
DEC_OPCODE_OUT=> s_DEC_OPCODE_OUT,
EX_FWD_OUT => EX_Forward_out,
FPU_OUT => fpu_out,
CCR => CCR_OUT
);
U5: entity work.write_back
Port Map ( CLK => CLK,
DATA_WE => WB_MEM_WE,
FPU_IN => fpu_out,
REG_A => s_OPA_REG_A,
D_OUT_SEL => WB_MUX_SEL,
WB_OUT => s_Bank_Data
);
Cntrl_unit: entity work.control_unit
Port Map( CLK => CLK,
OPA_OPCODE => DEC_opcode,
OP1_MUX_SEL => OP1_SEL,
OP2_MUX_SEL => OP2_SEL,
REG_BANK_WE => bank_RW,
DATA_MEM_WE => WB_MEM_WE,
WB_OPCODE => s_DEC_OPCODE_OUT,
OPA_D_OUT_SEL => WB_MUX_SEL
);
end Structural;
|
mit
|
b28eb686e6d345e6c42ce77ab4945a6a
| 0.508767 | 2.891608 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/MUX_RFDEST_tb.vhd
| 1 | 956 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MUX_RFDEST_tb IS
END MUX_RFDEST_tb;
ARCHITECTURE behavior OF MUX_RFDEST_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX_RFDEST
PORT(
RD : IN std_logic_vector(5 downto 0);
RFDEST : IN std_logic;
nRD : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal RD : std_logic_vector(5 downto 0) := (others => '0');
signal RFDEST : std_logic := '0';
--Outputs
signal nRD : std_logic_vector(5 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX_RFDEST PORT MAP (
RD => RD,
RFDEST => RFDEST,
nRD => nRD
);
-- Stimulus process
stim_proc: process
begin
RFDEST<='1';
RD<="010011";
wait for 20 ns;
RFDEST<='0';
RD<="100010";
wait;
end process;
END;
|
mit
|
31b17624bd05246102bcb2796f27be91
| 0.541841 | 3.705426 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_iic_0_0/system_axi_iic_0_0_sim_netlist.vhdl
| 1 | 392,367 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:17 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_iic_0_0/system_axi_iic_0_0_sim_netlist.vhdl
-- Design : system_axi_iic_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_SRL_FIFO is
port (
Rc_Data_Exists : out STD_LOGIC;
Rc_addr : out STD_LOGIC_VECTOR ( 0 to 3 );
Rc_fifo_data : out STD_LOGIC_VECTOR ( 0 to 7 );
p_6_out : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
Data_Exists_DFF_0 : out STD_LOGIC;
Bus2IIC_Reset : in STD_LOGIC;
D_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\data_i2c_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
Msms_set : in STD_LOGIC;
\RD_FIFO_CNTRL.Rc_fifo_rd_reg\ : in STD_LOGIC;
\RD_FIFO_CNTRL.Rc_fifo_wr_reg\ : in STD_LOGIC;
Rc_fifo_rd : in STD_LOGIC;
Rc_fifo_rd_d : in STD_LOGIC;
Rc_fifo_wr_d : in STD_LOGIC;
Rc_fifo_wr : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_SRL_FIFO : entity is "SRL_FIFO";
end system_axi_iic_0_0_SRL_FIFO;
architecture STRUCTURE of system_axi_iic_0_0_SRL_FIFO is
signal \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1__1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal \RD_FIFO_CNTRL.ro_prev_i_i_2_n_0\ : STD_LOGIC;
signal \RD_FIFO_CNTRL.ro_prev_i_i_3_n_0\ : STD_LOGIC;
signal \^rc_data_exists\ : STD_LOGIC;
signal \^rc_addr\ : STD_LOGIC_VECTOR ( 0 to 3 );
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute box_type of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute box_type of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute box_type of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute box_type of Data_Exists_DFF : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Data_Exists_DFF_i_2__1\ : label is "soft_lutpair23";
attribute box_type of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[0].SRL16E_I ";
attribute box_type of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[1].SRL16E_I ";
attribute box_type of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[2].SRL16E_I ";
attribute box_type of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[3].SRL16E_I ";
attribute box_type of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[4].SRL16E_I ";
attribute box_type of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[5].SRL16E_I ";
attribute box_type of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[6].SRL16E_I ";
attribute box_type of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\X_IIC/READ_FIFO_I/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \RD_FIFO_CNTRL.ro_prev_i_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \sr_i[1]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \sr_i[2]_i_1\ : label is "soft_lutpair23";
begin
Rc_Data_Exists <= \^rc_data_exists\;
Rc_addr(0 to 3) <= \^rc_addr\(0 to 3);
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^rc_data_exists\,
D => sum_A_3,
Q => \^rc_addr\(0),
R => Bus2IIC_Reset
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \^rc_addr\(2),
DI(1) => \^rc_addr\(1),
DI(0) => \^rc_addr\(0),
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1__1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A208"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\,
I1 => Rc_fifo_rd,
I2 => Rc_fifo_rd_d,
I3 => \^rc_addr\(0),
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFF00000000"
)
port map (
I0 => \^rc_addr\(1),
I1 => \^rc_addr\(2),
I2 => \^rc_addr\(3),
I3 => \^rc_addr\(0),
I4 => \RD_FIFO_CNTRL.Rc_fifo_rd_reg\,
I5 => \RD_FIFO_CNTRL.Rc_fifo_wr_reg\,
O => CI
);
\Addr_Counters[0].MUXCY_L_I_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF4"
)
port map (
I0 => Rc_fifo_wr_d,
I1 => Rc_fifo_wr,
I2 => \^rc_addr\(0),
I3 => \^rc_addr\(3),
I4 => \^rc_addr\(2),
I5 => \^rc_addr\(1),
O => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^rc_data_exists\,
D => sum_A_2,
Q => \^rc_addr\(1),
R => Bus2IIC_Reset
);
\Addr_Counters[1].MUXCY_L_I_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A208"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\,
I1 => Rc_fifo_rd,
I2 => Rc_fifo_rd_d,
I3 => \^rc_addr\(1),
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^rc_data_exists\,
D => sum_A_1,
Q => \^rc_addr\(2),
R => Bus2IIC_Reset
);
\Addr_Counters[2].MUXCY_L_I_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A208"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\,
I1 => Rc_fifo_rd,
I2 => Rc_fifo_rd_d,
I3 => \^rc_addr\(2),
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^rc_data_exists\,
D => sum_A_0,
Q => \^rc_addr\(3),
R => Bus2IIC_Reset
);
\Addr_Counters[3].XORCY_I_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A208"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3__1_n_0\,
I1 => Rc_fifo_rd,
I2 => Rc_fifo_rd_d,
I3 => \^rc_addr\(3),
O => \Addr_Counters[3].XORCY_I_i_1__1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => \^rc_data_exists\,
R => Bus2IIC_Reset
);
\Data_Exists_DFF_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^rc_addr\(1),
I1 => \^rc_addr\(2),
I2 => \^rc_addr\(3),
I3 => \^rc_addr\(0),
O => Data_Exists_DFF_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^rc_addr\(0),
A1 => \^rc_addr\(1),
A2 => \^rc_addr\(2),
A3 => \^rc_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => \data_i2c_i_reg[7]\(7),
Q => Rc_fifo_data(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^rc_addr\(0),
A1 => \^rc_addr\(1),
A2 => \^rc_addr\(2),
A3 => \^rc_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => \data_i2c_i_reg[7]\(6),
Q => Rc_fifo_data(1)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^rc_addr\(0),
A1 => \^rc_addr\(1),
A2 => \^rc_addr\(2),
A3 => \^rc_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => \data_i2c_i_reg[7]\(5),
Q => Rc_fifo_data(2)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^rc_addr\(0),
A1 => \^rc_addr\(1),
A2 => \^rc_addr\(2),
A3 => \^rc_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => \data_i2c_i_reg[7]\(4),
Q => Rc_fifo_data(3)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^rc_addr\(0),
A1 => \^rc_addr\(1),
A2 => \^rc_addr\(2),
A3 => \^rc_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => \data_i2c_i_reg[7]\(3),
Q => Rc_fifo_data(4)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^rc_addr\(0),
A1 => \^rc_addr\(1),
A2 => \^rc_addr\(2),
A3 => \^rc_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => \data_i2c_i_reg[7]\(2),
Q => Rc_fifo_data(5)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^rc_addr\(0),
A1 => \^rc_addr\(1),
A2 => \^rc_addr\(2),
A3 => \^rc_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => \data_i2c_i_reg[7]\(1),
Q => Rc_fifo_data(6)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^rc_addr\(0),
A1 => \^rc_addr\(1),
A2 => \^rc_addr\(2),
A3 => \^rc_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => \data_i2c_i_reg[7]\(0),
Q => Rc_fifo_data(7)
);
\RD_FIFO_CNTRL.ro_prev_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000004"
)
port map (
I0 => \RD_FIFO_CNTRL.ro_prev_i_i_2_n_0\,
I1 => \RD_FIFO_CNTRL.ro_prev_i_i_3_n_0\,
I2 => Bus2IIC_Reset,
I3 => \^rc_addr\(2),
I4 => Q(2),
I5 => Msms_set,
O => p_6_out
);
\RD_FIFO_CNTRL.ro_prev_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6F"
)
port map (
I0 => \^rc_addr\(0),
I1 => Q(0),
I2 => \^rc_data_exists\,
O => \RD_FIFO_CNTRL.ro_prev_i_i_2_n_0\
);
\RD_FIFO_CNTRL.ro_prev_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^rc_addr\(3),
I1 => Q(3),
I2 => \^rc_addr\(1),
I3 => Q(1),
O => \RD_FIFO_CNTRL.ro_prev_i_i_3_n_0\
);
\sr_i[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^rc_data_exists\,
O => D(1)
);
\sr_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^rc_addr\(1),
I1 => \^rc_addr\(2),
I2 => \^rc_addr\(3),
I3 => \^rc_addr\(0),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_SRL_FIFO_0 is
port (
Tx_data_exists : out STD_LOGIC;
Tx_addr : out STD_LOGIC_VECTOR ( 0 to 3 );
Tx_fifo_data : out STD_LOGIC_VECTOR ( 0 to 7 );
\sr_i_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : out STD_LOGIC;
\cr_i_reg[5]\ : out STD_LOGIC;
\sr_i_reg[0]\ : out STD_LOGIC;
\FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7]\ : out STD_LOGIC;
Data_Exists_DFF_0 : out STD_LOGIC;
\data_int_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Tx_fifo_rst : in STD_LOGIC;
D : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\FIFO_GEN_DTR.Tx_fifo_rd_reg\ : in STD_LOGIC;
\FIFO_GEN_DTR.Tx_fifo_wr_reg\ : in STD_LOGIC;
dynamic_MSMS : in STD_LOGIC_VECTOR ( 0 to 0 );
Tx_fifo_rd_d : in STD_LOGIC;
Tx_fifo_rd : in STD_LOGIC;
rdCntrFrmTxFifo : in STD_LOGIC;
Tx_fifo_wr_d : in STD_LOGIC;
Tx_fifo_wr : in STD_LOGIC;
shift_reg_ld : in STD_LOGIC;
scndry_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_SRL_FIFO_0 : entity is "SRL_FIFO";
end system_axi_iic_0_0_SRL_FIFO_0;
architecture STRUCTURE of system_axi_iic_0_0_SRL_FIFO_0 is
signal \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1__0_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal \^tx_addr\ : STD_LOGIC_VECTOR ( 0 to 3 );
signal \^tx_data_exists\ : STD_LOGIC;
signal \^tx_fifo_data\ : STD_LOGIC_VECTOR ( 0 to 7 );
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute box_type of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute box_type of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute box_type of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute box_type of Data_Exists_DFF : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Data_Exists_DFF_i_3 : label is "soft_lutpair30";
attribute box_type of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[0].SRL16E_I ";
attribute box_type of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[1].SRL16E_I ";
attribute box_type of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[2].SRL16E_I ";
attribute box_type of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[3].SRL16E_I ";
attribute box_type of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[4].SRL16E_I ";
attribute box_type of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[5].SRL16E_I ";
attribute box_type of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[6].SRL16E_I ";
attribute box_type of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_I/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of callingReadAccess_i_1 : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \cr_i[5]_i_2\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \sr_i[3]_i_1\ : label is "soft_lutpair30";
begin
Tx_addr(0 to 3) <= \^tx_addr\(0 to 3);
Tx_data_exists <= \^tx_data_exists\;
Tx_fifo_data(0 to 7) <= \^tx_fifo_data\(0 to 7);
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^tx_data_exists\,
D => sum_A_3,
Q => \^tx_addr\(0),
R => Tx_fifo_rst
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \^tx_addr\(2),
DI(1) => \^tx_addr\(1),
DI(0) => \^tx_addr\(0),
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1__0_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A2AA08"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\,
I1 => Tx_fifo_rd,
I2 => Tx_fifo_rd_d,
I3 => rdCntrFrmTxFifo,
I4 => \^tx_addr\(0),
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF00000000"
)
port map (
I0 => \FIFO_GEN_DTR.Tx_fifo_rd_reg\,
I1 => \^tx_addr\(1),
I2 => \^tx_addr\(3),
I3 => \^tx_addr\(0),
I4 => \^tx_addr\(2),
I5 => \FIFO_GEN_DTR.Tx_fifo_wr_reg\,
O => CI
);
\Addr_Counters[0].MUXCY_L_I_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF4"
)
port map (
I0 => Tx_fifo_wr_d,
I1 => Tx_fifo_wr,
I2 => \^tx_addr\(2),
I3 => \^tx_addr\(0),
I4 => \^tx_addr\(3),
I5 => \^tx_addr\(1),
O => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^tx_data_exists\,
D => sum_A_2,
Q => \^tx_addr\(1),
R => Tx_fifo_rst
);
\Addr_Counters[1].MUXCY_L_I_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A2AA08"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\,
I1 => Tx_fifo_rd,
I2 => Tx_fifo_rd_d,
I3 => rdCntrFrmTxFifo,
I4 => \^tx_addr\(1),
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^tx_data_exists\,
D => sum_A_1,
Q => \^tx_addr\(2),
R => Tx_fifo_rst
);
\Addr_Counters[2].MUXCY_L_I_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A2AA08"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\,
I1 => Tx_fifo_rd,
I2 => Tx_fifo_rd_d,
I3 => rdCntrFrmTxFifo,
I4 => \^tx_addr\(2),
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^tx_data_exists\,
D => sum_A_0,
Q => \^tx_addr\(3),
R => Tx_fifo_rst
);
\Addr_Counters[3].XORCY_I_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A2AA08"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3__0_n_0\,
I1 => Tx_fifo_rd,
I2 => Tx_fifo_rd_d,
I3 => rdCntrFrmTxFifo,
I4 => \^tx_addr\(3),
O => \Addr_Counters[3].XORCY_I_i_1__0_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D,
Q => \^tx_data_exists\,
R => Tx_fifo_rst
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^tx_addr\(1),
I1 => \^tx_addr\(3),
I2 => \^tx_addr\(0),
I3 => \^tx_addr\(2),
O => Data_Exists_DFF_0
);
\FIFO_GEN_DTR.IIC2Bus_IntrEvent[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^tx_addr\(3),
O => \FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7]\
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^tx_addr\(0),
A1 => \^tx_addr\(1),
A2 => \^tx_addr\(2),
A3 => \^tx_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => s_axi_wdata(7),
Q => \^tx_fifo_data\(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^tx_addr\(0),
A1 => \^tx_addr\(1),
A2 => \^tx_addr\(2),
A3 => \^tx_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => s_axi_wdata(6),
Q => \^tx_fifo_data\(1)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^tx_addr\(0),
A1 => \^tx_addr\(1),
A2 => \^tx_addr\(2),
A3 => \^tx_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => s_axi_wdata(5),
Q => \^tx_fifo_data\(2)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^tx_addr\(0),
A1 => \^tx_addr\(1),
A2 => \^tx_addr\(2),
A3 => \^tx_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => s_axi_wdata(4),
Q => \^tx_fifo_data\(3)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^tx_addr\(0),
A1 => \^tx_addr\(1),
A2 => \^tx_addr\(2),
A3 => \^tx_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => s_axi_wdata(3),
Q => \^tx_fifo_data\(4)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^tx_addr\(0),
A1 => \^tx_addr\(1),
A2 => \^tx_addr\(2),
A3 => \^tx_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => s_axi_wdata(2),
Q => \^tx_fifo_data\(5)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^tx_addr\(0),
A1 => \^tx_addr\(1),
A2 => \^tx_addr\(2),
A3 => \^tx_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => s_axi_wdata(1),
Q => \^tx_fifo_data\(6)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \^tx_addr\(0),
A1 => \^tx_addr\(1),
A2 => \^tx_addr\(2),
A3 => \^tx_addr\(3),
CE => CI,
CLK => s_axi_aclk,
D => s_axi_wdata(0),
Q => \^tx_fifo_data\(7)
);
callingReadAccess_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^tx_data_exists\,
I1 => dynamic_MSMS(0),
I2 => Tx_fifo_rd_d,
I3 => Tx_fifo_rd,
O => p_3_in
);
\cr_i[5]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^tx_data_exists\,
I1 => dynamic_MSMS(0),
O => \cr_i_reg[5]\
);
\data_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_fifo_data\(7),
I1 => shift_reg_ld,
I2 => scndry_out,
O => \data_int_reg[0]\(0)
);
\sr_i[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^tx_data_exists\,
O => \sr_i_reg[0]\
);
\sr_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^tx_addr\(1),
I1 => \^tx_addr\(3),
I2 => \^tx_addr\(0),
I3 => \^tx_addr\(2),
O => \sr_i_reg[3]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_iic_0_0_SRL_FIFO__parameterized0\ is
port (
\Addr_Counters[0].FDRE_I_0\ : out STD_LOGIC;
dynamic_MSMS : out STD_LOGIC_VECTOR ( 0 to 1 );
Data_Exists_DFF_0 : out STD_LOGIC;
Tx_fifo_rst : in STD_LOGIC;
D : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
ctrlFifoDin : in STD_LOGIC_VECTOR ( 0 to 1 );
Tx_fifo_rd : in STD_LOGIC;
Tx_fifo_rd_d : in STD_LOGIC;
rdCntrFrmTxFifo : in STD_LOGIC;
Tx_fifo_wr_d_reg : in STD_LOGIC;
\FIFO_GEN_DTR.Tx_fifo_rd_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_iic_0_0_SRL_FIFO__parameterized0\ : entity is "SRL_FIFO";
end \system_axi_iic_0_0_SRL_FIFO__parameterized0\;
architecture STRUCTURE of \system_axi_iic_0_0_SRL_FIFO__parameterized0\ is
signal \^addr_counters[0].fdre_i_0\ : STD_LOGIC;
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[0].MUXCY_L_I_i_3_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute box_type of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Addr_Counters[0].MUXCY_L_I_i_3\ : label is "soft_lutpair28";
attribute box_type of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute box_type of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute box_type of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute box_type of Data_Exists_DFF : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \Data_Exists_DFF_i_3__0\ : label is "soft_lutpair28";
attribute box_type of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM[0].SRL16E_I ";
attribute box_type of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\X_IIC/WRITE_FIFO_CTRL_I/FIFO_RAM[1].SRL16E_I ";
begin
\Addr_Counters[0].FDRE_I_0\ <= \^addr_counters[0].fdre_i_0\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^addr_counters[0].fdre_i_0\,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => Tx_fifo_rst
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A2AA08"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\,
I1 => Tx_fifo_rd,
I2 => Tx_fifo_rd_d,
I3 => rdCntrFrmTxFifo,
I4 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAAAAAAAAAA"
)
port map (
I0 => Tx_fifo_wr_d_reg,
I1 => \Addr_Counters[2].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[0].FDRE_I_n_0\,
I5 => \FIFO_GEN_DTR.Tx_fifo_rd_reg\,
O => CI
);
\Addr_Counters[0].MUXCY_L_I_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => Tx_fifo_wr_d_reg,
I1 => \Addr_Counters[2].FDRE_I_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[3].FDRE_I_n_0\,
I4 => \Addr_Counters[1].FDRE_I_n_0\,
O => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^addr_counters[0].fdre_i_0\,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => Tx_fifo_rst
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A2AA08"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\,
I1 => Tx_fifo_rd,
I2 => Tx_fifo_rd_d,
I3 => rdCntrFrmTxFifo,
I4 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^addr_counters[0].fdre_i_0\,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => Tx_fifo_rst
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A2AA08"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\,
I1 => Tx_fifo_rd,
I2 => Tx_fifo_rd_d,
I3 => rdCntrFrmTxFifo,
I4 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \^addr_counters[0].fdre_i_0\,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => Tx_fifo_rst
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A2AA08"
)
port map (
I0 => \Addr_Counters[0].MUXCY_L_I_i_3_n_0\,
I1 => Tx_fifo_rd,
I2 => Tx_fifo_rd_d,
I3 => rdCntrFrmTxFifo,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D,
Q => \^addr_counters[0].fdre_i_0\,
R => Tx_fifo_rst
);
\Data_Exists_DFF_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => ctrlFifoDin(0),
Q => dynamic_MSMS(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => ctrlFifoDin(1),
Q => dynamic_MSMS(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_address_decoder is
port (
\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0\ : out STD_LOGIC;
AXI_IP2Bus_WrAck2_reg : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0\ : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
AXI_IP2Bus_Error : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 10 downto 0 );
Bus2IIC_RdCE : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus2IIC_WrCE : out STD_LOGIC_VECTOR ( 11 downto 0 );
AXI_IP2Bus_RdAck20 : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
\GPO_GEN.gpo_i_reg[31]\ : out STD_LOGIC;
\s_axi_bresp_i_reg[1]\ : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
is_read : in STD_LOGIC;
AXI_IP2Bus_RdAck1 : in STD_LOGIC;
AXI_IP2Bus_RdAck2 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
AXI_IP2Bus_WrAck1 : in STD_LOGIC;
AXI_IP2Bus_WrAck2 : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 8 downto 0 );
irpt_wrack_d1 : in STD_LOGIC;
IIC2Bus_IntrEvent : in STD_LOGIC_VECTOR ( 0 to 7 );
p_1_in : in STD_LOGIC;
p_1_in2_in : in STD_LOGIC;
p_1_in5_in : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
\ip_irpt_enable_reg_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC;
\timing_param_thdsta_i_reg[0]\ : in STD_LOGIC;
\timing_param_thigh_i_reg[0]\ : in STD_LOGIC;
\Addr_Counters[1].FDRE_I\ : in STD_LOGIC;
\timing_param_thigh_i_reg[1]\ : in STD_LOGIC;
\adr_i_reg[6]\ : in STD_LOGIC;
\adr_i_reg[5]\ : in STD_LOGIC;
\Addr_Counters[2].FDRE_I\ : in STD_LOGIC;
\timing_param_thigh_i_reg[2]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[3]\ : in STD_LOGIC;
\adr_i_reg[4]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]\ : in STD_LOGIC;
\adr_i_reg[3]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_1\ : in STD_LOGIC;
\adr_i_reg[2]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_2\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_3\ : in STD_LOGIC;
\adr_i_reg[1]\ : in STD_LOGIC;
\timing_param_tsudat_i_reg[6]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_4\ : in STD_LOGIC;
\adr_i_reg[0]\ : in STD_LOGIC;
\timing_param_tsudat_i_reg[7]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]_1\ : in STD_LOGIC;
\cr_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cr_txModeSelect_set : in STD_LOGIC;
cr_txModeSelect_clr : in STD_LOGIC;
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
gpo : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_address_decoder : entity is "address_decoder";
end system_axi_iic_0_0_address_decoder;
architecture STRUCTURE of system_axi_iic_0_0_address_decoder is
signal \^axi_ip2bus_error\ : STD_LOGIC;
signal Bus_RNW_reg : STD_LOGIC;
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[21].ce_out_i_reg[21]_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[23].ce_out_i_reg[23]_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[26].ce_out_i_reg[26]_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].cs_out_i_reg\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS\ : STD_LOGIC;
signal \MEM_DECODE_GEN[1].cs_out_i_reg\ : STD_LOGIC;
signal \MEM_DECODE_GEN[2].cs_out_i_reg\ : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_16_out : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_17_out : STD_LOGIC;
signal p_18_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_27_in : STD_LOGIC;
signal p_28_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal pselect_hit_i_0 : STD_LOGIC;
signal pselect_hit_i_2 : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_6_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_7_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_8_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_9_n_0\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal \^sw_rst_cond\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of AXI_IP2Bus_RdAck2_i_1 : label is "soft_lutpair37";
attribute SOFT_HLUTNM of AXI_IP2Bus_WrAck2_i_1 : label is "soft_lutpair37";
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_2\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GPO_GEN.gpo_i[31]_i_2\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \MEM_DECODE_GEN[0].cs_out_i[0]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \MEM_DECODE_GEN[2].cs_out_i[2]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \RD_FIFO_CNTRL.Rc_fifo_rd_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \RD_FIFO_CNTRL.rc_fifo_pirq_i[4]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \adr_i[0]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \cr_i[0]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \ip_irpt_enable_reg[7]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of ipif_glbl_irpt_enable_reg_i_1 : label is "soft_lutpair36";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \s_axi_rdata_i[31]_i_2\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \s_axi_rdata_i[9]_i_8\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \s_axi_rdata_i[9]_i_9\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \timing_param_tbuf_i[9]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \timing_param_thddat_i[9]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \timing_param_thdsta_i[9]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \timing_param_thigh_i[9]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \timing_param_tlow_i[9]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \timing_param_tsudat_i[9]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \timing_param_tsusta_i[9]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \timing_param_tsusto_i[9]_i_1\ : label is "soft_lutpair33";
begin
AXI_IP2Bus_Error <= \^axi_ip2bus_error\;
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0\ <= \^gen_bkend_ce_registers[21].ce_out_i_reg[21]_0\;
\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0\ <= \^gen_bkend_ce_registers[23].ce_out_i_reg[23]_0\;
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0\ <= \^gen_bkend_ce_registers[26].ce_out_i_reg[26]_0\;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_wready <= \^s_axi_wready\;
sw_rst_cond <= \^sw_rst_cond\;
AXI_IP2Bus_RdAck2_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \MEM_DECODE_GEN[2].cs_out_i_reg\,
I1 => \MEM_DECODE_GEN[0].cs_out_i_reg\,
I2 => \MEM_DECODE_GEN[1].cs_out_i_reg\,
I3 => bus2ip_rnw_i_reg,
O => AXI_IP2Bus_RdAck20
);
AXI_IP2Bus_WrAck2_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \MEM_DECODE_GEN[2].cs_out_i_reg\,
I1 => \MEM_DECODE_GEN[0].cs_out_i_reg\,
I2 => \MEM_DECODE_GEN[1].cs_out_i_reg\,
I3 => bus2ip_rnw_i_reg,
O => AXI_IP2Bus_WrAck2_reg
);
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => Bus_RNW_reg,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => Bus_RNW_reg,
R => '0'
);
\FIFO_GEN_DTR.Tx_fifo_wr_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_16_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(10)
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => Q,
I1 => \bus2ip_addr_i_reg[8]\(7),
I2 => \bus2ip_addr_i_reg[8]\(8),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2_n_0\,
I5 => \^gen_bkend_ce_registers[23].ce_out_i_reg[23]_0\,
O => \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(4),
I1 => \bus2ip_addr_i_reg[8]\(5),
O => \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1_n_0\,
Q => p_25_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => Q,
I2 => \bus2ip_addr_i_reg[8]\(8),
I3 => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0\,
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_18_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => Q,
I2 => \bus2ip_addr_i_reg[8]\(8),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0\,
O => p_16_out
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(5),
I1 => \bus2ip_addr_i_reg[8]\(4),
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_16_out,
Q => p_17_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(5),
I1 => \bus2ip_addr_i_reg[8]\(4),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => pselect_hit_i_0,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\,
Q => p_16_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(5),
I1 => \^gen_bkend_ce_registers[26].ce_out_i_reg[26]_0\,
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(3),
I4 => Q,
I5 => \bus2ip_addr_i_reg[8]\(8),
O => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\,
Q => p_15_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => \^gen_bkend_ce_registers[21].ce_out_i_reg[21]_0\,
I1 => \bus2ip_addr_i_reg[8]\(8),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(6),
O => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\,
Q => p_14_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(8),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => \bus2ip_addr_i_reg[8]\(5),
O => \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1_n_0\,
Q => p_13_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => \^gen_bkend_ce_registers[23].ce_out_i_reg[23]_0\,
I1 => \bus2ip_addr_i_reg[8]\(8),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => \bus2ip_addr_i_reg[8]\(5),
O => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
O => \^gen_bkend_ce_registers[23].ce_out_i_reg[23]_0\
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1_n_0\,
Q => p_12_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => pselect_hit_i_0,
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(6),
O => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\,
Q => p_11_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => \^gen_bkend_ce_registers[21].ce_out_i_reg[21]_0\,
I1 => Q,
I2 => \bus2ip_addr_i_reg[8]\(8),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(4),
O => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\,
Q => p_10_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => Q,
I2 => \bus2ip_addr_i_reg[8]\(8),
I3 => \^gen_bkend_ce_registers[26].ce_out_i_reg[26]_0\,
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(6),
I1 => \bus2ip_addr_i_reg[8]\(4),
O => \^gen_bkend_ce_registers[26].ce_out_i_reg[26]_0\
);
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1_n_0\,
Q => p_9_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000400000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => pselect_hit_i_0,
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(4),
O => \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\,
Q => p_8_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => pselect_hit_i_0,
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(4),
O => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\,
Q => p_7_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => Q,
I2 => \bus2ip_addr_i_reg[8]\(8),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(2),
I5 => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(5),
I1 => \bus2ip_addr_i_reg[8]\(4),
O => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\,
Q => p_6_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(8),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(6),
O => \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => \bus2ip_addr_i_reg[8]\(3),
O => \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1_n_0\,
Q => p_5_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(8),
I3 => Q,
I4 => \bus2ip_addr_i_reg[8]\(4),
I5 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(6),
I1 => \bus2ip_addr_i_reg[8]\(5),
O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1_n_0\,
Q => p_4_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => pselect_hit_i_0,
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[32].ce_out_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[32].ce_out_i[32]_i_1_n_0\,
Q => p_3_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => Q,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(5),
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \^gen_bkend_ce_registers[21].ce_out_i_reg[21]_0\,
I5 => \bus2ip_addr_i_reg[8]\(8),
O => \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => \bus2ip_addr_i_reg[8]\(3),
O => \^gen_bkend_ce_registers[21].ce_out_i_reg[21]_0\
);
\GEN_BKEND_CE_REGISTERS[33].ce_out_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[33].ce_out_i[33]_i_1_n_0\,
Q => p_2_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF4F44FFFF"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => is_read,
I2 => AXI_IP2Bus_RdAck1,
I3 => AXI_IP2Bus_RdAck2,
I4 => s_axi_aresetn,
I5 => \^s_axi_wready\,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[34].ce_out_i[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => pselect_hit_i_0,
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(6),
O => p_17_out
);
\GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_17_out,
Q => \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => pselect_hit_i_2,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(5),
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_8_out,
Q => p_28_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => Q,
I1 => \bus2ip_addr_i_reg[8]\(7),
I2 => \bus2ip_addr_i_reg[8]\(8),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_2_n_0\,
I5 => \^gen_bkend_ce_registers[21].ce_out_i_reg[21]_0\,
O => \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1_n_0\,
Q => p_27_in,
R => cs_ce_clr
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFF0020"
)
port map (
I0 => s_axi_wdata(0),
I1 => Bus_RNW_reg,
I2 => p_27_in,
I3 => irpt_wrack_d1,
I4 => IIC2Bus_IntrEvent(0),
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFF0020"
)
port map (
I0 => s_axi_wdata(1),
I1 => Bus_RNW_reg,
I2 => p_27_in,
I3 => irpt_wrack_d1,
I4 => IIC2Bus_IntrEvent(1),
I5 => p_1_in17_in,
O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFF0020"
)
port map (
I0 => s_axi_wdata(2),
I1 => Bus_RNW_reg,
I2 => p_27_in,
I3 => irpt_wrack_d1,
I4 => IIC2Bus_IntrEvent(2),
I5 => p_1_in14_in,
O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFF0020"
)
port map (
I0 => s_axi_wdata(3),
I1 => Bus_RNW_reg,
I2 => p_27_in,
I3 => irpt_wrack_d1,
I4 => IIC2Bus_IntrEvent(3),
I5 => p_1_in11_in,
O => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFF0020"
)
port map (
I0 => s_axi_wdata(4),
I1 => Bus_RNW_reg,
I2 => p_27_in,
I3 => irpt_wrack_d1,
I4 => IIC2Bus_IntrEvent(4),
I5 => p_1_in8_in,
O => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFF0020"
)
port map (
I0 => s_axi_wdata(5),
I1 => Bus_RNW_reg,
I2 => p_27_in,
I3 => irpt_wrack_d1,
I4 => IIC2Bus_IntrEvent(5),
I5 => p_1_in5_in,
O => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFF0020"
)
port map (
I0 => s_axi_wdata(6),
I1 => Bus_RNW_reg,
I2 => p_27_in,
I3 => irpt_wrack_d1,
I4 => IIC2Bus_IntrEvent(6),
I5 => p_1_in2_in,
O => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFF0020"
)
port map (
I0 => s_axi_wdata(7),
I1 => Bus_RNW_reg,
I2 => p_27_in,
I3 => irpt_wrack_d1,
I4 => IIC2Bus_IntrEvent(7),
I5 => p_1_in,
O => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\
);
\GPO_GEN.gpo_i[31]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_9_in,
I2 => Bus_RNW_reg,
I3 => gpo(0),
O => \GPO_GEN.gpo_i_reg[31]\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(7),
I1 => \bus2ip_addr_i_reg[8]\(8),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(6),
O => pselect_hit_i_2
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => pselect_hit_i_2,
Q => \MEM_DECODE_GEN[0].cs_out_i_reg\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[1].cs_out_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => Q,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_2_n_0\,
I3 => \^gen_bkend_ce_registers[21].ce_out_i_reg[21]_0\,
I4 => \bus2ip_addr_i_reg[8]\(8),
I5 => \bus2ip_addr_i_reg[8]\(7),
O => \MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS\
);
\MEM_DECODE_GEN[1].cs_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \MEM_DECODE_GEN[1].GEN_FOR_MULTI_CS.MEM_SELECT_I/CS\,
Q => \MEM_DECODE_GEN[1].cs_out_i_reg\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[2].cs_out_i[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Q,
I1 => \bus2ip_addr_i_reg[8]\(8),
O => pselect_hit_i_0
);
\MEM_DECODE_GEN[2].cs_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => pselect_hit_i_0,
Q => \MEM_DECODE_GEN[2].cs_out_i_reg\,
R => cs_ce_clr
);
\RD_FIFO_CNTRL.Rc_fifo_rd_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Bus_RNW_reg,
I1 => p_15_in,
O => Bus2IIC_RdCE(0)
);
\RD_FIFO_CNTRL.rc_fifo_pirq_i[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_10_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(8)
);
\adr_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_14_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(9)
);
\cr_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_18_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(11)
);
\cr_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FBFBFB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => p_18_in,
I2 => Bus_RNW_reg,
I3 => \cr_i_reg[4]_0\(0),
I4 => cr_txModeSelect_set,
I5 => cr_txModeSelect_clr,
O => \cr_i_reg[4]\(0)
);
\ip_irpt_enable_reg[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_25_in,
I1 => Bus_RNW_reg,
O => E(0)
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(8),
I1 => p_28_in,
I2 => Bus_RNW_reg,
I3 => ipif_glbl_irpt_enable_reg,
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0F0E"
)
port map (
I0 => p_25_in,
I1 => p_28_in,
I2 => Bus_RNW_reg,
I3 => p_27_in,
O => irpt_wrack
);
reset_trig_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^sw_rst_cond\,
I1 => sw_rst_cond_d1,
O => reset_trig0
);
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^axi_ip2bus_error\,
I1 => \state_reg[1]\(1),
I2 => \state_reg[1]\(0),
I3 => s_axi_bresp(0),
O => \s_axi_bresp_i_reg[1]\
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAAAEAAAAA"
)
port map (
I0 => \s_axi_rdata_i[0]_i_2_n_0\,
I1 => p_25_in,
I2 => \ip_irpt_enable_reg_reg[7]\(0),
I3 => p_27_in,
I4 => Bus_RNW_reg,
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
O => D(0)
);
\s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000000DF"
)
port map (
I0 => \bus2ip_addr_i_reg[6]\,
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \s_axi_rdata_i[9]_i_3_n_0\,
I4 => \timing_param_thdsta_i_reg[0]\,
I5 => \timing_param_thigh_i_reg[0]\,
O => \s_axi_rdata_i[0]_i_2_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAAAEAAAAA"
)
port map (
I0 => \s_axi_rdata_i[1]_i_2_n_0\,
I1 => p_25_in,
I2 => \ip_irpt_enable_reg_reg[7]\(1),
I3 => p_27_in,
I4 => Bus_RNW_reg,
I5 => p_1_in17_in,
O => D(1)
);
\s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000C8CCC8C0"
)
port map (
I0 => \Addr_Counters[1].FDRE_I\,
I1 => \timing_param_thigh_i_reg[1]\,
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => \adr_i_reg[6]\,
I5 => \s_axi_rdata_i[9]_i_3_n_0\,
O => \s_axi_rdata_i[1]_i_2_n_0\
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAAAEAAAAA"
)
port map (
I0 => \s_axi_rdata_i[2]_i_2_n_0\,
I1 => p_25_in,
I2 => \ip_irpt_enable_reg_reg[7]\(2),
I3 => p_27_in,
I4 => Bus_RNW_reg,
I5 => p_1_in14_in,
O => D(2)
);
\s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FEBA"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \adr_i_reg[5]\,
I3 => \Addr_Counters[2].FDRE_I\,
I4 => \timing_param_thigh_i_reg[2]\,
I5 => \s_axi_rdata_i[9]_i_3_n_0\,
O => \s_axi_rdata_i[2]_i_2_n_0\
);
\s_axi_rdata_i[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => p_28_in,
I1 => ipif_glbl_irpt_enable_reg,
I2 => Bus_RNW_reg,
I3 => p_27_in,
I4 => p_25_in,
O => D(10)
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAAAEAAAAA"
)
port map (
I0 => \s_axi_rdata_i[3]_i_2_n_0\,
I1 => p_25_in,
I2 => \ip_irpt_enable_reg_reg[7]\(3),
I3 => p_27_in,
I4 => Bus_RNW_reg,
I5 => p_1_in11_in,
O => D(3)
);
\s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055455540"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \timing_param_tbuf_i_reg[3]\,
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => \adr_i_reg[4]\,
I5 => \s_axi_rdata_i[9]_i_3_n_0\,
O => \s_axi_rdata_i[3]_i_2_n_0\
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAAAEAAAAA"
)
port map (
I0 => \s_axi_rdata_i[4]_i_2_n_0\,
I1 => p_25_in,
I2 => \ip_irpt_enable_reg_reg[7]\(4),
I3 => p_27_in,
I4 => Bus_RNW_reg,
I5 => p_1_in8_in,
O => D(4)
);
\s_axi_rdata_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000AAFC"
)
port map (
I0 => \bus2ip_addr_i_reg[5]\,
I1 => \adr_i_reg[3]\,
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(3),
I4 => \bus2ip_addr_i_reg[5]_0\,
I5 => \s_axi_rdata_i[9]_i_3_n_0\,
O => \s_axi_rdata_i[4]_i_2_n_0\
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAAAEAAAAA"
)
port map (
I0 => \s_axi_rdata_i[5]_i_2_n_0\,
I1 => p_25_in,
I2 => \ip_irpt_enable_reg_reg[7]\(5),
I3 => p_27_in,
I4 => Bus_RNW_reg,
I5 => p_1_in5_in,
O => D(5)
);
\s_axi_rdata_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000AAFC"
)
port map (
I0 => \bus2ip_addr_i_reg[5]_1\,
I1 => \adr_i_reg[2]\,
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(3),
I4 => \bus2ip_addr_i_reg[5]_2\,
I5 => \s_axi_rdata_i[9]_i_3_n_0\,
O => \s_axi_rdata_i[5]_i_2_n_0\
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAAAEAAAAA"
)
port map (
I0 => \s_axi_rdata_i[6]_i_2_n_0\,
I1 => p_25_in,
I2 => \ip_irpt_enable_reg_reg[7]\(6),
I3 => p_27_in,
I4 => Bus_RNW_reg,
I5 => p_1_in2_in,
O => D(6)
);
\s_axi_rdata_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAF0CC"
)
port map (
I0 => \bus2ip_addr_i_reg[5]_3\,
I1 => \adr_i_reg[1]\,
I2 => \timing_param_tsudat_i_reg[6]\,
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \s_axi_rdata_i[9]_i_3_n_0\,
O => \s_axi_rdata_i[6]_i_2_n_0\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAAAAAAAEAAAAA"
)
port map (
I0 => \s_axi_rdata_i[7]_i_2_n_0\,
I1 => p_25_in,
I2 => \ip_irpt_enable_reg_reg[7]\(7),
I3 => p_27_in,
I4 => Bus_RNW_reg,
I5 => p_1_in,
O => D(7)
);
\s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAF0CC"
)
port map (
I0 => \bus2ip_addr_i_reg[5]_4\,
I1 => \adr_i_reg[0]\,
I2 => \timing_param_tsudat_i_reg[7]\,
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \s_axi_rdata_i[9]_i_3_n_0\,
O => \s_axi_rdata_i[7]_i_2_n_0\
);
\s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000222200000"
)
port map (
I0 => \bus2ip_addr_i_reg[2]_0\,
I1 => \s_axi_rdata_i[9]_i_3_n_0\,
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(6),
O => D(8)
);
\s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000222200000"
)
port map (
I0 => \bus2ip_addr_i_reg[2]_1\,
I1 => \s_axi_rdata_i[9]_i_3_n_0\,
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(6),
O => D(9)
);
\s_axi_rdata_i[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF4FFFFFFFF"
)
port map (
I0 => \s_axi_rdata_i[9]_i_6_n_0\,
I1 => \s_axi_rdata_i[9]_i_7_n_0\,
I2 => \bus2ip_addr_i_reg[8]\(7),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => Bus_RNW_reg,
O => \s_axi_rdata_i[9]_i_3_n_0\
);
\s_axi_rdata_i[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_9_in,
I1 => p_12_in,
I2 => p_13_in,
I3 => p_14_in,
I4 => \s_axi_rdata_i[9]_i_8_n_0\,
I5 => \s_axi_rdata_i[9]_i_9_n_0\,
O => \s_axi_rdata_i[9]_i_6_n_0\
);
\s_axi_rdata_i[9]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => p_17_in,
I1 => p_4_in,
I2 => p_10_in,
I3 => p_11_in,
I4 => p_6_in,
I5 => p_16_in,
O => \s_axi_rdata_i[9]_i_7_n_0\
);
\s_axi_rdata_i[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_7_in,
I1 => p_5_in,
I2 => p_15_in,
I3 => p_3_in,
O => \s_axi_rdata_i[9]_i_8_n_0\
);
\s_axi_rdata_i[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_8_in,
I1 => p_2_in,
I2 => p_18_in,
I3 => \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34]\,
O => \s_axi_rdata_i[9]_i_9_n_0\
);
\s_axi_rresp_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440444444444444"
)
port map (
I0 => Bus_RNW_reg,
I1 => \MEM_DECODE_GEN[1].cs_out_i_reg\,
I2 => s_axi_wdata(0),
I3 => s_axi_wdata(2),
I4 => s_axi_wdata(1),
I5 => s_axi_wdata(3),
O => \^axi_ip2bus_error\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => is_write_reg,
I2 => AXI_IP2Bus_WrAck1,
I3 => AXI_IP2Bus_WrAck2,
O => \^s_axi_wready\
);
s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
O => \^mem_decode_gen[0].cs_out_i_reg[0]_0\
);
sw_rst_cond_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => Bus_RNW_reg,
I1 => \MEM_DECODE_GEN[1].cs_out_i_reg\,
I2 => s_axi_wdata(0),
I3 => s_axi_wdata(2),
I4 => s_axi_wdata(1),
I5 => s_axi_wdata(3),
O => \^sw_rst_cond\
);
\timing_param_tbuf_i[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_4_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(3)
);
\timing_param_thddat_i[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[34].ce_out_i_reg_n_0_[34]\,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(0)
);
\timing_param_thdsta_i[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_6_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(5)
);
\timing_param_thigh_i[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_3_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(2)
);
\timing_param_tlow_i[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_2_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(1)
);
\timing_param_tsudat_i[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_5_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(4)
);
\timing_param_tsusta_i[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_8_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(7)
);
\timing_param_tsusto_i[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_7_in,
I1 => Bus_RNW_reg,
O => Bus2IIC_WrCE(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_cdc_sync is
port (
detect_stop_b_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
sda_rin_d1 : in STD_LOGIC;
sda_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_cdc_sync : entity is "cdc_sync";
end system_axi_iic_0_0_cdc_sync;
architecture STRUCTURE of system_axi_iic_0_0_cdc_sync is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => sda_i,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
detect_stop_b_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^scndry_out\,
I1 => sda_rin_d1,
O => detect_stop_b_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_cdc_sync_4 is
port (
scl_rising_edge0 : out STD_LOGIC;
scl_rin_d1_reg : out STD_LOGIC;
scl_rin_d1 : in STD_LOGIC;
scl_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_cdc_sync_4 : entity is "cdc_sync";
end system_axi_iic_0_0_cdc_sync_4;
architecture STRUCTURE of system_axi_iic_0_0_cdc_sync_4 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scl_rin_d1_reg\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scl_rin_d1_reg <= \^scl_rin_d1_reg\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => scl_i,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => \^scl_rin_d1_reg\,
R => '0'
);
scl_rising_edge_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^scl_rin_d1_reg\,
I1 => scl_rin_d1,
O => scl_rising_edge0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_dynamic_master is
port (
callingReadAccess : out STD_LOGIC;
rdCntrFrmTxFifo : out STD_LOGIC;
rxCntDone : out STD_LOGIC;
firstDynStartSeen : out STD_LOGIC;
cr_txModeSelect_set : out STD_LOGIC;
cr_txModeSelect_clr : out STD_LOGIC;
rxCntDone_reg_0 : out STD_LOGIC;
Tx_fifo_rst : in STD_LOGIC;
ackDataState : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
p_3_in : in STD_LOGIC;
Tx_fifo_data : in STD_LOGIC_VECTOR ( 0 to 7 );
rdCntrFrmTxFifo0 : in STD_LOGIC;
earlyAckDataState : in STD_LOGIC;
firstDynStartSeen_reg_0 : in STD_LOGIC;
earlyAckHdr : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_dynamic_master : entity is "dynamic_master";
end system_axi_iic_0_0_dynamic_master;
architecture STRUCTURE of system_axi_iic_0_0_dynamic_master is
signal Cr_txModeSelect_clr_i_1_n_0 : STD_LOGIC;
signal Cr_txModeSelect_set_i_1_n_0 : STD_LOGIC;
signal ackDataState_d1 : STD_LOGIC;
signal \^callingreadaccess\ : STD_LOGIC;
signal earlyAckDataState_d1 : STD_LOGIC;
signal \^firstdynstartseen\ : STD_LOGIC;
signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rdByteCntr[0]_i_1_n_0\ : STD_LOGIC;
signal \rdByteCntr[0]_i_3_n_0\ : STD_LOGIC;
signal \rdByteCntr[0]_i_4_n_0\ : STD_LOGIC;
signal \rdByteCntr[0]_i_5_n_0\ : STD_LOGIC;
signal \rdByteCntr[2]_i_2_n_0\ : STD_LOGIC;
signal \rdByteCntr_reg__0\ : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^rdcntrfrmtxfifo\ : STD_LOGIC;
signal rxCntDone0 : STD_LOGIC;
signal \^rxcntdone_reg_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Cr_txModeSelect_clr_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of Cr_txModeSelect_set_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rdByteCntr[0]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rdByteCntr[2]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rdByteCntr[6]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rdByteCntr[7]_i_1\ : label is "soft_lutpair0";
begin
callingReadAccess <= \^callingreadaccess\;
firstDynStartSeen <= \^firstdynstartseen\;
rdCntrFrmTxFifo <= \^rdcntrfrmtxfifo\;
rxCntDone_reg_0 <= \^rxcntdone_reg_0\;
Cr_txModeSelect_clr_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^callingreadaccess\,
I1 => \^firstdynstartseen\,
I2 => earlyAckHdr,
I3 => Tx_fifo_rst,
O => Cr_txModeSelect_clr_i_1_n_0
);
Cr_txModeSelect_clr_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Cr_txModeSelect_clr_i_1_n_0,
Q => cr_txModeSelect_clr,
R => '0'
);
Cr_txModeSelect_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^callingreadaccess\,
I1 => \^firstdynstartseen\,
I2 => earlyAckHdr,
I3 => Tx_fifo_rst,
O => Cr_txModeSelect_set_i_1_n_0
);
Cr_txModeSelect_set_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Cr_txModeSelect_set_i_1_n_0,
Q => cr_txModeSelect_set,
R => '0'
);
ackDataState_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ackDataState,
Q => ackDataState_d1,
R => Tx_fifo_rst
);
callingReadAccess_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => p_3_in,
D => Tx_fifo_data(7),
Q => \^callingreadaccess\,
R => Tx_fifo_rst
);
earlyAckDataState_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => earlyAckDataState,
Q => earlyAckDataState_d1,
R => Tx_fifo_rst
);
firstDynStartSeen_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => firstDynStartSeen_reg_0,
Q => \^firstdynstartseen\,
R => '0'
);
\rdByteCntr[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AABABABA"
)
port map (
I0 => \^rdcntrfrmtxfifo\,
I1 => earlyAckDataState_d1,
I2 => earlyAckDataState,
I3 => \rdByteCntr[0]_i_3_n_0\,
I4 => \rdByteCntr[0]_i_4_n_0\,
O => \rdByteCntr[0]_i_1_n_0\
);
\rdByteCntr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => Tx_fifo_data(0),
I1 => \^rdcntrfrmtxfifo\,
I2 => \rdByteCntr_reg__0\(0),
I3 => \rdByteCntr[0]_i_5_n_0\,
I4 => \rdByteCntr_reg__0\(1),
O => \p_0_in__2\(7)
);
\rdByteCntr[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \rdByteCntr_reg__0\(4),
I1 => \rdByteCntr_reg__0\(5),
I2 => \rdByteCntr_reg__0\(6),
I3 => \rdByteCntr_reg__0\(7),
O => \rdByteCntr[0]_i_3_n_0\
);
\rdByteCntr[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \rdByteCntr_reg__0\(0),
I1 => \rdByteCntr_reg__0\(1),
I2 => \rdByteCntr_reg__0\(2),
I3 => \rdByteCntr_reg__0\(3),
O => \rdByteCntr[0]_i_4_n_0\
);
\rdByteCntr[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \rdByteCntr_reg__0\(2),
I1 => \rdByteCntr_reg__0\(3),
I2 => \rdByteCntr_reg__0\(7),
I3 => \rdByteCntr_reg__0\(6),
I4 => \rdByteCntr_reg__0\(5),
I5 => \rdByteCntr_reg__0\(4),
O => \rdByteCntr[0]_i_5_n_0\
);
\rdByteCntr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8BBBB888B8888"
)
port map (
I0 => Tx_fifo_data(1),
I1 => \^rdcntrfrmtxfifo\,
I2 => \rdByteCntr_reg__0\(2),
I3 => \rdByteCntr_reg__0\(3),
I4 => \rdByteCntr[0]_i_3_n_0\,
I5 => \rdByteCntr_reg__0\(1),
O => \p_0_in__2\(6)
);
\rdByteCntr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B88BB8"
)
port map (
I0 => Tx_fifo_data(2),
I1 => \^rdcntrfrmtxfifo\,
I2 => \rdByteCntr_reg__0\(2),
I3 => \rdByteCntr[2]_i_2_n_0\,
I4 => \rdByteCntr_reg__0\(7),
O => \p_0_in__2\(5)
);
\rdByteCntr[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \rdByteCntr_reg__0\(4),
I1 => \rdByteCntr_reg__0\(5),
I2 => \rdByteCntr_reg__0\(3),
I3 => \rdByteCntr_reg__0\(6),
O => \rdByteCntr[2]_i_2_n_0\
);
\rdByteCntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => Tx_fifo_data(3),
I1 => \^rdcntrfrmtxfifo\,
I2 => \rdByteCntr_reg__0\(3),
I3 => \rdByteCntr[0]_i_3_n_0\,
O => \p_0_in__2\(4)
);
\rdByteCntr[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBB88888888B"
)
port map (
I0 => Tx_fifo_data(4),
I1 => \^rdcntrfrmtxfifo\,
I2 => \rdByteCntr_reg__0\(5),
I3 => \rdByteCntr_reg__0\(6),
I4 => \rdByteCntr_reg__0\(7),
I5 => \rdByteCntr_reg__0\(4),
O => \p_0_in__2\(3)
);
\rdByteCntr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBB8888B"
)
port map (
I0 => Tx_fifo_data(5),
I1 => \^rdcntrfrmtxfifo\,
I2 => \rdByteCntr_reg__0\(7),
I3 => \rdByteCntr_reg__0\(6),
I4 => \rdByteCntr_reg__0\(5),
O => \p_0_in__2\(2)
);
\rdByteCntr[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => Tx_fifo_data(6),
I1 => \^rdcntrfrmtxfifo\,
I2 => \rdByteCntr_reg__0\(7),
I3 => \rdByteCntr_reg__0\(6),
O => \p_0_in__2\(1)
);
\rdByteCntr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => Tx_fifo_data(7),
I1 => \^rdcntrfrmtxfifo\,
I2 => \rdByteCntr_reg__0\(7),
O => \p_0_in__2\(0)
);
\rdByteCntr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \rdByteCntr[0]_i_1_n_0\,
D => \p_0_in__2\(7),
Q => \rdByteCntr_reg__0\(0),
R => Tx_fifo_rst
);
\rdByteCntr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \rdByteCntr[0]_i_1_n_0\,
D => \p_0_in__2\(6),
Q => \rdByteCntr_reg__0\(1),
R => Tx_fifo_rst
);
\rdByteCntr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \rdByteCntr[0]_i_1_n_0\,
D => \p_0_in__2\(5),
Q => \rdByteCntr_reg__0\(2),
R => Tx_fifo_rst
);
\rdByteCntr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \rdByteCntr[0]_i_1_n_0\,
D => \p_0_in__2\(4),
Q => \rdByteCntr_reg__0\(3),
R => Tx_fifo_rst
);
\rdByteCntr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \rdByteCntr[0]_i_1_n_0\,
D => \p_0_in__2\(3),
Q => \rdByteCntr_reg__0\(4),
R => Tx_fifo_rst
);
\rdByteCntr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \rdByteCntr[0]_i_1_n_0\,
D => \p_0_in__2\(2),
Q => \rdByteCntr_reg__0\(5),
R => Tx_fifo_rst
);
\rdByteCntr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \rdByteCntr[0]_i_1_n_0\,
D => \p_0_in__2\(1),
Q => \rdByteCntr_reg__0\(6),
R => Tx_fifo_rst
);
\rdByteCntr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \rdByteCntr[0]_i_1_n_0\,
D => \p_0_in__2\(0),
Q => \rdByteCntr_reg__0\(7),
R => Tx_fifo_rst
);
rdCntrFrmTxFifo_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdCntrFrmTxFifo0,
Q => \^rdcntrfrmtxfifo\,
R => Tx_fifo_rst
);
rxCntDone_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^rxcntdone_reg_0\,
I1 => ackDataState,
I2 => ackDataState_d1,
O => rxCntDone0
);
rxCntDone_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \rdByteCntr[2]_i_2_n_0\,
I1 => \rdByteCntr_reg__0\(2),
I2 => \^callingreadaccess\,
I3 => \rdByteCntr_reg__0\(7),
I4 => \rdByteCntr_reg__0\(1),
I5 => \rdByteCntr_reg__0\(0),
O => \^rxcntdone_reg_0\
);
rxCntDone_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rxCntDone0,
Q => rxCntDone,
R => Tx_fifo_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : out STD_LOGIC;
p_1_in17_in : out STD_LOGIC;
p_1_in14_in : out STD_LOGIC;
p_1_in11_in : out STD_LOGIC;
p_1_in8_in : out STD_LOGIC;
p_1_in5_in : out STD_LOGIC;
p_1_in2_in : out STD_LOGIC;
p_1_in : out STD_LOGIC;
ipif_glbl_irpt_enable_reg : out STD_LOGIC;
iic2intc_irpt : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_interrupt_control : entity is "interrupt_control";
end system_axi_iic_0_0_interrupt_control;
architecture STRUCTURE of system_axi_iic_0_0_interrupt_control is
signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal iic2intc_irpt_INST_0_i_1_n_0 : STD_LOGIC;
signal iic2intc_irpt_INST_0_i_2_n_0 : STD_LOGIC;
signal iic2intc_irpt_INST_0_i_3_n_0 : STD_LOGIC;
signal iic2intc_irpt_INST_0_i_4_n_0 : STD_LOGIC;
signal \^ipif_glbl_irpt_enable_reg\ : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
signal \^p_1_in11_in\ : STD_LOGIC;
signal \^p_1_in14_in\ : STD_LOGIC;
signal \^p_1_in17_in\ : STD_LOGIC;
signal \^p_1_in2_in\ : STD_LOGIC;
signal \^p_1_in5_in\ : STD_LOGIC;
signal \^p_1_in8_in\ : STD_LOGIC;
begin
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\;
Q(7 downto 0) <= \^q\(7 downto 0);
ipif_glbl_irpt_enable_reg <= \^ipif_glbl_irpt_enable_reg\;
p_1_in <= \^p_1_in\;
p_1_in11_in <= \^p_1_in11_in\;
p_1_in14_in <= \^p_1_in14_in\;
p_1_in17_in <= \^p_1_in17_in\;
p_1_in2_in <= \^p_1_in2_in\;
p_1_in5_in <= \^p_1_in5_in\;
p_1_in8_in <= \^p_1_in8_in\;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg,
Q => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
R => SR(0)
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_0,
Q => \^p_1_in17_in\,
R => SR(0)
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_1,
Q => \^p_1_in14_in\,
R => SR(0)
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_2,
Q => \^p_1_in11_in\,
R => SR(0)
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_3,
Q => \^p_1_in8_in\,
R => SR(0)
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_4,
Q => \^p_1_in5_in\,
R => SR(0)
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_5,
Q => \^p_1_in2_in\,
R => SR(0)
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_6,
Q => \^p_1_in\,
R => SR(0)
);
iic2intc_irpt_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAA8AA"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg\,
I1 => iic2intc_irpt_INST_0_i_1_n_0,
I2 => iic2intc_irpt_INST_0_i_2_n_0,
I3 => iic2intc_irpt_INST_0_i_3_n_0,
I4 => iic2intc_irpt_INST_0_i_4_n_0,
O => iic2intc_irpt
);
iic2intc_irpt_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^q\(4),
I1 => \^p_1_in8_in\,
I2 => \^q\(2),
I3 => \^p_1_in14_in\,
O => iic2intc_irpt_INST_0_i_1_n_0
);
iic2intc_irpt_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^q\(3),
I1 => \^p_1_in11_in\,
I2 => \^q\(6),
I3 => \^p_1_in2_in\,
O => iic2intc_irpt_INST_0_i_2_n_0
);
iic2intc_irpt_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0777"
)
port map (
I0 => \^q\(5),
I1 => \^p_1_in5_in\,
I2 => \^q\(7),
I3 => \^p_1_in\,
O => iic2intc_irpt_INST_0_i_3_n_0
);
iic2intc_irpt_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^q\(1),
I1 => \^p_1_in17_in\,
I2 => \^q\(0),
I3 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
O => iic2intc_irpt_INST_0_i_4_n_0
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => \^q\(0),
R => SR(0)
);
\ip_irpt_enable_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => \^q\(1),
R => SR(0)
);
\ip_irpt_enable_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => \^q\(2),
R => SR(0)
);
\ip_irpt_enable_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => \^q\(3),
R => SR(0)
);
\ip_irpt_enable_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => \^q\(4),
R => SR(0)
);
\ip_irpt_enable_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => \^q\(5),
R => SR(0)
);
\ip_irpt_enable_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => \^q\(6),
R => SR(0)
);
\ip_irpt_enable_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => \^q\(7),
R => SR(0)
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\,
Q => \^ipif_glbl_irpt_enable_reg\,
R => SR(0)
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => irpt_wrack_d1,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_reg_interface is
port (
IIC2Bus_IntrEvent : out STD_LOGIC_VECTOR ( 0 to 7 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
Tx_fifo_wr : out STD_LOGIC;
Tx_fifo_rd : out STD_LOGIC;
Tx_fifo_rst : out STD_LOGIC;
new_rcv_dta_d1 : out STD_LOGIC;
Rc_fifo_wr : out STD_LOGIC;
Rc_fifo_rd : out STD_LOGIC;
dtre_d1_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
gpo : out STD_LOGIC_VECTOR ( 0 to 0 );
Msms_set : out STD_LOGIC;
state122_out : out STD_LOGIC;
slave_sda_reg : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\FSM_sequential_scl_state_reg[0]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
sda_cout_reg_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
sda_cout_reg_reg_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
\FSM_sequential_scl_state_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\FSM_sequential_scl_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\FSM_sequential_scl_state_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\q_int_reg[0]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\FSM_sequential_scl_state_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\FSM_sequential_scl_state_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_sequential_scl_state_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\FSM_sequential_scl_state_reg[1]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sda_setup_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
\FSM_onehot_state_reg[4]\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
Data_Exists_DFF : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
txak : out STD_LOGIC;
D_1 : out STD_LOGIC;
Data_Exists_DFF_0 : out STD_LOGIC;
\cr_i_reg[5]_0\ : out STD_LOGIC;
\q_int_reg[9]\ : out STD_LOGIC;
\FSM_sequential_scl_state_reg[0]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\RD_FIFO_CNTRL.ro_prev_i_reg_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_rdata_i_reg[3]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
\Addr_Counters[0].FDRE_I\ : out STD_LOGIC;
D_2 : out STD_LOGIC;
\Addr_Counters[0].FDRE_I_0\ : out STD_LOGIC;
\Addr_Counters[0].FDRE_I_1\ : out STD_LOGIC;
firstDynStartSeen_reg : out STD_LOGIC;
Bus2IIC_Reset : in STD_LOGIC;
\Addr_Counters[3].FDRE_I\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
p_6_out : in STD_LOGIC;
Bus2IIC_WrCE : in STD_LOGIC_VECTOR ( 11 downto 0 );
rdy_new_xmt_i : in STD_LOGIC;
New_rcv_dta : in STD_LOGIC;
new_rcv_dta_i_reg : in STD_LOGIC;
Bus2IIC_RdCE : in STD_LOGIC_VECTOR ( 0 to 0 );
Data_Exists_DFF_1 : in STD_LOGIC;
Aas : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\ : in STD_LOGIC;
master_slave : in STD_LOGIC;
\q_int_reg[0]_0\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\q_int_reg[0]_1\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\data_int_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
\FSM_sequential_scl_state_reg[2]_1\ : in STD_LOGIC;
\FSM_sequential_scl_state_reg[0]_2\ : in STD_LOGIC;
rdCntrFrmTxFifo : in STD_LOGIC;
Tx_fifo_rd_d : in STD_LOGIC;
\Addr_Counters[1].FDRE_I\ : in STD_LOGIC;
Data_Exists_DFF_2 : in STD_LOGIC;
Tx_fifo_wr_d : in STD_LOGIC;
Data_Exists_DFF_3 : in STD_LOGIC_VECTOR ( 5 downto 0 );
\rdByteCntr_reg[2]\ : in STD_LOGIC;
earlyAckDataState : in STD_LOGIC;
dynamic_MSMS : in STD_LOGIC_VECTOR ( 0 to 0 );
Tx_data_exists : in STD_LOGIC;
firstDynStartSeen : in STD_LOGIC;
\Addr_Counters[1].FDRE_I_0\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
stop_scl_reg : in STD_LOGIC;
\timing_param_tsusto_i_reg[9]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\timing_param_tsusta_i_reg[9]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
arb_lost : in STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
Rc_addr : in STD_LOGIC_VECTOR ( 0 to 3 );
Tx_fifo_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
Rc_fifo_wr_d : in STD_LOGIC;
Rc_fifo_rd_d : in STD_LOGIC;
\Addr_Counters[1].FDRE_I_1\ : in STD_LOGIC;
Rc_Data_Exists : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
al_i_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_reg_interface : entity is "reg_interface";
end system_axi_iic_0_0_reg_interface;
architecture STRUCTURE of system_axi_iic_0_0_reg_interface is
signal Cr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^data_exists_dff\ : STD_LOGIC;
signal \^data_exists_dff_0\ : STD_LOGIC;
signal \^fsm_sequential_scl_state_reg[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^fsm_sequential_scl_state_reg[1]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^fsm_sequential_scl_state_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^fsm_sequential_scl_state_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^iic2bus_intrevent\ : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^msms_set\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^rd_fifo_cntrl.ro_prev_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^rc_fifo_rd\ : STD_LOGIC;
signal \^rc_fifo_wr\ : STD_LOGIC;
signal \^tx_fifo_rd\ : STD_LOGIC;
signal \^tx_fifo_rst\ : STD_LOGIC;
signal \^tx_fifo_wr\ : STD_LOGIC;
signal adr_i : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \cr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \cr_i[2]_i_2_n_0\ : STD_LOGIC;
signal \^dtre_d1_reg\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal firstDynStartSeen_i_2_n_0 : STD_LOGIC;
signal \^gpo\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal msms_d1 : STD_LOGIC;
signal msms_set_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_10_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_6_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_9_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_8_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_8_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_8_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_8_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[8]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[8]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_5_n_0\ : STD_LOGIC;
signal \^s_axi_rdata_i_reg[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rdata_i_reg[7]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_rdata_i_reg[8]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^sda_cout_reg_reg_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal slave_sda_i_3_n_0 : STD_LOGIC;
signal slave_sda_i_4_n_0 : STD_LOGIC;
signal \^slave_sda_reg\ : STD_LOGIC;
signal sr_i : STD_LOGIC_VECTOR ( 1 to 7 );
signal timing_param_tbuf_i : STD_LOGIC_VECTOR ( 9 downto 0 );
signal timing_param_thddat_i : STD_LOGIC_VECTOR ( 9 downto 0 );
signal timing_param_thdsta_i : STD_LOGIC_VECTOR ( 9 downto 1 );
signal timing_param_thigh_i : STD_LOGIC_VECTOR ( 9 downto 8 );
signal timing_param_tlow_i : STD_LOGIC_VECTOR ( 9 downto 1 );
signal timing_param_tsudat_i : STD_LOGIC_VECTOR ( 9 to 9 );
signal timing_param_tsusta_i : STD_LOGIC_VECTOR ( 9 downto 0 );
signal timing_param_tsusto_i : STD_LOGIC_VECTOR ( 9 downto 8 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Addr_Counters[0].MUXCY_L_I_i_4\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Data_Exists_DFF_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \Data_Exists_DFF_i_2__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \FSM_onehot_state[0]_i_2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \FSM_onehot_state[4]_i_4\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of firstDynStartSeen_i_2 : label is "soft_lutpair27";
begin
D(0) <= \^d\(0);
Data_Exists_DFF <= \^data_exists_dff\;
Data_Exists_DFF_0 <= \^data_exists_dff_0\;
\FSM_sequential_scl_state_reg[0]\(7 downto 0) <= \^fsm_sequential_scl_state_reg[0]\(7 downto 0);
\FSM_sequential_scl_state_reg[1]_0\(0) <= \^fsm_sequential_scl_state_reg[1]_0\(0);
\FSM_sequential_scl_state_reg[2]_0\(0) <= \^fsm_sequential_scl_state_reg[2]_0\(0);
\FSM_sequential_scl_state_reg[3]_0\(3 downto 0) <= \^fsm_sequential_scl_state_reg[3]_0\(3 downto 0);
IIC2Bus_IntrEvent(0 to 7) <= \^iic2bus_intrevent\(0 to 7);
Msms_set <= \^msms_set\;
Q(4 downto 0) <= \^q\(4 downto 0);
\RD_FIFO_CNTRL.ro_prev_i_reg_0\(3 downto 0) <= \^rd_fifo_cntrl.ro_prev_i_reg_0\(3 downto 0);
Rc_fifo_rd <= \^rc_fifo_rd\;
Rc_fifo_wr <= \^rc_fifo_wr\;
Tx_fifo_rd <= \^tx_fifo_rd\;
Tx_fifo_rst <= \^tx_fifo_rst\;
Tx_fifo_wr <= \^tx_fifo_wr\;
dtre_d1_reg(2 downto 0) <= \^dtre_d1_reg\(2 downto 0);
gpo(0) <= \^gpo\(0);
\s_axi_rdata_i_reg[5]\(1 downto 0) <= \^s_axi_rdata_i_reg[5]\(1 downto 0);
\s_axi_rdata_i_reg[7]\(3 downto 0) <= \^s_axi_rdata_i_reg[7]\(3 downto 0);
\s_axi_rdata_i_reg[8]\(8 downto 0) <= \^s_axi_rdata_i_reg[8]\(8 downto 0);
sda_cout_reg_reg_0(7 downto 0) <= \^sda_cout_reg_reg_0\(7 downto 0);
slave_sda_reg <= \^slave_sda_reg\;
\Addr_Counters[0].MUXCY_L_I_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^tx_fifo_wr\,
I1 => Tx_fifo_wr_d,
O => \Addr_Counters[0].FDRE_I\
);
\Addr_Counters[0].MUXCY_L_I_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^rc_fifo_rd\,
I1 => Rc_fifo_rd_d,
O => \Addr_Counters[0].FDRE_I_1\
);
\Addr_Counters[0].MUXCY_L_I_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^rc_fifo_wr\,
I1 => Rc_fifo_wr_d,
O => \Addr_Counters[0].FDRE_I_0\
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBABB0000AAAA"
)
port map (
I0 => \^data_exists_dff\,
I1 => rdCntrFrmTxFifo,
I2 => Tx_fifo_rd_d,
I3 => \^tx_fifo_rd\,
I4 => \Addr_Counters[1].FDRE_I\,
I5 => Data_Exists_DFF_2,
O => D_0
);
\Data_Exists_DFF_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF20022"
)
port map (
I0 => \^tx_fifo_wr\,
I1 => Tx_fifo_wr_d,
I2 => \^data_exists_dff_0\,
I3 => \Addr_Counters[1].FDRE_I_0\,
I4 => Tx_data_exists,
O => D_1
);
\Data_Exists_DFF_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF2FF00002222"
)
port map (
I0 => \^rc_fifo_wr\,
I1 => Rc_fifo_wr_d,
I2 => Rc_fifo_rd_d,
I3 => \^rc_fifo_rd\,
I4 => \Addr_Counters[1].FDRE_I_1\,
I5 => Rc_Data_Exists,
O => D_2
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF4"
)
port map (
I0 => Tx_fifo_wr_d,
I1 => \^tx_fifo_wr\,
I2 => Bus2IIC_Reset,
I3 => \^tx_fifo_rst\,
O => \^data_exists_dff\
);
\Data_Exists_DFF_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"0D"
)
port map (
I0 => \^tx_fifo_rd\,
I1 => Tx_fifo_rd_d,
I2 => rdCntrFrmTxFifo,
O => \^data_exists_dff_0\
);
\FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Addr_Counters[3].FDRE_I\,
Q => \^iic2bus_intrevent\(7),
R => Bus2IIC_Reset
);
\FIFO_GEN_DTR.Tx_fifo_rd_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdy_new_xmt_i,
Q => \^tx_fifo_rd\,
R => Bus2IIC_Reset
);
\FIFO_GEN_DTR.Tx_fifo_rst_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => Cr(6),
Q => \^tx_fifo_rst\,
S => Bus2IIC_Reset
);
\FIFO_GEN_DTR.Tx_fifo_wr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus2IIC_WrCE(10),
Q => \^tx_fifo_wr\,
R => Bus2IIC_Reset
);
\FSM_onehot_state[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^slave_sda_reg\,
I1 => master_slave,
O => state122_out
);
\FSM_onehot_state[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \^q\(2),
I1 => master_slave,
I2 => \data_int_reg[7]\(0),
I3 => \^slave_sda_reg\,
O => \FSM_onehot_state_reg[4]\
);
\FSM_sequential_scl_state[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => SR(0)
);
\FSM_sequential_scl_state[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \timing_param_tsusta_i_reg[9]_0\(0),
I1 => \^q\(3),
I2 => \timing_param_tsusto_i_reg[9]_0\(0),
I3 => stop_scl_reg,
I4 => CO(0),
O => \FSM_sequential_scl_state_reg[0]_1\
);
\GPO_GEN.gpo_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\,
Q => \^gpo\(0),
R => Bus2IIC_Reset
);
\IIC2Bus_IntrEvent_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => al_i_reg(4),
Q => \^iic2bus_intrevent\(0),
R => Bus2IIC_Reset
);
\IIC2Bus_IntrEvent_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => al_i_reg(3),
Q => \^iic2bus_intrevent\(1),
R => Bus2IIC_Reset
);
\IIC2Bus_IntrEvent_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => al_i_reg(2),
Q => \^iic2bus_intrevent\(2),
R => Bus2IIC_Reset
);
\IIC2Bus_IntrEvent_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^d\(0),
Q => \^iic2bus_intrevent\(3),
R => Bus2IIC_Reset
);
\IIC2Bus_IntrEvent_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => al_i_reg(1),
Q => \^iic2bus_intrevent\(4),
R => Bus2IIC_Reset
);
\IIC2Bus_IntrEvent_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Aas,
Q => \^iic2bus_intrevent\(5),
R => Bus2IIC_Reset
);
\IIC2Bus_IntrEvent_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => al_i_reg(0),
Q => \^iic2bus_intrevent\(6),
R => Bus2IIC_Reset
);
\LEVEL_1_GEN.master_sda_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => Cr(3),
I1 => \rdByteCntr_reg[2]\,
I2 => earlyAckDataState,
O => txak
);
\RD_FIFO_CNTRL.Rc_fifo_rd_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus2IIC_RdCE(0),
Q => \^rc_fifo_rd\,
R => Bus2IIC_Reset
);
\RD_FIFO_CNTRL.Rc_fifo_wr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => new_rcv_dta_i_reg,
Q => \^rc_fifo_wr\,
R => Bus2IIC_Reset
);
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(8),
D => s_axi_wdata(3),
Q => \^rd_fifo_cntrl.ro_prev_i_reg_0\(3),
R => Bus2IIC_Reset
);
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(8),
D => s_axi_wdata(2),
Q => \^rd_fifo_cntrl.ro_prev_i_reg_0\(2),
R => Bus2IIC_Reset
);
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(8),
D => s_axi_wdata(1),
Q => \^rd_fifo_cntrl.ro_prev_i_reg_0\(1),
R => Bus2IIC_Reset
);
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(8),
D => s_axi_wdata(0),
Q => \^rd_fifo_cntrl.ro_prev_i_reg_0\(0),
R => Bus2IIC_Reset
);
\RD_FIFO_CNTRL.ro_prev_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_6_out,
Q => \^d\(0),
R => '0'
);
\adr_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(9),
D => s_axi_wdata(7),
Q => adr_i(7),
R => Bus2IIC_Reset
);
\adr_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(9),
D => s_axi_wdata(6),
Q => adr_i(6),
R => Bus2IIC_Reset
);
\adr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(9),
D => s_axi_wdata(5),
Q => adr_i(5),
R => Bus2IIC_Reset
);
\adr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(9),
D => s_axi_wdata(4),
Q => adr_i(4),
R => Bus2IIC_Reset
);
\adr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(9),
D => s_axi_wdata(3),
Q => adr_i(3),
R => Bus2IIC_Reset
);
\adr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(9),
D => s_axi_wdata(2),
Q => adr_i(2),
R => Bus2IIC_Reset
);
\adr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(9),
D => s_axi_wdata(1),
Q => adr_i(1),
R => Bus2IIC_Reset
);
clk_cnt_en1_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => timing_param_thigh_i(9),
I1 => \q_int_reg[0]_0\(9),
O => S(3)
);
clk_cnt_en1_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^fsm_sequential_scl_state_reg[0]\(7),
I1 => \q_int_reg[0]_0\(7),
I2 => \q_int_reg[0]_0\(8),
I3 => timing_param_thigh_i(8),
I4 => \q_int_reg[0]_0\(6),
I5 => \^fsm_sequential_scl_state_reg[0]\(6),
O => S(2)
);
clk_cnt_en1_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^fsm_sequential_scl_state_reg[0]\(4),
I1 => \q_int_reg[0]_0\(4),
I2 => \q_int_reg[0]_0\(5),
I3 => \^fsm_sequential_scl_state_reg[0]\(5),
I4 => \q_int_reg[0]_0\(3),
I5 => \^fsm_sequential_scl_state_reg[0]\(3),
O => S(1)
);
clk_cnt_en1_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^fsm_sequential_scl_state_reg[0]\(2),
I1 => \q_int_reg[0]_0\(2),
I2 => \q_int_reg[0]_0\(0),
I3 => \^fsm_sequential_scl_state_reg[0]\(0),
I4 => \q_int_reg[0]_0\(1),
I5 => \^fsm_sequential_scl_state_reg[0]\(1),
O => S(0)
);
clk_cnt_en2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => timing_param_thddat_i(9),
I1 => \q_int_reg[0]_0\(9),
O => \q_int_reg[0]\(3)
);
clk_cnt_en2_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_thddat_i(7),
I1 => \q_int_reg[0]_0\(7),
I2 => \q_int_reg[0]_0\(8),
I3 => timing_param_thddat_i(8),
I4 => \q_int_reg[0]_0\(6),
I5 => timing_param_thddat_i(6),
O => \q_int_reg[0]\(2)
);
clk_cnt_en2_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rdata_i_reg[5]\(0),
I1 => \q_int_reg[0]_0\(4),
I2 => \q_int_reg[0]_0\(5),
I3 => \^s_axi_rdata_i_reg[5]\(1),
I4 => \q_int_reg[0]_0\(3),
I5 => timing_param_thddat_i(3),
O => \q_int_reg[0]\(1)
);
clk_cnt_en2_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_thddat_i(2),
I1 => \q_int_reg[0]_0\(2),
I2 => \q_int_reg[0]_0\(0),
I3 => timing_param_thddat_i(0),
I4 => \q_int_reg[0]_0\(1),
I5 => timing_param_thddat_i(1),
O => \q_int_reg[0]\(0)
);
\cr_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B888B8B8B8"
)
port map (
I0 => s_axi_wdata(5),
I1 => Bus2IIC_WrCE(11),
I2 => \cr_i[2]_i_2_n_0\,
I3 => \FSM_sequential_scl_state_reg[2]_1\,
I4 => \^q\(3),
I5 => \FSM_sequential_scl_state_reg[0]_2\,
O => \cr_i[2]_i_1_n_0\
);
\cr_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEAAAAAAAAAAAAAA"
)
port map (
I0 => \^q\(3),
I1 => \^tx_fifo_rd\,
I2 => Tx_fifo_rd_d,
I3 => dynamic_MSMS(0),
I4 => Tx_data_exists,
I5 => firstDynStartSeen,
O => \cr_i[2]_i_2_n_0\
);
\cr_i[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Tx_fifo_rd_d,
I1 => \^tx_fifo_rd\,
O => \cr_i_reg[5]_0\
);
\cr_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(11),
D => s_axi_wdata(7),
Q => Cr(0),
R => Bus2IIC_Reset
);
\cr_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(11),
D => s_axi_wdata(6),
Q => \^q\(4),
R => Bus2IIC_Reset
);
\cr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \cr_i[2]_i_1_n_0\,
Q => \^q\(3),
R => Bus2IIC_Reset
);
\cr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(11),
D => s_axi_wdata(4),
Q => Cr(3),
R => Bus2IIC_Reset
);
\cr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\(1),
Q => \^q\(2),
R => Bus2IIC_Reset
);
\cr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\(0),
Q => \^q\(1),
R => Bus2IIC_Reset
);
\cr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(11),
D => s_axi_wdata(1),
Q => Cr(6),
R => Bus2IIC_Reset
);
\cr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(11),
D => s_axi_wdata(0),
Q => \^q\(0),
R => Bus2IIC_Reset
);
firstDynStartSeen_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00B0"
)
port map (
I0 => firstDynStartSeen,
I1 => firstDynStartSeen_i_2_n_0,
I2 => \^q\(1),
I3 => \^tx_fifo_rst\,
O => firstDynStartSeen_reg
);
firstDynStartSeen_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \^tx_fifo_rd\,
I1 => Tx_fifo_rd_d,
I2 => dynamic_MSMS(0),
I3 => Tx_data_exists,
O => firstDynStartSeen_i_2_n_0
);
\i__carry_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => timing_param_tsusto_i(9),
I1 => \q_int_reg[0]_0\(9),
O => sda_cout_reg_reg(3)
);
\i__carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => timing_param_tsusta_i(9),
I1 => \q_int_reg[0]_0\(9),
O => \FSM_sequential_scl_state_reg[0]_0\(3)
);
\i__carry_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => timing_param_tbuf_i(9),
I1 => \q_int_reg[0]_0\(9),
O => \FSM_sequential_scl_state_reg[3]\(3)
);
\i__carry_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => timing_param_thdsta_i(9),
I1 => \q_int_reg[0]_0\(9),
O => \FSM_sequential_scl_state_reg[2]\(3)
);
\i__carry_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => timing_param_tlow_i(9),
I1 => \q_int_reg[0]_0\(9),
O => \FSM_sequential_scl_state_reg[1]\(3)
);
\i__carry_i_1__4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => timing_param_tsudat_i(9),
I1 => \q_int_reg[0]_1\(6),
O => sda_setup_reg(2)
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_tsusto_i(8),
I1 => \q_int_reg[0]_0\(8),
I2 => \q_int_reg[0]_0\(7),
I3 => \^sda_cout_reg_reg_0\(7),
I4 => \q_int_reg[0]_0\(6),
I5 => \^sda_cout_reg_reg_0\(6),
O => sda_cout_reg_reg(2)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rdata_i_reg[7]\(3),
I1 => \q_int_reg[0]_0\(7),
I2 => \q_int_reg[0]_0\(8),
I3 => timing_param_tsusta_i(8),
I4 => \q_int_reg[0]_0\(6),
I5 => \^s_axi_rdata_i_reg[7]\(2),
O => \FSM_sequential_scl_state_reg[0]_0\(2)
);
\i__carry_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^fsm_sequential_scl_state_reg[3]_0\(3),
I1 => \q_int_reg[0]_0\(7),
I2 => \q_int_reg[0]_0\(8),
I3 => timing_param_tbuf_i(8),
I4 => \q_int_reg[0]_0\(6),
I5 => \^fsm_sequential_scl_state_reg[3]_0\(2),
O => \FSM_sequential_scl_state_reg[3]\(2)
);
\i__carry_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_thdsta_i(7),
I1 => \q_int_reg[0]_0\(7),
I2 => \q_int_reg[0]_0\(8),
I3 => timing_param_thdsta_i(8),
I4 => \q_int_reg[0]_0\(6),
I5 => timing_param_thdsta_i(6),
O => \FSM_sequential_scl_state_reg[2]\(2)
);
\i__carry_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_tlow_i(8),
I1 => \q_int_reg[0]_0\(8),
I2 => \q_int_reg[0]_0\(6),
I3 => timing_param_tlow_i(6),
I4 => \q_int_reg[0]_0\(7),
I5 => timing_param_tlow_i(7),
O => \FSM_sequential_scl_state_reg[1]\(2)
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^sda_cout_reg_reg_0\(5),
I1 => \q_int_reg[0]_0\(5),
I2 => \q_int_reg[0]_0\(4),
I3 => \^sda_cout_reg_reg_0\(4),
I4 => \q_int_reg[0]_0\(3),
I5 => \^sda_cout_reg_reg_0\(3),
O => sda_cout_reg_reg(1)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rdata_i_reg[7]\(0),
I1 => \q_int_reg[0]_0\(4),
I2 => \q_int_reg[0]_0\(5),
I3 => \^s_axi_rdata_i_reg[7]\(1),
I4 => \q_int_reg[0]_0\(3),
I5 => timing_param_tsusta_i(3),
O => \FSM_sequential_scl_state_reg[0]_0\(1)
);
\i__carry_i_3__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^fsm_sequential_scl_state_reg[3]_0\(1),
I1 => \q_int_reg[0]_0\(5),
I2 => \q_int_reg[0]_0\(3),
I3 => timing_param_tbuf_i(3),
I4 => \q_int_reg[0]_0\(4),
I5 => \^fsm_sequential_scl_state_reg[3]_0\(0),
O => \FSM_sequential_scl_state_reg[3]\(1)
);
\i__carry_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_thdsta_i(4),
I1 => \q_int_reg[0]_0\(4),
I2 => \q_int_reg[0]_0\(5),
I3 => timing_param_thdsta_i(5),
I4 => \q_int_reg[0]_0\(3),
I5 => timing_param_thdsta_i(3),
O => \FSM_sequential_scl_state_reg[2]\(1)
);
\i__carry_i_3__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_tlow_i(5),
I1 => \q_int_reg[0]_0\(5),
I2 => \q_int_reg[0]_0\(4),
I3 => timing_param_tlow_i(4),
I4 => \q_int_reg[0]_0\(3),
I5 => timing_param_tlow_i(3),
O => \FSM_sequential_scl_state_reg[1]\(1)
);
\i__carry_i_3__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rdata_i_reg[8]\(4),
I1 => \q_int_reg[0]_1\(4),
I2 => \q_int_reg[0]_1\(5),
I3 => \^s_axi_rdata_i_reg[8]\(5),
I4 => \q_int_reg[0]_1\(3),
I5 => \^s_axi_rdata_i_reg[8]\(3),
O => sda_setup_reg(1)
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^sda_cout_reg_reg_0\(2),
I1 => \q_int_reg[0]_0\(2),
I2 => \q_int_reg[0]_0\(0),
I3 => \^sda_cout_reg_reg_0\(0),
I4 => \q_int_reg[0]_0\(1),
I5 => \^sda_cout_reg_reg_0\(1),
O => sda_cout_reg_reg(0)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_tsusta_i(1),
I1 => \q_int_reg[0]_0\(1),
I2 => \q_int_reg[0]_0\(2),
I3 => timing_param_tsusta_i(2),
I4 => \q_int_reg[0]_0\(0),
I5 => timing_param_tsusta_i(0),
O => \FSM_sequential_scl_state_reg[0]_0\(0)
);
\i__carry_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_tbuf_i(2),
I1 => \q_int_reg[0]_0\(2),
I2 => \q_int_reg[0]_0\(0),
I3 => timing_param_tbuf_i(0),
I4 => \q_int_reg[0]_0\(1),
I5 => timing_param_tbuf_i(1),
O => \FSM_sequential_scl_state_reg[3]\(0)
);
\i__carry_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_thdsta_i(1),
I1 => \q_int_reg[0]_0\(1),
I2 => \q_int_reg[0]_0\(2),
I3 => timing_param_thdsta_i(2),
I4 => \q_int_reg[0]_0\(0),
I5 => \^fsm_sequential_scl_state_reg[2]_0\(0),
O => \FSM_sequential_scl_state_reg[2]\(0)
);
\i__carry_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => timing_param_tlow_i(2),
I1 => \q_int_reg[0]_0\(2),
I2 => \q_int_reg[0]_0\(0),
I3 => \^fsm_sequential_scl_state_reg[1]_0\(0),
I4 => \q_int_reg[0]_0\(1),
I5 => timing_param_tlow_i(1),
O => \FSM_sequential_scl_state_reg[1]\(0)
);
\i__carry_i_4__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rdata_i_reg[8]\(2),
I1 => \q_int_reg[0]_1\(2),
I2 => \q_int_reg[0]_1\(0),
I3 => \^s_axi_rdata_i_reg[8]\(0),
I4 => \q_int_reg[0]_1\(1),
I5 => \^s_axi_rdata_i_reg[8]\(1),
O => sda_setup_reg(0)
);
msms_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(1),
Q => msms_d1,
R => Bus2IIC_Reset
);
msms_set_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"CE0C0A00"
)
port map (
I0 => \^d\(0),
I1 => Data_Exists_DFF_3(1),
I2 => \^q\(1),
I3 => msms_d1,
I4 => \^msms_set\,
O => msms_set_i_i_1_n_0
);
msms_set_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => msms_set_i_i_1_n_0,
Q => \^msms_set\,
R => Bus2IIC_Reset
);
new_rcv_dta_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => New_rcv_dta,
Q => new_rcv_dta_d1,
R => Bus2IIC_Reset
);
\q_int[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFE200E2"
)
port map (
I0 => CO(0),
I1 => stop_scl_reg,
I2 => \timing_param_tsusto_i_reg[9]_0\(0),
I3 => \^q\(3),
I4 => \timing_param_tsusta_i_reg[9]_0\(0),
I5 => arb_lost,
O => \q_int_reg[9]\
);
\s_axi_rdata_i[0]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => \^gpo\(0),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_thddat_i(0),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => sr_i(7),
O => \s_axi_rdata_i_reg[0]\
);
\s_axi_rdata_i[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => timing_param_tbuf_i(0),
I1 => Rc_addr(0),
I2 => \bus2ip_addr_i_reg[6]\(2),
I3 => timing_param_tsusta_i(0),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => Tx_fifo_data(0),
O => \s_axi_rdata_i_reg[0]_0\
);
\s_axi_rdata_i[1]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^rd_fifo_cntrl.ro_prev_i_reg_0\(1),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_tlow_i(1),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => Cr(6),
O => \s_axi_rdata_i[1]_i_10_n_0\
);
\s_axi_rdata_i[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => adr_i(1),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_thdsta_i(1),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => \s_axi_rdata_i[1]_i_10_n_0\,
O => \s_axi_rdata_i_reg[1]\
);
\s_axi_rdata_i[1]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => \^iic2bus_intrevent\(5),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => timing_param_thddat_i(1),
I3 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i_reg[1]_0\
);
\s_axi_rdata_i[1]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => timing_param_tbuf_i(1),
I1 => Rc_addr(1),
I2 => \bus2ip_addr_i_reg[6]\(2),
I3 => timing_param_tsusta_i(1),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => Tx_fifo_data(1),
O => \s_axi_rdata_i_reg[1]_1\
);
\s_axi_rdata_i[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => adr_i(2),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_thdsta_i(2),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => \s_axi_rdata_i[2]_i_6_n_0\,
O => \s_axi_rdata_i_reg[2]_0\
);
\s_axi_rdata_i[2]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^rd_fifo_cntrl.ro_prev_i_reg_0\(2),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_tlow_i(2),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \^q\(1),
O => \s_axi_rdata_i[2]_i_6_n_0\
);
\s_axi_rdata_i[2]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => sr_i(5),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => timing_param_thddat_i(2),
I3 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i_reg[2]_1\
);
\s_axi_rdata_i[2]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => timing_param_tbuf_i(2),
I1 => Rc_addr(2),
I2 => \bus2ip_addr_i_reg[6]\(2),
I3 => timing_param_tsusta_i(2),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => Tx_fifo_data(2),
O => \s_axi_rdata_i_reg[2]\
);
\s_axi_rdata_i[3]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => sr_i(4),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => timing_param_thddat_i(3),
I3 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i_reg[3]_0\
);
\s_axi_rdata_i[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => timing_param_tbuf_i(3),
I1 => Rc_addr(3),
I2 => \bus2ip_addr_i_reg[6]\(2),
I3 => timing_param_tsusta_i(3),
I4 => \bus2ip_addr_i_reg[6]\(3),
I5 => Tx_fifo_data(3),
O => \s_axi_rdata_i_reg[3]_1\
);
\s_axi_rdata_i[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => adr_i(3),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_thdsta_i(3),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => \s_axi_rdata_i[3]_i_9_n_0\,
O => \s_axi_rdata_i_reg[3]\
);
\s_axi_rdata_i[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \^rd_fifo_cntrl.ro_prev_i_reg_0\(3),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_tlow_i(3),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \^q\(2),
O => \s_axi_rdata_i[3]_i_9_n_0\
);
\s_axi_rdata_i[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => adr_i(4),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_thdsta_i(4),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => \s_axi_rdata_i[4]_i_8_n_0\,
O => \s_axi_rdata_i_reg[4]\
);
\s_axi_rdata_i[4]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => Cr(3),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => timing_param_tlow_i(4),
I3 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i[4]_i_8_n_0\
);
\s_axi_rdata_i[5]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => adr_i(5),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_thdsta_i(5),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => \s_axi_rdata_i[5]_i_8_n_0\,
O => \s_axi_rdata_i_reg[5]_0\
);
\s_axi_rdata_i[5]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => \^q\(3),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => timing_param_tlow_i(5),
I3 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i[5]_i_8_n_0\
);
\s_axi_rdata_i[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => adr_i(6),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_thdsta_i(6),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => \s_axi_rdata_i[6]_i_8_n_0\,
O => \s_axi_rdata_i_reg[6]_0\
);
\s_axi_rdata_i[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088008833300030"
)
port map (
I0 => \^s_axi_rdata_i_reg[8]\(6),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => sr_i(1),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => timing_param_thddat_i(6),
I5 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i_reg[6]\
);
\s_axi_rdata_i[6]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => \^q\(4),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => timing_param_tlow_i(6),
I3 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i[6]_i_8_n_0\
);
\s_axi_rdata_i[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => adr_i(7),
I1 => \bus2ip_addr_i_reg[6]\(3),
I2 => timing_param_thdsta_i(7),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => \s_axi_rdata_i[7]_i_8_n_0\,
O => \s_axi_rdata_i_reg[7]_1\
);
\s_axi_rdata_i[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088008833300030"
)
port map (
I0 => \^s_axi_rdata_i_reg[8]\(7),
I1 => \bus2ip_addr_i_reg[6]\(2),
I2 => \^dtre_d1_reg\(2),
I3 => \bus2ip_addr_i_reg[6]\(4),
I4 => timing_param_thddat_i(7),
I5 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i_reg[7]_0\
);
\s_axi_rdata_i[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => Cr(0),
I1 => \bus2ip_addr_i_reg[6]\(4),
I2 => timing_param_tlow_i(7),
I3 => \bus2ip_addr_i_reg[6]\(3),
O => \s_axi_rdata_i[7]_i_8_n_0\
);
\s_axi_rdata_i[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => timing_param_tbuf_i(8),
I1 => timing_param_tsusta_i(8),
I2 => \bus2ip_addr_i_reg[6]\(1),
I3 => timing_param_thdsta_i(8),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => timing_param_tlow_i(8),
O => \s_axi_rdata_i[8]_i_3_n_0\
);
\s_axi_rdata_i[8]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => timing_param_thigh_i(8),
I1 => timing_param_tsusto_i(8),
I2 => \bus2ip_addr_i_reg[6]\(1),
I3 => \^s_axi_rdata_i_reg[8]\(8),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => timing_param_thddat_i(8),
O => \s_axi_rdata_i[8]_i_4_n_0\
);
\s_axi_rdata_i[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => timing_param_tbuf_i(9),
I1 => timing_param_tsusta_i(9),
I2 => \bus2ip_addr_i_reg[6]\(1),
I3 => timing_param_thdsta_i(9),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => timing_param_tlow_i(9),
O => \s_axi_rdata_i[9]_i_4_n_0\
);
\s_axi_rdata_i[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => timing_param_thigh_i(9),
I1 => timing_param_tsusto_i(9),
I2 => \bus2ip_addr_i_reg[6]\(1),
I3 => timing_param_tsudat_i(9),
I4 => \bus2ip_addr_i_reg[6]\(2),
I5 => timing_param_thddat_i(9),
O => \s_axi_rdata_i[9]_i_5_n_0\
);
\s_axi_rdata_i_reg[8]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \s_axi_rdata_i[8]_i_3_n_0\,
I1 => \s_axi_rdata_i[8]_i_4_n_0\,
O => \s_axi_rdata_i_reg[8]_0\,
S => \bus2ip_addr_i_reg[6]\(0)
);
\s_axi_rdata_i_reg[9]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \s_axi_rdata_i[9]_i_4_n_0\,
I1 => \s_axi_rdata_i[9]_i_5_n_0\,
O => \s_axi_rdata_i_reg[9]\,
S => \bus2ip_addr_i_reg[6]\(0)
);
slave_sda_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"55555514"
)
port map (
I0 => Data_Exists_DFF_3(0),
I1 => \data_int_reg[7]\(7),
I2 => adr_i(7),
I3 => slave_sda_i_3_n_0,
I4 => slave_sda_i_4_n_0,
O => \^slave_sda_reg\
);
slave_sda_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => adr_i(4),
I1 => \data_int_reg[7]\(4),
I2 => \data_int_reg[7]\(5),
I3 => adr_i(5),
I4 => \data_int_reg[7]\(6),
I5 => adr_i(6),
O => slave_sda_i_3_n_0
);
slave_sda_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => adr_i(1),
I1 => \data_int_reg[7]\(1),
I2 => \data_int_reg[7]\(3),
I3 => adr_i(3),
I4 => \data_int_reg[7]\(2),
I5 => adr_i(2),
O => slave_sda_i_4_n_0
);
\sr_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Data_Exists_DFF_1,
Q => \^dtre_d1_reg\(2),
R => Bus2IIC_Reset
);
\sr_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Data_Exists_DFF_3(5),
Q => sr_i(1),
R => Bus2IIC_Reset
);
\sr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Data_Exists_DFF_3(4),
Q => \^dtre_d1_reg\(1),
R => Bus2IIC_Reset
);
\sr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Data_Exists_DFF_3(3),
Q => \^dtre_d1_reg\(0),
R => Bus2IIC_Reset
);
\sr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Data_Exists_DFF_3(2),
Q => sr_i(4),
R => Bus2IIC_Reset
);
\sr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Data_Exists_DFF_3(1),
Q => sr_i(5),
R => Bus2IIC_Reset
);
\sr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Data_Exists_DFF_3(0),
Q => sr_i(7),
R => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(0),
Q => timing_param_tbuf_i(0),
R => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(1),
Q => timing_param_tbuf_i(1),
R => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(2),
Q => timing_param_tbuf_i(2),
S => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(3),
Q => timing_param_tbuf_i(3),
R => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(4),
Q => \^fsm_sequential_scl_state_reg[3]_0\(0),
S => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(5),
Q => \^fsm_sequential_scl_state_reg[3]_0\(1),
S => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[6]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(6),
Q => \^fsm_sequential_scl_state_reg[3]_0\(2),
S => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[7]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(7),
Q => \^fsm_sequential_scl_state_reg[3]_0\(3),
S => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[8]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(8),
Q => timing_param_tbuf_i(8),
S => Bus2IIC_Reset
);
\timing_param_tbuf_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(3),
D => s_axi_wdata(9),
Q => timing_param_tbuf_i(9),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(0),
Q => timing_param_thddat_i(0),
S => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(1),
Q => timing_param_thddat_i(1),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(2),
Q => timing_param_thddat_i(2),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(3),
Q => timing_param_thddat_i(3),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(4),
Q => \^s_axi_rdata_i_reg[5]\(0),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(5),
Q => \^s_axi_rdata_i_reg[5]\(1),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(6),
Q => timing_param_thddat_i(6),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(7),
Q => timing_param_thddat_i(7),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(8),
Q => timing_param_thddat_i(8),
R => Bus2IIC_Reset
);
\timing_param_thddat_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(0),
D => s_axi_wdata(9),
Q => timing_param_thddat_i(9),
R => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(0),
Q => \^fsm_sequential_scl_state_reg[2]_0\(0),
R => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(1),
Q => timing_param_thdsta_i(1),
S => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(2),
Q => timing_param_thdsta_i(2),
S => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(3),
Q => timing_param_thdsta_i(3),
S => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(4),
Q => timing_param_thdsta_i(4),
R => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(5),
Q => timing_param_thdsta_i(5),
S => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(6),
Q => timing_param_thdsta_i(6),
R => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[7]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(7),
Q => timing_param_thdsta_i(7),
S => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[8]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(8),
Q => timing_param_thdsta_i(8),
S => Bus2IIC_Reset
);
\timing_param_thdsta_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(5),
D => s_axi_wdata(9),
Q => timing_param_thdsta_i(9),
R => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(0),
Q => \^fsm_sequential_scl_state_reg[0]\(0),
S => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(1),
Q => \^fsm_sequential_scl_state_reg[0]\(1),
R => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(2),
Q => \^fsm_sequential_scl_state_reg[0]\(2),
S => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(3),
Q => \^fsm_sequential_scl_state_reg[0]\(3),
S => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(4),
Q => \^fsm_sequential_scl_state_reg[0]\(4),
R => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(5),
Q => \^fsm_sequential_scl_state_reg[0]\(5),
S => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[6]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(6),
Q => \^fsm_sequential_scl_state_reg[0]\(6),
S => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[7]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(7),
Q => \^fsm_sequential_scl_state_reg[0]\(7),
S => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[8]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(8),
Q => timing_param_thigh_i(8),
S => Bus2IIC_Reset
);
\timing_param_thigh_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(2),
D => s_axi_wdata(9),
Q => timing_param_thigh_i(9),
R => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(0),
Q => \^fsm_sequential_scl_state_reg[1]_0\(0),
S => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(1),
Q => timing_param_tlow_i(1),
R => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(2),
Q => timing_param_tlow_i(2),
S => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(3),
Q => timing_param_tlow_i(3),
S => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(4),
Q => timing_param_tlow_i(4),
R => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(5),
Q => timing_param_tlow_i(5),
S => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[6]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(6),
Q => timing_param_tlow_i(6),
S => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[7]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(7),
Q => timing_param_tlow_i(7),
S => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[8]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(8),
Q => timing_param_tlow_i(8),
S => Bus2IIC_Reset
);
\timing_param_tlow_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(1),
D => s_axi_wdata(9),
Q => timing_param_tlow_i(9),
R => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(0),
Q => \^s_axi_rdata_i_reg[8]\(0),
S => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(1),
Q => \^s_axi_rdata_i_reg[8]\(1),
S => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(2),
Q => \^s_axi_rdata_i_reg[8]\(2),
S => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(3),
Q => \^s_axi_rdata_i_reg[8]\(3),
R => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(4),
Q => \^s_axi_rdata_i_reg[8]\(4),
S => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(5),
Q => \^s_axi_rdata_i_reg[8]\(5),
S => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(6),
Q => \^s_axi_rdata_i_reg[8]\(6),
R => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(7),
Q => \^s_axi_rdata_i_reg[8]\(7),
R => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(8),
Q => \^s_axi_rdata_i_reg[8]\(8),
R => Bus2IIC_Reset
);
\timing_param_tsudat_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(4),
D => s_axi_wdata(9),
Q => timing_param_tsudat_i(9),
R => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(0),
Q => timing_param_tsusta_i(0),
R => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(1),
Q => timing_param_tsusta_i(1),
S => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(2),
Q => timing_param_tsusta_i(2),
R => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(3),
Q => timing_param_tsusta_i(3),
S => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(4),
Q => \^s_axi_rdata_i_reg[7]\(0),
S => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(5),
Q => \^s_axi_rdata_i_reg[7]\(1),
S => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(6),
Q => \^s_axi_rdata_i_reg[7]\(2),
R => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(7),
Q => \^s_axi_rdata_i_reg[7]\(3),
R => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(8),
Q => timing_param_tsusta_i(8),
R => Bus2IIC_Reset
);
\timing_param_tsusta_i_reg[9]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(7),
D => s_axi_wdata(9),
Q => timing_param_tsusta_i(9),
S => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(0),
Q => \^sda_cout_reg_reg_0\(0),
R => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(1),
Q => \^sda_cout_reg_reg_0\(1),
R => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(2),
Q => \^sda_cout_reg_reg_0\(2),
S => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(3),
Q => \^sda_cout_reg_reg_0\(3),
R => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(4),
Q => \^sda_cout_reg_reg_0\(4),
S => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(5),
Q => \^sda_cout_reg_reg_0\(5),
S => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[6]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(6),
Q => \^sda_cout_reg_reg_0\(6),
S => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[7]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(7),
Q => \^sda_cout_reg_reg_0\(7),
S => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[8]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(8),
Q => timing_param_tsusto_i(8),
S => Bus2IIC_Reset
);
\timing_param_tsusto_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus2IIC_WrCE(6),
D => s_axi_wdata(9),
Q => timing_param_tsusto_i(9),
R => Bus2IIC_Reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_shift8 is
port (
\LEVEL_1_GEN.master_sda_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
slave_sda_reg : out STD_LOGIC;
shift_reg_en : in STD_LOGIC;
shift_reg_ld_reg : in STD_LOGIC;
txak : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_under_prev_i_reg : in STD_LOGIC;
abgc_i_reg : in STD_LOGIC;
Tx_fifo_data : in STD_LOGIC_VECTOR ( 6 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
shift_reg_ld_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_shift8 : entity is "shift8";
end system_axi_iic_0_0_shift8;
architecture STRUCTURE of system_axi_iic_0_0_shift8 is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \data_int[1]_i_1_n_0\ : STD_LOGIC;
signal \data_int[2]_i_1_n_0\ : STD_LOGIC;
signal \data_int[3]_i_1_n_0\ : STD_LOGIC;
signal \data_int[4]_i_1_n_0\ : STD_LOGIC;
signal \data_int[5]_i_1_n_0\ : STD_LOGIC;
signal \data_int[6]_i_1_n_0\ : STD_LOGIC;
signal \data_int[7]_i_1_n_0\ : STD_LOGIC;
signal \data_int[7]_i_2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \data_int[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_int[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_int[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_int[5]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_int[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_int[7]_i_2\ : label is "soft_lutpair9";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\LEVEL_1_GEN.master_sda_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB0F0BFFFB000B"
)
port map (
I0 => txak,
I1 => \out\(3),
I2 => \out\(0),
I3 => \out\(2),
I4 => \^q\(7),
I5 => tx_under_prev_i_reg,
O => \LEVEL_1_GEN.master_sda_reg\
);
\data_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Tx_fifo_data(0),
I1 => shift_reg_ld_reg,
I2 => \^q\(0),
O => \data_int[1]_i_1_n_0\
);
\data_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Tx_fifo_data(1),
I1 => shift_reg_ld_reg,
I2 => \^q\(1),
O => \data_int[2]_i_1_n_0\
);
\data_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Tx_fifo_data(2),
I1 => shift_reg_ld_reg,
I2 => \^q\(2),
O => \data_int[3]_i_1_n_0\
);
\data_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Tx_fifo_data(3),
I1 => shift_reg_ld_reg,
I2 => \^q\(3),
O => \data_int[4]_i_1_n_0\
);
\data_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Tx_fifo_data(4),
I1 => shift_reg_ld_reg,
I2 => \^q\(4),
O => \data_int[5]_i_1_n_0\
);
\data_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Tx_fifo_data(5),
I1 => shift_reg_ld_reg,
I2 => \^q\(5),
O => \data_int[6]_i_1_n_0\
);
\data_int[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => shift_reg_en,
I1 => shift_reg_ld_reg,
O => \data_int[7]_i_1_n_0\
);
\data_int[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Tx_fifo_data(6),
I1 => shift_reg_ld_reg,
I2 => \^q\(6),
O => \data_int[7]_i_2_n_0\
);
\data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \data_int[7]_i_1_n_0\,
D => shift_reg_ld_reg_0(0),
Q => \^q\(0),
R => SR(0)
);
\data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \data_int[7]_i_1_n_0\,
D => \data_int[1]_i_1_n_0\,
Q => \^q\(1),
R => SR(0)
);
\data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \data_int[7]_i_1_n_0\,
D => \data_int[2]_i_1_n_0\,
Q => \^q\(2),
R => SR(0)
);
\data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \data_int[7]_i_1_n_0\,
D => \data_int[3]_i_1_n_0\,
Q => \^q\(3),
R => SR(0)
);
\data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \data_int[7]_i_1_n_0\,
D => \data_int[4]_i_1_n_0\,
Q => \^q\(4),
R => SR(0)
);
\data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \data_int[7]_i_1_n_0\,
D => \data_int[5]_i_1_n_0\,
Q => \^q\(5),
R => SR(0)
);
\data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \data_int[7]_i_1_n_0\,
D => \data_int[6]_i_1_n_0\,
Q => \^q\(6),
R => SR(0)
);
\data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \data_int[7]_i_1_n_0\,
D => \data_int[7]_i_2_n_0\,
Q => \^q\(7),
R => SR(0)
);
slave_sda_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFBFB0B000B0B"
)
port map (
I0 => \^q\(7),
I1 => \out\(2),
I2 => \out\(3),
I3 => abgc_i_reg,
I4 => \out\(1),
I5 => txak,
O => slave_sda_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_shift8_1 is
port (
D : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
shift_reg_ld0 : out STD_LOGIC;
abgc_i_reg : out STD_LOGIC;
srw_i_reg : out STD_LOGIC;
\RD_FIFO_CNTRL.ro_prev_i_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
arb_lost_reg : in STD_LOGIC;
sda_sample : in STD_LOGIC;
abgc_i_reg_0 : in STD_LOGIC;
master_slave_reg : in STD_LOGIC;
\cr_i_reg[1]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\FSM_onehot_state_reg[6]\ : in STD_LOGIC;
srw_i_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
detect_start : in STD_LOGIC;
detect_stop_reg : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
scndry_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_shift8_1 : entity is "shift8";
end system_axi_iic_0_0_shift8_1;
architecture STRUCTURE of system_axi_iic_0_0_shift8_1 is
signal \FSM_onehot_state[3]_i_3_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal abgc_i_i_2_n_0 : STD_LOGIC;
signal abgc_i_i_3_n_0 : STD_LOGIC;
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E2"
)
port map (
I0 => \RD_FIFO_CNTRL.ro_prev_i_reg\,
I1 => \out\(2),
I2 => \FSM_onehot_state[3]_i_3_n_0\,
I3 => \out\(1),
I4 => \out\(0),
O => D(0)
);
\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000111110001"
)
port map (
I0 => arb_lost_reg,
I1 => sda_sample,
I2 => abgc_i_reg_0,
I3 => \^q\(0),
I4 => master_slave_reg,
I5 => \cr_i_reg[1]\(1),
O => \FSM_onehot_state[3]_i_3_n_0\
);
abgc_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000AE0000"
)
port map (
I0 => srw_i_reg_0(0),
I1 => abgc_i_i_2_n_0,
I2 => abgc_i_i_3_n_0,
I3 => detect_start,
I4 => \cr_i_reg[1]\(0),
I5 => detect_stop_reg,
O => abgc_i_reg
);
abgc_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(7),
I1 => \^q\(0),
I2 => \^q\(6),
I3 => \^q\(1),
O => abgc_i_i_2_n_0
);
abgc_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFDFFFFFFFF"
)
port map (
I0 => \out\(2),
I1 => \^q\(5),
I2 => \^q\(2),
I3 => \^q\(3),
I4 => \^q\(4),
I5 => \cr_i_reg[1]\(2),
O => abgc_i_i_3_n_0
);
\data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => scndry_out,
Q => \^q\(0),
R => SR(0)
);
\data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(0),
Q => \^q\(1),
R => SR(0)
);
\data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(1),
Q => \^q\(2),
R => SR(0)
);
\data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(2),
Q => \^q\(3),
R => SR(0)
);
\data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(3),
Q => \^q\(4),
R => SR(0)
);
\data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(4),
Q => \^q\(5),
R => SR(0)
);
\data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(5),
Q => \^q\(6),
R => SR(0)
);
\data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(6),
Q => \^q\(7),
R => SR(0)
);
shift_reg_ld_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFB800"
)
port map (
I0 => \cr_i_reg[1]\(1),
I1 => master_slave_reg,
I2 => \^q\(0),
I3 => \out\(2),
I4 => \FSM_onehot_state_reg[6]\,
O => shift_reg_ld0
);
srw_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"E200"
)
port map (
I0 => srw_i_reg_0(1),
I1 => \out\(2),
I2 => \^q\(0),
I3 => \cr_i_reg[1]\(0),
O => srw_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_soft_reset is
port (
sw_rst_cond_d1 : out STD_LOGIC;
AXI_Bus2IP_Reset : out STD_LOGIC;
ctrlFifoDin : out STD_LOGIC_VECTOR ( 0 to 1 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
sw_rst_cond : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_trig0 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
Tx_fifo_rst : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_soft_reset : entity is "soft_reset";
end system_axi_iic_0_0_soft_reset;
architecture STRUCTURE of system_axi_iic_0_0_soft_reset is
signal \^axi_bus2ip_reset\ : STD_LOGIC;
signal \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[3].RST_FLOPS_n_0\ : STD_LOGIC;
signal S : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal flop_q_chain : STD_LOGIC_VECTOR ( 1 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute box_type : string;
attribute box_type of \RESET_FLOPS[0].RST_FLOPS\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[1].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[1].RST_FLOPS_i_1\ : label is "soft_lutpair54";
attribute IS_CE_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[2].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[2].RST_FLOPS_i_1\ : label is "soft_lutpair54";
attribute IS_CE_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[3].RST_FLOPS\ : label is "PRIMITIVE";
begin
AXI_Bus2IP_Reset <= \^axi_bus2ip_reset\;
SR(0) <= \^sr\(0);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^sr\(0),
I2 => Tx_fifo_rst,
O => ctrlFifoDin(0)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^sr\(0),
I2 => Tx_fifo_rst,
O => ctrlFifoDin(1)
);
\GPO_GEN.gpo_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \RESET_FLOPS[3].RST_FLOPS_n_0\,
I1 => s_axi_aresetn,
O => \^sr\(0)
);
\RESET_FLOPS[0].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => S,
Q => flop_q_chain(1),
R => \^axi_bus2ip_reset\
);
\RESET_FLOPS[1].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(2),
R => \^axi_bus2ip_reset\
);
\RESET_FLOPS[1].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(1),
O => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[2].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(3),
R => \^axi_bus2ip_reset\
);
\RESET_FLOPS[2].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(2),
O => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[3].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\,
Q => \RESET_FLOPS[3].RST_FLOPS_n_0\,
R => \^axi_bus2ip_reset\
);
\RESET_FLOPS[3].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(3),
O => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\
);
reset_trig_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => reset_trig0,
Q => S,
R => \^axi_bus2ip_reset\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^axi_bus2ip_reset\
);
sw_rst_cond_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => sw_rst_cond,
Q => sw_rst_cond_d1,
R => \^axi_bus2ip_reset\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_upcnt_n is
port (
\q_int_reg[0]_0\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
detect_stop_b_reg : in STD_LOGIC;
stop_scl_reg_reg : in STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC;
\timing_param_thddat_i_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_upcnt_n : entity is "upcnt_n";
end system_axi_iic_0_0_upcnt_n;
architecture STRUCTURE of system_axi_iic_0_0_upcnt_n is
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \q_int[0]_i_10_n_0\ : STD_LOGIC;
signal \q_int[0]_i_1_n_0\ : STD_LOGIC;
signal \q_int[0]_i_3_n_0\ : STD_LOGIC;
signal \q_int[0]_i_4_n_0\ : STD_LOGIC;
signal \q_int[0]_i_5__0_n_0\ : STD_LOGIC;
signal \q_int[0]_i_7_n_0\ : STD_LOGIC;
signal \q_int[0]_i_8_n_0\ : STD_LOGIC;
signal \q_int[0]_i_9_n_0\ : STD_LOGIC;
signal \q_int[1]_i_1__0_n_0\ : STD_LOGIC;
signal \q_int[1]_i_2_n_0\ : STD_LOGIC;
signal \q_int[1]_i_3_n_0\ : STD_LOGIC;
signal \q_int[1]_i_4_n_0\ : STD_LOGIC;
signal \q_int[1]_i_5_n_0\ : STD_LOGIC;
signal \q_int[2]_i_1__0_n_0\ : STD_LOGIC;
signal \q_int[2]_i_2_n_0\ : STD_LOGIC;
signal \q_int[3]_i_1__0_n_0\ : STD_LOGIC;
signal \q_int[3]_i_2_n_0\ : STD_LOGIC;
signal \q_int[4]_i_1_n_0\ : STD_LOGIC;
signal \q_int[4]_i_2_n_0\ : STD_LOGIC;
signal \q_int[5]_i_1__0_n_0\ : STD_LOGIC;
signal \q_int[5]_i_2_n_0\ : STD_LOGIC;
signal \q_int[6]_i_1__0_n_0\ : STD_LOGIC;
signal \q_int[6]_i_2_n_0\ : STD_LOGIC;
signal \q_int[7]_i_1__0_n_0\ : STD_LOGIC;
signal \q_int[7]_i_2_n_0\ : STD_LOGIC;
signal \^q_int_reg[0]_0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[0]_i_10\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \q_int[0]_i_5__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \q_int[0]_i_9\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \q_int[1]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \q_int[1]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \q_int[1]_i_5\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \q_int[5]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \q_int[6]_i_2\ : label is "soft_lutpair7";
begin
\q_int_reg[0]_0\(9 downto 0) <= \^q_int_reg[0]_0\(9 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEFEFEEEEFFEFFE"
)
port map (
I0 => \q_int[0]_i_3_n_0\,
I1 => \q_int[0]_i_4_n_0\,
I2 => \out\(3),
I3 => \out\(1),
I4 => \out\(0),
I5 => \out\(2),
O => \q_int[0]_i_1_n_0\
);
\q_int[0]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"0B"
)
port map (
I0 => CO(0),
I1 => detect_stop_b_reg,
I2 => \out\(0),
O => \q_int[0]_i_10_n_0\
);
\q_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2222202222222002"
)
port map (
I0 => \q_int[0]_i_5__0_n_0\,
I1 => \q_int[0]_i_4_n_0\,
I2 => \out\(3),
I3 => \out\(1),
I4 => \out\(0),
I5 => \out\(2),
O => \p_0_in__0\(9)
);
\q_int[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF040C"
)
port map (
I0 => stop_scl_reg_reg,
I1 => \out\(0),
I2 => \out\(3),
I3 => \out\(2),
I4 => \q_int[0]_i_7_n_0\,
I5 => \q_int[0]_i_8_n_0\,
O => \q_int[0]_i_3_n_0\
);
\q_int[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFAEAAAEAAAEAAAE"
)
port map (
I0 => \q_int[0]_i_9_n_0\,
I1 => \q_int[0]_i_10_n_0\,
I2 => \out\(3),
I3 => \out\(2),
I4 => \out\(1),
I5 => stop_scl_reg_reg,
O => \q_int[0]_i_4_n_0\
);
\q_int[0]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA6AAA"
)
port map (
I0 => \^q_int_reg[0]_0\(9),
I1 => \^q_int_reg[0]_0\(8),
I2 => \^q_int_reg[0]_0\(7),
I3 => \^q_int_reg[0]_0\(6),
I4 => \q_int[3]_i_2_n_0\,
O => \q_int[0]_i_5__0_n_0\
);
\q_int[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => \out\(1),
I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
I2 => \timing_param_thddat_i_reg[9]\(0),
I3 => \out\(3),
I4 => \out\(2),
O => \q_int[0]_i_7_n_0\
);
\q_int[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \out\(1),
I1 => detect_stop_b_reg,
I2 => CO(0),
I3 => \out\(3),
I4 => \out\(2),
O => \q_int[0]_i_8_n_0\
);
\q_int[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00540000"
)
port map (
I0 => \out\(0),
I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
I2 => \timing_param_thddat_i_reg[9]\(0),
I3 => \out\(3),
I4 => \out\(2),
O => \q_int[0]_i_9_n_0\
);
\q_int[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000011101110000"
)
port map (
I0 => \q_int[0]_i_4_n_0\,
I1 => \q_int[1]_i_2_n_0\,
I2 => \q_int[1]_i_3_n_0\,
I3 => \q_int[1]_i_4_n_0\,
I4 => \q_int[1]_i_5_n_0\,
I5 => \^q_int_reg[0]_0\(8),
O => \q_int[1]_i_1__0_n_0\
);
\q_int[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \out\(0),
I1 => \out\(1),
I2 => \out\(3),
O => \q_int[1]_i_2_n_0\
);
\q_int[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \out\(3),
I1 => \out\(2),
O => \q_int[1]_i_3_n_0\
);
\q_int[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \out\(0),
I1 => \out\(1),
O => \q_int[1]_i_4_n_0\
);
\q_int[1]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q_int_reg[0]_0\(7),
I1 => \^q_int_reg[0]_0\(6),
I2 => \q_int[3]_i_2_n_0\,
O => \q_int[1]_i_5_n_0\
);
\q_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0111000000000111"
)
port map (
I0 => \q_int[0]_i_4_n_0\,
I1 => \q_int[1]_i_2_n_0\,
I2 => \q_int[1]_i_3_n_0\,
I3 => \q_int[1]_i_4_n_0\,
I4 => \q_int[2]_i_2_n_0\,
I5 => \^q_int_reg[0]_0\(7),
O => \q_int[2]_i_1__0_n_0\
);
\q_int[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \q_int[3]_i_2_n_0\,
I1 => \^q_int_reg[0]_0\(6),
O => \q_int[2]_i_2_n_0\
);
\q_int[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0111000000000111"
)
port map (
I0 => \q_int[0]_i_4_n_0\,
I1 => \q_int[1]_i_2_n_0\,
I2 => \q_int[1]_i_3_n_0\,
I3 => \q_int[1]_i_4_n_0\,
I4 => \q_int[3]_i_2_n_0\,
I5 => \^q_int_reg[0]_0\(6),
O => \q_int[3]_i_1__0_n_0\
);
\q_int[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q_int_reg[0]_0\(4),
I1 => \^q_int_reg[0]_0\(2),
I2 => \^q_int_reg[0]_0\(0),
I3 => \^q_int_reg[0]_0\(1),
I4 => \^q_int_reg[0]_0\(3),
I5 => \^q_int_reg[0]_0\(5),
O => \q_int[3]_i_2_n_0\
);
\q_int[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055455541"
)
port map (
I0 => \q_int[0]_i_4_n_0\,
I1 => \out\(3),
I2 => \out\(1),
I3 => \out\(0),
I4 => \out\(2),
I5 => \q_int[4]_i_2_n_0\,
O => \q_int[4]_i_1_n_0\
);
\q_int[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9555555555555555"
)
port map (
I0 => \^q_int_reg[0]_0\(5),
I1 => \^q_int_reg[0]_0\(4),
I2 => \^q_int_reg[0]_0\(2),
I3 => \^q_int_reg[0]_0\(0),
I4 => \^q_int_reg[0]_0\(1),
I5 => \^q_int_reg[0]_0\(3),
O => \q_int[4]_i_2_n_0\
);
\q_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055455541"
)
port map (
I0 => \q_int[0]_i_4_n_0\,
I1 => \out\(3),
I2 => \out\(1),
I3 => \out\(0),
I4 => \out\(2),
I5 => \q_int[5]_i_2_n_0\,
O => \q_int[5]_i_1__0_n_0\
);
\q_int[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"95555555"
)
port map (
I0 => \^q_int_reg[0]_0\(4),
I1 => \^q_int_reg[0]_0\(3),
I2 => \^q_int_reg[0]_0\(1),
I3 => \^q_int_reg[0]_0\(0),
I4 => \^q_int_reg[0]_0\(2),
O => \q_int[5]_i_2_n_0\
);
\q_int[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055455541"
)
port map (
I0 => \q_int[0]_i_4_n_0\,
I1 => \out\(3),
I2 => \out\(1),
I3 => \out\(0),
I4 => \out\(2),
I5 => \q_int[6]_i_2_n_0\,
O => \q_int[6]_i_1__0_n_0\
);
\q_int[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \^q_int_reg[0]_0\(3),
I1 => \^q_int_reg[0]_0\(2),
I2 => \^q_int_reg[0]_0\(0),
I3 => \^q_int_reg[0]_0\(1),
O => \q_int[6]_i_2_n_0\
);
\q_int[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055455541"
)
port map (
I0 => \q_int[0]_i_4_n_0\,
I1 => \out\(3),
I2 => \out\(1),
I3 => \out\(0),
I4 => \out\(2),
I5 => \q_int[7]_i_2_n_0\,
O => \q_int[7]_i_1__0_n_0\
);
\q_int[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"95"
)
port map (
I0 => \^q_int_reg[0]_0\(2),
I1 => \^q_int_reg[0]_0\(1),
I2 => \^q_int_reg[0]_0\(0),
O => \q_int[7]_i_2_n_0\
);
\q_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000600060006"
)
port map (
I0 => \^q_int_reg[0]_0\(1),
I1 => \^q_int_reg[0]_0\(0),
I2 => \q_int[0]_i_4_n_0\,
I3 => \q_int[1]_i_2_n_0\,
I4 => \q_int[1]_i_3_n_0\,
I5 => \q_int[1]_i_4_n_0\,
O => \p_0_in__0\(1)
);
\q_int[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055455541"
)
port map (
I0 => \q_int[0]_i_4_n_0\,
I1 => \out\(3),
I2 => \out\(1),
I3 => \out\(0),
I4 => \out\(2),
I5 => \^q_int_reg[0]_0\(0),
O => \p_0_in__0\(0)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \p_0_in__0\(9),
Q => \^q_int_reg[0]_0\(9),
R => SR(0)
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \q_int[1]_i_1__0_n_0\,
Q => \^q_int_reg[0]_0\(8),
R => SR(0)
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \q_int[2]_i_1__0_n_0\,
Q => \^q_int_reg[0]_0\(7),
R => SR(0)
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \q_int[3]_i_1__0_n_0\,
Q => \^q_int_reg[0]_0\(6),
R => SR(0)
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \q_int[4]_i_1_n_0\,
Q => \^q_int_reg[0]_0\(5),
R => SR(0)
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \q_int[5]_i_1__0_n_0\,
Q => \^q_int_reg[0]_0\(4),
R => SR(0)
);
\q_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \q_int[6]_i_1__0_n_0\,
Q => \^q_int_reg[0]_0\(3),
R => SR(0)
);
\q_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \q_int[7]_i_1__0_n_0\,
Q => \^q_int_reg[0]_0\(2),
R => SR(0)
);
\q_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \p_0_in__0\(1),
Q => \^q_int_reg[0]_0\(1),
R => SR(0)
);
\q_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1_n_0\,
D => \p_0_in__0\(0),
Q => \^q_int_reg[0]_0\(0),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_upcnt_n_2 is
port (
\q_int_reg[1]_0\ : out STD_LOGIC;
\q_int_reg[0]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
S : out STD_LOGIC_VECTOR ( 0 to 0 );
sda_setup : in STD_LOGIC;
sda_rin_d1_reg : in STD_LOGIC;
scndry_out : in STD_LOGIC;
rsta_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_under_prev_d1 : in STD_LOGIC;
tx_under_prev_i_reg : in STD_LOGIC;
gen_stop : in STD_LOGIC;
gen_stop_d1 : in STD_LOGIC;
\timing_param_tsudat_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_upcnt_n_2 : entity is "upcnt_n";
end system_axi_iic_0_0_upcnt_n_2;
architecture STRUCTURE of system_axi_iic_0_0_upcnt_n_2 is
signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \q_int[0]_i_1__0_n_0\ : STD_LOGIC;
signal \q_int[0]_i_4__0_n_0\ : STD_LOGIC;
signal \q_int[0]_i_5_n_0\ : STD_LOGIC;
signal \q_int[1]_i_1__1_n_0\ : STD_LOGIC;
signal \q_int[2]_i_1__1_n_0\ : STD_LOGIC;
signal \q_int[3]_i_1__1_n_0\ : STD_LOGIC;
signal \q_int[4]_i_1__0_n_0\ : STD_LOGIC;
signal \q_int[4]_i_2__0_n_0\ : STD_LOGIC;
signal \^q_int_reg[0]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^q_int_reg[1]_0\ : STD_LOGIC;
signal \q_int_reg__0\ : STD_LOGIC_VECTOR ( 1 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \q_int[2]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \q_int[3]_i_1__1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \q_int[4]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \q_int[6]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \q_int[7]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \q_int[8]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \q_int[9]_i_1__0\ : label is "soft_lutpair15";
begin
\q_int_reg[0]_0\(6 downto 0) <= \^q_int_reg[0]_0\(6 downto 0);
\q_int_reg[1]_0\ <= \^q_int_reg[1]_0\;
\i__carry_i_2__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \q_int_reg__0\(1),
I1 => \timing_param_tsudat_i_reg[8]\(2),
I2 => \q_int_reg__0\(3),
I3 => \timing_param_tsudat_i_reg[8]\(0),
I4 => \timing_param_tsudat_i_reg[8]\(1),
I5 => \q_int_reg__0\(2),
O => S(0)
);
\q_int[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sda_setup,
I1 => \^q_int_reg[1]_0\,
O => \q_int[0]_i_1__0_n_0\
);
\q_int[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BFFF4000"
)
port map (
I0 => \q_int[0]_i_4__0_n_0\,
I1 => \q_int_reg__0\(3),
I2 => \q_int_reg__0\(2),
I3 => \q_int_reg__0\(1),
I4 => \^q_int_reg[0]_0\(6),
I5 => \^q_int_reg[1]_0\,
O => \p_0_in__1\(9)
);
\q_int[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F6"
)
port map (
I0 => sda_rin_d1_reg,
I1 => scndry_out,
I2 => \q_int[0]_i_5_n_0\,
O => \^q_int_reg[1]_0\
);
\q_int[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q_int_reg[0]_0\(4),
I1 => \^q_int_reg[0]_0\(2),
I2 => \^q_int_reg[0]_0\(0),
I3 => \^q_int_reg[0]_0\(1),
I4 => \^q_int_reg[0]_0\(3),
I5 => \^q_int_reg[0]_0\(5),
O => \q_int[0]_i_4__0_n_0\
);
\q_int[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => rsta_d1,
I1 => Q(0),
I2 => tx_under_prev_d1,
I3 => tx_under_prev_i_reg,
I4 => gen_stop,
I5 => gen_stop_d1,
O => \q_int[0]_i_5_n_0\
);
\q_int[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"55150040"
)
port map (
I0 => \^q_int_reg[1]_0\,
I1 => \q_int_reg__0\(2),
I2 => \q_int_reg__0\(3),
I3 => \q_int[0]_i_4__0_n_0\,
I4 => \q_int_reg__0\(1),
O => \q_int[1]_i_1__1_n_0\
);
\q_int[2]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4510"
)
port map (
I0 => \^q_int_reg[1]_0\,
I1 => \q_int[0]_i_4__0_n_0\,
I2 => \q_int_reg__0\(3),
I3 => \q_int_reg__0\(2),
O => \q_int[2]_i_1__1_n_0\
);
\q_int[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \^q_int_reg[1]_0\,
I1 => \q_int[0]_i_4__0_n_0\,
I2 => \q_int_reg__0\(3),
O => \q_int[3]_i_1__1_n_0\
);
\q_int[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \^q_int_reg[1]_0\,
I1 => \q_int[4]_i_2__0_n_0\,
I2 => \^q_int_reg[0]_0\(5),
O => \q_int[4]_i_1__0_n_0\
);
\q_int[4]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \^q_int_reg[0]_0\(3),
I1 => \^q_int_reg[0]_0\(1),
I2 => \^q_int_reg[0]_0\(0),
I3 => \^q_int_reg[0]_0\(2),
I4 => \^q_int_reg[0]_0\(4),
O => \q_int[4]_i_2__0_n_0\
);
\q_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFF8000"
)
port map (
I0 => \^q_int_reg[0]_0\(2),
I1 => \^q_int_reg[0]_0\(0),
I2 => \^q_int_reg[0]_0\(1),
I3 => \^q_int_reg[0]_0\(3),
I4 => \^q_int_reg[0]_0\(4),
I5 => \^q_int_reg[1]_0\,
O => \p_0_in__1\(4)
);
\q_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007F80"
)
port map (
I0 => \^q_int_reg[0]_0\(1),
I1 => \^q_int_reg[0]_0\(0),
I2 => \^q_int_reg[0]_0\(2),
I3 => \^q_int_reg[0]_0\(3),
I4 => \^q_int_reg[1]_0\,
O => \p_0_in__1\(3)
);
\q_int[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => \^q_int_reg[0]_0\(0),
I1 => \^q_int_reg[0]_0\(1),
I2 => \^q_int_reg[0]_0\(2),
I3 => \^q_int_reg[1]_0\,
O => \p_0_in__1\(2)
);
\q_int[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => \^q_int_reg[0]_0\(1),
I1 => \^q_int_reg[0]_0\(0),
I2 => \^q_int_reg[1]_0\,
O => \p_0_in__1\(1)
);
\q_int[9]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q_int_reg[0]_0\(0),
I1 => \^q_int_reg[1]_0\,
O => \p_0_in__1\(0)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \p_0_in__1\(9),
Q => \^q_int_reg[0]_0\(6),
R => SR(0)
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \q_int[1]_i_1__1_n_0\,
Q => \q_int_reg__0\(1),
R => SR(0)
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \q_int[2]_i_1__1_n_0\,
Q => \q_int_reg__0\(2),
R => SR(0)
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \q_int[3]_i_1__1_n_0\,
Q => \q_int_reg__0\(3),
R => SR(0)
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \q_int[4]_i_1__0_n_0\,
Q => \^q_int_reg[0]_0\(5),
R => SR(0)
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \p_0_in__1\(4),
Q => \^q_int_reg[0]_0\(4),
R => SR(0)
);
\q_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \p_0_in__1\(3),
Q => \^q_int_reg[0]_0\(3),
R => SR(0)
);
\q_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \p_0_in__1\(2),
Q => \^q_int_reg[0]_0\(2),
R => SR(0)
);
\q_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \p_0_in__1\(1),
Q => \^q_int_reg[0]_0\(1),
R => SR(0)
);
\q_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__0_n_0\,
D => \p_0_in__1\(0),
Q => \^q_int_reg[0]_0\(0),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_iic_0_0_upcnt_n__parameterized0\ is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
EarlyAckDataState0 : out STD_LOGIC;
dtc_i_reg : out STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\FSM_onehot_state_reg[4]\ : in STD_LOGIC;
detect_start : in STD_LOGIC;
ro_prev_d1_reg : in STD_LOGIC;
bit_cnt_en : in STD_LOGIC;
scl_falling_edge : in STD_LOGIC;
dtc_i : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_iic_0_0_upcnt_n__parameterized0\ : entity is "upcnt_n";
end \system_axi_iic_0_0_upcnt_n__parameterized0\;
architecture STRUCTURE of \system_axi_iic_0_0_upcnt_n__parameterized0\ is
signal \FSM_onehot_state[6]_i_4_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[6]_i_7_n_0\ : STD_LOGIC;
signal bit_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \q_int[0]_i_1__1_n_0\ : STD_LOGIC;
signal \q_int[0]_i_3__1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_state[6]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \q_int[0]_i_2__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair4";
begin
EarlyAckDataState_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AEAAAAAAAAAAAAEA"
)
port map (
I0 => \out\(4),
I1 => \out\(3),
I2 => bit_cnt(3),
I3 => bit_cnt(2),
I4 => bit_cnt(0),
I5 => bit_cnt(1),
O => EarlyAckDataState0
);
\FSM_onehot_state[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FEEE"
)
port map (
I0 => \FSM_onehot_state[6]_i_4_n_0\,
I1 => \out\(2),
I2 => detect_start,
I3 => \out\(0),
I4 => ro_prev_d1_reg,
O => E(0)
);
\FSM_onehot_state[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFEFFFCFCFC"
)
port map (
I0 => \out\(1),
I1 => \out\(5),
I2 => \out\(4),
I3 => \FSM_onehot_state_reg[4]\,
I4 => detect_start,
I5 => \FSM_onehot_state[6]_i_7_n_0\,
O => \FSM_onehot_state[6]_i_4_n_0\
);
\FSM_onehot_state[6]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => bit_cnt(1),
I1 => bit_cnt(0),
I2 => bit_cnt(3),
I3 => bit_cnt(2),
O => \FSM_onehot_state[6]_i_7_n_0\
);
dtc_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FFFF00800000"
)
port map (
I0 => bit_cnt(2),
I1 => bit_cnt(0),
I2 => bit_cnt(1),
I3 => bit_cnt(3),
I4 => scl_falling_edge,
I5 => dtc_i,
O => dtc_i_reg
);
\q_int[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => bit_cnt_en,
I1 => detect_start,
I2 => \out\(0),
I3 => \out\(4),
I4 => \out\(5),
I5 => \out\(2),
O => \q_int[0]_i_1__1_n_0\
);
\q_int[0]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA8000"
)
port map (
I0 => \q_int[0]_i_3__1_n_0\,
I1 => bit_cnt(1),
I2 => bit_cnt(0),
I3 => bit_cnt(2),
I4 => bit_cnt(3),
O => p_0_in(3)
);
\q_int[0]_i_3__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \out\(2),
I1 => \out\(5),
I2 => \out\(4),
I3 => \out\(0),
I4 => detect_start,
O => \q_int[0]_i_3__1_n_0\
);
\q_int[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2A80"
)
port map (
I0 => \q_int[0]_i_3__1_n_0\,
I1 => bit_cnt(0),
I2 => bit_cnt(1),
I3 => bit_cnt(2),
O => p_0_in(2)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"28"
)
port map (
I0 => \q_int[0]_i_3__1_n_0\,
I1 => bit_cnt(0),
I2 => bit_cnt(1),
O => p_0_in(1)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => detect_start,
I1 => \out\(0),
I2 => \out\(4),
I3 => \out\(5),
I4 => \out\(2),
I5 => bit_cnt(0),
O => p_0_in(0)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__1_n_0\,
D => p_0_in(3),
Q => bit_cnt(3),
R => SR(0)
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__1_n_0\,
D => p_0_in(2),
Q => bit_cnt(2),
R => SR(0)
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__1_n_0\,
D => p_0_in(1),
Q => bit_cnt(1),
R => SR(0)
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \q_int[0]_i_1__1_n_0\,
D => p_0_in(0),
Q => bit_cnt(0),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_debounce is
port (
scl_rising_edge0 : out STD_LOGIC;
scl_rin_d1_reg : out STD_LOGIC;
scl_rin_d1 : in STD_LOGIC;
scl_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_debounce : entity is "debounce";
end system_axi_iic_0_0_debounce;
architecture STRUCTURE of system_axi_iic_0_0_debounce is
begin
INPUT_DOUBLE_REGS: entity work.system_axi_iic_0_0_cdc_sync_4
port map (
s_axi_aclk => s_axi_aclk,
scl_i => scl_i,
scl_rin_d1 => scl_rin_d1,
scl_rin_d1_reg => scl_rin_d1_reg,
scl_rising_edge0 => scl_rising_edge0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_debounce_3 is
port (
detect_stop_b_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
sda_rin_d1 : in STD_LOGIC;
sda_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_debounce_3 : entity is "debounce";
end system_axi_iic_0_0_debounce_3;
architecture STRUCTURE of system_axi_iic_0_0_debounce_3 is
begin
INPUT_DOUBLE_REGS: entity work.system_axi_iic_0_0_cdc_sync
port map (
detect_stop_b_reg => detect_stop_b_reg,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sda_i => sda_i,
sda_rin_d1 => sda_rin_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_iic_control is
port (
New_rcv_dta : out STD_LOGIC;
shift_reg_ld : out STD_LOGIC;
sda_rin_d1 : out STD_LOGIC;
scl_rin_d1 : out STD_LOGIC;
Tx_under_prev : out STD_LOGIC;
Bb : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
earlyAckHdr : out STD_LOGIC;
earlyAckDataState : out STD_LOGIC;
ackDataState : out STD_LOGIC;
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
sda_cout_reg_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_sequential_scl_state_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
rdy_new_xmt_i : out STD_LOGIC;
arb_lost : out STD_LOGIC;
stop_scl_reg : out STD_LOGIC;
master_slave : out STD_LOGIC;
Aas : out STD_LOGIC;
\sr_i_reg[4]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\q_int_reg[0]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\q_int_reg[0]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\RD_FIFO_CNTRL.Rc_fifo_wr_reg\ : out STD_LOGIC;
abgc_i_reg_0 : out STD_LOGIC_VECTOR ( 7 downto 0 );
sda_t : out STD_LOGIC;
\cr_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
scl_t : out STD_LOGIC;
rdCntrFrmTxFifo0 : out STD_LOGIC;
detect_stop_b_reg_0 : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\FSM_sequential_scl_state_reg[2]_0\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
scndry_out : in STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : in STD_LOGIC;
scl_rising_edge0 : in STD_LOGIC;
Ro_prev : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
sr_i : in STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsusto_i_reg[9]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsusta_i_reg[9]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tbuf_i_reg[9]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_thddat_i_reg[9]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_thdsta_i_reg[9]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tlow_i_reg[9]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsudat_i_reg[9]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
state122_out : in STD_LOGIC;
new_rcv_dta_d1 : in STD_LOGIC;
\cr_i_reg[4]\ : in STD_LOGIC;
abgc_i_reg_1 : in STD_LOGIC;
txak : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Data_Exists_DFF : in STD_LOGIC;
rxCntDone : in STD_LOGIC;
dynamic_MSMS : in STD_LOGIC_VECTOR ( 0 to 0 );
Tx_data_exists : in STD_LOGIC;
Tx_fifo_rd_d_reg : in STD_LOGIC;
\timing_param_tsudat_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Msms_set : in STD_LOGIC;
callingReadAccess : in STD_LOGIC;
Tx_fifo_data : in STD_LOGIC_VECTOR ( 6 downto 0 );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ : in STD_LOGIC;
shift_reg_ld_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
stop_scl_reg_reg_0 : in STD_LOGIC;
\cr_i_reg[2]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_iic_control : entity is "iic_control";
end system_axi_iic_0_0_iic_control;
architecture STRUCTURE of system_axi_iic_0_0_iic_control is
signal \^aas\ : STD_LOGIC;
signal BITCNT_n_0 : STD_LOGIC;
signal BITCNT_n_2 : STD_LOGIC;
signal \^bb\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal EarlyAckDataState0 : STD_LOGIC;
signal EarlyAckHdr0 : STD_LOGIC;
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_4_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_5_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[4]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[4]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[5]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[5]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[6]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[6]_i_5_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[6]_i_6_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[6]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[6]\ : signal is "yes";
signal \FSM_sequential_scl_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[0]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[0]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[0]_i_5_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[0]_i_6_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[0]_i_7_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[0]_i_8_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[1]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[1]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[1]_i_5_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[1]_i_6_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[3]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_scl_state[3]_i_5_n_0\ : STD_LOGIC;
signal \^fsm_sequential_scl_state_reg[2]_0\ : STD_LOGIC;
signal I2CDATA_REG_n_0 : STD_LOGIC;
signal I2CDATA_REG_n_2 : STD_LOGIC;
signal I2CDATA_REG_n_3 : STD_LOGIC;
signal I2CDATA_REG_n_4 : STD_LOGIC;
signal I2CDATA_REG_n_5 : STD_LOGIC;
signal I2CDATA_REG_n_6 : STD_LOGIC;
signal I2CDATA_REG_n_7 : STD_LOGIC;
signal I2CDATA_REG_n_8 : STD_LOGIC;
signal I2CDATA_REG_n_9 : STD_LOGIC;
signal I2CHEADER_REG_n_0 : STD_LOGIC;
signal I2CHEADER_REG_n_10 : STD_LOGIC;
signal I2CHEADER_REG_n_11 : STD_LOGIC;
signal \LEVEL_1_GEN.master_sda_reg_n_0\ : STD_LOGIC;
signal \^new_rcv_dta\ : STD_LOGIC;
signal SETUP_CNT_n_0 : STD_LOGIC;
signal SETUP_CNT_n_8 : STD_LOGIC;
signal \^tx_under_prev\ : STD_LOGIC;
signal aas_i_i_1_n_0 : STD_LOGIC;
signal al_i_i_1_n_0 : STD_LOGIC;
signal al_i_i_2_n_0 : STD_LOGIC;
signal al_prevent : STD_LOGIC;
signal al_prevent_i_1_n_0 : STD_LOGIC;
signal \^arb_lost\ : STD_LOGIC;
signal arb_lost_i_1_n_0 : STD_LOGIC;
signal arb_lost_i_2_n_0 : STD_LOGIC;
signal arb_lost_i_3_n_0 : STD_LOGIC;
signal bit_cnt_en : STD_LOGIC;
signal bit_cnt_en0 : STD_LOGIC;
signal bus_busy_d1 : STD_LOGIC;
signal bus_busy_i_1_n_0 : STD_LOGIC;
signal clk_cnt_en13_out : STD_LOGIC;
signal clk_cnt_en1_carry_n_1 : STD_LOGIC;
signal clk_cnt_en1_carry_n_2 : STD_LOGIC;
signal clk_cnt_en1_carry_n_3 : STD_LOGIC;
signal \clk_cnt_en1_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \clk_cnt_en1_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \clk_cnt_en1_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \clk_cnt_en1_inferred__1/i__carry_n_1\ : STD_LOGIC;
signal \clk_cnt_en1_inferred__1/i__carry_n_2\ : STD_LOGIC;
signal \clk_cnt_en1_inferred__1/i__carry_n_3\ : STD_LOGIC;
signal \clk_cnt_en1_inferred__2/i__carry_n_1\ : STD_LOGIC;
signal \clk_cnt_en1_inferred__2/i__carry_n_2\ : STD_LOGIC;
signal \clk_cnt_en1_inferred__2/i__carry_n_3\ : STD_LOGIC;
signal clk_cnt_en2 : STD_LOGIC;
signal clk_cnt_en2_carry_n_1 : STD_LOGIC;
signal clk_cnt_en2_carry_n_2 : STD_LOGIC;
signal clk_cnt_en2_carry_n_3 : STD_LOGIC;
signal \cr_i[5]_i_3_n_0\ : STD_LOGIC;
signal data_i2c_i0 : STD_LOGIC;
signal detect_start : STD_LOGIC;
signal detect_start_i_1_n_0 : STD_LOGIC;
signal detect_stop0 : STD_LOGIC;
signal detect_stop_b_i_1_n_0 : STD_LOGIC;
signal detect_stop_b_i_3_n_0 : STD_LOGIC;
signal \^detect_stop_b_reg_0\ : STD_LOGIC;
signal detect_stop_b_reg_n_0 : STD_LOGIC;
signal detect_stop_i_1_n_0 : STD_LOGIC;
signal detect_stop_reg_n_0 : STD_LOGIC;
signal dtc_i : STD_LOGIC;
signal dtc_i_d1 : STD_LOGIC;
signal dtc_i_d2 : STD_LOGIC;
signal dtre_d1 : STD_LOGIC;
signal \^earlyackhdr\ : STD_LOGIC;
signal gen_start : STD_LOGIC;
signal gen_start_i_1_n_0 : STD_LOGIC;
signal gen_stop : STD_LOGIC;
signal gen_stop_d1 : STD_LOGIC;
signal gen_stop_i_1_n_0 : STD_LOGIC;
signal i2c_header_en : STD_LOGIC;
signal i2c_header_en0 : STD_LOGIC;
signal \^master_slave\ : STD_LOGIC;
signal master_slave_i_1_n_0 : STD_LOGIC;
signal msms_d1 : STD_LOGIC;
signal msms_d10 : STD_LOGIC;
signal msms_d1_i_2_n_0 : STD_LOGIC;
signal msms_d2 : STD_LOGIC;
signal msms_rst_i : STD_LOGIC;
signal msms_rst_i_i_1_n_0 : STD_LOGIC;
signal next_scl_state10_out : STD_LOGIC;
signal \next_scl_state1_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \next_scl_state1_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \next_scl_state1_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal \next_scl_state1_inferred__1/i__carry_n_0\ : STD_LOGIC;
signal \next_scl_state1_inferred__1/i__carry_n_1\ : STD_LOGIC;
signal \next_scl_state1_inferred__1/i__carry_n_2\ : STD_LOGIC;
signal \next_scl_state1_inferred__1/i__carry_n_3\ : STD_LOGIC;
signal p_0_in_0 : STD_LOGIC;
attribute RTL_KEEP of p_0_in_0 : signal is "yes";
signal p_1_in : STD_LOGIC;
attribute RTL_KEEP of p_1_in : signal is "yes";
signal p_1_in0_in : STD_LOGIC;
attribute RTL_KEEP of p_1_in0_in : signal is "yes";
signal p_1_in6_in : STD_LOGIC;
attribute RTL_KEEP of p_1_in6_in : signal is "yes";
signal p_2_in : STD_LOGIC;
attribute RTL_KEEP of p_2_in : signal is "yes";
signal p_4_in : STD_LOGIC;
attribute RTL_KEEP of p_4_in : signal is "yes";
signal \^rdy_new_xmt_i\ : STD_LOGIC;
signal rdy_new_xmt_i_i_1_n_0 : STD_LOGIC;
signal ro_prev_d1 : STD_LOGIC;
signal rsta_d1 : STD_LOGIC;
signal rsta_tx_under_prev : STD_LOGIC;
signal rsta_tx_under_prev_i_1_n_0 : STD_LOGIC;
signal scl_cout_reg : STD_LOGIC;
signal scl_cout_reg0 : STD_LOGIC;
signal scl_f_edg_d1 : STD_LOGIC;
signal scl_f_edg_d2 : STD_LOGIC;
signal scl_f_edg_d3 : STD_LOGIC;
signal scl_falling_edge : STD_LOGIC;
signal scl_falling_edge0 : STD_LOGIC;
signal \^scl_rin_d1\ : STD_LOGIC;
signal scl_rising_edge : STD_LOGIC;
signal scl_state : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute RTL_KEEP of scl_state : signal is "yes";
signal sda_cout : STD_LOGIC;
signal sda_cout1 : STD_LOGIC;
signal sda_cout13_out : STD_LOGIC;
signal sda_cout4_out : STD_LOGIC;
signal sda_cout_reg : STD_LOGIC;
signal sda_cout_reg_i_1_n_0 : STD_LOGIC;
signal sda_cout_reg_i_2_n_0 : STD_LOGIC;
signal \^sda_cout_reg_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sda_rin_d1\ : STD_LOGIC;
signal sda_sample : STD_LOGIC;
signal sda_sample_i_1_n_0 : STD_LOGIC;
signal sda_setup : STD_LOGIC;
signal \sda_setup0_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \sda_setup0_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \sda_setup0_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \sda_setup0_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal sda_setup_i_1_n_0 : STD_LOGIC;
signal shift_reg : STD_LOGIC_VECTOR ( 7 to 7 );
signal shift_reg_en : STD_LOGIC;
signal shift_reg_en0 : STD_LOGIC;
signal shift_reg_en_i_2_n_0 : STD_LOGIC;
signal \^shift_reg_ld\ : STD_LOGIC;
signal shift_reg_ld0 : STD_LOGIC;
signal shift_reg_ld_d1 : STD_LOGIC;
signal shift_reg_ld_i_2_n_0 : STD_LOGIC;
signal slave_sda_reg_n_0 : STD_LOGIC;
signal sm_stop : STD_LOGIC;
signal sm_stop_i_1_n_0 : STD_LOGIC;
signal sm_stop_reg_n_0 : STD_LOGIC;
signal \^sr_i_reg[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal state0 : STD_LOGIC;
signal stop_scl : STD_LOGIC;
signal \^stop_scl_reg\ : STD_LOGIC;
signal stop_scl_reg_i_1_n_0 : STD_LOGIC;
signal stop_scl_reg_i_3_n_0 : STD_LOGIC;
signal tx_under_prev_d1 : STD_LOGIC;
signal tx_under_prev_i0 : STD_LOGIC;
signal tx_under_prev_i_i_1_n_0 : STD_LOGIC;
signal tx_under_prev_i_i_3_n_0 : STD_LOGIC;
signal txer_edge_i_1_n_0 : STD_LOGIC;
signal txer_i : STD_LOGIC;
signal txer_i_i_1_n_0 : STD_LOGIC;
signal txer_i_reg_n_0 : STD_LOGIC;
signal NLW_clk_cnt_en1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_clk_cnt_en1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_clk_cnt_en1_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_clk_cnt_en1_inferred__2/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_clk_cnt_en2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_next_scl_state1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_next_scl_state1_inferred__1/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_sda_setup0_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_state[0]_i_3\ : label is "soft_lutpair21";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[4]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[5]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[6]\ : label is "yes";
attribute SOFT_HLUTNM of \FSM_sequential_scl_state[1]_i_6\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \FSM_sequential_scl_state[2]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \FSM_sequential_scl_state[3]_i_5\ : label is "soft_lutpair19";
attribute KEEP of \FSM_sequential_scl_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_scl_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_scl_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_sequential_scl_state_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM of \IIC2Bus_IntrEvent[4]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of al_i_i_2 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of al_prevent_i_1 : label is "soft_lutpair20";
attribute SOFT_HLUTNM of detect_stop_b_i_3 : label is "soft_lutpair20";
attribute SOFT_HLUTNM of detect_stop_i_2 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of gen_stop_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of master_slave_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of sda_cout_reg_i_4 : label is "soft_lutpair22";
attribute SOFT_HLUTNM of sda_cout_reg_i_5 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of sda_sample_i_1 : label is "soft_lutpair21";
begin
Aas <= \^aas\;
Bb <= \^bb\;
D(3 downto 0) <= \^d\(3 downto 0);
\FSM_sequential_scl_state_reg[2]_0\ <= \^fsm_sequential_scl_state_reg[2]_0\;
New_rcv_dta <= \^new_rcv_dta\;
Tx_under_prev <= \^tx_under_prev\;
arb_lost <= \^arb_lost\;
detect_stop_b_reg_0 <= \^detect_stop_b_reg_0\;
earlyAckHdr <= \^earlyackhdr\;
master_slave <= \^master_slave\;
rdy_new_xmt_i <= \^rdy_new_xmt_i\;
scl_rin_d1 <= \^scl_rin_d1\;
sda_cout_reg_reg_0(0) <= \^sda_cout_reg_reg_0\(0);
sda_rin_d1 <= \^sda_rin_d1\;
shift_reg_ld <= \^shift_reg_ld\;
\sr_i_reg[4]\(1 downto 0) <= \^sr_i_reg[4]\(1 downto 0);
stop_scl_reg <= \^stop_scl_reg\;
AckDataState_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => ackDataState,
R => SR(0)
);
BITCNT: entity work.\system_axi_iic_0_0_upcnt_n__parameterized0\
port map (
E(0) => BITCNT_n_0,
EarlyAckDataState0 => EarlyAckDataState0,
\FSM_onehot_state_reg[4]\ => \FSM_onehot_state[6]_i_6_n_0\,
SR(0) => SR(0),
bit_cnt_en => bit_cnt_en,
detect_start => detect_start,
dtc_i => dtc_i,
dtc_i_reg => BITCNT_n_2,
\out\(5) => \FSM_onehot_state_reg_n_0_[6]\,
\out\(4) => p_1_in,
\out\(3) => p_1_in6_in,
\out\(2) => p_1_in0_in,
\out\(1) => p_2_in,
\out\(0) => p_4_in,
ro_prev_d1_reg => \FSM_onehot_state[6]_i_5_n_0\,
s_axi_aclk => s_axi_aclk,
scl_falling_edge => scl_falling_edge
);
CLKCNT: entity work.system_axi_iic_0_0_upcnt_n
port map (
CO(0) => clk_cnt_en13_out,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
SR(0) => SR(0),
detect_stop_b_reg => detect_stop_b_reg_n_0,
\out\(3 downto 0) => scl_state(3 downto 0),
\q_int_reg[0]_0\(9 downto 0) => \q_int_reg[0]\(9 downto 0),
s_axi_aclk => s_axi_aclk,
stop_scl_reg_reg => stop_scl_reg_reg_0,
\timing_param_thddat_i_reg[9]\(0) => clk_cnt_en2
);
EarlyAckDataState_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => EarlyAckDataState0,
Q => earlyAckDataState,
R => SR(0)
);
EarlyAckHdr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in0_in,
I1 => scl_f_edg_d3,
O => EarlyAckHdr0
);
EarlyAckHdr_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => EarlyAckHdr0,
Q => \^earlyackhdr\,
R => SR(0)
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEFE0"
)
port map (
I0 => state122_out,
I1 => \FSM_onehot_state[0]_i_3_n_0\,
I2 => p_1_in0_in,
I3 => \FSM_onehot_state[0]_i_4_n_0\,
I4 => \FSM_onehot_state[0]_i_5_n_0\,
I5 => \FSM_onehot_state[4]_i_2_n_0\,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sda_sample,
I1 => \^arb_lost\,
O => \FSM_onehot_state[0]_i_3_n_0\
);
\FSM_onehot_state[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4400440044007703"
)
port map (
I0 => detect_start,
I1 => p_1_in6_in,
I2 => \FSM_onehot_state_reg_n_0_[6]\,
I3 => state122_out,
I4 => p_1_in,
I5 => p_0_in_0,
O => \FSM_onehot_state[0]_i_4_n_0\
);
\FSM_onehot_state[0]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000054"
)
port map (
I0 => p_1_in6_in,
I1 => sda_sample,
I2 => \^arb_lost\,
I3 => p_0_in_0,
I4 => p_1_in,
O => \FSM_onehot_state[0]_i_5_n_0\
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAEEEA"
)
port map (
I0 => p_4_in,
I1 => detect_start,
I2 => p_1_in6_in,
I3 => p_0_in_0,
I4 => p_1_in0_in,
I5 => p_2_in,
O => \FSM_onehot_state[1]_i_1_n_0\
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_2_in,
I1 => p_4_in,
O => \FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => Ro_prev,
I1 => p_0_in_0,
I2 => p_1_in,
I3 => p_1_in6_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0101010000000100"
)
port map (
I0 => \^arb_lost\,
I1 => sda_sample,
I2 => \FSM_onehot_state[4]_i_2_n_0\,
I3 => \FSM_onehot_state[4]_i_3_n_0\,
I4 => p_1_in0_in,
I5 => \cr_i_reg[4]\,
O => \FSM_onehot_state[4]_i_1_n_0\
);
\FSM_onehot_state[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_4_in,
I1 => p_2_in,
O => \FSM_onehot_state[4]_i_2_n_0\
);
\FSM_onehot_state[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[6]\,
I1 => p_0_in_0,
I2 => p_1_in6_in,
I3 => p_1_in,
I4 => state122_out,
O => \FSM_onehot_state[4]_i_3_n_0\
);
\FSM_onehot_state[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => p_1_in0_in,
I1 => p_4_in,
I2 => p_2_in,
I3 => \FSM_onehot_state[5]_i_2_n_0\,
O => \FSM_onehot_state[5]_i_1_n_0\
);
\FSM_onehot_state[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"101F101010101010"
)
port map (
I0 => state122_out,
I1 => detect_start,
I2 => p_1_in6_in,
I3 => p_0_in_0,
I4 => Ro_prev,
I5 => p_1_in,
O => \FSM_onehot_state[5]_i_2_n_0\
);
\FSM_onehot_state[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => detect_stop_reg_n_0,
I1 => Q(0),
O => state0
);
\FSM_onehot_state[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => detect_start,
I1 => p_1_in6_in,
I2 => p_4_in,
I3 => p_0_in_0,
I4 => p_1_in0_in,
I5 => p_2_in,
O => \FSM_onehot_state[6]_i_3_n_0\
);
\FSM_onehot_state[6]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"0D"
)
port map (
I0 => ro_prev_d1,
I1 => Ro_prev,
I2 => scl_f_edg_d2,
O => \FSM_onehot_state[6]_i_5_n_0\
);
\FSM_onehot_state[6]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in_0,
I1 => p_1_in6_in,
O => \FSM_onehot_state[6]_i_6_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => BITCNT_n_0,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_4_in,
S => state0
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BITCNT_n_0,
D => \FSM_onehot_state[1]_i_1_n_0\,
Q => p_2_in,
R => state0
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BITCNT_n_0,
D => \FSM_onehot_state[2]_i_1_n_0\,
Q => p_1_in0_in,
R => state0
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BITCNT_n_0,
D => I2CHEADER_REG_n_0,
Q => p_1_in6_in,
R => state0
);
\FSM_onehot_state_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BITCNT_n_0,
D => \FSM_onehot_state[4]_i_1_n_0\,
Q => p_0_in_0,
R => state0
);
\FSM_onehot_state_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BITCNT_n_0,
D => \FSM_onehot_state[5]_i_1_n_0\,
Q => p_1_in,
R => state0
);
\FSM_onehot_state_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BITCNT_n_0,
D => \FSM_onehot_state[6]_i_3_n_0\,
Q => \FSM_onehot_state_reg_n_0_[6]\,
R => state0
);
\FSM_sequential_scl_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEEEEFE"
)
port map (
I0 => \FSM_sequential_scl_state[0]_i_2_n_0\,
I1 => \FSM_sequential_scl_state[0]_i_3_n_0\,
I2 => \FSM_sequential_scl_state[0]_i_4_n_0\,
I3 => clk_cnt_en13_out,
I4 => scl_state(2),
I5 => \FSM_sequential_scl_state[0]_i_5_n_0\,
O => \FSM_sequential_scl_state[0]_i_1_n_0\
);
\FSM_sequential_scl_state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBAAAAAAA"
)
port map (
I0 => \FSM_sequential_scl_state[0]_i_6_n_0\,
I1 => next_scl_state10_out,
I2 => scl_state(0),
I3 => scl_state(1),
I4 => \^detect_stop_b_reg_0\,
I5 => \FSM_sequential_scl_state[0]_i_7_n_0\,
O => \FSM_sequential_scl_state[0]_i_2_n_0\
);
\FSM_sequential_scl_state[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => scl_state(2),
I1 => scl_state(3),
I2 => scl_state(0),
I3 => scl_state(1),
I4 => \next_scl_state1_inferred__1/i__carry_n_0\,
O => \FSM_sequential_scl_state[0]_i_3_n_0\
);
\FSM_sequential_scl_state[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => scl_state(0),
I1 => scl_state(1),
O => \FSM_sequential_scl_state[0]_i_4_n_0\
);
\FSM_sequential_scl_state[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000004444C000"
)
port map (
I0 => scndry_out,
I1 => \^detect_stop_b_reg_0\,
I2 => \FSM_sequential_scl_state[0]_i_8_n_0\,
I3 => \FSM_sequential_scl_state[1]_i_6_n_0\,
I4 => scl_state(1),
I5 => scl_state(0),
O => \FSM_sequential_scl_state[0]_i_5_n_0\
);
\FSM_sequential_scl_state[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C020000000200"
)
port map (
I0 => scndry_out,
I1 => scl_state(1),
I2 => scl_state(0),
I3 => scl_state(3),
I4 => scl_state(2),
I5 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
O => \FSM_sequential_scl_state[0]_i_6_n_0\
);
\FSM_sequential_scl_state[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => clk_cnt_en2,
I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
I2 => scl_state(2),
I3 => scl_state(3),
I4 => scl_state(1),
I5 => scl_state(0),
O => \FSM_sequential_scl_state[0]_i_7_n_0\
);
\FSM_sequential_scl_state[0]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => detect_stop_b_reg_n_0,
I1 => clk_cnt_en13_out,
O => \FSM_sequential_scl_state[0]_i_8_n_0\
);
\FSM_sequential_scl_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF88F8"
)
port map (
I0 => \FSM_sequential_scl_state[1]_i_2_n_0\,
I1 => \next_scl_state1_inferred__1/i__carry_n_0\,
I2 => \FSM_sequential_scl_state[1]_i_3_n_0\,
I3 => scl_state(3),
I4 => \FSM_sequential_scl_state[1]_i_4_n_0\,
I5 => \FSM_sequential_scl_state[1]_i_5_n_0\,
O => \FSM_sequential_scl_state[1]_i_1_n_0\
);
\FSM_sequential_scl_state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => scl_state(1),
I1 => scl_state(0),
I2 => scl_state(3),
I3 => scl_state(2),
O => \FSM_sequential_scl_state[1]_i_2_n_0\
);
\FSM_sequential_scl_state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => scl_state(1),
I1 => scl_state(0),
O => \FSM_sequential_scl_state[1]_i_3_n_0\
);
\FSM_sequential_scl_state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4C4C000C40400000"
)
port map (
I0 => scl_state(1),
I1 => \^detect_stop_b_reg_0\,
I2 => scl_state(0),
I3 => detect_stop_b_reg_n_0,
I4 => clk_cnt_en13_out,
I5 => \FSM_sequential_scl_state[1]_i_6_n_0\,
O => \FSM_sequential_scl_state[1]_i_4_n_0\
);
\FSM_sequential_scl_state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"010D010100000000"
)
port map (
I0 => next_scl_state10_out,
I1 => scl_state(2),
I2 => scl_state(3),
I3 => \^arb_lost\,
I4 => Q(3),
I5 => scl_state(1),
O => \FSM_sequential_scl_state[1]_i_5_n_0\
);
\FSM_sequential_scl_state[1]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^bb\,
I1 => gen_start,
I2 => \^master_slave\,
O => \FSM_sequential_scl_state[1]_i_6_n_0\
);
\FSM_sequential_scl_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF0000003000AA"
)
port map (
I0 => next_scl_state10_out,
I1 => \^stop_scl_reg\,
I2 => \FSM_sequential_scl_state[2]_i_2_n_0\,
I3 => scl_state(3),
I4 => scl_state(2),
I5 => \^fsm_sequential_scl_state_reg[2]_0\,
O => \FSM_sequential_scl_state[2]_i_1_n_0\
);
\FSM_sequential_scl_state[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^arb_lost\,
I1 => Q(3),
O => \FSM_sequential_scl_state[2]_i_2_n_0\
);
\FSM_sequential_scl_state[2]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => scl_state(0),
I1 => scl_state(1),
O => \^fsm_sequential_scl_state_reg[2]_0\
);
\FSM_sequential_scl_state[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"05FF05FF05FF057F"
)
port map (
I0 => scl_state(1),
I1 => scl_state(0),
I2 => scl_state(2),
I3 => scl_state(3),
I4 => \cr_i_reg[2]\,
I5 => \^arb_lost\,
O => \FSM_sequential_scl_state[3]_i_2_n_0\
);
\FSM_sequential_scl_state[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A000000003000F0"
)
port map (
I0 => \FSM_sequential_scl_state[3]_i_5_n_0\,
I1 => clk_cnt_en13_out,
I2 => scl_state(3),
I3 => scl_state(2),
I4 => scl_state(0),
I5 => scl_state(1),
O => \FSM_sequential_scl_state[3]_i_3_n_0\
);
\FSM_sequential_scl_state[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => Q(3),
I1 => \^arb_lost\,
I2 => \^stop_scl_reg\,
O => \FSM_sequential_scl_state[3]_i_5_n_0\
);
\FSM_sequential_scl_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_scl_state[3]_i_2_n_0\,
D => \FSM_sequential_scl_state[0]_i_1_n_0\,
Q => scl_state(0),
R => SR(0)
);
\FSM_sequential_scl_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_scl_state[3]_i_2_n_0\,
D => \FSM_sequential_scl_state[1]_i_1_n_0\,
Q => scl_state(1),
R => SR(0)
);
\FSM_sequential_scl_state_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_scl_state[3]_i_2_n_0\,
D => \FSM_sequential_scl_state[2]_i_1_n_0\,
Q => scl_state(2),
R => SR(0)
);
\FSM_sequential_scl_state_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_scl_state[3]_i_2_n_0\,
D => \FSM_sequential_scl_state[3]_i_3_n_0\,
Q => scl_state(3),
R => SR(0)
);
I2CDATA_REG: entity work.system_axi_iic_0_0_shift8
port map (
\LEVEL_1_GEN.master_sda_reg\ => I2CDATA_REG_n_0,
Q(7) => shift_reg(7),
Q(6) => I2CDATA_REG_n_2,
Q(5) => I2CDATA_REG_n_3,
Q(4) => I2CDATA_REG_n_4,
Q(3) => I2CDATA_REG_n_5,
Q(2) => I2CDATA_REG_n_6,
Q(1) => I2CDATA_REG_n_7,
Q(0) => I2CDATA_REG_n_8,
SR(0) => SR(0),
Tx_fifo_data(6 downto 0) => Tx_fifo_data(6 downto 0),
abgc_i_reg => abgc_i_reg_1,
\out\(3) => p_1_in,
\out\(2) => p_0_in_0,
\out\(1) => p_1_in0_in,
\out\(0) => p_2_in,
s_axi_aclk => s_axi_aclk,
shift_reg_en => shift_reg_en,
shift_reg_ld_reg => \^shift_reg_ld\,
shift_reg_ld_reg_0(0) => shift_reg_ld_reg_0(0),
slave_sda_reg => I2CDATA_REG_n_9,
tx_under_prev_i_reg => \^tx_under_prev\,
txak => txak
);
I2CHEADER_REG: entity work.system_axi_iic_0_0_shift8_1
port map (
D(0) => I2CHEADER_REG_n_0,
E(0) => i2c_header_en,
\FSM_onehot_state_reg[6]\ => shift_reg_ld_i_2_n_0,
Q(7 downto 0) => abgc_i_reg_0(7 downto 0),
\RD_FIFO_CNTRL.ro_prev_i_reg\ => \FSM_onehot_state[3]_i_2_n_0\,
SR(0) => SR(0),
abgc_i_reg => I2CHEADER_REG_n_10,
abgc_i_reg_0 => abgc_i_reg_1,
arb_lost_reg => \^arb_lost\,
\cr_i_reg[1]\(2) => Q(4),
\cr_i_reg[1]\(1) => Q(2),
\cr_i_reg[1]\(0) => Q(0),
detect_start => detect_start,
detect_stop_reg => detect_stop_reg_n_0,
master_slave_reg => \^master_slave\,
\out\(2) => p_1_in0_in,
\out\(1) => p_2_in,
\out\(0) => p_4_in,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sda_sample => sda_sample,
shift_reg_ld0 => shift_reg_ld0,
srw_i_reg => I2CHEADER_REG_n_11,
srw_i_reg_0(1 downto 0) => \^sr_i_reg[4]\(1 downto 0)
);
\IIC2Bus_IntrEvent[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bb\,
O => \^d\(1)
);
\IIC2Bus_IntrEvent[6]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aas\,
O => \^d\(0)
);
\LEVEL_1_GEN.master_sda_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => I2CDATA_REG_n_0,
Q => \LEVEL_1_GEN.master_sda_reg_n_0\,
S => SR(0)
);
\RD_FIFO_CNTRL.Rc_fifo_wr_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^new_rcv_dta\,
I1 => new_rcv_dta_d1,
O => \RD_FIFO_CNTRL.Rc_fifo_wr_reg\
);
SETUP_CNT: entity work.system_axi_iic_0_0_upcnt_n_2
port map (
Q(0) => Q(3),
S(0) => SETUP_CNT_n_8,
SR(0) => SR(0),
gen_stop => gen_stop,
gen_stop_d1 => gen_stop_d1,
\q_int_reg[0]_0\(6 downto 0) => \q_int_reg[0]_0\(6 downto 0),
\q_int_reg[1]_0\ => SETUP_CNT_n_0,
rsta_d1 => rsta_d1,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sda_rin_d1_reg => \^sda_rin_d1\,
sda_setup => sda_setup,
\timing_param_tsudat_i_reg[8]\(2 downto 0) => \timing_param_tsudat_i_reg[8]\(2 downto 0),
tx_under_prev_d1 => tx_under_prev_d1,
tx_under_prev_i_reg => \^tx_under_prev\
);
aas_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000E0000"
)
port map (
I0 => \^aas\,
I1 => p_1_in0_in,
I2 => abgc_i_reg_1,
I3 => detect_stop_reg_n_0,
I4 => Q(0),
O => aas_i_i_1_n_0
);
aas_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => aas_i_i_1_n_0,
Q => \^aas\,
R => '0'
);
abgc_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I2CHEADER_REG_n_10,
Q => \^sr_i_reg[4]\(0),
R => '0'
);
al_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0E0E0E0EEE0E0"
)
port map (
I0 => Q(3),
I1 => \^master_slave\,
I2 => al_i_i_2_n_0,
I3 => al_prevent,
I4 => detect_stop_reg_n_0,
I5 => sm_stop_reg_n_0,
O => al_i_i_1_n_0
);
al_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FF8F"
)
port map (
I0 => bus_busy_d1,
I1 => gen_start,
I2 => \^master_slave\,
I3 => \^arb_lost\,
O => al_i_i_2_n_0
);
al_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => al_i_i_1_n_0,
Q => \^d\(3),
R => SR(0)
);
al_prevent_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"5554"
)
port map (
I0 => detect_start,
I1 => gen_stop,
I2 => sm_stop_reg_n_0,
I3 => al_prevent,
O => al_prevent_i_1_n_0
);
al_prevent_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => al_prevent_i_1_n_0,
Q => al_prevent,
R => SR(0)
);
arb_lost_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002AEA2A2A"
)
port map (
I0 => \^arb_lost\,
I1 => \^master_slave\,
I2 => arb_lost_i_2_n_0,
I3 => scndry_out,
I4 => sda_cout_reg,
I5 => arb_lost_i_3_n_0,
O => arb_lost_i_1_n_0
);
arb_lost_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => scl_rising_edge,
I1 => p_0_in_0,
I2 => p_2_in,
O => arb_lost_i_2_n_0
);
arb_lost_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"0401FFFF"
)
port map (
I0 => scl_state(2),
I1 => scl_state(3),
I2 => scl_state(1),
I3 => scl_state(0),
I4 => Q(0),
O => arb_lost_i_3_n_0
);
arb_lost_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => arb_lost_i_1_n_0,
Q => \^arb_lost\,
R => '0'
);
bit_cnt_en_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => scl_falling_edge,
I1 => p_1_in6_in,
I2 => p_2_in,
I3 => p_0_in_0,
O => bit_cnt_en0
);
bit_cnt_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bit_cnt_en0,
Q => bit_cnt_en,
R => SR(0)
);
bus_busy_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^bb\,
Q => bus_busy_d1,
R => SR(0)
);
bus_busy_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => \^bb\,
I1 => detect_start,
I2 => Q(0),
I3 => detect_stop_reg_n_0,
O => bus_busy_i_1_n_0
);
bus_busy_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus_busy_i_1_n_0,
Q => \^bb\,
R => '0'
);
clk_cnt_en1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => clk_cnt_en1_carry_n_1,
CO(1) => clk_cnt_en1_carry_n_2,
CO(0) => clk_cnt_en1_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_clk_cnt_en1_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\clk_cnt_en1_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \^sda_cout_reg_reg_0\(0),
CO(2) => \clk_cnt_en1_inferred__0/i__carry_n_1\,
CO(1) => \clk_cnt_en1_inferred__0/i__carry_n_2\,
CO(0) => \clk_cnt_en1_inferred__0/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_clk_cnt_en1_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \timing_param_tsusto_i_reg[9]\(3 downto 0)
);
\clk_cnt_en1_inferred__1/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \FSM_sequential_scl_state_reg[0]_0\(0),
CO(2) => \clk_cnt_en1_inferred__1/i__carry_n_1\,
CO(1) => \clk_cnt_en1_inferred__1/i__carry_n_2\,
CO(0) => \clk_cnt_en1_inferred__1/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_clk_cnt_en1_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \timing_param_tsusta_i_reg[9]\(3 downto 0)
);
\clk_cnt_en1_inferred__2/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => clk_cnt_en13_out,
CO(2) => \clk_cnt_en1_inferred__2/i__carry_n_1\,
CO(1) => \clk_cnt_en1_inferred__2/i__carry_n_2\,
CO(0) => \clk_cnt_en1_inferred__2/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_clk_cnt_en1_inferred__2/i__carry_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \timing_param_tbuf_i_reg[9]\(3 downto 0)
);
clk_cnt_en2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => clk_cnt_en2,
CO(2) => clk_cnt_en2_carry_n_1,
CO(1) => clk_cnt_en2_carry_n_2,
CO(0) => clk_cnt_en2_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_clk_cnt_en2_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => \timing_param_thddat_i_reg[9]\(3 downto 0)
);
\cr_i[2]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => scl_state(2),
I1 => scl_state(3),
O => \^detect_stop_b_reg_0\
);
\cr_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888BBBB888B"
)
port map (
I0 => s_axi_wdata(0),
I1 => E(0),
I2 => \^bb\,
I3 => Data_Exists_DFF,
I4 => Q(1),
I5 => \cr_i[5]_i_3_n_0\,
O => \cr_i_reg[5]\(0)
);
\cr_i[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFFFEFEFE"
)
port map (
I0 => rxCntDone,
I1 => msms_rst_i,
I2 => sm_stop_reg_n_0,
I3 => dynamic_MSMS(0),
I4 => Tx_data_exists,
I5 => Tx_fifo_rd_d_reg,
O => \cr_i[5]_i_3_n_0\
);
\data_i2c_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => data_i2c_i0,
D => I2CDATA_REG_n_8,
Q => \s_axi_rdata_i_reg[7]\(0),
R => SR(0)
);
\data_i2c_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => data_i2c_i0,
D => I2CDATA_REG_n_7,
Q => \s_axi_rdata_i_reg[7]\(1),
R => SR(0)
);
\data_i2c_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => data_i2c_i0,
D => I2CDATA_REG_n_6,
Q => \s_axi_rdata_i_reg[7]\(2),
R => SR(0)
);
\data_i2c_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => data_i2c_i0,
D => I2CDATA_REG_n_5,
Q => \s_axi_rdata_i_reg[7]\(3),
R => SR(0)
);
\data_i2c_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => data_i2c_i0,
D => I2CDATA_REG_n_4,
Q => \s_axi_rdata_i_reg[7]\(4),
R => SR(0)
);
\data_i2c_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => data_i2c_i0,
D => I2CDATA_REG_n_3,
Q => \s_axi_rdata_i_reg[7]\(5),
R => SR(0)
);
\data_i2c_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => data_i2c_i0,
D => I2CDATA_REG_n_2,
Q => \s_axi_rdata_i_reg[7]\(6),
R => SR(0)
);
\data_i2c_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => data_i2c_i0,
D => shift_reg(7),
Q => \s_axi_rdata_i_reg[7]\(7),
R => SR(0)
);
detect_start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BA8A0000"
)
port map (
I0 => detect_start,
I1 => scndry_out,
I2 => \^sda_rin_d1\,
I3 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
I4 => Q(0),
I5 => p_2_in,
O => detect_start_i_1_n_0
);
detect_start_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => detect_start_i_1_n_0,
Q => detect_start,
R => '0'
);
detect_stop_b_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000CEEE0222"
)
port map (
I0 => detect_stop_b_reg_n_0,
I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\,
I2 => \FSM_sequential_scl_state[1]_i_3_n_0\,
I3 => \^detect_stop_b_reg_0\,
I4 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
I5 => detect_stop_b_i_3_n_0,
O => detect_stop_b_i_1_n_0
);
detect_stop_b_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => detect_start,
I1 => Q(0),
O => detect_stop_b_i_3_n_0
);
detect_stop_b_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => detect_stop_b_i_1_n_0,
Q => detect_stop_b_reg_n_0,
R => '0'
);
detect_stop_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000022F22202"
)
port map (
I0 => detect_stop_reg_n_0,
I1 => detect_stop0,
I2 => scndry_out,
I3 => \^sda_rin_d1\,
I4 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
I5 => detect_stop_b_i_3_n_0,
O => detect_stop_i_1_n_0
);
detect_stop_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => msms_d1,
I1 => msms_d2,
O => detect_stop0
);
detect_stop_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => detect_stop_i_1_n_0,
Q => detect_stop_reg_n_0,
R => '0'
);
dtc_i_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => dtc_i,
Q => dtc_i_d1,
R => SR(0)
);
dtc_i_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => dtc_i_d1,
Q => dtc_i_d2,
R => SR(0)
);
dtc_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => BITCNT_n_2,
Q => dtc_i,
R => SR(0)
);
dtre_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => sr_i(0),
Q => dtre_d1,
R => SR(0)
);
gen_start_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7530"
)
port map (
I0 => detect_start,
I1 => msms_d2,
I2 => msms_d1,
I3 => gen_start,
O => gen_start_i_1_n_0
);
gen_start_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gen_start_i_1_n_0,
Q => gen_start,
R => SR(0)
);
gen_stop_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gen_stop,
Q => gen_stop_d1,
R => SR(0)
);
gen_stop_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55750030"
)
port map (
I0 => detect_stop_reg_n_0,
I1 => \^arb_lost\,
I2 => msms_d2,
I3 => msms_d1,
I4 => gen_stop,
O => gen_stop_i_1_n_0
);
gen_stop_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gen_stop_i_1_n_0,
Q => gen_stop,
R => SR(0)
);
i2c_header_en_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_2_in,
I1 => scl_rising_edge,
O => i2c_header_en0
);
i2c_header_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => i2c_header_en0,
Q => i2c_header_en,
R => SR(0)
);
master_slave_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00A0C0A0"
)
port map (
I0 => msms_d1,
I1 => \^master_slave\,
I2 => Q(0),
I3 => \^bb\,
I4 => \^arb_lost\,
O => master_slave_i_1_n_0
);
master_slave_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => master_slave_i_1_n_0,
Q => \^master_slave\,
R => '0'
);
msms_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => msms_d1_i_2_n_0,
I1 => msms_rst_i,
O => msms_d10
);
msms_d1_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAAAAAABAAABA"
)
port map (
I0 => Q(1),
I1 => txer_i_reg_n_0,
I2 => msms_d1,
I3 => Msms_set,
I4 => dtc_i_d2,
I5 => dtc_i_d1,
O => msms_d1_i_2_n_0
);
msms_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => msms_d10,
Q => msms_d1,
R => SR(0)
);
msms_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => msms_d1,
Q => msms_d2,
R => SR(0)
);
msms_rst_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000030AA00AA"
)
port map (
I0 => msms_rst_i,
I1 => scndry_out,
I2 => sda_cout_reg,
I3 => \^master_slave\,
I4 => arb_lost_i_2_n_0,
I5 => arb_lost_i_3_n_0,
O => msms_rst_i_i_1_n_0
);
msms_rst_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => msms_rst_i_i_1_n_0,
Q => msms_rst_i,
R => '0'
);
new_rcv_dta_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => p_1_in,
I1 => scl_falling_edge,
I2 => Ro_prev,
O => data_i2c_i0
);
new_rcv_dta_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => data_i2c_i0,
Q => \^new_rcv_dta\,
R => SR(0)
);
\next_scl_state1_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => next_scl_state10_out,
CO(2) => \next_scl_state1_inferred__0/i__carry_n_1\,
CO(1) => \next_scl_state1_inferred__0/i__carry_n_2\,
CO(0) => \next_scl_state1_inferred__0/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_next_scl_state1_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \timing_param_thdsta_i_reg[9]\(3 downto 0)
);
\next_scl_state1_inferred__1/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \next_scl_state1_inferred__1/i__carry_n_0\,
CO(2) => \next_scl_state1_inferred__1/i__carry_n_1\,
CO(1) => \next_scl_state1_inferred__1/i__carry_n_2\,
CO(0) => \next_scl_state1_inferred__1/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_next_scl_state1_inferred__1/i__carry_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => \timing_param_tlow_i_reg[9]\(3 downto 0)
);
rdCntrFrmTxFifo_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^earlyackhdr\,
I1 => callingReadAccess,
I2 => Tx_data_exists,
O => rdCntrFrmTxFifo0
);
rdy_new_xmt_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"222F2F2F22202020"
)
port map (
I0 => shift_reg_ld_d1,
I1 => \^shift_reg_ld\,
I2 => p_0_in_0,
I3 => Q(1),
I4 => p_2_in,
I5 => \^rdy_new_xmt_i\,
O => rdy_new_xmt_i_i_1_n_0
);
rdy_new_xmt_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdy_new_xmt_i_i_1_n_0,
Q => \^rdy_new_xmt_i\,
R => SR(0)
);
ro_prev_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Ro_prev,
Q => ro_prev_d1,
R => SR(0)
);
rsta_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Q(3),
Q => rsta_d1,
R => SR(0)
);
rsta_tx_under_prev_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F0FF2020"
)
port map (
I0 => Q(3),
I1 => rsta_d1,
I2 => sr_i(0),
I3 => dtre_d1,
I4 => rsta_tx_under_prev,
O => rsta_tx_under_prev_i_1_n_0
);
rsta_tx_under_prev_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rsta_tx_under_prev_i_1_n_0,
Q => rsta_tx_under_prev,
R => SR(0)
);
scl_cout_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"001D"
)
port map (
I0 => scl_state(2),
I1 => scl_state(1),
I2 => scl_state(3),
I3 => Ro_prev,
O => scl_cout_reg0
);
scl_cout_reg_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => scl_cout_reg0,
Q => scl_cout_reg,
S => SR(0)
);
scl_f_edg_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => scl_falling_edge,
Q => scl_f_edg_d1,
R => SR(0)
);
scl_f_edg_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => scl_f_edg_d1,
Q => scl_f_edg_d2,
R => SR(0)
);
scl_f_edg_d3_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => scl_f_edg_d2,
Q => scl_f_edg_d3,
R => SR(0)
);
scl_falling_edge_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^scl_rin_d1\,
I1 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
O => scl_falling_edge0
);
scl_falling_edge_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => scl_falling_edge0,
Q => scl_falling_edge,
R => SR(0)
);
scl_rin_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
Q => \^scl_rin_d1\,
R => '0'
);
scl_rising_edge_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => scl_rising_edge0,
Q => scl_rising_edge,
R => SR(0)
);
scl_t_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => sda_setup,
I1 => scl_cout_reg,
I2 => rsta_tx_under_prev,
I3 => Ro_prev,
O => scl_t
);
sda_cout_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => sda_cout_reg_i_2_n_0,
I1 => sda_cout,
I2 => sda_cout_reg,
O => sda_cout_reg_i_1_n_0
);
sda_cout_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000CAAA00FF"
)
port map (
I0 => sda_cout4_out,
I1 => \^sda_cout_reg_reg_0\(0),
I2 => scl_state(0),
I3 => scl_state(1),
I4 => scl_state(2),
I5 => scl_state(3),
O => sda_cout_reg_i_2_n_0
);
sda_cout_reg_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"45054141"
)
port map (
I0 => scl_state(3),
I1 => scl_state(2),
I2 => scl_state(0),
I3 => sda_cout13_out,
I4 => scl_state(1),
O => sda_cout
);
sda_cout_reg_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => Q(3),
I1 => \LEVEL_1_GEN.master_sda_reg_n_0\,
I2 => sda_cout1,
O => sda_cout4_out
);
sda_cout_reg_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \^arb_lost\,
I1 => \^stop_scl_reg\,
I2 => \^sda_cout_reg_reg_0\(0),
I3 => Q(3),
O => sda_cout13_out
);
sda_cout_reg_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => sda_cout_reg_i_1_n_0,
Q => sda_cout_reg,
S => SR(0)
);
sda_rin_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => scndry_out,
Q => \^sda_rin_d1\,
R => '0'
);
sda_sample_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => scndry_out,
I1 => scl_rising_edge,
I2 => sda_sample,
O => sda_sample_i_1_n_0
);
sda_sample_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => sda_sample_i_1_n_0,
Q => sda_sample,
R => SR(0)
);
\sda_setup0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \sda_setup0_inferred__0/i__carry_n_0\,
CO(2) => \sda_setup0_inferred__0/i__carry_n_1\,
CO(1) => \sda_setup0_inferred__0/i__carry_n_2\,
CO(0) => \sda_setup0_inferred__0/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_sda_setup0_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \timing_param_tsudat_i_reg[9]\(2),
S(2) => SETUP_CNT_n_8,
S(1 downto 0) => \timing_param_tsudat_i_reg[9]\(1 downto 0)
);
sda_setup_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55FD00FC"
)
port map (
I0 => \sda_setup0_inferred__0/i__carry_n_0\,
I1 => \^tx_under_prev\,
I2 => SETUP_CNT_n_0,
I3 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\,
I4 => sda_setup,
O => sda_setup_i_1_n_0
);
sda_setup_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => sda_setup_i_1_n_0,
Q => sda_setup,
R => SR(0)
);
sda_t_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EFE0"
)
port map (
I0 => \^arb_lost\,
I1 => sda_cout_reg,
I2 => \^master_slave\,
I3 => slave_sda_reg_n_0,
I4 => \^stop_scl_reg\,
O => sda_t
);
shift_reg_en_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => shift_reg_en_i_2_n_0,
I1 => \^master_slave\,
I2 => p_2_in,
I3 => scl_rising_edge,
O => shift_reg_en0
);
shift_reg_en_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"55404040"
)
port map (
I0 => detect_start,
I1 => p_0_in_0,
I2 => scl_f_edg_d2,
I3 => scl_rising_edge,
I4 => p_1_in6_in,
O => shift_reg_en_i_2_n_0
);
shift_reg_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => shift_reg_en0,
Q => shift_reg_en,
R => SR(0)
);
shift_reg_ld_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^shift_reg_ld\,
Q => shift_reg_ld_d1,
R => SR(0)
);
shift_reg_ld_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEEEFEEEFEEE"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[6]\,
I1 => \^tx_under_prev\,
I2 => \^master_slave\,
I3 => p_4_in,
I4 => p_1_in6_in,
I5 => detect_start,
O => shift_reg_ld_i_2_n_0
);
shift_reg_ld_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => shift_reg_ld0,
Q => \^shift_reg_ld\,
R => SR(0)
);
slave_sda_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => I2CDATA_REG_n_9,
Q => slave_sda_reg_n_0,
S => SR(0)
);
sm_stop_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BA8A0000"
)
port map (
I0 => sm_stop_reg_n_0,
I1 => \FSM_onehot_state[6]_i_5_n_0\,
I2 => sm_stop,
I3 => \^master_slave\,
I4 => Q(0),
I5 => detect_stop_reg_n_0,
O => sm_stop_i_1_n_0
);
sm_stop_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"40404000"
)
port map (
I0 => \^arb_lost\,
I1 => \^master_slave\,
I2 => sda_sample,
I3 => \FSM_onehot_state_reg_n_0_[6]\,
I4 => p_1_in0_in,
O => sm_stop
);
sm_stop_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => sm_stop_i_1_n_0,
Q => sm_stop_reg_n_0,
R => '0'
);
srw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I2CHEADER_REG_n_11,
Q => \^sr_i_reg[4]\(1),
R => '0'
);
stop_scl_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"2800FFFF28000000"
)
port map (
I0 => sda_cout1,
I1 => scl_state(1),
I2 => scl_state(0),
I3 => stop_scl_reg_i_3_n_0,
I4 => stop_scl,
I5 => \^stop_scl_reg\,
O => stop_scl_reg_i_1_n_0
);
stop_scl_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000000E"
)
port map (
I0 => gen_stop,
I1 => sm_stop_reg_n_0,
I2 => \FSM_onehot_state_reg_n_0_[6]\,
I3 => p_1_in0_in,
I4 => p_1_in,
O => sda_cout1
);
stop_scl_reg_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => scl_state(2),
I1 => scl_state(3),
O => stop_scl_reg_i_3_n_0
);
stop_scl_reg_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"40555F55"
)
port map (
I0 => scl_state(3),
I1 => sda_cout13_out,
I2 => scl_state(2),
I3 => scl_state(0),
I4 => scl_state(1),
O => stop_scl
);
stop_scl_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => stop_scl_reg_i_1_n_0,
Q => \^stop_scl_reg\,
R => SR(0)
);
tx_under_prev_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^tx_under_prev\,
Q => tx_under_prev_d1,
R => SR(0)
);
tx_under_prev_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"AABAAAAA"
)
port map (
I0 => tx_under_prev_i0,
I1 => p_4_in,
I2 => sr_i(0),
I3 => p_1_in6_in,
I4 => \^tx_under_prev\,
O => tx_under_prev_i_i_1_n_0
);
tx_under_prev_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000900000000000"
)
port map (
I0 => \^aas\,
I1 => \^sr_i_reg[4]\(1),
I2 => tx_under_prev_i_i_3_n_0,
I3 => sr_i(0),
I4 => gen_stop,
I5 => scl_falling_edge,
O => tx_under_prev_i0
);
tx_under_prev_i_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_1_in0_in,
I1 => \FSM_onehot_state_reg_n_0_[6]\,
O => tx_under_prev_i_i_3_n_0
);
tx_under_prev_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_under_prev_i_i_1_n_0,
Q => \^tx_under_prev\,
R => SR(0)
);
txer_edge_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"E200E2000000E200"
)
port map (
I0 => \^d\(2),
I1 => txer_i,
I2 => sda_sample,
I3 => Q(0),
I4 => scl_f_edg_d2,
I5 => scl_falling_edge,
O => txer_edge_i_1_n_0
);
txer_edge_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => scl_falling_edge,
I1 => p_1_in0_in,
I2 => \FSM_onehot_state_reg_n_0_[6]\,
I3 => p_1_in,
O => txer_i
);
txer_edge_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => txer_edge_i_1_n_0,
Q => \^d\(2),
R => '0'
);
txer_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBF88888880"
)
port map (
I0 => sda_sample,
I1 => scl_falling_edge,
I2 => p_1_in0_in,
I3 => \FSM_onehot_state_reg_n_0_[6]\,
I4 => p_1_in,
I5 => txer_i_reg_n_0,
O => txer_i_i_1_n_0
);
txer_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => txer_i_i_1_n_0,
Q => txer_i_reg_n_0,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_slave_attachment is
port (
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
AXI_IP2Bus_WrAck2_reg : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
Bus2IIC_RdCE : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus2IIC_WrCE : out STD_LOGIC_VECTOR ( 11 downto 0 );
AXI_IP2Bus_RdAck20 : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
\GPO_GEN.gpo_i_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
AXI_Bus2IP_Reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\timing_param_tsudat_i_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\cr_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_tlow_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AXI_IP2Bus_RdAck1 : in STD_LOGIC;
AXI_IP2Bus_RdAck2 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
AXI_IP2Bus_WrAck1 : in STD_LOGIC;
AXI_IP2Bus_WrAck2 : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 8 downto 0 );
irpt_wrack_d1 : in STD_LOGIC;
IIC2Bus_IntrEvent : in STD_LOGIC_VECTOR ( 0 to 7 );
p_1_in : in STD_LOGIC;
p_1_in2_in : in STD_LOGIC;
p_1_in5_in : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
\ip_irpt_enable_reg_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\timing_param_thdsta_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\adr_i_reg[6]\ : in STD_LOGIC;
\adr_i_reg[5]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[3]\ : in STD_LOGIC;
\adr_i_reg[4]\ : in STD_LOGIC;
\adr_i_reg[3]\ : in STD_LOGIC;
\adr_i_reg[2]\ : in STD_LOGIC;
\adr_i_reg[1]\ : in STD_LOGIC;
\timing_param_tsudat_i_reg[6]\ : in STD_LOGIC;
\adr_i_reg[0]\ : in STD_LOGIC;
\timing_param_tsudat_i_reg[7]\ : in STD_LOGIC;
Tx_fifo_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsusta_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsusto_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Rc_fifo_data : in STD_LOGIC_VECTOR ( 0 to 7 );
\timing_param_thigh_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\timing_param_tbuf_i_reg[1]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[0]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[2]\ : in STD_LOGIC;
\sr_i_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_thddat_i_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_tbuf_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
Tx_addr : in STD_LOGIC_VECTOR ( 0 to 3 );
\GPO_GEN.gpo_i_reg[31]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]_1\ : in STD_LOGIC;
cr_txModeSelect_set : in STD_LOGIC;
cr_txModeSelect_clr : in STD_LOGIC;
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
\sr_i_reg[4]\ : in STD_LOGIC;
\sr_i_reg[5]\ : in STD_LOGIC;
\IIC2Bus_IntrEvent_reg[5]\ : in STD_LOGIC;
gpo : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_slave_attachment : entity is "slave_attachment";
end system_axi_iic_0_0_slave_attachment;
architecture STRUCTURE of system_axi_iic_0_0_slave_attachment is
signal AXI_IP2Bus_Data : STD_LOGIC_VECTOR ( 24 to 31 );
signal AXI_IP2Bus_Error : STD_LOGIC;
signal Bus2IIC_Addr : STD_LOGIC_VECTOR ( 0 to 1 );
signal IIC2Bus_Data : STD_LOGIC_VECTOR ( 22 to 23 );
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal I_DECODER_n_0 : STD_LOGIC;
signal I_DECODER_n_1 : STD_LOGIC;
signal I_DECODER_n_3 : STD_LOGIC;
signal I_DECODER_n_47 : STD_LOGIC;
signal I_DECODER_n_5 : STD_LOGIC;
signal Intr2Bus_DBus : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \bus2ip_addr_i[0]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[1]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[5]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[6]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[7]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[0]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[1]\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal bus2ip_rnw_i_reg_n_0 : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_5_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_7_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_9_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_8_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_9_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_5_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_8_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_6_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_7_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_8_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_5_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_6_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_7_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_9_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_5_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_6_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_7_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_9_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_6_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_7_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_6_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_7_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i0 : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \s_axi_rdata_i[3]_i_8\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \s_axi_rdata_i[5]_i_7\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \state[0]_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair49";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
s_axi_bresp(0) <= \^s_axi_bresp\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_iic_0_0_address_decoder
port map (
AXI_IP2Bus_Error => AXI_IP2Bus_Error,
AXI_IP2Bus_RdAck1 => AXI_IP2Bus_RdAck1,
AXI_IP2Bus_RdAck2 => AXI_IP2Bus_RdAck2,
AXI_IP2Bus_RdAck20 => AXI_IP2Bus_RdAck20,
AXI_IP2Bus_WrAck1 => AXI_IP2Bus_WrAck1,
AXI_IP2Bus_WrAck2 => AXI_IP2Bus_WrAck2,
AXI_IP2Bus_WrAck2_reg => AXI_IP2Bus_WrAck2_reg,
\Addr_Counters[1].FDRE_I\ => \s_axi_rdata_i[1]_i_3_n_0\,
\Addr_Counters[2].FDRE_I\ => \s_axi_rdata_i[2]_i_4_n_0\,
Bus2IIC_RdCE(0) => Bus2IIC_RdCE(0),
Bus2IIC_WrCE(11 downto 0) => Bus2IIC_WrCE(11 downto 0),
D(10) => Intr2Bus_DBus(0),
D(9) => IIC2Bus_Data(22),
D(8) => IIC2Bus_Data(23),
D(7) => AXI_IP2Bus_Data(24),
D(6) => AXI_IP2Bus_Data(25),
D(5) => AXI_IP2Bus_Data(26),
D(4) => AXI_IP2Bus_Data(27),
D(3) => AXI_IP2Bus_Data(28),
D(2) => AXI_IP2Bus_Data(29),
D(1) => AXI_IP2Bus_Data(30),
D(0) => AXI_IP2Bus_Data(31),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]_0\ => I_DECODER_n_1,
\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]_0\ => I_DECODER_n_0,
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]_0\ => I_DECODER_n_5,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\,
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\,
\GPO_GEN.gpo_i_reg[31]\ => \GPO_GEN.gpo_i_reg[31]\,
IIC2Bus_IntrEvent(0 to 7) => IIC2Bus_IntrEvent(0 to 7),
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => I_DECODER_n_3,
Q => start2,
\adr_i_reg[0]\ => \adr_i_reg[0]\,
\adr_i_reg[1]\ => \adr_i_reg[1]\,
\adr_i_reg[2]\ => \adr_i_reg[2]\,
\adr_i_reg[3]\ => \adr_i_reg[3]\,
\adr_i_reg[4]\ => \adr_i_reg[4]\,
\adr_i_reg[5]\ => \adr_i_reg[5]\,
\adr_i_reg[6]\ => \adr_i_reg[6]\,
\bus2ip_addr_i_reg[2]\ => \s_axi_rdata_i[3]_i_3_n_0\,
\bus2ip_addr_i_reg[2]_0\ => \bus2ip_addr_i_reg[2]_0\,
\bus2ip_addr_i_reg[2]_1\ => \bus2ip_addr_i_reg[2]_1\,
\bus2ip_addr_i_reg[5]\ => \s_axi_rdata_i[4]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_0\ => \s_axi_rdata_i[4]_i_5_n_0\,
\bus2ip_addr_i_reg[5]_1\ => \s_axi_rdata_i[5]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_2\ => \s_axi_rdata_i[5]_i_5_n_0\,
\bus2ip_addr_i_reg[5]_3\ => \s_axi_rdata_i[6]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_4\ => \s_axi_rdata_i[7]_i_3_n_0\,
\bus2ip_addr_i_reg[6]\ => \s_axi_rdata_i[0]_i_3_n_0\,
\bus2ip_addr_i_reg[8]\(8) => Bus2IIC_Addr(0),
\bus2ip_addr_i_reg[8]\(7) => Bus2IIC_Addr(1),
\bus2ip_addr_i_reg[8]\(6 downto 2) => \^q\(4 downto 0),
\bus2ip_addr_i_reg[8]\(1) => \bus2ip_addr_i_reg_n_0_[1]\,
\bus2ip_addr_i_reg[8]\(0) => \bus2ip_addr_i_reg_n_0_[0]\,
bus2ip_rnw_i_reg => bus2ip_rnw_i_reg_n_0,
\cr_i_reg[4]\(0) => \cr_i_reg[4]\(0),
\cr_i_reg[4]_0\(0) => \cr_i_reg[4]_0\(1),
cr_txModeSelect_clr => cr_txModeSelect_clr,
cr_txModeSelect_set => cr_txModeSelect_set,
gpo(0) => gpo(0),
\ip_irpt_enable_reg_reg[7]\(7 downto 0) => \ip_irpt_enable_reg_reg[7]\(7 downto 0),
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_1_in => p_1_in,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in2_in => p_1_in2_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => p_1_in8_in,
reset_trig0 => reset_trig0,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_bresp(0) => \^s_axi_bresp\(0),
\s_axi_bresp_i_reg[1]\ => I_DECODER_n_47,
s_axi_wdata(8 downto 0) => s_axi_wdata(8 downto 0),
s_axi_wready => \^s_axi_wready\,
\state_reg[1]\(1 downto 0) => state(1 downto 0),
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
\timing_param_tbuf_i_reg[3]\ => \timing_param_tbuf_i_reg[3]\,
\timing_param_thdsta_i_reg[0]\ => \s_axi_rdata_i[0]_i_4_n_0\,
\timing_param_thigh_i_reg[0]\ => \s_axi_rdata_i[0]_i_5_n_0\,
\timing_param_thigh_i_reg[1]\ => \s_axi_rdata_i[1]_i_4_n_0\,
\timing_param_thigh_i_reg[2]\ => \s_axi_rdata_i[2]_i_5_n_0\,
\timing_param_tsudat_i_reg[6]\ => \timing_param_tsudat_i_reg[6]\,
\timing_param_tsudat_i_reg[7]\ => \timing_param_tsudat_i_reg[7]\
);
\bus2ip_addr_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[0]_i_1_n_0\
);
\bus2ip_addr_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[1]_i_1_n_0\
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(3),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(4),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(5),
O => \bus2ip_addr_i[5]_i_1_n_0\
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(6),
O => \bus2ip_addr_i[6]_i_1_n_0\
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(7),
O => \bus2ip_addr_i[7]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_wvalid,
I2 => s_axi_awvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(8),
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[0]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[0]\,
R => rst
);
\bus2ip_addr_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[1]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[1]\,
R => rst
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \^q\(0),
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \^q\(1),
R => rst
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_1_n_0\,
Q => \^q\(2),
R => rst
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[5]_i_1_n_0\,
Q => \^q\(3),
R => rst
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[6]_i_1_n_0\,
Q => \^q\(4),
R => rst
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[7]_i_1_n_0\,
Q => Bus2IIC_Addr(1),
R => rst
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => Bus2IIC_Addr(0),
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => bus2ip_rnw_i_reg_n_0,
R => rst
);
is_read_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => s_axi_arvalid,
I1 => state(1),
I2 => is_write,
I3 => is_read,
O => is_read_i_1_n_0
);
is_read_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"AA80808055555555"
)
port map (
I0 => state(0),
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_bvalid\,
I4 => s_axi_bready,
I5 => state(1),
O => is_write
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => rst
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0008FFFF00080000"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_Bus2IP_Reset,
Q => rst,
R => '0'
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => I_DECODER_n_3,
I1 => is_read,
I2 => AXI_IP2Bus_RdAck1,
I3 => AXI_IP2Bus_RdAck2,
O => s_axi_arready
);
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_47,
Q => \^s_axi_bresp\(0),
R => rst
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"5D550C00"
)
port map (
I0 => s_axi_bready,
I1 => state(1),
I2 => state(0),
I3 => \^s_axi_wready\,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFBFFFFABFB0000"
)
port map (
I0 => \^q\(4),
I1 => Tx_addr(0),
I2 => \^q\(3),
I3 => \timing_param_tsudat_i_reg[5]\(0),
I4 => \^q\(2),
I5 => \GPO_GEN.gpo_i_reg[31]_0\,
O => \s_axi_rdata_i[0]_i_3_n_0\
);
\s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888088888888888"
)
port map (
I0 => \s_axi_rdata_i[0]_i_7_n_0\,
I1 => I_DECODER_n_1,
I2 => \timing_param_thdsta_i_reg[0]\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(3),
O => \s_axi_rdata_i[0]_i_4_n_0\
);
\s_axi_rdata_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F4F44444444"
)
port map (
I0 => \timing_param_tbuf_i_reg[0]\,
I1 => I_DECODER_n_0,
I2 => \s_axi_rdata_i[1]_i_8_n_0\,
I3 => \s_axi_rdata_i[3]_i_8_n_0\,
I4 => \timing_param_thigh_i_reg[7]\(0),
I5 => \s_axi_rdata_i[0]_i_9_n_0\,
O => \s_axi_rdata_i[0]_i_5_n_0\
);
\s_axi_rdata_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFAABFBFFFFABFB"
)
port map (
I0 => \^q\(2),
I1 => \cr_i_reg[4]_0\(0),
I2 => \^q\(4),
I3 => \timing_param_tlow_i_reg[0]\(0),
I4 => \^q\(3),
I5 => \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\(0),
O => \s_axi_rdata_i[0]_i_7_n_0\
);
\s_axi_rdata_i[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEFFFEF"
)
port map (
I0 => \^q\(2),
I1 => \^q\(4),
I2 => Rc_fifo_data(7),
I3 => \^q\(3),
I4 => \timing_param_tsusto_i_reg[7]\(0),
O => \s_axi_rdata_i[0]_i_9_n_0\
);
\s_axi_rdata_i[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => Tx_addr(1),
I1 => \^q\(3),
I2 => \timing_param_tsudat_i_reg[5]\(1),
I3 => \^q\(4),
I4 => \^q\(2),
I5 => \IIC2Bus_IntrEvent_reg[5]\,
O => \s_axi_rdata_i[1]_i_3_n_0\
);
\s_axi_rdata_i[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"D0DDD0D0DDDDDDDD"
)
port map (
I0 => I_DECODER_n_0,
I1 => \timing_param_tbuf_i_reg[1]\,
I2 => \s_axi_rdata_i[1]_i_8_n_0\,
I3 => \s_axi_rdata_i[3]_i_8_n_0\,
I4 => \timing_param_thigh_i_reg[7]\(1),
I5 => \s_axi_rdata_i[1]_i_9_n_0\,
O => \s_axi_rdata_i[1]_i_4_n_0\
);
\s_axi_rdata_i[1]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => \^q\(0),
I1 => \^q\(4),
I2 => \^q\(1),
O => \s_axi_rdata_i[1]_i_8_n_0\
);
\s_axi_rdata_i[1]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEFFFEF"
)
port map (
I0 => \^q\(2),
I1 => \^q\(4),
I2 => Rc_fifo_data(6),
I3 => \^q\(3),
I4 => \timing_param_tsusto_i_reg[7]\(1),
O => \s_axi_rdata_i[1]_i_9_n_0\
);
\s_axi_rdata_i[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => Tx_addr(2),
I1 => \^q\(3),
I2 => \timing_param_tsudat_i_reg[5]\(2),
I3 => \^q\(4),
I4 => \^q\(2),
I5 => \sr_i_reg[5]\,
O => \s_axi_rdata_i[2]_i_4_n_0\
);
\s_axi_rdata_i[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"4545454545FF4545"
)
port map (
I0 => \s_axi_rdata_i[2]_i_8_n_0\,
I1 => \s_axi_rdata_i[3]_i_8_n_0\,
I2 => \timing_param_thigh_i_reg[7]\(2),
I3 => \timing_param_tbuf_i_reg[2]\,
I4 => \^q\(1),
I5 => \^q\(0),
O => \s_axi_rdata_i[2]_i_5_n_0\
);
\s_axi_rdata_i[2]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAEFEA"
)
port map (
I0 => \s_axi_rdata_i[1]_i_8_n_0\,
I1 => \timing_param_tsusto_i_reg[7]\(2),
I2 => \^q\(3),
I3 => Rc_fifo_data(5),
I4 => \^q\(4),
I5 => \^q\(2),
O => \s_axi_rdata_i[2]_i_8_n_0\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"04FF040404FF04FF"
)
port map (
I0 => \s_axi_rdata_i[3]_i_6_n_0\,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \s_axi_rdata_i[3]_i_7_n_0\,
I4 => \s_axi_rdata_i[3]_i_8_n_0\,
I5 => \timing_param_thigh_i_reg[7]\(3),
O => \s_axi_rdata_i[3]_i_3_n_0\
);
\s_axi_rdata_i[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E2FFFF00E20000"
)
port map (
I0 => Tx_addr(3),
I1 => \^q\(3),
I2 => \timing_param_tsudat_i_reg[5]\(3),
I3 => \^q\(4),
I4 => \^q\(2),
I5 => \sr_i_reg[4]\,
O => \s_axi_rdata_i[3]_i_6_n_0\
);
\s_axi_rdata_i[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000000B8"
)
port map (
I0 => \timing_param_tsusto_i_reg[7]\(3),
I1 => \^q\(3),
I2 => Rc_fifo_data(4),
I3 => \^q\(4),
I4 => \^q\(2),
I5 => \s_axi_rdata_i[1]_i_8_n_0\,
O => \s_axi_rdata_i[3]_i_7_n_0\
);
\s_axi_rdata_i[3]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
I2 => \^q\(2),
O => \s_axi_rdata_i[3]_i_8_n_0\
);
\s_axi_rdata_i[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"88800080AAAAAAAA"
)
port map (
I0 => \s_axi_rdata_i[4]_i_6_n_0\,
I1 => I_DECODER_n_5,
I2 => Tx_fifo_data(0),
I3 => \^q\(3),
I4 => \timing_param_tsusta_i_reg[7]\(0),
I5 => \s_axi_rdata_i[4]_i_7_n_0\,
O => \s_axi_rdata_i[4]_i_3_n_0\
);
\s_axi_rdata_i[4]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFABFB"
)
port map (
I0 => \^q\(3),
I1 => \sr_i_reg[2]\(0),
I2 => \^q\(4),
I3 => \timing_param_thddat_i_reg[5]\(0),
I4 => \^q\(2),
I5 => \s_axi_rdata_i[4]_i_9_n_0\,
O => \s_axi_rdata_i[4]_i_5_n_0\
);
\s_axi_rdata_i[4]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDD55F555DD55F5"
)
port map (
I0 => \^q\(0),
I1 => \timing_param_tsusto_i_reg[7]\(4),
I2 => Rc_fifo_data(3),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \timing_param_thigh_i_reg[7]\(4),
O => \s_axi_rdata_i[4]_i_6_n_0\
);
\s_axi_rdata_i[4]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABFFF"
)
port map (
I0 => \^q\(4),
I1 => \timing_param_tbuf_i_reg[7]\(0),
I2 => \^q\(2),
I3 => \^q\(3),
I4 => \^q\(0),
O => \s_axi_rdata_i[4]_i_7_n_0\
);
\s_axi_rdata_i[4]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2000FFFFFFFF"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
I2 => \^q\(2),
I3 => \timing_param_tsudat_i_reg[5]\(4),
I4 => \^q\(1),
I5 => \^q\(0),
O => \s_axi_rdata_i[4]_i_9_n_0\
);
\s_axi_rdata_i[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"88800080AAAAAAAA"
)
port map (
I0 => \s_axi_rdata_i[5]_i_6_n_0\,
I1 => I_DECODER_n_5,
I2 => Tx_fifo_data(1),
I3 => \^q\(3),
I4 => \timing_param_tsusta_i_reg[7]\(1),
I5 => \s_axi_rdata_i[5]_i_7_n_0\,
O => \s_axi_rdata_i[5]_i_3_n_0\
);
\s_axi_rdata_i[5]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFABFB"
)
port map (
I0 => \^q\(3),
I1 => \sr_i_reg[2]\(1),
I2 => \^q\(4),
I3 => \timing_param_thddat_i_reg[5]\(1),
I4 => \^q\(2),
I5 => \s_axi_rdata_i[5]_i_9_n_0\,
O => \s_axi_rdata_i[5]_i_5_n_0\
);
\s_axi_rdata_i[5]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDD55F555DD55F5"
)
port map (
I0 => \^q\(0),
I1 => \timing_param_tsusto_i_reg[7]\(5),
I2 => Rc_fifo_data(2),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \timing_param_thigh_i_reg[7]\(5),
O => \s_axi_rdata_i[5]_i_6_n_0\
);
\s_axi_rdata_i[5]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABFFF"
)
port map (
I0 => \^q\(4),
I1 => \timing_param_tbuf_i_reg[7]\(1),
I2 => \^q\(2),
I3 => \^q\(3),
I4 => \^q\(0),
O => \s_axi_rdata_i[5]_i_7_n_0\
);
\s_axi_rdata_i[5]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2000FFFFFFFF"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
I2 => \^q\(2),
I3 => \timing_param_tsudat_i_reg[5]\(5),
I4 => \^q\(1),
I5 => \^q\(0),
O => \s_axi_rdata_i[5]_i_9_n_0\
);
\s_axi_rdata_i[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"88800080AAAAAAAA"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => I_DECODER_n_5,
I2 => Tx_fifo_data(2),
I3 => \^q\(3),
I4 => \timing_param_tsusta_i_reg[7]\(2),
I5 => \s_axi_rdata_i[6]_i_7_n_0\,
O => \s_axi_rdata_i[6]_i_3_n_0\
);
\s_axi_rdata_i[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDD55F555DD55F5"
)
port map (
I0 => \^q\(0),
I1 => \timing_param_tsusto_i_reg[7]\(6),
I2 => Rc_fifo_data(1),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \timing_param_thigh_i_reg[7]\(6),
O => \s_axi_rdata_i[6]_i_6_n_0\
);
\s_axi_rdata_i[6]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABFFF"
)
port map (
I0 => \^q\(4),
I1 => \timing_param_tbuf_i_reg[7]\(2),
I2 => \^q\(2),
I3 => \^q\(3),
I4 => \^q\(0),
O => \s_axi_rdata_i[6]_i_7_n_0\
);
\s_axi_rdata_i[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"88800080AAAAAAAA"
)
port map (
I0 => \s_axi_rdata_i[7]_i_6_n_0\,
I1 => I_DECODER_n_5,
I2 => Tx_fifo_data(3),
I3 => \^q\(3),
I4 => \timing_param_tsusta_i_reg[7]\(3),
I5 => \s_axi_rdata_i[7]_i_7_n_0\,
O => \s_axi_rdata_i[7]_i_3_n_0\
);
\s_axi_rdata_i[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDD55F555DD55F5"
)
port map (
I0 => \^q\(0),
I1 => \timing_param_tsusto_i_reg[7]\(7),
I2 => Rc_fifo_data(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \timing_param_thigh_i_reg[7]\(7),
O => \s_axi_rdata_i[7]_i_6_n_0\
);
\s_axi_rdata_i[7]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABFFF"
)
port map (
I0 => \^q\(4),
I1 => \timing_param_tbuf_i_reg[7]\(3),
I2 => \^q\(2),
I3 => \^q\(3),
I4 => \^q\(0),
O => \s_axi_rdata_i[7]_i_7_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Data(31),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Data(30),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Data(29),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => Intr2Bus_DBus(0),
Q => s_axi_rdata(10),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Data(28),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Data(27),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Data(26),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Data(25),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Data(24),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IIC2Bus_Data(23),
Q => s_axi_rdata(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IIC2Bus_Data(22),
Q => s_axi_rdata(9),
R => rst
);
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => AXI_IP2Bus_Error,
Q => s_axi_rresp(0),
R => rst
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"DC"
)
port map (
I0 => s_axi_rready,
I1 => s_axi_rvalid_i0,
I2 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000022F200000000"
)
port map (
I0 => AXI_IP2Bus_RdAck2,
I1 => AXI_IP2Bus_RdAck1,
I2 => is_read,
I3 => I_DECODER_n_3,
I4 => state(1),
I5 => state(0),
O => s_axi_rvalid_i0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => rst
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000F0008"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => state(1),
I3 => state(0),
I4 => s_axi_arvalid,
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2F2CEFEC"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => \state[0]_i_2_n_0\,
O => \state[0]_i_1_n_0\
);
\state[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFAFAE"
)
port map (
I0 => s_axi_rvalid_i0,
I1 => state(1),
I2 => state(0),
I3 => \state[1]_i_2_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(1),
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_axi_lite_ipif is
port (
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
AXI_IP2Bus_WrAck2_reg : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
Bus2IIC_RdCE : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus2IIC_WrCE : out STD_LOGIC_VECTOR ( 11 downto 0 );
AXI_IP2Bus_RdAck20 : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
\GPO_GEN.gpo_i_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
AXI_Bus2IP_Reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\timing_param_tsudat_i_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\cr_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_tlow_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AXI_IP2Bus_RdAck1 : in STD_LOGIC;
AXI_IP2Bus_RdAck2 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
AXI_IP2Bus_WrAck1 : in STD_LOGIC;
AXI_IP2Bus_WrAck2 : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 8 downto 0 );
irpt_wrack_d1 : in STD_LOGIC;
IIC2Bus_IntrEvent : in STD_LOGIC_VECTOR ( 0 to 7 );
p_1_in : in STD_LOGIC;
p_1_in2_in : in STD_LOGIC;
p_1_in5_in : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
p_1_in14_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
\ip_irpt_enable_reg_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\timing_param_thdsta_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\adr_i_reg[6]\ : in STD_LOGIC;
\adr_i_reg[5]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[3]\ : in STD_LOGIC;
\adr_i_reg[4]\ : in STD_LOGIC;
\adr_i_reg[3]\ : in STD_LOGIC;
\adr_i_reg[2]\ : in STD_LOGIC;
\adr_i_reg[1]\ : in STD_LOGIC;
\timing_param_tsudat_i_reg[6]\ : in STD_LOGIC;
\adr_i_reg[0]\ : in STD_LOGIC;
\timing_param_tsudat_i_reg[7]\ : in STD_LOGIC;
Tx_fifo_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsusta_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsusto_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Rc_fifo_data : in STD_LOGIC_VECTOR ( 0 to 7 );
\timing_param_thigh_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\timing_param_tbuf_i_reg[1]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[0]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[2]\ : in STD_LOGIC;
\sr_i_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_thddat_i_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_tbuf_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
Tx_addr : in STD_LOGIC_VECTOR ( 0 to 3 );
\GPO_GEN.gpo_i_reg[31]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]_0\ : in STD_LOGIC;
cr_txModeSelect_set : in STD_LOGIC;
cr_txModeSelect_clr : in STD_LOGIC;
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
\sr_i_reg[4]\ : in STD_LOGIC;
\sr_i_reg[5]\ : in STD_LOGIC;
\IIC2Bus_IntrEvent_reg[5]\ : in STD_LOGIC;
gpo : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_iic_0_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_iic_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_iic_0_0_slave_attachment
port map (
AXI_Bus2IP_Reset => AXI_Bus2IP_Reset,
AXI_IP2Bus_RdAck1 => AXI_IP2Bus_RdAck1,
AXI_IP2Bus_RdAck2 => AXI_IP2Bus_RdAck2,
AXI_IP2Bus_RdAck20 => AXI_IP2Bus_RdAck20,
AXI_IP2Bus_WrAck1 => AXI_IP2Bus_WrAck1,
AXI_IP2Bus_WrAck2 => AXI_IP2Bus_WrAck2,
AXI_IP2Bus_WrAck2_reg => AXI_IP2Bus_WrAck2_reg,
Bus2IIC_RdCE(0) => Bus2IIC_RdCE(0),
Bus2IIC_WrCE(11 downto 0) => Bus2IIC_WrCE(11 downto 0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\,
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\,
\GPO_GEN.gpo_i_reg[31]\ => \GPO_GEN.gpo_i_reg[31]\,
\GPO_GEN.gpo_i_reg[31]_0\ => \GPO_GEN.gpo_i_reg[31]_0\,
IIC2Bus_IntrEvent(0 to 7) => IIC2Bus_IntrEvent(0 to 7),
\IIC2Bus_IntrEvent_reg[5]\ => \IIC2Bus_IntrEvent_reg[5]\,
Q(4 downto 0) => Q(4 downto 0),
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\(0) => \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\(0),
Rc_fifo_data(0 to 7) => Rc_fifo_data(0 to 7),
Tx_addr(0 to 3) => Tx_addr(0 to 3),
Tx_fifo_data(3 downto 0) => Tx_fifo_data(3 downto 0),
\adr_i_reg[0]\ => \adr_i_reg[0]\,
\adr_i_reg[1]\ => \adr_i_reg[1]\,
\adr_i_reg[2]\ => \adr_i_reg[2]\,
\adr_i_reg[3]\ => \adr_i_reg[3]\,
\adr_i_reg[4]\ => \adr_i_reg[4]\,
\adr_i_reg[5]\ => \adr_i_reg[5]\,
\adr_i_reg[6]\ => \adr_i_reg[6]\,
\bus2ip_addr_i_reg[2]_0\ => \bus2ip_addr_i_reg[2]\,
\bus2ip_addr_i_reg[2]_1\ => \bus2ip_addr_i_reg[2]_0\,
\cr_i_reg[4]\(0) => \cr_i_reg[4]\(0),
\cr_i_reg[4]_0\(1 downto 0) => \cr_i_reg[4]_0\(1 downto 0),
cr_txModeSelect_clr => cr_txModeSelect_clr,
cr_txModeSelect_set => cr_txModeSelect_set,
gpo(0) => gpo(0),
\ip_irpt_enable_reg_reg[7]\(7 downto 0) => \ip_irpt_enable_reg_reg[7]\(7 downto 0),
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_1_in => p_1_in,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in2_in => p_1_in2_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => p_1_in8_in,
reset_trig0 => reset_trig0,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(10 downto 0) => s_axi_rdata(10 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(8 downto 0) => s_axi_wdata(8 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
\sr_i_reg[2]\(1 downto 0) => \sr_i_reg[2]\(1 downto 0),
\sr_i_reg[4]\ => \sr_i_reg[4]\,
\sr_i_reg[5]\ => \sr_i_reg[5]\,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
\timing_param_tbuf_i_reg[0]\ => \timing_param_tbuf_i_reg[0]\,
\timing_param_tbuf_i_reg[1]\ => \timing_param_tbuf_i_reg[1]\,
\timing_param_tbuf_i_reg[2]\ => \timing_param_tbuf_i_reg[2]\,
\timing_param_tbuf_i_reg[3]\ => \timing_param_tbuf_i_reg[3]\,
\timing_param_tbuf_i_reg[7]\(3 downto 0) => \timing_param_tbuf_i_reg[7]\(3 downto 0),
\timing_param_thddat_i_reg[5]\(1 downto 0) => \timing_param_thddat_i_reg[5]\(1 downto 0),
\timing_param_thdsta_i_reg[0]\(0) => \timing_param_thdsta_i_reg[0]\(0),
\timing_param_thigh_i_reg[7]\(7 downto 0) => \timing_param_thigh_i_reg[7]\(7 downto 0),
\timing_param_tlow_i_reg[0]\(0) => \timing_param_tlow_i_reg[0]\(0),
\timing_param_tsudat_i_reg[5]\(5 downto 0) => \timing_param_tsudat_i_reg[5]\(5 downto 0),
\timing_param_tsudat_i_reg[6]\ => \timing_param_tsudat_i_reg[6]\,
\timing_param_tsudat_i_reg[7]\ => \timing_param_tsudat_i_reg[7]\,
\timing_param_tsusta_i_reg[7]\(3 downto 0) => \timing_param_tsusta_i_reg[7]\(3 downto 0),
\timing_param_tsusto_i_reg[7]\(7 downto 0) => \timing_param_tsusto_i_reg[7]\(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_filter is
port (
detect_stop_b_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
scl_rising_edge0 : out STD_LOGIC;
scl_rin_d1_reg : out STD_LOGIC;
sda_rin_d1 : in STD_LOGIC;
scl_rin_d1 : in STD_LOGIC;
scl_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
sda_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_filter : entity is "filter";
end system_axi_iic_0_0_filter;
architecture STRUCTURE of system_axi_iic_0_0_filter is
begin
SCL_DEBOUNCE: entity work.system_axi_iic_0_0_debounce
port map (
s_axi_aclk => s_axi_aclk,
scl_i => scl_i,
scl_rin_d1 => scl_rin_d1,
scl_rin_d1_reg => scl_rin_d1_reg,
scl_rising_edge0 => scl_rising_edge0
);
SDA_DEBOUNCE: entity work.system_axi_iic_0_0_debounce_3
port map (
detect_stop_b_reg => detect_stop_b_reg,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sda_i => sda_i,
sda_rin_d1 => sda_rin_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_axi_ipif_ssp1 is
port (
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus2IIC_Reset : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
ctrlFifoDin : out STD_LOGIC_VECTOR ( 0 to 1 );
Bus2IIC_RdCE : out STD_LOGIC_VECTOR ( 0 to 0 );
\cr_i_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus2IIC_WrCE : out STD_LOGIC_VECTOR ( 11 downto 0 );
iic2intc_irpt : out STD_LOGIC;
\GPO_GEN.gpo_i_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
\timing_param_tsudat_i_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\cr_i_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_tlow_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 10 downto 0 );
IIC2Bus_IntrEvent : in STD_LOGIC_VECTOR ( 0 to 7 );
Tx_fifo_rst : in STD_LOGIC;
\timing_param_thdsta_i_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\adr_i_reg[6]\ : in STD_LOGIC;
\adr_i_reg[5]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[3]\ : in STD_LOGIC;
\adr_i_reg[4]\ : in STD_LOGIC;
\adr_i_reg[3]\ : in STD_LOGIC;
\adr_i_reg[2]\ : in STD_LOGIC;
\adr_i_reg[1]\ : in STD_LOGIC;
\timing_param_tsudat_i_reg[6]\ : in STD_LOGIC;
\adr_i_reg[0]\ : in STD_LOGIC;
\timing_param_tsudat_i_reg[7]\ : in STD_LOGIC;
Tx_fifo_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsusta_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\timing_param_tsusto_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Rc_fifo_data : in STD_LOGIC_VECTOR ( 0 to 7 );
\timing_param_thigh_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\timing_param_tbuf_i_reg[1]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[0]\ : in STD_LOGIC;
\timing_param_tbuf_i_reg[2]\ : in STD_LOGIC;
\sr_i_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_thddat_i_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\timing_param_tbuf_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
Tx_addr : in STD_LOGIC_VECTOR ( 0 to 3 );
\GPO_GEN.gpo_i_reg[31]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]_0\ : in STD_LOGIC;
cr_txModeSelect_set : in STD_LOGIC;
cr_txModeSelect_clr : in STD_LOGIC;
\sr_i_reg[4]\ : in STD_LOGIC;
\sr_i_reg[5]\ : in STD_LOGIC;
\IIC2Bus_IntrEvent_reg[5]\ : in STD_LOGIC;
gpo : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_axi_ipif_ssp1 : entity is "axi_ipif_ssp1";
end system_axi_iic_0_0_axi_ipif_ssp1;
architecture STRUCTURE of system_axi_iic_0_0_axi_ipif_ssp1 is
signal AXI_Bus2IP_Reset : STD_LOGIC;
signal AXI_Bus2IP_WrCE : STD_LOGIC_VECTOR ( 10 to 10 );
signal AXI_IP2Bus_RdAck1 : STD_LOGIC;
signal AXI_IP2Bus_RdAck2 : STD_LOGIC;
signal AXI_IP2Bus_RdAck20 : STD_LOGIC;
signal AXI_IP2Bus_WrAck1 : STD_LOGIC;
signal AXI_IP2Bus_WrAck2 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_19 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_20 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_39 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_9 : STD_LOGIC;
signal \^bus2iic_reset\ : STD_LOGIC;
signal X_INTERRUPT_CONTROL_n_1 : STD_LOGIC;
signal X_INTERRUPT_CONTROL_n_18 : STD_LOGIC;
signal ipif_glbl_irpt_enable_reg : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_0_in10_in : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_0_in16_in : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal p_0_in4_in : STD_LOGIC;
signal p_0_in7_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_1_in11_in : STD_LOGIC;
signal p_1_in14_in : STD_LOGIC;
signal p_1_in17_in : STD_LOGIC;
signal p_1_in2_in : STD_LOGIC;
signal p_1_in5_in : STD_LOGIC;
signal p_1_in8_in : STD_LOGIC;
signal reset_trig0 : STD_LOGIC;
signal sw_rst_cond : STD_LOGIC;
signal sw_rst_cond_d1 : STD_LOGIC;
begin
Bus2IIC_Reset <= \^bus2iic_reset\;
AXI_IP2Bus_RdAck1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_IP2Bus_RdAck2,
Q => AXI_IP2Bus_RdAck1,
R => '0'
);
AXI_IP2Bus_RdAck2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_IP2Bus_RdAck20,
Q => AXI_IP2Bus_RdAck2,
R => '0'
);
AXI_IP2Bus_WrAck1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_IP2Bus_WrAck2,
Q => AXI_IP2Bus_WrAck1,
R => '0'
);
AXI_IP2Bus_WrAck2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_9,
Q => AXI_IP2Bus_WrAck2,
R => '0'
);
AXI_LITE_IPIF_I: entity work.system_axi_iic_0_0_axi_lite_ipif
port map (
AXI_Bus2IP_Reset => AXI_Bus2IP_Reset,
AXI_IP2Bus_RdAck1 => AXI_IP2Bus_RdAck1,
AXI_IP2Bus_RdAck2 => AXI_IP2Bus_RdAck2,
AXI_IP2Bus_RdAck20 => AXI_IP2Bus_RdAck20,
AXI_IP2Bus_WrAck1 => AXI_IP2Bus_WrAck1,
AXI_IP2Bus_WrAck2 => AXI_IP2Bus_WrAck2,
AXI_IP2Bus_WrAck2_reg => AXI_LITE_IPIF_I_n_9,
Bus2IIC_RdCE(0) => Bus2IIC_RdCE(0),
Bus2IIC_WrCE(11 downto 0) => Bus2IIC_WrCE(11 downto 0),
E(0) => AXI_Bus2IP_WrCE(10),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => AXI_LITE_IPIF_I_n_20,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => X_INTERRUPT_CONTROL_n_1,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => AXI_LITE_IPIF_I_n_19,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ => AXI_LITE_IPIF_I_n_18,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => AXI_LITE_IPIF_I_n_17,
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ => AXI_LITE_IPIF_I_n_16,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ => AXI_LITE_IPIF_I_n_15,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ => AXI_LITE_IPIF_I_n_14,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ => AXI_LITE_IPIF_I_n_13,
\GPO_GEN.gpo_i_reg[31]\ => \GPO_GEN.gpo_i_reg[31]\,
\GPO_GEN.gpo_i_reg[31]_0\ => \GPO_GEN.gpo_i_reg[31]_0\,
IIC2Bus_IntrEvent(0 to 7) => IIC2Bus_IntrEvent(0 to 7),
\IIC2Bus_IntrEvent_reg[5]\ => \IIC2Bus_IntrEvent_reg[5]\,
Q(4 downto 0) => Q(4 downto 0),
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\(0) => \RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\(0),
Rc_fifo_data(0 to 7) => Rc_fifo_data(0 to 7),
Tx_addr(0 to 3) => Tx_addr(0 to 3),
Tx_fifo_data(3 downto 0) => Tx_fifo_data(3 downto 0),
\adr_i_reg[0]\ => \adr_i_reg[0]\,
\adr_i_reg[1]\ => \adr_i_reg[1]\,
\adr_i_reg[2]\ => \adr_i_reg[2]\,
\adr_i_reg[3]\ => \adr_i_reg[3]\,
\adr_i_reg[4]\ => \adr_i_reg[4]\,
\adr_i_reg[5]\ => \adr_i_reg[5]\,
\adr_i_reg[6]\ => \adr_i_reg[6]\,
\bus2ip_addr_i_reg[2]\ => \bus2ip_addr_i_reg[2]\,
\bus2ip_addr_i_reg[2]_0\ => \bus2ip_addr_i_reg[2]_0\,
\cr_i_reg[4]\(0) => \cr_i_reg[4]\(0),
\cr_i_reg[4]_0\(1 downto 0) => \cr_i_reg[4]_0\(1 downto 0),
cr_txModeSelect_clr => cr_txModeSelect_clr,
cr_txModeSelect_set => cr_txModeSelect_set,
gpo(0) => gpo(0),
\ip_irpt_enable_reg_reg[7]\(7) => p_0_in16_in,
\ip_irpt_enable_reg_reg[7]\(6) => p_0_in13_in,
\ip_irpt_enable_reg_reg[7]\(5) => p_0_in10_in,
\ip_irpt_enable_reg_reg[7]\(4) => p_0_in7_in,
\ip_irpt_enable_reg_reg[7]\(3) => p_0_in4_in,
\ip_irpt_enable_reg_reg[7]\(2) => p_0_in1_in,
\ip_irpt_enable_reg_reg[7]\(1) => p_0_in,
\ip_irpt_enable_reg_reg[7]\(0) => X_INTERRUPT_CONTROL_n_18,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_39,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_1_in => p_1_in,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in2_in => p_1_in2_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => p_1_in8_in,
reset_trig0 => reset_trig0,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(10 downto 0) => s_axi_rdata(10 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(8) => s_axi_wdata(10),
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
\sr_i_reg[2]\(1 downto 0) => \sr_i_reg[2]\(1 downto 0),
\sr_i_reg[4]\ => \sr_i_reg[4]\,
\sr_i_reg[5]\ => \sr_i_reg[5]\,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
\timing_param_tbuf_i_reg[0]\ => \timing_param_tbuf_i_reg[0]\,
\timing_param_tbuf_i_reg[1]\ => \timing_param_tbuf_i_reg[1]\,
\timing_param_tbuf_i_reg[2]\ => \timing_param_tbuf_i_reg[2]\,
\timing_param_tbuf_i_reg[3]\ => \timing_param_tbuf_i_reg[3]\,
\timing_param_tbuf_i_reg[7]\(3 downto 0) => \timing_param_tbuf_i_reg[7]\(3 downto 0),
\timing_param_thddat_i_reg[5]\(1 downto 0) => \timing_param_thddat_i_reg[5]\(1 downto 0),
\timing_param_thdsta_i_reg[0]\(0) => \timing_param_thdsta_i_reg[0]\(0),
\timing_param_thigh_i_reg[7]\(7 downto 0) => \timing_param_thigh_i_reg[7]\(7 downto 0),
\timing_param_tlow_i_reg[0]\(0) => \timing_param_tlow_i_reg[0]\(0),
\timing_param_tsudat_i_reg[5]\(5 downto 0) => \timing_param_tsudat_i_reg[5]\(5 downto 0),
\timing_param_tsudat_i_reg[6]\ => \timing_param_tsudat_i_reg[6]\,
\timing_param_tsudat_i_reg[7]\ => \timing_param_tsudat_i_reg[7]\,
\timing_param_tsusta_i_reg[7]\(3 downto 0) => \timing_param_tsusta_i_reg[7]\(3 downto 0),
\timing_param_tsusto_i_reg[7]\(7 downto 0) => \timing_param_tsusto_i_reg[7]\(7 downto 0)
);
X_INTERRUPT_CONTROL: entity work.system_axi_iic_0_0_interrupt_control
port map (
Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_20,
Bus_RNW_reg_reg_0 => AXI_LITE_IPIF_I_n_19,
Bus_RNW_reg_reg_1 => AXI_LITE_IPIF_I_n_18,
Bus_RNW_reg_reg_2 => AXI_LITE_IPIF_I_n_17,
Bus_RNW_reg_reg_3 => AXI_LITE_IPIF_I_n_16,
Bus_RNW_reg_reg_4 => AXI_LITE_IPIF_I_n_15,
Bus_RNW_reg_reg_5 => AXI_LITE_IPIF_I_n_14,
Bus_RNW_reg_reg_6 => AXI_LITE_IPIF_I_n_13,
E(0) => AXI_Bus2IP_WrCE(10),
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ => AXI_LITE_IPIF_I_n_39,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => X_INTERRUPT_CONTROL_n_1,
Q(7) => p_0_in16_in,
Q(6) => p_0_in13_in,
Q(5) => p_0_in10_in,
Q(4) => p_0_in7_in,
Q(3) => p_0_in4_in,
Q(2) => p_0_in1_in,
Q(1) => p_0_in,
Q(0) => X_INTERRUPT_CONTROL_n_18,
SR(0) => \^bus2iic_reset\,
iic2intc_irpt => iic2intc_irpt,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_1_in => p_1_in,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in2_in => p_1_in2_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => p_1_in8_in,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
);
X_SOFT_RESET: entity work.system_axi_iic_0_0_soft_reset
port map (
AXI_Bus2IP_Reset => AXI_Bus2IP_Reset,
SR(0) => \^bus2iic_reset\,
Tx_fifo_rst => Tx_fifo_rst,
ctrlFifoDin(0 to 1) => ctrlFifoDin(0 to 1),
reset_trig0 => reset_trig0,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(1 downto 0) => s_axi_wdata(9 downto 8),
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_iic is
port (
s_axi_wready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
sda_t : out STD_LOGIC;
gpo : out STD_LOGIC_VECTOR ( 0 to 0 );
iic2intc_irpt : out STD_LOGIC;
scl_t : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
scl_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
sda_i : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_iic : entity is "iic";
end system_axi_iic_0_0_iic;
architecture STRUCTURE of system_axi_iic_0_0_iic is
signal Aas : STD_LOGIC;
signal Abgc : STD_LOGIC;
signal Al : STD_LOGIC;
signal Bb : STD_LOGIC;
signal Bus2IIC_Addr : STD_LOGIC_VECTOR ( 2 to 6 );
signal Bus2IIC_RdCE : STD_LOGIC_VECTOR ( 3 to 3 );
signal Bus2IIC_Reset : STD_LOGIC;
signal Bus2IIC_WrCE : STD_LOGIC_VECTOR ( 0 to 17 );
signal \CLKCNT/q_int_reg__0\ : STD_LOGIC_VECTOR ( 0 to 9 );
signal Cr : STD_LOGIC_VECTOR ( 1 to 7 );
signal D : STD_LOGIC;
signal DYN_MASTER_I_n_6 : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal D_1 : STD_LOGIC;
signal Data_i2c : STD_LOGIC_VECTOR ( 0 to 7 );
signal FILTER_I_n_0 : STD_LOGIC;
signal IIC2Bus_IntrEvent : STD_LOGIC_VECTOR ( 0 to 7 );
signal IIC_CONTROL_I_n_40 : STD_LOGIC;
signal IIC_CONTROL_I_n_50 : STD_LOGIC;
signal IIC_CONTROL_I_n_53 : STD_LOGIC;
signal IIC_CONTROL_I_n_62 : STD_LOGIC;
signal IIC_CONTROL_I_n_8 : STD_LOGIC;
signal Msms_set : STD_LOGIC;
signal New_rcv_dta : STD_LOGIC;
signal READ_FIFO_I_n_16 : STD_LOGIC;
signal REG_INTERFACE_I_n_101 : STD_LOGIC;
signal REG_INTERFACE_I_n_102 : STD_LOGIC;
signal REG_INTERFACE_I_n_103 : STD_LOGIC;
signal REG_INTERFACE_I_n_104 : STD_LOGIC;
signal REG_INTERFACE_I_n_105 : STD_LOGIC;
signal REG_INTERFACE_I_n_106 : STD_LOGIC;
signal REG_INTERFACE_I_n_107 : STD_LOGIC;
signal REG_INTERFACE_I_n_108 : STD_LOGIC;
signal REG_INTERFACE_I_n_109 : STD_LOGIC;
signal REG_INTERFACE_I_n_110 : STD_LOGIC;
signal REG_INTERFACE_I_n_111 : STD_LOGIC;
signal REG_INTERFACE_I_n_112 : STD_LOGIC;
signal REG_INTERFACE_I_n_113 : STD_LOGIC;
signal REG_INTERFACE_I_n_114 : STD_LOGIC;
signal REG_INTERFACE_I_n_118 : STD_LOGIC;
signal REG_INTERFACE_I_n_119 : STD_LOGIC;
signal REG_INTERFACE_I_n_120 : STD_LOGIC;
signal REG_INTERFACE_I_n_121 : STD_LOGIC;
signal REG_INTERFACE_I_n_122 : STD_LOGIC;
signal REG_INTERFACE_I_n_123 : STD_LOGIC;
signal REG_INTERFACE_I_n_124 : STD_LOGIC;
signal REG_INTERFACE_I_n_125 : STD_LOGIC;
signal REG_INTERFACE_I_n_126 : STD_LOGIC;
signal REG_INTERFACE_I_n_127 : STD_LOGIC;
signal REG_INTERFACE_I_n_128 : STD_LOGIC;
signal REG_INTERFACE_I_n_130 : STD_LOGIC;
signal REG_INTERFACE_I_n_131 : STD_LOGIC;
signal REG_INTERFACE_I_n_132 : STD_LOGIC;
signal REG_INTERFACE_I_n_26 : STD_LOGIC;
signal REG_INTERFACE_I_n_27 : STD_LOGIC;
signal REG_INTERFACE_I_n_28 : STD_LOGIC;
signal REG_INTERFACE_I_n_29 : STD_LOGIC;
signal REG_INTERFACE_I_n_30 : STD_LOGIC;
signal REG_INTERFACE_I_n_39 : STD_LOGIC;
signal REG_INTERFACE_I_n_40 : STD_LOGIC;
signal REG_INTERFACE_I_n_41 : STD_LOGIC;
signal REG_INTERFACE_I_n_42 : STD_LOGIC;
signal REG_INTERFACE_I_n_51 : STD_LOGIC;
signal REG_INTERFACE_I_n_52 : STD_LOGIC;
signal REG_INTERFACE_I_n_53 : STD_LOGIC;
signal REG_INTERFACE_I_n_54 : STD_LOGIC;
signal REG_INTERFACE_I_n_59 : STD_LOGIC;
signal REG_INTERFACE_I_n_60 : STD_LOGIC;
signal REG_INTERFACE_I_n_61 : STD_LOGIC;
signal REG_INTERFACE_I_n_62 : STD_LOGIC;
signal REG_INTERFACE_I_n_67 : STD_LOGIC;
signal REG_INTERFACE_I_n_68 : STD_LOGIC;
signal REG_INTERFACE_I_n_69 : STD_LOGIC;
signal REG_INTERFACE_I_n_70 : STD_LOGIC;
signal REG_INTERFACE_I_n_73 : STD_LOGIC;
signal REG_INTERFACE_I_n_74 : STD_LOGIC;
signal REG_INTERFACE_I_n_75 : STD_LOGIC;
signal REG_INTERFACE_I_n_76 : STD_LOGIC;
signal REG_INTERFACE_I_n_78 : STD_LOGIC;
signal REG_INTERFACE_I_n_79 : STD_LOGIC;
signal REG_INTERFACE_I_n_80 : STD_LOGIC;
signal REG_INTERFACE_I_n_81 : STD_LOGIC;
signal REG_INTERFACE_I_n_83 : STD_LOGIC;
signal REG_INTERFACE_I_n_84 : STD_LOGIC;
signal REG_INTERFACE_I_n_85 : STD_LOGIC;
signal REG_INTERFACE_I_n_95 : STD_LOGIC;
signal REG_INTERFACE_I_n_97 : STD_LOGIC;
signal REG_INTERFACE_I_n_98 : STD_LOGIC;
signal Rc_Data_Exists : STD_LOGIC;
signal Rc_addr : STD_LOGIC_VECTOR ( 0 to 3 );
signal Rc_fifo_data : STD_LOGIC_VECTOR ( 0 to 7 );
signal Rc_fifo_full : STD_LOGIC;
signal Rc_fifo_rd : STD_LOGIC;
signal Rc_fifo_rd_d : STD_LOGIC;
signal Rc_fifo_wr : STD_LOGIC;
signal Rc_fifo_wr_d : STD_LOGIC;
signal Ro_prev : STD_LOGIC;
signal \SETUP_CNT/q_int_reg__0\ : STD_LOGIC_VECTOR ( 0 to 9 );
signal Srw : STD_LOGIC;
signal Tx_addr : STD_LOGIC_VECTOR ( 0 to 3 );
signal Tx_data_exists : STD_LOGIC;
signal Tx_fifo_data : STD_LOGIC_VECTOR ( 0 to 7 );
signal Tx_fifo_full : STD_LOGIC;
signal Tx_fifo_rd : STD_LOGIC;
signal Tx_fifo_rd_d : STD_LOGIC;
signal Tx_fifo_rst : STD_LOGIC;
signal Tx_fifo_wr : STD_LOGIC;
signal Tx_fifo_wr_d : STD_LOGIC;
signal Tx_under_prev : STD_LOGIC;
signal Txer : STD_LOGIC;
signal WRITE_FIFO_CTRL_I_n_0 : STD_LOGIC;
signal WRITE_FIFO_CTRL_I_n_3 : STD_LOGIC;
signal WRITE_FIFO_I_n_15 : STD_LOGIC;
signal WRITE_FIFO_I_n_16 : STD_LOGIC;
signal WRITE_FIFO_I_n_17 : STD_LOGIC;
signal WRITE_FIFO_I_n_18 : STD_LOGIC;
signal WRITE_FIFO_I_n_19 : STD_LOGIC;
signal X_AXI_IPIF_SSP1_n_15 : STD_LOGIC;
signal X_AXI_IPIF_SSP1_n_29 : STD_LOGIC;
signal ackDataState : STD_LOGIC;
signal arb_lost : STD_LOGIC;
signal callingReadAccess : STD_LOGIC;
signal clk_cnt_en1 : STD_LOGIC;
signal clk_cnt_en11_out : STD_LOGIC;
signal clk_cnt_en12_out : STD_LOGIC;
signal cr_txModeSelect_clr : STD_LOGIC;
signal cr_txModeSelect_set : STD_LOGIC;
signal ctrlFifoDin : STD_LOGIC_VECTOR ( 0 to 1 );
signal dynamic_MSMS : STD_LOGIC_VECTOR ( 0 to 1 );
signal earlyAckDataState : STD_LOGIC;
signal earlyAckHdr : STD_LOGIC;
signal firstDynStartSeen : STD_LOGIC;
signal \^gpo\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_header : STD_LOGIC_VECTOR ( 7 downto 0 );
signal master_slave : STD_LOGIC;
signal new_rcv_dta_d1 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC;
signal p_1_in4_in : STD_LOGIC;
signal p_1_in6_in : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 6 to 6 );
signal p_3_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal rdCntrFrmTxFifo : STD_LOGIC;
signal rdCntrFrmTxFifo0 : STD_LOGIC;
signal rdy_new_xmt_i : STD_LOGIC;
signal rxCntDone : STD_LOGIC;
signal scl_clean : STD_LOGIC;
signal scl_rin_d1 : STD_LOGIC;
signal scl_rising_edge0 : STD_LOGIC;
signal sda_clean : STD_LOGIC;
signal sda_rin_d1 : STD_LOGIC;
signal shift_reg_ld : STD_LOGIC;
signal sr_i : STD_LOGIC_VECTOR ( 0 to 3 );
signal state122_out : STD_LOGIC;
signal stop_scl_reg : STD_LOGIC;
signal timing_param_tbuf_i : STD_LOGIC_VECTOR ( 7 downto 4 );
signal timing_param_thddat_i : STD_LOGIC_VECTOR ( 5 downto 4 );
signal timing_param_thdsta_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal timing_param_thigh_i : STD_LOGIC_VECTOR ( 7 downto 0 );
signal timing_param_tlow_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal timing_param_tsudat_i : STD_LOGIC_VECTOR ( 8 downto 0 );
signal timing_param_tsusta_i : STD_LOGIC_VECTOR ( 7 downto 4 );
signal timing_param_tsusto_i : STD_LOGIC_VECTOR ( 7 downto 0 );
signal txak : STD_LOGIC;
begin
gpo(0) <= \^gpo\(0);
DYN_MASTER_I: entity work.system_axi_iic_0_0_dynamic_master
port map (
Tx_fifo_data(0 to 7) => Tx_fifo_data(0 to 7),
Tx_fifo_rst => Tx_fifo_rst,
ackDataState => ackDataState,
callingReadAccess => callingReadAccess,
cr_txModeSelect_clr => cr_txModeSelect_clr,
cr_txModeSelect_set => cr_txModeSelect_set,
earlyAckDataState => earlyAckDataState,
earlyAckHdr => earlyAckHdr,
firstDynStartSeen => firstDynStartSeen,
firstDynStartSeen_reg_0 => REG_INTERFACE_I_n_132,
p_3_in => p_3_in,
rdCntrFrmTxFifo => rdCntrFrmTxFifo,
rdCntrFrmTxFifo0 => rdCntrFrmTxFifo0,
rxCntDone => rxCntDone,
rxCntDone_reg_0 => DYN_MASTER_I_n_6,
s_axi_aclk => s_axi_aclk
);
FILTER_I: entity work.system_axi_iic_0_0_filter
port map (
detect_stop_b_reg => FILTER_I_n_0,
s_axi_aclk => s_axi_aclk,
scl_i => scl_i,
scl_rin_d1 => scl_rin_d1,
scl_rin_d1_reg => scl_clean,
scl_rising_edge0 => scl_rising_edge0,
scndry_out => sda_clean,
sda_i => sda_i,
sda_rin_d1 => sda_rin_d1
);
IIC_CONTROL_I: entity work.system_axi_iic_0_0_iic_control
port map (
Aas => Aas,
Bb => Bb,
CO(0) => clk_cnt_en1,
D(3) => Al,
D(2) => Txer,
D(1) => IIC_CONTROL_I_n_8,
D(0) => p_0_out(0),
Data_Exists_DFF => WRITE_FIFO_I_n_15,
E(0) => Bus2IIC_WrCE(0),
\FSM_sequential_scl_state_reg[0]_0\(0) => clk_cnt_en12_out,
\FSM_sequential_scl_state_reg[2]_0\ => IIC_CONTROL_I_n_62,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ => scl_clean,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4_0\ => FILTER_I_n_0,
Msms_set => Msms_set,
New_rcv_dta => New_rcv_dta,
Q(4) => Cr(1),
Q(3) => Cr(2),
Q(2) => Cr(4),
Q(1) => Cr(5),
Q(0) => Cr(7),
\RD_FIFO_CNTRL.Rc_fifo_wr_reg\ => IIC_CONTROL_I_n_40,
Ro_prev => Ro_prev,
S(3) => REG_INTERFACE_I_n_27,
S(2) => REG_INTERFACE_I_n_28,
S(1) => REG_INTERFACE_I_n_29,
S(0) => REG_INTERFACE_I_n_30,
SR(0) => REG_INTERFACE_I_n_98,
Tx_data_exists => Tx_data_exists,
Tx_fifo_data(6) => Tx_fifo_data(0),
Tx_fifo_data(5) => Tx_fifo_data(1),
Tx_fifo_data(4) => Tx_fifo_data(2),
Tx_fifo_data(3) => Tx_fifo_data(3),
Tx_fifo_data(2) => Tx_fifo_data(4),
Tx_fifo_data(1) => Tx_fifo_data(5),
Tx_fifo_data(0) => Tx_fifo_data(6),
Tx_fifo_rd_d_reg => REG_INTERFACE_I_n_102,
Tx_under_prev => Tx_under_prev,
abgc_i_reg_0(7 downto 0) => i2c_header(7 downto 0),
abgc_i_reg_1 => REG_INTERFACE_I_n_26,
ackDataState => ackDataState,
arb_lost => arb_lost,
callingReadAccess => callingReadAccess,
\cr_i_reg[2]\ => REG_INTERFACE_I_n_104,
\cr_i_reg[4]\ => REG_INTERFACE_I_n_95,
\cr_i_reg[5]\(0) => IIC_CONTROL_I_n_50,
detect_stop_b_reg_0 => IIC_CONTROL_I_n_53,
dynamic_MSMS(0) => dynamic_MSMS(0),
earlyAckDataState => earlyAckDataState,
earlyAckHdr => earlyAckHdr,
master_slave => master_slave,
new_rcv_dta_d1 => new_rcv_dta_d1,
\q_int_reg[0]\(9) => \CLKCNT/q_int_reg__0\(0),
\q_int_reg[0]\(8) => \CLKCNT/q_int_reg__0\(1),
\q_int_reg[0]\(7) => \CLKCNT/q_int_reg__0\(2),
\q_int_reg[0]\(6) => \CLKCNT/q_int_reg__0\(3),
\q_int_reg[0]\(5) => \CLKCNT/q_int_reg__0\(4),
\q_int_reg[0]\(4) => \CLKCNT/q_int_reg__0\(5),
\q_int_reg[0]\(3) => \CLKCNT/q_int_reg__0\(6),
\q_int_reg[0]\(2) => \CLKCNT/q_int_reg__0\(7),
\q_int_reg[0]\(1) => \CLKCNT/q_int_reg__0\(8),
\q_int_reg[0]\(0) => \CLKCNT/q_int_reg__0\(9),
\q_int_reg[0]_0\(6) => \SETUP_CNT/q_int_reg__0\(0),
\q_int_reg[0]_0\(5) => \SETUP_CNT/q_int_reg__0\(4),
\q_int_reg[0]_0\(4) => \SETUP_CNT/q_int_reg__0\(5),
\q_int_reg[0]_0\(3) => \SETUP_CNT/q_int_reg__0\(6),
\q_int_reg[0]_0\(2) => \SETUP_CNT/q_int_reg__0\(7),
\q_int_reg[0]_0\(1) => \SETUP_CNT/q_int_reg__0\(8),
\q_int_reg[0]_0\(0) => \SETUP_CNT/q_int_reg__0\(9),
rdCntrFrmTxFifo0 => rdCntrFrmTxFifo0,
rdy_new_xmt_i => rdy_new_xmt_i,
rxCntDone => rxCntDone,
s_axi_aclk => s_axi_aclk,
\s_axi_rdata_i_reg[7]\(7) => Data_i2c(0),
\s_axi_rdata_i_reg[7]\(6) => Data_i2c(1),
\s_axi_rdata_i_reg[7]\(5) => Data_i2c(2),
\s_axi_rdata_i_reg[7]\(4) => Data_i2c(3),
\s_axi_rdata_i_reg[7]\(3) => Data_i2c(4),
\s_axi_rdata_i_reg[7]\(2) => Data_i2c(5),
\s_axi_rdata_i_reg[7]\(1) => Data_i2c(6),
\s_axi_rdata_i_reg[7]\(0) => Data_i2c(7),
s_axi_wdata(0) => s_axi_wdata(2),
scl_rin_d1 => scl_rin_d1,
scl_rising_edge0 => scl_rising_edge0,
scl_t => scl_t,
scndry_out => sda_clean,
sda_cout_reg_reg_0(0) => clk_cnt_en11_out,
sda_rin_d1 => sda_rin_d1,
sda_t => sda_t,
shift_reg_ld => shift_reg_ld,
shift_reg_ld_reg_0(0) => WRITE_FIFO_I_n_19,
sr_i(0) => sr_i(0),
\sr_i_reg[4]\(1) => Srw,
\sr_i_reg[4]\(0) => Abgc,
state122_out => state122_out,
stop_scl_reg => stop_scl_reg,
stop_scl_reg_reg_0 => REG_INTERFACE_I_n_103,
\timing_param_tbuf_i_reg[9]\(3) => REG_INTERFACE_I_n_59,
\timing_param_tbuf_i_reg[9]\(2) => REG_INTERFACE_I_n_60,
\timing_param_tbuf_i_reg[9]\(1) => REG_INTERFACE_I_n_61,
\timing_param_tbuf_i_reg[9]\(0) => REG_INTERFACE_I_n_62,
\timing_param_thddat_i_reg[9]\(3) => REG_INTERFACE_I_n_67,
\timing_param_thddat_i_reg[9]\(2) => REG_INTERFACE_I_n_68,
\timing_param_thddat_i_reg[9]\(1) => REG_INTERFACE_I_n_69,
\timing_param_thddat_i_reg[9]\(0) => REG_INTERFACE_I_n_70,
\timing_param_thdsta_i_reg[9]\(3) => REG_INTERFACE_I_n_73,
\timing_param_thdsta_i_reg[9]\(2) => REG_INTERFACE_I_n_74,
\timing_param_thdsta_i_reg[9]\(1) => REG_INTERFACE_I_n_75,
\timing_param_thdsta_i_reg[9]\(0) => REG_INTERFACE_I_n_76,
\timing_param_tlow_i_reg[9]\(3) => REG_INTERFACE_I_n_78,
\timing_param_tlow_i_reg[9]\(2) => REG_INTERFACE_I_n_79,
\timing_param_tlow_i_reg[9]\(1) => REG_INTERFACE_I_n_80,
\timing_param_tlow_i_reg[9]\(0) => REG_INTERFACE_I_n_81,
\timing_param_tsudat_i_reg[8]\(2 downto 0) => timing_param_tsudat_i(8 downto 6),
\timing_param_tsudat_i_reg[9]\(2) => REG_INTERFACE_I_n_83,
\timing_param_tsudat_i_reg[9]\(1) => REG_INTERFACE_I_n_84,
\timing_param_tsudat_i_reg[9]\(0) => REG_INTERFACE_I_n_85,
\timing_param_tsusta_i_reg[9]\(3) => REG_INTERFACE_I_n_51,
\timing_param_tsusta_i_reg[9]\(2) => REG_INTERFACE_I_n_52,
\timing_param_tsusta_i_reg[9]\(1) => REG_INTERFACE_I_n_53,
\timing_param_tsusta_i_reg[9]\(0) => REG_INTERFACE_I_n_54,
\timing_param_tsusto_i_reg[9]\(3) => REG_INTERFACE_I_n_39,
\timing_param_tsusto_i_reg[9]\(2) => REG_INTERFACE_I_n_40,
\timing_param_tsusto_i_reg[9]\(1) => REG_INTERFACE_I_n_41,
\timing_param_tsusto_i_reg[9]\(0) => REG_INTERFACE_I_n_42,
txak => txak
);
READ_FIFO_I: entity work.system_axi_iic_0_0_SRL_FIFO
port map (
Bus2IIC_Reset => Bus2IIC_Reset,
D(1) => p_1_out(6),
D(0) => Rc_fifo_full,
D_0 => D,
Data_Exists_DFF_0 => READ_FIFO_I_n_16,
Msms_set => Msms_set,
Q(3) => p_1_in6_in,
Q(2) => p_1_in4_in,
Q(1) => p_1_in,
Q(0) => REG_INTERFACE_I_n_118,
\RD_FIFO_CNTRL.Rc_fifo_rd_reg\ => REG_INTERFACE_I_n_131,
\RD_FIFO_CNTRL.Rc_fifo_wr_reg\ => REG_INTERFACE_I_n_130,
Rc_Data_Exists => Rc_Data_Exists,
Rc_addr(0 to 3) => Rc_addr(0 to 3),
Rc_fifo_data(0 to 7) => Rc_fifo_data(0 to 7),
Rc_fifo_rd => Rc_fifo_rd,
Rc_fifo_rd_d => Rc_fifo_rd_d,
Rc_fifo_wr => Rc_fifo_wr,
Rc_fifo_wr_d => Rc_fifo_wr_d,
\data_i2c_i_reg[7]\(7) => Data_i2c(0),
\data_i2c_i_reg[7]\(6) => Data_i2c(1),
\data_i2c_i_reg[7]\(5) => Data_i2c(2),
\data_i2c_i_reg[7]\(4) => Data_i2c(3),
\data_i2c_i_reg[7]\(3) => Data_i2c(4),
\data_i2c_i_reg[7]\(2) => Data_i2c(5),
\data_i2c_i_reg[7]\(1) => Data_i2c(6),
\data_i2c_i_reg[7]\(0) => Data_i2c(7),
p_6_out => p_6_out,
s_axi_aclk => s_axi_aclk
);
REG_INTERFACE_I: entity work.system_axi_iic_0_0_reg_interface
port map (
Aas => Aas,
\Addr_Counters[0].FDRE_I\ => REG_INTERFACE_I_n_128,
\Addr_Counters[0].FDRE_I_0\ => REG_INTERFACE_I_n_130,
\Addr_Counters[0].FDRE_I_1\ => REG_INTERFACE_I_n_131,
\Addr_Counters[1].FDRE_I\ => WRITE_FIFO_CTRL_I_n_3,
\Addr_Counters[1].FDRE_I_0\ => WRITE_FIFO_I_n_18,
\Addr_Counters[1].FDRE_I_1\ => READ_FIFO_I_n_16,
\Addr_Counters[3].FDRE_I\ => WRITE_FIFO_I_n_17,
Bus2IIC_RdCE(0) => Bus2IIC_RdCE(3),
Bus2IIC_Reset => Bus2IIC_Reset,
Bus2IIC_WrCE(11) => Bus2IIC_WrCE(0),
Bus2IIC_WrCE(10) => Bus2IIC_WrCE(2),
Bus2IIC_WrCE(9) => Bus2IIC_WrCE(4),
Bus2IIC_WrCE(8) => Bus2IIC_WrCE(8),
Bus2IIC_WrCE(7) => Bus2IIC_WrCE(10),
Bus2IIC_WrCE(6) => Bus2IIC_WrCE(11),
Bus2IIC_WrCE(5) => Bus2IIC_WrCE(12),
Bus2IIC_WrCE(4) => Bus2IIC_WrCE(13),
Bus2IIC_WrCE(3) => Bus2IIC_WrCE(14),
Bus2IIC_WrCE(2) => Bus2IIC_WrCE(15),
Bus2IIC_WrCE(1) => Bus2IIC_WrCE(16),
Bus2IIC_WrCE(0) => Bus2IIC_WrCE(17),
CO(0) => clk_cnt_en1,
D(0) => Ro_prev,
D_0 => D_1,
D_1 => D_0,
D_2 => D,
Data_Exists_DFF => REG_INTERFACE_I_n_97,
Data_Exists_DFF_0 => REG_INTERFACE_I_n_101,
Data_Exists_DFF_1 => WRITE_FIFO_I_n_16,
Data_Exists_DFF_2 => WRITE_FIFO_CTRL_I_n_0,
Data_Exists_DFF_3(5) => p_1_out(6),
Data_Exists_DFF_3(4) => Rc_fifo_full,
Data_Exists_DFF_3(3) => Tx_fifo_full,
Data_Exists_DFF_3(2) => Srw,
Data_Exists_DFF_3(1) => Bb,
Data_Exists_DFF_3(0) => Abgc,
\FSM_onehot_state_reg[4]\ => REG_INTERFACE_I_n_95,
\FSM_sequential_scl_state_reg[0]\(7 downto 0) => timing_param_thigh_i(7 downto 0),
\FSM_sequential_scl_state_reg[0]_0\(3) => REG_INTERFACE_I_n_51,
\FSM_sequential_scl_state_reg[0]_0\(2) => REG_INTERFACE_I_n_52,
\FSM_sequential_scl_state_reg[0]_0\(1) => REG_INTERFACE_I_n_53,
\FSM_sequential_scl_state_reg[0]_0\(0) => REG_INTERFACE_I_n_54,
\FSM_sequential_scl_state_reg[0]_1\ => REG_INTERFACE_I_n_104,
\FSM_sequential_scl_state_reg[0]_2\ => IIC_CONTROL_I_n_62,
\FSM_sequential_scl_state_reg[1]\(3) => REG_INTERFACE_I_n_78,
\FSM_sequential_scl_state_reg[1]\(2) => REG_INTERFACE_I_n_79,
\FSM_sequential_scl_state_reg[1]\(1) => REG_INTERFACE_I_n_80,
\FSM_sequential_scl_state_reg[1]\(0) => REG_INTERFACE_I_n_81,
\FSM_sequential_scl_state_reg[1]_0\(0) => timing_param_tlow_i(0),
\FSM_sequential_scl_state_reg[2]\(3) => REG_INTERFACE_I_n_73,
\FSM_sequential_scl_state_reg[2]\(2) => REG_INTERFACE_I_n_74,
\FSM_sequential_scl_state_reg[2]\(1) => REG_INTERFACE_I_n_75,
\FSM_sequential_scl_state_reg[2]\(0) => REG_INTERFACE_I_n_76,
\FSM_sequential_scl_state_reg[2]_0\(0) => timing_param_thdsta_i(0),
\FSM_sequential_scl_state_reg[2]_1\ => IIC_CONTROL_I_n_53,
\FSM_sequential_scl_state_reg[3]\(3) => REG_INTERFACE_I_n_59,
\FSM_sequential_scl_state_reg[3]\(2) => REG_INTERFACE_I_n_60,
\FSM_sequential_scl_state_reg[3]\(1) => REG_INTERFACE_I_n_61,
\FSM_sequential_scl_state_reg[3]\(0) => REG_INTERFACE_I_n_62,
\FSM_sequential_scl_state_reg[3]_0\(3 downto 0) => timing_param_tbuf_i(7 downto 4),
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\(1) => X_AXI_IPIF_SSP1_n_15,
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\(0) => IIC_CONTROL_I_n_50,
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\ => X_AXI_IPIF_SSP1_n_29,
IIC2Bus_IntrEvent(0 to 7) => IIC2Bus_IntrEvent(0 to 7),
Msms_set => Msms_set,
New_rcv_dta => New_rcv_dta,
Q(4) => Cr(1),
Q(3) => Cr(2),
Q(2) => Cr(4),
Q(1) => Cr(5),
Q(0) => Cr(7),
\RD_FIFO_CNTRL.ro_prev_i_reg_0\(3) => p_1_in6_in,
\RD_FIFO_CNTRL.ro_prev_i_reg_0\(2) => p_1_in4_in,
\RD_FIFO_CNTRL.ro_prev_i_reg_0\(1) => p_1_in,
\RD_FIFO_CNTRL.ro_prev_i_reg_0\(0) => REG_INTERFACE_I_n_118,
Rc_Data_Exists => Rc_Data_Exists,
Rc_addr(0 to 3) => Rc_addr(0 to 3),
Rc_fifo_rd => Rc_fifo_rd,
Rc_fifo_rd_d => Rc_fifo_rd_d,
Rc_fifo_wr => Rc_fifo_wr,
Rc_fifo_wr_d => Rc_fifo_wr_d,
S(3) => REG_INTERFACE_I_n_27,
S(2) => REG_INTERFACE_I_n_28,
S(1) => REG_INTERFACE_I_n_29,
S(0) => REG_INTERFACE_I_n_30,
SR(0) => REG_INTERFACE_I_n_98,
Tx_data_exists => Tx_data_exists,
Tx_fifo_data(3) => Tx_fifo_data(4),
Tx_fifo_data(2) => Tx_fifo_data(5),
Tx_fifo_data(1) => Tx_fifo_data(6),
Tx_fifo_data(0) => Tx_fifo_data(7),
Tx_fifo_rd => Tx_fifo_rd,
Tx_fifo_rd_d => Tx_fifo_rd_d,
Tx_fifo_rst => Tx_fifo_rst,
Tx_fifo_wr => Tx_fifo_wr,
Tx_fifo_wr_d => Tx_fifo_wr_d,
al_i_reg(4) => Al,
al_i_reg(3) => Txer,
al_i_reg(2) => Tx_under_prev,
al_i_reg(1) => IIC_CONTROL_I_n_8,
al_i_reg(0) => p_0_out(0),
arb_lost => arb_lost,
\bus2ip_addr_i_reg[6]\(4) => Bus2IIC_Addr(2),
\bus2ip_addr_i_reg[6]\(3) => Bus2IIC_Addr(3),
\bus2ip_addr_i_reg[6]\(2) => Bus2IIC_Addr(4),
\bus2ip_addr_i_reg[6]\(1) => Bus2IIC_Addr(5),
\bus2ip_addr_i_reg[6]\(0) => Bus2IIC_Addr(6),
\cr_i_reg[5]_0\ => REG_INTERFACE_I_n_102,
\data_int_reg[7]\(7 downto 0) => i2c_header(7 downto 0),
dtre_d1_reg(2) => sr_i(0),
dtre_d1_reg(1) => sr_i(2),
dtre_d1_reg(0) => sr_i(3),
dynamic_MSMS(0) => dynamic_MSMS(1),
earlyAckDataState => earlyAckDataState,
firstDynStartSeen => firstDynStartSeen,
firstDynStartSeen_reg => REG_INTERFACE_I_n_132,
gpo(0) => \^gpo\(0),
master_slave => master_slave,
new_rcv_dta_d1 => new_rcv_dta_d1,
new_rcv_dta_i_reg => IIC_CONTROL_I_n_40,
p_6_out => p_6_out,
\q_int_reg[0]\(3) => REG_INTERFACE_I_n_67,
\q_int_reg[0]\(2) => REG_INTERFACE_I_n_68,
\q_int_reg[0]\(1) => REG_INTERFACE_I_n_69,
\q_int_reg[0]\(0) => REG_INTERFACE_I_n_70,
\q_int_reg[0]_0\(9) => \CLKCNT/q_int_reg__0\(0),
\q_int_reg[0]_0\(8) => \CLKCNT/q_int_reg__0\(1),
\q_int_reg[0]_0\(7) => \CLKCNT/q_int_reg__0\(2),
\q_int_reg[0]_0\(6) => \CLKCNT/q_int_reg__0\(3),
\q_int_reg[0]_0\(5) => \CLKCNT/q_int_reg__0\(4),
\q_int_reg[0]_0\(4) => \CLKCNT/q_int_reg__0\(5),
\q_int_reg[0]_0\(3) => \CLKCNT/q_int_reg__0\(6),
\q_int_reg[0]_0\(2) => \CLKCNT/q_int_reg__0\(7),
\q_int_reg[0]_0\(1) => \CLKCNT/q_int_reg__0\(8),
\q_int_reg[0]_0\(0) => \CLKCNT/q_int_reg__0\(9),
\q_int_reg[0]_1\(6) => \SETUP_CNT/q_int_reg__0\(0),
\q_int_reg[0]_1\(5) => \SETUP_CNT/q_int_reg__0\(4),
\q_int_reg[0]_1\(4) => \SETUP_CNT/q_int_reg__0\(5),
\q_int_reg[0]_1\(3) => \SETUP_CNT/q_int_reg__0\(6),
\q_int_reg[0]_1\(2) => \SETUP_CNT/q_int_reg__0\(7),
\q_int_reg[0]_1\(1) => \SETUP_CNT/q_int_reg__0\(8),
\q_int_reg[0]_1\(0) => \SETUP_CNT/q_int_reg__0\(9),
\q_int_reg[9]\ => REG_INTERFACE_I_n_103,
\rdByteCntr_reg[2]\ => DYN_MASTER_I_n_6,
rdCntrFrmTxFifo => rdCntrFrmTxFifo,
rdy_new_xmt_i => rdy_new_xmt_i,
s_axi_aclk => s_axi_aclk,
\s_axi_rdata_i_reg[0]\ => REG_INTERFACE_I_n_105,
\s_axi_rdata_i_reg[0]_0\ => REG_INTERFACE_I_n_127,
\s_axi_rdata_i_reg[1]\ => REG_INTERFACE_I_n_124,
\s_axi_rdata_i_reg[1]_0\ => REG_INTERFACE_I_n_125,
\s_axi_rdata_i_reg[1]_1\ => REG_INTERFACE_I_n_126,
\s_axi_rdata_i_reg[2]\ => REG_INTERFACE_I_n_121,
\s_axi_rdata_i_reg[2]_0\ => REG_INTERFACE_I_n_122,
\s_axi_rdata_i_reg[2]_1\ => REG_INTERFACE_I_n_123,
\s_axi_rdata_i_reg[3]\ => REG_INTERFACE_I_n_114,
\s_axi_rdata_i_reg[3]_0\ => REG_INTERFACE_I_n_119,
\s_axi_rdata_i_reg[3]_1\ => REG_INTERFACE_I_n_120,
\s_axi_rdata_i_reg[4]\ => REG_INTERFACE_I_n_113,
\s_axi_rdata_i_reg[5]\(1 downto 0) => timing_param_thddat_i(5 downto 4),
\s_axi_rdata_i_reg[5]_0\ => REG_INTERFACE_I_n_112,
\s_axi_rdata_i_reg[6]\ => REG_INTERFACE_I_n_106,
\s_axi_rdata_i_reg[6]_0\ => REG_INTERFACE_I_n_111,
\s_axi_rdata_i_reg[7]\(3 downto 0) => timing_param_tsusta_i(7 downto 4),
\s_axi_rdata_i_reg[7]_0\ => REG_INTERFACE_I_n_107,
\s_axi_rdata_i_reg[7]_1\ => REG_INTERFACE_I_n_110,
\s_axi_rdata_i_reg[8]\(8 downto 0) => timing_param_tsudat_i(8 downto 0),
\s_axi_rdata_i_reg[8]_0\ => REG_INTERFACE_I_n_109,
\s_axi_rdata_i_reg[9]\ => REG_INTERFACE_I_n_108,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
sda_cout_reg_reg(3) => REG_INTERFACE_I_n_39,
sda_cout_reg_reg(2) => REG_INTERFACE_I_n_40,
sda_cout_reg_reg(1) => REG_INTERFACE_I_n_41,
sda_cout_reg_reg(0) => REG_INTERFACE_I_n_42,
sda_cout_reg_reg_0(7 downto 0) => timing_param_tsusto_i(7 downto 0),
sda_setup_reg(2) => REG_INTERFACE_I_n_83,
sda_setup_reg(1) => REG_INTERFACE_I_n_84,
sda_setup_reg(0) => REG_INTERFACE_I_n_85,
slave_sda_reg => REG_INTERFACE_I_n_26,
state122_out => state122_out,
stop_scl_reg => stop_scl_reg,
\timing_param_tsusta_i_reg[9]_0\(0) => clk_cnt_en12_out,
\timing_param_tsusto_i_reg[9]_0\(0) => clk_cnt_en11_out,
txak => txak
);
Rc_fifo_rd_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Rc_fifo_rd,
Q => Rc_fifo_rd_d,
R => Bus2IIC_Reset
);
Rc_fifo_wr_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Rc_fifo_wr,
Q => Rc_fifo_wr_d,
R => Bus2IIC_Reset
);
Tx_fifo_rd_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Tx_fifo_rd,
Q => Tx_fifo_rd_d,
R => Bus2IIC_Reset
);
Tx_fifo_wr_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Tx_fifo_wr,
Q => Tx_fifo_wr_d,
R => Bus2IIC_Reset
);
WRITE_FIFO_CTRL_I: entity work.\system_axi_iic_0_0_SRL_FIFO__parameterized0\
port map (
\Addr_Counters[0].FDRE_I_0\ => WRITE_FIFO_CTRL_I_n_0,
D => D_1,
Data_Exists_DFF_0 => WRITE_FIFO_CTRL_I_n_3,
\FIFO_GEN_DTR.Tx_fifo_rd_reg\ => REG_INTERFACE_I_n_101,
Tx_fifo_rd => Tx_fifo_rd,
Tx_fifo_rd_d => Tx_fifo_rd_d,
Tx_fifo_rst => Tx_fifo_rst,
Tx_fifo_wr_d_reg => REG_INTERFACE_I_n_97,
ctrlFifoDin(0 to 1) => ctrlFifoDin(0 to 1),
dynamic_MSMS(0 to 1) => dynamic_MSMS(0 to 1),
rdCntrFrmTxFifo => rdCntrFrmTxFifo,
s_axi_aclk => s_axi_aclk
);
WRITE_FIFO_I: entity work.system_axi_iic_0_0_SRL_FIFO_0
port map (
D => D_0,
Data_Exists_DFF_0 => WRITE_FIFO_I_n_18,
\FIFO_GEN_DTR.IIC2Bus_IntrEvent_reg[7]\ => WRITE_FIFO_I_n_17,
\FIFO_GEN_DTR.Tx_fifo_rd_reg\ => REG_INTERFACE_I_n_101,
\FIFO_GEN_DTR.Tx_fifo_wr_reg\ => REG_INTERFACE_I_n_128,
Tx_addr(0 to 3) => Tx_addr(0 to 3),
Tx_data_exists => Tx_data_exists,
Tx_fifo_data(0 to 7) => Tx_fifo_data(0 to 7),
Tx_fifo_rd => Tx_fifo_rd,
Tx_fifo_rd_d => Tx_fifo_rd_d,
Tx_fifo_rst => Tx_fifo_rst,
Tx_fifo_wr => Tx_fifo_wr,
Tx_fifo_wr_d => Tx_fifo_wr_d,
\cr_i_reg[5]\ => WRITE_FIFO_I_n_15,
\data_int_reg[0]\(0) => WRITE_FIFO_I_n_19,
dynamic_MSMS(0) => dynamic_MSMS(1),
p_3_in => p_3_in,
rdCntrFrmTxFifo => rdCntrFrmTxFifo,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
scndry_out => sda_clean,
shift_reg_ld => shift_reg_ld,
\sr_i_reg[0]\ => WRITE_FIFO_I_n_16,
\sr_i_reg[3]\(0) => Tx_fifo_full
);
X_AXI_IPIF_SSP1: entity work.system_axi_iic_0_0_axi_ipif_ssp1
port map (
Bus2IIC_RdCE(0) => Bus2IIC_RdCE(3),
Bus2IIC_Reset => Bus2IIC_Reset,
Bus2IIC_WrCE(11) => Bus2IIC_WrCE(0),
Bus2IIC_WrCE(10) => Bus2IIC_WrCE(2),
Bus2IIC_WrCE(9) => Bus2IIC_WrCE(4),
Bus2IIC_WrCE(8) => Bus2IIC_WrCE(8),
Bus2IIC_WrCE(7) => Bus2IIC_WrCE(10),
Bus2IIC_WrCE(6) => Bus2IIC_WrCE(11),
Bus2IIC_WrCE(5) => Bus2IIC_WrCE(12),
Bus2IIC_WrCE(4) => Bus2IIC_WrCE(13),
Bus2IIC_WrCE(3) => Bus2IIC_WrCE(14),
Bus2IIC_WrCE(2) => Bus2IIC_WrCE(15),
Bus2IIC_WrCE(1) => Bus2IIC_WrCE(16),
Bus2IIC_WrCE(0) => Bus2IIC_WrCE(17),
\GPO_GEN.gpo_i_reg[31]\ => X_AXI_IPIF_SSP1_n_29,
\GPO_GEN.gpo_i_reg[31]_0\ => REG_INTERFACE_I_n_105,
IIC2Bus_IntrEvent(0 to 7) => IIC2Bus_IntrEvent(0 to 7),
\IIC2Bus_IntrEvent_reg[5]\ => REG_INTERFACE_I_n_125,
Q(4) => Bus2IIC_Addr(2),
Q(3) => Bus2IIC_Addr(3),
Q(2) => Bus2IIC_Addr(4),
Q(1) => Bus2IIC_Addr(5),
Q(0) => Bus2IIC_Addr(6),
\RD_FIFO_CNTRL.rc_fifo_pirq_i_reg[7]\(0) => REG_INTERFACE_I_n_118,
Rc_fifo_data(0 to 7) => Rc_fifo_data(0 to 7),
Tx_addr(0 to 3) => Tx_addr(0 to 3),
Tx_fifo_data(3) => Tx_fifo_data(0),
Tx_fifo_data(2) => Tx_fifo_data(1),
Tx_fifo_data(1) => Tx_fifo_data(2),
Tx_fifo_data(0) => Tx_fifo_data(3),
Tx_fifo_rst => Tx_fifo_rst,
\adr_i_reg[0]\ => REG_INTERFACE_I_n_110,
\adr_i_reg[1]\ => REG_INTERFACE_I_n_111,
\adr_i_reg[2]\ => REG_INTERFACE_I_n_112,
\adr_i_reg[3]\ => REG_INTERFACE_I_n_113,
\adr_i_reg[4]\ => REG_INTERFACE_I_n_114,
\adr_i_reg[5]\ => REG_INTERFACE_I_n_122,
\adr_i_reg[6]\ => REG_INTERFACE_I_n_124,
\bus2ip_addr_i_reg[2]\ => REG_INTERFACE_I_n_109,
\bus2ip_addr_i_reg[2]_0\ => REG_INTERFACE_I_n_108,
\cr_i_reg[4]\(0) => X_AXI_IPIF_SSP1_n_15,
\cr_i_reg[4]_0\(1) => Cr(4),
\cr_i_reg[4]_0\(0) => Cr(7),
cr_txModeSelect_clr => cr_txModeSelect_clr,
cr_txModeSelect_set => cr_txModeSelect_set,
ctrlFifoDin(0 to 1) => ctrlFifoDin(0 to 1),
gpo(0) => \^gpo\(0),
iic2intc_irpt => iic2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(10 downto 0) => s_axi_rdata(10 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(10 downto 0) => s_axi_wdata(10 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
\sr_i_reg[2]\(1) => sr_i(2),
\sr_i_reg[2]\(0) => sr_i(3),
\sr_i_reg[4]\ => REG_INTERFACE_I_n_119,
\sr_i_reg[5]\ => REG_INTERFACE_I_n_123,
\timing_param_tbuf_i_reg[0]\ => REG_INTERFACE_I_n_127,
\timing_param_tbuf_i_reg[1]\ => REG_INTERFACE_I_n_126,
\timing_param_tbuf_i_reg[2]\ => REG_INTERFACE_I_n_121,
\timing_param_tbuf_i_reg[3]\ => REG_INTERFACE_I_n_120,
\timing_param_tbuf_i_reg[7]\(3 downto 0) => timing_param_tbuf_i(7 downto 4),
\timing_param_thddat_i_reg[5]\(1 downto 0) => timing_param_thddat_i(5 downto 4),
\timing_param_thdsta_i_reg[0]\(0) => timing_param_thdsta_i(0),
\timing_param_thigh_i_reg[7]\(7 downto 0) => timing_param_thigh_i(7 downto 0),
\timing_param_tlow_i_reg[0]\(0) => timing_param_tlow_i(0),
\timing_param_tsudat_i_reg[5]\(5 downto 0) => timing_param_tsudat_i(5 downto 0),
\timing_param_tsudat_i_reg[6]\ => REG_INTERFACE_I_n_106,
\timing_param_tsudat_i_reg[7]\ => REG_INTERFACE_I_n_107,
\timing_param_tsusta_i_reg[7]\(3 downto 0) => timing_param_tsusta_i(7 downto 4),
\timing_param_tsusto_i_reg[7]\(7 downto 0) => timing_param_tsusto_i(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0_axi_iic is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
iic2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
sda_t : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
scl_t : out STD_LOGIC;
gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of system_axi_iic_0_0_axi_iic : entity is "8'b00000000";
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_iic_0_0_axi_iic : entity is "artix7";
attribute C_GPO_WIDTH : integer;
attribute C_GPO_WIDTH of system_axi_iic_0_0_axi_iic : entity is 1;
attribute C_IIC_FREQ : integer;
attribute C_IIC_FREQ of system_axi_iic_0_0_axi_iic : entity is 100000;
attribute C_SCL_INERTIAL_DELAY : integer;
attribute C_SCL_INERTIAL_DELAY of system_axi_iic_0_0_axi_iic : entity is 0;
attribute C_SDA_INERTIAL_DELAY : integer;
attribute C_SDA_INERTIAL_DELAY of system_axi_iic_0_0_axi_iic : entity is 0;
attribute C_SDA_LEVEL : integer;
attribute C_SDA_LEVEL of system_axi_iic_0_0_axi_iic : entity is 1;
attribute C_SMBUS_PMBUS_HOST : integer;
attribute C_SMBUS_PMBUS_HOST of system_axi_iic_0_0_axi_iic : entity is 0;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of system_axi_iic_0_0_axi_iic : entity is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_iic_0_0_axi_iic : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_iic_0_0_axi_iic : entity is 32;
attribute C_TEN_BIT_ADR : integer;
attribute C_TEN_BIT_ADR of system_axi_iic_0_0_axi_iic : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_iic_0_0_axi_iic : entity is "axi_iic";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_iic_0_0_axi_iic : entity is "yes";
end system_axi_iic_0_0_axi_iic;
architecture STRUCTURE of system_axi_iic_0_0_axi_iic is
signal \<const0>\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \^s_axi_bresp\(1);
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9 downto 0) <= \^s_axi_rdata\(9 downto 0);
s_axi_rresp(1) <= \^s_axi_rresp\(1);
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
scl_o <= \<const0>\;
sda_o <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
X_IIC: entity work.system_axi_iic_0_0_iic
port map (
gpo(0) => gpo(0),
iic2intc_irpt => iic2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(1),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(10) => \^s_axi_rdata\(31),
s_axi_rdata(9 downto 0) => \^s_axi_rdata\(9 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => \^s_axi_rresp\(1),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(10) => s_axi_wdata(31),
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid,
scl_i => scl_i,
scl_t => scl_t,
sda_i => sda_i,
sda_t => sda_t
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_iic_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
iic2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
sda_t : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
scl_t : out STD_LOGIC;
gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_iic_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_iic_0_0 : entity is "system_axi_iic_0_0,axi_iic,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_iic_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_iic_0_0 : entity is "axi_iic,Vivado 2016.4";
end system_axi_iic_0_0;
architecture STRUCTURE of system_axi_iic_0_0 is
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "8'b00000000";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPO_WIDTH : integer;
attribute C_GPO_WIDTH of U0 : label is 1;
attribute C_IIC_FREQ : integer;
attribute C_IIC_FREQ of U0 : label is 100000;
attribute C_SCL_INERTIAL_DELAY : integer;
attribute C_SCL_INERTIAL_DELAY of U0 : label is 0;
attribute C_SDA_INERTIAL_DELAY : integer;
attribute C_SDA_INERTIAL_DELAY of U0 : label is 0;
attribute C_SDA_LEVEL : integer;
attribute C_SDA_LEVEL of U0 : label is 1;
attribute C_SMBUS_PMBUS_HOST : integer;
attribute C_SMBUS_PMBUS_HOST of U0 : label is 0;
attribute C_S_AXI_ACLK_FREQ_HZ : integer;
attribute C_S_AXI_ACLK_FREQ_HZ of U0 : label is 100000000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TEN_BIT_ADR : integer;
attribute C_TEN_BIT_ADR of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_axi_iic_0_0_axi_iic
port map (
gpo(0) => gpo(0),
iic2intc_irpt => iic2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t
);
end STRUCTURE;
|
apache-2.0
|
e0a72967b7742d459d94fd4c6fc935f1
| 0.538753 | 2.555371 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/hdl/system_wrapper.vhd
| 1 | 50,648 |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
--Date : Mon Mar 20 20:54:09 2017
--Host : N73-PC running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_cas_n : out STD_LOGIC;
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
Vaux0_v_n : in STD_LOGIC;
Vaux0_v_p : in STD_LOGIC;
Vaux10_v_n : in STD_LOGIC;
Vaux10_v_p : in STD_LOGIC;
Vaux12_v_n : in STD_LOGIC;
Vaux12_v_p : in STD_LOGIC;
Vaux13_v_n : in STD_LOGIC;
Vaux13_v_p : in STD_LOGIC;
Vaux14_v_n : in STD_LOGIC;
Vaux14_v_p : in STD_LOGIC;
Vaux15_v_n : in STD_LOGIC;
Vaux15_v_p : in STD_LOGIC;
Vaux1_v_n : in STD_LOGIC;
Vaux1_v_p : in STD_LOGIC;
Vaux2_v_n : in STD_LOGIC;
Vaux2_v_p : in STD_LOGIC;
Vaux4_v_n : in STD_LOGIC;
Vaux4_v_p : in STD_LOGIC;
Vaux5_v_n : in STD_LOGIC;
Vaux5_v_p : in STD_LOGIC;
Vaux6_v_n : in STD_LOGIC;
Vaux6_v_p : in STD_LOGIC;
Vaux7_v_n : in STD_LOGIC;
Vaux7_v_p : in STD_LOGIC;
Vaux9_v_n : in STD_LOGIC;
Vaux9_v_p : in STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC;
dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_io : inout STD_LOGIC;
eth_mii_col : in STD_LOGIC;
eth_mii_crs : in STD_LOGIC;
eth_mii_rst_n : out STD_LOGIC;
eth_mii_rx_clk : in STD_LOGIC;
eth_mii_rx_dv : in STD_LOGIC;
eth_mii_rx_er : in STD_LOGIC;
eth_mii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mii_tx_clk : in STD_LOGIC;
eth_mii_tx_en : out STD_LOGIC;
eth_mii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 );
eth_ref_clk : out STD_LOGIC;
i2c_pullups_tri_io : inout STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_scl_io : inout STD_LOGIC;
i2c_sda_io : inout STD_LOGIC;
led_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 );
push_buttons_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
qspi_flash_io0_io : inout STD_LOGIC;
qspi_flash_io1_io : inout STD_LOGIC;
qspi_flash_io2_io : inout STD_LOGIC;
qspi_flash_io3_io : inout STD_LOGIC;
qspi_flash_sck_io : inout STD_LOGIC;
qspi_flash_ss_io : inout STD_LOGIC;
reset : in STD_LOGIC;
rgb_led_tri_io : inout STD_LOGIC_VECTOR ( 11 downto 0 );
shield_dp0_dp19_tri_io : inout STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp26_dp41_tri_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
spi_io0_io : inout STD_LOGIC;
spi_io1_io : inout STD_LOGIC;
spi_sck_io : inout STD_LOGIC;
spi_ss_io : inout STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 );
DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 );
DDR3_ras_n : out STD_LOGIC;
DDR3_cas_n : out STD_LOGIC;
DDR3_we_n : out STD_LOGIC;
DDR3_reset_n : out STD_LOGIC;
DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
Vaux0_v_n : in STD_LOGIC;
Vaux0_v_p : in STD_LOGIC;
Vaux1_v_n : in STD_LOGIC;
Vaux1_v_p : in STD_LOGIC;
Vaux2_v_n : in STD_LOGIC;
Vaux2_v_p : in STD_LOGIC;
Vaux4_v_n : in STD_LOGIC;
Vaux4_v_p : in STD_LOGIC;
Vaux5_v_n : in STD_LOGIC;
Vaux5_v_p : in STD_LOGIC;
Vaux6_v_n : in STD_LOGIC;
Vaux6_v_p : in STD_LOGIC;
Vaux7_v_n : in STD_LOGIC;
Vaux7_v_p : in STD_LOGIC;
Vaux9_v_n : in STD_LOGIC;
Vaux9_v_p : in STD_LOGIC;
Vaux10_v_n : in STD_LOGIC;
Vaux10_v_p : in STD_LOGIC;
Vaux12_v_n : in STD_LOGIC;
Vaux12_v_p : in STD_LOGIC;
Vaux13_v_n : in STD_LOGIC;
Vaux13_v_p : in STD_LOGIC;
Vaux14_v_n : in STD_LOGIC;
Vaux14_v_p : in STD_LOGIC;
Vaux15_v_n : in STD_LOGIC;
Vaux15_v_p : in STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC;
dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mdio_mdc_mdc : out STD_LOGIC;
eth_mdio_mdc_mdio_i : in STD_LOGIC;
eth_mdio_mdc_mdio_o : out STD_LOGIC;
eth_mdio_mdc_mdio_t : out STD_LOGIC;
eth_mii_col : in STD_LOGIC;
eth_mii_crs : in STD_LOGIC;
eth_mii_rst_n : out STD_LOGIC;
eth_mii_rx_clk : in STD_LOGIC;
eth_mii_rx_dv : in STD_LOGIC;
eth_mii_rx_er : in STD_LOGIC;
eth_mii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 );
eth_mii_tx_clk : in STD_LOGIC;
eth_mii_tx_en : out STD_LOGIC;
eth_mii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 );
i2c_scl_i : in STD_LOGIC;
i2c_scl_o : out STD_LOGIC;
i2c_scl_t : out STD_LOGIC;
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC;
i2c_sda_t : out STD_LOGIC;
i2c_pullups_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_pullups_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
i2c_pullups_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
led_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
led_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
led_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
push_buttons_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
qspi_flash_io0_i : in STD_LOGIC;
qspi_flash_io0_o : out STD_LOGIC;
qspi_flash_io0_t : out STD_LOGIC;
qspi_flash_io1_i : in STD_LOGIC;
qspi_flash_io1_o : out STD_LOGIC;
qspi_flash_io1_t : out STD_LOGIC;
qspi_flash_io2_i : in STD_LOGIC;
qspi_flash_io2_o : out STD_LOGIC;
qspi_flash_io2_t : out STD_LOGIC;
qspi_flash_io3_i : in STD_LOGIC;
qspi_flash_io3_o : out STD_LOGIC;
qspi_flash_io3_t : out STD_LOGIC;
qspi_flash_sck_i : in STD_LOGIC;
qspi_flash_sck_o : out STD_LOGIC;
qspi_flash_sck_t : out STD_LOGIC;
qspi_flash_ss_i : in STD_LOGIC;
qspi_flash_ss_o : out STD_LOGIC;
qspi_flash_ss_t : out STD_LOGIC;
rgb_led_tri_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
rgb_led_tri_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
rgb_led_tri_t : out STD_LOGIC_VECTOR ( 11 downto 0 );
shield_dp0_dp19_tri_i : in STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp0_dp19_tri_o : out STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp0_dp19_tri_t : out STD_LOGIC_VECTOR ( 19 downto 0 );
shield_dp26_dp41_tri_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
shield_dp26_dp41_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
shield_dp26_dp41_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
spi_io0_i : in STD_LOGIC;
spi_io0_o : out STD_LOGIC;
spi_io0_t : out STD_LOGIC;
spi_io1_i : in STD_LOGIC;
spi_io1_o : out STD_LOGIC;
spi_io1_t : out STD_LOGIC;
spi_sck_i : in STD_LOGIC;
spi_sck_o : out STD_LOGIC;
spi_sck_t : out STD_LOGIC;
spi_ss_i : in STD_LOGIC;
spi_ss_o : out STD_LOGIC;
spi_ss_t : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
eth_ref_clk : out STD_LOGIC;
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC
);
end component system;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal eth_mdio_mdc_mdio_i : STD_LOGIC;
signal eth_mdio_mdc_mdio_o : STD_LOGIC;
signal eth_mdio_mdc_mdio_t : STD_LOGIC;
signal i2c_pullups_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_pullups_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal i2c_pullups_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_pullups_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal i2c_pullups_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_pullups_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal i2c_pullups_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal i2c_pullups_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal i2c_scl_i : STD_LOGIC;
signal i2c_scl_o : STD_LOGIC;
signal i2c_scl_t : STD_LOGIC;
signal i2c_sda_i : STD_LOGIC;
signal i2c_sda_o : STD_LOGIC;
signal i2c_sda_t : STD_LOGIC;
signal led_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal led_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal led_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal led_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal led_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal led_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal led_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal led_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal led_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal led_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal led_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal led_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal led_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal led_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal led_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal led_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal qspi_flash_io0_i : STD_LOGIC;
signal qspi_flash_io0_o : STD_LOGIC;
signal qspi_flash_io0_t : STD_LOGIC;
signal qspi_flash_io1_i : STD_LOGIC;
signal qspi_flash_io1_o : STD_LOGIC;
signal qspi_flash_io1_t : STD_LOGIC;
signal qspi_flash_io2_i : STD_LOGIC;
signal qspi_flash_io2_o : STD_LOGIC;
signal qspi_flash_io2_t : STD_LOGIC;
signal qspi_flash_io3_i : STD_LOGIC;
signal qspi_flash_io3_o : STD_LOGIC;
signal qspi_flash_io3_t : STD_LOGIC;
signal qspi_flash_sck_i : STD_LOGIC;
signal qspi_flash_sck_o : STD_LOGIC;
signal qspi_flash_sck_t : STD_LOGIC;
signal qspi_flash_ss_i : STD_LOGIC;
signal qspi_flash_ss_o : STD_LOGIC;
signal qspi_flash_ss_t : STD_LOGIC;
signal rgb_led_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal rgb_led_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal rgb_led_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal rgb_led_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal rgb_led_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal rgb_led_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal rgb_led_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal rgb_led_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal rgb_led_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal rgb_led_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal rgb_led_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal rgb_led_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal rgb_led_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal rgb_led_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal rgb_led_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal rgb_led_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal rgb_led_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal rgb_led_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal rgb_led_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal rgb_led_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal rgb_led_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal rgb_led_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal rgb_led_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal rgb_led_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rgb_led_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal rgb_led_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal rgb_led_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal rgb_led_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal rgb_led_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal rgb_led_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp0_dp19_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp0_dp19_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp0_dp19_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp0_dp19_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp0_dp19_tri_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp0_dp19_tri_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp0_dp19_tri_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp0_dp19_tri_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp0_dp19_tri_i_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal shield_dp0_dp19_tri_i_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal shield_dp0_dp19_tri_i_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal shield_dp0_dp19_tri_i_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal shield_dp0_dp19_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp0_dp19_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp0_dp19_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp0_dp19_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp0_dp19_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp0_dp19_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp0_dp19_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp0_dp19_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp0_dp19_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp0_dp19_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp0_dp19_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp0_dp19_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp0_dp19_tri_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp0_dp19_tri_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp0_dp19_tri_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp0_dp19_tri_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp0_dp19_tri_io_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal shield_dp0_dp19_tri_io_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal shield_dp0_dp19_tri_io_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal shield_dp0_dp19_tri_io_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal shield_dp0_dp19_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp0_dp19_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp0_dp19_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp0_dp19_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp0_dp19_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp0_dp19_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp0_dp19_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp0_dp19_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp0_dp19_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp0_dp19_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp0_dp19_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp0_dp19_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp0_dp19_tri_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp0_dp19_tri_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp0_dp19_tri_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp0_dp19_tri_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp0_dp19_tri_o_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal shield_dp0_dp19_tri_o_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal shield_dp0_dp19_tri_o_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal shield_dp0_dp19_tri_o_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal shield_dp0_dp19_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp0_dp19_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp0_dp19_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp0_dp19_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp0_dp19_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp0_dp19_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp0_dp19_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp0_dp19_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp0_dp19_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp0_dp19_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp0_dp19_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp0_dp19_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp0_dp19_tri_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp0_dp19_tri_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp0_dp19_tri_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp0_dp19_tri_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp0_dp19_tri_t_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal shield_dp0_dp19_tri_t_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal shield_dp0_dp19_tri_t_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal shield_dp0_dp19_tri_t_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal shield_dp0_dp19_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp0_dp19_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp0_dp19_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp0_dp19_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp0_dp19_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp0_dp19_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp0_dp19_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp0_dp19_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp26_dp41_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp26_dp41_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp26_dp41_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp26_dp41_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp26_dp41_tri_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp26_dp41_tri_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp26_dp41_tri_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp26_dp41_tri_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp26_dp41_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp26_dp41_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp26_dp41_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp26_dp41_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp26_dp41_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp26_dp41_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp26_dp41_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp26_dp41_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp26_dp41_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp26_dp41_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp26_dp41_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp26_dp41_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp26_dp41_tri_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp26_dp41_tri_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp26_dp41_tri_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp26_dp41_tri_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp26_dp41_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp26_dp41_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp26_dp41_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp26_dp41_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp26_dp41_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp26_dp41_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp26_dp41_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp26_dp41_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp26_dp41_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp26_dp41_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp26_dp41_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp26_dp41_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp26_dp41_tri_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp26_dp41_tri_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp26_dp41_tri_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp26_dp41_tri_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp26_dp41_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp26_dp41_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp26_dp41_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp26_dp41_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp26_dp41_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp26_dp41_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp26_dp41_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp26_dp41_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal shield_dp26_dp41_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal shield_dp26_dp41_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal shield_dp26_dp41_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal shield_dp26_dp41_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal shield_dp26_dp41_tri_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal shield_dp26_dp41_tri_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal shield_dp26_dp41_tri_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal shield_dp26_dp41_tri_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal shield_dp26_dp41_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal shield_dp26_dp41_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal shield_dp26_dp41_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal shield_dp26_dp41_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal shield_dp26_dp41_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal shield_dp26_dp41_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal shield_dp26_dp41_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal shield_dp26_dp41_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal spi_io0_i : STD_LOGIC;
signal spi_io0_o : STD_LOGIC;
signal spi_io0_t : STD_LOGIC;
signal spi_io1_i : STD_LOGIC;
signal spi_io1_o : STD_LOGIC;
signal spi_io1_t : STD_LOGIC;
signal spi_sck_i : STD_LOGIC;
signal spi_sck_o : STD_LOGIC;
signal spi_sck_t : STD_LOGIC;
signal spi_ss_i : STD_LOGIC;
signal spi_ss_o : STD_LOGIC;
signal spi_ss_t : STD_LOGIC;
begin
eth_mdio_mdc_mdio_iobuf: component IOBUF
port map (
I => eth_mdio_mdc_mdio_o,
IO => eth_mdio_mdc_mdio_io,
O => eth_mdio_mdc_mdio_i,
T => eth_mdio_mdc_mdio_t
);
i2c_pullups_tri_iobuf_0: component IOBUF
port map (
I => i2c_pullups_tri_o_0(0),
IO => i2c_pullups_tri_io(0),
O => i2c_pullups_tri_i_0(0),
T => i2c_pullups_tri_t_0(0)
);
i2c_pullups_tri_iobuf_1: component IOBUF
port map (
I => i2c_pullups_tri_o_1(1),
IO => i2c_pullups_tri_io(1),
O => i2c_pullups_tri_i_1(1),
T => i2c_pullups_tri_t_1(1)
);
i2c_scl_iobuf: component IOBUF
port map (
I => i2c_scl_o,
IO => i2c_scl_io,
O => i2c_scl_i,
T => i2c_scl_t
);
i2c_sda_iobuf: component IOBUF
port map (
I => i2c_sda_o,
IO => i2c_sda_io,
O => i2c_sda_i,
T => i2c_sda_t
);
led_4bits_tri_iobuf_0: component IOBUF
port map (
I => led_4bits_tri_o_0(0),
IO => led_4bits_tri_io(0),
O => led_4bits_tri_i_0(0),
T => led_4bits_tri_t_0(0)
);
led_4bits_tri_iobuf_1: component IOBUF
port map (
I => led_4bits_tri_o_1(1),
IO => led_4bits_tri_io(1),
O => led_4bits_tri_i_1(1),
T => led_4bits_tri_t_1(1)
);
led_4bits_tri_iobuf_2: component IOBUF
port map (
I => led_4bits_tri_o_2(2),
IO => led_4bits_tri_io(2),
O => led_4bits_tri_i_2(2),
T => led_4bits_tri_t_2(2)
);
led_4bits_tri_iobuf_3: component IOBUF
port map (
I => led_4bits_tri_o_3(3),
IO => led_4bits_tri_io(3),
O => led_4bits_tri_i_3(3),
T => led_4bits_tri_t_3(3)
);
qspi_flash_io0_iobuf: component IOBUF
port map (
I => qspi_flash_io0_o,
IO => qspi_flash_io0_io,
O => qspi_flash_io0_i,
T => qspi_flash_io0_t
);
qspi_flash_io1_iobuf: component IOBUF
port map (
I => qspi_flash_io1_o,
IO => qspi_flash_io1_io,
O => qspi_flash_io1_i,
T => qspi_flash_io1_t
);
qspi_flash_io2_iobuf: component IOBUF
port map (
I => qspi_flash_io2_o,
IO => qspi_flash_io2_io,
O => qspi_flash_io2_i,
T => qspi_flash_io2_t
);
qspi_flash_io3_iobuf: component IOBUF
port map (
I => qspi_flash_io3_o,
IO => qspi_flash_io3_io,
O => qspi_flash_io3_i,
T => qspi_flash_io3_t
);
qspi_flash_sck_iobuf: component IOBUF
port map (
I => qspi_flash_sck_o,
IO => qspi_flash_sck_io,
O => qspi_flash_sck_i,
T => qspi_flash_sck_t
);
qspi_flash_ss_iobuf: component IOBUF
port map (
I => qspi_flash_ss_o,
IO => qspi_flash_ss_io,
O => qspi_flash_ss_i,
T => qspi_flash_ss_t
);
rgb_led_tri_iobuf_0: component IOBUF
port map (
I => rgb_led_tri_o_0(0),
IO => rgb_led_tri_io(0),
O => rgb_led_tri_i_0(0),
T => rgb_led_tri_t_0(0)
);
rgb_led_tri_iobuf_1: component IOBUF
port map (
I => rgb_led_tri_o_1(1),
IO => rgb_led_tri_io(1),
O => rgb_led_tri_i_1(1),
T => rgb_led_tri_t_1(1)
);
rgb_led_tri_iobuf_10: component IOBUF
port map (
I => rgb_led_tri_o_10(10),
IO => rgb_led_tri_io(10),
O => rgb_led_tri_i_10(10),
T => rgb_led_tri_t_10(10)
);
rgb_led_tri_iobuf_11: component IOBUF
port map (
I => rgb_led_tri_o_11(11),
IO => rgb_led_tri_io(11),
O => rgb_led_tri_i_11(11),
T => rgb_led_tri_t_11(11)
);
rgb_led_tri_iobuf_2: component IOBUF
port map (
I => rgb_led_tri_o_2(2),
IO => rgb_led_tri_io(2),
O => rgb_led_tri_i_2(2),
T => rgb_led_tri_t_2(2)
);
rgb_led_tri_iobuf_3: component IOBUF
port map (
I => rgb_led_tri_o_3(3),
IO => rgb_led_tri_io(3),
O => rgb_led_tri_i_3(3),
T => rgb_led_tri_t_3(3)
);
rgb_led_tri_iobuf_4: component IOBUF
port map (
I => rgb_led_tri_o_4(4),
IO => rgb_led_tri_io(4),
O => rgb_led_tri_i_4(4),
T => rgb_led_tri_t_4(4)
);
rgb_led_tri_iobuf_5: component IOBUF
port map (
I => rgb_led_tri_o_5(5),
IO => rgb_led_tri_io(5),
O => rgb_led_tri_i_5(5),
T => rgb_led_tri_t_5(5)
);
rgb_led_tri_iobuf_6: component IOBUF
port map (
I => rgb_led_tri_o_6(6),
IO => rgb_led_tri_io(6),
O => rgb_led_tri_i_6(6),
T => rgb_led_tri_t_6(6)
);
rgb_led_tri_iobuf_7: component IOBUF
port map (
I => rgb_led_tri_o_7(7),
IO => rgb_led_tri_io(7),
O => rgb_led_tri_i_7(7),
T => rgb_led_tri_t_7(7)
);
rgb_led_tri_iobuf_8: component IOBUF
port map (
I => rgb_led_tri_o_8(8),
IO => rgb_led_tri_io(8),
O => rgb_led_tri_i_8(8),
T => rgb_led_tri_t_8(8)
);
rgb_led_tri_iobuf_9: component IOBUF
port map (
I => rgb_led_tri_o_9(9),
IO => rgb_led_tri_io(9),
O => rgb_led_tri_i_9(9),
T => rgb_led_tri_t_9(9)
);
shield_dp0_dp19_tri_iobuf_0: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_0(0),
IO => shield_dp0_dp19_tri_io(0),
O => shield_dp0_dp19_tri_i_0(0),
T => shield_dp0_dp19_tri_t_0(0)
);
shield_dp0_dp19_tri_iobuf_1: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_1(1),
IO => shield_dp0_dp19_tri_io(1),
O => shield_dp0_dp19_tri_i_1(1),
T => shield_dp0_dp19_tri_t_1(1)
);
shield_dp0_dp19_tri_iobuf_10: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_10(10),
IO => shield_dp0_dp19_tri_io(10),
O => shield_dp0_dp19_tri_i_10(10),
T => shield_dp0_dp19_tri_t_10(10)
);
shield_dp0_dp19_tri_iobuf_11: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_11(11),
IO => shield_dp0_dp19_tri_io(11),
O => shield_dp0_dp19_tri_i_11(11),
T => shield_dp0_dp19_tri_t_11(11)
);
shield_dp0_dp19_tri_iobuf_12: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_12(12),
IO => shield_dp0_dp19_tri_io(12),
O => shield_dp0_dp19_tri_i_12(12),
T => shield_dp0_dp19_tri_t_12(12)
);
shield_dp0_dp19_tri_iobuf_13: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_13(13),
IO => shield_dp0_dp19_tri_io(13),
O => shield_dp0_dp19_tri_i_13(13),
T => shield_dp0_dp19_tri_t_13(13)
);
shield_dp0_dp19_tri_iobuf_14: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_14(14),
IO => shield_dp0_dp19_tri_io(14),
O => shield_dp0_dp19_tri_i_14(14),
T => shield_dp0_dp19_tri_t_14(14)
);
shield_dp0_dp19_tri_iobuf_15: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_15(15),
IO => shield_dp0_dp19_tri_io(15),
O => shield_dp0_dp19_tri_i_15(15),
T => shield_dp0_dp19_tri_t_15(15)
);
shield_dp0_dp19_tri_iobuf_16: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_16(16),
IO => shield_dp0_dp19_tri_io(16),
O => shield_dp0_dp19_tri_i_16(16),
T => shield_dp0_dp19_tri_t_16(16)
);
shield_dp0_dp19_tri_iobuf_17: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_17(17),
IO => shield_dp0_dp19_tri_io(17),
O => shield_dp0_dp19_tri_i_17(17),
T => shield_dp0_dp19_tri_t_17(17)
);
shield_dp0_dp19_tri_iobuf_18: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_18(18),
IO => shield_dp0_dp19_tri_io(18),
O => shield_dp0_dp19_tri_i_18(18),
T => shield_dp0_dp19_tri_t_18(18)
);
shield_dp0_dp19_tri_iobuf_19: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_19(19),
IO => shield_dp0_dp19_tri_io(19),
O => shield_dp0_dp19_tri_i_19(19),
T => shield_dp0_dp19_tri_t_19(19)
);
shield_dp0_dp19_tri_iobuf_2: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_2(2),
IO => shield_dp0_dp19_tri_io(2),
O => shield_dp0_dp19_tri_i_2(2),
T => shield_dp0_dp19_tri_t_2(2)
);
shield_dp0_dp19_tri_iobuf_3: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_3(3),
IO => shield_dp0_dp19_tri_io(3),
O => shield_dp0_dp19_tri_i_3(3),
T => shield_dp0_dp19_tri_t_3(3)
);
shield_dp0_dp19_tri_iobuf_4: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_4(4),
IO => shield_dp0_dp19_tri_io(4),
O => shield_dp0_dp19_tri_i_4(4),
T => shield_dp0_dp19_tri_t_4(4)
);
shield_dp0_dp19_tri_iobuf_5: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_5(5),
IO => shield_dp0_dp19_tri_io(5),
O => shield_dp0_dp19_tri_i_5(5),
T => shield_dp0_dp19_tri_t_5(5)
);
shield_dp0_dp19_tri_iobuf_6: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_6(6),
IO => shield_dp0_dp19_tri_io(6),
O => shield_dp0_dp19_tri_i_6(6),
T => shield_dp0_dp19_tri_t_6(6)
);
shield_dp0_dp19_tri_iobuf_7: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_7(7),
IO => shield_dp0_dp19_tri_io(7),
O => shield_dp0_dp19_tri_i_7(7),
T => shield_dp0_dp19_tri_t_7(7)
);
shield_dp0_dp19_tri_iobuf_8: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_8(8),
IO => shield_dp0_dp19_tri_io(8),
O => shield_dp0_dp19_tri_i_8(8),
T => shield_dp0_dp19_tri_t_8(8)
);
shield_dp0_dp19_tri_iobuf_9: component IOBUF
port map (
I => shield_dp0_dp19_tri_o_9(9),
IO => shield_dp0_dp19_tri_io(9),
O => shield_dp0_dp19_tri_i_9(9),
T => shield_dp0_dp19_tri_t_9(9)
);
shield_dp26_dp41_tri_iobuf_0: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_0(0),
IO => shield_dp26_dp41_tri_io(0),
O => shield_dp26_dp41_tri_i_0(0),
T => shield_dp26_dp41_tri_t_0(0)
);
shield_dp26_dp41_tri_iobuf_1: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_1(1),
IO => shield_dp26_dp41_tri_io(1),
O => shield_dp26_dp41_tri_i_1(1),
T => shield_dp26_dp41_tri_t_1(1)
);
shield_dp26_dp41_tri_iobuf_10: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_10(10),
IO => shield_dp26_dp41_tri_io(10),
O => shield_dp26_dp41_tri_i_10(10),
T => shield_dp26_dp41_tri_t_10(10)
);
shield_dp26_dp41_tri_iobuf_11: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_11(11),
IO => shield_dp26_dp41_tri_io(11),
O => shield_dp26_dp41_tri_i_11(11),
T => shield_dp26_dp41_tri_t_11(11)
);
shield_dp26_dp41_tri_iobuf_12: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_12(12),
IO => shield_dp26_dp41_tri_io(12),
O => shield_dp26_dp41_tri_i_12(12),
T => shield_dp26_dp41_tri_t_12(12)
);
shield_dp26_dp41_tri_iobuf_13: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_13(13),
IO => shield_dp26_dp41_tri_io(13),
O => shield_dp26_dp41_tri_i_13(13),
T => shield_dp26_dp41_tri_t_13(13)
);
shield_dp26_dp41_tri_iobuf_14: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_14(14),
IO => shield_dp26_dp41_tri_io(14),
O => shield_dp26_dp41_tri_i_14(14),
T => shield_dp26_dp41_tri_t_14(14)
);
shield_dp26_dp41_tri_iobuf_15: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_15(15),
IO => shield_dp26_dp41_tri_io(15),
O => shield_dp26_dp41_tri_i_15(15),
T => shield_dp26_dp41_tri_t_15(15)
);
shield_dp26_dp41_tri_iobuf_2: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_2(2),
IO => shield_dp26_dp41_tri_io(2),
O => shield_dp26_dp41_tri_i_2(2),
T => shield_dp26_dp41_tri_t_2(2)
);
shield_dp26_dp41_tri_iobuf_3: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_3(3),
IO => shield_dp26_dp41_tri_io(3),
O => shield_dp26_dp41_tri_i_3(3),
T => shield_dp26_dp41_tri_t_3(3)
);
shield_dp26_dp41_tri_iobuf_4: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_4(4),
IO => shield_dp26_dp41_tri_io(4),
O => shield_dp26_dp41_tri_i_4(4),
T => shield_dp26_dp41_tri_t_4(4)
);
shield_dp26_dp41_tri_iobuf_5: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_5(5),
IO => shield_dp26_dp41_tri_io(5),
O => shield_dp26_dp41_tri_i_5(5),
T => shield_dp26_dp41_tri_t_5(5)
);
shield_dp26_dp41_tri_iobuf_6: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_6(6),
IO => shield_dp26_dp41_tri_io(6),
O => shield_dp26_dp41_tri_i_6(6),
T => shield_dp26_dp41_tri_t_6(6)
);
shield_dp26_dp41_tri_iobuf_7: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_7(7),
IO => shield_dp26_dp41_tri_io(7),
O => shield_dp26_dp41_tri_i_7(7),
T => shield_dp26_dp41_tri_t_7(7)
);
shield_dp26_dp41_tri_iobuf_8: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_8(8),
IO => shield_dp26_dp41_tri_io(8),
O => shield_dp26_dp41_tri_i_8(8),
T => shield_dp26_dp41_tri_t_8(8)
);
shield_dp26_dp41_tri_iobuf_9: component IOBUF
port map (
I => shield_dp26_dp41_tri_o_9(9),
IO => shield_dp26_dp41_tri_io(9),
O => shield_dp26_dp41_tri_i_9(9),
T => shield_dp26_dp41_tri_t_9(9)
);
spi_io0_iobuf: component IOBUF
port map (
I => spi_io0_o,
IO => spi_io0_io,
O => spi_io0_i,
T => spi_io0_t
);
spi_io1_iobuf: component IOBUF
port map (
I => spi_io1_o,
IO => spi_io1_io,
O => spi_io1_i,
T => spi_io1_t
);
spi_sck_iobuf: component IOBUF
port map (
I => spi_sck_o,
IO => spi_sck_io,
O => spi_sck_i,
T => spi_sck_t
);
spi_ss_iobuf: component IOBUF
port map (
I => spi_ss_o,
IO => spi_ss_io,
O => spi_ss_i,
T => spi_ss_t
);
system_i: component system
port map (
DDR3_addr(13 downto 0) => DDR3_addr(13 downto 0),
DDR3_ba(2 downto 0) => DDR3_ba(2 downto 0),
DDR3_cas_n => DDR3_cas_n,
DDR3_ck_n(0) => DDR3_ck_n(0),
DDR3_ck_p(0) => DDR3_ck_p(0),
DDR3_cke(0) => DDR3_cke(0),
DDR3_cs_n(0) => DDR3_cs_n(0),
DDR3_dm(1 downto 0) => DDR3_dm(1 downto 0),
DDR3_dq(15 downto 0) => DDR3_dq(15 downto 0),
DDR3_dqs_n(1 downto 0) => DDR3_dqs_n(1 downto 0),
DDR3_dqs_p(1 downto 0) => DDR3_dqs_p(1 downto 0),
DDR3_odt(0) => DDR3_odt(0),
DDR3_ras_n => DDR3_ras_n,
DDR3_reset_n => DDR3_reset_n,
DDR3_we_n => DDR3_we_n,
Vaux0_v_n => Vaux0_v_n,
Vaux0_v_p => Vaux0_v_p,
Vaux10_v_n => Vaux10_v_n,
Vaux10_v_p => Vaux10_v_p,
Vaux12_v_n => Vaux12_v_n,
Vaux12_v_p => Vaux12_v_p,
Vaux13_v_n => Vaux13_v_n,
Vaux13_v_p => Vaux13_v_p,
Vaux14_v_n => Vaux14_v_n,
Vaux14_v_p => Vaux14_v_p,
Vaux15_v_n => Vaux15_v_n,
Vaux15_v_p => Vaux15_v_p,
Vaux1_v_n => Vaux1_v_n,
Vaux1_v_p => Vaux1_v_p,
Vaux2_v_n => Vaux2_v_n,
Vaux2_v_p => Vaux2_v_p,
Vaux4_v_n => Vaux4_v_n,
Vaux4_v_p => Vaux4_v_p,
Vaux5_v_n => Vaux5_v_n,
Vaux5_v_p => Vaux5_v_p,
Vaux6_v_n => Vaux6_v_n,
Vaux6_v_p => Vaux6_v_p,
Vaux7_v_n => Vaux7_v_n,
Vaux7_v_p => Vaux7_v_p,
Vaux9_v_n => Vaux9_v_n,
Vaux9_v_p => Vaux9_v_p,
Vp_Vn_v_n => Vp_Vn_v_n,
Vp_Vn_v_p => Vp_Vn_v_p,
dip_switches_4bits_tri_i(3 downto 0) => dip_switches_4bits_tri_i(3 downto 0),
eth_mdio_mdc_mdc => eth_mdio_mdc_mdc,
eth_mdio_mdc_mdio_i => eth_mdio_mdc_mdio_i,
eth_mdio_mdc_mdio_o => eth_mdio_mdc_mdio_o,
eth_mdio_mdc_mdio_t => eth_mdio_mdc_mdio_t,
eth_mii_col => eth_mii_col,
eth_mii_crs => eth_mii_crs,
eth_mii_rst_n => eth_mii_rst_n,
eth_mii_rx_clk => eth_mii_rx_clk,
eth_mii_rx_dv => eth_mii_rx_dv,
eth_mii_rx_er => eth_mii_rx_er,
eth_mii_rxd(3 downto 0) => eth_mii_rxd(3 downto 0),
eth_mii_tx_clk => eth_mii_tx_clk,
eth_mii_tx_en => eth_mii_tx_en,
eth_mii_txd(3 downto 0) => eth_mii_txd(3 downto 0),
eth_ref_clk => eth_ref_clk,
i2c_pullups_tri_i(1) => i2c_pullups_tri_i_1(1),
i2c_pullups_tri_i(0) => i2c_pullups_tri_i_0(0),
i2c_pullups_tri_o(1) => i2c_pullups_tri_o_1(1),
i2c_pullups_tri_o(0) => i2c_pullups_tri_o_0(0),
i2c_pullups_tri_t(1) => i2c_pullups_tri_t_1(1),
i2c_pullups_tri_t(0) => i2c_pullups_tri_t_0(0),
i2c_scl_i => i2c_scl_i,
i2c_scl_o => i2c_scl_o,
i2c_scl_t => i2c_scl_t,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
led_4bits_tri_i(3) => led_4bits_tri_i_3(3),
led_4bits_tri_i(2) => led_4bits_tri_i_2(2),
led_4bits_tri_i(1) => led_4bits_tri_i_1(1),
led_4bits_tri_i(0) => led_4bits_tri_i_0(0),
led_4bits_tri_o(3) => led_4bits_tri_o_3(3),
led_4bits_tri_o(2) => led_4bits_tri_o_2(2),
led_4bits_tri_o(1) => led_4bits_tri_o_1(1),
led_4bits_tri_o(0) => led_4bits_tri_o_0(0),
led_4bits_tri_t(3) => led_4bits_tri_t_3(3),
led_4bits_tri_t(2) => led_4bits_tri_t_2(2),
led_4bits_tri_t(1) => led_4bits_tri_t_1(1),
led_4bits_tri_t(0) => led_4bits_tri_t_0(0),
push_buttons_4bits_tri_i(3 downto 0) => push_buttons_4bits_tri_i(3 downto 0),
qspi_flash_io0_i => qspi_flash_io0_i,
qspi_flash_io0_o => qspi_flash_io0_o,
qspi_flash_io0_t => qspi_flash_io0_t,
qspi_flash_io1_i => qspi_flash_io1_i,
qspi_flash_io1_o => qspi_flash_io1_o,
qspi_flash_io1_t => qspi_flash_io1_t,
qspi_flash_io2_i => qspi_flash_io2_i,
qspi_flash_io2_o => qspi_flash_io2_o,
qspi_flash_io2_t => qspi_flash_io2_t,
qspi_flash_io3_i => qspi_flash_io3_i,
qspi_flash_io3_o => qspi_flash_io3_o,
qspi_flash_io3_t => qspi_flash_io3_t,
qspi_flash_sck_i => qspi_flash_sck_i,
qspi_flash_sck_o => qspi_flash_sck_o,
qspi_flash_sck_t => qspi_flash_sck_t,
qspi_flash_ss_i => qspi_flash_ss_i,
qspi_flash_ss_o => qspi_flash_ss_o,
qspi_flash_ss_t => qspi_flash_ss_t,
reset => reset,
rgb_led_tri_i(11) => rgb_led_tri_i_11(11),
rgb_led_tri_i(10) => rgb_led_tri_i_10(10),
rgb_led_tri_i(9) => rgb_led_tri_i_9(9),
rgb_led_tri_i(8) => rgb_led_tri_i_8(8),
rgb_led_tri_i(7) => rgb_led_tri_i_7(7),
rgb_led_tri_i(6) => rgb_led_tri_i_6(6),
rgb_led_tri_i(5) => rgb_led_tri_i_5(5),
rgb_led_tri_i(4) => rgb_led_tri_i_4(4),
rgb_led_tri_i(3) => rgb_led_tri_i_3(3),
rgb_led_tri_i(2) => rgb_led_tri_i_2(2),
rgb_led_tri_i(1) => rgb_led_tri_i_1(1),
rgb_led_tri_i(0) => rgb_led_tri_i_0(0),
rgb_led_tri_o(11) => rgb_led_tri_o_11(11),
rgb_led_tri_o(10) => rgb_led_tri_o_10(10),
rgb_led_tri_o(9) => rgb_led_tri_o_9(9),
rgb_led_tri_o(8) => rgb_led_tri_o_8(8),
rgb_led_tri_o(7) => rgb_led_tri_o_7(7),
rgb_led_tri_o(6) => rgb_led_tri_o_6(6),
rgb_led_tri_o(5) => rgb_led_tri_o_5(5),
rgb_led_tri_o(4) => rgb_led_tri_o_4(4),
rgb_led_tri_o(3) => rgb_led_tri_o_3(3),
rgb_led_tri_o(2) => rgb_led_tri_o_2(2),
rgb_led_tri_o(1) => rgb_led_tri_o_1(1),
rgb_led_tri_o(0) => rgb_led_tri_o_0(0),
rgb_led_tri_t(11) => rgb_led_tri_t_11(11),
rgb_led_tri_t(10) => rgb_led_tri_t_10(10),
rgb_led_tri_t(9) => rgb_led_tri_t_9(9),
rgb_led_tri_t(8) => rgb_led_tri_t_8(8),
rgb_led_tri_t(7) => rgb_led_tri_t_7(7),
rgb_led_tri_t(6) => rgb_led_tri_t_6(6),
rgb_led_tri_t(5) => rgb_led_tri_t_5(5),
rgb_led_tri_t(4) => rgb_led_tri_t_4(4),
rgb_led_tri_t(3) => rgb_led_tri_t_3(3),
rgb_led_tri_t(2) => rgb_led_tri_t_2(2),
rgb_led_tri_t(1) => rgb_led_tri_t_1(1),
rgb_led_tri_t(0) => rgb_led_tri_t_0(0),
shield_dp0_dp19_tri_i(19) => shield_dp0_dp19_tri_i_19(19),
shield_dp0_dp19_tri_i(18) => shield_dp0_dp19_tri_i_18(18),
shield_dp0_dp19_tri_i(17) => shield_dp0_dp19_tri_i_17(17),
shield_dp0_dp19_tri_i(16) => shield_dp0_dp19_tri_i_16(16),
shield_dp0_dp19_tri_i(15) => shield_dp0_dp19_tri_i_15(15),
shield_dp0_dp19_tri_i(14) => shield_dp0_dp19_tri_i_14(14),
shield_dp0_dp19_tri_i(13) => shield_dp0_dp19_tri_i_13(13),
shield_dp0_dp19_tri_i(12) => shield_dp0_dp19_tri_i_12(12),
shield_dp0_dp19_tri_i(11) => shield_dp0_dp19_tri_i_11(11),
shield_dp0_dp19_tri_i(10) => shield_dp0_dp19_tri_i_10(10),
shield_dp0_dp19_tri_i(9) => shield_dp0_dp19_tri_i_9(9),
shield_dp0_dp19_tri_i(8) => shield_dp0_dp19_tri_i_8(8),
shield_dp0_dp19_tri_i(7) => shield_dp0_dp19_tri_i_7(7),
shield_dp0_dp19_tri_i(6) => shield_dp0_dp19_tri_i_6(6),
shield_dp0_dp19_tri_i(5) => shield_dp0_dp19_tri_i_5(5),
shield_dp0_dp19_tri_i(4) => shield_dp0_dp19_tri_i_4(4),
shield_dp0_dp19_tri_i(3) => shield_dp0_dp19_tri_i_3(3),
shield_dp0_dp19_tri_i(2) => shield_dp0_dp19_tri_i_2(2),
shield_dp0_dp19_tri_i(1) => shield_dp0_dp19_tri_i_1(1),
shield_dp0_dp19_tri_i(0) => shield_dp0_dp19_tri_i_0(0),
shield_dp0_dp19_tri_o(19) => shield_dp0_dp19_tri_o_19(19),
shield_dp0_dp19_tri_o(18) => shield_dp0_dp19_tri_o_18(18),
shield_dp0_dp19_tri_o(17) => shield_dp0_dp19_tri_o_17(17),
shield_dp0_dp19_tri_o(16) => shield_dp0_dp19_tri_o_16(16),
shield_dp0_dp19_tri_o(15) => shield_dp0_dp19_tri_o_15(15),
shield_dp0_dp19_tri_o(14) => shield_dp0_dp19_tri_o_14(14),
shield_dp0_dp19_tri_o(13) => shield_dp0_dp19_tri_o_13(13),
shield_dp0_dp19_tri_o(12) => shield_dp0_dp19_tri_o_12(12),
shield_dp0_dp19_tri_o(11) => shield_dp0_dp19_tri_o_11(11),
shield_dp0_dp19_tri_o(10) => shield_dp0_dp19_tri_o_10(10),
shield_dp0_dp19_tri_o(9) => shield_dp0_dp19_tri_o_9(9),
shield_dp0_dp19_tri_o(8) => shield_dp0_dp19_tri_o_8(8),
shield_dp0_dp19_tri_o(7) => shield_dp0_dp19_tri_o_7(7),
shield_dp0_dp19_tri_o(6) => shield_dp0_dp19_tri_o_6(6),
shield_dp0_dp19_tri_o(5) => shield_dp0_dp19_tri_o_5(5),
shield_dp0_dp19_tri_o(4) => shield_dp0_dp19_tri_o_4(4),
shield_dp0_dp19_tri_o(3) => shield_dp0_dp19_tri_o_3(3),
shield_dp0_dp19_tri_o(2) => shield_dp0_dp19_tri_o_2(2),
shield_dp0_dp19_tri_o(1) => shield_dp0_dp19_tri_o_1(1),
shield_dp0_dp19_tri_o(0) => shield_dp0_dp19_tri_o_0(0),
shield_dp0_dp19_tri_t(19) => shield_dp0_dp19_tri_t_19(19),
shield_dp0_dp19_tri_t(18) => shield_dp0_dp19_tri_t_18(18),
shield_dp0_dp19_tri_t(17) => shield_dp0_dp19_tri_t_17(17),
shield_dp0_dp19_tri_t(16) => shield_dp0_dp19_tri_t_16(16),
shield_dp0_dp19_tri_t(15) => shield_dp0_dp19_tri_t_15(15),
shield_dp0_dp19_tri_t(14) => shield_dp0_dp19_tri_t_14(14),
shield_dp0_dp19_tri_t(13) => shield_dp0_dp19_tri_t_13(13),
shield_dp0_dp19_tri_t(12) => shield_dp0_dp19_tri_t_12(12),
shield_dp0_dp19_tri_t(11) => shield_dp0_dp19_tri_t_11(11),
shield_dp0_dp19_tri_t(10) => shield_dp0_dp19_tri_t_10(10),
shield_dp0_dp19_tri_t(9) => shield_dp0_dp19_tri_t_9(9),
shield_dp0_dp19_tri_t(8) => shield_dp0_dp19_tri_t_8(8),
shield_dp0_dp19_tri_t(7) => shield_dp0_dp19_tri_t_7(7),
shield_dp0_dp19_tri_t(6) => shield_dp0_dp19_tri_t_6(6),
shield_dp0_dp19_tri_t(5) => shield_dp0_dp19_tri_t_5(5),
shield_dp0_dp19_tri_t(4) => shield_dp0_dp19_tri_t_4(4),
shield_dp0_dp19_tri_t(3) => shield_dp0_dp19_tri_t_3(3),
shield_dp0_dp19_tri_t(2) => shield_dp0_dp19_tri_t_2(2),
shield_dp0_dp19_tri_t(1) => shield_dp0_dp19_tri_t_1(1),
shield_dp0_dp19_tri_t(0) => shield_dp0_dp19_tri_t_0(0),
shield_dp26_dp41_tri_i(15) => shield_dp26_dp41_tri_i_15(15),
shield_dp26_dp41_tri_i(14) => shield_dp26_dp41_tri_i_14(14),
shield_dp26_dp41_tri_i(13) => shield_dp26_dp41_tri_i_13(13),
shield_dp26_dp41_tri_i(12) => shield_dp26_dp41_tri_i_12(12),
shield_dp26_dp41_tri_i(11) => shield_dp26_dp41_tri_i_11(11),
shield_dp26_dp41_tri_i(10) => shield_dp26_dp41_tri_i_10(10),
shield_dp26_dp41_tri_i(9) => shield_dp26_dp41_tri_i_9(9),
shield_dp26_dp41_tri_i(8) => shield_dp26_dp41_tri_i_8(8),
shield_dp26_dp41_tri_i(7) => shield_dp26_dp41_tri_i_7(7),
shield_dp26_dp41_tri_i(6) => shield_dp26_dp41_tri_i_6(6),
shield_dp26_dp41_tri_i(5) => shield_dp26_dp41_tri_i_5(5),
shield_dp26_dp41_tri_i(4) => shield_dp26_dp41_tri_i_4(4),
shield_dp26_dp41_tri_i(3) => shield_dp26_dp41_tri_i_3(3),
shield_dp26_dp41_tri_i(2) => shield_dp26_dp41_tri_i_2(2),
shield_dp26_dp41_tri_i(1) => shield_dp26_dp41_tri_i_1(1),
shield_dp26_dp41_tri_i(0) => shield_dp26_dp41_tri_i_0(0),
shield_dp26_dp41_tri_o(15) => shield_dp26_dp41_tri_o_15(15),
shield_dp26_dp41_tri_o(14) => shield_dp26_dp41_tri_o_14(14),
shield_dp26_dp41_tri_o(13) => shield_dp26_dp41_tri_o_13(13),
shield_dp26_dp41_tri_o(12) => shield_dp26_dp41_tri_o_12(12),
shield_dp26_dp41_tri_o(11) => shield_dp26_dp41_tri_o_11(11),
shield_dp26_dp41_tri_o(10) => shield_dp26_dp41_tri_o_10(10),
shield_dp26_dp41_tri_o(9) => shield_dp26_dp41_tri_o_9(9),
shield_dp26_dp41_tri_o(8) => shield_dp26_dp41_tri_o_8(8),
shield_dp26_dp41_tri_o(7) => shield_dp26_dp41_tri_o_7(7),
shield_dp26_dp41_tri_o(6) => shield_dp26_dp41_tri_o_6(6),
shield_dp26_dp41_tri_o(5) => shield_dp26_dp41_tri_o_5(5),
shield_dp26_dp41_tri_o(4) => shield_dp26_dp41_tri_o_4(4),
shield_dp26_dp41_tri_o(3) => shield_dp26_dp41_tri_o_3(3),
shield_dp26_dp41_tri_o(2) => shield_dp26_dp41_tri_o_2(2),
shield_dp26_dp41_tri_o(1) => shield_dp26_dp41_tri_o_1(1),
shield_dp26_dp41_tri_o(0) => shield_dp26_dp41_tri_o_0(0),
shield_dp26_dp41_tri_t(15) => shield_dp26_dp41_tri_t_15(15),
shield_dp26_dp41_tri_t(14) => shield_dp26_dp41_tri_t_14(14),
shield_dp26_dp41_tri_t(13) => shield_dp26_dp41_tri_t_13(13),
shield_dp26_dp41_tri_t(12) => shield_dp26_dp41_tri_t_12(12),
shield_dp26_dp41_tri_t(11) => shield_dp26_dp41_tri_t_11(11),
shield_dp26_dp41_tri_t(10) => shield_dp26_dp41_tri_t_10(10),
shield_dp26_dp41_tri_t(9) => shield_dp26_dp41_tri_t_9(9),
shield_dp26_dp41_tri_t(8) => shield_dp26_dp41_tri_t_8(8),
shield_dp26_dp41_tri_t(7) => shield_dp26_dp41_tri_t_7(7),
shield_dp26_dp41_tri_t(6) => shield_dp26_dp41_tri_t_6(6),
shield_dp26_dp41_tri_t(5) => shield_dp26_dp41_tri_t_5(5),
shield_dp26_dp41_tri_t(4) => shield_dp26_dp41_tri_t_4(4),
shield_dp26_dp41_tri_t(3) => shield_dp26_dp41_tri_t_3(3),
shield_dp26_dp41_tri_t(2) => shield_dp26_dp41_tri_t_2(2),
shield_dp26_dp41_tri_t(1) => shield_dp26_dp41_tri_t_1(1),
shield_dp26_dp41_tri_t(0) => shield_dp26_dp41_tri_t_0(0),
spi_io0_i => spi_io0_i,
spi_io0_o => spi_io0_o,
spi_io0_t => spi_io0_t,
spi_io1_i => spi_io1_i,
spi_io1_o => spi_io1_o,
spi_io1_t => spi_io1_t,
spi_sck_i => spi_sck_i,
spi_sck_o => spi_sck_o,
spi_sck_t => spi_sck_t,
spi_ss_i => spi_ss_i,
spi_ss_o => spi_ss_o,
spi_ss_t => spi_ss_t,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
end STRUCTURE;
|
apache-2.0
|
e308dbeeedcd265cf67c2fb17b275f54
| 0.594258 | 2.385456 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/Decoder3to8.vhd
| 1 | 1,800 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/17/2015 08:25:09 PM
-- Design Name:
-- Module Name: Decoder3to8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder3to8 is
Port
(
F : in BIT_VECTOR(2 downto 0); -- 3-Bit Function Code (Input)
X : out BIT_VECTOR(7 downto 0); -- 8-Bit State (Output)
Started: in BIT -- Is the CPU already running?
);
end Decoder3to8;
architecture Behavioral of Decoder3to8 is
begin
-- 000
X(0) <= not(F(0)) and not(F(1)) and not (F(2)) and Started after 1 ns;
-- 001
X(1) <= F(0) and not (F(1)) and not (F(2)) and Started after 1 ns;
-- 010
X(2) <= not(F(0)) and F(1) and not (F(2)) and Started after 1 ns;
-- 011
X(3) <= F(0) and F(1) and not (F(2)) and Started after 1 ns;
-- 100
X(4) <= not(F(0)) and not(F(1)) and F(2) and Started after 1 ns;
-- 101
X(5) <= F(0) and not(F(1)) and F(2) and Started after 1 ns;
-- 110
X(6) <= not(F(0)) and F(1) and F(2) and Started after 1 ns;
-- 111
X(7) <= F(0) and F(1) and F(2) and Started after 1 ns;
end Behavioral;
|
mit
|
408d0151c49fc7aade266984f52a8a3b
| 0.538889 | 3.358209 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/Debug Unit/ASCII_BUFFER_tb.vhd
| 1 | 4,190 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: DEBUG UNIT_tb
-- Project Name: DEBUG UNIT
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debug Unit Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ASCII_BUFFER_tb IS
END ASCII_BUFFER_tb;
ARCHITECTURE behavior OF ASCII_BUFFER_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ASCII_BUFFER
PORT(
ASCII_DATA : IN std_logic_vector(7 downto 0);
ASCII_RD : IN std_logic;
ASCII_WE : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
ASCII_BUFF : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal ASCII_DATA : std_logic_vector(7 downto 0) := (others => '0');
signal ASCII_RD : std_logic := '0';
signal ASCII_WE : std_logic := '0';
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--Outputs
signal ASCII_BUFF : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ASCII_BUFFER PORT MAP (
ASCII_DATA => ASCII_DATA,
ASCII_RD => ASCII_RD,
ASCII_WE => ASCII_WE,
CLK => CLK,
RST => RST,
ASCII_BUFF => ASCII_BUFF
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0'; wait for CLK_period/2;
CLK <= '1'; wait for CLK_period/2;
end process;
-- Stimulus process
tb: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
report "Start Debug Test Bench!" severity Note;
ASCII_DATA <= x"32"; -- 2 key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"46"; -- F key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"38"; -- 8 key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"30"; -- 0 key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"0D"; -- ENTER pressed
ASCII_WE <= '0';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
wait for 100 ns;
ASCII_DATA <= x"31"; -- 1 key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"64"; -- d key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"08"; -- BACKSPACE key is pressed
ASCII_WE <= '0';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"63"; -- c key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"35"; -- 5 key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"30"; -- 0 key is pressed
ASCII_WE <= '1';
wait for CLK_period;
ASCII_RD <= '1';
wait for CLK_period;
ASCII_RD <= '0';
wait for CLK_period;
ASCII_DATA <= x"0D"; -- ENTER pressed
ASCII_WE <= '0';
wait for CLK_PERIOD;
ASCII_RD <= '1';
wait for CLK_PERIOD;
ASCII_RD <= '0';
wait for CLK_PERIOD;
wait for 100 ns;
wait;
end process;
END;
|
mit
|
99321fc55222f567220a2859b7dbceab
| 0.555609 | 3.188737 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_sw_0/system_axi_gpio_sw_0_sim_netlist.vhdl
| 1 | 132,886 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:44:26 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_sw_0/system_axi_gpio_sw_0_sim_netlist.vhdl
-- Design : system_axi_gpio_sw_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0_address_decoder is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
gpio2_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\ip_irpt_enable_reg_reg[1]\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_sw_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_sw_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_sw_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[30]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[30]_i_3_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[31]_i_2_n_0\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC;
signal \^ipif_glbl_irpt_enable_reg_reg\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair2";
begin
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]\ <= \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\;
\ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\;
ipif_glbl_irpt_enable_reg_reg <= \^ipif_glbl_irpt_enable_reg_reg\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ipif_glbl_irpt_enable_reg_reg\,
R => '0'
);
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(3),
I1 => \Dual.gpio2_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(0)
);
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(2),
I1 => \Dual.gpio2_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(1)
);
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(1),
I1 => \Dual.gpio2_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(2)
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(0),
I1 => \Dual.gpio2_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(3)
);
\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(0)
);
\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(1)
);
\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(2)
);
\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(3)
);
\Dual.gpio2_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00001000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Dual.gpio2_Data_Out_reg[0]\(0)
);
\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF10000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => E(0)
);
\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Dual.gpio_Data_Out_reg[0]\(0)
);
\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00040000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I5 => bus2ip_reset,
O => \Dual.gpio_OE_reg[0]\(0)
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_10_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_9_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => p_8_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_7_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => \^ip2bus_data_i_d1_reg[0]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_5_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_4_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_3_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_2_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_arready\,
I2 => \^s_axi_wready\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out,
Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_16_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_15_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_14_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_13_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out,
Q => p_12_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out,
Q => p_11_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => irpt_wrack_d1,
I2 => p_8_in,
O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
O => intr_rd_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FE0000"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => ip2Bus_RdAck_intr_reg_hole_d1,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
O => intr_wr_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_2_in,
I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
I3 => p_14_in,
I4 => p_15_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_12_in,
I1 => p_13_in,
I2 => p_10_in,
I3 => p_11_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_5_in,
I1 => p_7_in,
I2 => p_3_in,
I3 => p_4_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
I4 => ip2Bus_WrAck_intr_reg_hole_d1,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(4),
I3 => \bus2ip_addr_i_reg[8]\(5),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => pselect_hit_i_1
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => pselect_hit_i_1,
Q => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"44444440"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => p_9_in,
I3 => p_8_in,
I4 => \^ip2bus_data_i_d1_reg[0]\,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_9_in,
I1 => p_8_in,
I2 => \^ip2bus_data_i_d1_reg[0]\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => ipif_glbl_irpt_enable_reg,
I1 => p_9_in,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
I3 => \^ip2bus_data_i_d1_reg[0]\,
I4 => p_8_in,
O => D(4)
);
\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(3),
O => D(3)
);
\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(2),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(2),
O => D(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEAE"
)
port map (
I0 => \ip2bus_data_i_D1[30]_i_2_n_0\,
I1 => GPIO_DBus_i(1),
I2 => \ip2bus_data_i_D1[30]_i_3_n_0\,
I3 => GPIO2_DBus_i(1),
O => D(1)
);
\ip2bus_data_i_D1[30]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA00C000"
)
port map (
I0 => p_1_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => \ip_irpt_enable_reg_reg[1]\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
I4 => p_8_in,
O => \ip2bus_data_i_D1[30]_i_2_n_0\
);
\ip2bus_data_i_D1[30]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \^dual.read_reg2_gen[3].gpio2_dbus_i_reg[31]\,
I3 => bus2ip_rnw_i_reg,
O => \ip2bus_data_i_D1[30]_i_3_n_0\
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEAE"
)
port map (
I0 => \ip2bus_data_i_D1[31]_i_2_n_0\,
I1 => GPIO_DBus_i(0),
I2 => \ip2bus_data_i_D1[30]_i_3_n_0\,
I3 => GPIO2_DBus_i(0),
O => D(0)
);
\ip2bus_data_i_D1[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA00C000"
)
port map (
I0 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => \ip_irpt_enable_reg_reg[0]\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
I4 => p_8_in,
O => \ip2bus_data_i_D1[31]_i_2_n_0\
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_9_in,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
I3 => ipif_glbl_irpt_enable_reg,
O => ipif_glbl_irpt_enable_reg_reg_0
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => p_9_in,
I1 => p_8_in,
I2 => \^ip2bus_data_i_d1_reg[0]\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => p_9_in,
I1 => p_8_in,
I2 => \^ip2bus_data_i_d1_reg[0]\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
O => irpt_wrack
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0_cdc_sync is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_sw_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_sw_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_sw_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(3 downto 0) <= \^scndry_vect_out\(3 downto 0);
\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Dual.gen_interrupt_dual.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0_cdc_sync_0 is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_sw_0_cdc_sync_0 : entity is "cdc_sync";
end system_axi_gpio_sw_0_cdc_sync_0;
architecture STRUCTURE of system_axi_gpio_sw_0_cdc_sync_0 is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(3 downto 0) <= \^scndry_vect_out\(3 downto 0);
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \Dual.gpio2_Data_In_reg[0]\(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : out STD_LOGIC;
p_1_in : out STD_LOGIC;
irpt_rdack_d1 : out STD_LOGIC;
ipif_glbl_irpt_enable_reg : out STD_LOGIC;
IP2INTC_Irpt_i : out STD_LOGIC;
\ip_irpt_enable_reg_reg[1]_0\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
GPIO_intr : in STD_LOGIC;
GPIO2_intr : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_sw_0_interrupt_control : entity is "interrupt_control";
end system_axi_gpio_sw_0_interrupt_control;
architecture STRUCTURE of system_axi_gpio_sw_0_interrupt_control is
signal \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\ : STD_LOGIC;
signal \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\ : STD_LOGIC;
signal intr2bus_rdack : STD_LOGIC;
signal intr2bus_wrack : STD_LOGIC;
signal \ip_irpt_enable_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \ip_irpt_enable_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[0]_0\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[1]_0\ : STD_LOGIC;
signal \^ipif_glbl_irpt_enable_reg\ : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
begin
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\;
\ip_irpt_enable_reg_reg[0]_0\ <= \^ip_irpt_enable_reg_reg[0]_0\;
\ip_irpt_enable_reg_reg[1]_0\ <= \^ip_irpt_enable_reg_reg[1]_0\;
ipif_glbl_irpt_enable_reg <= \^ipif_glbl_irpt_enable_reg\;
p_1_in <= \^p_1_in\;
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_intr,
Q => irpt_dly1,
S => bus2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => bus2ip_reset
);
\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO2_intr,
Q => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
S => bus2ip_reset
);
\DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
Q => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
S => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F44FF4F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
I3 => Bus_RNW_reg_reg,
I4 => s_axi_wdata(0),
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
R => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F44FF4F4"
)
port map (
I0 => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly2_reg_n_0\,
I1 => \DO_IRPT_INPUT[1].GEN_POS_EDGE_DETECT.irpt_dly1_reg_n_0\,
I2 => \^p_1_in\,
I3 => Bus_RNW_reg_reg,
I4 => s_axi_wdata(1),
O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1_n_0\,
Q => \^p_1_in\,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[1]_0\,
I1 => \^p_1_in\,
I2 => \^ipif_glbl_irpt_enable_reg\,
I3 => \^ip_irpt_enable_reg_reg[0]_0\,
I4 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
O => IP2INTC_Irpt_i
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr2bus_rdack,
R => bus2ip_reset
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr2bus_wrack,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => intr2bus_rdack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole,
I1 => intr2bus_wrack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_wrack_i
);
\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_6_in,
I2 => Bus_RNW_reg,
I3 => \^ip_irpt_enable_reg_reg[0]_0\,
O => \ip_irpt_enable_reg[0]_i_1_n_0\
);
\ip_irpt_enable_reg[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => p_6_in,
I2 => Bus_RNW_reg,
I3 => \^ip_irpt_enable_reg_reg[1]_0\,
O => \ip_irpt_enable_reg[1]_i_1_n_0\
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ip_irpt_enable_reg[0]_i_1_n_0\,
Q => \^ip_irpt_enable_reg_reg[0]_0\,
R => bus2ip_reset
);
\ip_irpt_enable_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ip_irpt_enable_reg[1]_i_1_n_0\,
Q => \^ip_irpt_enable_reg_reg[1]_0\,
R => bus2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\,
Q => \^ipif_glbl_irpt_enable_reg\,
R => bus2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => bus2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => irpt_wrack_d1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0_GPIO_Core is
port (
GPIO2_DBus_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
GPIO_intr : out STD_LOGIC;
GPIO2_intr : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
Read_Reg2_In : in STD_LOGIC_VECTOR ( 0 to 3 );
s_axi_aclk : in STD_LOGIC;
Read_Reg_In : in STD_LOGIC_VECTOR ( 0 to 3 );
bus2ip_reset : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_sw_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_sw_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_sw_0_GPIO_Core is
signal \^dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Read_Reg_Rst : STD_LOGIC;
signal gpio2_data_in_xor : STD_LOGIC_VECTOR ( 0 to 3 );
signal gpio2_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 3 );
signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 3 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 3 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal or_ints : STD_LOGIC;
signal or_ints2 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_0_in2_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_1_in3_in : STD_LOGIC;
begin
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(3 downto 0) <= \^dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(3 downto 0);
GPIO_xferAck_i <= \^gpio_xferack_i\;
Q(3 downto 0) <= \^q\(3 downto 0);
\Dual.INPUT_DOUBLE_REGS4\: entity work.system_axi_gpio_sw_0_cdc_sync
port map (
D(3) => gpio_data_in_xor(0),
D(2) => gpio_data_in_xor(1),
D(1) => gpio_data_in_xor(2),
D(0) => gpio_data_in_xor(3),
Q(3 downto 0) => \^q\(3 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(3) => gpio_io_i_d2(0),
scndry_vect_out(2) => gpio_io_i_d2(1),
scndry_vect_out(1) => gpio_io_i_d2(2),
scndry_vect_out(0) => gpio_io_i_d2(3)
);
\Dual.INPUT_DOUBLE_REGS5\: entity work.system_axi_gpio_sw_0_cdc_sync_0
port map (
D(3) => gpio2_data_in_xor(0),
D(2) => gpio2_data_in_xor(1),
D(1) => gpio2_data_in_xor(2),
D(0) => gpio2_data_in_xor(3),
\Dual.gpio2_Data_In_reg[0]\(3 downto 0) => \^dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(3 downto 0),
gpio2_io_i(3 downto 0) => gpio2_io_i(3 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(3) => gpio2_io_i_d2(0),
scndry_vect_out(2) => gpio2_io_i_d2(1),
scndry_vect_out(1) => gpio2_io_i_d2(2),
scndry_vect_out(0) => gpio2_io_i_d2(3)
);
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(0),
Q => GPIO2_DBus_i(3),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(1),
Q => GPIO2_DBus_i(2),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(2),
Q => GPIO2_DBus_i(1),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => gpio_xferAck_Reg,
I1 => \^gpio_xferack_i\,
I2 => bus2ip_rnw,
I3 => bus2ip_cs(0),
O => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(3),
Q => GPIO2_DBus_i(0),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(0),
Q => GPIO_DBus_i(3),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(1),
Q => GPIO_DBus_i(2),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(2),
Q => GPIO_DBus_i(1),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(3),
Q => GPIO_DBus_i(0),
R => Read_Reg_Rst
);
\Dual.gen_interrupt_dual.GPIO2_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints2,
Q => GPIO2_intr,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.GPIO_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints,
Q => GPIO_intr,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_data_in_xor(0),
Q => \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_data_in_xor(1),
Q => p_0_in,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_data_in_xor(2),
Q => p_1_in,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_data_in_xor(3),
Q => \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[3]\,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(0),
Q => \Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(1),
Q => p_0_in2_in,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(2),
Q => p_1_in3_in,
R => bus2ip_reset
);
\Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(3),
Q => \Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[3]\,
R => bus2ip_reset
);
\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(0),
Q => \^dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(3),
R => '0'
);
\Dual.gpio2_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(1),
Q => \^dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(2),
R => '0'
);
\Dual.gpio2_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(2),
Q => \^dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(1),
R => '0'
);
\Dual.gpio2_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(3),
Q => \^dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(0),
R => '0'
);
\Dual.gpio2_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => s_axi_wdata(3),
Q => gpio2_io_o(3),
R => bus2ip_reset
);
\Dual.gpio2_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => s_axi_wdata(2),
Q => gpio2_io_o(2),
R => bus2ip_reset
);
\Dual.gpio2_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => s_axi_wdata(1),
Q => gpio2_io_o(1),
R => bus2ip_reset
);
\Dual.gpio2_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => s_axi_wdata(0),
Q => gpio2_io_o(0),
R => bus2ip_reset
);
\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => s_axi_wdata(3),
Q => gpio2_io_t(3),
S => bus2ip_reset
);
\Dual.gpio2_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => s_axi_wdata(2),
Q => gpio2_io_t(2),
S => bus2ip_reset
);
\Dual.gpio2_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => s_axi_wdata(1),
Q => gpio2_io_t(1),
S => bus2ip_reset
);
\Dual.gpio2_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => s_axi_wdata(0),
Q => gpio2_io_t(0),
S => bus2ip_reset
);
\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \^q\(3),
R => '0'
);
\Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \^q\(2),
R => '0'
);
\Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \^q\(1),
R => '0'
);
\Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \^q\(0),
R => '0'
);
\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => gpio_io_o(3),
R => bus2ip_reset
);
\Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => gpio_io_o(2),
R => bus2ip_reset
);
\Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => gpio_io_o(1),
R => bus2ip_reset
);
\Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => gpio_io_o(0),
R => bus2ip_reset
);
\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => s_axi_wdata(3),
Q => gpio_io_t(3),
S => bus2ip_reset
);
\Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => s_axi_wdata(2),
Q => gpio_io_t(2),
S => bus2ip_reset
);
\Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => s_axi_wdata(1),
Q => gpio_io_t(1),
S => bus2ip_reset
);
\Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => s_axi_wdata(0),
Q => gpio_io_t(0),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => gpio_xferAck_Reg,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => gpio_xferAck_Reg,
I1 => bus2ip_cs(0),
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
or_reduce: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_0_in2_in,
I1 => p_1_in3_in,
I2 => \Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[0]\,
I3 => \Dual.gen_interrupt_dual.gpio_data_in_xor_reg_reg_n_0_[3]\,
O => or_ints
);
\or_reduce_inferred__0/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_0_in,
I1 => p_1_in,
I2 => \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[0]\,
I3 => \Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg_n_0_[3]\,
O => or_ints2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0_slave_attachment is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC;
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
gpio2_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\ip_irpt_enable_reg_reg[1]\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_sw_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_sw_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_sw_0_slave_attachment is
signal \^dual.gpio2_oe_reg[0]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair5";
begin
\Dual.gpio2_OE_reg[0]\ <= \^dual.gpio2_oe_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_sw_0_address_decoder
port map (
D(4 downto 0) => D(4 downto 0),
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]\ => \Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]\,
\Dual.gpio2_Data_In_reg[0]\(3 downto 0) => Q(3 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio_Data_In_reg[0]\(3 downto 0) => \Dual.gpio_Data_In_reg[0]\(3 downto 0),
\Dual.gpio_Data_Out_reg[0]\(0) => \Dual.gpio_Data_Out_reg[0]\(0),
\Dual.gpio_OE_reg[0]\(0) => \Dual.gpio_OE_reg[0]\(0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\,
GPIO2_DBus_i(3 downto 0) => GPIO2_DBus_i(3 downto 0),
GPIO_DBus_i(3 downto 0) => GPIO_DBus_i(3 downto 0),
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg2_In(0 to 3) => Read_Reg2_In(0 to 3),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
\bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1),
\bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2),
\bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3),
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg => \^dual.gpio2_oe_reg[0]\,
gpio2_io_t(3 downto 0) => gpio2_io_t(3 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[1]\ => \ip_irpt_enable_reg_reg[1]\,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg_0,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_1_in => p_1_in,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(0) => s_axi_wdata(0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \p_1_in__0\(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \p_1_in__0\(3)
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \p_1_in__0\(4)
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(3),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(3),
O => \p_1_in__0\(5)
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(4),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(4),
O => \p_1_in__0\(6)
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(5),
O => \p_1_in__0\(7)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(6),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \p_1_in__0\(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(2),
Q => bus2ip_addr(6),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(3),
Q => bus2ip_addr(5),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(4),
Q => bus2ip_addr(4),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(5),
Q => bus2ip_addr(3),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(6),
Q => bus2ip_addr(2),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(7),
Q => bus2ip_addr(1),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(8),
Q => bus2ip_addr(0),
R => bus2ip_reset
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^dual.gpio2_oe_reg[0]\,
R => bus2ip_reset
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => bus2ip_reset
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => bus2ip_reset
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => bus2ip_reset
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_0\(0),
Q => s_axi_rdata(0),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_0\(1),
Q => s_axi_rdata(1),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_0\(2),
Q => s_axi_rdata(2),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_0\(4),
Q => s_axi_rdata(4),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_0\(3),
Q => s_axi_rdata(3),
R => bus2ip_reset
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => bus2ip_reset
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => bus2ip_reset
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \p_0_out__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \p_0_out__0\(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(0),
Q => state(0),
R => bus2ip_reset
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(1),
Q => state(1),
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0_axi_lite_ipif is
port (
p_6_in : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
\Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
gpio2_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\ip_irpt_enable_reg_reg[1]\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : in STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_sw_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_sw_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_sw_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_sw_0_slave_attachment
port map (
D(4 downto 0) => D(4 downto 0),
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]\ => bus2ip_cs(0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\ => bus2ip_rnw,
\Dual.gpio_Data_In_reg[0]\(3 downto 0) => \Dual.gpio_Data_In_reg[0]\(3 downto 0),
\Dual.gpio_Data_Out_reg[0]\(0) => \Dual.gpio_Data_Out_reg[0]\(0),
\Dual.gpio_OE_reg[0]\(0) => \Dual.gpio_OE_reg[0]\(0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\,
GPIO2_DBus_i(3 downto 0) => GPIO2_DBus_i(3 downto 0),
GPIO_DBus_i(3 downto 0) => GPIO_DBus_i(3 downto 0),
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
Q(3 downto 0) => Q(3 downto 0),
Read_Reg2_In(0 to 3) => Read_Reg2_In(0 to 3),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
bus2ip_reset => bus2ip_reset,
gpio2_io_t(3 downto 0) => gpio2_io_t(3 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]\ => p_6_in,
\ip2bus_data_i_D1_reg[0]_0\(4 downto 0) => \ip2bus_data_i_D1_reg[0]\(4 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[1]\ => \ip_irpt_enable_reg_reg[1]\,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => Bus_RNW_reg,
ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_1_in => p_1_in,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(4 downto 0) => s_axi_rdata(4 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(0) => s_axi_wdata(0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_sw_0_axi_gpio : entity is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_sw_0_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_sw_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_sw_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_sw_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_sw_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_sw_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_sw_0_axi_gpio : entity is 4;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_sw_0_axi_gpio : entity is 4;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_sw_0_axi_gpio : entity is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_sw_0_axi_gpio : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_sw_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_sw_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_sw_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_sw_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_sw_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_sw_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_sw_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_sw_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_sw_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_23 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_24 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC;
signal GPIO2_DBus_i : STD_LOGIC_VECTOR ( 28 to 31 );
signal GPIO2_intr : STD_LOGIC;
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 28 to 31 );
signal GPIO_intr : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_6\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_7\ : STD_LOGIC;
signal IP2INTC_Irpt_i : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\ : STD_LOGIC;
signal Read_Reg2_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal Read_Reg_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_reset_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio2_Data_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal \^gpio2_io_t\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interrupt_wrce_strb : STD_LOGIC;
signal intr2bus_rdack0 : STD_LOGIC;
signal intr_rd_ce_or_reduce : STD_LOGIC;
signal intr_wr_ce_or_reduce : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 28 to 29 );
signal ip2bus_data_i : STD_LOGIC_VECTOR ( 30 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal ipif_glbl_irpt_enable_reg : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH";
begin
gpio2_io_t(3 downto 0) <= \^gpio2_io_t\(3 downto 0);
gpio_io_t(3 downto 0) <= \^gpio_io_t\(3 downto 0);
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3 downto 0) <= \^s_axi_rdata\(3 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_sw_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(4) => p_0_out(0),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data_i(30),
D(0) => ip2bus_data_i(31),
\Dual.gpio2_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_13,
\Dual.gpio_Data_In_reg[0]\(3) => gpio_Data_In(0),
\Dual.gpio_Data_In_reg[0]\(2) => gpio_Data_In(1),
\Dual.gpio_Data_In_reg[0]\(1) => gpio_Data_In(2),
\Dual.gpio_Data_In_reg[0]\(0) => gpio_Data_In(3),
\Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_24,
\Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_23,
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => AXI_LITE_IPIF_I_n_29,
GPIO2_DBus_i(3) => GPIO2_DBus_i(28),
GPIO2_DBus_i(2) => GPIO2_DBus_i(29),
GPIO2_DBus_i(1) => GPIO2_DBus_i(30),
GPIO2_DBus_i(0) => GPIO2_DBus_i(31),
GPIO_DBus_i(3) => GPIO_DBus_i(28),
GPIO_DBus_i(2) => GPIO_DBus_i(29),
GPIO_DBus_i(1) => GPIO_DBus_i(30),
GPIO_DBus_i(0) => GPIO_DBus_i(31),
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_30,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_32,
Q(3) => gpio2_Data_In(0),
Q(2) => gpio2_Data_In(1),
Q(1) => gpio2_Data_In(2),
Q(0) => gpio2_Data_In(3),
Read_Reg2_In(0 to 3) => Read_Reg2_In(0 to 3),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio2_io_t(3 downto 0) => \^gpio2_io_t\(3 downto 0),
gpio_io_t(3 downto 0) => \^gpio_io_t\(3 downto 0),
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]\(4) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_7\,
\ip_irpt_enable_reg_reg[1]\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_6\,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_34,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_1_in => p_1_in,
p_6_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(4) => \^s_axi_rdata\(31),
s_axi_rdata(3 downto 0) => \^s_axi_rdata\(3 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(0) => s_axi_wdata(31),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.system_axi_gpio_sw_0_interrupt_control
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_29,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_34,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_1\,
GPIO2_intr => GPIO2_intr,
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
IP2INTC_Irpt_i => IP2INTC_Irpt_i,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
\ip_irpt_enable_reg_reg[0]_0\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_7\,
\ip_irpt_enable_reg_reg[1]_0\ => \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I_n_6\,
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_1_in => p_1_in,
p_6_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0)
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_30,
Q => ip2Bus_RdAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_32,
Q => ip2Bus_WrAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2INTC_Irpt_i,
Q => ip2intc_irpt,
R => bus2ip_reset
);
bus2ip_reset_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => bus2ip_reset_i_1_n_0
);
bus2ip_reset_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset_i_1_n_0,
Q => bus2ip_reset,
R => '0'
);
gpio_core_1: entity work.system_axi_gpio_sw_0_GPIO_Core
port map (
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(3) => gpio2_Data_In(0),
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(2) => gpio2_Data_In(1),
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(1) => gpio2_Data_In(2),
\Dual.gen_interrupt_dual.gpio2_data_in_xor_reg_reg[0]_0\(0) => gpio2_Data_In(3),
E(0) => AXI_LITE_IPIF_I_n_24,
GPIO2_DBus_i(3) => GPIO2_DBus_i(28),
GPIO2_DBus_i(2) => GPIO2_DBus_i(29),
GPIO2_DBus_i(1) => GPIO2_DBus_i(30),
GPIO2_DBus_i(0) => GPIO2_DBus_i(31),
GPIO2_intr => GPIO2_intr,
GPIO_DBus_i(3) => GPIO_DBus_i(28),
GPIO_DBus_i(2) => GPIO_DBus_i(29),
GPIO_DBus_i(1) => GPIO_DBus_i(30),
GPIO_DBus_i(0) => GPIO_DBus_i(31),
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
Q(3) => gpio_Data_In(0),
Q(2) => gpio_Data_In(1),
Q(1) => gpio_Data_In(2),
Q(0) => gpio_Data_In(3),
Read_Reg2_In(0 to 3) => Read_Reg2_In(0 to 3),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_23,
bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_13,
bus2ip_rnw_i_reg_1(0) => AXI_LITE_IPIF_I_n_12,
gpio2_io_i(3 downto 0) => gpio2_io_i(3 downto 0),
gpio2_io_o(3 downto 0) => gpio2_io_o(3 downto 0),
gpio2_io_t(3 downto 0) => \^gpio2_io_t\(3 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
gpio_io_o(3 downto 0) => gpio_io_o(3 downto 0),
gpio_io_t(3 downto 0) => \^gpio_io_t\(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(3 downto 0) => s_axi_wdata(3 downto 0)
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_sw_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_sw_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_sw_0 : entity is "system_axi_gpio_sw_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_sw_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_sw_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_sw_0;
architecture STRUCTURE of system_axi_gpio_sw_0 is
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 4;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 4;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_sw_0_axi_gpio
port map (
gpio2_io_i(3 downto 0) => gpio2_io_i(3 downto 0),
gpio2_io_o(3 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(3 downto 0),
gpio2_io_t(3 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(3 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
gpio_io_o(3 downto 0) => NLW_U0_gpio_io_o_UNCONNECTED(3 downto 0),
gpio_io_t(3 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(3 downto 0),
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
2d23d6d570c9d4cfe8cad88d82c63502
| 0.585698 | 2.57536 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/FlipFlop1Bit2WayInput.vhd
| 1 | 1,868 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/28/2015 07:11:32 PM
-- Design Name:
-- Module Name: FlipFlop1Bit2WayInput - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FlipFlop1Bit2WayInput is
Port
(
Load1 : in BIT; -- Load Line #1
Load2 : in BIT; -- Load Line #2
Sel : in BIT; -- Select Line
Input1 : in BIT; -- Input Data #1
Input2 : in BIT; -- Input Data #2
Output : out BIT; -- Output Data
State : out BIT -- Current state of the Flip Flop
);
end FlipFlop1Bit2WayInput;
architecture Behavioral of FlipFlop1Bit2WayInput is
signal Nand1 : BIT;
signal Nand2 : BIT;
signal Not1 : BIT;
signal F1 : BIT;
signal F2 : BIT;
signal Load: BIT;
signal Input: BIT;
begin
-- We accept input from 2 inputs
Load <= Load1 or Load2;
Input <= Input1 or Input2;
Nand1 <= not(Load and Input);
Not1 <= not Input;
Nand2 <= not(Not1 and Load);
F1 <= not (F2 and Nand1);
F2 <= not (Nand2 and F1) after 1 ns;
-- Return the internal state for debugging/monitoring purposes
State <= F1;
Output <= F1 and Sel;
end Behavioral;
|
mit
|
c9cad6d2114f71d80490e9faed5ef9ba
| 0.562099 | 3.92437 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_timer_0_0/system_axi_timer_0_0_sim_netlist.vhdl
| 1 | 420,504 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:47 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_timer_0_0/system_axi_timer_0_0_sim_netlist.vhdl
-- Design : system_axi_timer_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_cdc_sync is
port (
captureTrig0_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_cdc_sync : entity is "cdc_sync";
end system_axi_timer_0_0_cdc_sync;
architecture STRUCTURE of system_axi_timer_0_0_cdc_sync is
signal CaptureTrig0_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig0,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig0_int,
R => '0'
);
captureTrig0_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig0_int,
O => captureTrig0_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_cdc_sync_1 is
port (
captureTrig1_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_cdc_sync_1 : entity is "cdc_sync";
end system_axi_timer_0_0_cdc_sync_1;
architecture STRUCTURE of system_axi_timer_0_0_cdc_sync_1 is
signal CaptureTrig1_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig1_int,
R => '0'
);
captureTrig1_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig1_int,
O => captureTrig1_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_cdc_sync_2 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[32]\ : out STD_LOGIC;
counter_En : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[32]_0\ : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
\Load_Counter_Reg153_out__1\ : in STD_LOGIC;
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR0_GENERATE[27].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR0_GENERATE[20].TCSR0_FF_I_0\ : in STD_LOGIC;
Counter_En17_out : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[32]_1\ : in STD_LOGIC;
\TCSR1_GENERATE[30].TCSR1_FF_I\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
generateOutPre0 : in STD_LOGIC;
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 1 downto 0 );
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_cdc_sync_2 : entity is "cdc_sync";
end system_axi_timer_0_0_cdc_sync_2;
architecture STRUCTURE of system_axi_timer_0_0_cdc_sync_2 is
signal Freeze_int : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_7_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[32]_i_4_n_0\ : STD_LOGIC;
signal \^counter_en\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_7\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[32]_i_4\ : label is "soft_lutpair45";
begin
counter_En(0) <= \^counter_en\(0);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => freeze,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => Freeze_int,
R => '0'
);
\INFERRED_GEN.icount_out[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF080808"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[32]_0\,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => Freeze_int,
I3 => \Load_Counter_Reg153_out__1\,
I4 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I5 => \TCSR0_GENERATE[27].TCSR0_FF_I\,
O => E(0)
);
\INFERRED_GEN.icount_out[31]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => load_Counter_Reg(0),
I1 => \^counter_en\(0),
O => \INFERRED_GEN.icount_out_reg[0]\(0)
);
\INFERRED_GEN.icount_out[31]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888F88888"
)
port map (
I0 => Counter_En17_out,
I1 => \INFERRED_GEN.icount_out[31]_i_7_n_0\,
I2 => \INFERRED_GEN.icount_out_reg[32]_1\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \TCSR1_GENERATE[24].TCSR1_FF_I\,
I5 => Freeze_int,
O => \^counter_en\(0)
);
\INFERRED_GEN.icount_out[31]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I2 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I3 => generateOutPre0,
O => \INFERRED_GEN.icount_out[31]_i_7_n_0\
);
\INFERRED_GEN.icount_out[32]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0C0C0AA808080"
)
port map (
I0 => \TCSR0_GENERATE[20].TCSR0_FF_I_0\,
I1 => Counter_En17_out,
I2 => \INFERRED_GEN.icount_out[31]_i_7_n_0\,
I3 => \INFERRED_GEN.icount_out_reg[32]_1\,
I4 => \INFERRED_GEN.icount_out[32]_i_4_n_0\,
I5 => \TCSR1_GENERATE[30].TCSR1_FF_I\,
O => \INFERRED_GEN.icount_out_reg[32]\
);
\INFERRED_GEN.icount_out[32]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I1 => \TCSR1_GENERATE[24].TCSR1_FF_I\,
I2 => Freeze_int,
O => \INFERRED_GEN.icount_out[32]_i_4_n_0\
);
icount_out0_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"56AA9AAA"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(0),
I1 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I2 => read_Mux_In(0),
I3 => \^counter_en\(0),
I4 => read_Mux_In(1),
O => S(0)
);
\icount_out0_carry_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAAA"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(1),
I1 => Freeze_int,
I2 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I3 => \INFERRED_GEN.icount_out_reg[32]_0\,
I4 => read_Mux_In(1),
O => \INFERRED_GEN.icount_out_reg[4]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_counter_f is
port (
read_Mux_In : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
generateOutPre10 : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\LOAD_REG_GEN[0].LOAD_REG_I\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
counter_En : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_counter_f : entity is "counter_f";
end system_axi_timer_0_0_counter_f;
architecture STRUCTURE of system_axi_timer_0_0_counter_f is
signal \INFERRED_GEN.icount_out[0]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[10]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[11]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[12]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[13]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[14]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[15]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[16]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[17]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[18]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[19]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[1]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[20]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[21]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[22]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[23]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[24]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[25]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[26]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[27]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[28]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[29]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[2]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[30]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_2__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[3]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[4]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[5]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[6]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[7]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[8]_i_1__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal icount_out0_carry_i_1_n_0 : STD_LOGIC;
signal icount_out0_carry_i_2_n_0 : STD_LOGIC;
signal icount_out0_carry_i_3_n_0 : STD_LOGIC;
signal icount_out0_carry_i_4_n_0 : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1__0\ : label is "soft_lutpair40";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
SR(0) <= \^sr\(0);
counter_TC(0) <= \^counter_tc\(0);
read_Mux_In(31 downto 0) <= \^read_mux_in\(31 downto 0);
GenerateOut0_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\INFERRED_GEN.icount_out[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(0),
I1 => load_Counter_Reg(0),
I2 => \^read_mux_in\(0),
O => \INFERRED_GEN.icount_out[0]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_6\,
O => \INFERRED_GEN.icount_out[10]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(11),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_5\,
O => \INFERRED_GEN.icount_out[11]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(12),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_4\,
O => \INFERRED_GEN.icount_out[12]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(13),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_7\,
O => \INFERRED_GEN.icount_out[13]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(14),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_6\,
O => \INFERRED_GEN.icount_out[14]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(15),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_5\,
O => \INFERRED_GEN.icount_out[15]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(16),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_4\,
O => \INFERRED_GEN.icount_out[16]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(17),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_7\,
O => \INFERRED_GEN.icount_out[17]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(18),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_6\,
O => \INFERRED_GEN.icount_out[18]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(19),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_5\,
O => \INFERRED_GEN.icount_out[19]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(1),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_7,
O => \INFERRED_GEN.icount_out[1]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(20),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_4\,
O => \INFERRED_GEN.icount_out[20]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(21),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_7\,
O => \INFERRED_GEN.icount_out[21]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(22),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_6\,
O => \INFERRED_GEN.icount_out[22]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(23),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_5\,
O => \INFERRED_GEN.icount_out[23]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(24),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_4\,
O => \INFERRED_GEN.icount_out[24]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(25),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_7\,
O => \INFERRED_GEN.icount_out[25]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(26),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_6\,
O => \INFERRED_GEN.icount_out[26]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(27),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_5\,
O => \INFERRED_GEN.icount_out[27]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(28),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_4\,
O => \INFERRED_GEN.icount_out[28]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(29),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_7\,
O => \INFERRED_GEN.icount_out[29]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(2),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_6,
O => \INFERRED_GEN.icount_out[2]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(30),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_6\,
O => \INFERRED_GEN.icount_out[30]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(31),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_5\,
O => \INFERRED_GEN.icount_out[31]_i_2__0_n_0\
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE020000"
)
port map (
I0 => \^counter_tc\(0),
I1 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I2 => counter_En(0),
I3 => \icount_out0_carry__6_n_4\,
I4 => s_axi_aresetn,
I5 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(3),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_5,
O => \INFERRED_GEN.icount_out[3]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(4),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_4,
O => \INFERRED_GEN.icount_out[4]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_7\,
O => \INFERRED_GEN.icount_out[5]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_6\,
O => \INFERRED_GEN.icount_out[6]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_5\,
O => \INFERRED_GEN.icount_out[7]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_4\,
O => \INFERRED_GEN.icount_out[8]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_7\,
O => \INFERRED_GEN.icount_out[9]_i_1__0_n_0\
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[0]_i_1__0_n_0\,
Q => \^read_mux_in\(0),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[10]_i_1__0_n_0\,
Q => \^read_mux_in\(10),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[11]_i_1__0_n_0\,
Q => \^read_mux_in\(11),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[12]_i_1__0_n_0\,
Q => \^read_mux_in\(12),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[13]_i_1__0_n_0\,
Q => \^read_mux_in\(13),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[14]_i_1__0_n_0\,
Q => \^read_mux_in\(14),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[15]_i_1__0_n_0\,
Q => \^read_mux_in\(15),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[16]_i_1__0_n_0\,
Q => \^read_mux_in\(16),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[17]_i_1__0_n_0\,
Q => \^read_mux_in\(17),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[18]_i_1__0_n_0\,
Q => \^read_mux_in\(18),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[19]_i_1__0_n_0\,
Q => \^read_mux_in\(19),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[1]_i_1__0_n_0\,
Q => \^read_mux_in\(1),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[20]_i_1__0_n_0\,
Q => \^read_mux_in\(20),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[21]_i_1__0_n_0\,
Q => \^read_mux_in\(21),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[22]_i_1__0_n_0\,
Q => \^read_mux_in\(22),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[23]_i_1__0_n_0\,
Q => \^read_mux_in\(23),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[24]_i_1__0_n_0\,
Q => \^read_mux_in\(24),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[25]_i_1__0_n_0\,
Q => \^read_mux_in\(25),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[26]_i_1__0_n_0\,
Q => \^read_mux_in\(26),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[27]_i_1__0_n_0\,
Q => \^read_mux_in\(27),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[28]_i_1__0_n_0\,
Q => \^read_mux_in\(28),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[29]_i_1__0_n_0\,
Q => \^read_mux_in\(29),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[2]_i_1__0_n_0\,
Q => \^read_mux_in\(2),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[30]_i_1__0_n_0\,
Q => \^read_mux_in\(30),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[31]_i_2__0_n_0\,
Q => \^read_mux_in\(31),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[3]_i_1__0_n_0\,
Q => \^read_mux_in\(3),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[4]_i_1__0_n_0\,
Q => \^read_mux_in\(4),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[5]_i_1__0_n_0\,
Q => \^read_mux_in\(5),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[6]_i_1__0_n_0\,
Q => \^read_mux_in\(6),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[7]_i_1__0_n_0\,
Q => \^read_mux_in\(7),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[8]_i_1__0_n_0\,
Q => \^read_mux_in\(8),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[9]_i_1__0_n_0\,
Q => \^read_mux_in\(9),
R => \^sr\(0)
);
generateOutPre1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => Q(0),
O => generateOutPre10
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^read_mux_in\(0),
DI(3 downto 1) => \^read_mux_in\(3 downto 1),
DI(0) => icount_out0_carry_i_1_n_0,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => icount_out0_carry_i_2_n_0,
S(2) => icount_out0_carry_i_3_n_0,
S(1) => icount_out0_carry_i_4_n_0,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1_n_0\,
S(2) => \icount_out0_carry__0_i_2_n_0\,
S(1) => \icount_out0_carry__0_i_3_n_0\,
S(0) => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(7),
I1 => \^read_mux_in\(8),
O => \icount_out0_carry__0_i_1_n_0\
);
\icount_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(6),
I1 => \^read_mux_in\(7),
O => \icount_out0_carry__0_i_2_n_0\
);
\icount_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(5),
I1 => \^read_mux_in\(6),
O => \icount_out0_carry__0_i_3_n_0\
);
\icount_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(4),
I1 => \^read_mux_in\(5),
O => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1_n_0\,
S(2) => \icount_out0_carry__1_i_2_n_0\,
S(1) => \icount_out0_carry__1_i_3_n_0\,
S(0) => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(11),
I1 => \^read_mux_in\(12),
O => \icount_out0_carry__1_i_1_n_0\
);
\icount_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(10),
I1 => \^read_mux_in\(11),
O => \icount_out0_carry__1_i_2_n_0\
);
\icount_out0_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(9),
I1 => \^read_mux_in\(10),
O => \icount_out0_carry__1_i_3_n_0\
);
\icount_out0_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(8),
I1 => \^read_mux_in\(9),
O => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1_n_0\,
S(2) => \icount_out0_carry__2_i_2_n_0\,
S(1) => \icount_out0_carry__2_i_3_n_0\,
S(0) => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(15),
I1 => \^read_mux_in\(16),
O => \icount_out0_carry__2_i_1_n_0\
);
\icount_out0_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(14),
I1 => \^read_mux_in\(15),
O => \icount_out0_carry__2_i_2_n_0\
);
\icount_out0_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(13),
I1 => \^read_mux_in\(14),
O => \icount_out0_carry__2_i_3_n_0\
);
\icount_out0_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(12),
I1 => \^read_mux_in\(13),
O => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1_n_0\,
S(2) => \icount_out0_carry__3_i_2_n_0\,
S(1) => \icount_out0_carry__3_i_3_n_0\,
S(0) => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(19),
I1 => \^read_mux_in\(20),
O => \icount_out0_carry__3_i_1_n_0\
);
\icount_out0_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(18),
I1 => \^read_mux_in\(19),
O => \icount_out0_carry__3_i_2_n_0\
);
\icount_out0_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(17),
I1 => \^read_mux_in\(18),
O => \icount_out0_carry__3_i_3_n_0\
);
\icount_out0_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(16),
I1 => \^read_mux_in\(17),
O => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1_n_0\,
S(2) => \icount_out0_carry__4_i_2_n_0\,
S(1) => \icount_out0_carry__4_i_3_n_0\,
S(0) => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(23),
I1 => \^read_mux_in\(24),
O => \icount_out0_carry__4_i_1_n_0\
);
\icount_out0_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(22),
I1 => \^read_mux_in\(23),
O => \icount_out0_carry__4_i_2_n_0\
);
\icount_out0_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(21),
I1 => \^read_mux_in\(22),
O => \icount_out0_carry__4_i_3_n_0\
);
\icount_out0_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(20),
I1 => \^read_mux_in\(21),
O => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1_n_0\,
S(2) => \icount_out0_carry__5_i_2_n_0\,
S(1) => \icount_out0_carry__5_i_3_n_0\,
S(0) => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(27),
I1 => \^read_mux_in\(28),
O => \icount_out0_carry__5_i_1_n_0\
);
\icount_out0_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(26),
I1 => \^read_mux_in\(27),
O => \icount_out0_carry__5_i_2_n_0\
);
\icount_out0_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(25),
I1 => \^read_mux_in\(26),
O => \icount_out0_carry__5_i_3_n_0\
);
\icount_out0_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(24),
I1 => \^read_mux_in\(25),
O => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^read_mux_in\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1_n_0\,
S(2) => \icount_out0_carry__6_i_2_n_0\,
S(1) => \icount_out0_carry__6_i_3_n_0\,
S(0) => \icount_out0_carry__6_i_4_n_0\
);
\icount_out0_carry__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^read_mux_in\(31),
O => \icount_out0_carry__6_i_1_n_0\
);
\icount_out0_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(30),
I1 => \^read_mux_in\(31),
O => \icount_out0_carry__6_i_2_n_0\
);
\icount_out0_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(29),
I1 => \^read_mux_in\(30),
O => \icount_out0_carry__6_i_3_n_0\
);
\icount_out0_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(28),
I1 => \^read_mux_in\(29),
O => \icount_out0_carry__6_i_4_n_0\
);
icount_out0_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^read_mux_in\(1),
O => icount_out0_carry_i_1_n_0
);
icount_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(3),
I1 => \^read_mux_in\(4),
O => icount_out0_carry_i_2_n_0
);
icount_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(2),
I1 => \^read_mux_in\(3),
O => icount_out0_carry_i_3_n_0
);
icount_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(1),
I1 => \^read_mux_in\(2),
O => icount_out0_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_counter_f_3 is
port (
read_Mux_In : out STD_LOGIC_VECTOR ( 31 downto 0 );
generateOutPre00 : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[0].LOAD_REG_I\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_counter_f_3 : entity is "counter_f";
end system_axi_timer_0_0_counter_f_3;
architecture STRUCTURE of system_axi_timer_0_0_counter_f_3 is
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal \icount_out0_carry_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_4__0_n_0\ : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1\ : label is "soft_lutpair24";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
counter_TC(0) <= \^counter_tc\(0);
read_Mux_In(31 downto 0) <= \^read_mux_in\(31 downto 0);
\INFERRED_GEN.icount_out[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(0),
I1 => load_Counter_Reg(0),
I2 => \^read_mux_in\(0),
O => p_1_in(0)
);
\INFERRED_GEN.icount_out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_6\,
O => p_1_in(10)
);
\INFERRED_GEN.icount_out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(11),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_5\,
O => p_1_in(11)
);
\INFERRED_GEN.icount_out[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(12),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_4\,
O => p_1_in(12)
);
\INFERRED_GEN.icount_out[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(13),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_7\,
O => p_1_in(13)
);
\INFERRED_GEN.icount_out[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(14),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_6\,
O => p_1_in(14)
);
\INFERRED_GEN.icount_out[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(15),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_5\,
O => p_1_in(15)
);
\INFERRED_GEN.icount_out[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(16),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_4\,
O => p_1_in(16)
);
\INFERRED_GEN.icount_out[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(17),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_7\,
O => p_1_in(17)
);
\INFERRED_GEN.icount_out[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(18),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_6\,
O => p_1_in(18)
);
\INFERRED_GEN.icount_out[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(19),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_5\,
O => p_1_in(19)
);
\INFERRED_GEN.icount_out[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(1),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_7,
O => p_1_in(1)
);
\INFERRED_GEN.icount_out[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(20),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_4\,
O => p_1_in(20)
);
\INFERRED_GEN.icount_out[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(21),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_7\,
O => p_1_in(21)
);
\INFERRED_GEN.icount_out[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(22),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_6\,
O => p_1_in(22)
);
\INFERRED_GEN.icount_out[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(23),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_5\,
O => p_1_in(23)
);
\INFERRED_GEN.icount_out[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(24),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_4\,
O => p_1_in(24)
);
\INFERRED_GEN.icount_out[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(25),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_7\,
O => p_1_in(25)
);
\INFERRED_GEN.icount_out[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(26),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_6\,
O => p_1_in(26)
);
\INFERRED_GEN.icount_out[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(27),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_5\,
O => p_1_in(27)
);
\INFERRED_GEN.icount_out[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(28),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_4\,
O => p_1_in(28)
);
\INFERRED_GEN.icount_out[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(29),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_7\,
O => p_1_in(29)
);
\INFERRED_GEN.icount_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(2),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_6,
O => p_1_in(2)
);
\INFERRED_GEN.icount_out[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(30),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_6\,
O => p_1_in(30)
);
\INFERRED_GEN.icount_out[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(31),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_5\,
O => p_1_in(31)
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(3),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_5,
O => p_1_in(3)
);
\INFERRED_GEN.icount_out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(4),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_4,
O => p_1_in(4)
);
\INFERRED_GEN.icount_out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_7\,
O => p_1_in(5)
);
\INFERRED_GEN.icount_out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_6\,
O => p_1_in(6)
);
\INFERRED_GEN.icount_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_5\,
O => p_1_in(7)
);
\INFERRED_GEN.icount_out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_4\,
O => p_1_in(8)
);
\INFERRED_GEN.icount_out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I\(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_7\,
O => p_1_in(9)
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(0),
Q => \^read_mux_in\(0),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(10),
Q => \^read_mux_in\(10),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(11),
Q => \^read_mux_in\(11),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(12),
Q => \^read_mux_in\(12),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(13),
Q => \^read_mux_in\(13),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(14),
Q => \^read_mux_in\(14),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(15),
Q => \^read_mux_in\(15),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(16),
Q => \^read_mux_in\(16),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(17),
Q => \^read_mux_in\(17),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(18),
Q => \^read_mux_in\(18),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(19),
Q => \^read_mux_in\(19),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(1),
Q => \^read_mux_in\(1),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(20),
Q => \^read_mux_in\(20),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(21),
Q => \^read_mux_in\(21),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(22),
Q => \^read_mux_in\(22),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(23),
Q => \^read_mux_in\(23),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(24),
Q => \^read_mux_in\(24),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(25),
Q => \^read_mux_in\(25),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(26),
Q => \^read_mux_in\(26),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(27),
Q => \^read_mux_in\(27),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(28),
Q => \^read_mux_in\(28),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(29),
Q => \^read_mux_in\(29),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(2),
Q => \^read_mux_in\(2),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(30),
Q => \^read_mux_in\(30),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(31),
Q => \^read_mux_in\(31),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(3),
Q => \^read_mux_in\(3),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(4),
Q => \^read_mux_in\(4),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(5),
Q => \^read_mux_in\(5),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(6),
Q => \^read_mux_in\(6),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(7),
Q => \^read_mux_in\(7),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(8),
Q => \^read_mux_in\(8),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(9),
Q => \^read_mux_in\(9),
R => s_axi_aresetn_0
);
generateOutPre0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => Q(0),
O => generateOutPre00
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^read_mux_in\(0),
DI(3 downto 1) => \^read_mux_in\(3 downto 1),
DI(0) => \icount_out0_carry_i_1__0_n_0\,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => \icount_out0_carry_i_2__0_n_0\,
S(2) => \icount_out0_carry_i_3__0_n_0\,
S(1) => \icount_out0_carry_i_4__0_n_0\,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1__0_n_0\,
S(2) => \icount_out0_carry__0_i_2__0_n_0\,
S(1) => \icount_out0_carry__0_i_3__0_n_0\,
S(0) => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(7),
I1 => \^read_mux_in\(8),
O => \icount_out0_carry__0_i_1__0_n_0\
);
\icount_out0_carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(6),
I1 => \^read_mux_in\(7),
O => \icount_out0_carry__0_i_2__0_n_0\
);
\icount_out0_carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(5),
I1 => \^read_mux_in\(6),
O => \icount_out0_carry__0_i_3__0_n_0\
);
\icount_out0_carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(4),
I1 => \^read_mux_in\(5),
O => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1__0_n_0\,
S(2) => \icount_out0_carry__1_i_2__0_n_0\,
S(1) => \icount_out0_carry__1_i_3__0_n_0\,
S(0) => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(11),
I1 => \^read_mux_in\(12),
O => \icount_out0_carry__1_i_1__0_n_0\
);
\icount_out0_carry__1_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(10),
I1 => \^read_mux_in\(11),
O => \icount_out0_carry__1_i_2__0_n_0\
);
\icount_out0_carry__1_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(9),
I1 => \^read_mux_in\(10),
O => \icount_out0_carry__1_i_3__0_n_0\
);
\icount_out0_carry__1_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(8),
I1 => \^read_mux_in\(9),
O => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1__0_n_0\,
S(2) => \icount_out0_carry__2_i_2__0_n_0\,
S(1) => \icount_out0_carry__2_i_3__0_n_0\,
S(0) => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__2_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(15),
I1 => \^read_mux_in\(16),
O => \icount_out0_carry__2_i_1__0_n_0\
);
\icount_out0_carry__2_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(14),
I1 => \^read_mux_in\(15),
O => \icount_out0_carry__2_i_2__0_n_0\
);
\icount_out0_carry__2_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(13),
I1 => \^read_mux_in\(14),
O => \icount_out0_carry__2_i_3__0_n_0\
);
\icount_out0_carry__2_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(12),
I1 => \^read_mux_in\(13),
O => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1__0_n_0\,
S(2) => \icount_out0_carry__3_i_2__0_n_0\,
S(1) => \icount_out0_carry__3_i_3__0_n_0\,
S(0) => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__3_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(19),
I1 => \^read_mux_in\(20),
O => \icount_out0_carry__3_i_1__0_n_0\
);
\icount_out0_carry__3_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(18),
I1 => \^read_mux_in\(19),
O => \icount_out0_carry__3_i_2__0_n_0\
);
\icount_out0_carry__3_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(17),
I1 => \^read_mux_in\(18),
O => \icount_out0_carry__3_i_3__0_n_0\
);
\icount_out0_carry__3_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(16),
I1 => \^read_mux_in\(17),
O => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1__0_n_0\,
S(2) => \icount_out0_carry__4_i_2__0_n_0\,
S(1) => \icount_out0_carry__4_i_3__0_n_0\,
S(0) => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__4_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(23),
I1 => \^read_mux_in\(24),
O => \icount_out0_carry__4_i_1__0_n_0\
);
\icount_out0_carry__4_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(22),
I1 => \^read_mux_in\(23),
O => \icount_out0_carry__4_i_2__0_n_0\
);
\icount_out0_carry__4_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(21),
I1 => \^read_mux_in\(22),
O => \icount_out0_carry__4_i_3__0_n_0\
);
\icount_out0_carry__4_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(20),
I1 => \^read_mux_in\(21),
O => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^read_mux_in\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1__0_n_0\,
S(2) => \icount_out0_carry__5_i_2__0_n_0\,
S(1) => \icount_out0_carry__5_i_3__0_n_0\,
S(0) => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__5_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(27),
I1 => \^read_mux_in\(28),
O => \icount_out0_carry__5_i_1__0_n_0\
);
\icount_out0_carry__5_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(26),
I1 => \^read_mux_in\(27),
O => \icount_out0_carry__5_i_2__0_n_0\
);
\icount_out0_carry__5_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(25),
I1 => \^read_mux_in\(26),
O => \icount_out0_carry__5_i_3__0_n_0\
);
\icount_out0_carry__5_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(24),
I1 => \^read_mux_in\(25),
O => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^read_mux_in\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1__0_n_0\,
S(2) => \icount_out0_carry__6_i_2__0_n_0\,
S(1) => \icount_out0_carry__6_i_3__0_n_0\,
S(0) => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry__6_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^read_mux_in\(31),
O => \icount_out0_carry__6_i_1__0_n_0\
);
\icount_out0_carry__6_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(30),
I1 => \^read_mux_in\(31),
O => \icount_out0_carry__6_i_2__0_n_0\
);
\icount_out0_carry__6_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(29),
I1 => \^read_mux_in\(30),
O => \icount_out0_carry__6_i_3__0_n_0\
);
\icount_out0_carry__6_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(28),
I1 => \^read_mux_in\(29),
O => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^read_mux_in\(1),
O => \icount_out0_carry_i_1__0_n_0\
);
\icount_out0_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(3),
I1 => \^read_mux_in\(4),
O => \icount_out0_carry_i_2__0_n_0\
);
\icount_out0_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(2),
I1 => \^read_mux_in\(3),
O => \icount_out0_carry_i_3__0_n_0\
);
\icount_out0_carry_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^read_mux_in\(1),
I1 => \^read_mux_in\(2),
O => \icount_out0_carry_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_mux_onehot_f is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
Bus_RNW_reg_reg : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]\ : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\TCSR1_GENERATE[21].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\TCSR1_GENERATE[22].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\TCSR1_GENERATE[25].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\TCSR1_GENERATE[26].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\TCSR1_GENERATE[27].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\TCSR1_GENERATE[28].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\TCSR1_GENERATE[29].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\TCSR1_GENERATE[30].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\TCSR1_GENERATE[31].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_mux_onehot_f : entity is "mux_onehot_f";
end system_axi_timer_0_0_mux_onehot_f;
architecture STRUCTURE of system_axi_timer_0_0_mux_onehot_f is
signal \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal cyout_1 : STD_LOGIC;
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
begin
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(31),
CO(0) => cyout_1,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[31]\,
S(0) => Bus_RNW_reg_reg
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(21),
CO(0) => \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[21]\,
S(0) => Bus_RNW_reg_reg_9
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(20),
CO(0) => \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[20]\,
S(0) => Bus_RNW_reg_reg_10
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(19),
CO(0) => \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[19]\,
S(0) => Bus_RNW_reg_reg_11
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(18),
CO(0) => \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[18]\,
S(0) => Bus_RNW_reg_reg_12
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(17),
CO(0) => \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[17]\,
S(0) => Bus_RNW_reg_reg_13
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(16),
CO(0) => \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[16]\,
S(0) => Bus_RNW_reg_reg_14
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(15),
CO(0) => \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[15]\,
S(0) => Bus_RNW_reg_reg_15
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(14),
CO(0) => \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[14]\,
S(0) => Bus_RNW_reg_reg_16
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(13),
CO(0) => \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[13]\,
S(0) => Bus_RNW_reg_reg_17
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(12),
CO(0) => \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[12]\,
S(0) => Bus_RNW_reg_reg_18
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(30),
CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[30]\,
S(0) => Bus_RNW_reg_reg_0
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(11),
CO(0) => \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[11]\,
S(0) => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(10),
CO(0) => \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[10]\,
S(0) => \TCSR1_GENERATE[21].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(9),
CO(0) => \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[9]\,
S(0) => \TCSR1_GENERATE[22].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(8),
CO(0) => \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[8]\,
S(0) => \TCSR1_GENERATE[23].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(7),
CO(0) => \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[7]\,
S(0) => \TCSR1_GENERATE[24].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(6),
CO(0) => \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[6]\,
S(0) => \TCSR1_GENERATE[25].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(5),
CO(0) => \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[5]\,
S(0) => \TCSR1_GENERATE[26].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(4),
CO(0) => \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[4]\,
S(0) => \TCSR1_GENERATE[27].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(3),
CO(0) => \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[3]\,
S(0) => \TCSR1_GENERATE[28].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(2),
CO(0) => \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[2]\,
S(0) => \TCSR1_GENERATE[29].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(29),
CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[29]\,
S(0) => Bus_RNW_reg_reg_1
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(1),
CO(0) => \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[1]\,
S(0) => \TCSR1_GENERATE[30].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(0),
CO(0) => \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[0]\,
S(0) => \TCSR1_GENERATE[31].TCSR1_FF_I\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(28),
CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[28]\,
S(0) => Bus_RNW_reg_reg_2
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(27),
CO(0) => \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[27]\,
S(0) => Bus_RNW_reg_reg_3
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(26),
CO(0) => \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[26]\,
S(0) => Bus_RNW_reg_reg_4
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(25),
CO(0) => \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[25]\,
S(0) => Bus_RNW_reg_reg_5
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(24),
CO(0) => \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[24]\,
S(0) => Bus_RNW_reg_reg_6
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(23),
CO(0) => \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[23]\,
S(0) => Bus_RNW_reg_reg_7
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(22),
CO(0) => \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[22]\,
S(0) => Bus_RNW_reg_reg_8
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_pselect_f is
port (
ce_expnd_i_7 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_pselect_f : entity is "pselect_f";
end system_axi_timer_0_0_pselect_f;
architecture STRUCTURE of system_axi_timer_0_0_pselect_f is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_7
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_timer_0_0_pselect_f__parameterized1\ is
port (
ce_expnd_i_5 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_timer_0_0_pselect_f__parameterized1\ : entity is "pselect_f";
end \system_axi_timer_0_0_pselect_f__parameterized1\;
architecture STRUCTURE of \system_axi_timer_0_0_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_5
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_timer_0_0_pselect_f__parameterized3\ is
port (
ce_expnd_i_3 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_timer_0_0_pselect_f__parameterized3\ : entity is "pselect_f";
end \system_axi_timer_0_0_pselect_f__parameterized3\;
architecture STRUCTURE of \system_axi_timer_0_0_pselect_f__parameterized3\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_timer_0_0_pselect_f__parameterized4\ is
port (
ce_expnd_i_2 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_timer_0_0_pselect_f__parameterized4\ : entity is "pselect_f";
end \system_axi_timer_0_0_pselect_f__parameterized4\;
architecture STRUCTURE of \system_axi_timer_0_0_pselect_f__parameterized4\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_timer_0_0_pselect_f__parameterized5\ is
port (
ce_expnd_i_1 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_timer_0_0_pselect_f__parameterized5\ : entity is "pselect_f";
end \system_axi_timer_0_0_pselect_f__parameterized5\;
architecture STRUCTURE of \system_axi_timer_0_0_pselect_f__parameterized5\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(0),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_timer_0_0_pselect_f__parameterized6\ is
port (
ce_expnd_i_0 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_timer_0_0_pselect_f__parameterized6\ : entity is "pselect_f";
end \system_axi_timer_0_0_pselect_f__parameterized6\;
architecture STRUCTURE of \system_axi_timer_0_0_pselect_f__parameterized6\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_address_decoder is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_2\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 150 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\state1__2\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid_0 : in STD_LOGIC;
is_read : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_rvalid_i_reg_0 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
bus2ip_rnw_i : in STD_LOGIC;
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_address_decoder : entity is "address_decoder";
end system_axi_timer_0_0_address_decoder;
architecture STRUCTURE of system_axi_timer_0_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\ : STD_LOGIC;
signal \^load_reg_gen[31].load_reg_i\ : STD_LOGIC;
signal \^load_reg_gen[31].load_reg_i_0\ : STD_LOGIC;
signal \^tcsr1_generate[24].tcsr1_ff_i\ : STD_LOGIC;
signal bus2ip_rdce : STD_LOGIC_VECTOR ( 0 to 6 );
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_5 : STD_LOGIC;
signal ce_expnd_i_6 : STD_LOGIC;
signal ce_expnd_i_7 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \eqOp__4\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_axi_arready_INST_0_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[31].LOAD_REG_I_i_1__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[7].LOAD_REG_I_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of READ_DONE0_I_i_2 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of READ_DONE1_I_i_2 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\ : label is "soft_lutpair0";
begin
\LOAD_REG_GEN[31].LOAD_REG_I\ <= \^load_reg_gen[31].load_reg_i\;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ <= \^load_reg_gen[31].load_reg_i_0\;
\TCSR1_GENERATE[24].TCSR1_FF_I\ <= \^tcsr1_generate[24].tcsr1_ff_i\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i,
I1 => Q,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^tcsr1_generate[24].tcsr1_ff_i\,
R => '0'
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(127),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(63),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(31),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(95),
O => \s_axi_rdata_i_reg[31]_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => bus2ip_rdce(2)
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => bus2ip_rdce(6)
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => bus2ip_rdce(5)
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(117),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(53),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(21),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(85),
O => \s_axi_rdata_i_reg[21]_0\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(116),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(52),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(20),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(84),
O => \s_axi_rdata_i_reg[20]_0\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(115),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(51),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(19),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(83),
O => \s_axi_rdata_i_reg[19]_0\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(114),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(50),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(18),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(82),
O => \s_axi_rdata_i_reg[18]_0\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(113),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(49),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(17),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(81),
O => \s_axi_rdata_i_reg[17]_0\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(112),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(48),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(16),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(80),
O => \s_axi_rdata_i_reg[16]_0\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(111),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(47),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(15),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(79),
O => \s_axi_rdata_i_reg[15]_0\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(110),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(46),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(14),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(78),
O => \s_axi_rdata_i_reg[14]_0\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(109),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(45),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(13),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(77),
O => \s_axi_rdata_i_reg[13]_0\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(108),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(44),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(12),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(76),
O => \s_axi_rdata_i_reg[12]_0\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(126),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(62),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(30),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(94),
O => \s_axi_rdata_i_reg[30]_0\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F7F7F7F"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => read_Mux_In(150),
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => \^load_reg_gen[31].load_reg_i_0\,
I4 => read_Mux_In(107),
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(43),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(11),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(75),
O => \s_axi_rdata_i_reg[11]_0\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(138),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(106),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(149),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => bus2ip_rdce(4)
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i_0\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => bus2ip_rdce(1)
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => bus2ip_rdce(0)
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(42),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(10),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(74),
O => \s_axi_rdata_i_reg[10]_0\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(137),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(105),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(148),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(41),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(9),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(73),
O => \s_axi_rdata_i_reg[9]_0\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(136),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(104),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(147),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(40),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(8),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(72),
O => \s_axi_rdata_i_reg[8]_0\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(135),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(103),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(146),
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(39),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(7),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(71),
O => \s_axi_rdata_i_reg[7]_0\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(134),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(102),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(145),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(38),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(6),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(70),
O => \s_axi_rdata_i_reg[6]_0\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(133),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(101),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(144),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(37),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(5),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(69),
O => \s_axi_rdata_i_reg[5]_0\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(132),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(100),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(143),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(36),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(4),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(68),
O => \s_axi_rdata_i_reg[4]_0\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(131),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(99),
I4 => read_Mux_In(142),
I5 => bus2ip_rdce(0),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(35),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(3),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(67),
O => \s_axi_rdata_i_reg[3]_0\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(130),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(98),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(141),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(34),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(2),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(66),
O => \s_axi_rdata_i_reg[2]_0\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(125),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(61),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(29),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(93),
O => \s_axi_rdata_i_reg[29]_0\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(129),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(97),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(140),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(33),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(1),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(65),
O => \s_axi_rdata_i_reg[1]_0\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(4),
I1 => read_Mux_In(128),
I2 => bus2ip_rdce(1),
I3 => read_Mux_In(96),
I4 => bus2ip_rdce(0),
I5 => read_Mux_In(139),
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(32),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(0),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(64),
O => \s_axi_rdata_i_reg[0]_0\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(124),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(60),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(28),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(92),
O => \s_axi_rdata_i_reg[28]_0\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(123),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(59),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(27),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(91),
O => \s_axi_rdata_i_reg[27]_0\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(122),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(58),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(26),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(90),
O => \s_axi_rdata_i_reg[26]_0\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(121),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(57),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(25),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(89),
O => \s_axi_rdata_i_reg[25]_0\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(120),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(56),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(24),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(88),
O => \s_axi_rdata_i_reg[24]_0\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(119),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(55),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(23),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(87),
O => \s_axi_rdata_i_reg[23]_0\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr1_generate[24].tcsr1_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => read_Mux_In(118),
O => \s_axi_rdata_i_reg[22]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => bus2ip_rdce(2),
I1 => read_Mux_In(54),
I2 => bus2ip_rdce(6),
I3 => read_Mux_In(22),
I4 => bus2ip_rdce(5),
I5 => read_Mux_In(86),
O => \s_axi_rdata_i_reg[22]_0\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_7,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_6
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_6,
Q => \^load_reg_gen[31].load_reg_i_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_5,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \^load_reg_gen[31].load_reg_i\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
R => cs_ce_clr
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(63),
O => D_0
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(31),
O => D_1
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(21),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(53),
O => \LOAD_REG_GEN[10].LOAD_REG_I\
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(21),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(21),
O => \LOAD_REG_GEN[10].LOAD_REG_I_0\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(20),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(52),
O => \LOAD_REG_GEN[11].LOAD_REG_I\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(20),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(20),
O => \LOAD_REG_GEN[11].LOAD_REG_I_0\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(19),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(51),
O => \LOAD_REG_GEN[12].LOAD_REG_I\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(19),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(19),
O => \LOAD_REG_GEN[12].LOAD_REG_I_0\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(18),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(50),
O => \LOAD_REG_GEN[13].LOAD_REG_I\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(18),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(18),
O => \LOAD_REG_GEN[13].LOAD_REG_I_0\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(17),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(49),
O => \LOAD_REG_GEN[14].LOAD_REG_I\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(17),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(17),
O => \LOAD_REG_GEN[14].LOAD_REG_I_0\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(16),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(48),
O => \LOAD_REG_GEN[15].LOAD_REG_I\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(16),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(16),
O => \LOAD_REG_GEN[15].LOAD_REG_I_0\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(15),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(47),
O => \LOAD_REG_GEN[16].LOAD_REG_I\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(15),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(15),
O => \LOAD_REG_GEN[16].LOAD_REG_I_0\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(14),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(46),
O => \LOAD_REG_GEN[17].LOAD_REG_I\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(14),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(14),
O => \LOAD_REG_GEN[17].LOAD_REG_I_0\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(13),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(45),
O => \LOAD_REG_GEN[18].LOAD_REG_I\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(13),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(13),
O => \LOAD_REG_GEN[18].LOAD_REG_I_0\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(12),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(44),
O => \LOAD_REG_GEN[19].LOAD_REG_I\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(12),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(12),
O => \LOAD_REG_GEN[19].LOAD_REG_I_0\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(30),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(62),
O => \LOAD_REG_GEN[1].LOAD_REG_I\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(30),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(30),
O => \LOAD_REG_GEN[1].LOAD_REG_I_0\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(11),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(43),
O => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(11),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(11),
O => \LOAD_REG_GEN[20].LOAD_REG_I_0\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(10),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(42),
O => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(10),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(10),
O => \LOAD_REG_GEN[21].LOAD_REG_I_0\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(41),
O => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(9),
O => \LOAD_REG_GEN[22].LOAD_REG_I_0\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(8),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(40),
O => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(8),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(8),
O => \LOAD_REG_GEN[23].LOAD_REG_I_0\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(39),
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(7),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(38),
O => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(6),
O => \LOAD_REG_GEN[25].LOAD_REG_I_0\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(37),
O => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(5),
O => \LOAD_REG_GEN[26].LOAD_REG_I_0\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(36),
O => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(4),
O => \LOAD_REG_GEN[27].LOAD_REG_I_0\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(35),
O => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(3),
O => \LOAD_REG_GEN[28].LOAD_REG_I_0\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(34),
O => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(2),
O => \LOAD_REG_GEN[29].LOAD_REG_I_0\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(29),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(61),
O => \LOAD_REG_GEN[2].LOAD_REG_I\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(29),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(29),
O => \LOAD_REG_GEN[2].LOAD_REG_I_0\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(33),
O => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(1),
O => \LOAD_REG_GEN[30].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(32),
O => \LOAD_REG_GEN[31].LOAD_REG_I_1\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(0),
O => \LOAD_REG_GEN[31].LOAD_REG_I_2\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(28),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(60),
O => \LOAD_REG_GEN[3].LOAD_REG_I\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(28),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(28),
O => \LOAD_REG_GEN[3].LOAD_REG_I_0\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(27),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(59),
O => \LOAD_REG_GEN[4].LOAD_REG_I\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(27),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(27),
O => \LOAD_REG_GEN[4].LOAD_REG_I_0\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(26),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(58),
O => \LOAD_REG_GEN[5].LOAD_REG_I\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(26),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(26),
O => \LOAD_REG_GEN[5].LOAD_REG_I_0\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(25),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(57),
O => \LOAD_REG_GEN[6].LOAD_REG_I\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(25),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(25),
O => \LOAD_REG_GEN[6].LOAD_REG_I_0\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(24),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(56),
O => \LOAD_REG_GEN[7].LOAD_REG_I\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(24),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(24),
O => \LOAD_REG_GEN[7].LOAD_REG_I_0\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(23),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(55),
O => \LOAD_REG_GEN[8].LOAD_REG_I\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(23),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(23),
O => \LOAD_REG_GEN[8].LOAD_REG_I_0\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(22),
I1 => \^load_reg_gen[31].load_reg_i_0\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(54),
O => \LOAD_REG_GEN[9].LOAD_REG_I\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(22),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr1_generate[24].tcsr1_ff_i\,
I3 => read_Mux_In(22),
O => \LOAD_REG_GEN[9].LOAD_REG_I_0\
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.system_axi_timer_0_0_pselect_f
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_7 => ce_expnd_i_7
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_timer_0_0_pselect_f__parameterized1\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_5 => ce_expnd_i_5
);
\MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_timer_0_0_pselect_f__parameterized3\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_3 => ce_expnd_i_3
);
\MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_timer_0_0_pselect_f__parameterized4\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_2 => ce_expnd_i_2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_timer_0_0_pselect_f__parameterized5\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_1 => ce_expnd_i_1
);
\MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_timer_0_0_pselect_f__parameterized6\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_0 => ce_expnd_i_0
);
READ_DONE0_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i_0\,
I1 => D_2,
O => READ_DONE0_I
);
READ_DONE1_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => read_done1,
O => READ_DONE1_I
);
\TCSR0_GENERATE[20].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => bus2ip_wrce(1)
);
\TCSR0_GENERATE[21].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
O => pair0_Select
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR0_GENERATE[23].TCSR0_FF_I\
);
\TCSR0_GENERATE[24].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEFAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(146),
I2 => s_axi_wdata(7),
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => \TCSR0_GENERATE[24].TCSR0_FF_I\
);
\TCSR1_GENERATE[22].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => bus2ip_wrce(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr1_generate[24].tcsr1_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR1_GENERATE[23].TCSR1_FF_I\
);
\TCSR1_GENERATE[24].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEFAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(135),
I2 => s_axi_wdata(7),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I4 => \^tcsr1_generate[24].tcsr1_ff_i\,
O => \TCSR1_GENERATE[24].TCSR1_FF_I_0\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEAEAFFEAEAEA"
)
port map (
I0 => s_axi_arready_INST_0_i_1_n_0,
I1 => \eqOp__4\,
I2 => is_read,
I3 => \^load_reg_gen[31].load_reg_i_0\,
I4 => \^tcsr1_generate[24].tcsr1_ff_i\,
I5 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
O => \^s_axi_arready\
);
s_axi_arready_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000FFFE0000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I4 => \^tcsr1_generate[24].tcsr1_ff_i\,
I5 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => s_axi_arready_INST_0_i_1_n_0
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => \state_reg[1]\(1),
I2 => \state_reg[1]\(0),
I3 => s_axi_bready,
I4 => s_axi_bvalid_i_reg_0,
O => s_axi_bvalid_i_reg
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => s_axi_rready,
I4 => s_axi_rvalid_i_reg_0,
O => s_axi_rvalid_i_reg
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEAFFFFEAEAFFEA"
)
port map (
I0 => s_axi_wready_INST_0_i_1_n_0,
I1 => \eqOp__4\,
I2 => is_write_reg,
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I4 => \^tcsr1_generate[24].tcsr1_ff_i\,
I5 => \^load_reg_gen[31].load_reg_i_0\,
O => \^s_axi_wready\
);
s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF0000FFFE"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I4 => \^tcsr1_generate[24].tcsr1_ff_i\,
I5 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_1_n_0
);
s_axi_wready_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5),
O => \eqOp__4\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"55FFE4E4"
)
port map (
I0 => \state_reg[1]\(1),
I1 => s_axi_arvalid,
I2 => \^s_axi_wready\,
I3 => \state1__2\,
I4 => \state_reg[1]\(0),
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3AFF3AF0"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state1__2\,
I2 => \state_reg[1]\(1),
I3 => \state_reg[1]\(0),
I4 => s_axi_arvalid_0,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_count_module is
port (
read_Mux_In : out STD_LOGIC_VECTOR ( 63 downto 0 );
generateOutPre00 : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
CE : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_count_module : entity is "count_module";
end system_axi_timer_0_0_count_module;
architecture STRUCTURE of system_axi_timer_0_0_count_module is
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 63 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
read_Mux_In(63 downto 0) <= \^read_mux_in\(63 downto 0);
COUNTER_I: entity work.system_axi_timer_0_0_counter_f_3
port map (
E(0) => E(0),
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) => \^read_mux_in\(63 downto 32),
Q(0) => Q(0),
S(0) => S(0),
counter_TC(0) => counter_TC(0),
generateOutPre00 => generateOutPre00,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(31 downto 0) => \^read_mux_in\(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => D_1,
Q => \^read_mux_in\(63),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
Q => \^read_mux_in\(53),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
Q => \^read_mux_in\(52),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
Q => \^read_mux_in\(51),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
Q => \^read_mux_in\(50),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
Q => \^read_mux_in\(49),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
Q => \^read_mux_in\(48),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
Q => \^read_mux_in\(47),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
Q => \^read_mux_in\(46),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
Q => \^read_mux_in\(45),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
Q => \^read_mux_in\(44),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^read_mux_in\(62),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
Q => \^read_mux_in\(43),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
Q => \^read_mux_in\(42),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
Q => \^read_mux_in\(41),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
Q => \^read_mux_in\(40),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
Q => \^read_mux_in\(39),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
Q => \^read_mux_in\(38),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
Q => \^read_mux_in\(37),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
Q => \^read_mux_in\(36),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
Q => \^read_mux_in\(35),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
Q => \^read_mux_in\(34),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
Q => \^read_mux_in\(61),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
Q => \^read_mux_in\(33),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
Q => \^read_mux_in\(32),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
Q => \^read_mux_in\(60),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
Q => \^read_mux_in\(59),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
Q => \^read_mux_in\(58),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
Q => \^read_mux_in\(57),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
Q => \^read_mux_in\(56),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
Q => \^read_mux_in\(55),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
Q => \^read_mux_in\(54),
R => s_axi_aresetn_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_count_module_0 is
port (
read_Mux_In : out STD_LOGIC_VECTOR ( 63 downto 0 );
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC;
generateOutPre10 : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
CE : in STD_LOGIC;
D_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_29\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
counter_En : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_count_module_0 : entity is "count_module";
end system_axi_timer_0_0_count_module_0;
architecture STRUCTURE of system_axi_timer_0_0_count_module_0 is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC;
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 63 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\ <= \^inferred_gen.icount_out_reg[31]\;
read_Mux_In(63 downto 0) <= \^read_mux_in\(63 downto 0);
COUNTER_I: entity work.system_axi_timer_0_0_counter_f
port map (
E(0) => E(0),
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) => \^read_mux_in\(63 downto 32),
Q(0) => Q(0),
S(0) => S(0),
SR(0) => \^inferred_gen.icount_out_reg[31]\,
\TCSR0_GENERATE[20].TCSR0_FF_I\ => \TCSR0_GENERATE[20].TCSR0_FF_I\,
counter_En(0) => counter_En(0),
counter_TC(0) => counter_TC(0),
generateOutPre10 => generateOutPre10,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(31 downto 0) => \^read_mux_in\(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => D_2,
Q => \^read_mux_in\(63),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_8\,
Q => \^read_mux_in\(53),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_9\,
Q => \^read_mux_in\(52),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_10\,
Q => \^read_mux_in\(51),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_11\,
Q => \^read_mux_in\(50),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_12\,
Q => \^read_mux_in\(49),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_13\,
Q => \^read_mux_in\(48),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_14\,
Q => \^read_mux_in\(47),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_15\,
Q => \^read_mux_in\(46),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_16\,
Q => \^read_mux_in\(45),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_17\,
Q => \^read_mux_in\(44),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
Q => \^read_mux_in\(62),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_18\,
Q => \^read_mux_in\(43),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_19\,
Q => \^read_mux_in\(42),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_20\,
Q => \^read_mux_in\(41),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_21\,
Q => \^read_mux_in\(40),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_22\,
Q => \^read_mux_in\(39),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_23\,
Q => \^read_mux_in\(38),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_24\,
Q => \^read_mux_in\(37),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_25\,
Q => \^read_mux_in\(36),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_26\,
Q => \^read_mux_in\(35),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_27\,
Q => \^read_mux_in\(34),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\,
Q => \^read_mux_in\(61),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_28\,
Q => \^read_mux_in\(33),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_29\,
Q => \^read_mux_in\(32),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_1\,
Q => \^read_mux_in\(60),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_2\,
Q => \^read_mux_in\(59),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_3\,
Q => \^read_mux_in\(58),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_4\,
Q => \^read_mux_in\(57),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_5\,
Q => \^read_mux_in\(56),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_6\,
Q => \^read_mux_in\(55),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_7\,
Q => \^read_mux_in\(54),
R => \^inferred_gen.icount_out_reg[31]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_timer_control is
port (
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC;
read_Mux_In : out STD_LOGIC_VECTOR ( 21 downto 0 );
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
CE : out STD_LOGIC;
CE_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : out STD_LOGIC_VECTOR ( 0 to 1 );
\INFERRED_GEN.icount_out_reg[32]\ : out STD_LOGIC;
counter_En : out STD_LOGIC_VECTOR ( 0 to 0 );
R : out STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
PWM_FF_I : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
generateOutPre10 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
generateOutPre00 : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
pwm0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_timer_control : entity is "timer_control";
end system_axi_timer_0_0_timer_control;
architecture STRUCTURE of system_axi_timer_0_0_timer_control is
signal Counter_En17_out : STD_LOGIC;
signal \^d_0\ : STD_LOGIC;
signal GenerateOut00 : STD_LOGIC;
signal GenerateOut10 : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_3__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_5__0_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_8_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[32]_i_3_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[32]_i_5_n_0\ : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC;
signal Interrupt0 : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_3__0_n_0\ : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_4_n_0\ : STD_LOGIC;
signal \Load_Counter_Reg0__3\ : STD_LOGIC;
signal \Load_Counter_Reg153_out__1\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal READ_DONE0_I_i_3_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_1_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_3_n_0 : STD_LOGIC;
signal R_0 : STD_LOGIC;
signal \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ : STD_LOGIC;
signal \TCSR0_GENERATE[23].TCSR0_FF_I_i_3_n_0\ : STD_LOGIC;
signal \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ : STD_LOGIC;
signal captureTrig0_d : STD_LOGIC;
signal captureTrig0_d0 : STD_LOGIC;
signal captureTrig0_d2 : STD_LOGIC;
signal captureTrig0_pulse_d1 : STD_LOGIC;
signal captureTrig0_pulse_d2 : STD_LOGIC;
signal captureTrig1_d : STD_LOGIC;
signal captureTrig1_d0 : STD_LOGIC;
signal captureTrig1_d2 : STD_LOGIC;
signal counter_TC_Reg2 : STD_LOGIC;
signal generateOutPre0 : STD_LOGIC;
signal generateOutPre1 : STD_LOGIC;
signal \^generateout0\ : STD_LOGIC;
signal \^generateout1\ : STD_LOGIC;
signal \^load_counter_reg\ : STD_LOGIC_VECTOR ( 0 to 1 );
signal p_30_in : STD_LOGIC;
signal p_46_in : STD_LOGIC;
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 21 downto 0 );
signal \^read_done1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of GenerateOut0_i_2 : label is "soft_lutpair46";
attribute SOFT_HLUTNM of GenerateOut1_i_1 : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_6\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_6__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[32]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[32]_i_5\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_3__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_4\ : label is "soft_lutpair49";
attribute BOX_TYPE : string;
attribute BOX_TYPE of READ_DONE0_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of READ_DONE0_I : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of READ_DONE0_I : label is "1'b0";
attribute BOX_TYPE of READ_DONE1_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED of READ_DONE1_I : label is "1'b0";
attribute IS_S_INVERTED of READ_DONE1_I : label is "1'b0";
attribute SOFT_HLUTNM of READ_DONE1_I_i_3 : label is "soft_lutpair48";
attribute BOX_TYPE of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[23].TCSR0_FF_I_i_3\ : label is "soft_lutpair51";
attribute BOX_TYPE of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute SOFT_HLUTNM of captureTrig0_pulse_d1_i_1 : label is "soft_lutpair48";
begin
D_0 <= \^d_0\;
\INFERRED_GEN.icount_out_reg[0]\ <= \^inferred_gen.icount_out_reg[0]\;
Q(1 downto 0) <= \^q\(1 downto 0);
generateout0 <= \^generateout0\;
generateout1 <= \^generateout1\;
load_Counter_Reg(0 to 1) <= \^load_counter_reg\(0 to 1);
read_Mux_In(21 downto 0) <= \^read_mux_in\(21 downto 0);
read_done1 <= \^read_done1\;
GenerateOut0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"E200"
)
port map (
I0 => generateOutPre0,
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => generateOutPre1,
I3 => \^read_mux_in\(13),
O => GenerateOut00
);
GenerateOut0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut00,
Q => \^generateout0\,
R => SR(0)
);
GenerateOut1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8F808080"
)
port map (
I0 => generateOutPre0,
I1 => \^read_mux_in\(13),
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => generateOutPre1,
I4 => \^read_mux_in\(2),
O => GenerateOut10
);
GenerateOut1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut10,
Q => \^generateout1\,
R => SR(0)
);
\INFERRED_GEN.icount_out[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCCCCCCAAAAAAAA"
)
port map (
I0 => \Load_Counter_Reg0__3\,
I1 => \^read_mux_in\(5),
I2 => \^read_mux_in\(11),
I3 => \^read_mux_in\(15),
I4 => counter_TC(1),
I5 => \^inferred_gen.icount_out_reg[0]\,
O => \^load_counter_reg\(1)
);
\INFERRED_GEN.icount_out[31]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF74FFFFFF77"
)
port map (
I0 => counter_TC(1),
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => \^read_mux_in\(20),
I3 => \^read_mux_in\(15),
I4 => \^read_mux_in\(11),
I5 => counter_TC(0),
O => \INFERRED_GEN.icount_out[31]_i_3__0_n_0\
);
\INFERRED_GEN.icount_out[31]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^read_mux_in\(11),
I1 => \^read_mux_in\(15),
I2 => counter_TC(1),
O => \Load_Counter_Reg153_out__1\
);
\INFERRED_GEN.icount_out[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEAAFAAAAA"
)
port map (
I0 => \^read_mux_in\(5),
I1 => counter_TC(0),
I2 => \^read_mux_in\(4),
I3 => \^read_mux_in\(0),
I4 => counter_TC(1),
I5 => \^read_mux_in\(9),
O => \Load_Counter_Reg0__3\
);
\INFERRED_GEN.icount_out[31]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000E00"
)
port map (
I0 => \^read_mux_in\(15),
I1 => \^read_mux_in\(20),
I2 => \^read_mux_in\(11),
I3 => counter_TC(0),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => \^read_mux_in\(16),
O => \INFERRED_GEN.icount_out[31]_i_5__0_n_0\
);
\INFERRED_GEN.icount_out[31]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAAAAA"
)
port map (
I0 => \INFERRED_GEN.icount_out[31]_i_5__0_n_0\,
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => \^read_mux_in\(11),
I3 => \^read_mux_in\(15),
I4 => counter_TC(1),
O => \^load_counter_reg\(0)
);
\INFERRED_GEN.icount_out[31]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => counter_TC(1),
I1 => \^read_mux_in\(11),
I2 => \^read_mux_in\(15),
O => Counter_En17_out
);
\INFERRED_GEN.icount_out[31]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => counter_TC(1),
I1 => \^read_mux_in\(0),
I2 => \^read_mux_in\(9),
I3 => \^read_mux_in\(4),
O => \INFERRED_GEN.icount_out[31]_i_8_n_0\
);
\INFERRED_GEN.icount_out[32]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^inferred_gen.icount_out_reg[0]\,
I1 => \^read_mux_in\(12),
O => \INFERRED_GEN.icount_out[32]_i_3_n_0\
);
\INFERRED_GEN.icount_out[32]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^read_mux_in\(1),
I1 => \^inferred_gen.icount_out_reg[0]\,
O => \INFERRED_GEN.icount_out[32]_i_5_n_0\
);
INPUT_DOUBLE_REGS: entity work.system_axi_timer_0_0_cdc_sync
port map (
captureTrig0_d0 => captureTrig0_d0,
capturetrig0 => capturetrig0,
read_Mux_In(0) => \^read_mux_in\(14),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS2: entity work.system_axi_timer_0_0_cdc_sync_1
port map (
captureTrig1_d0 => captureTrig1_d0,
capturetrig1 => capturetrig1,
read_Mux_In(0) => \^read_mux_in\(3),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS3: entity work.system_axi_timer_0_0_cdc_sync_2
port map (
Counter_En17_out => Counter_En17_out,
E(0) => E(0),
\INFERRED_GEN.icount_out_reg[0]\(0) => \INFERRED_GEN.icount_out_reg[0]_0\(0),
\INFERRED_GEN.icount_out_reg[1]\(1 downto 0) => \INFERRED_GEN.icount_out_reg[1]\(1 downto 0),
\INFERRED_GEN.icount_out_reg[32]\ => \INFERRED_GEN.icount_out_reg[32]\,
\INFERRED_GEN.icount_out_reg[32]_0\ => \INFERRED_GEN.icount_out[31]_i_3__0_n_0\,
\INFERRED_GEN.icount_out_reg[32]_1\ => \INFERRED_GEN.icount_out[31]_i_8_n_0\,
\INFERRED_GEN.icount_out_reg[4]\(0) => \INFERRED_GEN.icount_out_reg[4]\(0),
\Load_Counter_Reg153_out__1\ => \Load_Counter_Reg153_out__1\,
S(0) => S(0),
\TCSR0_GENERATE[20].TCSR0_FF_I\ => \^inferred_gen.icount_out_reg[0]\,
\TCSR0_GENERATE[20].TCSR0_FF_I_0\ => \INFERRED_GEN.icount_out[32]_i_3_n_0\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \^read_mux_in\(18),
\TCSR0_GENERATE[27].TCSR0_FF_I\ => \INFERRED_GEN.icount_out[31]_i_5__0_n_0\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \^read_mux_in\(7),
\TCSR1_GENERATE[30].TCSR1_FF_I\ => \INFERRED_GEN.icount_out[32]_i_5_n_0\,
counter_En(0) => counter_En(0),
freeze => freeze,
generateOutPre0 => generateOutPre0,
load_Counter_Reg(0) => \^load_counter_reg\(1),
read_Mux_In(1) => \^read_mux_in\(12),
read_Mux_In(0) => \^read_mux_in\(1),
s_axi_aclk => s_axi_aclk
);
Interrupt_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^read_mux_in\(6),
I1 => \^read_mux_in\(8),
I2 => \^read_mux_in\(17),
I3 => \^read_mux_in\(19),
O => Interrupt0
);
Interrupt_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Interrupt0,
Q => interrupt,
R => SR(0)
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2222F2222222"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \LOAD_REG_GEN[0].LOAD_REG_I_i_3__0_n_0\,
I3 => \^read_mux_in\(0),
I4 => READ_DONE1_I_i_1_n_0,
I5 => \LOAD_REG_GEN[0].LOAD_REG_I_i_4_n_0\,
O => CE
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF22222"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \^d_0\,
I3 => \^read_mux_in\(15),
I4 => p_30_in,
O => CE_0
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEE222A00000000"
)
port map (
I0 => p_46_in,
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => counter_TC(0),
I3 => \^q\(1),
I4 => READ_DONE0_I_i_3_n_0,
I5 => \^read_mux_in\(11),
O => p_30_in
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \^read_mux_in\(4),
I1 => \^read_done1\,
I2 => \^inferred_gen.icount_out_reg[0]\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_3__0_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => \^read_mux_in\(11),
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => \^read_mux_in\(15),
I3 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_4_n_0\
);
PWM_FF_I_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F1"
)
port map (
I0 => \^read_mux_in\(20),
I1 => \^read_mux_in\(9),
I2 => \^generateout1\,
O => R
);
PWM_FF_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^generateout0\,
I1 => pwm0,
O => PWM_FF_I
);
READ_DONE0_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^d_0\,
R => R_0
);
READ_DONE0_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AA00ABFFAA00"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => \^q\(1),
I2 => counter_TC(0),
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_d,
I5 => captureTrig0_d2,
O => R_0
);
READ_DONE0_I_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => captureTrig0_pulse_d1,
I1 => captureTrig0_pulse_d2,
I2 => counter_TC_Reg2,
O => READ_DONE0_I_i_3_n_0
);
READ_DONE1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
Q => \^read_done1\,
R => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"E0E0EFE0"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => READ_DONE1_I_i_3_n_0,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => captureTrig1_d,
I4 => captureTrig1_d2,
O => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => counter_TC(0),
I1 => \^q\(1),
I2 => captureTrig0_d2,
I3 => captureTrig0_d,
O => READ_DONE1_I_i_3_n_0
);
\TCSR0_GENERATE[20].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(9),
Q => \^inferred_gen.icount_out_reg[0]\,
R => SR(0)
);
\TCSR0_GENERATE[21].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => \^read_mux_in\(21),
R => SR(0)
);
\TCSR0_GENERATE[22].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(7),
Q => \^read_mux_in\(20),
R => SR(0)
);
\TCSR0_GENERATE[23].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\,
Q => \^read_mux_in\(19),
R => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF88F8"
)
port map (
I0 => p_30_in,
I1 => \^read_mux_in\(18),
I2 => \TCSR0_GENERATE[23].TCSR0_FF_I_i_3_n_0\,
I3 => \^read_mux_in\(11),
I4 => \^read_mux_in\(19),
O => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => generateOutPre1,
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => generateOutPre0,
O => \TCSR0_GENERATE[23].TCSR0_FF_I_i_3_n_0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR0_GENERATE[24].TCSR0_FF_I_0\,
Q => \^read_mux_in\(18),
R => SR(0)
);
\TCSR0_GENERATE[25].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(6),
Q => \^read_mux_in\(17),
R => SR(0)
);
\TCSR0_GENERATE[26].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(5),
Q => \^read_mux_in\(16),
R => SR(0)
);
\TCSR0_GENERATE[27].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(4),
Q => \^read_mux_in\(15),
R => SR(0)
);
\TCSR0_GENERATE[28].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(3),
Q => \^read_mux_in\(14),
R => SR(0)
);
\TCSR0_GENERATE[29].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(2),
Q => \^read_mux_in\(13),
R => SR(0)
);
\TCSR0_GENERATE[30].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(1),
Q => \^read_mux_in\(12),
R => SR(0)
);
\TCSR0_GENERATE[31].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(0),
Q => \^read_mux_in\(11),
R => SR(0)
);
\TCSR1_GENERATE[21].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => \^read_mux_in\(10),
R => SR(0)
);
\TCSR1_GENERATE[22].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(7),
Q => \^read_mux_in\(9),
R => SR(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\,
Q => \^read_mux_in\(8),
R => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF45054000"
)
port map (
I0 => \^inferred_gen.icount_out_reg[0]\,
I1 => \^read_mux_in\(7),
I2 => \^read_mux_in\(0),
I3 => READ_DONE1_I_i_1_n_0,
I4 => generateOutPre1,
I5 => \^read_mux_in\(8),
O => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\
);
\TCSR1_GENERATE[24].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR1_GENERATE[24].TCSR1_FF_I_0\,
Q => \^read_mux_in\(7),
R => SR(0)
);
\TCSR1_GENERATE[25].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(6),
Q => \^read_mux_in\(6),
R => SR(0)
);
\TCSR1_GENERATE[26].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(5),
Q => \^read_mux_in\(5),
R => SR(0)
);
\TCSR1_GENERATE[27].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(4),
Q => \^read_mux_in\(4),
R => SR(0)
);
\TCSR1_GENERATE[28].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(3),
Q => \^read_mux_in\(3),
R => SR(0)
);
\TCSR1_GENERATE[29].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(2),
Q => \^read_mux_in\(2),
R => SR(0)
);
\TCSR1_GENERATE[30].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(1),
Q => \^read_mux_in\(1),
R => SR(0)
);
\TCSR1_GENERATE[31].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(0),
Q => \^read_mux_in\(0),
R => SR(0)
);
captureTrig0_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d,
Q => captureTrig0_d2,
R => SR(0)
);
captureTrig0_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d0,
Q => captureTrig0_d,
R => SR(0)
);
captureTrig0_pulse_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => captureTrig0_d,
I1 => captureTrig0_d2,
O => p_46_in
);
captureTrig0_pulse_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_46_in,
Q => captureTrig0_pulse_d1,
R => SR(0)
);
captureTrig0_pulse_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1,
Q => captureTrig0_pulse_d2,
R => SR(0)
);
captureTrig1_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d,
Q => captureTrig1_d2,
R => SR(0)
);
captureTrig1_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d0,
Q => captureTrig1_d,
R => SR(0)
);
counter_TC_Reg2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(1),
Q => counter_TC_Reg2,
R => SR(0)
);
\counter_TC_Reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(0),
Q => \^q\(1),
R => SR(0)
);
\counter_TC_Reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(1),
Q => \^q\(0),
R => SR(0)
);
generateOutPre0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => generateOutPre00,
Q => generateOutPre0,
R => SR(0)
);
generateOutPre1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => generateOutPre10,
Q => generateOutPre1,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_slave_attachment is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\s_axi_rdata_i_reg[31]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_1\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_2\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 150 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_slave_attachment : entity is "slave_attachment";
end system_axi_timer_0_0_slave_attachment;
architecture STRUCTURE of system_axi_timer_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal I_DECODER_n_142 : STD_LOGIC;
signal I_DECODER_n_143 : STD_LOGIC;
signal I_DECODER_n_17 : STD_LOGIC;
signal I_DECODER_n_18 : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 2 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i : STD_LOGIC;
signal bus2ip_rnw_i_i_1_n_0 : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rst : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \bus2ip_addr_i[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair10";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
O => plusOp(4)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
O => plusOp(5)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(4),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(5),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1_n_0\
);
I_DECODER: entity work.system_axi_timer_0_0_address_decoder
port map (
D(1) => I_DECODER_n_17,
D(0) => I_DECODER_n_18,
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0),
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_1\,
\LOAD_REG_GEN[31].LOAD_REG_I_2\ => \LOAD_REG_GEN[31].LOAD_REG_I_2\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
Q => start2,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I_0\,
\bus2ip_addr_i_reg[4]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[4]\(1) => bus2ip_addr(1),
\bus2ip_addr_i_reg[4]\(0) => bus2ip_addr(2),
bus2ip_rnw_i => bus2ip_rnw_i,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
is_read => is_read,
is_write_reg => is_write_reg_n_0,
pair0_Select => pair0_Select,
read_Mux_In(150 downto 0) => read_Mux_In(150 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_arvalid_0 => \state[1]_i_3_n_0\,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg => I_DECODER_n_143,
s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]_1\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]_0\,
\s_axi_rdata_i_reg[10]_0\ => \s_axi_rdata_i_reg[10]_1\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]_0\,
\s_axi_rdata_i_reg[11]_0\ => \s_axi_rdata_i_reg[11]_1\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]_0\,
\s_axi_rdata_i_reg[12]_0\ => \s_axi_rdata_i_reg[12]_1\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]_0\,
\s_axi_rdata_i_reg[13]_0\ => \s_axi_rdata_i_reg[13]_1\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]_0\,
\s_axi_rdata_i_reg[14]_0\ => \s_axi_rdata_i_reg[14]_1\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]_0\,
\s_axi_rdata_i_reg[15]_0\ => \s_axi_rdata_i_reg[15]_1\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]_0\,
\s_axi_rdata_i_reg[16]_0\ => \s_axi_rdata_i_reg[16]_1\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]_0\,
\s_axi_rdata_i_reg[17]_0\ => \s_axi_rdata_i_reg[17]_1\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]_0\,
\s_axi_rdata_i_reg[18]_0\ => \s_axi_rdata_i_reg[18]_1\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]_0\,
\s_axi_rdata_i_reg[19]_0\ => \s_axi_rdata_i_reg[19]_1\,
\s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i_reg[1]_0\,
\s_axi_rdata_i_reg[1]_0\ => \s_axi_rdata_i_reg[1]_1\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]_0\,
\s_axi_rdata_i_reg[20]_0\ => \s_axi_rdata_i_reg[20]_1\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]_0\,
\s_axi_rdata_i_reg[21]_0\ => \s_axi_rdata_i_reg[21]_1\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]_0\,
\s_axi_rdata_i_reg[22]_0\ => \s_axi_rdata_i_reg[22]_1\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]_0\,
\s_axi_rdata_i_reg[23]_0\ => \s_axi_rdata_i_reg[23]_1\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]_0\,
\s_axi_rdata_i_reg[24]_0\ => \s_axi_rdata_i_reg[24]_1\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]_0\,
\s_axi_rdata_i_reg[25]_0\ => \s_axi_rdata_i_reg[25]_1\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]_0\,
\s_axi_rdata_i_reg[26]_0\ => \s_axi_rdata_i_reg[26]_1\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]_0\,
\s_axi_rdata_i_reg[27]_0\ => \s_axi_rdata_i_reg[27]_1\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]_0\,
\s_axi_rdata_i_reg[28]_0\ => \s_axi_rdata_i_reg[28]_1\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]_0\,
\s_axi_rdata_i_reg[29]_0\ => \s_axi_rdata_i_reg[29]_1\,
\s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i_reg[2]_0\,
\s_axi_rdata_i_reg[2]_0\ => \s_axi_rdata_i_reg[2]_1\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]_0\,
\s_axi_rdata_i_reg[30]_0\ => \s_axi_rdata_i_reg[30]_1\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]_0\,
\s_axi_rdata_i_reg[31]_0\ => \s_axi_rdata_i_reg[31]_1\,
\s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i_reg[3]_0\,
\s_axi_rdata_i_reg[3]_0\ => \s_axi_rdata_i_reg[3]_1\,
\s_axi_rdata_i_reg[4]\ => \s_axi_rdata_i_reg[4]_0\,
\s_axi_rdata_i_reg[4]_0\ => \s_axi_rdata_i_reg[4]_1\,
\s_axi_rdata_i_reg[5]\ => \s_axi_rdata_i_reg[5]_0\,
\s_axi_rdata_i_reg[5]_0\ => \s_axi_rdata_i_reg[5]_1\,
\s_axi_rdata_i_reg[6]\ => \s_axi_rdata_i_reg[6]_0\,
\s_axi_rdata_i_reg[6]_0\ => \s_axi_rdata_i_reg[6]_1\,
\s_axi_rdata_i_reg[7]\ => \s_axi_rdata_i_reg[7]_0\,
\s_axi_rdata_i_reg[7]_0\ => \s_axi_rdata_i_reg[7]_1\,
\s_axi_rdata_i_reg[8]\ => \s_axi_rdata_i_reg[8]_0\,
\s_axi_rdata_i_reg[8]_0\ => \s_axi_rdata_i_reg[8]_1\,
\s_axi_rdata_i_reg[9]\ => \s_axi_rdata_i_reg[9]_0\,
\s_axi_rdata_i_reg[9]_0\ => \s_axi_rdata_i_reg[9]_1\,
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg => I_DECODER_n_142,
s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
\state1__2\ => \state1__2\,
\state_reg[1]\(1 downto 0) => state(1 downto 0)
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020202"
)
port map (
I0 => s_axi_arvalid,
I1 => state(1),
I2 => state(0),
I3 => s_axi_awvalid,
I4 => s_axi_wvalid,
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(2),
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(1),
R => rst
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_2_n_0\,
Q => bus2ip_addr(0),
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i_i_1_n_0
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => bus2ip_rnw_i_i_1_n_0,
Q => bus2ip_rnw_i,
R => rst
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => rst
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset,
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_143,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(0),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(10),
Q => s_axi_rdata(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(11),
Q => s_axi_rdata(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(12),
Q => s_axi_rdata(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(13),
Q => s_axi_rdata(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(14),
Q => s_axi_rdata(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(15),
Q => s_axi_rdata(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(16),
Q => s_axi_rdata(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(17),
Q => s_axi_rdata(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(18),
Q => s_axi_rdata(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(19),
Q => s_axi_rdata(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(1),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(20),
Q => s_axi_rdata(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(21),
Q => s_axi_rdata(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(22),
Q => s_axi_rdata(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(23),
Q => s_axi_rdata(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(24),
Q => s_axi_rdata(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(25),
Q => s_axi_rdata(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(26),
Q => s_axi_rdata(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(27),
Q => s_axi_rdata(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(28),
Q => s_axi_rdata(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(29),
Q => s_axi_rdata(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(2),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(30),
Q => s_axi_rdata(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(31),
Q => s_axi_rdata(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(3),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(4),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(5),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(6),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(7),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(8),
Q => s_axi_rdata(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => D(9),
Q => s_axi_rdata(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_142,
Q => \^s_axi_rvalid\,
R => rst
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000F0008"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => state(1),
I3 => state(0),
I4 => s_axi_arvalid,
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_18,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_17,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_tc_core is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
read_Mux_In : out STD_LOGIC_VECTOR ( 150 downto 0 );
bus2ip_reset : out STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]\ : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\TCSR1_GENERATE[21].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\TCSR1_GENERATE[22].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\TCSR1_GENERATE[25].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\TCSR1_GENERATE[26].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\TCSR1_GENERATE[27].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\TCSR1_GENERATE[28].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\TCSR1_GENERATE[29].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\TCSR1_GENERATE[30].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\TCSR1_GENERATE[31].TCSR1_FF_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_29\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_30\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_tc_core : entity is "tc_core";
end system_axi_timer_0_0_tc_core;
architecture STRUCTURE of system_axi_timer_0_0_tc_core is
signal CE : STD_LOGIC;
signal CE_0 : STD_LOGIC;
signal R : STD_LOGIC;
signal TIMER_CONTROL_I_n_3 : STD_LOGIC;
signal TIMER_CONTROL_I_n_32 : STD_LOGIC;
signal TIMER_CONTROL_I_n_35 : STD_LOGIC;
signal TIMER_CONTROL_I_n_38 : STD_LOGIC;
signal TIMER_CONTROL_I_n_39 : STD_LOGIC;
signal TIMER_CONTROL_I_n_4 : STD_LOGIC;
signal TIMER_CONTROL_I_n_40 : STD_LOGIC;
signal TIMER_CONTROL_I_n_41 : STD_LOGIC;
signal \^bus2ip_reset\ : STD_LOGIC;
signal counter_En : STD_LOGIC_VECTOR ( 1 to 1 );
signal counter_TC : STD_LOGIC_VECTOR ( 0 to 1 );
signal generateOutPre00 : STD_LOGIC;
signal generateOutPre10 : STD_LOGIC;
signal load_Counter_Reg : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^pwm0\ : STD_LOGIC;
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 150 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of PWM_FF_I : label is "PRIMITIVE";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of PWM_FF_I : label is "1'b0";
begin
bus2ip_reset <= \^bus2ip_reset\;
pwm0 <= \^pwm0\;
read_Mux_In(150 downto 0) <= \^read_mux_in\(150 downto 0);
COUNTER_0_I: entity work.system_axi_timer_0_0_count_module
port map (
CE => CE,
D_1 => D_1,
E(0) => TIMER_CONTROL_I_n_32,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
Q(0) => TIMER_CONTROL_I_n_3,
S(0) => TIMER_CONTROL_I_n_41,
counter_TC(0) => counter_TC(0),
generateOutPre00 => generateOutPre00,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(63 downto 32) => \^read_mux_in\(127 downto 96),
read_Mux_In(31 downto 0) => \^read_mux_in\(63 downto 32),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^bus2ip_reset\
);
\GEN_SECOND_TIMER.COUNTER_1_I\: entity work.system_axi_timer_0_0_count_module_0
port map (
CE => CE_0,
D_2 => D_2,
E(0) => TIMER_CONTROL_I_n_38,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_1\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_1\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_10\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_10\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_11\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_11\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_12\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_12\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_13\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_13\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_14\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_14\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_15\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_15\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_16\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_16\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_17\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_17\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_18\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_18\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_19\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_19\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_2\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_2\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_20\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_20\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_21\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_21\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_22\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_22\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_23\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_23\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_24\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_24\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_25\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_25\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_26\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_26\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_27\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_27\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_28\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_28\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_29\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_29\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_3\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_3\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_4\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_4\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_5\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_5\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_6\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_6\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_7\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_7\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_8\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_8\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_9\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_9\,
\INFERRED_GEN.icount_out_reg[31]\ => \^bus2ip_reset\,
Q(0) => TIMER_CONTROL_I_n_4,
S(0) => TIMER_CONTROL_I_n_40,
\TCSR0_GENERATE[20].TCSR0_FF_I\ => TIMER_CONTROL_I_n_35,
counter_En(0) => counter_En(1),
counter_TC(0) => counter_TC(1),
generateOutPre10 => generateOutPre10,
load_Counter_Reg(0) => load_Counter_Reg(1),
read_Mux_In(63 downto 32) => \^read_mux_in\(95 downto 64),
read_Mux_In(31 downto 0) => \^read_mux_in\(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn
);
PWM_FF_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => TIMER_CONTROL_I_n_39,
Q => \^pwm0\,
R => R
);
READ_MUX_I: entity work.system_axi_timer_0_0_mux_onehot_f
port map (
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1 => Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_10 => Bus_RNW_reg_reg_10,
Bus_RNW_reg_reg_11 => Bus_RNW_reg_reg_11,
Bus_RNW_reg_reg_12 => Bus_RNW_reg_reg_12,
Bus_RNW_reg_reg_13 => Bus_RNW_reg_reg_13,
Bus_RNW_reg_reg_14 => Bus_RNW_reg_reg_14,
Bus_RNW_reg_reg_15 => Bus_RNW_reg_reg_15,
Bus_RNW_reg_reg_16 => Bus_RNW_reg_reg_16,
Bus_RNW_reg_reg_17 => Bus_RNW_reg_reg_17,
Bus_RNW_reg_reg_18 => Bus_RNW_reg_reg_18,
Bus_RNW_reg_reg_2 => Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3 => Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4 => Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5 => Bus_RNW_reg_reg_5,
Bus_RNW_reg_reg_6 => Bus_RNW_reg_reg_6,
Bus_RNW_reg_reg_7 => Bus_RNW_reg_reg_7,
Bus_RNW_reg_reg_8 => Bus_RNW_reg_reg_8,
Bus_RNW_reg_reg_9 => Bus_RNW_reg_reg_9,
D(31 downto 0) => D(31 downto 0),
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\INFERRED_GEN.icount_out_reg[0]\ => \INFERRED_GEN.icount_out_reg[0]\,
\INFERRED_GEN.icount_out_reg[10]\ => \INFERRED_GEN.icount_out_reg[10]\,
\INFERRED_GEN.icount_out_reg[11]\ => \INFERRED_GEN.icount_out_reg[11]\,
\INFERRED_GEN.icount_out_reg[12]\ => \INFERRED_GEN.icount_out_reg[12]\,
\INFERRED_GEN.icount_out_reg[13]\ => \INFERRED_GEN.icount_out_reg[13]\,
\INFERRED_GEN.icount_out_reg[14]\ => \INFERRED_GEN.icount_out_reg[14]\,
\INFERRED_GEN.icount_out_reg[15]\ => \INFERRED_GEN.icount_out_reg[15]\,
\INFERRED_GEN.icount_out_reg[16]\ => \INFERRED_GEN.icount_out_reg[16]\,
\INFERRED_GEN.icount_out_reg[17]\ => \INFERRED_GEN.icount_out_reg[17]\,
\INFERRED_GEN.icount_out_reg[18]\ => \INFERRED_GEN.icount_out_reg[18]\,
\INFERRED_GEN.icount_out_reg[19]\ => \INFERRED_GEN.icount_out_reg[19]\,
\INFERRED_GEN.icount_out_reg[1]\ => \INFERRED_GEN.icount_out_reg[1]\,
\INFERRED_GEN.icount_out_reg[20]\ => \INFERRED_GEN.icount_out_reg[20]\,
\INFERRED_GEN.icount_out_reg[21]\ => \INFERRED_GEN.icount_out_reg[21]\,
\INFERRED_GEN.icount_out_reg[22]\ => \INFERRED_GEN.icount_out_reg[22]\,
\INFERRED_GEN.icount_out_reg[23]\ => \INFERRED_GEN.icount_out_reg[23]\,
\INFERRED_GEN.icount_out_reg[24]\ => \INFERRED_GEN.icount_out_reg[24]\,
\INFERRED_GEN.icount_out_reg[25]\ => \INFERRED_GEN.icount_out_reg[25]\,
\INFERRED_GEN.icount_out_reg[26]\ => \INFERRED_GEN.icount_out_reg[26]\,
\INFERRED_GEN.icount_out_reg[27]\ => \INFERRED_GEN.icount_out_reg[27]\,
\INFERRED_GEN.icount_out_reg[28]\ => \INFERRED_GEN.icount_out_reg[28]\,
\INFERRED_GEN.icount_out_reg[29]\ => \INFERRED_GEN.icount_out_reg[29]\,
\INFERRED_GEN.icount_out_reg[2]\ => \INFERRED_GEN.icount_out_reg[2]\,
\INFERRED_GEN.icount_out_reg[30]\ => \INFERRED_GEN.icount_out_reg[30]\,
\INFERRED_GEN.icount_out_reg[31]\ => \INFERRED_GEN.icount_out_reg[31]\,
\INFERRED_GEN.icount_out_reg[3]\ => \INFERRED_GEN.icount_out_reg[3]\,
\INFERRED_GEN.icount_out_reg[4]\ => \INFERRED_GEN.icount_out_reg[4]\,
\INFERRED_GEN.icount_out_reg[5]\ => \INFERRED_GEN.icount_out_reg[5]\,
\INFERRED_GEN.icount_out_reg[6]\ => \INFERRED_GEN.icount_out_reg[6]\,
\INFERRED_GEN.icount_out_reg[7]\ => \INFERRED_GEN.icount_out_reg[7]\,
\INFERRED_GEN.icount_out_reg[8]\ => \INFERRED_GEN.icount_out_reg[8]\,
\INFERRED_GEN.icount_out_reg[9]\ => \INFERRED_GEN.icount_out_reg[9]\,
\TCSR1_GENERATE[21].TCSR1_FF_I\ => \TCSR1_GENERATE[21].TCSR1_FF_I\,
\TCSR1_GENERATE[22].TCSR1_FF_I\ => \TCSR1_GENERATE[22].TCSR1_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
\TCSR1_GENERATE[25].TCSR1_FF_I\ => \TCSR1_GENERATE[25].TCSR1_FF_I\,
\TCSR1_GENERATE[26].TCSR1_FF_I\ => \TCSR1_GENERATE[26].TCSR1_FF_I\,
\TCSR1_GENERATE[27].TCSR1_FF_I\ => \TCSR1_GENERATE[27].TCSR1_FF_I\,
\TCSR1_GENERATE[28].TCSR1_FF_I\ => \TCSR1_GENERATE[28].TCSR1_FF_I\,
\TCSR1_GENERATE[29].TCSR1_FF_I\ => \TCSR1_GENERATE[29].TCSR1_FF_I\,
\TCSR1_GENERATE[30].TCSR1_FF_I\ => \TCSR1_GENERATE[30].TCSR1_FF_I\,
\TCSR1_GENERATE[31].TCSR1_FF_I\ => \TCSR1_GENERATE[31].TCSR1_FF_I\
);
TIMER_CONTROL_I: entity work.system_axi_timer_0_0_timer_control
port map (
Bus_RNW_reg => Bus_RNW_reg,
CE => CE_0,
CE_0 => CE,
D_0 => D_0,
E(0) => TIMER_CONTROL_I_n_32,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_30\,
\INFERRED_GEN.icount_out_reg[0]\ => \^read_mux_in\(150),
\INFERRED_GEN.icount_out_reg[0]_0\(0) => TIMER_CONTROL_I_n_38,
\INFERRED_GEN.icount_out_reg[1]\(1) => \^read_mux_in\(33),
\INFERRED_GEN.icount_out_reg[1]\(0) => \^read_mux_in\(1),
\INFERRED_GEN.icount_out_reg[32]\ => TIMER_CONTROL_I_n_35,
\INFERRED_GEN.icount_out_reg[4]\(0) => TIMER_CONTROL_I_n_41,
PWM_FF_I => TIMER_CONTROL_I_n_39,
Q(1) => TIMER_CONTROL_I_n_3,
Q(0) => TIMER_CONTROL_I_n_4,
R => R,
S(0) => TIMER_CONTROL_I_n_40,
SR(0) => \^bus2ip_reset\,
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I_0\,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
counter_En(0) => counter_En(1),
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateOutPre00 => generateOutPre00,
generateOutPre10 => generateOutPre10,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
load_Counter_Reg(0 to 1) => load_Counter_Reg(0 to 1),
pair0_Select => pair0_Select,
pwm0 => \^pwm0\,
read_Mux_In(21 downto 0) => \^read_mux_in\(149 downto 128),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 150 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_timer_0_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_timer_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_timer_0_0_slave_attachment
port map (
D(31 downto 0) => D(31 downto 0),
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_2\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => Bus_RNW_reg,
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
pair0_Select => pair0_Select,
read_Mux_In(150 downto 0) => read_Mux_In(150 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[0]_1\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[10]_0\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[10]_1\ => \s_axi_rdata_i_reg[10]_0\,
\s_axi_rdata_i_reg[11]_0\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[11]_1\ => \s_axi_rdata_i_reg[11]_0\,
\s_axi_rdata_i_reg[12]_0\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[12]_1\ => \s_axi_rdata_i_reg[12]_0\,
\s_axi_rdata_i_reg[13]_0\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[13]_1\ => \s_axi_rdata_i_reg[13]_0\,
\s_axi_rdata_i_reg[14]_0\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[14]_1\ => \s_axi_rdata_i_reg[14]_0\,
\s_axi_rdata_i_reg[15]_0\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[15]_1\ => \s_axi_rdata_i_reg[15]_0\,
\s_axi_rdata_i_reg[16]_0\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[16]_1\ => \s_axi_rdata_i_reg[16]_0\,
\s_axi_rdata_i_reg[17]_0\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[17]_1\ => \s_axi_rdata_i_reg[17]_0\,
\s_axi_rdata_i_reg[18]_0\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[18]_1\ => \s_axi_rdata_i_reg[18]_0\,
\s_axi_rdata_i_reg[19]_0\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[19]_1\ => \s_axi_rdata_i_reg[19]_0\,
\s_axi_rdata_i_reg[1]_0\ => \s_axi_rdata_i_reg[1]\,
\s_axi_rdata_i_reg[1]_1\ => \s_axi_rdata_i_reg[1]_0\,
\s_axi_rdata_i_reg[20]_0\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[20]_1\ => \s_axi_rdata_i_reg[20]_0\,
\s_axi_rdata_i_reg[21]_0\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[21]_1\ => \s_axi_rdata_i_reg[21]_0\,
\s_axi_rdata_i_reg[22]_0\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[22]_1\ => \s_axi_rdata_i_reg[22]_0\,
\s_axi_rdata_i_reg[23]_0\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[23]_1\ => \s_axi_rdata_i_reg[23]_0\,
\s_axi_rdata_i_reg[24]_0\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[24]_1\ => \s_axi_rdata_i_reg[24]_0\,
\s_axi_rdata_i_reg[25]_0\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[25]_1\ => \s_axi_rdata_i_reg[25]_0\,
\s_axi_rdata_i_reg[26]_0\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[26]_1\ => \s_axi_rdata_i_reg[26]_0\,
\s_axi_rdata_i_reg[27]_0\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[27]_1\ => \s_axi_rdata_i_reg[27]_0\,
\s_axi_rdata_i_reg[28]_0\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[28]_1\ => \s_axi_rdata_i_reg[28]_0\,
\s_axi_rdata_i_reg[29]_0\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[29]_1\ => \s_axi_rdata_i_reg[29]_0\,
\s_axi_rdata_i_reg[2]_0\ => \s_axi_rdata_i_reg[2]\,
\s_axi_rdata_i_reg[2]_1\ => \s_axi_rdata_i_reg[2]_0\,
\s_axi_rdata_i_reg[30]_0\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[30]_1\ => \s_axi_rdata_i_reg[30]_0\,
\s_axi_rdata_i_reg[31]_0\ => \s_axi_rdata_i_reg[31]\,
\s_axi_rdata_i_reg[31]_1\ => \s_axi_rdata_i_reg[31]_0\,
\s_axi_rdata_i_reg[3]_0\ => \s_axi_rdata_i_reg[3]\,
\s_axi_rdata_i_reg[3]_1\ => \s_axi_rdata_i_reg[3]_0\,
\s_axi_rdata_i_reg[4]_0\ => \s_axi_rdata_i_reg[4]\,
\s_axi_rdata_i_reg[4]_1\ => \s_axi_rdata_i_reg[4]_0\,
\s_axi_rdata_i_reg[5]_0\ => \s_axi_rdata_i_reg[5]\,
\s_axi_rdata_i_reg[5]_1\ => \s_axi_rdata_i_reg[5]_0\,
\s_axi_rdata_i_reg[6]_0\ => \s_axi_rdata_i_reg[6]\,
\s_axi_rdata_i_reg[6]_1\ => \s_axi_rdata_i_reg[6]_0\,
\s_axi_rdata_i_reg[7]_0\ => \s_axi_rdata_i_reg[7]\,
\s_axi_rdata_i_reg[7]_1\ => \s_axi_rdata_i_reg[7]_0\,
\s_axi_rdata_i_reg[8]_0\ => \s_axi_rdata_i_reg[8]\,
\s_axi_rdata_i_reg[8]_1\ => \s_axi_rdata_i_reg[8]_0\,
\s_axi_rdata_i_reg[9]_0\ => \s_axi_rdata_i_reg[9]\,
\s_axi_rdata_i_reg[9]_1\ => \s_axi_rdata_i_reg[9]_0\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0_axi_timer is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of system_axi_timer_0_0_axi_timer : entity is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_timer_0_0_axi_timer : entity is "artix7";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of system_axi_timer_0_0_axi_timer : entity is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of system_axi_timer_0_0_axi_timer : entity is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of system_axi_timer_0_0_axi_timer : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_timer_0_0_axi_timer : entity is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_timer_0_0_axi_timer : entity is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of system_axi_timer_0_0_axi_timer : entity is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of system_axi_timer_0_0_axi_timer : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_timer_0_0_axi_timer : entity is "axi_timer";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_timer_0_0_axi_timer : entity is "yes";
end system_axi_timer_0_0_axi_timer;
architecture STRUCTURE of system_axi_timer_0_0_axi_timer is
signal \<const0>\ : STD_LOGIC;
signal AXI4_LITE_I_n_10 : STD_LOGIC;
signal AXI4_LITE_I_n_100 : STD_LOGIC;
signal AXI4_LITE_I_n_101 : STD_LOGIC;
signal AXI4_LITE_I_n_102 : STD_LOGIC;
signal AXI4_LITE_I_n_103 : STD_LOGIC;
signal AXI4_LITE_I_n_104 : STD_LOGIC;
signal AXI4_LITE_I_n_105 : STD_LOGIC;
signal AXI4_LITE_I_n_106 : STD_LOGIC;
signal AXI4_LITE_I_n_107 : STD_LOGIC;
signal AXI4_LITE_I_n_108 : STD_LOGIC;
signal AXI4_LITE_I_n_109 : STD_LOGIC;
signal AXI4_LITE_I_n_11 : STD_LOGIC;
signal AXI4_LITE_I_n_110 : STD_LOGIC;
signal AXI4_LITE_I_n_111 : STD_LOGIC;
signal AXI4_LITE_I_n_112 : STD_LOGIC;
signal AXI4_LITE_I_n_113 : STD_LOGIC;
signal AXI4_LITE_I_n_114 : STD_LOGIC;
signal AXI4_LITE_I_n_115 : STD_LOGIC;
signal AXI4_LITE_I_n_116 : STD_LOGIC;
signal AXI4_LITE_I_n_117 : STD_LOGIC;
signal AXI4_LITE_I_n_118 : STD_LOGIC;
signal AXI4_LITE_I_n_119 : STD_LOGIC;
signal AXI4_LITE_I_n_12 : STD_LOGIC;
signal AXI4_LITE_I_n_120 : STD_LOGIC;
signal AXI4_LITE_I_n_121 : STD_LOGIC;
signal AXI4_LITE_I_n_122 : STD_LOGIC;
signal AXI4_LITE_I_n_123 : STD_LOGIC;
signal AXI4_LITE_I_n_124 : STD_LOGIC;
signal AXI4_LITE_I_n_125 : STD_LOGIC;
signal AXI4_LITE_I_n_126 : STD_LOGIC;
signal AXI4_LITE_I_n_127 : STD_LOGIC;
signal AXI4_LITE_I_n_128 : STD_LOGIC;
signal AXI4_LITE_I_n_129 : STD_LOGIC;
signal AXI4_LITE_I_n_13 : STD_LOGIC;
signal AXI4_LITE_I_n_130 : STD_LOGIC;
signal AXI4_LITE_I_n_131 : STD_LOGIC;
signal AXI4_LITE_I_n_132 : STD_LOGIC;
signal AXI4_LITE_I_n_133 : STD_LOGIC;
signal AXI4_LITE_I_n_134 : STD_LOGIC;
signal AXI4_LITE_I_n_135 : STD_LOGIC;
signal AXI4_LITE_I_n_136 : STD_LOGIC;
signal AXI4_LITE_I_n_137 : STD_LOGIC;
signal AXI4_LITE_I_n_138 : STD_LOGIC;
signal AXI4_LITE_I_n_139 : STD_LOGIC;
signal AXI4_LITE_I_n_14 : STD_LOGIC;
signal AXI4_LITE_I_n_140 : STD_LOGIC;
signal AXI4_LITE_I_n_142 : STD_LOGIC;
signal AXI4_LITE_I_n_143 : STD_LOGIC;
signal AXI4_LITE_I_n_15 : STD_LOGIC;
signal AXI4_LITE_I_n_16 : STD_LOGIC;
signal AXI4_LITE_I_n_19 : STD_LOGIC;
signal AXI4_LITE_I_n_20 : STD_LOGIC;
signal AXI4_LITE_I_n_21 : STD_LOGIC;
signal AXI4_LITE_I_n_22 : STD_LOGIC;
signal AXI4_LITE_I_n_23 : STD_LOGIC;
signal AXI4_LITE_I_n_24 : STD_LOGIC;
signal AXI4_LITE_I_n_25 : STD_LOGIC;
signal AXI4_LITE_I_n_26 : STD_LOGIC;
signal AXI4_LITE_I_n_27 : STD_LOGIC;
signal AXI4_LITE_I_n_28 : STD_LOGIC;
signal AXI4_LITE_I_n_29 : STD_LOGIC;
signal AXI4_LITE_I_n_30 : STD_LOGIC;
signal AXI4_LITE_I_n_31 : STD_LOGIC;
signal AXI4_LITE_I_n_32 : STD_LOGIC;
signal AXI4_LITE_I_n_33 : STD_LOGIC;
signal AXI4_LITE_I_n_34 : STD_LOGIC;
signal AXI4_LITE_I_n_35 : STD_LOGIC;
signal AXI4_LITE_I_n_36 : STD_LOGIC;
signal AXI4_LITE_I_n_37 : STD_LOGIC;
signal AXI4_LITE_I_n_38 : STD_LOGIC;
signal AXI4_LITE_I_n_40 : STD_LOGIC;
signal AXI4_LITE_I_n_41 : STD_LOGIC;
signal AXI4_LITE_I_n_44 : STD_LOGIC;
signal AXI4_LITE_I_n_45 : STD_LOGIC;
signal AXI4_LITE_I_n_46 : STD_LOGIC;
signal AXI4_LITE_I_n_47 : STD_LOGIC;
signal AXI4_LITE_I_n_48 : STD_LOGIC;
signal AXI4_LITE_I_n_49 : STD_LOGIC;
signal AXI4_LITE_I_n_5 : STD_LOGIC;
signal AXI4_LITE_I_n_50 : STD_LOGIC;
signal AXI4_LITE_I_n_51 : STD_LOGIC;
signal AXI4_LITE_I_n_52 : STD_LOGIC;
signal AXI4_LITE_I_n_53 : STD_LOGIC;
signal AXI4_LITE_I_n_54 : STD_LOGIC;
signal AXI4_LITE_I_n_55 : STD_LOGIC;
signal AXI4_LITE_I_n_56 : STD_LOGIC;
signal AXI4_LITE_I_n_57 : STD_LOGIC;
signal AXI4_LITE_I_n_58 : STD_LOGIC;
signal AXI4_LITE_I_n_59 : STD_LOGIC;
signal AXI4_LITE_I_n_6 : STD_LOGIC;
signal AXI4_LITE_I_n_60 : STD_LOGIC;
signal AXI4_LITE_I_n_61 : STD_LOGIC;
signal AXI4_LITE_I_n_62 : STD_LOGIC;
signal AXI4_LITE_I_n_63 : STD_LOGIC;
signal AXI4_LITE_I_n_64 : STD_LOGIC;
signal AXI4_LITE_I_n_65 : STD_LOGIC;
signal AXI4_LITE_I_n_66 : STD_LOGIC;
signal AXI4_LITE_I_n_67 : STD_LOGIC;
signal AXI4_LITE_I_n_68 : STD_LOGIC;
signal AXI4_LITE_I_n_69 : STD_LOGIC;
signal AXI4_LITE_I_n_7 : STD_LOGIC;
signal AXI4_LITE_I_n_70 : STD_LOGIC;
signal AXI4_LITE_I_n_71 : STD_LOGIC;
signal AXI4_LITE_I_n_72 : STD_LOGIC;
signal AXI4_LITE_I_n_73 : STD_LOGIC;
signal AXI4_LITE_I_n_74 : STD_LOGIC;
signal AXI4_LITE_I_n_75 : STD_LOGIC;
signal AXI4_LITE_I_n_76 : STD_LOGIC;
signal AXI4_LITE_I_n_78 : STD_LOGIC;
signal AXI4_LITE_I_n_79 : STD_LOGIC;
signal AXI4_LITE_I_n_8 : STD_LOGIC;
signal AXI4_LITE_I_n_80 : STD_LOGIC;
signal AXI4_LITE_I_n_81 : STD_LOGIC;
signal AXI4_LITE_I_n_82 : STD_LOGIC;
signal AXI4_LITE_I_n_83 : STD_LOGIC;
signal AXI4_LITE_I_n_84 : STD_LOGIC;
signal AXI4_LITE_I_n_85 : STD_LOGIC;
signal AXI4_LITE_I_n_86 : STD_LOGIC;
signal AXI4_LITE_I_n_87 : STD_LOGIC;
signal AXI4_LITE_I_n_88 : STD_LOGIC;
signal AXI4_LITE_I_n_89 : STD_LOGIC;
signal AXI4_LITE_I_n_9 : STD_LOGIC;
signal AXI4_LITE_I_n_90 : STD_LOGIC;
signal AXI4_LITE_I_n_91 : STD_LOGIC;
signal AXI4_LITE_I_n_92 : STD_LOGIC;
signal AXI4_LITE_I_n_93 : STD_LOGIC;
signal AXI4_LITE_I_n_94 : STD_LOGIC;
signal AXI4_LITE_I_n_95 : STD_LOGIC;
signal AXI4_LITE_I_n_96 : STD_LOGIC;
signal AXI4_LITE_I_n_97 : STD_LOGIC;
signal AXI4_LITE_I_n_98 : STD_LOGIC;
signal AXI4_LITE_I_n_99 : STD_LOGIC;
signal \COUNTER_0_I/D\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I/D\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : STD_LOGIC;
signal \TIMER_CONTROL_I/D\ : STD_LOGIC;
signal \TIMER_CONTROL_I/pair0_Select\ : STD_LOGIC;
signal \TIMER_CONTROL_I/read_done1\ : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_wrce : STD_LOGIC_VECTOR ( 0 to 4 );
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal read_Mux_In : STD_LOGIC_VECTOR ( 20 to 191 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI4_LITE_I: entity work.system_axi_timer_0_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \COUNTER_0_I/D\,
D_1 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
D_2 => \TIMER_CONTROL_I/D\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
\LOAD_REG_GEN[10].LOAD_REG_I\ => AXI4_LITE_I_n_67,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => AXI4_LITE_I_n_131,
\LOAD_REG_GEN[11].LOAD_REG_I\ => AXI4_LITE_I_n_66,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => AXI4_LITE_I_n_130,
\LOAD_REG_GEN[12].LOAD_REG_I\ => AXI4_LITE_I_n_65,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => AXI4_LITE_I_n_129,
\LOAD_REG_GEN[13].LOAD_REG_I\ => AXI4_LITE_I_n_64,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => AXI4_LITE_I_n_128,
\LOAD_REG_GEN[14].LOAD_REG_I\ => AXI4_LITE_I_n_63,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => AXI4_LITE_I_n_127,
\LOAD_REG_GEN[15].LOAD_REG_I\ => AXI4_LITE_I_n_62,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => AXI4_LITE_I_n_126,
\LOAD_REG_GEN[16].LOAD_REG_I\ => AXI4_LITE_I_n_61,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => AXI4_LITE_I_n_125,
\LOAD_REG_GEN[17].LOAD_REG_I\ => AXI4_LITE_I_n_60,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => AXI4_LITE_I_n_124,
\LOAD_REG_GEN[18].LOAD_REG_I\ => AXI4_LITE_I_n_59,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => AXI4_LITE_I_n_123,
\LOAD_REG_GEN[19].LOAD_REG_I\ => AXI4_LITE_I_n_58,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => AXI4_LITE_I_n_122,
\LOAD_REG_GEN[1].LOAD_REG_I\ => AXI4_LITE_I_n_76,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => AXI4_LITE_I_n_140,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_57,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => AXI4_LITE_I_n_121,
\LOAD_REG_GEN[21].LOAD_REG_I\ => AXI4_LITE_I_n_56,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => AXI4_LITE_I_n_120,
\LOAD_REG_GEN[22].LOAD_REG_I\ => AXI4_LITE_I_n_55,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => AXI4_LITE_I_n_119,
\LOAD_REG_GEN[23].LOAD_REG_I\ => AXI4_LITE_I_n_54,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => AXI4_LITE_I_n_118,
\LOAD_REG_GEN[24].LOAD_REG_I\ => AXI4_LITE_I_n_53,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => AXI4_LITE_I_n_117,
\LOAD_REG_GEN[25].LOAD_REG_I\ => AXI4_LITE_I_n_52,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => AXI4_LITE_I_n_116,
\LOAD_REG_GEN[26].LOAD_REG_I\ => AXI4_LITE_I_n_51,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => AXI4_LITE_I_n_115,
\LOAD_REG_GEN[27].LOAD_REG_I\ => AXI4_LITE_I_n_50,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => AXI4_LITE_I_n_114,
\LOAD_REG_GEN[28].LOAD_REG_I\ => AXI4_LITE_I_n_49,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => AXI4_LITE_I_n_113,
\LOAD_REG_GEN[29].LOAD_REG_I\ => AXI4_LITE_I_n_48,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => AXI4_LITE_I_n_112,
\LOAD_REG_GEN[2].LOAD_REG_I\ => AXI4_LITE_I_n_75,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => AXI4_LITE_I_n_139,
\LOAD_REG_GEN[30].LOAD_REG_I\ => AXI4_LITE_I_n_47,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => AXI4_LITE_I_n_111,
\LOAD_REG_GEN[31].LOAD_REG_I\ => AXI4_LITE_I_n_46,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => AXI4_LITE_I_n_110,
\LOAD_REG_GEN[3].LOAD_REG_I\ => AXI4_LITE_I_n_74,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => AXI4_LITE_I_n_138,
\LOAD_REG_GEN[4].LOAD_REG_I\ => AXI4_LITE_I_n_73,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => AXI4_LITE_I_n_137,
\LOAD_REG_GEN[5].LOAD_REG_I\ => AXI4_LITE_I_n_72,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => AXI4_LITE_I_n_136,
\LOAD_REG_GEN[6].LOAD_REG_I\ => AXI4_LITE_I_n_71,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => AXI4_LITE_I_n_135,
\LOAD_REG_GEN[7].LOAD_REG_I\ => AXI4_LITE_I_n_70,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => AXI4_LITE_I_n_134,
\LOAD_REG_GEN[8].LOAD_REG_I\ => AXI4_LITE_I_n_69,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => AXI4_LITE_I_n_133,
\LOAD_REG_GEN[9].LOAD_REG_I\ => AXI4_LITE_I_n_68,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => AXI4_LITE_I_n_132,
READ_DONE0_I => AXI4_LITE_I_n_142,
READ_DONE1_I => AXI4_LITE_I_n_143,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => AXI4_LITE_I_n_40,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_41,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => AXI4_LITE_I_n_44,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_45,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
read_Mux_In(150) => read_Mux_In(20),
read_Mux_In(149) => read_Mux_In(21),
read_Mux_In(148) => read_Mux_In(22),
read_Mux_In(147) => read_Mux_In(23),
read_Mux_In(146) => read_Mux_In(24),
read_Mux_In(145) => read_Mux_In(25),
read_Mux_In(144) => read_Mux_In(26),
read_Mux_In(143) => read_Mux_In(27),
read_Mux_In(142) => read_Mux_In(28),
read_Mux_In(141) => read_Mux_In(29),
read_Mux_In(140) => read_Mux_In(30),
read_Mux_In(139) => read_Mux_In(31),
read_Mux_In(138) => read_Mux_In(53),
read_Mux_In(137) => read_Mux_In(54),
read_Mux_In(136) => read_Mux_In(55),
read_Mux_In(135) => read_Mux_In(56),
read_Mux_In(134) => read_Mux_In(57),
read_Mux_In(133) => read_Mux_In(58),
read_Mux_In(132) => read_Mux_In(59),
read_Mux_In(131) => read_Mux_In(60),
read_Mux_In(130) => read_Mux_In(61),
read_Mux_In(129) => read_Mux_In(62),
read_Mux_In(128) => read_Mux_In(63),
read_Mux_In(127) => read_Mux_In(64),
read_Mux_In(126) => read_Mux_In(65),
read_Mux_In(125) => read_Mux_In(66),
read_Mux_In(124) => read_Mux_In(67),
read_Mux_In(123) => read_Mux_In(68),
read_Mux_In(122) => read_Mux_In(69),
read_Mux_In(121) => read_Mux_In(70),
read_Mux_In(120) => read_Mux_In(71),
read_Mux_In(119) => read_Mux_In(72),
read_Mux_In(118) => read_Mux_In(73),
read_Mux_In(117) => read_Mux_In(74),
read_Mux_In(116) => read_Mux_In(75),
read_Mux_In(115) => read_Mux_In(76),
read_Mux_In(114) => read_Mux_In(77),
read_Mux_In(113) => read_Mux_In(78),
read_Mux_In(112) => read_Mux_In(79),
read_Mux_In(111) => read_Mux_In(80),
read_Mux_In(110) => read_Mux_In(81),
read_Mux_In(109) => read_Mux_In(82),
read_Mux_In(108) => read_Mux_In(83),
read_Mux_In(107) => read_Mux_In(84),
read_Mux_In(106) => read_Mux_In(85),
read_Mux_In(105) => read_Mux_In(86),
read_Mux_In(104) => read_Mux_In(87),
read_Mux_In(103) => read_Mux_In(88),
read_Mux_In(102) => read_Mux_In(89),
read_Mux_In(101) => read_Mux_In(90),
read_Mux_In(100) => read_Mux_In(91),
read_Mux_In(99) => read_Mux_In(92),
read_Mux_In(98) => read_Mux_In(93),
read_Mux_In(97) => read_Mux_In(94),
read_Mux_In(96) => read_Mux_In(95),
read_Mux_In(95) => read_Mux_In(96),
read_Mux_In(94) => read_Mux_In(97),
read_Mux_In(93) => read_Mux_In(98),
read_Mux_In(92) => read_Mux_In(99),
read_Mux_In(91) => read_Mux_In(100),
read_Mux_In(90) => read_Mux_In(101),
read_Mux_In(89) => read_Mux_In(102),
read_Mux_In(88) => read_Mux_In(103),
read_Mux_In(87) => read_Mux_In(104),
read_Mux_In(86) => read_Mux_In(105),
read_Mux_In(85) => read_Mux_In(106),
read_Mux_In(84) => read_Mux_In(107),
read_Mux_In(83) => read_Mux_In(108),
read_Mux_In(82) => read_Mux_In(109),
read_Mux_In(81) => read_Mux_In(110),
read_Mux_In(80) => read_Mux_In(111),
read_Mux_In(79) => read_Mux_In(112),
read_Mux_In(78) => read_Mux_In(113),
read_Mux_In(77) => read_Mux_In(114),
read_Mux_In(76) => read_Mux_In(115),
read_Mux_In(75) => read_Mux_In(116),
read_Mux_In(74) => read_Mux_In(117),
read_Mux_In(73) => read_Mux_In(118),
read_Mux_In(72) => read_Mux_In(119),
read_Mux_In(71) => read_Mux_In(120),
read_Mux_In(70) => read_Mux_In(121),
read_Mux_In(69) => read_Mux_In(122),
read_Mux_In(68) => read_Mux_In(123),
read_Mux_In(67) => read_Mux_In(124),
read_Mux_In(66) => read_Mux_In(125),
read_Mux_In(65) => read_Mux_In(126),
read_Mux_In(64) => read_Mux_In(127),
read_Mux_In(63) => read_Mux_In(128),
read_Mux_In(62) => read_Mux_In(129),
read_Mux_In(61) => read_Mux_In(130),
read_Mux_In(60) => read_Mux_In(131),
read_Mux_In(59) => read_Mux_In(132),
read_Mux_In(58) => read_Mux_In(133),
read_Mux_In(57) => read_Mux_In(134),
read_Mux_In(56) => read_Mux_In(135),
read_Mux_In(55) => read_Mux_In(136),
read_Mux_In(54) => read_Mux_In(137),
read_Mux_In(53) => read_Mux_In(138),
read_Mux_In(52) => read_Mux_In(139),
read_Mux_In(51) => read_Mux_In(140),
read_Mux_In(50) => read_Mux_In(141),
read_Mux_In(49) => read_Mux_In(142),
read_Mux_In(48) => read_Mux_In(143),
read_Mux_In(47) => read_Mux_In(144),
read_Mux_In(46) => read_Mux_In(145),
read_Mux_In(45) => read_Mux_In(146),
read_Mux_In(44) => read_Mux_In(147),
read_Mux_In(43) => read_Mux_In(148),
read_Mux_In(42) => read_Mux_In(149),
read_Mux_In(41) => read_Mux_In(150),
read_Mux_In(40) => read_Mux_In(151),
read_Mux_In(39) => read_Mux_In(152),
read_Mux_In(38) => read_Mux_In(153),
read_Mux_In(37) => read_Mux_In(154),
read_Mux_In(36) => read_Mux_In(155),
read_Mux_In(35) => read_Mux_In(156),
read_Mux_In(34) => read_Mux_In(157),
read_Mux_In(33) => read_Mux_In(158),
read_Mux_In(32) => read_Mux_In(159),
read_Mux_In(31) => read_Mux_In(160),
read_Mux_In(30) => read_Mux_In(161),
read_Mux_In(29) => read_Mux_In(162),
read_Mux_In(28) => read_Mux_In(163),
read_Mux_In(27) => read_Mux_In(164),
read_Mux_In(26) => read_Mux_In(165),
read_Mux_In(25) => read_Mux_In(166),
read_Mux_In(24) => read_Mux_In(167),
read_Mux_In(23) => read_Mux_In(168),
read_Mux_In(22) => read_Mux_In(169),
read_Mux_In(21) => read_Mux_In(170),
read_Mux_In(20) => read_Mux_In(171),
read_Mux_In(19) => read_Mux_In(172),
read_Mux_In(18) => read_Mux_In(173),
read_Mux_In(17) => read_Mux_In(174),
read_Mux_In(16) => read_Mux_In(175),
read_Mux_In(15) => read_Mux_In(176),
read_Mux_In(14) => read_Mux_In(177),
read_Mux_In(13) => read_Mux_In(178),
read_Mux_In(12) => read_Mux_In(179),
read_Mux_In(11) => read_Mux_In(180),
read_Mux_In(10) => read_Mux_In(181),
read_Mux_In(9) => read_Mux_In(182),
read_Mux_In(8) => read_Mux_In(183),
read_Mux_In(7) => read_Mux_In(184),
read_Mux_In(6) => read_Mux_In(185),
read_Mux_In(5) => read_Mux_In(186),
read_Mux_In(4) => read_Mux_In(187),
read_Mux_In(3) => read_Mux_In(188),
read_Mux_In(2) => read_Mux_In(189),
read_Mux_In(1) => read_Mux_In(190),
read_Mux_In(0) => read_Mux_In(191),
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(4 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(4 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]\ => AXI4_LITE_I_n_16,
\s_axi_rdata_i_reg[0]_0\ => AXI4_LITE_I_n_109,
\s_axi_rdata_i_reg[10]\ => AXI4_LITE_I_n_6,
\s_axi_rdata_i_reg[10]_0\ => AXI4_LITE_I_n_99,
\s_axi_rdata_i_reg[11]\ => AXI4_LITE_I_n_5,
\s_axi_rdata_i_reg[11]_0\ => AXI4_LITE_I_n_98,
\s_axi_rdata_i_reg[12]\ => AXI4_LITE_I_n_38,
\s_axi_rdata_i_reg[12]_0\ => AXI4_LITE_I_n_97,
\s_axi_rdata_i_reg[13]\ => AXI4_LITE_I_n_37,
\s_axi_rdata_i_reg[13]_0\ => AXI4_LITE_I_n_96,
\s_axi_rdata_i_reg[14]\ => AXI4_LITE_I_n_36,
\s_axi_rdata_i_reg[14]_0\ => AXI4_LITE_I_n_95,
\s_axi_rdata_i_reg[15]\ => AXI4_LITE_I_n_35,
\s_axi_rdata_i_reg[15]_0\ => AXI4_LITE_I_n_94,
\s_axi_rdata_i_reg[16]\ => AXI4_LITE_I_n_34,
\s_axi_rdata_i_reg[16]_0\ => AXI4_LITE_I_n_93,
\s_axi_rdata_i_reg[17]\ => AXI4_LITE_I_n_33,
\s_axi_rdata_i_reg[17]_0\ => AXI4_LITE_I_n_92,
\s_axi_rdata_i_reg[18]\ => AXI4_LITE_I_n_32,
\s_axi_rdata_i_reg[18]_0\ => AXI4_LITE_I_n_91,
\s_axi_rdata_i_reg[19]\ => AXI4_LITE_I_n_31,
\s_axi_rdata_i_reg[19]_0\ => AXI4_LITE_I_n_90,
\s_axi_rdata_i_reg[1]\ => AXI4_LITE_I_n_15,
\s_axi_rdata_i_reg[1]_0\ => AXI4_LITE_I_n_108,
\s_axi_rdata_i_reg[20]\ => AXI4_LITE_I_n_30,
\s_axi_rdata_i_reg[20]_0\ => AXI4_LITE_I_n_89,
\s_axi_rdata_i_reg[21]\ => AXI4_LITE_I_n_29,
\s_axi_rdata_i_reg[21]_0\ => AXI4_LITE_I_n_88,
\s_axi_rdata_i_reg[22]\ => AXI4_LITE_I_n_28,
\s_axi_rdata_i_reg[22]_0\ => AXI4_LITE_I_n_87,
\s_axi_rdata_i_reg[23]\ => AXI4_LITE_I_n_27,
\s_axi_rdata_i_reg[23]_0\ => AXI4_LITE_I_n_86,
\s_axi_rdata_i_reg[24]\ => AXI4_LITE_I_n_26,
\s_axi_rdata_i_reg[24]_0\ => AXI4_LITE_I_n_85,
\s_axi_rdata_i_reg[25]\ => AXI4_LITE_I_n_25,
\s_axi_rdata_i_reg[25]_0\ => AXI4_LITE_I_n_84,
\s_axi_rdata_i_reg[26]\ => AXI4_LITE_I_n_24,
\s_axi_rdata_i_reg[26]_0\ => AXI4_LITE_I_n_83,
\s_axi_rdata_i_reg[27]\ => AXI4_LITE_I_n_23,
\s_axi_rdata_i_reg[27]_0\ => AXI4_LITE_I_n_82,
\s_axi_rdata_i_reg[28]\ => AXI4_LITE_I_n_22,
\s_axi_rdata_i_reg[28]_0\ => AXI4_LITE_I_n_81,
\s_axi_rdata_i_reg[29]\ => AXI4_LITE_I_n_21,
\s_axi_rdata_i_reg[29]_0\ => AXI4_LITE_I_n_80,
\s_axi_rdata_i_reg[2]\ => AXI4_LITE_I_n_14,
\s_axi_rdata_i_reg[2]_0\ => AXI4_LITE_I_n_107,
\s_axi_rdata_i_reg[30]\ => AXI4_LITE_I_n_20,
\s_axi_rdata_i_reg[30]_0\ => AXI4_LITE_I_n_79,
\s_axi_rdata_i_reg[31]\ => AXI4_LITE_I_n_19,
\s_axi_rdata_i_reg[31]_0\ => AXI4_LITE_I_n_78,
\s_axi_rdata_i_reg[3]\ => AXI4_LITE_I_n_13,
\s_axi_rdata_i_reg[3]_0\ => AXI4_LITE_I_n_106,
\s_axi_rdata_i_reg[4]\ => AXI4_LITE_I_n_12,
\s_axi_rdata_i_reg[4]_0\ => AXI4_LITE_I_n_105,
\s_axi_rdata_i_reg[5]\ => AXI4_LITE_I_n_11,
\s_axi_rdata_i_reg[5]_0\ => AXI4_LITE_I_n_104,
\s_axi_rdata_i_reg[6]\ => AXI4_LITE_I_n_10,
\s_axi_rdata_i_reg[6]_0\ => AXI4_LITE_I_n_103,
\s_axi_rdata_i_reg[7]\ => AXI4_LITE_I_n_9,
\s_axi_rdata_i_reg[7]_0\ => AXI4_LITE_I_n_102,
\s_axi_rdata_i_reg[8]\ => AXI4_LITE_I_n_8,
\s_axi_rdata_i_reg[8]_0\ => AXI4_LITE_I_n_101,
\s_axi_rdata_i_reg[9]\ => AXI4_LITE_I_n_7,
\s_axi_rdata_i_reg[9]_0\ => AXI4_LITE_I_n_100,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
TC_CORE_I: entity work.system_axi_timer_0_0_tc_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI4_LITE_I_n_19,
Bus_RNW_reg_reg_0 => AXI4_LITE_I_n_20,
Bus_RNW_reg_reg_1 => AXI4_LITE_I_n_21,
Bus_RNW_reg_reg_10 => AXI4_LITE_I_n_30,
Bus_RNW_reg_reg_11 => AXI4_LITE_I_n_31,
Bus_RNW_reg_reg_12 => AXI4_LITE_I_n_32,
Bus_RNW_reg_reg_13 => AXI4_LITE_I_n_33,
Bus_RNW_reg_reg_14 => AXI4_LITE_I_n_34,
Bus_RNW_reg_reg_15 => AXI4_LITE_I_n_35,
Bus_RNW_reg_reg_16 => AXI4_LITE_I_n_36,
Bus_RNW_reg_reg_17 => AXI4_LITE_I_n_37,
Bus_RNW_reg_reg_18 => AXI4_LITE_I_n_38,
Bus_RNW_reg_reg_2 => AXI4_LITE_I_n_22,
Bus_RNW_reg_reg_3 => AXI4_LITE_I_n_23,
Bus_RNW_reg_reg_4 => AXI4_LITE_I_n_24,
Bus_RNW_reg_reg_5 => AXI4_LITE_I_n_25,
Bus_RNW_reg_reg_6 => AXI4_LITE_I_n_26,
Bus_RNW_reg_reg_7 => AXI4_LITE_I_n_27,
Bus_RNW_reg_reg_8 => AXI4_LITE_I_n_28,
Bus_RNW_reg_reg_9 => AXI4_LITE_I_n_29,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \TIMER_CONTROL_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI4_LITE_I_n_5,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI4_LITE_I_n_40,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI4_LITE_I_n_76,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => AXI4_LITE_I_n_75,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => AXI4_LITE_I_n_74,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => AXI4_LITE_I_n_65,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => AXI4_LITE_I_n_64,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => AXI4_LITE_I_n_63,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => AXI4_LITE_I_n_62,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => AXI4_LITE_I_n_61,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => AXI4_LITE_I_n_60,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => AXI4_LITE_I_n_59,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => AXI4_LITE_I_n_58,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => AXI4_LITE_I_n_57,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => AXI4_LITE_I_n_56,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => AXI4_LITE_I_n_73,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => AXI4_LITE_I_n_55,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => AXI4_LITE_I_n_54,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => AXI4_LITE_I_n_53,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => AXI4_LITE_I_n_52,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => AXI4_LITE_I_n_51,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => AXI4_LITE_I_n_50,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => AXI4_LITE_I_n_49,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => AXI4_LITE_I_n_48,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => AXI4_LITE_I_n_47,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => AXI4_LITE_I_n_46,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => AXI4_LITE_I_n_72,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ => AXI4_LITE_I_n_142,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => AXI4_LITE_I_n_71,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => AXI4_LITE_I_n_70,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => AXI4_LITE_I_n_69,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => AXI4_LITE_I_n_68,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => AXI4_LITE_I_n_67,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => AXI4_LITE_I_n_66,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI4_LITE_I_n_44,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => AXI4_LITE_I_n_140,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => AXI4_LITE_I_n_139,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_1\ => AXI4_LITE_I_n_138,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_10\ => AXI4_LITE_I_n_129,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_11\ => AXI4_LITE_I_n_128,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_12\ => AXI4_LITE_I_n_127,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_13\ => AXI4_LITE_I_n_126,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_14\ => AXI4_LITE_I_n_125,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_15\ => AXI4_LITE_I_n_124,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_16\ => AXI4_LITE_I_n_123,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_17\ => AXI4_LITE_I_n_122,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_18\ => AXI4_LITE_I_n_121,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_19\ => AXI4_LITE_I_n_120,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_2\ => AXI4_LITE_I_n_137,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_20\ => AXI4_LITE_I_n_119,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_21\ => AXI4_LITE_I_n_118,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_22\ => AXI4_LITE_I_n_117,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_23\ => AXI4_LITE_I_n_116,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_24\ => AXI4_LITE_I_n_115,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_25\ => AXI4_LITE_I_n_114,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_26\ => AXI4_LITE_I_n_113,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_27\ => AXI4_LITE_I_n_112,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_28\ => AXI4_LITE_I_n_111,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_29\ => AXI4_LITE_I_n_110,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_3\ => AXI4_LITE_I_n_136,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_30\ => AXI4_LITE_I_n_143,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_4\ => AXI4_LITE_I_n_135,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_5\ => AXI4_LITE_I_n_134,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_6\ => AXI4_LITE_I_n_133,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_7\ => AXI4_LITE_I_n_132,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_8\ => AXI4_LITE_I_n_131,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_9\ => AXI4_LITE_I_n_130,
\INFERRED_GEN.icount_out_reg[0]\ => AXI4_LITE_I_n_109,
\INFERRED_GEN.icount_out_reg[10]\ => AXI4_LITE_I_n_99,
\INFERRED_GEN.icount_out_reg[11]\ => AXI4_LITE_I_n_98,
\INFERRED_GEN.icount_out_reg[12]\ => AXI4_LITE_I_n_97,
\INFERRED_GEN.icount_out_reg[13]\ => AXI4_LITE_I_n_96,
\INFERRED_GEN.icount_out_reg[14]\ => AXI4_LITE_I_n_95,
\INFERRED_GEN.icount_out_reg[15]\ => AXI4_LITE_I_n_94,
\INFERRED_GEN.icount_out_reg[16]\ => AXI4_LITE_I_n_93,
\INFERRED_GEN.icount_out_reg[17]\ => AXI4_LITE_I_n_92,
\INFERRED_GEN.icount_out_reg[18]\ => AXI4_LITE_I_n_91,
\INFERRED_GEN.icount_out_reg[19]\ => AXI4_LITE_I_n_90,
\INFERRED_GEN.icount_out_reg[1]\ => AXI4_LITE_I_n_108,
\INFERRED_GEN.icount_out_reg[20]\ => AXI4_LITE_I_n_89,
\INFERRED_GEN.icount_out_reg[21]\ => AXI4_LITE_I_n_88,
\INFERRED_GEN.icount_out_reg[22]\ => AXI4_LITE_I_n_87,
\INFERRED_GEN.icount_out_reg[23]\ => AXI4_LITE_I_n_86,
\INFERRED_GEN.icount_out_reg[24]\ => AXI4_LITE_I_n_85,
\INFERRED_GEN.icount_out_reg[25]\ => AXI4_LITE_I_n_84,
\INFERRED_GEN.icount_out_reg[26]\ => AXI4_LITE_I_n_83,
\INFERRED_GEN.icount_out_reg[27]\ => AXI4_LITE_I_n_82,
\INFERRED_GEN.icount_out_reg[28]\ => AXI4_LITE_I_n_81,
\INFERRED_GEN.icount_out_reg[29]\ => AXI4_LITE_I_n_80,
\INFERRED_GEN.icount_out_reg[2]\ => AXI4_LITE_I_n_107,
\INFERRED_GEN.icount_out_reg[30]\ => AXI4_LITE_I_n_79,
\INFERRED_GEN.icount_out_reg[31]\ => AXI4_LITE_I_n_78,
\INFERRED_GEN.icount_out_reg[3]\ => AXI4_LITE_I_n_106,
\INFERRED_GEN.icount_out_reg[4]\ => AXI4_LITE_I_n_105,
\INFERRED_GEN.icount_out_reg[5]\ => AXI4_LITE_I_n_104,
\INFERRED_GEN.icount_out_reg[6]\ => AXI4_LITE_I_n_103,
\INFERRED_GEN.icount_out_reg[7]\ => AXI4_LITE_I_n_102,
\INFERRED_GEN.icount_out_reg[8]\ => AXI4_LITE_I_n_101,
\INFERRED_GEN.icount_out_reg[9]\ => AXI4_LITE_I_n_100,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_41,
\TCSR1_GENERATE[21].TCSR1_FF_I\ => AXI4_LITE_I_n_6,
\TCSR1_GENERATE[22].TCSR1_FF_I\ => AXI4_LITE_I_n_7,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => AXI4_LITE_I_n_8,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_9,
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ => AXI4_LITE_I_n_45,
\TCSR1_GENERATE[25].TCSR1_FF_I\ => AXI4_LITE_I_n_10,
\TCSR1_GENERATE[26].TCSR1_FF_I\ => AXI4_LITE_I_n_11,
\TCSR1_GENERATE[27].TCSR1_FF_I\ => AXI4_LITE_I_n_12,
\TCSR1_GENERATE[28].TCSR1_FF_I\ => AXI4_LITE_I_n_13,
\TCSR1_GENERATE[29].TCSR1_FF_I\ => AXI4_LITE_I_n_14,
\TCSR1_GENERATE[30].TCSR1_FF_I\ => AXI4_LITE_I_n_15,
\TCSR1_GENERATE[31].TCSR1_FF_I\ => AXI4_LITE_I_n_16,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
pwm0 => pwm0,
read_Mux_In(150) => read_Mux_In(20),
read_Mux_In(149) => read_Mux_In(21),
read_Mux_In(148) => read_Mux_In(22),
read_Mux_In(147) => read_Mux_In(23),
read_Mux_In(146) => read_Mux_In(24),
read_Mux_In(145) => read_Mux_In(25),
read_Mux_In(144) => read_Mux_In(26),
read_Mux_In(143) => read_Mux_In(27),
read_Mux_In(142) => read_Mux_In(28),
read_Mux_In(141) => read_Mux_In(29),
read_Mux_In(140) => read_Mux_In(30),
read_Mux_In(139) => read_Mux_In(31),
read_Mux_In(138) => read_Mux_In(53),
read_Mux_In(137) => read_Mux_In(54),
read_Mux_In(136) => read_Mux_In(55),
read_Mux_In(135) => read_Mux_In(56),
read_Mux_In(134) => read_Mux_In(57),
read_Mux_In(133) => read_Mux_In(58),
read_Mux_In(132) => read_Mux_In(59),
read_Mux_In(131) => read_Mux_In(60),
read_Mux_In(130) => read_Mux_In(61),
read_Mux_In(129) => read_Mux_In(62),
read_Mux_In(128) => read_Mux_In(63),
read_Mux_In(127) => read_Mux_In(64),
read_Mux_In(126) => read_Mux_In(65),
read_Mux_In(125) => read_Mux_In(66),
read_Mux_In(124) => read_Mux_In(67),
read_Mux_In(123) => read_Mux_In(68),
read_Mux_In(122) => read_Mux_In(69),
read_Mux_In(121) => read_Mux_In(70),
read_Mux_In(120) => read_Mux_In(71),
read_Mux_In(119) => read_Mux_In(72),
read_Mux_In(118) => read_Mux_In(73),
read_Mux_In(117) => read_Mux_In(74),
read_Mux_In(116) => read_Mux_In(75),
read_Mux_In(115) => read_Mux_In(76),
read_Mux_In(114) => read_Mux_In(77),
read_Mux_In(113) => read_Mux_In(78),
read_Mux_In(112) => read_Mux_In(79),
read_Mux_In(111) => read_Mux_In(80),
read_Mux_In(110) => read_Mux_In(81),
read_Mux_In(109) => read_Mux_In(82),
read_Mux_In(108) => read_Mux_In(83),
read_Mux_In(107) => read_Mux_In(84),
read_Mux_In(106) => read_Mux_In(85),
read_Mux_In(105) => read_Mux_In(86),
read_Mux_In(104) => read_Mux_In(87),
read_Mux_In(103) => read_Mux_In(88),
read_Mux_In(102) => read_Mux_In(89),
read_Mux_In(101) => read_Mux_In(90),
read_Mux_In(100) => read_Mux_In(91),
read_Mux_In(99) => read_Mux_In(92),
read_Mux_In(98) => read_Mux_In(93),
read_Mux_In(97) => read_Mux_In(94),
read_Mux_In(96) => read_Mux_In(95),
read_Mux_In(95) => read_Mux_In(96),
read_Mux_In(94) => read_Mux_In(97),
read_Mux_In(93) => read_Mux_In(98),
read_Mux_In(92) => read_Mux_In(99),
read_Mux_In(91) => read_Mux_In(100),
read_Mux_In(90) => read_Mux_In(101),
read_Mux_In(89) => read_Mux_In(102),
read_Mux_In(88) => read_Mux_In(103),
read_Mux_In(87) => read_Mux_In(104),
read_Mux_In(86) => read_Mux_In(105),
read_Mux_In(85) => read_Mux_In(106),
read_Mux_In(84) => read_Mux_In(107),
read_Mux_In(83) => read_Mux_In(108),
read_Mux_In(82) => read_Mux_In(109),
read_Mux_In(81) => read_Mux_In(110),
read_Mux_In(80) => read_Mux_In(111),
read_Mux_In(79) => read_Mux_In(112),
read_Mux_In(78) => read_Mux_In(113),
read_Mux_In(77) => read_Mux_In(114),
read_Mux_In(76) => read_Mux_In(115),
read_Mux_In(75) => read_Mux_In(116),
read_Mux_In(74) => read_Mux_In(117),
read_Mux_In(73) => read_Mux_In(118),
read_Mux_In(72) => read_Mux_In(119),
read_Mux_In(71) => read_Mux_In(120),
read_Mux_In(70) => read_Mux_In(121),
read_Mux_In(69) => read_Mux_In(122),
read_Mux_In(68) => read_Mux_In(123),
read_Mux_In(67) => read_Mux_In(124),
read_Mux_In(66) => read_Mux_In(125),
read_Mux_In(65) => read_Mux_In(126),
read_Mux_In(64) => read_Mux_In(127),
read_Mux_In(63) => read_Mux_In(128),
read_Mux_In(62) => read_Mux_In(129),
read_Mux_In(61) => read_Mux_In(130),
read_Mux_In(60) => read_Mux_In(131),
read_Mux_In(59) => read_Mux_In(132),
read_Mux_In(58) => read_Mux_In(133),
read_Mux_In(57) => read_Mux_In(134),
read_Mux_In(56) => read_Mux_In(135),
read_Mux_In(55) => read_Mux_In(136),
read_Mux_In(54) => read_Mux_In(137),
read_Mux_In(53) => read_Mux_In(138),
read_Mux_In(52) => read_Mux_In(139),
read_Mux_In(51) => read_Mux_In(140),
read_Mux_In(50) => read_Mux_In(141),
read_Mux_In(49) => read_Mux_In(142),
read_Mux_In(48) => read_Mux_In(143),
read_Mux_In(47) => read_Mux_In(144),
read_Mux_In(46) => read_Mux_In(145),
read_Mux_In(45) => read_Mux_In(146),
read_Mux_In(44) => read_Mux_In(147),
read_Mux_In(43) => read_Mux_In(148),
read_Mux_In(42) => read_Mux_In(149),
read_Mux_In(41) => read_Mux_In(150),
read_Mux_In(40) => read_Mux_In(151),
read_Mux_In(39) => read_Mux_In(152),
read_Mux_In(38) => read_Mux_In(153),
read_Mux_In(37) => read_Mux_In(154),
read_Mux_In(36) => read_Mux_In(155),
read_Mux_In(35) => read_Mux_In(156),
read_Mux_In(34) => read_Mux_In(157),
read_Mux_In(33) => read_Mux_In(158),
read_Mux_In(32) => read_Mux_In(159),
read_Mux_In(31) => read_Mux_In(160),
read_Mux_In(30) => read_Mux_In(161),
read_Mux_In(29) => read_Mux_In(162),
read_Mux_In(28) => read_Mux_In(163),
read_Mux_In(27) => read_Mux_In(164),
read_Mux_In(26) => read_Mux_In(165),
read_Mux_In(25) => read_Mux_In(166),
read_Mux_In(24) => read_Mux_In(167),
read_Mux_In(23) => read_Mux_In(168),
read_Mux_In(22) => read_Mux_In(169),
read_Mux_In(21) => read_Mux_In(170),
read_Mux_In(20) => read_Mux_In(171),
read_Mux_In(19) => read_Mux_In(172),
read_Mux_In(18) => read_Mux_In(173),
read_Mux_In(17) => read_Mux_In(174),
read_Mux_In(16) => read_Mux_In(175),
read_Mux_In(15) => read_Mux_In(176),
read_Mux_In(14) => read_Mux_In(177),
read_Mux_In(13) => read_Mux_In(178),
read_Mux_In(12) => read_Mux_In(179),
read_Mux_In(11) => read_Mux_In(180),
read_Mux_In(10) => read_Mux_In(181),
read_Mux_In(9) => read_Mux_In(182),
read_Mux_In(8) => read_Mux_In(183),
read_Mux_In(7) => read_Mux_In(184),
read_Mux_In(6) => read_Mux_In(185),
read_Mux_In(5) => read_Mux_In(186),
read_Mux_In(4) => read_Mux_In(187),
read_Mux_In(3) => read_Mux_In(188),
read_Mux_In(2) => read_Mux_In(189),
read_Mux_In(1) => read_Mux_In(190),
read_Mux_In(0) => read_Mux_In(191),
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(9 downto 7) => s_axi_wdata(11 downto 9),
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_timer_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_timer_0_0 : entity is "system_axi_timer_0_0,axi_timer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_timer_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_timer_0_0 : entity is "axi_timer,Vivado 2016.4";
end system_axi_timer_0_0;
architecture STRUCTURE of system_axi_timer_0_0 is
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of U0 : label is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of U0 : label is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of U0 : label is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of U0 : label is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of U0 : label is "1'b1";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_axi_timer_0_0_axi_timer
port map (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pwm0 => pwm0,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
76169fa1d0983c28d72b3f5f4698d2ca
| 0.572211 | 2.519346 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/VGA Part 2/clk25MHz.vhd
| 1 | 2,032 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Pixel Clock
-- Output a 25Mhz clock for a vga controller
-- 50 Mhz to 25 Mhz
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity CLK_25MHZ is
port(CLK_IN: in std_logic;
CLK_OUT: inout std_logic);
end CLK_25MHZ;
architecture Behavioral of CLK_25MHZ is
component CLKDLL
generic (CLKDV_DIVIDE : real := 2.0;
DUTY_CYCLE_CORRECTION : Boolean := TRUE;
STARTUP_WAIT : boolean := FALSE);
port(CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
attribute CLKDV_DIVIDE : real;
attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
signal CLK_D: std_logic;
begin
CLKDLL_inst : CLKDLL
port map (
CLK0 => open, -- 0 degree DLL CLK ouptput
CLK180 => open, -- 180 degree DLL CLK output
CLK270 => open, -- 270 degree DLL CLK output
CLK2X => CLK_D, -- 2X DLL CLK output
CLK90 => open, -- 90 degree DLL CLK output
CLKDV => CLK_OUT, -- Divided DLL CLK out (CLKDV_DIVIDE)
LOCKED => open, -- DLL LOCK status output
CLKFB => CLK_D, -- DLL clock feedback
CLKIN => CLK_IN, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
end Behavioral;
|
mit
|
9391a151f46a0cef9a4916eb5ce54002
| 0.59252 | 3.812383 | false | false | false | false |
kaott/16-bit-risc
|
vhdl/pc.vhd
| 4 | 510 |
-- PC
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity pc is
port( CLK, EN, RST : in std_logic;
INPUT : in std_logic_vector(15 downto 0);
OUTPUT : out std_logic_vector(15 downto 0)
);
end pc;
architecture logic of pc is
begin
process(CLK, EN, RST)
begin
if (CLK'event and CLK = '1') and EN = '1' then
OUTPUT <= INPUT;
end if;
if (CLK'event and CLK = '1') and RST = '1' then
OUTPUT <= "0000000000000000";
end if;
end process;
end logic;
|
mit
|
8b321bf9201db81c07f5afbc4473bdca
| 0.609804 | 2.786885 | false | false | false | false |
daniw/add
|
lab1/Ex3/FIR_5x5_load_coeff/vhd/fir_2d_trn_load_tb.vhd
| 1 | 8,442 |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 27-May-11
-- Project : RT Video Lab 1: Exercise 3
-- Description: Testbench for 5x5 FIR filter with loadable coefficients
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std; use std.textio.all;
ENTITY fir_2d_trn_load_tb IS
END fir_2d_trn_load_tb;
ARCHITECTURE behavior OF fir_2d_trn_load_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fir_2d_trn_load
PORT(
ce_1 : IN std_logic;
clk_1 : IN std_logic;
coef : IN std_logic_vector(6 downto 0);
gain : IN std_logic_vector(19 downto 0);
line1 : IN std_logic_vector(7 downto 0);
line2 : IN std_logic_vector(7 downto 0);
line3 : IN std_logic_vector(7 downto 0);
line4 : IN std_logic_vector(7 downto 0);
line5 : IN std_logic_vector(7 downto 0);
load_1 : IN std_logic;
load_2 : IN std_logic;
load_3 : IN std_logic;
load_4 : IN std_logic;
load_5 : IN std_logic;
dout : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
-- clock frequency definition
constant clk_freq : real := 100.0; -- 100 MHz
constant t_clk : time := 1000.0/clk_freq * 1 ns; -- one clock period
-- define delays for timing-simulation
constant t_stim : time := 0.25*t_clk; -- delay time for stimuli application
constant t_prop : time := 0.25*t_clk; -- propagation delay for UUT mimic
-- design parameters
constant IN_DW : integer := 8;
constant OUT_DW : integer := 8;
constant COEF_DW : integer := 7;
constant TAPS : integer := 5;
-- Input signals
signal clk : std_logic := '1';
signal line1, line2, line3, line4, line5
: std_logic_vector(7 downto 0) := (others => '0');
signal load_1, load_2, load_3, load_4, load_5
: std_logic := '0';
signal coef : std_logic_vector(6 downto 0) := (others => '0');
signal gain : std_logic_vector(19 downto 0) := (others => '0');
-- Output signals
signal dout : std_logic_vector(7 downto 0) := (others => '0');
-- local testbench control signals
signal load_done : boolean := false;
signal err_cnt : natural := 0;
-- I/O files
-- Filter :
-------------------
-- 1_Identity :
-- 2_Edge :
-- 3_SobelX :
-- 4_SobelY :
-- 5_SobelXY :
-- 6_Blur :
-- 7_Smooth :
-- 8_Sharpen :
-- 9_Gaussian :
-------------------
constant mask_type : string := "9_Gaussian";
file f_stimuli_d1 : text is in "..\5x5_Filter\" & mask_type & "\Line1.txt";
file f_stimuli_d2 : text is in "..\5x5_Filter\" & mask_type & "\Line2.txt";
file f_stimuli_d3 : text is in "..\5x5_Filter\" & mask_type & "\Line3.txt";
file f_stimuli_d4 : text is in "..\5x5_Filter\" & mask_type & "\Line4.txt";
file f_stimuli_d5 : text is in "..\5x5_Filter\" & mask_type & "\Line5.txt";
file f_stimuli_c : text is in "..\5x5_Filter\" & mask_type & "\Coef.txt";
file f_stimuli_g : text is in "..\5x5_Filter\" & mask_type & "\Gain.txt";
file f_exp_resp : text is in "..\5x5_Filter\" & mask_type & "\Dout.txt";
begin
-- Instantiate the Unit Under Test
uut : fir_2d_trn_load
port map (
ce_1 => '1',
clk_1 => clk,
coef => coef,
gain => gain,
line1 => line1,
line2 => line2,
line3 => line3,
line4 => line4,
line5 => line5,
load_1 => load_1,
load_2 => load_2,
load_3 => load_3,
load_4 => load_4,
load_5 => load_5,
dout => dout
);
-- Clock generation
p_clk :process
begin
wait for t_clk/2;
clk <= not clk;
end process;
-- apply coeff/gain load stimuli to UUT
p_stim_c:process(clk)
variable inline : line;
variable char : character;
variable cnt_load : natural := 0;
begin
if clk'event and clk = '1' then
cnt_load := cnt_load + 1;
-- read gain value (only once)
if cnt_load = 1 then
readline(f_stimuli_g,inline);
for k in 19 downto 0 loop
read(inline,char);
if char = '0' then
gain(k) <= '0' after t_stim;
else
gain(k) <= '1' after t_stim;
end if;
end loop;
end if;
-- generate 5 consecutive load-pulses each 5 cycles long
if cnt_load = 100 then
load_1 <= '1' after t_stim;
elsif cnt_load = 105 then
load_1 <= '0' after t_stim;
load_2 <= '1' after t_stim;
elsif cnt_load = 110 then
load_2 <= '0' after t_stim;
load_3 <= '1' after t_stim;
elsif cnt_load = 115 then
load_3 <= '0' after t_stim;
load_4 <= '1' after t_stim;
elsif cnt_load = 120 then
load_4 <= '0' after t_stim;
load_5 <= '1' after t_stim;
elsif cnt_load = 125 then
load_5 <= '0' after t_stim;
end if;
-- apply coefficients 1 cycle too early and one cycle too long in order
-- to check correct load sequence (see COEF_SEQ.txt)
if cnt_load >= 100 then
if not endfile(f_stimuli_c) then
readline(f_stimuli_c,inline);
for k in COEF_DW-1 downto 0 loop
read(inline,char);
if char = '0' then
coef(k) <= '0' after t_stim;
else
coef(k) <= '1' after t_stim;
end if;
end loop;
else
-- start application of input data
load_done <= true;
end if;
end if;
end if;
end process;
-- apply data_in stimuli to UUT
p_stim_d:process(clk)
variable inl1, inl2, inl3, inl4, inl5 : line;
variable char1,char2,char3,char4,char5 : character;
begin
if clk'event and clk = '1' then
if load_done and (not endfile(f_stimuli_d1)) then
readline(f_stimuli_d1,inl1);
readline(f_stimuli_d2,inl2);
readline(f_stimuli_d3,inl3);
readline(f_stimuli_d4,inl4);
readline(f_stimuli_d5,inl5);
for k in IN_DW-1 downto 0 loop
read(inl1,char1);
read(inl2,char2);
read(inl3,char3);
read(inl4,char4);
read(inl5,char5);
if char1 = '0' then line1(k) <= '0' after t_stim;
else line1(k) <= '1' after t_stim; end if;
if char2 = '0' then line2(k) <= '0' after t_stim;
else line2(k) <= '1' after t_stim; end if;
if char3 = '0' then line3(k) <= '0' after t_stim;
else line3(k) <= '1' after t_stim; end if;
if char4 = '0' then line4(k) <= '0' after t_stim;
else line4(k) <= '1' after t_stim; end if;
if char5 = '0' then line5(k) <= '0' after t_stim;
else line5(k) <= '1' after t_stim; end if;
end loop;
elsif endfile(f_stimuli_d1) then
-- end of simulation
assert false report "******** End of simulation : " &
"Total Number of Mismatches detected = " &
integer'image(err_cnt) &
" ********"
severity failure;
end if;
end if;
end process;
-- compare expected with actual responses
p_check: process(clk)
variable line_exp, line_act : line;
variable str_exp, str_act : string(OUT_DW downto 1);
begin
if clk'event and clk = '1' then
if load_done then
-- read expected value from file
readline(f_exp_resp, line_exp);
for k in OUT_DW-1 downto 0 loop
-- get all bits in actual output
if dout(k) = '0' then
str_act(k+1) := '0';
elsif dout(k) = '1' then
str_act(k+1) := '1';
end if;
write(line_act, str_act(k+1));
-- get all bits in expected output
read(line_exp, str_exp(k+1));
end loop;
-- compare actual and expected output vector
if not (str_exp = str_act) then
assert false
report "expected: " & str_exp & " actual: " & str_act severity note;
err_cnt <= err_cnt + 1;
end if;
end if;
end if;
end process;
end;
|
gpl-2.0
|
d0f7fe07034355880d7d54e2e65c4964
| 0.518479 | 3.324931 | false | false | false | false |
jeffmagina/ECE368
|
Project1/FETCH/ProgramCounter.vhd
| 1 | 1,190 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:13:08 03/04/2015
-- Design Name:
-- Module Name: ProgramCounter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ProgramCounter is
Port (CLK : in STD_LOGIC;
NEW_PC: in STD_LOGIC_VECTOR (9 downto 0):= (OTHERS => '0');
PC_OUT: out STD_LOGIC_VECTOR (9 downto 0):= (OTHERS => '0'));
end ProgramCounter;
architecture Behavioral of ProgramCounter is
begin
Process(CLK)
begin
if(CLK'event and CLK='1') then
PC_OUT <= NEW_PC;
end if;
end Process;
end Behavioral;
|
mit
|
ceb3a28652e191eb82f5d7db80716803
| 0.589076 | 3.876221 | false | false | false | false |
jeffmagina/ECE368
|
Project1/OPERAND_ACCESS/op_access.vhd
| 1 | 4,233 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:38:02 03/25/2015
-- Design Name:
-- Module Name: op_access - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity op_access is
Port( CLK : IN STD_LOGIC;
OPCODE_IN : IN STD_LOGIC_VECTOR (3 downto 0);
REG_A : IN STD_LOGIC_VECTOR (3 downto 0);
IMMEDIATE : IN STD_LOGIC_VECTOR (7 downto 0);
W_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
OP1_MUX_SEL : IN STD_LOGIC_VECTOR(1 downto 0);
OP2_MUX_SEL : IN STD_LOGIC_VECTOR(1 downto 0);
BANK_R_W : IN STD_LOGIC;
BANK_ENB : IN STD_LOGIC;
BANK_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
DEC_REG_ADDR : OUT STD_LOGIC_VECTOR (3 downto 0);
OPCODE_OUT : OUT STD_LOGIC_VECTOR (3 downto 0);
EX_FWD_IN : IN STD_LOGIC_VECTOR(15 downto 0);
EX_FWD_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
WB_FWD_IN : IN STD_LOGIC_VECTOR(15 downto 0);
WB_FWD_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
OP1_OUT : OUT STD_LOGIC_VECTOR (15 downto 0);
OP2_OUT : OUT STD_LOGIC_VECTOR (15 downto 0)
);
end op_access;
architecture Structural of op_access is
signal REG_BANK_A_OUT, REG_BANK_B_OUT, IMM_DATA, REG_A_IN, REG_B_IN, REG_B : STD_LOGIC_VECTOR (15 downto 0);
signal OPCODE_DEL_OUT, write_address, EX_FWD_ADDR_REG, WB_FWD_ADDR_REG : STD_LOGIC_VECTOR (3 downto 0);
signal DETECT_SEL1, DETECT_SEL2 : STD_LOGIC_VECTOR(1 downto 0);
begin
IMM_DATA <= x"00" & IMMEDIATE;
REG_B <= X"000" & IMMEDIATE(3 downto 0);
RegBank: entity work.register_bank
Port Map( CLK => CLK,
ADDR_A => REG_A,
ADDR_B => IMMEDIATE(7 downto 4),
W_ADDR => write_address,
R_W => BANK_R_W,
ENB => BANK_ENB,
DATA_IN => BANK_DATA,
REG_A => REG_BANK_A_OUT,
REG_B => REG_BANK_B_OUT);
OPCODE: entity work.Register_FE_4
Port Map( CLK => CLK,
D => OPCODE_IN,
ENB => '1',
Q => OPCODE_OUT);
REGA: entity work.Register_FE_4
Port Map( CLK => CLK,
D => REG_A,
ENB => '1',
Q => DEC_REG_ADDR);
-- OPCODEDEL: entity work.Register_FE_4
-- Port Map( CLK => CLK,
-- D => OPCODE_DEL_OUT,
-- ENB => '1',
-- Q => OPCODE_OUT);
FWD_DETECT1: entity work.Forwarding_unit
PORT MAP( OPA_REG => REG_A,
EX_FWD_REG => EX_FWD_ADDR_REG,
WB_FWD_REG => WB_FWD_ADDR_REG,
FWD_SEL => OP1_MUX_SEL,
FWD_MUX_SEL => DETECT_SEL1);
OP1_MUX: entity work.MUX4to1
PORT MAP( SEL => DETECT_SEL1,
DATA_0 => REG_BANK_A_OUT,
DATA_1 => x"0000",
DATA_2 => WB_FWD_IN,
DATA_3 => EX_FWD_IN,
OUTPUT => REG_A_IN);
OP1: entity work.Register_FE_16
Port Map( CLK => CLK,
D => REG_A_IN,
ENB => '1',
Q => OP1_OUT);
FWD_DETECT2: entity work.Forwarding_unit
PORT MAP( OPA_REG => IMMEDIATE(3 downto 0),
EX_FWD_REG => EX_FWD_ADDR_REG,
WB_FWD_REG => WB_FWD_ADDR_REG,
FWD_SEL => OP2_MUX_SEL,
FWD_MUX_SEL => DETECT_SEL2);
OP2_MUX: entity work.mux4to1
Port Map( SEL => DETECT_SEL2,
DATA_0 => REG_BANK_B_OUT,
DATA_1 => IMM_DATA,
DATA_2 => WB_FWD_IN,
DATA_3 => EX_FWD_IN,
OUTPUT => REG_B_IN);
OP2: entity work.Register_FE_16
Port Map( CLK => CLK,
D => REG_B_IN,
ENB => '1',
Q => OP2_OUT);
U5: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => W_ADDR,
Q => write_address);
U6: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => EX_FWD_ADDR,
Q => EX_FWD_ADDR_REG);
U7: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => WB_FWD_ADDR,
Q => WB_FWD_ADDR_REG);
end Structural;
|
mit
|
99f0c1477d1ed99743f7e83af2824c04
| 0.516655 | 2.941626 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/keycode_to_ascii.vhd
| 4 | 6,904 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Keycode to ascii
---------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity KEYCODE_TO_ASCII is
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
KEYCODE : in STD_LOGIC_VECTOR(7 downto 0);
VALID_SIGNAL : in STD_LOGIC;
-- Output
COMPLETE: out STD_LOGIC; -- Hit Key sucessfully
ASCII : out STD_LOGIC_VECTOR(7 downto 0)--;
--KEYBOARD_OUT : out STD_LOGIC_VECTOR(7 downto 0);
--WRITE_KEYBOARD: out STD_LOGIC;
);
end KEYCODE_TO_ASCII;
architecture dataflow of KEYCODE_TO_ASCII is
type StateType is (init, idle, READ_BREAKCODE, READ_EXTENDED, READ_KEYCODE,SEND_COMPLETE);--,SEND_CAPS);
signal STATE : StateType := init;
signal ASCII_LOWER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ASCII_UPPER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
shared variable Shift_Key : boolean := false;
shared variable Caps_Lock : boolean := false;
shared variable Extended : boolean := false;
begin
with KEYCODE select
ASCII_LOWER <=
-- Alphabet
x"61" when x"1C", -- a
x"62" when x"32", -- b
x"63" when x"21", -- c
x"64" when x"23", -- d
x"65" when x"24", -- e
x"66" when x"2B", -- f
x"67" when x"34", -- g
x"68" when x"33", -- h
x"69" when x"43", -- i
x"6A" when x"3B", -- j
x"6B" when x"42", -- k
x"6C" when x"4B", -- l
x"6D" when x"3A", -- m
x"6E" when x"31", -- n
x"6F" when x"44", -- o
x"70" when x"4D", -- p
x"71" when x"15", -- q
x"72" when x"2D", -- r
x"73" when x"1B", -- s
x"74" when x"2C", -- t
x"75" when x"3C", -- u
x"76" when x"2A", -- v
x"77" when x"1D", -- w
x"78" when x"22", -- x
x"79" when x"35", -- y
x"7A" when x"1A", -- z
--Top Row
x"60" when x"0E", -- `
x"31" when x"16", -- 1
x"32" when x"1E", -- 2
x"33" when x"26", -- 3
x"34" when x"25", -- 4
x"35" when x"2E", -- 5
x"36" when x"36", -- 6
x"37" when x"3D", -- 7
x"38" when x"3E", -- 8
x"39" when x"46", -- 9
x"30" when x"45", -- 0
x"2D" when x"4E", -- -
x"3D" when x"55", -- =
--Enter Corner
x"5B" when x"54", -- [
x"5D" when x"5B", -- ]
x"5C" when x"5D", -- \
x"3B" when x"4C", -- ;
x"27" when x"52", -- '
x"2C" when x"41", -- ,
x"2E" when x"49", -- .
x"2F" when x"4A", -- /
--Function Keys -- Based on the IBM PC Codes
x"1B" when x"76", -- Esc (Escape)
x"3B" when x"05", -- F1
x"3C" when x"06", -- F2
x"3D" when x"04", -- F3
x"3E" when x"0C", -- F4
x"3F" when x"03", -- F5
x"40" when x"0B", -- F6
x"41" when x"83", -- F7
x"42" when x"0A", -- F8
x"43" when x"01", -- F9
x"44" when x"09", -- F10
x"85" when x"78", -- F11
x"86" when x"07", -- F12
x"09" when x"0D", -- Tab (Horizontal Tab)
x"0D" when x"5A", -- Enter (Carriage Return)
--special characters -- taking up unneaded ascii codes for simplicity
x"05" when x"58", -- Caps Lock
x"06" when x"14", -- Ctrl
x"07" when x"11", -- Alt
x"08" when x"66", -- Back Space
x"20" when x"29", -- Space
--Direction Keys -- taking up unneaded ascii codes for simplicity
x"01" when x"75", -- Up
x"02" when x"72", -- Down
x"03" when x"6B", -- Left
x"04" when x"74", -- Right
--Unknown input
x"00" when OTHERS; -- Null
with KEYCODE select
ASCII_UPPER <=
-- Alphabet
x"41" when x"1C", -- A
x"42" when x"32", -- B
x"43" when x"21", -- C
x"44" when x"23", -- D
x"45" when x"24", -- E
x"46" when x"2B", -- F
x"47" when x"34", -- G
x"48" when x"33", -- H
x"49" when x"43", -- I
x"4A" when x"3B", -- J
x"4B" when x"42", -- K
x"4C" when x"4B", -- L
x"4D" when x"3A", -- M
x"4E" when x"31", -- N
x"4F" when x"44", -- O
x"50" when x"4D", -- P
x"51" when x"15", -- Q
x"52" when x"2D", -- R
x"53" when x"1B", -- S
x"54" when x"2C", -- T
x"55" when x"3C", -- U
x"56" when x"2A", -- V
x"57" when x"1D", -- W
x"58" when x"22", -- X
x"59" when x"35", -- Y
x"5A" when x"1A", -- Z
-- Special Upper case Characters (top left to bottom right)
-- Top Row
x"7E" when x"0E", -- ~
x"21" when x"16", -- !
x"40" when x"1E", -- @
x"23" when x"26", -- #
x"24" when x"25", -- $
x"25" when x"2E", -- %
x"5E" when x"36", -- ^
x"26" when x"3D", -- &
x"2A" when x"3E", -- *
x"28" when x"46", -- (
x"29" when x"45", -- )
x"5F" when x"4E", -- _
x"2B" when x"55", -- +
-- Enter Corner
x"7B" when x"54", -- {
x"7D" when x"5B", -- }
x"7C" when x"5D", -- |
x"3A" when x"4C", -- :
x"22" when x"52", -- "
x"3C" when x"41", -- <
x"3E" when x"49", -- >
x"3F" when x"4A", -- ?
-- Unknown Key
x"00" when OTHERS; -- Null
PROCESS (KEYCODE,CLK, RST)
BEGIN
if (RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '0' ) then
case STATE is
when init =>
ascii <= (OTHERS => '0');
COMPLETE <= '0';
state <= idle;
when idle =>
COMPLETE <= '0';
if VALID_SIGNAL= '1' then
Extended := false;
if keycode=x"E0" then
state <= READ_EXTENDED;
-- A Key was pressed
elsif keycode=x"F0" then
state <= READ_KEYCODE;
else
-- No break code yet
state <= idle;
end if;
-- Shift Key was press (on)
if (keycode=x"12" or keycode=x"59") then
Shift_Key := true;
end if;
end if;
when READ_EXTENDED =>
if VALID_SIGNAL= '1' then
Extended := true;
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_BREAKCODE =>
if VALID_SIGNAL= '1' then
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_KEYCODE =>
if VALID_SIGNAL= '1' then
-- Shift Key was released (off)
if (keycode=x"12" or keycode=x"59") then
Shift_Key := false;
elsif (keycode=x"58") then
if (Caps_Lock = false) then
Caps_Lock := true;
else
Caps_Lock := false;
end if;
--state <= SEND_CAPS;
else
if (Shift_Key = true or Caps_Lock = true) then
ascii <= ASCII_UPPER;
else
ascii <= ASCII_LOWER;
end if;
end if;
state <= SEND_COMPLETE;
end if;
when SEND_COMPLETE =>
COMPLETE <= '1';
state <= idle;
--when SEND_CAPS =>
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
|
mit
|
28c3f2a7efecdf42cf12876a1985c019
| 0.510718 | 2.398888 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_auto_cc_1/system_auto_cc_1_sim_netlist.vhdl
| 1 | 180,107 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:42:53 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_cc_1/system_auto_cc_1_sim_netlist.vhdl
-- Design : system_auto_cc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_1_xpm_cdc_single is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of system_auto_cc_1_xpm_cdc_single : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_1_xpm_cdc_single : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of system_auto_cc_1_xpm_cdc_single : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of system_auto_cc_1_xpm_cdc_single : entity is 0;
attribute VERSION : integer;
attribute VERSION of system_auto_cc_1_xpm_cdc_single : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of system_auto_cc_1_xpm_cdc_single : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of system_auto_cc_1_xpm_cdc_single : entity is "SINGLE";
end system_auto_cc_1_xpm_cdc_single;
architecture STRUCTURE of system_auto_cc_1_xpm_cdc_single is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__10\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__10\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__10\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__10\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__10\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__10\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__10\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__10\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__10\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__10\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__11\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__11\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__11\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__11\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__11\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__11\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__11\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__11\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__11\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__11\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__12\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__12\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__12\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__12\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__12\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__12\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__12\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__12\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__12\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__12\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__13\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__13\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__13\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__13\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__13\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__13\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__13\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__13\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__13\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__13\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__14\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__14\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__14\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__14\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__14\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__14\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__14\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__14\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__14\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__14\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__15\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__15\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__15\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__15\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__15\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__15\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__15\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__15\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__15\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__15\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__16\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__16\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__16\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__16\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__16\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__16\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__16\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__16\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__16\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__16\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__17\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__17\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__17\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__17\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__17\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__17\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__17\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__17\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__17\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__17\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_single__18\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_single__18\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_single__18\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_single__18\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \system_auto_cc_1_xpm_cdc_single__18\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_single__18\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_single__18\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_single__18\ : entity is "SINGLE";
end \system_auto_cc_1_xpm_cdc_single__18\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_single__18\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_1_xpm_cdc_handshake is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 13 downto 0 );
src_send : in STD_LOGIC;
src_rcv : out STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC_VECTOR ( 13 downto 0 );
dest_req : out STD_LOGIC;
dest_ack : in STD_LOGIC
);
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of system_auto_cc_1_xpm_cdc_handshake : entity is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of system_auto_cc_1_xpm_cdc_handshake : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_1_xpm_cdc_handshake : entity is "xpm_cdc_handshake";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of system_auto_cc_1_xpm_cdc_handshake : entity is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of system_auto_cc_1_xpm_cdc_handshake : entity is 2;
attribute VERSION : integer;
attribute VERSION of system_auto_cc_1_xpm_cdc_handshake : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of system_auto_cc_1_xpm_cdc_handshake : entity is 14;
attribute XPM_MODULE : string;
attribute XPM_MODULE of system_auto_cc_1_xpm_cdc_handshake : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of system_auto_cc_1_xpm_cdc_handshake : entity is "HANDSHAKE";
end system_auto_cc_1_xpm_cdc_handshake;
architecture STRUCTURE of system_auto_cc_1_xpm_cdc_handshake is
signal dest_hsdata_en : STD_LOGIC;
attribute DIRECT_ENABLE : boolean;
attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
signal dest_hsdata_ff : STD_LOGIC_VECTOR ( 13 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
signal \^dest_req\ : STD_LOGIC;
signal dest_req_nxt : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal src_hsdata_ff : STD_LOGIC_VECTOR ( 13 downto 0 );
signal src_sendd_ff : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[10]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[10]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[11]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[11]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[12]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[12]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[13]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[13]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[1]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[1]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[2]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[2]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[3]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[3]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[4]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[4]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[5]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[5]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[6]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[6]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[7]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[7]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[8]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[8]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[9]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[9]\ : label is "HANDSHAKE";
attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
begin
dest_out(13 downto 0) <= dest_hsdata_ff(13 downto 0);
dest_req <= \^dest_req\;
dest_hsdata_en_inferred_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => dest_req_nxt,
I1 => \^dest_req\,
O => dest_hsdata_en
);
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(0),
Q => dest_hsdata_ff(0),
R => '0'
);
\dest_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(10),
Q => dest_hsdata_ff(10),
R => '0'
);
\dest_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(11),
Q => dest_hsdata_ff(11),
R => '0'
);
\dest_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(12),
Q => dest_hsdata_ff(12),
R => '0'
);
\dest_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(13),
Q => dest_hsdata_ff(13),
R => '0'
);
\dest_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(1),
Q => dest_hsdata_ff(1),
R => '0'
);
\dest_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(2),
Q => dest_hsdata_ff(2),
R => '0'
);
\dest_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(3),
Q => dest_hsdata_ff(3),
R => '0'
);
\dest_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(4),
Q => dest_hsdata_ff(4),
R => '0'
);
\dest_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(5),
Q => dest_hsdata_ff(5),
R => '0'
);
\dest_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(6),
Q => dest_hsdata_ff(6),
R => '0'
);
\dest_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(7),
Q => dest_hsdata_ff(7),
R => '0'
);
\dest_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(8),
Q => dest_hsdata_ff(8),
R => '0'
);
\dest_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(9),
Q => dest_hsdata_ff(9),
R => '0'
);
dest_req_ff_reg: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => dest_req_nxt,
Q => \^dest_req\,
R => '0'
);
\src_hsdata_ff[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => src_sendd_ff,
O => p_0_in
);
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(0),
Q => src_hsdata_ff(0),
R => '0'
);
\src_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(10),
Q => src_hsdata_ff(10),
R => '0'
);
\src_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(11),
Q => src_hsdata_ff(11),
R => '0'
);
\src_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(12),
Q => src_hsdata_ff(12),
R => '0'
);
\src_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(13),
Q => src_hsdata_ff(13),
R => '0'
);
\src_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(1),
Q => src_hsdata_ff(1),
R => '0'
);
\src_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(2),
Q => src_hsdata_ff(2),
R => '0'
);
\src_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(3),
Q => src_hsdata_ff(3),
R => '0'
);
\src_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(4),
Q => src_hsdata_ff(4),
R => '0'
);
\src_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(5),
Q => src_hsdata_ff(5),
R => '0'
);
\src_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(6),
Q => src_hsdata_ff(6),
R => '0'
);
\src_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(7),
Q => src_hsdata_ff(7),
R => '0'
);
\src_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(8),
Q => src_hsdata_ff(8),
R => '0'
);
\src_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(9),
Q => src_hsdata_ff(9),
R => '0'
);
src_sendd_ff_reg: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_send,
Q => src_sendd_ff,
R => '0'
);
xpm_cdc_single_dest2src_inst: entity work.\system_auto_cc_1_xpm_cdc_single__11\
port map (
dest_clk => src_clk,
dest_out => src_rcv,
src_clk => dest_clk,
src_in => dest_ack
);
xpm_cdc_single_src2dest_inst: entity work.\system_auto_cc_1_xpm_cdc_single__10\
port map (
dest_clk => dest_clk,
dest_out => dest_req_nxt,
src_clk => src_clk,
src_in => src_sendd_ff
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 35 downto 0 );
src_send : in STD_LOGIC;
src_rcv : out STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC_VECTOR ( 35 downto 0 );
dest_req : out STD_LOGIC;
dest_ack : in STD_LOGIC
);
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is "xpm_cdc_handshake";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is 2;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is 36;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ : entity is "HANDSHAKE";
end \system_auto_cc_1_xpm_cdc_handshake__parameterized0\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_handshake__parameterized0\ is
signal dest_hsdata_en : STD_LOGIC;
attribute DIRECT_ENABLE : boolean;
attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
signal dest_hsdata_ff : STD_LOGIC_VECTOR ( 35 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
signal \^dest_req\ : STD_LOGIC;
signal dest_req_nxt : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal src_hsdata_ff : STD_LOGIC_VECTOR ( 35 downto 0 );
signal src_sendd_ff : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[10]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[10]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[11]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[11]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[12]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[12]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[13]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[13]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[14]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[14]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[15]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[15]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[16]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[16]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[17]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[17]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[18]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[18]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[19]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[19]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[1]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[1]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[20]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[20]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[21]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[21]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[22]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[22]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[23]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[23]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[24]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[24]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[25]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[25]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[26]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[26]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[27]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[27]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[28]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[28]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[29]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[29]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[2]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[2]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[30]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[30]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[31]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[31]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[32]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[32]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[33]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[33]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[34]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[34]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[35]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[35]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[3]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[3]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[4]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[4]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[5]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[5]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[6]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[6]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[7]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[7]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[8]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[8]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[9]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[9]\ : label is "HANDSHAKE";
attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
begin
dest_out(35 downto 0) <= dest_hsdata_ff(35 downto 0);
dest_req <= \^dest_req\;
dest_hsdata_en_inferred_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => dest_req_nxt,
I1 => \^dest_req\,
O => dest_hsdata_en
);
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(0),
Q => dest_hsdata_ff(0),
R => '0'
);
\dest_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(10),
Q => dest_hsdata_ff(10),
R => '0'
);
\dest_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(11),
Q => dest_hsdata_ff(11),
R => '0'
);
\dest_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(12),
Q => dest_hsdata_ff(12),
R => '0'
);
\dest_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(13),
Q => dest_hsdata_ff(13),
R => '0'
);
\dest_hsdata_ff_reg[14]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(14),
Q => dest_hsdata_ff(14),
R => '0'
);
\dest_hsdata_ff_reg[15]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(15),
Q => dest_hsdata_ff(15),
R => '0'
);
\dest_hsdata_ff_reg[16]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(16),
Q => dest_hsdata_ff(16),
R => '0'
);
\dest_hsdata_ff_reg[17]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(17),
Q => dest_hsdata_ff(17),
R => '0'
);
\dest_hsdata_ff_reg[18]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(18),
Q => dest_hsdata_ff(18),
R => '0'
);
\dest_hsdata_ff_reg[19]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(19),
Q => dest_hsdata_ff(19),
R => '0'
);
\dest_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(1),
Q => dest_hsdata_ff(1),
R => '0'
);
\dest_hsdata_ff_reg[20]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(20),
Q => dest_hsdata_ff(20),
R => '0'
);
\dest_hsdata_ff_reg[21]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(21),
Q => dest_hsdata_ff(21),
R => '0'
);
\dest_hsdata_ff_reg[22]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(22),
Q => dest_hsdata_ff(22),
R => '0'
);
\dest_hsdata_ff_reg[23]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(23),
Q => dest_hsdata_ff(23),
R => '0'
);
\dest_hsdata_ff_reg[24]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(24),
Q => dest_hsdata_ff(24),
R => '0'
);
\dest_hsdata_ff_reg[25]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(25),
Q => dest_hsdata_ff(25),
R => '0'
);
\dest_hsdata_ff_reg[26]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(26),
Q => dest_hsdata_ff(26),
R => '0'
);
\dest_hsdata_ff_reg[27]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(27),
Q => dest_hsdata_ff(27),
R => '0'
);
\dest_hsdata_ff_reg[28]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(28),
Q => dest_hsdata_ff(28),
R => '0'
);
\dest_hsdata_ff_reg[29]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(29),
Q => dest_hsdata_ff(29),
R => '0'
);
\dest_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(2),
Q => dest_hsdata_ff(2),
R => '0'
);
\dest_hsdata_ff_reg[30]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(30),
Q => dest_hsdata_ff(30),
R => '0'
);
\dest_hsdata_ff_reg[31]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(31),
Q => dest_hsdata_ff(31),
R => '0'
);
\dest_hsdata_ff_reg[32]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(32),
Q => dest_hsdata_ff(32),
R => '0'
);
\dest_hsdata_ff_reg[33]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(33),
Q => dest_hsdata_ff(33),
R => '0'
);
\dest_hsdata_ff_reg[34]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(34),
Q => dest_hsdata_ff(34),
R => '0'
);
\dest_hsdata_ff_reg[35]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(35),
Q => dest_hsdata_ff(35),
R => '0'
);
\dest_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(3),
Q => dest_hsdata_ff(3),
R => '0'
);
\dest_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(4),
Q => dest_hsdata_ff(4),
R => '0'
);
\dest_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(5),
Q => dest_hsdata_ff(5),
R => '0'
);
\dest_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(6),
Q => dest_hsdata_ff(6),
R => '0'
);
\dest_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(7),
Q => dest_hsdata_ff(7),
R => '0'
);
\dest_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(8),
Q => dest_hsdata_ff(8),
R => '0'
);
\dest_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(9),
Q => dest_hsdata_ff(9),
R => '0'
);
dest_req_ff_reg: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => dest_req_nxt,
Q => \^dest_req\,
R => '0'
);
\src_hsdata_ff[35]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => src_sendd_ff,
O => p_0_in
);
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(0),
Q => src_hsdata_ff(0),
R => '0'
);
\src_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(10),
Q => src_hsdata_ff(10),
R => '0'
);
\src_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(11),
Q => src_hsdata_ff(11),
R => '0'
);
\src_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(12),
Q => src_hsdata_ff(12),
R => '0'
);
\src_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(13),
Q => src_hsdata_ff(13),
R => '0'
);
\src_hsdata_ff_reg[14]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(14),
Q => src_hsdata_ff(14),
R => '0'
);
\src_hsdata_ff_reg[15]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(15),
Q => src_hsdata_ff(15),
R => '0'
);
\src_hsdata_ff_reg[16]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(16),
Q => src_hsdata_ff(16),
R => '0'
);
\src_hsdata_ff_reg[17]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(17),
Q => src_hsdata_ff(17),
R => '0'
);
\src_hsdata_ff_reg[18]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(18),
Q => src_hsdata_ff(18),
R => '0'
);
\src_hsdata_ff_reg[19]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(19),
Q => src_hsdata_ff(19),
R => '0'
);
\src_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(1),
Q => src_hsdata_ff(1),
R => '0'
);
\src_hsdata_ff_reg[20]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(20),
Q => src_hsdata_ff(20),
R => '0'
);
\src_hsdata_ff_reg[21]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(21),
Q => src_hsdata_ff(21),
R => '0'
);
\src_hsdata_ff_reg[22]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(22),
Q => src_hsdata_ff(22),
R => '0'
);
\src_hsdata_ff_reg[23]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(23),
Q => src_hsdata_ff(23),
R => '0'
);
\src_hsdata_ff_reg[24]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(24),
Q => src_hsdata_ff(24),
R => '0'
);
\src_hsdata_ff_reg[25]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(25),
Q => src_hsdata_ff(25),
R => '0'
);
\src_hsdata_ff_reg[26]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(26),
Q => src_hsdata_ff(26),
R => '0'
);
\src_hsdata_ff_reg[27]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(27),
Q => src_hsdata_ff(27),
R => '0'
);
\src_hsdata_ff_reg[28]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(28),
Q => src_hsdata_ff(28),
R => '0'
);
\src_hsdata_ff_reg[29]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(29),
Q => src_hsdata_ff(29),
R => '0'
);
\src_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(2),
Q => src_hsdata_ff(2),
R => '0'
);
\src_hsdata_ff_reg[30]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(30),
Q => src_hsdata_ff(30),
R => '0'
);
\src_hsdata_ff_reg[31]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(31),
Q => src_hsdata_ff(31),
R => '0'
);
\src_hsdata_ff_reg[32]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(32),
Q => src_hsdata_ff(32),
R => '0'
);
\src_hsdata_ff_reg[33]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(33),
Q => src_hsdata_ff(33),
R => '0'
);
\src_hsdata_ff_reg[34]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(34),
Q => src_hsdata_ff(34),
R => '0'
);
\src_hsdata_ff_reg[35]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(35),
Q => src_hsdata_ff(35),
R => '0'
);
\src_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(3),
Q => src_hsdata_ff(3),
R => '0'
);
\src_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(4),
Q => src_hsdata_ff(4),
R => '0'
);
\src_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(5),
Q => src_hsdata_ff(5),
R => '0'
);
\src_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(6),
Q => src_hsdata_ff(6),
R => '0'
);
\src_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(7),
Q => src_hsdata_ff(7),
R => '0'
);
\src_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(8),
Q => src_hsdata_ff(8),
R => '0'
);
\src_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(9),
Q => src_hsdata_ff(9),
R => '0'
);
src_sendd_ff_reg: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_send,
Q => src_sendd_ff,
R => '0'
);
xpm_cdc_single_dest2src_inst: entity work.\system_auto_cc_1_xpm_cdc_single__15\
port map (
dest_clk => src_clk,
dest_out => src_rcv,
src_clk => dest_clk,
src_in => dest_ack
);
xpm_cdc_single_src2dest_inst: entity work.\system_auto_cc_1_xpm_cdc_single__14\
port map (
dest_clk => dest_clk,
dest_out => dest_req_nxt,
src_clk => src_clk,
src_in => src_sendd_ff
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
src_send : in STD_LOGIC;
src_rcv : out STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
dest_req : out STD_LOGIC;
dest_ack : in STD_LOGIC
);
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is "xpm_cdc_handshake";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is 2;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is 2;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ : entity is "HANDSHAKE";
end \system_auto_cc_1_xpm_cdc_handshake__parameterized1\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_handshake__parameterized1\ is
signal dest_hsdata_en : STD_LOGIC;
attribute DIRECT_ENABLE : boolean;
attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
signal dest_hsdata_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
signal \^dest_req\ : STD_LOGIC;
signal dest_req_nxt : STD_LOGIC;
signal src_hsdata_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \src_hsdata_ff[0]_i_1_n_0\ : STD_LOGIC;
signal \src_hsdata_ff[1]_i_1_n_0\ : STD_LOGIC;
signal src_sendd_ff : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[1]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[1]\ : label is "HANDSHAKE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_hsdata_ff[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \src_hsdata_ff[1]_i_1\ : label is "soft_lutpair0";
attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
begin
dest_out(1 downto 0) <= dest_hsdata_ff(1 downto 0);
dest_req <= \^dest_req\;
dest_hsdata_en_inferred_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => dest_req_nxt,
I1 => \^dest_req\,
O => dest_hsdata_en
);
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(0),
Q => dest_hsdata_ff(0),
R => '0'
);
\dest_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(1),
Q => dest_hsdata_ff(1),
R => '0'
);
dest_req_ff_reg: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => dest_req_nxt,
Q => \^dest_req\,
R => '0'
);
\src_hsdata_ff[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => src_in(0),
I1 => src_sendd_ff,
I2 => src_hsdata_ff(0),
O => \src_hsdata_ff[0]_i_1_n_0\
);
\src_hsdata_ff[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => src_in(1),
I1 => src_sendd_ff,
I2 => src_hsdata_ff(1),
O => \src_hsdata_ff[1]_i_1_n_0\
);
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => \src_hsdata_ff[0]_i_1_n_0\,
Q => src_hsdata_ff(0),
R => '0'
);
\src_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => \src_hsdata_ff[1]_i_1_n_0\,
Q => src_hsdata_ff(1),
R => '0'
);
src_sendd_ff_reg: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_send,
Q => src_sendd_ff,
R => '0'
);
xpm_cdc_single_dest2src_inst: entity work.\system_auto_cc_1_xpm_cdc_single__17\
port map (
dest_clk => src_clk,
dest_out => src_rcv,
src_clk => dest_clk,
src_in => dest_ack
);
xpm_cdc_single_src2dest_inst: entity work.\system_auto_cc_1_xpm_cdc_single__16\
port map (
dest_clk => dest_clk,
dest_out => dest_req_nxt,
src_clk => src_clk,
src_in => src_sendd_ff
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 33 downto 0 );
src_send : in STD_LOGIC;
src_rcv : out STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC_VECTOR ( 33 downto 0 );
dest_req : out STD_LOGIC;
dest_ack : in STD_LOGIC
);
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is "xpm_cdc_handshake";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is 2;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is 34;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ : entity is "HANDSHAKE";
end \system_auto_cc_1_xpm_cdc_handshake__parameterized2\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_handshake__parameterized2\ is
signal dest_hsdata_en : STD_LOGIC;
attribute DIRECT_ENABLE : boolean;
attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
signal dest_hsdata_ff : STD_LOGIC_VECTOR ( 33 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
signal \^dest_req\ : STD_LOGIC;
signal dest_req_nxt : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal src_hsdata_ff : STD_LOGIC_VECTOR ( 33 downto 0 );
signal src_sendd_ff : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[10]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[10]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[11]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[11]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[12]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[12]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[13]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[13]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[14]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[14]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[15]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[15]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[16]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[16]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[17]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[17]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[18]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[18]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[19]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[19]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[1]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[1]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[20]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[20]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[21]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[21]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[22]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[22]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[23]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[23]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[24]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[24]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[25]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[25]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[26]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[26]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[27]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[27]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[28]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[28]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[29]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[29]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[2]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[2]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[30]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[30]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[31]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[31]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[32]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[32]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[33]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[33]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[3]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[3]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[4]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[4]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[5]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[5]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[6]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[6]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[7]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[7]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[8]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[8]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[9]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[9]\ : label is "HANDSHAKE";
attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
begin
dest_out(33 downto 0) <= dest_hsdata_ff(33 downto 0);
dest_req <= \^dest_req\;
dest_hsdata_en_inferred_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => dest_req_nxt,
I1 => \^dest_req\,
O => dest_hsdata_en
);
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(0),
Q => dest_hsdata_ff(0),
R => '0'
);
\dest_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(10),
Q => dest_hsdata_ff(10),
R => '0'
);
\dest_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(11),
Q => dest_hsdata_ff(11),
R => '0'
);
\dest_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(12),
Q => dest_hsdata_ff(12),
R => '0'
);
\dest_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(13),
Q => dest_hsdata_ff(13),
R => '0'
);
\dest_hsdata_ff_reg[14]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(14),
Q => dest_hsdata_ff(14),
R => '0'
);
\dest_hsdata_ff_reg[15]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(15),
Q => dest_hsdata_ff(15),
R => '0'
);
\dest_hsdata_ff_reg[16]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(16),
Q => dest_hsdata_ff(16),
R => '0'
);
\dest_hsdata_ff_reg[17]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(17),
Q => dest_hsdata_ff(17),
R => '0'
);
\dest_hsdata_ff_reg[18]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(18),
Q => dest_hsdata_ff(18),
R => '0'
);
\dest_hsdata_ff_reg[19]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(19),
Q => dest_hsdata_ff(19),
R => '0'
);
\dest_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(1),
Q => dest_hsdata_ff(1),
R => '0'
);
\dest_hsdata_ff_reg[20]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(20),
Q => dest_hsdata_ff(20),
R => '0'
);
\dest_hsdata_ff_reg[21]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(21),
Q => dest_hsdata_ff(21),
R => '0'
);
\dest_hsdata_ff_reg[22]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(22),
Q => dest_hsdata_ff(22),
R => '0'
);
\dest_hsdata_ff_reg[23]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(23),
Q => dest_hsdata_ff(23),
R => '0'
);
\dest_hsdata_ff_reg[24]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(24),
Q => dest_hsdata_ff(24),
R => '0'
);
\dest_hsdata_ff_reg[25]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(25),
Q => dest_hsdata_ff(25),
R => '0'
);
\dest_hsdata_ff_reg[26]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(26),
Q => dest_hsdata_ff(26),
R => '0'
);
\dest_hsdata_ff_reg[27]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(27),
Q => dest_hsdata_ff(27),
R => '0'
);
\dest_hsdata_ff_reg[28]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(28),
Q => dest_hsdata_ff(28),
R => '0'
);
\dest_hsdata_ff_reg[29]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(29),
Q => dest_hsdata_ff(29),
R => '0'
);
\dest_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(2),
Q => dest_hsdata_ff(2),
R => '0'
);
\dest_hsdata_ff_reg[30]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(30),
Q => dest_hsdata_ff(30),
R => '0'
);
\dest_hsdata_ff_reg[31]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(31),
Q => dest_hsdata_ff(31),
R => '0'
);
\dest_hsdata_ff_reg[32]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(32),
Q => dest_hsdata_ff(32),
R => '0'
);
\dest_hsdata_ff_reg[33]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(33),
Q => dest_hsdata_ff(33),
R => '0'
);
\dest_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(3),
Q => dest_hsdata_ff(3),
R => '0'
);
\dest_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(4),
Q => dest_hsdata_ff(4),
R => '0'
);
\dest_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(5),
Q => dest_hsdata_ff(5),
R => '0'
);
\dest_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(6),
Q => dest_hsdata_ff(6),
R => '0'
);
\dest_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(7),
Q => dest_hsdata_ff(7),
R => '0'
);
\dest_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(8),
Q => dest_hsdata_ff(8),
R => '0'
);
\dest_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(9),
Q => dest_hsdata_ff(9),
R => '0'
);
dest_req_ff_reg: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => dest_req_nxt,
Q => \^dest_req\,
R => '0'
);
\src_hsdata_ff[33]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => src_sendd_ff,
O => p_0_in
);
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(0),
Q => src_hsdata_ff(0),
R => '0'
);
\src_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(10),
Q => src_hsdata_ff(10),
R => '0'
);
\src_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(11),
Q => src_hsdata_ff(11),
R => '0'
);
\src_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(12),
Q => src_hsdata_ff(12),
R => '0'
);
\src_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(13),
Q => src_hsdata_ff(13),
R => '0'
);
\src_hsdata_ff_reg[14]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(14),
Q => src_hsdata_ff(14),
R => '0'
);
\src_hsdata_ff_reg[15]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(15),
Q => src_hsdata_ff(15),
R => '0'
);
\src_hsdata_ff_reg[16]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(16),
Q => src_hsdata_ff(16),
R => '0'
);
\src_hsdata_ff_reg[17]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(17),
Q => src_hsdata_ff(17),
R => '0'
);
\src_hsdata_ff_reg[18]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(18),
Q => src_hsdata_ff(18),
R => '0'
);
\src_hsdata_ff_reg[19]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(19),
Q => src_hsdata_ff(19),
R => '0'
);
\src_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(1),
Q => src_hsdata_ff(1),
R => '0'
);
\src_hsdata_ff_reg[20]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(20),
Q => src_hsdata_ff(20),
R => '0'
);
\src_hsdata_ff_reg[21]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(21),
Q => src_hsdata_ff(21),
R => '0'
);
\src_hsdata_ff_reg[22]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(22),
Q => src_hsdata_ff(22),
R => '0'
);
\src_hsdata_ff_reg[23]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(23),
Q => src_hsdata_ff(23),
R => '0'
);
\src_hsdata_ff_reg[24]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(24),
Q => src_hsdata_ff(24),
R => '0'
);
\src_hsdata_ff_reg[25]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(25),
Q => src_hsdata_ff(25),
R => '0'
);
\src_hsdata_ff_reg[26]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(26),
Q => src_hsdata_ff(26),
R => '0'
);
\src_hsdata_ff_reg[27]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(27),
Q => src_hsdata_ff(27),
R => '0'
);
\src_hsdata_ff_reg[28]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(28),
Q => src_hsdata_ff(28),
R => '0'
);
\src_hsdata_ff_reg[29]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(29),
Q => src_hsdata_ff(29),
R => '0'
);
\src_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(2),
Q => src_hsdata_ff(2),
R => '0'
);
\src_hsdata_ff_reg[30]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(30),
Q => src_hsdata_ff(30),
R => '0'
);
\src_hsdata_ff_reg[31]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(31),
Q => src_hsdata_ff(31),
R => '0'
);
\src_hsdata_ff_reg[32]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(32),
Q => src_hsdata_ff(32),
R => '0'
);
\src_hsdata_ff_reg[33]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(33),
Q => src_hsdata_ff(33),
R => '0'
);
\src_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(3),
Q => src_hsdata_ff(3),
R => '0'
);
\src_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(4),
Q => src_hsdata_ff(4),
R => '0'
);
\src_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(5),
Q => src_hsdata_ff(5),
R => '0'
);
\src_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(6),
Q => src_hsdata_ff(6),
R => '0'
);
\src_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(7),
Q => src_hsdata_ff(7),
R => '0'
);
\src_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(8),
Q => src_hsdata_ff(8),
R => '0'
);
\src_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(9),
Q => src_hsdata_ff(9),
R => '0'
);
src_sendd_ff_reg: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_send,
Q => src_sendd_ff,
R => '0'
);
xpm_cdc_single_dest2src_inst: entity work.system_auto_cc_1_xpm_cdc_single
port map (
dest_clk => src_clk,
dest_out => src_rcv,
src_clk => dest_clk,
src_in => dest_ack
);
xpm_cdc_single_src2dest_inst: entity work.\system_auto_cc_1_xpm_cdc_single__18\
port map (
dest_clk => dest_clk,
dest_out => dest_req_nxt,
src_clk => src_clk,
src_in => src_sendd_ff
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 13 downto 0 );
src_send : in STD_LOGIC;
src_rcv : out STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC_VECTOR ( 13 downto 0 );
dest_req : out STD_LOGIC;
dest_ack : in STD_LOGIC
);
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is "xpm_cdc_handshake";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is 2;
attribute VERSION : integer;
attribute VERSION of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is 14;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ : entity is "HANDSHAKE";
end \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\;
architecture STRUCTURE of \system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\ is
signal dest_hsdata_en : STD_LOGIC;
attribute DIRECT_ENABLE : boolean;
attribute DIRECT_ENABLE of dest_hsdata_en : signal is std.standard.true;
signal dest_hsdata_ff : STD_LOGIC_VECTOR ( 13 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_hsdata_ff : signal is "true";
attribute xpm_cdc of dest_hsdata_ff : signal is "HANDSHAKE";
signal \^dest_req\ : STD_LOGIC;
signal dest_req_nxt : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal src_hsdata_ff : STD_LOGIC_VECTOR ( 13 downto 0 );
signal src_sendd_ff : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \dest_hsdata_ff_reg[0]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[0]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[10]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[10]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[11]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[11]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[12]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[12]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[13]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[13]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[1]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[1]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[2]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[2]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[3]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[3]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[4]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[4]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[5]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[5]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[6]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[6]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[7]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[7]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[8]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[8]\ : label is "HANDSHAKE";
attribute KEEP of \dest_hsdata_ff_reg[9]\ : label is "yes";
attribute XPM_CDC of \dest_hsdata_ff_reg[9]\ : label is "HANDSHAKE";
attribute DEST_SYNC_FF of xpm_cdc_single_dest2src_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_dest2src_inst : label is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of xpm_cdc_single_dest2src_inst : label is 0;
attribute VERSION of xpm_cdc_single_dest2src_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_dest2src_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_dest2src_inst : label is "TRUE";
attribute DEST_SYNC_FF of xpm_cdc_single_src2dest_inst : label is 2;
attribute SIM_ASSERT_CHK of xpm_cdc_single_src2dest_inst : label is 0;
attribute SRC_INPUT_REG of xpm_cdc_single_src2dest_inst : label is 0;
attribute VERSION of xpm_cdc_single_src2dest_inst : label is 0;
attribute XPM_CDC of xpm_cdc_single_src2dest_inst : label is "SINGLE";
attribute XPM_MODULE of xpm_cdc_single_src2dest_inst : label is "TRUE";
begin
dest_out(13 downto 0) <= dest_hsdata_ff(13 downto 0);
dest_req <= \^dest_req\;
dest_hsdata_en_inferred_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => dest_req_nxt,
I1 => \^dest_req\,
O => dest_hsdata_en
);
\dest_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(0),
Q => dest_hsdata_ff(0),
R => '0'
);
\dest_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(10),
Q => dest_hsdata_ff(10),
R => '0'
);
\dest_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(11),
Q => dest_hsdata_ff(11),
R => '0'
);
\dest_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(12),
Q => dest_hsdata_ff(12),
R => '0'
);
\dest_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(13),
Q => dest_hsdata_ff(13),
R => '0'
);
\dest_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(1),
Q => dest_hsdata_ff(1),
R => '0'
);
\dest_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(2),
Q => dest_hsdata_ff(2),
R => '0'
);
\dest_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(3),
Q => dest_hsdata_ff(3),
R => '0'
);
\dest_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(4),
Q => dest_hsdata_ff(4),
R => '0'
);
\dest_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(5),
Q => dest_hsdata_ff(5),
R => '0'
);
\dest_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(6),
Q => dest_hsdata_ff(6),
R => '0'
);
\dest_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(7),
Q => dest_hsdata_ff(7),
R => '0'
);
\dest_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(8),
Q => dest_hsdata_ff(8),
R => '0'
);
\dest_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => dest_hsdata_en,
D => src_hsdata_ff(9),
Q => dest_hsdata_ff(9),
R => '0'
);
dest_req_ff_reg: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => dest_req_nxt,
Q => \^dest_req\,
R => '0'
);
\src_hsdata_ff[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => src_sendd_ff,
O => p_0_in
);
\src_hsdata_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(0),
Q => src_hsdata_ff(0),
R => '0'
);
\src_hsdata_ff_reg[10]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(10),
Q => src_hsdata_ff(10),
R => '0'
);
\src_hsdata_ff_reg[11]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(11),
Q => src_hsdata_ff(11),
R => '0'
);
\src_hsdata_ff_reg[12]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(12),
Q => src_hsdata_ff(12),
R => '0'
);
\src_hsdata_ff_reg[13]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(13),
Q => src_hsdata_ff(13),
R => '0'
);
\src_hsdata_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(1),
Q => src_hsdata_ff(1),
R => '0'
);
\src_hsdata_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(2),
Q => src_hsdata_ff(2),
R => '0'
);
\src_hsdata_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(3),
Q => src_hsdata_ff(3),
R => '0'
);
\src_hsdata_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(4),
Q => src_hsdata_ff(4),
R => '0'
);
\src_hsdata_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(5),
Q => src_hsdata_ff(5),
R => '0'
);
\src_hsdata_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(6),
Q => src_hsdata_ff(6),
R => '0'
);
\src_hsdata_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(7),
Q => src_hsdata_ff(7),
R => '0'
);
\src_hsdata_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(8),
Q => src_hsdata_ff(8),
R => '0'
);
\src_hsdata_ff_reg[9]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => p_0_in,
D => src_in(9),
Q => src_hsdata_ff(9),
R => '0'
);
src_sendd_ff_reg: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_send,
Q => src_sendd_ff,
R => '0'
);
xpm_cdc_single_dest2src_inst: entity work.\system_auto_cc_1_xpm_cdc_single__13\
port map (
dest_clk => src_clk,
dest_out => src_rcv,
src_clk => dest_clk,
src_in => dest_ack
);
xpm_cdc_single_src2dest_inst: entity work.\system_auto_cc_1_xpm_cdc_single__12\
port map (
dest_clk => dest_clk,
dest_out => dest_req_nxt,
src_clk => src_clk,
src_in => src_sendd_ff
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async is
port (
dest_out : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
\out\ : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
m_axi_awready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async : entity is "axi_clock_converter_v2_1_10_lite_async";
end system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async;
architecture STRUCTURE of system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async is
signal \FSM_sequential_dest_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_dest_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[1]_i_1_n_0\ : STD_LOGIC;
signal dest_ack_i_1_n_0 : STD_LOGIC;
signal dest_ack_reg_n_0 : STD_LOGIC;
signal dest_req : STD_LOGIC;
signal dest_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_state : signal is "yes";
signal \^m_axi_awvalid\ : STD_LOGIC;
signal m_valid_i_2_n_0 : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i_2_n_0 : STD_LOGIC;
signal src_rcv : STD_LOGIC;
signal src_send_i_1_n_0 : STD_LOGIC;
signal src_send_reg_n_0 : STD_LOGIC;
signal src_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of src_state : signal is "yes";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_dest_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_dest_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[1]\ : label is "yes";
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of handshake : label is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of handshake : label is 2;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of handshake : label is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of handshake : label is 2;
attribute VERSION : integer;
attribute VERSION of handshake : label is 0;
attribute WIDTH : integer;
attribute WIDTH of handshake : label is 14;
attribute XPM_CDC : string;
attribute XPM_CDC of handshake : label is "HANDSHAKE";
attribute XPM_MODULE : string;
attribute XPM_MODULE of handshake : label is "TRUE";
begin
m_axi_awvalid <= \^m_axi_awvalid\;
s_axi_awready <= \^s_axi_awready\;
\FSM_sequential_dest_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0D5D5D5D04040404"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => m_axi_awready,
I4 => \^m_axi_awvalid\,
I5 => dest_state(0),
O => \FSM_sequential_dest_state[0]_i_1_n_0\
);
\FSM_sequential_dest_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5959595950000000"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => m_axi_awready,
I4 => \^m_axi_awvalid\,
I5 => dest_state(1),
O => \FSM_sequential_dest_state[1]_i_1_n_0\
);
\FSM_sequential_dest_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[0]_i_1_n_0\,
Q => dest_state(0),
R => m_axi_aresetn
);
\FSM_sequential_dest_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[1]_i_1_n_0\,
Q => dest_state(1),
R => m_axi_aresetn
);
\FSM_sequential_src_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5D040C"
)
port map (
I0 => src_state(1),
I1 => s_axi_awvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(0),
O => \FSM_sequential_src_state[0]_i_1_n_0\
);
\FSM_sequential_src_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5B515000"
)
port map (
I0 => src_state(1),
I1 => s_axi_awvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(1),
O => \FSM_sequential_src_state[1]_i_1_n_0\
);
\FSM_sequential_src_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[0]_i_1_n_0\,
Q => src_state(0),
R => s_axi_aresetn
);
\FSM_sequential_src_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[1]_i_1_n_0\,
Q => src_state(1),
R => s_axi_aresetn
);
dest_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"55FF550040004000"
)
port map (
I0 => dest_state(1),
I1 => \^m_axi_awvalid\,
I2 => m_axi_awready,
I3 => dest_state(0),
I4 => dest_req,
I5 => dest_ack_reg_n_0,
O => dest_ack_i_1_n_0
);
dest_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_axi_aclk,
CE => '1',
D => dest_ack_i_1_n_0,
Q => dest_ack_reg_n_0,
R => m_axi_aresetn
);
handshake: entity work.system_auto_cc_1_xpm_cdc_handshake
port map (
dest_ack => dest_ack_reg_n_0,
dest_clk => m_axi_aclk,
dest_out(13 downto 0) => dest_out(13 downto 0),
dest_req => dest_req,
src_clk => \out\,
src_in(13 downto 0) => src_in(13 downto 0),
src_rcv => src_rcv,
src_send => src_send_reg_n_0
);
m_valid_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0030F0AA"
)
port map (
I0 => dest_req,
I1 => m_axi_awready,
I2 => \^m_axi_awvalid\,
I3 => dest_state(1),
I4 => dest_state(0),
O => m_valid_i_2_n_0
);
m_valid_reg: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => m_valid_i_2_n_0,
Q => \^m_axi_awvalid\,
R => m_axi_aresetn
);
s_ready_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"5540"
)
port map (
I0 => src_state(1),
I1 => src_rcv,
I2 => src_state(0),
I3 => \^s_axi_awready\,
O => s_ready_i_2_n_0
);
s_ready_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_2_n_0,
Q => \^s_axi_awready\,
R => s_axi_aresetn
);
src_send_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5F040C"
)
port map (
I0 => src_state(1),
I1 => s_axi_awvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_send_reg_n_0,
O => src_send_i_1_n_0
);
src_send_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => src_send_i_1_n_0,
Q => src_send_reg_n_0,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized0\ is
port (
dest_out : out STD_LOGIC_VECTOR ( 35 downto 0 );
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\out\ : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
m_axi_wready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized0\ : entity is "axi_clock_converter_v2_1_10_lite_async";
end \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized0\;
architecture STRUCTURE of \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized0\ is
signal \FSM_sequential_dest_state[0]_i_1__1_n_0\ : STD_LOGIC;
signal \FSM_sequential_dest_state[1]_i_1__1_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[0]_i_1__1_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[1]_i_1__1_n_0\ : STD_LOGIC;
signal \dest_ack_i_1__1_n_0\ : STD_LOGIC;
signal dest_ack_reg_n_0 : STD_LOGIC;
signal dest_req : STD_LOGIC;
signal dest_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_state : signal is "yes";
signal \^m_axi_wvalid\ : STD_LOGIC;
signal \m_valid_i_1__0_n_0\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal \s_ready_i_1__0_n_0\ : STD_LOGIC;
signal src_rcv : STD_LOGIC;
signal \src_send_i_1__1_n_0\ : STD_LOGIC;
signal src_send_reg_n_0 : STD_LOGIC;
signal src_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of src_state : signal is "yes";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_dest_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_dest_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[1]\ : label is "yes";
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of handshake : label is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of handshake : label is 2;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of handshake : label is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of handshake : label is 2;
attribute VERSION : integer;
attribute VERSION of handshake : label is 0;
attribute WIDTH : integer;
attribute WIDTH of handshake : label is 36;
attribute XPM_CDC : string;
attribute XPM_CDC of handshake : label is "HANDSHAKE";
attribute XPM_MODULE : string;
attribute XPM_MODULE of handshake : label is "TRUE";
begin
m_axi_wvalid <= \^m_axi_wvalid\;
s_axi_wready <= \^s_axi_wready\;
\FSM_sequential_dest_state[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0D5D5D5D04040404"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => dest_state(0),
O => \FSM_sequential_dest_state[0]_i_1__1_n_0\
);
\FSM_sequential_dest_state[1]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5959595950000000"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => m_axi_wready,
I4 => \^m_axi_wvalid\,
I5 => dest_state(1),
O => \FSM_sequential_dest_state[1]_i_1__1_n_0\
);
\FSM_sequential_dest_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[0]_i_1__1_n_0\,
Q => dest_state(0),
R => m_axi_aresetn
);
\FSM_sequential_dest_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[1]_i_1__1_n_0\,
Q => dest_state(1),
R => m_axi_aresetn
);
\FSM_sequential_src_state[0]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5D040C"
)
port map (
I0 => src_state(1),
I1 => s_axi_wvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(0),
O => \FSM_sequential_src_state[0]_i_1__1_n_0\
);
\FSM_sequential_src_state[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5B515000"
)
port map (
I0 => src_state(1),
I1 => s_axi_wvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(1),
O => \FSM_sequential_src_state[1]_i_1__1_n_0\
);
\FSM_sequential_src_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[0]_i_1__1_n_0\,
Q => src_state(0),
R => s_axi_aresetn
);
\FSM_sequential_src_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[1]_i_1__1_n_0\,
Q => src_state(1),
R => s_axi_aresetn
);
\dest_ack_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FF550040004000"
)
port map (
I0 => dest_state(1),
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
I3 => dest_state(0),
I4 => dest_req,
I5 => dest_ack_reg_n_0,
O => \dest_ack_i_1__1_n_0\
);
dest_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_axi_aclk,
CE => '1',
D => \dest_ack_i_1__1_n_0\,
Q => dest_ack_reg_n_0,
R => m_axi_aresetn
);
handshake: entity work.\system_auto_cc_1_xpm_cdc_handshake__parameterized0\
port map (
dest_ack => dest_ack_reg_n_0,
dest_clk => m_axi_aclk,
dest_out(35 downto 0) => dest_out(35 downto 0),
dest_req => dest_req,
src_clk => \out\,
src_in(35 downto 0) => src_in(35 downto 0),
src_rcv => src_rcv,
src_send => src_send_reg_n_0
);
\m_valid_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0030F0AA"
)
port map (
I0 => dest_req,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => dest_state(1),
I4 => dest_state(0),
O => \m_valid_i_1__0_n_0\
);
m_valid_reg: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => \m_valid_i_1__0_n_0\,
Q => \^m_axi_wvalid\,
R => m_axi_aresetn
);
\s_ready_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5540"
)
port map (
I0 => src_state(1),
I1 => src_rcv,
I2 => src_state(0),
I3 => \^s_axi_wready\,
O => \s_ready_i_1__0_n_0\
);
s_ready_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \s_ready_i_1__0_n_0\,
Q => \^s_axi_wready\,
R => s_axi_aresetn
);
\src_send_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5F040C"
)
port map (
I0 => src_state(1),
I1 => s_axi_wvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_send_reg_n_0,
O => \src_send_i_1__1_n_0\
);
src_send_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \src_send_i_1__1_n_0\,
Q => src_send_reg_n_0,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized1\ is
port (
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized1\ : entity is "axi_clock_converter_v2_1_10_lite_async";
end \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized1\;
architecture STRUCTURE of \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized1\ is
signal \FSM_sequential_dest_state[0]_i_1__2_n_0\ : STD_LOGIC;
signal \FSM_sequential_dest_state[1]_i_1__2_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[0]_i_1__2_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[1]_i_1__2_n_0\ : STD_LOGIC;
signal \dest_ack_i_1__2_n_0\ : STD_LOGIC;
signal dest_ack_reg_n_0 : STD_LOGIC;
signal dest_req : STD_LOGIC;
signal dest_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_state : signal is "yes";
signal \^m_axi_bready\ : STD_LOGIC;
signal \m_valid_i_1__1_n_0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \s_ready_i_1__1_n_0\ : STD_LOGIC;
signal src_rcv : STD_LOGIC;
signal \src_send_i_1__2_n_0\ : STD_LOGIC;
signal src_send_reg_n_0 : STD_LOGIC;
signal src_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of src_state : signal is "yes";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_dest_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_dest_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[1]\ : label is "yes";
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of handshake : label is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of handshake : label is 2;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of handshake : label is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of handshake : label is 2;
attribute VERSION : integer;
attribute VERSION of handshake : label is 0;
attribute WIDTH : integer;
attribute WIDTH of handshake : label is 2;
attribute XPM_CDC : string;
attribute XPM_CDC of handshake : label is "HANDSHAKE";
attribute XPM_MODULE : string;
attribute XPM_MODULE of handshake : label is "TRUE";
begin
m_axi_bready <= \^m_axi_bready\;
s_axi_bvalid <= \^s_axi_bvalid\;
\FSM_sequential_dest_state[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0D5D5D5D04040404"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
I5 => dest_state(0),
O => \FSM_sequential_dest_state[0]_i_1__2_n_0\
);
\FSM_sequential_dest_state[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5959595950000000"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
I5 => dest_state(1),
O => \FSM_sequential_dest_state[1]_i_1__2_n_0\
);
\FSM_sequential_dest_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[0]_i_1__2_n_0\,
Q => dest_state(0),
R => s_axi_aresetn
);
\FSM_sequential_dest_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[1]_i_1__2_n_0\,
Q => dest_state(1),
R => s_axi_aresetn
);
\FSM_sequential_src_state[0]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5D040C"
)
port map (
I0 => src_state(1),
I1 => m_axi_bvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(0),
O => \FSM_sequential_src_state[0]_i_1__2_n_0\
);
\FSM_sequential_src_state[1]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5B515000"
)
port map (
I0 => src_state(1),
I1 => m_axi_bvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(1),
O => \FSM_sequential_src_state[1]_i_1__2_n_0\
);
\FSM_sequential_src_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[0]_i_1__2_n_0\,
Q => src_state(0),
R => m_axi_aresetn
);
\FSM_sequential_src_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[1]_i_1__2_n_0\,
Q => src_state(1),
R => m_axi_aresetn
);
\dest_ack_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FF550040004000"
)
port map (
I0 => dest_state(1),
I1 => \^s_axi_bvalid\,
I2 => s_axi_bready,
I3 => dest_state(0),
I4 => dest_req,
I5 => dest_ack_reg_n_0,
O => \dest_ack_i_1__2_n_0\
);
dest_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \dest_ack_i_1__2_n_0\,
Q => dest_ack_reg_n_0,
R => s_axi_aresetn
);
handshake: entity work.\system_auto_cc_1_xpm_cdc_handshake__parameterized1\
port map (
dest_ack => dest_ack_reg_n_0,
dest_clk => s_axi_aclk,
dest_out(1 downto 0) => s_axi_bresp(1 downto 0),
dest_req => dest_req,
src_clk => \out\,
src_in(1 downto 0) => m_axi_bresp(1 downto 0),
src_rcv => src_rcv,
src_send => src_send_reg_n_0
);
\m_valid_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0030F0AA"
)
port map (
I0 => dest_req,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => dest_state(1),
I4 => dest_state(0),
O => \m_valid_i_1__1_n_0\
);
m_valid_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \m_valid_i_1__1_n_0\,
Q => \^s_axi_bvalid\,
R => s_axi_aresetn
);
\s_ready_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5540"
)
port map (
I0 => src_state(1),
I1 => src_rcv,
I2 => src_state(0),
I3 => \^m_axi_bready\,
O => \s_ready_i_1__1_n_0\
);
s_ready_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \s_ready_i_1__1_n_0\,
Q => \^m_axi_bready\,
R => m_axi_aresetn
);
\src_send_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5F040C"
)
port map (
I0 => src_state(1),
I1 => m_axi_bvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_send_reg_n_0,
O => \src_send_i_1__2_n_0\
);
src_send_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \src_send_i_1__2_n_0\,
Q => src_send_reg_n_0,
R => m_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized2\ is
port (
dest_out : out STD_LOGIC_VECTOR ( 33 downto 0 );
m_axi_rready : out STD_LOGIC;
src_send_reg_0 : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
dest_ack_reg_0 : out STD_LOGIC;
\out\ : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized2\ : entity is "axi_clock_converter_v2_1_10_lite_async";
end \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized2\;
architecture STRUCTURE of \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized2\ is
signal \FSM_sequential_dest_state[0]_i_1__3_n_0\ : STD_LOGIC;
signal \FSM_sequential_dest_state[1]_i_1__3_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[0]_i_1__3_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[1]_i_1__3_n_0\ : STD_LOGIC;
signal \dest_ack_i_1__3_n_0\ : STD_LOGIC;
signal \^dest_ack_reg_0\ : STD_LOGIC;
signal dest_ack_reg_n_0 : STD_LOGIC;
signal dest_req : STD_LOGIC;
signal dest_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_state : signal is "yes";
signal \^m_axi_rready\ : STD_LOGIC;
signal \m_valid_i_1__2_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_1__2_n_0\ : STD_LOGIC;
signal src_rcv : STD_LOGIC;
signal \src_send_i_1__3_n_0\ : STD_LOGIC;
signal \^src_send_reg_0\ : STD_LOGIC;
signal src_send_reg_n_0 : STD_LOGIC;
signal src_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of src_state : signal is "yes";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_dest_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_dest_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[1]\ : label is "yes";
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of handshake : label is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of handshake : label is 2;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of handshake : label is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of handshake : label is 2;
attribute VERSION : integer;
attribute VERSION of handshake : label is 0;
attribute WIDTH : integer;
attribute WIDTH of handshake : label is 34;
attribute XPM_CDC : string;
attribute XPM_CDC of handshake : label is "HANDSHAKE";
attribute XPM_MODULE : string;
attribute XPM_MODULE of handshake : label is "TRUE";
begin
dest_ack_reg_0 <= \^dest_ack_reg_0\;
m_axi_rready <= \^m_axi_rready\;
s_axi_rvalid <= \^s_axi_rvalid\;
src_send_reg_0 <= \^src_send_reg_0\;
\FSM_sequential_dest_state[0]_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0D5D5D5D04040404"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => dest_state(0),
O => \FSM_sequential_dest_state[0]_i_1__3_n_0\
);
\FSM_sequential_dest_state[1]_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"5959595950000000"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => dest_state(1),
O => \FSM_sequential_dest_state[1]_i_1__3_n_0\
);
\FSM_sequential_dest_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[0]_i_1__3_n_0\,
Q => dest_state(0),
R => \^dest_ack_reg_0\
);
\FSM_sequential_dest_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[1]_i_1__3_n_0\,
Q => dest_state(1),
R => \^dest_ack_reg_0\
);
\FSM_sequential_src_state[0]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5D040C"
)
port map (
I0 => src_state(1),
I1 => m_axi_rvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(0),
O => \FSM_sequential_src_state[0]_i_1__3_n_0\
);
\FSM_sequential_src_state[1]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"5B515000"
)
port map (
I0 => src_state(1),
I1 => m_axi_rvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(1),
O => \FSM_sequential_src_state[1]_i_1__3_n_0\
);
\FSM_sequential_src_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[0]_i_1__3_n_0\,
Q => src_state(0),
R => \^src_send_reg_0\
);
\FSM_sequential_src_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[1]_i_1__3_n_0\,
Q => src_state(1),
R => \^src_send_reg_0\
);
\dest_ack_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FF550040004000"
)
port map (
I0 => dest_state(1),
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => dest_state(0),
I4 => dest_req,
I5 => dest_ack_reg_n_0,
O => \dest_ack_i_1__3_n_0\
);
dest_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \dest_ack_i_1__3_n_0\,
Q => dest_ack_reg_n_0,
R => \^dest_ack_reg_0\
);
handshake: entity work.\system_auto_cc_1_xpm_cdc_handshake__parameterized2\
port map (
dest_ack => dest_ack_reg_n_0,
dest_clk => s_axi_aclk,
dest_out(33 downto 0) => dest_out(33 downto 0),
dest_req => dest_req,
src_clk => \out\,
src_in(33 downto 0) => src_in(33 downto 0),
src_rcv => src_rcv,
src_send => src_send_reg_n_0
);
\m_valid_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0030F0AA"
)
port map (
I0 => dest_req,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => dest_state(1),
I4 => dest_state(0),
O => \m_valid_i_1__2_n_0\
);
\m_valid_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => m_axi_aresetn,
O => \^src_send_reg_0\
);
m_valid_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \m_valid_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \^dest_ack_reg_0\
);
\s_ready_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5540"
)
port map (
I0 => src_state(1),
I1 => src_rcv,
I2 => src_state(0),
I3 => \^m_axi_rready\,
O => \s_ready_i_1__2_n_0\
);
\s_ready_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^dest_ack_reg_0\
);
s_ready_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \s_ready_i_1__2_n_0\,
Q => \^m_axi_rready\,
R => \^src_send_reg_0\
);
\src_send_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5F040C"
)
port map (
I0 => src_state(1),
I1 => m_axi_rvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_send_reg_n_0,
O => \src_send_i_1__3_n_0\
);
src_send_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \src_send_i_1__3_n_0\,
Q => src_send_reg_n_0,
R => \^src_send_reg_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__xdcDup__1\ is
port (
dest_out : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\out\ : in STD_LOGIC;
src_in : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__xdcDup__1\ : entity is "axi_clock_converter_v2_1_10_lite_async";
end \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__xdcDup__1\;
architecture STRUCTURE of \system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__xdcDup__1\ is
signal \FSM_sequential_dest_state[0]_i_1__0_n_0\ : STD_LOGIC;
signal \FSM_sequential_dest_state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[0]_i_1__0_n_0\ : STD_LOGIC;
signal \FSM_sequential_src_state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \dest_ack_i_1__0_n_0\ : STD_LOGIC;
signal dest_ack_reg_n_0 : STD_LOGIC;
signal dest_req : STD_LOGIC;
signal dest_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of dest_state : signal is "yes";
signal \^m_axi_arvalid\ : STD_LOGIC;
signal m_valid_i_1_n_0 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i_1_n_0 : STD_LOGIC;
signal src_rcv : STD_LOGIC;
signal \src_send_i_1__0_n_0\ : STD_LOGIC;
signal src_send_reg_n_0 : STD_LOGIC;
signal src_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of src_state : signal is "yes";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_dest_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_dest_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_src_state_reg[1]\ : label is "yes";
attribute DEST_EXT_HSK : integer;
attribute DEST_EXT_HSK of handshake : label is 1;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of handshake : label is 2;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of handshake : label is 0;
attribute SRC_SYNC_FF : integer;
attribute SRC_SYNC_FF of handshake : label is 2;
attribute VERSION : integer;
attribute VERSION of handshake : label is 0;
attribute WIDTH : integer;
attribute WIDTH of handshake : label is 14;
attribute XPM_CDC : string;
attribute XPM_CDC of handshake : label is "HANDSHAKE";
attribute XPM_MODULE : string;
attribute XPM_MODULE of handshake : label is "TRUE";
begin
m_axi_arvalid <= \^m_axi_arvalid\;
s_axi_arready <= \^s_axi_arready\;
\FSM_sequential_dest_state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0D5D5D5D04040404"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => m_axi_arready,
I4 => \^m_axi_arvalid\,
I5 => dest_state(0),
O => \FSM_sequential_dest_state[0]_i_1__0_n_0\
);
\FSM_sequential_dest_state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5959595950000000"
)
port map (
I0 => dest_state(1),
I1 => dest_req,
I2 => dest_state(0),
I3 => m_axi_arready,
I4 => \^m_axi_arvalid\,
I5 => dest_state(1),
O => \FSM_sequential_dest_state[1]_i_1__0_n_0\
);
\FSM_sequential_dest_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[0]_i_1__0_n_0\,
Q => dest_state(0),
R => m_axi_aresetn
);
\FSM_sequential_dest_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => \FSM_sequential_dest_state[1]_i_1__0_n_0\,
Q => dest_state(1),
R => m_axi_aresetn
);
\FSM_sequential_src_state[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5D040C"
)
port map (
I0 => src_state(1),
I1 => s_axi_arvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(0),
O => \FSM_sequential_src_state[0]_i_1__0_n_0\
);
\FSM_sequential_src_state[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5B515000"
)
port map (
I0 => src_state(1),
I1 => s_axi_arvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_state(1),
O => \FSM_sequential_src_state[1]_i_1__0_n_0\
);
\FSM_sequential_src_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[0]_i_1__0_n_0\,
Q => src_state(0),
R => s_axi_aresetn
);
\FSM_sequential_src_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \FSM_sequential_src_state[1]_i_1__0_n_0\,
Q => src_state(1),
R => s_axi_aresetn
);
\dest_ack_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FF550040004000"
)
port map (
I0 => dest_state(1),
I1 => \^m_axi_arvalid\,
I2 => m_axi_arready,
I3 => dest_state(0),
I4 => dest_req,
I5 => dest_ack_reg_n_0,
O => \dest_ack_i_1__0_n_0\
);
dest_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_axi_aclk,
CE => '1',
D => \dest_ack_i_1__0_n_0\,
Q => dest_ack_reg_n_0,
R => m_axi_aresetn
);
handshake: entity work.\system_auto_cc_1_xpm_cdc_handshake__xdcDup__1\
port map (
dest_ack => dest_ack_reg_n_0,
dest_clk => m_axi_aclk,
dest_out(13 downto 0) => dest_out(13 downto 0),
dest_req => dest_req,
src_clk => \out\,
src_in(13 downto 0) => src_in(13 downto 0),
src_rcv => src_rcv,
src_send => src_send_reg_n_0
);
m_valid_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0030F0AA"
)
port map (
I0 => dest_req,
I1 => m_axi_arready,
I2 => \^m_axi_arvalid\,
I3 => dest_state(1),
I4 => dest_state(0),
O => m_valid_i_1_n_0
);
m_valid_reg: unisim.vcomponents.FDRE
port map (
C => m_axi_aclk,
CE => '1',
D => m_valid_i_1_n_0,
Q => \^m_axi_arvalid\,
R => m_axi_aresetn
);
s_ready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"5540"
)
port map (
I0 => src_state(1),
I1 => src_rcv,
I2 => src_state(0),
I3 => \^s_axi_arready\,
O => s_ready_i_1_n_0
);
s_ready_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_1_n_0,
Q => \^s_axi_arready\,
R => s_axi_aresetn
);
\src_send_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F5F040C"
)
port map (
I0 => src_state(1),
I1 => s_axi_arvalid,
I2 => src_state(0),
I3 => src_rcv,
I4 => src_send_reg_n_0,
O => \src_send_i_1__0_n_0\
);
src_send_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \src_send_i_1__0_n_0\,
Q => src_send_reg_n_0,
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 14;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 14;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 14;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 14;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 14;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 14;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 34;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 36;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 34;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 34;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 36;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 36;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "axi_clock_converter_v2_1_10_axi_clock_converter";
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "1'b1";
end system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter;
architecture STRUCTURE of system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter is
signal \<const0>\ : STD_LOGIC;
signal \gen_clock_conv.gen_async_lite_conv.r_handshake_n_35\ : STD_LOGIC;
signal \gen_clock_conv.gen_async_lite_conv.r_handshake_n_37\ : STD_LOGIC;
begin
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_clock_conv.gen_async_lite_conv.ar_handshake\: entity work.\system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__xdcDup__1\
port map (
dest_out(13 downto 11) => m_axi_arprot(2 downto 0),
dest_out(10 downto 0) => m_axi_araddr(10 downto 0),
m_axi_aclk => m_axi_aclk,
m_axi_aresetn => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_35\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\ => s_axi_aclk,
s_axi_aresetn => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_37\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
src_in(13 downto 11) => s_axi_arprot(2 downto 0),
src_in(10 downto 0) => s_axi_araddr(10 downto 0)
);
\gen_clock_conv.gen_async_lite_conv.aw_handshake\: entity work.system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async
port map (
dest_out(13 downto 11) => m_axi_awprot(2 downto 0),
dest_out(10 downto 0) => m_axi_awaddr(10 downto 0),
m_axi_aclk => m_axi_aclk,
m_axi_aresetn => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_35\,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\ => s_axi_aclk,
s_axi_aresetn => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_37\,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
src_in(13 downto 11) => s_axi_awprot(2 downto 0),
src_in(10 downto 0) => s_axi_awaddr(10 downto 0)
);
\gen_clock_conv.gen_async_lite_conv.b_handshake\: entity work.\system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized1\
port map (
m_axi_aresetn => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_35\,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\ => m_axi_aclk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_37\,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid
);
\gen_clock_conv.gen_async_lite_conv.r_handshake\: entity work.\system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized2\
port map (
dest_ack_reg_0 => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_37\,
dest_out(33 downto 32) => s_axi_rresp(1 downto 0),
dest_out(31 downto 0) => s_axi_rdata(31 downto 0),
m_axi_aresetn => m_axi_aresetn,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => m_axi_aclk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
src_in(33 downto 32) => m_axi_rresp(1 downto 0),
src_in(31 downto 0) => m_axi_rdata(31 downto 0),
src_send_reg_0 => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_35\
);
\gen_clock_conv.gen_async_lite_conv.w_handshake\: entity work.\system_auto_cc_1_axi_clock_converter_v2_1_10_lite_async__parameterized0\
port map (
dest_out(35 downto 32) => m_axi_wstrb(3 downto 0),
dest_out(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_aclk => m_axi_aclk,
m_axi_aresetn => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_35\,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\ => s_axi_aclk,
s_axi_aresetn => \gen_clock_conv.gen_async_lite_conv.r_handshake_n_37\,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
src_in(35 downto 32) => s_axi_wstrb(3 downto 0),
src_in(31 downto 0) => s_axi_wdata(31 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_cc_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_cc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_cc_1 : entity is "system_auto_cc_1,axi_clock_converter_v2_1_10_axi_clock_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_cc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_cc_1 : entity is "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4";
end system_auto_cc_1;
architecture STRUCTURE of system_auto_cc_1 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of inst : label is 3;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of inst : label is 11;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of inst : label is 3;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of inst : label is 0;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of inst : label is 3;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of inst : label is 0;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of inst : label is 14;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of inst : label is 0;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of inst : label is 3;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of inst : label is 0;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of inst : label is 3;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of inst : label is 0;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of inst : label is 0;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of inst : label is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of inst : label is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of inst : label is 0;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of inst : label is 0;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of inst : label is 0;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of inst : label is 3;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of inst : label is 0;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of inst : label is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of inst : label is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of inst : label is 14;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of inst : label is 3;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of inst : label is 11;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of inst : label is 3;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of inst : label is 0;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of inst : label is 3;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of inst : label is 0;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of inst : label is 14;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of inst : label is 0;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of inst : label is 3;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of inst : label is 0;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of inst : label is 3;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of inst : label is 0;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of inst : label is 0;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of inst : label is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of inst : label is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of inst : label is 0;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of inst : label is 0;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of inst : label is 0;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of inst : label is 3;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of inst : label is 0;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of inst : label is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of inst : label is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of inst : label is 14;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 11;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of inst : label is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of inst : label is 0;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of inst : label is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of inst : label is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of inst : label is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of inst : label is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of inst : label is 2;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of inst : label is 14;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of inst : label is 14;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of inst : label is 2;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of inst : label is 34;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of inst : label is 36;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of inst : label is 2;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of inst : label is 32;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of inst : label is 34;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of inst : label is 0;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of inst : label is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of inst : label is 0;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of inst : label is 0;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of inst : label is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of inst : label is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of inst : label is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of inst : label is 34;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of inst : label is 4;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of inst : label is 32;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of inst : label is 36;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of inst : label is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of inst : label is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of inst : label is 0;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of inst : label is 0;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of inst : label is 4;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of inst : label is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of inst : label is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of inst : label is 36;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of inst : label is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of inst : label is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of inst : label is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of inst : label is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of inst : label is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of inst : label is "1'b1";
begin
inst: entity work.system_auto_cc_1_axi_clock_converter_v2_1_10_axi_clock_converter
port map (
m_axi_aclk => m_axi_aclk,
m_axi_araddr(10 downto 0) => m_axi_araddr(10 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_aresetn => m_axi_aresetn,
m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(10 downto 0) => m_axi_awaddr(10 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => '0',
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(0) => '0',
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(10 downto 0),
s_axi_arburst(1 downto 0) => B"01",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(10 downto 0),
s_axi_awburst(1 downto 0) => B"01",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_inst_s_axi_rlast_UNCONNECTED,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => '1',
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
0fbf4967ae7a60dcc6f5c83b12472534
| 0.610204 | 2.957859 | false | false | false | false |
daniw/add
|
lab1/Ex1/FIR_1x5_const_coeff/vhd/fir_1d_dir.vhd
| 1 | 2,970 |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 05-Apr-11, 21-Mar-14
-- Project : RT Video Lab 1: Exercise 1
-- Description: 5-tap FIR filter in direct form
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity fir_1d_dir is
generic
(IN_DW : integer := 8; -- Input word width
OUT_DW : integer := 19; -- Output word width
COEF_DW : integer := 7; -- coefficient word width
TAPS : integer := 5; -- # of taps + 1 input register
DELAY : integer := 8); -- output delay line
-- (to adapt latency to system architecture)
port
(ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector(COEF_DW-1 downto 0);
din : in std_logic_vector(IN_DW-1 downto 0);
out_data : out std_logic_vector(OUT_DW-1 downto 0)
);
end fir_1d_dir;
architecture Behavioral of fir_1d_dir is
-- type declarations
type STAGE_TYPE is array(TAPS-1 downto 0) of signed(IN_DW-1 downto 0);
type DELAY_TYPE is array(DELAY downto 0) of signed(IN_DW-1 downto 0);
type COEFF_TYPE is array(TAPS-1 downto 0) of signed(COEF_DW-1 downto 0);
-- signal declarations (init values for simulation only!!!)
signal stage : STAGE_TYPE := (others => (others => '0'));
signal del_line : DELAY_TYPE := (others => (others => '0'));
-- constant declarations
constant C_coef : COEFF_TYPE := (to_signed(2, COEF_DW), -- b4
to_signed(4, COEF_DW), -- b3
to_signed(8, COEF_DW), -- b2
to_signed(4, COEF_DW), -- b1
to_signed(2, COEF_DW)); -- b0
constant C_ext : signed(OUT_DW-IN_DW-COEF_DW-1 downto 0) := (others => '0');
begin
-- sequential process (without reset, because SysGen uses FIR-Compiler without
-- reset signal)
p0_FIR : process(clk_1)
variable v_filt : signed(OUT_DW-1 downto 0);
begin
if rising_edge(clk_1) then
if ce_1 = '1' then
-- input delay line
del_line(DELAY) <= signed(din);
del_line(DELAY-1 downto 0) <= del_line(DELAY downto 1);
-- shift tap delay line
stage(0) <= del_line(0);
stage(TAPS-1 downto 1) <= stage(TAPS-2 downto 0);
-- compute filter taps
v_filt := (C_ext & stage(0)) * C_coef(0);
for k in 1 to TAPS-1 loop
v_filt := ((C_ext & stage(k)) * C_coef(k)) + v_filt;
end loop;
-- output register
out_data <= std_logic_vector(v_filt);
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
30d24f8efa4affa17ecb90b42b9781d5
| 0.511448 | 3.639706 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/SRAM16Bytes.vhd
| 1 | 7,838 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/21/2015 12:17:45 PM
-- Design Name:
-- Module Name: SRAM16Bytes - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SRAM16Bytes is
Port
(
Load : in BIT;
Sel : in BIT;
Address : in BIT_VECTOR(3 downto 0);
InData : in BIT_VECTOR(7 downto 0);
OutData : out BIT_VECTOR(7 downto 0)
);
end SRAM16Bytes;
architecture Behavioral of SRAM16Bytes is
component Register8Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end component Register8Bit;
component Decoder2to4 is
Port
(
A : in BIT_VECTOR(1 downto 0); -- 2-Bit Memory Address (Input)
X : out BIT_VECTOR(3 downto 0) -- 4-Bit Address Lines (Output)
);
end component Decoder2to4;
signal AccessLines1: BIT_VECTOR(3 downto 0);
signal AccessLines2: BIT_VECTOR(3 downto 0);
signal OutData1 : BIT_VECTOR(7 downto 0);
signal OutData2 : BIT_VECTOR(7 downto 0);
signal OutData3 : BIT_VECTOR(7 downto 0);
signal OutData4 : BIT_VECTOR(7 downto 0);
signal OutData5 : BIT_VECTOR(7 downto 0);
signal OutData6 : BIT_VECTOR(7 downto 0);
signal OutData7 : BIT_VECTOR(7 downto 0);
signal OutData8 : BIT_VECTOR(7 downto 0);
signal OutData9 : BIT_VECTOR(7 downto 0);
signal OutData10 : BIT_VECTOR(7 downto 0);
signal OutData11 : BIT_VECTOR(7 downto 0);
signal OutData12 : BIT_VECTOR(7 downto 0);
signal OutData13 : BIT_VECTOR(7 downto 0);
signal OutData14 : BIT_VECTOR(7 downto 0);
signal OutData15 : BIT_VECTOR(7 downto 0);
signal OutData16 : BIT_VECTOR(7 downto 0);
signal LoadLine1: BIT;
signal LoadLine2: BIT;
signal LoadLine3: BIT;
signal LoadLine4: BIT;
signal LoadLine5: BIT;
signal LoadLine6: BIT;
signal LoadLine7: BIT;
signal LoadLine8: BIT;
signal LoadLine9: BIT;
signal LoadLine10: BIT;
signal LoadLine11: BIT;
signal LoadLine12: BIT;
signal LoadLine13: BIT;
signal LoadLine14: BIT;
signal LoadLine15: BIT;
signal LoadLine16: BIT;
signal SelectLine1: BIT;
signal SelectLine2: BIT;
signal SelectLine3: BIT;
signal SelectLine4: BIT;
signal SelectLine5: BIT;
signal SelectLine6: BIT;
signal SelectLine7: BIT;
signal SelectLine8: BIT;
signal SelectLine9: BIT;
signal SelectLine10: BIT;
signal SelectLine11: BIT;
signal SelectLine12: BIT;
signal SelectLine13: BIT;
signal SelectLine14: BIT;
signal SelectLine15: BIT;
signal SelectLine16: BIT;
begin
-- The 16 8-bit SRAM memory cells are logically arranged in a 4x4 matrix
-- 1 2 3 4
-- 5 6 7 8
-- 9 10 11 12
-- 13 14 14 16
-- The 1st decoder takes the lower 2 bits of the address and provides the row offset into the 4x4 matrix
Decoder1: Decoder2to4 port map(Address(1 downto 0), AccessLines1);
-- The 2nd decoder takes the upper 2 bits of the address and provides the column offset into the 4x4 matrix
Decoder2: Decoder2to4 port map(Address(3 downto 2), AccessLines2);
-- Create a dedicate Load-Line for every 8-bit SRAM memory cell
LoadLine1 <= Load and AccessLines1(0) and AccessLines2(0);
LoadLine2 <= Load and AccessLines1(1) and AccessLines2(0);
LoadLine3 <= Load and AccessLines1(2) and AccessLines2(0);
LoadLine4 <= Load and AccessLines1(3) and AccessLines2(0);
LoadLine5 <= Load and AccessLines1(0) and AccessLines2(1);
LoadLine6 <= Load and AccessLines1(1) and AccessLines2(1);
LoadLine7 <= Load and AccessLines1(2) and AccessLines2(1);
LoadLine8 <= Load and AccessLines1(3) and AccessLines2(1);
LoadLine9 <= Load and AccessLines1(0) and AccessLines2(2);
LoadLine10 <= Load and AccessLines1(1) and AccessLines2(2);
LoadLine11 <= Load and AccessLines1(2) and AccessLines2(2);
LoadLine12 <= Load and AccessLines1(3) and AccessLines2(2);
LoadLine13 <= Load and AccessLines1(0) and AccessLines2(3);
LoadLine14 <= Load and AccessLines1(1) and AccessLines2(3);
LoadLine15 <= Load and AccessLines1(2) and AccessLines2(3);
LoadLine16 <= Load and AccessLines1(3) and AccessLines2(3);
-- Create a dedicate Select-Line for every 8-bit SRAM memory cell
SelectLine1 <= Sel and AccessLines1(0) and AccessLines2(0);
SelectLine2 <= Sel and AccessLines1(1) and AccessLines2(0);
SelectLine3 <= Sel and AccessLines1(2) and AccessLines2(0);
SelectLine4 <= Sel and AccessLines1(3) and AccessLines2(0);
SelectLine5 <= Sel and AccessLines1(0) and AccessLines2(1);
SelectLine6 <= Sel and AccessLines1(1) and AccessLines2(1);
SelectLine7 <= Sel and AccessLines1(2) and AccessLines2(1);
SelectLine8 <= Sel and AccessLines1(3) and AccessLines2(1);
SelectLine9 <= Sel and AccessLines1(0) and AccessLines2(2);
SelectLine10 <= Sel and AccessLines1(1) and AccessLines2(2);
SelectLine11 <= Sel and AccessLines1(2) and AccessLines2(2);
SelectLine12 <= Sel and AccessLines1(3) and AccessLines2(2);
SelectLine13 <= Sel and AccessLines1(0) and AccessLines2(3);
SelectLine14 <= Sel and AccessLines1(1) and AccessLines2(3);
SelectLine15 <= Sel and AccessLines1(2) and AccessLines2(3);
SelectLine16 <= Sel and AccessLines1(3) and AccessLines2(3);
-- Instantiate the 16 individual 8-bit SRAM memory cells
ram1: Register8Bit port map (LoadLine1, SelectLine1, InData, OutData1);
ram2: Register8Bit port map (LoadLine2, SelectLine2, InData, OutData2);
ram3: Register8Bit port map (LoadLine3, SelectLine3, InData, OutData3);
ram4: Register8Bit port map (LoadLine4, SelectLine4, InData, OutData4);
ram5: Register8Bit port map (LoadLine5, SelectLine5, InData, OutData5);
ram6: Register8Bit port map (LoadLine6, SelectLine6, InData, OutData6);
ram7: Register8Bit port map (LoadLine7, SelectLine7, InData, OutData7);
ram8: Register8Bit port map (LoadLine8, SelectLine8, InData, OutData8);
ram9: Register8Bit port map (LoadLine9, SelectLine9, InData, OutData9);
ram10: Register8Bit port map (LoadLine10, SelectLine10, InData, OutData10);
ram11: Register8Bit port map (LoadLine11, SelectLine11, InData, OutData11);
ram12: Register8Bit port map (LoadLine12, SelectLine12, InData, OutData12);
ram13: Register8Bit port map (LoadLine13, SelectLine13, InData, OutData13);
ram14: Register8Bit port map (LoadLine14, SelectLine14, InData, OutData14);
ram15: Register8Bit port map (LoadLine15, SelectLine15, InData, OutData15);
ram16: Register8Bit port map (LoadLine16, SelectLine16, InData, OutData16);
-- Return the read data
OutData <= OutData1 or
OutData2 or
OutData3 or
OutData4 or
OutData5 or
OutData6 or
OutData7 or
OutData8 or
OutData9 or
OutData10 or
OutData11 or
OutData12 or
OutData13 or
OutData14 or
OutData15 or
OutData16;
end Behavioral;
|
mit
|
408f9d6115bff605cc761fb08074f404
| 0.667007 | 3.815969 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_auto_us_0/system_auto_us_0_sim_netlist.vhdl
| 1 | 931,063 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:43:59 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_us_0/system_auto_us_0_sim_netlist.vhdl
-- Design : system_auto_us_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer is
port (
first_word : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
use_wrap_buffer : out STD_LOGIC;
first_mi_word_q : out STD_LOGIC;
wrap_buffer_available : out STD_LOGIC;
first_word_reg_0 : out STD_LOGIC;
first_word_reg_1 : out STD_LOGIC;
\sel_first_word__0\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\current_word_1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
first_word_reg_2 : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 127 downto 0 );
use_wrap_buffer_reg_0 : in STD_LOGIC;
\out\ : in STD_LOGIC;
wrap_buffer_available_reg_0 : in STD_LOGIC;
\m_payload_i_reg[130]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_cmd_valid : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_13_in : in STD_LOGIC;
\m_payload_i_reg[129]\ : in STD_LOGIC_VECTOR ( 129 downto 0 );
\last_beat__6\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\pre_next_word_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer : entity is "axi_dwidth_converter_v2_1_11_r_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^use_rtl_length.length_counter_q_reg[0]_0\ : STD_LOGIC;
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word\ : STD_LOGIC;
signal \length_counter__0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_7_in : STD_LOGIC;
signal rresp_wrap_buffer : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^use_wrap_buffer\ : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal \wrap_buffer_available_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_3\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_2__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_3\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[5]_i_3\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[6]_i_4\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_4\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_7 : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \s_axi_rresp[0]_INST_0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair67";
begin
E(0) <= \^e\(0);
\USE_RTL_LENGTH.length_counter_q_reg[0]_0\ <= \^use_rtl_length.length_counter_q_reg[0]_0\;
first_mi_word_q <= \^first_mi_word_q\;
first_word <= \^first_word\;
use_wrap_buffer <= \^use_wrap_buffer\;
wrap_buffer_available <= \^wrap_buffer_available\;
\M_AXI_RDATA_I[127]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000000"
)
port map (
I0 => \^first_mi_word_q\,
I1 => Q(8),
I2 => \^use_wrap_buffer\,
I3 => rd_cmd_valid,
I4 => mr_rvalid,
O => p_7_in
);
\M_AXI_RDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(0),
Q => \s_axi_rdata[31]\(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(100),
Q => \s_axi_rdata[31]\(100),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(101),
Q => \s_axi_rdata[31]\(101),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(102),
Q => \s_axi_rdata[31]\(102),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(103),
Q => \s_axi_rdata[31]\(103),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(104),
Q => \s_axi_rdata[31]\(104),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(105),
Q => \s_axi_rdata[31]\(105),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(106),
Q => \s_axi_rdata[31]\(106),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(107),
Q => \s_axi_rdata[31]\(107),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(108),
Q => \s_axi_rdata[31]\(108),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(109),
Q => \s_axi_rdata[31]\(109),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(10),
Q => \s_axi_rdata[31]\(10),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(110),
Q => \s_axi_rdata[31]\(110),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(111),
Q => \s_axi_rdata[31]\(111),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(112),
Q => \s_axi_rdata[31]\(112),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(113),
Q => \s_axi_rdata[31]\(113),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(114),
Q => \s_axi_rdata[31]\(114),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(115),
Q => \s_axi_rdata[31]\(115),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(116),
Q => \s_axi_rdata[31]\(116),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(117),
Q => \s_axi_rdata[31]\(117),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(118),
Q => \s_axi_rdata[31]\(118),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(119),
Q => \s_axi_rdata[31]\(119),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(11),
Q => \s_axi_rdata[31]\(11),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(120),
Q => \s_axi_rdata[31]\(120),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(121),
Q => \s_axi_rdata[31]\(121),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(122),
Q => \s_axi_rdata[31]\(122),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(123),
Q => \s_axi_rdata[31]\(123),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(124),
Q => \s_axi_rdata[31]\(124),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(125),
Q => \s_axi_rdata[31]\(125),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(126),
Q => \s_axi_rdata[31]\(126),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(127),
Q => \s_axi_rdata[31]\(127),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(12),
Q => \s_axi_rdata[31]\(12),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(13),
Q => \s_axi_rdata[31]\(13),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(14),
Q => \s_axi_rdata[31]\(14),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(15),
Q => \s_axi_rdata[31]\(15),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(16),
Q => \s_axi_rdata[31]\(16),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(17),
Q => \s_axi_rdata[31]\(17),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(18),
Q => \s_axi_rdata[31]\(18),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(19),
Q => \s_axi_rdata[31]\(19),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(1),
Q => \s_axi_rdata[31]\(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(20),
Q => \s_axi_rdata[31]\(20),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(21),
Q => \s_axi_rdata[31]\(21),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(22),
Q => \s_axi_rdata[31]\(22),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(23),
Q => \s_axi_rdata[31]\(23),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(24),
Q => \s_axi_rdata[31]\(24),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(25),
Q => \s_axi_rdata[31]\(25),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(26),
Q => \s_axi_rdata[31]\(26),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(27),
Q => \s_axi_rdata[31]\(27),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(28),
Q => \s_axi_rdata[31]\(28),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(29),
Q => \s_axi_rdata[31]\(29),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(2),
Q => \s_axi_rdata[31]\(2),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(30),
Q => \s_axi_rdata[31]\(30),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(31),
Q => \s_axi_rdata[31]\(31),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(32),
Q => \s_axi_rdata[31]\(32),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(33),
Q => \s_axi_rdata[31]\(33),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(34),
Q => \s_axi_rdata[31]\(34),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(35),
Q => \s_axi_rdata[31]\(35),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(36),
Q => \s_axi_rdata[31]\(36),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(37),
Q => \s_axi_rdata[31]\(37),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(38),
Q => \s_axi_rdata[31]\(38),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(39),
Q => \s_axi_rdata[31]\(39),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(3),
Q => \s_axi_rdata[31]\(3),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(40),
Q => \s_axi_rdata[31]\(40),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(41),
Q => \s_axi_rdata[31]\(41),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(42),
Q => \s_axi_rdata[31]\(42),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(43),
Q => \s_axi_rdata[31]\(43),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(44),
Q => \s_axi_rdata[31]\(44),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(45),
Q => \s_axi_rdata[31]\(45),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(46),
Q => \s_axi_rdata[31]\(46),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(47),
Q => \s_axi_rdata[31]\(47),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(48),
Q => \s_axi_rdata[31]\(48),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(49),
Q => \s_axi_rdata[31]\(49),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(4),
Q => \s_axi_rdata[31]\(4),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(50),
Q => \s_axi_rdata[31]\(50),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(51),
Q => \s_axi_rdata[31]\(51),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(52),
Q => \s_axi_rdata[31]\(52),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(53),
Q => \s_axi_rdata[31]\(53),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(54),
Q => \s_axi_rdata[31]\(54),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(55),
Q => \s_axi_rdata[31]\(55),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(56),
Q => \s_axi_rdata[31]\(56),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(57),
Q => \s_axi_rdata[31]\(57),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(58),
Q => \s_axi_rdata[31]\(58),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(59),
Q => \s_axi_rdata[31]\(59),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(5),
Q => \s_axi_rdata[31]\(5),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(60),
Q => \s_axi_rdata[31]\(60),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(61),
Q => \s_axi_rdata[31]\(61),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(62),
Q => \s_axi_rdata[31]\(62),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(63),
Q => \s_axi_rdata[31]\(63),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(64),
Q => \s_axi_rdata[31]\(64),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(65),
Q => \s_axi_rdata[31]\(65),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(66),
Q => \s_axi_rdata[31]\(66),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(67),
Q => \s_axi_rdata[31]\(67),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(68),
Q => \s_axi_rdata[31]\(68),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(69),
Q => \s_axi_rdata[31]\(69),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(6),
Q => \s_axi_rdata[31]\(6),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(70),
Q => \s_axi_rdata[31]\(70),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(71),
Q => \s_axi_rdata[31]\(71),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(72),
Q => \s_axi_rdata[31]\(72),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(73),
Q => \s_axi_rdata[31]\(73),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(74),
Q => \s_axi_rdata[31]\(74),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(75),
Q => \s_axi_rdata[31]\(75),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(76),
Q => \s_axi_rdata[31]\(76),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(77),
Q => \s_axi_rdata[31]\(77),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(78),
Q => \s_axi_rdata[31]\(78),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(79),
Q => \s_axi_rdata[31]\(79),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(7),
Q => \s_axi_rdata[31]\(7),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(80),
Q => \s_axi_rdata[31]\(80),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(81),
Q => \s_axi_rdata[31]\(81),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(82),
Q => \s_axi_rdata[31]\(82),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(83),
Q => \s_axi_rdata[31]\(83),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(84),
Q => \s_axi_rdata[31]\(84),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(85),
Q => \s_axi_rdata[31]\(85),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(86),
Q => \s_axi_rdata[31]\(86),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(87),
Q => \s_axi_rdata[31]\(87),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(88),
Q => \s_axi_rdata[31]\(88),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(89),
Q => \s_axi_rdata[31]\(89),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(8),
Q => \s_axi_rdata[31]\(8),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(90),
Q => \s_axi_rdata[31]\(90),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(91),
Q => \s_axi_rdata[31]\(91),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(92),
Q => \s_axi_rdata[31]\(92),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(93),
Q => \s_axi_rdata[31]\(93),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(94),
Q => \s_axi_rdata[31]\(94),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(95),
Q => \s_axi_rdata[31]\(95),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(96),
Q => \s_axi_rdata[31]\(96),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(97),
Q => \s_axi_rdata[31]\(97),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(98),
Q => \s_axi_rdata[31]\(98),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(99),
Q => \s_axi_rdata[31]\(99),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\M_AXI_RDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(9),
Q => \s_axi_rdata[31]\(9),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => '1',
D => \m_payload_i_reg[130]\,
Q => \^first_mi_word_q\,
S => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FFFFFFF70000000"
)
port map (
I0 => \^first_mi_word_q\,
I1 => Q(0),
I2 => m_valid_i_reg,
I3 => s_axi_rready,
I4 => p_13_in,
I5 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAAA2AAA2AAAEAAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => m_valid_i_reg,
I2 => s_axi_rready,
I3 => p_13_in,
I4 => \length_counter__0\(0),
I5 => \length_counter__0\(1),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
O => \length_counter__0\(0)
);
\USE_RTL_LENGTH.length_counter_q[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
O => \length_counter__0\(1)
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CACCCCCCC5CCC3CC"
)
port map (
I0 => Q(2),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
I3 => m_valid_i_reg,
I4 => \^first_mi_word_q\,
I5 => \USE_RTL_LENGTH.length_counter_q[2]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => Q(0),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I3 => \^first_mi_word_q\,
I4 => Q(1),
O => \USE_RTL_LENGTH.length_counter_q[2]_i_2__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAAA2AAA2AAAEAAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => m_valid_i_reg,
I2 => s_axi_rready,
I3 => p_13_in,
I4 => \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\,
I5 => \length_counter__0\(3),
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFE2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I1 => \^first_mi_word_q\,
I2 => Q(2),
I3 => \USE_RTL_LENGTH.length_counter_q[2]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
O => \length_counter__0\(3)
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CACCCCCCC5CCC3CC"
)
port map (
I0 => Q(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
I3 => m_valid_i_reg,
I4 => \^first_mi_word_q\,
I5 => \USE_RTL_LENGTH.length_counter_q[4]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFAEEEEFFFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[2]_i_2__0_n_0\,
I1 => Q(2),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => \^first_mi_word_q\,
I5 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_2__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAAA2AAA2AAAEAAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => m_valid_i_reg,
I2 => s_axi_rready,
I3 => p_13_in,
I4 => \USE_RTL_LENGTH.length_counter_q[5]_i_2__0_n_0\,
I5 => \length_counter__0\(5),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFE2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I1 => \^first_mi_word_q\,
I2 => Q(4),
I3 => \USE_RTL_LENGTH.length_counter_q[4]_i_2__0_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => \length_counter__0\(5)
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAAA2AAA2AAAEAAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => m_valid_i_reg,
I2 => s_axi_rready,
I3 => p_13_in,
I4 => \USE_RTL_LENGTH.length_counter_q[6]_i_3_n_0\,
I5 => \length_counter__0\(6),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFAEEEEFFFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[4]_i_2__0_n_0\,
I1 => Q(4),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_3_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
O => \length_counter__0\(6)
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F2F0D0D2D0F0F2D2"
)
port map (
I0 => m_valid_i_reg,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\,
I5 => Q(7),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEAE"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[6]_i_3_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I2 => \^first_mi_word_q\,
I3 => Q(6),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_4_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\current_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^e\(0),
D => \pre_next_word_1_reg[3]_0\(0),
Q => first_word_reg_2(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\current_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^e\(0),
D => \pre_next_word_1_reg[3]_0\(1),
Q => first_word_reg_2(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\current_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^e\(0),
D => \pre_next_word_1_reg[3]_0\(2),
Q => first_word_reg_2(2),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\current_word_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^e\(0),
D => \pre_next_word_1_reg[3]_0\(3),
Q => first_word_reg_2(3),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
first_word_reg: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => \^e\(0),
D => use_wrap_buffer_reg_0,
Q => \^first_word\,
S => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\pre_next_word_1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA00"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => mr_rvalid,
I2 => rd_cmd_valid,
I3 => s_axi_rready,
O => \^e\(0)
);
\pre_next_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^e\(0),
D => D(0),
Q => \current_word_1_reg[3]_0\(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\pre_next_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^e\(0),
D => D(1),
Q => \current_word_1_reg[3]_0\(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\pre_next_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^e\(0),
D => D(2),
Q => \current_word_1_reg[3]_0\(2),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\pre_next_word_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^e\(0),
D => D(3),
Q => \current_word_1_reg[3]_0\(3),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\rresp_wrap_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(128),
Q => rresp_wrap_buffer(0),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\rresp_wrap_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_7_in,
D => \m_payload_i_reg[129]\(129),
Q => rresp_wrap_buffer(1),
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\s_axi_rdata[31]_INST_0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^first_word\,
I1 => Q(9),
O => \sel_first_word__0\
);
s_axi_rlast_INST_0_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I2 => \^first_mi_word_q\,
O => first_word_reg_0
);
s_axi_rlast_INST_0_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I5 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
O => first_word_reg_1
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(0),
I1 => \^use_wrap_buffer\,
I2 => \m_payload_i_reg[129]\(128),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(1),
I1 => \^use_wrap_buffer\,
I2 => \m_payload_i_reg[129]\(129),
O => s_axi_rresp(1)
);
use_wrap_buffer_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => wrap_buffer_available_reg_0,
Q => \^use_wrap_buffer\,
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
\wrap_buffer_available_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"BFA0"
)
port map (
I0 => p_7_in,
I1 => \last_beat__6\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\,
I3 => \^wrap_buffer_available\,
O => \wrap_buffer_available_i_1__0_n_0\
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wrap_buffer_available_i_1__0_n_0\,
Q => \^wrap_buffer_available\,
R => \^use_rtl_length.length_counter_q_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer is
port (
first_word_q : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]_0\ : out STD_LOGIC;
wstrb_wrap_buffer_1 : out STD_LOGIC;
wstrb_wrap_buffer_2 : out STD_LOGIC;
wstrb_wrap_buffer_3 : out STD_LOGIC;
wstrb_wrap_buffer_4 : out STD_LOGIC;
wstrb_wrap_buffer_5 : out STD_LOGIC;
wstrb_wrap_buffer_6 : out STD_LOGIC;
wstrb_wrap_buffer_7 : out STD_LOGIC;
wstrb_wrap_buffer_8 : out STD_LOGIC;
wstrb_wrap_buffer_9 : out STD_LOGIC;
wstrb_wrap_buffer_10 : out STD_LOGIC;
wstrb_wrap_buffer_11 : out STD_LOGIC;
wstrb_wrap_buffer_12 : out STD_LOGIC;
wstrb_wrap_buffer_13 : out STD_LOGIC;
wstrb_wrap_buffer_14 : out STD_LOGIC;
wstrb_wrap_buffer_15 : out STD_LOGIC;
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_buffer_available : out STD_LOGIC;
first_mi_word_q : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]_0\ : out STD_LOGIC;
\sel_first_word__0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_0\ : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_1\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]_1\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]_1\ : out STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
\out\ : in STD_LOGIC;
p_55_out56_out : in STD_LOGIC;
p_51_out52_out : in STD_LOGIC;
p_47_out : in STD_LOGIC;
p_44_out : in STD_LOGIC;
p_41_out : in STD_LOGIC;
p_37_out : in STD_LOGIC;
p_33_out : in STD_LOGIC;
p_30_out : in STD_LOGIC;
p_25_out26_out : in STD_LOGIC;
p_22_out : in STD_LOGIC;
p_17_out18_out : in STD_LOGIC;
p_14_out : in STD_LOGIC;
p_11_out : in STD_LOGIC;
p_8_out : in STD_LOGIC;
p_3_out4_out : in STD_LOGIC;
p_0_out : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ : in STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_487_in : in STD_LOGIC;
wrap_buffer_available_reg_0 : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_2\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_2\ : in STD_LOGIC;
p_476_in : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_3\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
\current_word_idx_1__0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_4\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_5\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_6\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_7\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\ : in STD_LOGIC;
\p_61_out__2\ : in STD_LOGIC;
\p_91_out__2\ : in STD_LOGIC;
\p_122_out__2\ : in STD_LOGIC;
\p_151_out__2\ : in STD_LOGIC;
\p_180_out__2\ : in STD_LOGIC;
\p_209_out__2\ : in STD_LOGIC;
\p_240_out__2\ : in STD_LOGIC;
\p_269_out__2\ : in STD_LOGIC;
\p_298_out__2\ : in STD_LOGIC;
\p_327_out__2\ : in STD_LOGIC;
\p_358_out__2\ : in STD_LOGIC;
\p_387_out__2\ : in STD_LOGIC;
\p_416_out__2\ : in STD_LOGIC;
\p_445_out__2\ : in STD_LOGIC;
\p_481_out__2\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
wr_cmd_valid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wrap_buffer_available_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wrap_buffer_available_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wrap_buffer_available_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_8\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wrap_buffer_available_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_9\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_10\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_13\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_14\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_15\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_16\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_17\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer : entity is "axi_dwidth_converter_v2_1_11_w_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer is
signal \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\ : STD_LOGIC;
signal \^use_register.m_axi_wvalid_q_reg_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \^use_rtl_length.length_counter_q_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^use_rtl_length.length_counter_q_reg[2]_0\ : STD_LOGIC;
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\ : STD_LOGIC;
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_1\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[64]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[65]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[66]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[67]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[68]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[69]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[70]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[72]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[73]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[74]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[75]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[76]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[77]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[78]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[80]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[81]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[82]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[83]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[84]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[85]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[86]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[88]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[89]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[90]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[91]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[92]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[93]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[94]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[100]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[101]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[102]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[96]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[97]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[98]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[99]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[104]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[105]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[106]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[107]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[108]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[109]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[110]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[112]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[113]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[114]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[115]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[116]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[117]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[118]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_2_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[120]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[121]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[122]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[123]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[124]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[125]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[126]_i_1_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_3_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word_q\ : STD_LOGIC;
signal \^m_axi_wlast\ : STD_LOGIC;
signal \^m_axi_wstrb\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^m_axi_wvalid\ : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_19_out : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_out : STD_LOGIC;
signal p_23_out : STD_LOGIC;
signal p_27_out : STD_LOGIC;
signal p_31_out : STD_LOGIC;
signal p_34_out : STD_LOGIC;
signal p_38_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_45_out : STD_LOGIC;
signal p_48_out49_out : STD_LOGIC;
signal p_53_out : STD_LOGIC;
signal p_57_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_1\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_10\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_11\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_12\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_13\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_14\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_15\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_2\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_3\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_4\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_5\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_6\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_7\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_8\ : STD_LOGIC;
signal \^wstrb_wrap_buffer_9\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WLAST_q_i_1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[3]_i_2\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[4]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[5]_i_2\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[6]_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[7]_i_2\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3\ : label is "soft_lutpair82";
begin
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ <= \^use_register.m_axi_wvalid_q_reg_0\;
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\(1 downto 0) <= \^use_rtl_length.length_counter_q_reg[1]_0\(1 downto 0);
\USE_RTL_LENGTH.length_counter_q_reg[2]_0\ <= \^use_rtl_length.length_counter_q_reg[2]_0\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]_0\ <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]_1\ <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_1\;
first_mi_word_q <= \^first_mi_word_q\;
first_word_q <= \^first_word_q\;
m_axi_wlast <= \^m_axi_wlast\;
m_axi_wstrb(15 downto 0) <= \^m_axi_wstrb\(15 downto 0);
m_axi_wvalid <= \^m_axi_wvalid\;
wrap_buffer_available <= \^wrap_buffer_available\;
wstrb_wrap_buffer_1 <= \^wstrb_wrap_buffer_1\;
wstrb_wrap_buffer_10 <= \^wstrb_wrap_buffer_10\;
wstrb_wrap_buffer_11 <= \^wstrb_wrap_buffer_11\;
wstrb_wrap_buffer_12 <= \^wstrb_wrap_buffer_12\;
wstrb_wrap_buffer_13 <= \^wstrb_wrap_buffer_13\;
wstrb_wrap_buffer_14 <= \^wstrb_wrap_buffer_14\;
wstrb_wrap_buffer_15 <= \^wstrb_wrap_buffer_15\;
wstrb_wrap_buffer_2 <= \^wstrb_wrap_buffer_2\;
wstrb_wrap_buffer_3 <= \^wstrb_wrap_buffer_3\;
wstrb_wrap_buffer_4 <= \^wstrb_wrap_buffer_4\;
wstrb_wrap_buffer_5 <= \^wstrb_wrap_buffer_5\;
wstrb_wrap_buffer_6 <= \^wstrb_wrap_buffer_6\;
wstrb_wrap_buffer_7 <= \^wstrb_wrap_buffer_7\;
wstrb_wrap_buffer_8 <= \^wstrb_wrap_buffer_8\;
wstrb_wrap_buffer_9 <= \^wstrb_wrap_buffer_9\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0000000B0B00000"
)
port map (
I0 => m_axi_wready,
I1 => \^m_axi_wvalid\,
I2 => s_axi_wvalid,
I3 => \^wrap_buffer_available\,
I4 => wr_cmd_valid,
I5 => Q(8),
O => \USE_RTL_LENGTH.length_counter_q_reg[1]_1\
);
\USE_REGISTER.M_AXI_WLAST_q_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wlast,
I1 => m_axi_wready,
I2 => \^m_axi_wvalid\,
I3 => \^m_axi_wlast\,
O => \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\
);
\USE_REGISTER.M_AXI_WLAST_q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0\,
Q => \^m_axi_wlast\,
R => SR(0)
);
\USE_REGISTER.M_AXI_WVALID_q_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I1 => Q(4),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I3 => \^first_mi_word_q\,
I4 => Q(5),
O => \^use_register.m_axi_wvalid_q_reg_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I1 => Q(2),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I3 => \^first_mi_word_q\,
I4 => Q(3),
O => \USE_REGISTER.M_AXI_WVALID_q_reg_1\
);
\USE_REGISTER.M_AXI_WVALID_q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\,
Q => \^m_axi_wvalid\,
R => SR(0)
);
\USE_RTL_CURR_WORD.current_word_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(0),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]_0\(0),
R => SR(0)
);
\USE_RTL_CURR_WORD.current_word_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(1),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]_0\(1),
R => SR(0)
);
\USE_RTL_CURR_WORD.current_word_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(2),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]_0\(2),
R => SR(0)
);
\USE_RTL_CURR_WORD.current_word_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(3),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]_0\(3),
R => SR(0)
);
\USE_RTL_CURR_WORD.first_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => E(0),
D => s_axi_wlast,
Q => \^first_word_q\,
S => SR(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^first_word_q\,
I1 => Q(9),
O => \sel_first_word__0\
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => D(0),
Q => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(0),
R => SR(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => D(1),
Q => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(1),
R => SR(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => D(2),
Q => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(2),
R => SR(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => D(3),
Q => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(3),
R => SR(0)
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.first_mi_word_q_reg_0\,
Q => \^first_mi_word_q\,
S => SR(0)
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F70"
)
port map (
I0 => \^first_mi_word_q\,
I1 => Q(0),
I2 => p_487_in,
I3 => \^use_rtl_length.length_counter_q_reg[1]_0\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACCC5C3C"
)
port map (
I0 => Q(2),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => p_487_in,
I3 => \^first_mi_word_q\,
I4 => \^use_rtl_length.length_counter_q_reg[2]_0\,
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[1]_0\(0),
I1 => Q(0),
I2 => \^use_rtl_length.length_counter_q_reg[1]_0\(1),
I3 => \^first_mi_word_q\,
I4 => Q(1),
O => \^use_rtl_length.length_counter_q_reg[2]_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D8D272D2"
)
port map (
I0 => p_487_in,
I1 => \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I3 => \^first_mi_word_q\,
I4 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFE2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I1 => \^first_mi_word_q\,
I2 => Q(2),
I3 => \^use_rtl_length.length_counter_q_reg[2]_0\,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACCC5C3C"
)
port map (
I0 => Q(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => p_487_in,
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFAEEEEFFFA"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[2]_0\,
I1 => Q(2),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I4 => \^first_mi_word_q\,
I5 => Q(3),
O => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D8D272D2"
)
port map (
I0 => p_487_in,
I1 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I3 => \^first_mi_word_q\,
I4 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFE2"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I1 => \^first_mi_word_q\,
I2 => Q(4),
I3 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D8D272D2"
)
port map (
I0 => p_487_in,
I1 => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I3 => \^first_mi_word_q\,
I4 => Q(6),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFAEEEEFFFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[4]_i_2_n_0\,
I1 => Q(4),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => Q(5),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AC5CCC3C"
)
port map (
I0 => Q(7),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I2 => p_487_in,
I3 => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\,
I4 => \^first_mi_word_q\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEAE"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I2 => \^first_mi_word_q\,
I3 => Q(6),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\,
Q => \^use_rtl_length.length_counter_q_reg[1]_0\(0),
R => SR(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q_reg[0]_0\,
Q => \^use_rtl_length.length_counter_q_reg[1]_0\(1),
R => SR(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => SR(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => SR(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => SR(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => SR(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => SR(0)
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(0),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I3 => p_476_in,
I4 => \p_481_out__2\,
O => p_1_in(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(1),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I3 => p_476_in,
I4 => \p_481_out__2\,
O => p_1_in(1)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(2),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I3 => p_476_in,
I4 => \p_481_out__2\,
O => p_1_in(2)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(3),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I3 => p_476_in,
I4 => \p_481_out__2\,
O => p_1_in(3)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(4),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I3 => p_476_in,
I4 => \p_481_out__2\,
O => p_1_in(4)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(5),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I3 => p_476_in,
I4 => \p_481_out__2\,
O => p_1_in(5)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(6),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I3 => p_476_in,
I4 => \p_481_out__2\,
O => p_1_in(6)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(7),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I3 => p_476_in,
I4 => \p_481_out__2\,
O => p_1_in(7)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_2\(0),
D => p_1_in(0),
Q => m_axi_wdata(0),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_2\(0),
D => p_1_in(1),
Q => m_axi_wdata(1),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_2\(0),
D => p_1_in(2),
Q => m_axi_wdata(2),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_2\(0),
D => p_1_in(3),
Q => m_axi_wdata(3),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_2\(0),
D => p_1_in(4),
Q => m_axi_wdata(4),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_2\(0),
D => p_1_in(5),
Q => m_axi_wdata(5),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_2\(0),
D => p_1_in(6),
Q => m_axi_wdata(6),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_2\(0),
D => p_1_in(7),
Q => m_axi_wdata(7),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(0),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_7\,
O => p_57_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_57_out,
Q => \^m_axi_wstrb\(0),
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_55_out56_out,
Q => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_0\,
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(10),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_1\,
I3 => p_476_in,
I4 => \p_445_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(11),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_1\,
I3 => p_476_in,
I4 => \p_445_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(12),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_1\,
I3 => p_476_in,
I4 => \p_445_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(13),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_1\,
I3 => p_476_in,
I4 => \p_445_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(14),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_1\,
I3 => p_476_in,
I4 => \p_445_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(15),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_1\,
I3 => p_476_in,
I4 => \p_445_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(8),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_1\,
I3 => p_476_in,
I4 => \p_445_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(9),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_1\,
I3 => p_476_in,
I4 => \p_445_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_3\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0\,
Q => m_axi_wdata(10),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_3\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0\,
Q => m_axi_wdata(11),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_3\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0\,
Q => m_axi_wdata(12),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_3\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0\,
Q => m_axi_wdata(13),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_3\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0\,
Q => m_axi_wdata(14),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_3\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0\,
Q => m_axi_wdata(15),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_3\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0\,
Q => m_axi_wdata(8),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_3\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0\,
Q => m_axi_wdata(9),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_1\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(1),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_6\,
O => p_53_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_53_out,
Q => \^m_axi_wstrb\(1),
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_51_out52_out,
Q => \^wstrb_wrap_buffer_1\,
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(16),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_2\,
I3 => p_476_in,
I4 => \p_416_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(17),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_2\,
I3 => p_476_in,
I4 => \p_416_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(18),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_2\,
I3 => p_476_in,
I4 => \p_416_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(19),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_2\,
I3 => p_476_in,
I4 => \p_416_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(20),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_2\,
I3 => p_476_in,
I4 => \p_416_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(21),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_2\,
I3 => p_476_in,
I4 => \p_416_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(22),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_2\,
I3 => p_476_in,
I4 => \p_416_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(23),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_2\,
I3 => p_476_in,
I4 => \p_416_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_4\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0\,
Q => m_axi_wdata(16),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_4\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0\,
Q => m_axi_wdata(17),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_4\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0\,
Q => m_axi_wdata(18),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_4\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0\,
Q => m_axi_wdata(19),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_4\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0\,
Q => m_axi_wdata(20),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_4\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0\,
Q => m_axi_wdata(21),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_4\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0\,
Q => m_axi_wdata(22),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_4\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0\,
Q => m_axi_wdata(23),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_2\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(2),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_5\,
O => p_48_out49_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_48_out49_out,
Q => \^m_axi_wstrb\(2),
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_47_out,
Q => \^wstrb_wrap_buffer_2\,
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(24),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_3\,
I3 => p_476_in,
I4 => \p_387_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(25),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_3\,
I3 => p_476_in,
I4 => \p_387_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(26),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_3\,
I3 => p_476_in,
I4 => \p_387_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(27),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_3\,
I3 => p_476_in,
I4 => \p_387_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(28),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_3\,
I3 => p_476_in,
I4 => \p_387_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(29),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_3\,
I3 => p_476_in,
I4 => \p_387_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(30),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_3\,
I3 => p_476_in,
I4 => \p_387_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(31),
I1 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_3\,
I3 => p_476_in,
I4 => \p_387_out__2\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_5\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0\,
Q => m_axi_wdata(24),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_5\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0\,
Q => m_axi_wdata(25),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_5\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0\,
Q => m_axi_wdata(26),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_5\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0\,
Q => m_axi_wdata(27),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_5\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0\,
Q => m_axi_wdata(28),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_5\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0\,
Q => m_axi_wdata(29),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_5\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0\,
Q => m_axi_wdata(30),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_5\(0),
D => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0\,
Q => m_axi_wdata(31),
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_3\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(3),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_4\,
O => p_45_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_45_out,
Q => \^m_axi_wstrb\(3),
R => '0'
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_44_out,
Q => \^wstrb_wrap_buffer_3\,
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(0),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_4\,
I3 => p_476_in,
I4 => \p_358_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(1),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_4\,
I3 => p_476_in,
I4 => \p_358_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(2),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_4\,
I3 => p_476_in,
I4 => \p_358_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(3),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_4\,
I3 => p_476_in,
I4 => \p_358_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(4),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_4\,
I3 => p_476_in,
I4 => \p_358_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(5),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_4\,
I3 => p_476_in,
I4 => \p_358_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(6),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_4\,
I3 => p_476_in,
I4 => \p_358_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(7),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_4\,
I3 => p_476_in,
I4 => \p_358_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_6\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0\,
Q => m_axi_wdata(32),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_6\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0\,
Q => m_axi_wdata(33),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_6\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0\,
Q => m_axi_wdata(34),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_6\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0\,
Q => m_axi_wdata(35),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_6\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0\,
Q => m_axi_wdata(36),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_6\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0\,
Q => m_axi_wdata(37),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_6\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0\,
Q => m_axi_wdata(38),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_6\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0\,
Q => m_axi_wdata(39),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF8F8F8F8F8F8F8"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_4\,
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2_n_0\,
I3 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I4 => \current_word_idx_1__0\,
I5 => s_axi_wstrb(0),
O => p_42_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7000"
)
port map (
I0 => m_axi_wready,
I1 => \^m_axi_wvalid\,
I2 => s_axi_aresetn,
I3 => \^m_axi_wstrb\(4),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_42_out,
Q => \^m_axi_wstrb\(4),
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_1(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_1(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_1(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_1(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_1(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_1(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_1(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_1(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_41_out,
Q => \^wstrb_wrap_buffer_4\,
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(8),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_5\,
I3 => p_476_in,
I4 => \p_327_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(9),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_5\,
I3 => p_476_in,
I4 => \p_327_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(10),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_5\,
I3 => p_476_in,
I4 => \p_327_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(11),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_5\,
I3 => p_476_in,
I4 => \p_327_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(12),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_5\,
I3 => p_476_in,
I4 => \p_327_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(13),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_5\,
I3 => p_476_in,
I4 => \p_327_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(14),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_5\,
I3 => p_476_in,
I4 => \p_327_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(15),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_5\,
I3 => p_476_in,
I4 => \p_327_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_7\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0\,
Q => m_axi_wdata(40),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_7\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0\,
Q => m_axi_wdata(41),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_7\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0\,
Q => m_axi_wdata(42),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_7\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0\,
Q => m_axi_wdata(43),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_7\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0\,
Q => m_axi_wdata(44),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_7\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0\,
Q => m_axi_wdata(45),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_7\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0\,
Q => m_axi_wdata(46),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_7\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0\,
Q => m_axi_wdata(47),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF8F8F8F8F8F8F8"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_5\,
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2_n_0\,
I3 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I4 => \current_word_idx_1__0\,
I5 => s_axi_wstrb(1),
O => p_38_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7000"
)
port map (
I0 => m_axi_wready,
I1 => \^m_axi_wvalid\,
I2 => s_axi_aresetn,
I3 => \^m_axi_wstrb\(5),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_38_out,
Q => \^m_axi_wstrb\(5),
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_2(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_2(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_2(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_2(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_2(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_2(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_2(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_2(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_37_out,
Q => \^wstrb_wrap_buffer_5\,
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(16),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_6\,
I3 => p_476_in,
I4 => \p_298_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(17),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_6\,
I3 => p_476_in,
I4 => \p_298_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(18),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_6\,
I3 => p_476_in,
I4 => \p_298_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(19),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_6\,
I3 => p_476_in,
I4 => \p_298_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(20),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_6\,
I3 => p_476_in,
I4 => \p_298_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(21),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_6\,
I3 => p_476_in,
I4 => \p_298_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(22),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_6\,
I3 => p_476_in,
I4 => \p_298_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(23),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_6\,
I3 => p_476_in,
I4 => \p_298_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_8\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0\,
Q => m_axi_wdata(48),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_8\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0\,
Q => m_axi_wdata(49),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_8\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0\,
Q => m_axi_wdata(50),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_8\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0\,
Q => m_axi_wdata(51),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_8\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0\,
Q => m_axi_wdata(52),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_8\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0\,
Q => m_axi_wdata(53),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_8\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0\,
Q => m_axi_wdata(54),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_8\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0\,
Q => m_axi_wdata(55),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF8F8F8F8F8F8F8"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_6\,
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2_n_0\,
I3 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I4 => \current_word_idx_1__0\,
I5 => s_axi_wstrb(2),
O => p_34_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7000"
)
port map (
I0 => m_axi_wready,
I1 => \^m_axi_wvalid\,
I2 => s_axi_aresetn,
I3 => \^m_axi_wstrb\(6),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_34_out,
Q => \^m_axi_wstrb\(6),
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_3(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_3(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_3(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_3(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_3(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_3(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_3(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_3(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_33_out,
Q => \^wstrb_wrap_buffer_6\,
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(24),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_7\,
I3 => p_476_in,
I4 => \p_269_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(25),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_7\,
I3 => p_476_in,
I4 => \p_269_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(26),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_7\,
I3 => p_476_in,
I4 => \p_269_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(27),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_7\,
I3 => p_476_in,
I4 => \p_269_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(28),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_7\,
I3 => p_476_in,
I4 => \p_269_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(29),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_7\,
I3 => p_476_in,
I4 => \p_269_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(30),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_7\,
I3 => p_476_in,
I4 => \p_269_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(31),
I1 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_7\,
I3 => p_476_in,
I4 => \p_269_out__2\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_9\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0\,
Q => m_axi_wdata(56),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_9\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0\,
Q => m_axi_wdata(57),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_9\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0\,
Q => m_axi_wdata(58),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_9\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0\,
Q => m_axi_wdata(59),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_9\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0\,
Q => m_axi_wdata(60),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_9\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0\,
Q => m_axi_wdata(61),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_9\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0\,
Q => m_axi_wdata(62),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_9\(0),
D => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0\,
Q => m_axi_wdata(63),
R => SR(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF800F000F800F0"
)
port map (
I0 => \^wstrb_wrap_buffer_7\,
I1 => p_476_in,
I2 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2_n_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_3\,
I4 => s_axi_aresetn,
I5 => s_axi_wstrb(3),
O => p_31_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7000"
)
port map (
I0 => m_axi_wready,
I1 => \^m_axi_wvalid\,
I2 => s_axi_aresetn,
I3 => \^m_axi_wstrb\(7),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_31_out,
Q => \^m_axi_wstrb\(7),
R => '0'
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_4(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_4(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_4(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_4(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_4(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_4(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_4(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wrap_buffer_available_reg_4(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_30_out,
Q => \^wstrb_wrap_buffer_7\,
R => '0'
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[64]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(0),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_8\,
I3 => p_476_in,
I4 => \p_240_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[64]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[65]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(1),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_8\,
I3 => p_476_in,
I4 => \p_240_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[65]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[66]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(2),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_8\,
I3 => p_476_in,
I4 => \p_240_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[66]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[67]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(3),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_8\,
I3 => p_476_in,
I4 => \p_240_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[67]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[68]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(4),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_8\,
I3 => p_476_in,
I4 => \p_240_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[68]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[69]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(5),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_8\,
I3 => p_476_in,
I4 => \p_240_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[69]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[70]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(6),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_8\,
I3 => p_476_in,
I4 => \p_240_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[70]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(7),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_8\,
I3 => p_476_in,
I4 => \p_240_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_2_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_10\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[64]_i_1_n_0\,
Q => m_axi_wdata(64),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_10\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[65]_i_1_n_0\,
Q => m_axi_wdata(65),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_10\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[66]_i_1_n_0\,
Q => m_axi_wdata(66),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_10\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[67]_i_1_n_0\,
Q => m_axi_wdata(67),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_10\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[68]_i_1_n_0\,
Q => m_axi_wdata(68),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_10\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[69]_i_1_n_0\,
Q => m_axi_wdata(69),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_10\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[70]_i_1_n_0\,
Q => m_axi_wdata(70),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_10\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_2_n_0\,
Q => m_axi_wdata(71),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_8\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(8),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_2\,
O => p_27_out
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_27_out,
Q => \^m_axi_wstrb\(8),
R => '0'
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_25_out26_out,
Q => \^wstrb_wrap_buffer_8\,
R => '0'
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[72]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(8),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_9\,
I3 => p_476_in,
I4 => \p_209_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[72]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[73]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(9),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_9\,
I3 => p_476_in,
I4 => \p_209_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[73]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[74]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(10),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_9\,
I3 => p_476_in,
I4 => \p_209_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[74]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[75]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(11),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_9\,
I3 => p_476_in,
I4 => \p_209_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[75]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[76]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(12),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_9\,
I3 => p_476_in,
I4 => \p_209_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[76]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[77]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(13),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_9\,
I3 => p_476_in,
I4 => \p_209_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[77]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[78]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(14),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_9\,
I3 => p_476_in,
I4 => \p_209_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[78]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(15),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_9\,
I3 => p_476_in,
I4 => \p_209_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_2_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_11\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[72]_i_1_n_0\,
Q => m_axi_wdata(72),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_11\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[73]_i_1_n_0\,
Q => m_axi_wdata(73),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_11\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[74]_i_1_n_0\,
Q => m_axi_wdata(74),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_11\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[75]_i_1_n_0\,
Q => m_axi_wdata(75),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_11\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[76]_i_1_n_0\,
Q => m_axi_wdata(76),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_11\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[77]_i_1_n_0\,
Q => m_axi_wdata(77),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_11\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[78]_i_1_n_0\,
Q => m_axi_wdata(78),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_11\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_2_n_0\,
Q => m_axi_wdata(79),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_9\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(9),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_1\,
O => p_23_out
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_23_out,
Q => \^m_axi_wstrb\(9),
R => '0'
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_22_out,
Q => \^wstrb_wrap_buffer_9\,
R => '0'
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[80]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(16),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_10\,
I3 => p_476_in,
I4 => \p_180_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[80]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[81]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(17),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_10\,
I3 => p_476_in,
I4 => \p_180_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[81]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[82]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(18),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_10\,
I3 => p_476_in,
I4 => \p_180_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[82]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[83]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(19),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_10\,
I3 => p_476_in,
I4 => \p_180_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[83]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[84]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(20),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_10\,
I3 => p_476_in,
I4 => \p_180_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[84]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[85]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(21),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_10\,
I3 => p_476_in,
I4 => \p_180_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[85]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[86]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(22),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_10\,
I3 => p_476_in,
I4 => \p_180_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[86]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(23),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_10\,
I3 => p_476_in,
I4 => \p_180_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_2_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_12\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[80]_i_1_n_0\,
Q => m_axi_wdata(80),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_12\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[81]_i_1_n_0\,
Q => m_axi_wdata(81),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_12\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[82]_i_1_n_0\,
Q => m_axi_wdata(82),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_12\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[83]_i_1_n_0\,
Q => m_axi_wdata(83),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_12\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[84]_i_1_n_0\,
Q => m_axi_wdata(84),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_12\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[85]_i_1_n_0\,
Q => m_axi_wdata(85),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_12\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[86]_i_1_n_0\,
Q => m_axi_wdata(86),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_12\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_2_n_0\,
Q => m_axi_wdata(87),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_10\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(10),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_0\,
O => p_19_out
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_19_out,
Q => \^m_axi_wstrb\(10),
R => '0'
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_17_out18_out,
Q => \^wstrb_wrap_buffer_10\,
R => '0'
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[88]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(24),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_11\,
I3 => p_476_in,
I4 => \p_151_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[88]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[89]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(25),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_11\,
I3 => p_476_in,
I4 => \p_151_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[89]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[90]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(26),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_11\,
I3 => p_476_in,
I4 => \p_151_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[90]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[91]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(27),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_11\,
I3 => p_476_in,
I4 => \p_151_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[91]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[92]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(28),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_11\,
I3 => p_476_in,
I4 => \p_151_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[92]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[93]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(29),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_11\,
I3 => p_476_in,
I4 => \p_151_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[93]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[94]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(30),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_11\,
I3 => p_476_in,
I4 => \p_151_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[94]_i_1_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(31),
I1 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_11\,
I3 => p_476_in,
I4 => \p_151_out__2\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_2_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_13\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[88]_i_1_n_0\,
Q => m_axi_wdata(88),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_13\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[89]_i_1_n_0\,
Q => m_axi_wdata(89),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_13\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[90]_i_1_n_0\,
Q => m_axi_wdata(90),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_13\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[91]_i_1_n_0\,
Q => m_axi_wdata(91),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_13\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[92]_i_1_n_0\,
Q => m_axi_wdata(92),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_13\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[93]_i_1_n_0\,
Q => m_axi_wdata(93),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_13\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[94]_i_1_n_0\,
Q => m_axi_wdata(94),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_13\(0),
D => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_2_n_0\,
Q => m_axi_wdata(95),
R => SR(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_11\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(11),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
O => p_15_out
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_15_out,
Q => \^m_axi_wstrb\(11),
R => '0'
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_14_out,
Q => \^wstrb_wrap_buffer_11\,
R => '0'
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[100]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(4),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_12\,
I3 => p_476_in,
I4 => \p_122_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[100]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[101]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(5),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_12\,
I3 => p_476_in,
I4 => \p_122_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[101]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[102]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(6),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_12\,
I3 => p_476_in,
I4 => \p_122_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[102]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(7),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_12\,
I3 => p_476_in,
I4 => \p_122_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_2_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[96]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(0),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_12\,
I3 => p_476_in,
I4 => \p_122_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[96]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[97]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(1),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_12\,
I3 => p_476_in,
I4 => \p_122_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[97]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[98]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(2),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_12\,
I3 => p_476_in,
I4 => \p_122_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[98]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[99]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(3),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_12\,
I3 => p_476_in,
I4 => \p_122_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[99]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_14\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[100]_i_1_n_0\,
Q => m_axi_wdata(100),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_14\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[101]_i_1_n_0\,
Q => m_axi_wdata(101),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_14\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[102]_i_1_n_0\,
Q => m_axi_wdata(102),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_14\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_2_n_0\,
Q => m_axi_wdata(103),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_14\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[96]_i_1_n_0\,
Q => m_axi_wdata(96),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_14\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[97]_i_1_n_0\,
Q => m_axi_wdata(97),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_14\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[98]_i_1_n_0\,
Q => m_axi_wdata(98),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_14\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[99]_i_1_n_0\,
Q => m_axi_wdata(99),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_12\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(12),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_2\,
O => p_12_out
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_12_out,
Q => \^m_axi_wstrb\(12),
R => '0'
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0),
D => s_axi_wdata(4),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0),
D => s_axi_wdata(5),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0),
D => s_axi_wdata(6),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0),
D => s_axi_wdata(7),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0),
D => s_axi_wdata(0),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0),
D => s_axi_wdata(1),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0),
D => s_axi_wdata(2),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0),
D => s_axi_wdata(3),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_11_out,
Q => \^wstrb_wrap_buffer_12\,
R => '0'
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[104]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(8),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_13\,
I3 => p_476_in,
I4 => \p_91_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[104]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[105]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(9),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_13\,
I3 => p_476_in,
I4 => \p_91_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[105]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[106]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(10),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_13\,
I3 => p_476_in,
I4 => \p_91_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[106]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[107]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(11),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_13\,
I3 => p_476_in,
I4 => \p_91_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[107]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[108]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(12),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_13\,
I3 => p_476_in,
I4 => \p_91_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[108]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[109]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(13),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_13\,
I3 => p_476_in,
I4 => \p_91_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[109]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[110]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(14),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_13\,
I3 => p_476_in,
I4 => \p_91_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[110]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(15),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_13\,
I3 => p_476_in,
I4 => \p_91_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_2_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_15\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[104]_i_1_n_0\,
Q => m_axi_wdata(104),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_15\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[105]_i_1_n_0\,
Q => m_axi_wdata(105),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_15\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[106]_i_1_n_0\,
Q => m_axi_wdata(106),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_15\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[107]_i_1_n_0\,
Q => m_axi_wdata(107),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_15\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[108]_i_1_n_0\,
Q => m_axi_wdata(108),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_15\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[109]_i_1_n_0\,
Q => m_axi_wdata(109),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_15\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[110]_i_1_n_0\,
Q => m_axi_wdata(110),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_15\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_2_n_0\,
Q => m_axi_wdata(111),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_13\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(13),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\,
O => p_9_out
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_9_out,
Q => \^m_axi_wstrb\(13),
R => '0'
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0),
D => s_axi_wdata(8),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0),
D => s_axi_wdata(9),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0),
D => s_axi_wdata(10),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0),
D => s_axi_wdata(11),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0),
D => s_axi_wdata(12),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0),
D => s_axi_wdata(13),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0),
D => s_axi_wdata(14),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0),
D => s_axi_wdata(15),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_8_out,
Q => \^wstrb_wrap_buffer_13\,
R => '0'
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[112]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(16),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_14\,
I3 => p_476_in,
I4 => \p_61_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[112]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[113]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(17),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_14\,
I3 => p_476_in,
I4 => \p_61_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[113]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[114]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(18),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_14\,
I3 => p_476_in,
I4 => \p_61_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[114]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[115]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(19),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_14\,
I3 => p_476_in,
I4 => \p_61_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[115]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[116]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(20),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_14\,
I3 => p_476_in,
I4 => \p_61_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[116]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[117]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(21),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_14\,
I3 => p_476_in,
I4 => \p_61_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[117]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[118]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(22),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_14\,
I3 => p_476_in,
I4 => \p_61_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[118]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(23),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_14\,
I3 => p_476_in,
I4 => \p_61_out__2\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_2_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_16\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[112]_i_1_n_0\,
Q => m_axi_wdata(112),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_16\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[113]_i_1_n_0\,
Q => m_axi_wdata(113),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_16\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[114]_i_1_n_0\,
Q => m_axi_wdata(114),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_16\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[115]_i_1_n_0\,
Q => m_axi_wdata(115),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_16\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[116]_i_1_n_0\,
Q => m_axi_wdata(116),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_16\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[117]_i_1_n_0\,
Q => m_axi_wdata(117),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_16\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[118]_i_1_n_0\,
Q => m_axi_wdata(118),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_16\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_2_n_0\,
Q => m_axi_wdata(119),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_14\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(14),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\,
O => p_5_out
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_5_out,
Q => \^m_axi_wstrb\(14),
R => '0'
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0),
D => s_axi_wdata(16),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0),
D => s_axi_wdata(17),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0),
D => s_axi_wdata(18),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0),
D => s_axi_wdata(19),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0),
D => s_axi_wdata(20),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0),
D => s_axi_wdata(21),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0),
D => s_axi_wdata(22),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0),
D => s_axi_wdata(23),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_3_out4_out,
Q => \^wstrb_wrap_buffer_14\,
R => '0'
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[120]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(24),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
I2 => \^wstrb_wrap_buffer_15\,
I3 => p_476_in,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[120]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[121]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(25),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
I2 => \^wstrb_wrap_buffer_15\,
I3 => p_476_in,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[121]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[122]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(26),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
I2 => \^wstrb_wrap_buffer_15\,
I3 => p_476_in,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[122]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[123]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(27),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
I2 => \^wstrb_wrap_buffer_15\,
I3 => p_476_in,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[123]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[124]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(28),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
I2 => \^wstrb_wrap_buffer_15\,
I3 => p_476_in,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[124]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[125]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(29),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
I2 => \^wstrb_wrap_buffer_15\,
I3 => p_476_in,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[125]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[126]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(30),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
I2 => \^wstrb_wrap_buffer_15\,
I3 => p_476_in,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[126]_i_1_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => Q(3),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I3 => Q(2),
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I5 => \^use_register.m_axi_wvalid_q_reg_0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAC000"
)
port map (
I0 => s_axi_wdata(31),
I1 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
I2 => \^wstrb_wrap_buffer_15\,
I3 => p_476_in,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_3_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D0000000D00000"
)
port map (
I0 => \^m_axi_wvalid\,
I1 => m_axi_wready,
I2 => s_axi_wvalid,
I3 => Q(8),
I4 => wr_cmd_valid,
I5 => \^wrap_buffer_available\,
O => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_1\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"1010101F"
)
port map (
I0 => Q(6),
I1 => Q(7),
I2 => \^first_mi_word_q\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_1\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_17\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[120]_i_1_n_0\,
Q => m_axi_wdata(120),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_17\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[121]_i_1_n_0\,
Q => m_axi_wdata(121),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_17\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[122]_i_1_n_0\,
Q => m_axi_wdata(122),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_17\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[123]_i_1_n_0\,
Q => m_axi_wdata(123),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_17\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[124]_i_1_n_0\,
Q => m_axi_wdata(124),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_17\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[125]_i_1_n_0\,
Q => m_axi_wdata(125),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_17\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[126]_i_1_n_0\,
Q => m_axi_wdata(126),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_REGISTER.M_AXI_WVALID_q_reg_17\(0),
D => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_3_n_0\,
Q => m_axi_wdata(127),
R => SR(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => wrap_buffer_available_reg_0,
I1 => \^wstrb_wrap_buffer_15\,
I2 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\,
I3 => \^m_axi_wstrb\(15),
I4 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
O => p_1_out
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => s_axi_aresetn,
I1 => \^m_axi_wvalid\,
I2 => m_axi_wready,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_3_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wstrb_i_reg[0]_1\,
I1 => s_axi_aresetn,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_4_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_1_out,
Q => \^m_axi_wstrb\(15),
R => '0'
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0),
D => s_axi_wdata(24),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(0),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0),
D => s_axi_wdata(25),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(1),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0),
D => s_axi_wdata(26),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(2),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0),
D => s_axi_wdata(27),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(3),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0),
D => s_axi_wdata(28),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(4),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0),
D => s_axi_wdata(29),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(5),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0),
D => s_axi_wdata(30),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(6),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0),
D => s_axi_wdata(31),
Q => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg__0\(7),
R => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_0_out,
Q => \^wstrb_wrap_buffer_15\,
R => '0'
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\,
Q => \^wrap_buffer_available\,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice is
port (
s_ready_i_reg_0 : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arregion[3]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ : in STD_LOGIC;
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 );
\m_payload_i_reg[37]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[50]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice is
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\ : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \USE_READ.read_addr_inst/access_need_extra_word__3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst/mi_word_intra_len__10\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \USE_READ.read_addr_inst/upsized_length__40\ : STD_LOGIC_VECTOR ( 4 downto 3 );
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\ : STD_LOGIC;
signal \m_axi_araddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^m_axi_arregion[3]\ : STD_LOGIC_VECTOR ( 43 downto 0 );
signal \m_axi_arsize[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arsize[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_arlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal sr_araddr : STD_LOGIC_VECTOR ( 3 downto 0 );
signal sr_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_arvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1__0\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_1__0\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2__0\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1__0\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1__0\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3__0\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4__0\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6__0\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7__0\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8__0\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1__0\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1__0\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1__0\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \m_axi_araddr[0]_INST_0_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \m_axi_araddr[3]_INST_0_i_2\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_axi_arburst[0]_INST_0\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_axi_arburst[1]_INST_0\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_8\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_7\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_8\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \m_axi_arlen[2]_INST_0_i_2\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \m_axi_arlen[2]_INST_0_i_4\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_4\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_5\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_1\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_4\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_axi_arlen[5]_INST_0_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_axi_arlen[6]_INST_0_i_2\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_axi_arlen[6]_INST_0_i_3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_axi_arlen[7]_INST_0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \m_axi_arsize[0]_INST_0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \m_axi_arsize[1]_INST_0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \m_axi_arsize[1]_INST_0_i_2\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \m_axi_arsize[2]_INST_0\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_axi_arsize[2]_INST_0_i_2\ : label is "soft_lutpair131";
begin
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(32 downto 0) <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(32 downto 0);
\m_axi_arregion[3]\(43 downto 0) <= \^m_axi_arregion[3]\(43 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
sr_arvalid <= \^sr_arvalid\;
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFDFFFDF"
)
port map (
I0 => \m_payload_i_reg[37]_0\(0),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF11011000"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_payload_i_reg[37]_0\(0),
O => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2__0_n_0\,
I1 => \m_payload_i_reg[37]_0\(0),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000FAC000000AC"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(2),
I2 => sr_arsize(0),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFBAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0_n_0\,
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2__0_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000CA"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(2),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_payload_i_reg[37]_0\(0),
I3 => sr_araddr(2),
I4 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_payload_i_reg[37]_0\(0),
I3 => sr_araddr(3),
I4 => \m_axi_araddr[3]_INST_0_i_1_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1101115544444400"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => \m_payload_i_reg[37]_0\(0),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => sr_araddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4888884848884888"
)
port map (
I0 => sr_araddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2__0_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3__0_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\,
I5 => sr_araddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0303020303020202"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0_n_0\,
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(0),
I5 => s_axi_arlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000CA"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA55155555AA2AA"
)
port map (
I0 => sr_araddr(2),
I1 => \m_payload_i_reg[37]_0\(0),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
I4 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2__0_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2__0_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AEAAAAAAAAAAAAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3__0_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4__0_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_2_n_0\,
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => sr_araddr(1),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0E02020200000000"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
I1 => sr_arsize(0),
I2 => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_2_n_0\,
I3 => s_axi_arlen_ii(0),
I4 => sr_araddr(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3__0_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => \m_payload_i_reg[37]_0\(0),
I1 => sr_arburst(1),
I2 => sr_arburst(0),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE01000001FE0000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2__0_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3__0_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4__0_n_0\,
I3 => \USE_READ.read_addr_inst/mi_word_intra_len__10\(3),
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(14),
I5 => sr_araddr(3),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4__0_n_0\,
I1 => sr_araddr(1),
I2 => sr_araddr(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(0),
I5 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0000080800000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6__0_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(9),
I3 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7__0_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3__0_n_0\,
I5 => sr_araddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEAEEEAAAAAAAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8__0_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9__0_n_0\,
I2 => sr_arburst(0),
I3 => sr_arburst(1),
I4 => \m_payload_i_reg[37]_0\(0),
I5 => sr_araddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000010000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3__0_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2__0_n_0\,
O => \USE_READ.read_addr_inst/mi_word_intra_len__10\(3)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"54000000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => sr_arburst(1),
I2 => sr_arburst(0),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3330303030200000"
)
port map (
I0 => sr_arsize(0),
I1 => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_2_n_0\,
I2 => sr_araddr(1),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => s_axi_arlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFDF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_payload_i_reg[37]_0\(0),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I5 => sr_araddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA02000000A8"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2__0_n_0\,
I1 => sr_araddr(0),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
I5 => sr_araddr(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"802A2A80"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(13),
I1 => sr_araddr(1),
I2 => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2__0_n_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(10),
I4 => sr_araddr(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0302"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => sr_arsize(0),
O => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4844444484888888"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2__0_n_0\,
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(14),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => sr_arsize(0),
I5 => sr_araddr(3),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000F000C00080"
)
port map (
I0 => sr_araddr(0),
I1 => sr_araddr(1),
I2 => sr_araddr(2),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
I5 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2__0_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545555500000000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => \m_payload_i_reg[37]_0\(0),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => sr_araddr(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(25)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00CA00000000"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_2_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0_n_0\,
I5 => sr_araddr(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(26)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
O => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(13),
I1 => sr_araddr(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(27)
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAEA00000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2__0_n_0\,
I1 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2__0_n_0\,
I5 => sr_araddr(3),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(28)
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\,
I1 => \^m_axi_arregion[3]\(32),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(29)
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sr_araddr(3),
I1 => sr_araddr(2),
I2 => sr_araddr(1),
I3 => sr_araddr(0),
O => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \m_payload_i_reg[37]_0\(0),
I3 => \^m_axi_arregion[3]\(32),
I4 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(30)
);
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I1 => \^m_axi_arregion[3]\(32),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(31)
);
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(32)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(8)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => s_axi_aresetn
);
\cmd_packed_wrap_i1_carry_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3)
);
\cmd_packed_wrap_i1_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(2)
);
\cmd_packed_wrap_i1_carry_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAFAFA88"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arsize(0),
I2 => s_axi_arlen_ii(2),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(1)
);
\cmd_packed_wrap_i1_carry_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAEAEA00"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0)
);
\cmd_packed_wrap_i1_carry_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(7),
I1 => s_axi_arlen_ii(6),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3)
);
\cmd_packed_wrap_i1_carry_i_6__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(4),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(2)
);
\cmd_packed_wrap_i1_carry_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"010010EE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(1)
);
\cmd_packed_wrap_i1_carry_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"11181188"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0)
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00B000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => \m_payload_i_reg[37]_0\(0),
I3 => sr_araddr(0),
I4 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(0)
);
\m_axi_araddr[0]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[0]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000EF000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I3 => \m_payload_i_reg[37]_0\(0),
I4 => sr_araddr(1),
I5 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(1)
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(0),
I2 => s_axi_arlen_ii(1),
O => \m_axi_araddr[1]_INST_0_i_1_n_0\
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F080"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[37]_0\(0),
I2 => sr_araddr(2),
I3 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(2)
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF530FFFFF53F"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => s_axi_arlen_ii(2),
O => \m_axi_araddr[2]_INST_0_i_1_n_0\
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F080"
)
port map (
I0 => \m_axi_araddr[3]_INST_0_i_1_n_0\,
I1 => \m_payload_i_reg[37]_0\(0),
I2 => sr_araddr(3),
I3 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(3)
);
\m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F3F3F3F5F5F0FF"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(3),
I4 => sr_arsize(0),
I5 => sr_arsize(1),
O => \m_axi_araddr[3]_INST_0_i_1_n_0\
);
\m_axi_araddr[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFBBBF"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => \m_payload_i_reg[37]_0\(0),
I4 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
O => \m_axi_araddr[3]_INST_0_i_2_n_0\
);
\m_axi_arburst[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8000"
)
port map (
I0 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I1 => \^m_axi_arregion[3]\(32),
I2 => sr_arburst(1),
I3 => \m_payload_i_reg[37]_0\(0),
I4 => sr_arburst(0),
O => m_axi_arburst(0)
);
\m_axi_arburst[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F0B0"
)
port map (
I0 => sr_arburst(0),
I1 => \m_payload_i_reg[37]_0\(0),
I2 => sr_arburst(1),
I3 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
O => m_axi_arburst(1)
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10151515EFEAEAEA"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(10),
I4 => s_axi_arlen_ii(2),
I5 => \USE_READ.read_addr_inst/access_need_extra_word__3\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(0)
);
\m_axi_arlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000C000A"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(3),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => \m_axi_arlen[0]_INST_0_i_1_n_0\
);
\m_axi_arlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBAAABAAABAAA"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I1 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I2 => \m_axi_arlen[2]_INST_0_i_4_n_0\,
I3 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[0]_INST_0_i_5_n_0\,
I5 => \m_axi_arlen[4]_INST_0_i_6_n_0\,
O => \USE_READ.read_addr_inst/access_need_extra_word__3\
);
\m_axi_arlen[0]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEEECCCCEEEECCCC"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => \m_axi_arlen[0]_INST_0_i_6_n_0\,
I2 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I5 => sr_araddr(0),
O => \m_axi_arlen[0]_INST_0_i_3_n_0\
);
\m_axi_arlen[0]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEAEAEAAA"
)
port map (
I0 => sr_araddr(3),
I1 => s_axi_arlen_ii(1),
I2 => sr_araddr(1),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
O => \m_axi_arlen[0]_INST_0_i_4_n_0\
);
\m_axi_arlen[0]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_araddr(3),
I3 => sr_arburst(0),
I4 => \^m_axi_arregion[3]\(32),
I5 => sr_arburst(1),
O => \m_axi_arlen[0]_INST_0_i_5_n_0\
);
\m_axi_arlen[0]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888800080000000"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(10),
I1 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(2),
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[0]_INST_0_i_6_n_0\
);
\m_axi_arlen[0]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F00000088000000"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_8_n_0\,
I1 => sr_araddr(2),
I2 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_7_n_0\
);
\m_axi_arlen[0]_INST_0_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_8_n_0\
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555AA6A6A"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(9),
I3 => s_axi_arlen_ii(1),
I4 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I5 => \m_axi_arlen[1]_INST_0_i_2_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(1)
);
\m_axi_arlen[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF080"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I3 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I4 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I5 => \m_axi_arlen[1]_INST_0_i_4_n_0\,
O => \m_axi_arlen[1]_INST_0_i_1_n_0\
);
\m_axi_arlen[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(5),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000008800C8"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_arlen[1]_INST_0_i_5_n_0\,
I2 => sr_araddr(2),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_3_n_0\
);
\m_axi_arlen[1]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAEAEAAA"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I2 => \m_axi_arlen[4]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => sr_araddr(3),
O => \m_axi_arlen[1]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
I1 => sr_araddr(3),
I2 => s_axi_arlen_ii(4),
I3 => sr_arburst(0),
I4 => \^m_axi_arregion[3]\(32),
I5 => sr_arburst(1),
O => \m_axi_arlen[1]_INST_0_i_5_n_0\
);
\m_axi_arlen[1]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444040404040"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => sr_araddr(3),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
O => \m_axi_arlen[1]_INST_0_i_6_n_0\
);
\m_axi_arlen[1]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF808000"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_araddr(1),
I2 => sr_araddr(0),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
O => \m_axi_arlen[1]_INST_0_i_7_n_0\
);
\m_axi_arlen[1]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA00"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(0),
I2 => s_axi_arlen_ii(0),
I3 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_8_n_0\
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555AA6A6A"
)
port map (
I0 => \m_axi_arlen[2]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(5),
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(9),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I5 => \m_axi_arlen[2]_INST_0_i_3_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(2)
);
\m_axi_arlen[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFC888C888C888"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[2]_INST_0_i_4_n_0\,
I2 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
I5 => \m_axi_arlen[2]_INST_0_i_5_n_0\,
O => \m_axi_arlen[2]_INST_0_i_1_n_0\
);
\m_axi_arlen[2]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(9)
);
\m_axi_arlen[2]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[2]_INST_0_i_3_n_0\
);
\m_axi_arlen[2]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => sr_arburst(0),
I1 => \^m_axi_arregion[3]\(32),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(3),
O => \m_axi_arlen[2]_INST_0_i_4_n_0\
);
\m_axi_arlen[2]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => sr_arburst(1),
I1 => \^m_axi_arregion[3]\(32),
I2 => sr_arburst(0),
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I5 => s_axi_arlen_ii(5),
O => \m_axi_arlen[2]_INST_0_i_5_n_0\
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00551555FFAAEAAA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I5 => \USE_READ.read_addr_inst/upsized_length__40\(3),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(3)
);
\m_axi_arlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I5 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
O => \m_axi_arlen[3]_INST_0_i_1_n_0\
);
\m_axi_arlen[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010100010000000"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
I3 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(2),
O => \m_axi_arlen[3]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBEAEAEA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(9),
I4 => s_axi_arlen_ii(6),
O => \USE_READ.read_addr_inst/upsized_length__40\(3)
);
\m_axi_arlen[3]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sr_arburst(1),
I1 => \^m_axi_arregion[3]\(32),
I2 => sr_arburst(0),
O => \m_axi_arlen[3]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"E8A0"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => sr_araddr(1),
I2 => sr_araddr(2),
I3 => s_axi_arlen_ii(0),
O => \m_axi_arlen[3]_INST_0_i_5_n_0\
);
\m_axi_arlen[3]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[3]_INST_0_i_6_n_0\
);
\m_axi_arlen[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00007FFFFFFF8000"
)
port map (
I0 => \m_axi_arlen[4]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[4]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(7),
I3 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
I4 => \m_axi_arlen[4]_INST_0_i_4_n_0\,
I5 => \USE_READ.read_addr_inst/upsized_length__40\(4),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(4)
);
\m_axi_arlen[4]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => sr_arburst(0),
I3 => \^m_axi_arregion[3]\(32),
I4 => sr_arburst(1),
O => \m_axi_arlen[4]_INST_0_i_1_n_0\
);
\m_axi_arlen[4]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
O => \m_axi_arlen[4]_INST_0_i_2_n_0\
);
\m_axi_arlen[4]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => sr_araddr(3),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_arlen[4]_INST_0_i_6_n_0\,
O => \m_axi_arlen[4]_INST_0_i_3_n_0\
);
\m_axi_arlen[4]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EA000000"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(5),
I4 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[4]_INST_0_i_4_n_0\
);
\m_axi_arlen[4]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F888F888"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(10),
I1 => s_axi_arlen_ii(6),
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(9),
I3 => s_axi_arlen_ii(7),
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => \USE_READ.read_addr_inst/upsized_length__40\(4)
);
\m_axi_arlen[4]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCE8E8C0E8E8C0C0"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => sr_araddr(2),
I2 => s_axi_arlen_ii(2),
I3 => sr_araddr(0),
I4 => sr_araddr(1),
I5 => s_axi_arlen_ii(0),
O => \m_axi_arlen[4]_INST_0_i_6_n_0\
);
\m_axi_arlen[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"596A6A6A"
)
port map (
I0 => \m_axi_arlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(10),
I4 => s_axi_arlen_ii(7),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(5)
);
\m_axi_arlen[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000000000000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(6),
I4 => s_axi_arlen_ii(5),
I5 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[5]_INST_0_i_1_n_0\
);
\m_axi_arlen[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(10)
);
\m_axi_arlen[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => s_axi_arlen_ii(7),
I4 => s_axi_arlen_ii(6),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(6)
);
\m_axi_arlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888800080000000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(10),
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(2),
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[6]_INST_0_i_1_n_0\
);
\m_axi_arlen[6]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arburst(1),
I2 => \^m_axi_arregion[3]\(32),
I3 => sr_arburst(0),
I4 => s_axi_arlen_ii(4),
O => \m_axi_arlen[6]_INST_0_i_2_n_0\
);
\m_axi_arlen[6]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^m_axi_arregion[3]\(32),
O => \m_axi_arlen[6]_INST_0_i_3_n_0\
);
\m_axi_arlen[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5700"
)
port map (
I0 => \^m_axi_arregion[3]\(32),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(7),
O => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[34]\(7)
);
\m_axi_arsize[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F100"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
I3 => sr_arsize(0),
O => m_axi_arsize(0)
);
\m_axi_arsize[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F100"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
I3 => sr_arsize(1),
O => m_axi_arsize(1)
);
\m_axi_arsize[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000002FFFFFFFF"
)
port map (
I0 => \m_axi_arsize[1]_INST_0_i_2_n_0\,
I1 => \m_axi_arsize[2]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arsize[2]_INST_0_i_3_n_0\,
I5 => \^m_axi_arregion[3]\(32),
O => \m_axi_arsize[1]_INST_0_i_1_n_0\
);
\m_axi_arsize[1]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
O => \m_axi_arsize[1]_INST_0_i_2_n_0\
);
\m_axi_arsize[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFE000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^m_axi_arregion[3]\(32),
I3 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I4 => sr_arsize(2),
O => m_axi_arsize(2)
);
\m_axi_arsize[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(2),
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arsize[2]_INST_0_i_2_n_0\,
I5 => \m_axi_arsize[2]_INST_0_i_3_n_0\,
O => \m_axi_arsize[2]_INST_0_i_1_n_0\
);
\m_axi_arsize[2]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
O => \m_axi_arsize[2]_INST_0_i_2_n_0\
);
\m_axi_arsize[2]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
O => \m_axi_arsize[2]_INST_0_i_3_n_0\
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_arvalid\,
O => \m_payload_i[31]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(0),
Q => sr_araddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(10),
Q => \^m_axi_arregion[3]\(6),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(11),
Q => \^m_axi_arregion[3]\(7),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(12),
Q => \^m_axi_arregion[3]\(8),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(13),
Q => \^m_axi_arregion[3]\(9),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(14),
Q => \^m_axi_arregion[3]\(10),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(15),
Q => \^m_axi_arregion[3]\(11),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(16),
Q => \^m_axi_arregion[3]\(12),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(17),
Q => \^m_axi_arregion[3]\(13),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(18),
Q => \^m_axi_arregion[3]\(14),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(19),
Q => \^m_axi_arregion[3]\(15),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(1),
Q => sr_araddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(20),
Q => \^m_axi_arregion[3]\(16),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(21),
Q => \^m_axi_arregion[3]\(17),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(22),
Q => \^m_axi_arregion[3]\(18),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(23),
Q => \^m_axi_arregion[3]\(19),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(24),
Q => \^m_axi_arregion[3]\(20),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(25),
Q => \^m_axi_arregion[3]\(21),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(26),
Q => \^m_axi_arregion[3]\(22),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(27),
Q => \^m_axi_arregion[3]\(23),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(28),
Q => \^m_axi_arregion[3]\(24),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(29),
Q => \^m_axi_arregion[3]\(25),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(2),
Q => sr_araddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(30),
Q => \^m_axi_arregion[3]\(26),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(31),
Q => \^m_axi_arregion[3]\(27),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(32),
Q => \^m_axi_arregion[3]\(28),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(33),
Q => \^m_axi_arregion[3]\(29),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(34),
Q => \^m_axi_arregion[3]\(30),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(35),
Q => sr_arsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(36),
Q => sr_arsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(37),
Q => sr_arsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(38),
Q => sr_arburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(39),
Q => sr_arburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(3),
Q => sr_araddr(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(40),
Q => \^m_axi_arregion[3]\(31),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(41),
Q => \^m_axi_arregion[3]\(32),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(42),
Q => \^m_axi_arregion[3]\(33),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(43),
Q => \^m_axi_arregion[3]\(34),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(44),
Q => s_axi_arlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(45),
Q => s_axi_arlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(46),
Q => s_axi_arlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(47),
Q => s_axi_arlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(48),
Q => s_axi_arlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(49),
Q => s_axi_arlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(4),
Q => \^m_axi_arregion[3]\(0),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(50),
Q => s_axi_arlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(51),
Q => s_axi_arlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(52),
Q => \^m_axi_arregion[3]\(35),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(53),
Q => \^m_axi_arregion[3]\(36),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(54),
Q => \^m_axi_arregion[3]\(37),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(55),
Q => \^m_axi_arregion[3]\(38),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(56),
Q => \^m_axi_arregion[3]\(39),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(57),
Q => \^m_axi_arregion[3]\(40),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(58),
Q => \^m_axi_arregion[3]\(41),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(5),
Q => \^m_axi_arregion[3]\(1),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(59),
Q => \^m_axi_arregion[3]\(42),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(60),
Q => \^m_axi_arregion[3]\(43),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(6),
Q => \^m_axi_arregion[3]\(2),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(7),
Q => \^m_axi_arregion[3]\(3),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(8),
Q => \^m_axi_arregion[3]\(4),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1__0_n_0\,
D => \s_axi_arregion[3]\(9),
Q => \^m_axi_arregion[3]\(5),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7F007F00000000"
)
port map (
I0 => cmd_push_block_reg,
I1 => m_axi_arready,
I2 => s_axi_aresetn_0,
I3 => \^s_axi_arready\,
I4 => s_axi_arvalid,
I5 => \^s_ready_i_reg_0\,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_arvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"757F0000"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => \USE_RTL_VALID_WRITE.buffer_Full_q_reg\,
I2 => \^sr_arvalid\,
I3 => s_axi_arvalid,
I4 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_arready\,
R => '0'
);
\sub_sized_wrap0_carry_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010111"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1)
);
\sub_sized_wrap0_carry_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00070077"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0)
);
\sub_sized_wrap0_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(7),
I1 => s_axi_arlen_ii(6),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(3)
);
\sub_sized_wrap0_carry_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(4),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(2)
);
\sub_sized_wrap0_carry_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"010010EE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(1)
);
\sub_sized_wrap0_carry_i_6__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"11181188"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 is
port (
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
sr_awvalid : out STD_LOGIC;
\in\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 1 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_block_reg : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
\m_payload_i_reg[50]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 is
signal \^q\ : STD_LOGIC_VECTOR ( 41 downto 0 );
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_10_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_11_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst/cmd_next_word_ii__17\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \USE_WRITE.write_addr_inst/mi_word_intra_len__10\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \USE_WRITE.write_addr_inst/upsized_length__40\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^in\ : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \m_axi_awaddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[4]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awaddr[5]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_awlen[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_awlen[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awlen[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_awlen[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_awlen[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_awlen[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_awlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_awlen[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_awsize[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awsize[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_awsize[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_axi_awlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal sr_awaddr : STD_LOGIC_VECTOR ( 5 downto 0 );
signal sr_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_awvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_1\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_10\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \m_axi_awaddr[0]_INST_0_i_1\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \m_axi_awaddr[2]_INST_0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \m_axi_awaddr[3]_INST_0_i_2\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \m_axi_awaddr[4]_INST_0_i_3\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \m_axi_awaddr[4]_INST_0_i_6\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \m_axi_awaddr[4]_INST_0_i_7\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_12\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_6\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_7\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_8\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_9\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \m_axi_awburst[0]_INST_0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \m_axi_awburst[1]_INST_0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_10\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_11\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_12\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_6\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_7\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \m_axi_awlen[0]_INST_0_i_8\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \m_axi_awlen[1]_INST_0_i_4\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \m_axi_awlen[1]_INST_0_i_6\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \m_axi_awlen[1]_INST_0_i_7\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \m_axi_awlen[3]_INST_0_i_2\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \m_axi_awlen[4]_INST_0_i_2\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \m_axi_awlen[4]_INST_0_i_5\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \m_axi_awlen[5]_INST_0_i_1\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \m_axi_awlen[6]_INST_0_i_2\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \m_axi_awlen[6]_INST_0_i_3\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \m_axi_awlen[7]_INST_0\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \m_axi_awsize[0]_INST_0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \m_axi_awsize[1]_INST_0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \m_axi_awsize[2]_INST_0\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \m_axi_awsize[2]_INST_0_i_2\ : label is "soft_lutpair153";
begin
Q(41 downto 0) <= \^q\(41 downto 0);
\in\(32 downto 0) <= \^in\(32 downto 0);
p_0_in(0) <= \^p_0_in\(0);
s_axi_awready <= \^s_axi_awready\;
sr_awvalid <= \^sr_awvalid\;
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(0),
I2 => sr_awsize(1),
O => \^in\(10)
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFDFFFDF"
)
port map (
I0 => CO(0),
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => s_axi_awlen_ii(0),
I4 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
O => \^in\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAEFEA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I1 => s_axi_awlen_ii(0),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(1),
I5 => sr_awsize(2),
O => \^in\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => CO(0),
O => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\,
I1 => CO(0),
I2 => sr_awburst(0),
I3 => sr_awburst(1),
O => \^in\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000FAC000000AC"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => s_axi_awlen_ii(2),
I2 => sr_awsize(0),
I3 => sr_awsize(1),
I4 => sr_awsize(2),
I5 => s_axi_awlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFBAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => \m_axi_awaddr[5]_INST_0_i_1_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\,
O => \^in\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030200"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(3),
O => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => CO(0),
I3 => sr_awaddr(2),
I4 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
O => \^in\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"23002200"
)
port map (
I0 => \m_axi_awaddr[3]_INST_0_i_2_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I2 => \m_axi_awaddr[5]_INST_0_i_1_n_0\,
I3 => sr_awaddr(3),
I4 => sr_awsize(1),
O => \^in\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"001D001F00E000E0"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => s_axi_awlen_ii(0),
I3 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I4 => CO(0),
I5 => sr_awaddr(0),
O => \^in\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4114114441140000"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
I3 => sr_awaddr(1),
I4 => \m_axi_awaddr[5]_INST_0_i_1_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
O => \^in\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000A800"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => s_axi_awlen_ii(0),
I4 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA55155555AA2AA"
)
port map (
I0 => sr_awaddr(2),
I1 => CO(0),
I2 => sr_awburst(0),
I3 => sr_awburst(1),
I4 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\,
O => \^in\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF20000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
I2 => s_axi_awlen_ii(0),
I3 => sr_awaddr(1),
I4 => sr_awaddr(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => CO(0),
I1 => sr_awburst(1),
I2 => sr_awburst(0),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F444F440000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\,
I1 => sr_awaddr(1),
I2 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[0]_INST_0_i_6_n_0\,
I4 => sr_awburst(1),
I5 => sr_awburst(0),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEFFFEF"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(1),
I2 => s_axi_awlen_ii(1),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8484848484848448"
)
port map (
I0 => sr_awaddr(3),
I1 => \^in\(14),
I2 => \USE_WRITE.write_addr_inst/mi_word_intra_len__10\(3),
I3 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\,
O => \^in\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_10_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"000008FF000008A8"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => sr_awaddr(0),
I2 => sr_awsize(0),
I3 => sr_awsize(1),
I4 => sr_awsize(2),
I5 => s_axi_awlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_11_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000010000000"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(0),
I2 => sr_awsize(1),
I3 => s_axi_awlen_ii(1),
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\,
O => \USE_WRITE.write_addr_inst/mi_word_intra_len__10\(3)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F88888800000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\,
I1 => sr_awaddr(2),
I2 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\,
I3 => s_axi_awlen_ii(2),
I4 => \m_axi_awlen[0]_INST_0_i_11_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"2202200020002000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
I2 => sr_awsize(0),
I3 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9_n_0\,
I4 => s_axi_awlen_ii(2),
I5 => \m_axi_awlen[1]_INST_0_i_6_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"A800"
)
port map (
I0 => sr_awaddr(2),
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_10_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF800080008000"
)
port map (
I0 => \m_axi_awlen[1]_INST_0_i_7_n_0\,
I1 => sr_awaddr(0),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(0),
I4 => sr_awaddr(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_11_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => s_axi_awlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => s_axi_awlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => sr_awaddr(1),
I2 => sr_awaddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FBFF"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => CO(0),
I2 => sr_awburst(0),
I3 => sr_awburst(1),
I4 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I5 => sr_awaddr(0),
O => \^in\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001111000000000"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awaddr(0),
I3 => sr_awsize(0),
I4 => sr_awaddr(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_2_n_0\,
O => \^in\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFDFDFFFDF"
)
port map (
I0 => CO(0),
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => s_axi_awlen_ii(1),
I4 => sr_awsize(0),
I5 => s_axi_awlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFF0000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\,
I1 => CO(0),
I2 => sr_awburst(0),
I3 => sr_awburst(1),
I4 => \USE_WRITE.write_addr_inst/cmd_next_word_ii__17\(2),
O => \^in\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0F5F7000F0A08"
)
port map (
I0 => sr_awaddr(1),
I1 => sr_awaddr(0),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => sr_awsize(1),
I5 => sr_awaddr(2),
O => \USE_WRITE.write_addr_inst/cmd_next_word_ii__17\(2)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2822222282888888"
)
port map (
I0 => \^in\(14),
I1 => sr_awaddr(3),
I2 => sr_awsize(2),
I3 => sr_awsize(0),
I4 => sr_awsize(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\,
O => \^in\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000F000C00080"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awaddr(1),
I2 => sr_awaddr(2),
I3 => sr_awsize(2),
I4 => sr_awsize(0),
I5 => sr_awsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545555500000000"
)
port map (
I0 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_awlen_ii(0),
I2 => CO(0),
I3 => sr_awburst(0),
I4 => sr_awburst(1),
I5 => sr_awaddr(0),
O => \^in\(25)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444440444000"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
I1 => sr_awaddr(1),
I2 => s_axi_awlen_ii(0),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
O => \^in\(26)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFF0000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\,
I1 => CO(0),
I2 => sr_awburst(0),
I3 => sr_awburst(1),
I4 => sr_awaddr(2),
O => \^in\(27)
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAEA00000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_1_n_0\,
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I5 => sr_awaddr(3),
O => \^in\(28)
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \^q\(30),
I1 => \m_payload_i_reg[50]_0\(0),
I2 => sr_awburst(1),
I3 => sr_awburst(0),
I4 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I5 => \m_axi_awsize[2]_INST_0_i_1_n_0\,
O => \^in\(29)
);
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => CO(0),
I3 => \^q\(30),
I4 => \m_axi_awsize[2]_INST_0_i_1_n_0\,
O => \^in\(30)
);
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => \m_axi_awsize[2]_INST_0_i_1_n_0\,
I1 => \^q\(30),
I2 => sr_awburst(0),
I3 => sr_awburst(1),
O => \^in\(31)
);
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
O => \^in\(32)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
O => \^in\(8)
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
O => \^in\(9)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => '1',
Q => \^p_0_in\(0),
R => s_axi_aresetn
);
cmd_packed_wrap_i1_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_awlen_ii(6),
I1 => s_axi_awlen_ii(7),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3)
);
cmd_packed_wrap_i1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => s_axi_awlen_ii(5),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(2)
);
cmd_packed_wrap_i1_carry_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"EEECEEE0"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => s_axi_awlen_ii(3),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
I4 => sr_awsize(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(1)
);
cmd_packed_wrap_i1_carry_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"EAEAEA00"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(0),
I2 => sr_awsize(1),
I3 => s_axi_awlen_ii(1),
I4 => s_axi_awlen_ii(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0)
);
cmd_packed_wrap_i1_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awlen_ii(7),
I1 => s_axi_awlen_ii(6),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3)
);
cmd_packed_wrap_i1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => s_axi_awlen_ii(4),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(2)
);
cmd_packed_wrap_i1_carry_i_7: unisim.vcomponents.LUT5
generic map(
INIT => X"010E100E"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(1),
I2 => s_axi_awlen_ii(3),
I3 => s_axi_awlen_ii(2),
I4 => sr_awsize(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(1)
);
cmd_packed_wrap_i1_carry_i_8: unisim.vcomponents.LUT5
generic map(
INIT => X"11111888"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => s_axi_awlen_ii(1),
I2 => sr_awsize(1),
I3 => sr_awsize(0),
I4 => sr_awsize(2),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0)
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"EF00AA00"
)
port map (
I0 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
I1 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I2 => s_axi_awlen_ii(0),
I3 => sr_awaddr(0),
I4 => CO(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[0]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(1),
I2 => sr_awsize(0),
O => \m_axi_awaddr[0]_INST_0_i_1_n_0\
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFF0000AAAA0000"
)
port map (
I0 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => \m_axi_awaddr[5]_INST_0_i_1_n_0\,
I4 => sr_awaddr(1),
I5 => CO(0),
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E0A0"
)
port map (
I0 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
I1 => \m_axi_awaddr[2]_INST_0_i_1_n_0\,
I2 => sr_awaddr(2),
I3 => CO(0),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBAAFAAFFF"
)
port map (
I0 => sr_awsize(2),
I1 => s_axi_awlen_ii(0),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => s_axi_awlen_ii(2),
I5 => sr_awsize(1),
O => \m_axi_awaddr[2]_INST_0_i_1_n_0\
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBA0000AAAA0000"
)
port map (
I0 => \m_axi_awaddr[3]_INST_0_i_1_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_1_n_0\,
I2 => sr_awsize(1),
I3 => \m_axi_awaddr[3]_INST_0_i_2_n_0\,
I4 => sr_awaddr(3),
I5 => CO(0),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[3]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFBBBF"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => CO(0),
I4 => \m_axi_awsize[1]_INST_0_i_1_n_0\,
O => \m_axi_awaddr[3]_INST_0_i_1_n_0\
);
\m_axi_awaddr[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1015"
)
port map (
I0 => sr_awsize(1),
I1 => s_axi_awlen_ii(2),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(3),
I4 => sr_awsize(2),
O => \m_axi_awaddr[3]_INST_0_i_2_n_0\
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBAAAAAAA"
)
port map (
I0 => \m_axi_awaddr[4]_INST_0_i_1_n_0\,
I1 => s_axi_awlen_ii(1),
I2 => sr_awaddr(4),
I3 => sr_awsize(1),
I4 => sr_awsize(0),
I5 => \m_axi_awaddr[4]_INST_0_i_2_n_0\,
O => m_axi_awaddr(4)
);
\m_axi_awaddr[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFECC0000"
)
port map (
I0 => \m_axi_awaddr[4]_INST_0_i_3_n_0\,
I1 => \m_axi_awaddr[4]_INST_0_i_4_n_0\,
I2 => sr_awsize(1),
I3 => sr_awsize(2),
I4 => sr_awaddr(4),
I5 => \m_axi_awaddr[4]_INST_0_i_5_n_0\,
O => \m_axi_awaddr[4]_INST_0_i_1_n_0\
);
\m_axi_awaddr[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAAABAAAAA"
)
port map (
I0 => \m_axi_awaddr[4]_INST_0_i_6_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_8_n_0\,
I2 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I3 => sr_awaddr(4),
I4 => \m_axi_awaddr[4]_INST_0_i_7_n_0\,
I5 => \m_axi_awaddr[4]_INST_0_i_8_n_0\,
O => \m_axi_awaddr[4]_INST_0_i_2_n_0\
);
\m_axi_awaddr[4]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => sr_awsize(0),
I1 => s_axi_awlen_ii(0),
O => \m_axi_awaddr[4]_INST_0_i_3_n_0\
);
\m_axi_awaddr[4]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFFFFFFFFFF"
)
port map (
I0 => CO(0),
I1 => \^q\(30),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => sr_awburst(1),
I4 => sr_awburst(0),
I5 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
O => \m_axi_awaddr[4]_INST_0_i_4_n_0\
);
\m_axi_awaddr[4]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"03004400"
)
port map (
I0 => s_axi_awlen_ii(2),
I1 => sr_awsize(1),
I2 => s_axi_awlen_ii(3),
I3 => sr_awaddr(4),
I4 => sr_awsize(0),
O => \m_axi_awaddr[4]_INST_0_i_5_n_0\
);
\m_axi_awaddr[4]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => sr_awaddr(4),
I2 => sr_awsize(0),
I3 => sr_awsize(1),
I4 => sr_awsize(2),
O => \m_axi_awaddr[4]_INST_0_i_6_n_0\
);
\m_axi_awaddr[4]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030200"
)
port map (
I0 => s_axi_awlen_ii(3),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(4),
O => \m_axi_awaddr[4]_INST_0_i_7_n_0\
);
\m_axi_awaddr[4]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"02CC02C0020C0200"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => sr_awsize(1),
I2 => sr_awsize(0),
I3 => sr_awsize(2),
I4 => s_axi_awlen_ii(2),
I5 => s_axi_awlen_ii(1),
O => \m_axi_awaddr[4]_INST_0_i_8_n_0\
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF08"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awaddr(5),
I2 => \m_axi_awaddr[5]_INST_0_i_1_n_0\,
I3 => \m_axi_awaddr[5]_INST_0_i_2_n_0\,
I4 => \m_axi_awaddr[5]_INST_0_i_3_n_0\,
I5 => \m_axi_awaddr[5]_INST_0_i_4_n_0\,
O => m_axi_awaddr(5)
);
\m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(1),
O => \m_axi_awaddr[5]_INST_0_i_1_n_0\
);
\m_axi_awaddr[5]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFBFFFFFF"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_11_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I2 => \m_axi_awaddr[5]_INST_0_i_12_n_0\,
I3 => \m_payload_i_reg[50]_0\(0),
I4 => \^q\(30),
I5 => CO(0),
O => \m_axi_awaddr[5]_INST_0_i_10_n_0\
);
\m_axi_awaddr[5]_INST_0_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
O => \m_axi_awaddr[5]_INST_0_i_11_n_0\
);
\m_axi_awaddr[5]_INST_0_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
O => \m_axi_awaddr[5]_INST_0_i_12_n_0\
);
\m_axi_awaddr[5]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00088808"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awaddr(5),
I2 => s_axi_awlen_ii(3),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(2),
O => \m_axi_awaddr[5]_INST_0_i_2_n_0\
);
\m_axi_awaddr[5]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000EE00000"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_5_n_0\,
I1 => \m_axi_awaddr[5]_INST_0_i_6_n_0\,
I2 => sr_awaddr(4),
I3 => sr_awaddr(5),
I4 => \m_axi_awaddr[5]_INST_0_i_7_n_0\,
I5 => \m_axi_awaddr[5]_INST_0_i_8_n_0\,
O => \m_axi_awaddr[5]_INST_0_i_3_n_0\
);
\m_axi_awaddr[5]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000010D0000"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => sr_awsize(0),
I2 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
I3 => s_axi_awlen_ii(4),
I4 => sr_awaddr(5),
I5 => \m_axi_awaddr[5]_INST_0_i_10_n_0\,
O => \m_axi_awaddr[5]_INST_0_i_4_n_0\
);
\m_axi_awaddr[5]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"22CC22C0220C2200"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_1_n_0\,
I1 => sr_awsize(1),
I2 => sr_awsize(0),
I3 => sr_awsize(2),
I4 => s_axi_awlen_ii(3),
I5 => s_axi_awlen_ii(2),
O => \m_axi_awaddr[5]_INST_0_i_5_n_0\
);
\m_axi_awaddr[5]_INST_0_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"02030200"
)
port map (
I0 => s_axi_awlen_ii(4),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(5),
O => \m_axi_awaddr[5]_INST_0_i_6_n_0\
);
\m_axi_awaddr[5]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sr_awaddr(1),
I1 => sr_awaddr(0),
I2 => sr_awaddr(3),
I3 => sr_awaddr(2),
O => \m_axi_awaddr[5]_INST_0_i_7_n_0\
);
\m_axi_awaddr[5]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFBFFF"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => \^q\(30),
I4 => CO(0),
O => \m_axi_awaddr[5]_INST_0_i_8_n_0\
);
\m_axi_awaddr[5]_INST_0_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
O => \m_axi_awaddr[5]_INST_0_i_9_n_0\
);
\m_axi_awburst[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8000"
)
port map (
I0 => \m_axi_awsize[2]_INST_0_i_1_n_0\,
I1 => CO(0),
I2 => \^q\(30),
I3 => sr_awburst(1),
I4 => sr_awburst(0),
O => m_axi_awburst(0)
);
\m_axi_awburst[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F0D0"
)
port map (
I0 => CO(0),
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => \m_axi_awsize[1]_INST_0_i_1_n_0\,
O => m_axi_awburst(1)
);
\m_axi_awlen[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55565656"
)
port map (
I0 => \USE_WRITE.write_addr_inst/upsized_length__40\(0),
I1 => \m_axi_awlen[0]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[0]_INST_0_i_3_n_0\,
I3 => \m_axi_awlen[4]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[1]_INST_0_i_1_n_0\,
O => \^in\(0)
);
\m_axi_awlen[0]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00EAEA"
)
port map (
I0 => \m_axi_awaddr[4]_INST_0_i_7_n_0\,
I1 => \^in\(10),
I2 => s_axi_awlen_ii(2),
I3 => s_axi_awlen_ii(0),
I4 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
O => \USE_WRITE.write_addr_inst/upsized_length__40\(0)
);
\m_axi_awlen[0]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => \m_axi_awlen[5]_INST_0_i_3_n_0\,
O => \m_axi_awlen[0]_INST_0_i_10_n_0\
);
\m_axi_awlen[0]_INST_0_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => sr_awaddr(0),
I1 => sr_awaddr(1),
O => \m_axi_awlen[0]_INST_0_i_11_n_0\
);
\m_axi_awlen[0]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230022"
)
port map (
I0 => sr_awaddr(3),
I1 => sr_awsize(2),
I2 => sr_awsize(1),
I3 => sr_awsize(0),
I4 => s_axi_awlen_ii(3),
O => \m_axi_awlen[0]_INST_0_i_12_n_0\
);
\m_axi_awlen[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => \m_axi_awlen[0]_INST_0_i_4_n_0\,
I1 => sr_awaddr(3),
I2 => \m_axi_awlen[0]_INST_0_i_5_n_0\,
I3 => \m_axi_awlen[0]_INST_0_i_6_n_0\,
I4 => \m_axi_awlen[4]_INST_0_i_2_n_0\,
O => \m_axi_awlen[0]_INST_0_i_2_n_0\
);
\m_axi_awlen[0]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0FF00FF00"
)
port map (
I0 => \m_axi_awlen[0]_INST_0_i_7_n_0\,
I1 => sr_awaddr(3),
I2 => \m_axi_awlen[0]_INST_0_i_8_n_0\,
I3 => \m_axi_awlen[0]_INST_0_i_9_n_0\,
I4 => \m_axi_awlen[0]_INST_0_i_10_n_0\,
I5 => \m_axi_awlen[4]_INST_0_i_2_n_0\,
O => \m_axi_awlen[0]_INST_0_i_3_n_0\
);
\m_axi_awlen[0]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF00C080800000"
)
port map (
I0 => \m_axi_awlen[1]_INST_0_i_7_n_0\,
I1 => \m_axi_awlen[0]_INST_0_i_11_n_0\,
I2 => s_axi_awlen_ii(0),
I3 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
I4 => sr_awaddr(2),
I5 => s_axi_awlen_ii(2),
O => \m_axi_awlen[0]_INST_0_i_4_n_0\
);
\m_axi_awlen[0]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EECCE000E000"
)
port map (
I0 => sr_awaddr(2),
I1 => s_axi_awlen_ii(2),
I2 => sr_awaddr(3),
I3 => \m_axi_awlen[1]_INST_0_i_7_n_0\,
I4 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[0]_INST_0_i_5_n_0\
);
\m_axi_awlen[0]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => sr_awaddr(0),
I1 => s_axi_awlen_ii(1),
I2 => s_axi_awlen_ii(0),
O => \m_axi_awlen[0]_INST_0_i_6_n_0\
);
\m_axi_awlen[0]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF808000"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => sr_awaddr(1),
I2 => sr_awaddr(0),
I3 => s_axi_awlen_ii(2),
I4 => sr_awaddr(2),
O => \m_axi_awlen[0]_INST_0_i_7_n_0\
);
\m_axi_awlen[0]_INST_0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => s_axi_awlen_ii(3),
I1 => sr_awsize(0),
I2 => sr_awsize(1),
I3 => sr_awsize(2),
O => \m_axi_awlen[0]_INST_0_i_8_n_0\
);
\m_axi_awlen[0]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"8080800000000000"
)
port map (
I0 => \m_axi_awlen[4]_INST_0_i_2_n_0\,
I1 => s_axi_awlen_ii(1),
I2 => sr_awaddr(1),
I3 => s_axi_awlen_ii(2),
I4 => sr_awaddr(2),
I5 => \m_axi_awlen[0]_INST_0_i_12_n_0\,
O => \m_axi_awlen[0]_INST_0_i_9_n_0\
);
\m_axi_awlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00003777FFFFC888"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[4]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[1]_INST_0_i_1_n_0\,
I3 => s_axi_awlen_ii(2),
I4 => \m_axi_awlen[1]_INST_0_i_2_n_0\,
I5 => \USE_WRITE.write_addr_inst/upsized_length__40\(1),
O => \^in\(1)
);
\m_axi_awlen[1]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8808080"
)
port map (
I0 => \^in\(10),
I1 => sr_awaddr(3),
I2 => s_axi_awlen_ii(1),
I3 => s_axi_awlen_ii(0),
I4 => sr_awaddr(2),
O => \m_axi_awlen[1]_INST_0_i_1_n_0\
);
\m_axi_awlen[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222222200000000"
)
port map (
I0 => \m_axi_awlen[1]_INST_0_i_4_n_0\,
I1 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I2 => \m_axi_awlen[1]_INST_0_i_5_n_0\,
I3 => s_axi_awlen_ii(1),
I4 => \m_axi_awlen[1]_INST_0_i_6_n_0\,
I5 => \m_axi_awlen[3]_INST_0_i_2_n_0\,
O => \m_axi_awlen[1]_INST_0_i_2_n_0\
);
\m_axi_awlen[1]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00EAEA"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_6_n_0\,
I1 => \^in\(10),
I2 => s_axi_awlen_ii(3),
I3 => s_axi_awlen_ii(1),
I4 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
O => \USE_WRITE.write_addr_inst/upsized_length__40\(1)
);
\m_axi_awlen[1]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \m_axi_awlen[0]_INST_0_i_7_n_0\,
I1 => s_axi_awlen_ii(3),
I2 => sr_awaddr(3),
O => \m_axi_awlen[1]_INST_0_i_4_n_0\
);
\m_axi_awlen[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"C000EEEEC000E0A0"
)
port map (
I0 => sr_awaddr(2),
I1 => s_axi_awlen_ii(2),
I2 => sr_awaddr(3),
I3 => \m_axi_awlen[1]_INST_0_i_7_n_0\,
I4 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[1]_INST_0_i_5_n_0\
);
\m_axi_awlen[1]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => sr_awaddr(0),
I2 => sr_awaddr(1),
O => \m_axi_awlen[1]_INST_0_i_6_n_0\
);
\m_axi_awlen[1]_INST_0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(2),
O => \m_axi_awlen[1]_INST_0_i_7_n_0\
);
\m_axi_awlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"151515EA15EA15EA"
)
port map (
I0 => \m_axi_awlen[2]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[4]_INST_0_i_2_n_0\,
I3 => \m_axi_awlen[2]_INST_0_i_2_n_0\,
I4 => \m_axi_awlen[3]_INST_0_i_4_n_0\,
I5 => s_axi_awlen_ii(4),
O => \^in\(2)
);
\m_axi_awlen[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA000000EA000000"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[4]_INST_0_i_4_n_0\,
I2 => s_axi_awlen_ii(5),
I3 => \m_axi_awlen[4]_INST_0_i_2_n_0\,
I4 => s_axi_awlen_ii(4),
I5 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
O => \m_axi_awlen[2]_INST_0_i_1_n_0\
);
\m_axi_awlen[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF541000005410"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(6),
I3 => s_axi_awlen_ii(5),
I4 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
I5 => s_axi_awlen_ii(2),
O => \m_axi_awlen[2]_INST_0_i_2_n_0\
);
\m_axi_awlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"151515EA15EA15EA"
)
port map (
I0 => \m_axi_awlen[3]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I2 => \m_axi_awlen[3]_INST_0_i_2_n_0\,
I3 => \m_axi_awlen[3]_INST_0_i_3_n_0\,
I4 => \m_axi_awlen[3]_INST_0_i_4_n_0\,
I5 => s_axi_awlen_ii(5),
O => \^in\(3)
);
\m_axi_awlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA000000EA000000"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[4]_INST_0_i_4_n_0\,
I2 => s_axi_awlen_ii(6),
I3 => \m_axi_awlen[3]_INST_0_i_2_n_0\,
I4 => s_axi_awlen_ii(5),
I5 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
O => \m_axi_awlen[3]_INST_0_i_1_n_0\
);
\m_axi_awlen[3]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^q\(30),
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => s_axi_awlen_ii(4),
O => \m_axi_awlen[3]_INST_0_i_2_n_0\
);
\m_axi_awlen[3]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF541000005410"
)
port map (
I0 => \m_axi_awaddr[5]_INST_0_i_9_n_0\,
I1 => sr_awsize(0),
I2 => s_axi_awlen_ii(7),
I3 => s_axi_awlen_ii(6),
I4 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
I5 => s_axi_awlen_ii(3),
O => \m_axi_awlen[3]_INST_0_i_3_n_0\
);
\m_axi_awlen[3]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200020002000000"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => \^q\(30),
I4 => sr_awburst(0),
I5 => sr_awburst(1),
O => \m_axi_awlen[3]_INST_0_i_4_n_0\
);
\m_axi_awlen[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"15555555EAAAAAAA"
)
port map (
I0 => \m_axi_awlen[4]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_awlen_ii(5),
I3 => \m_axi_awlen[4]_INST_0_i_2_n_0\,
I4 => s_axi_awlen_ii(4),
I5 => \USE_WRITE.write_addr_inst/upsized_length__40\(4),
O => \^in\(4)
);
\m_axi_awlen[4]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAA0000"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[4]_INST_0_i_4_n_0\,
I2 => \m_axi_awaddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_awlen_ii(7),
I4 => \m_axi_awlen[6]_INST_0_i_1_n_0\,
O => \m_axi_awlen[4]_INST_0_i_1_n_0\
);
\m_axi_awlen[4]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => \^q\(30),
O => \m_axi_awlen[4]_INST_0_i_2_n_0\
);
\m_axi_awlen[4]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F888F888"
)
port map (
I0 => s_axi_awlen_ii(7),
I1 => \^in\(9),
I2 => \^in\(10),
I3 => s_axi_awlen_ii(6),
I4 => s_axi_awlen_ii(4),
I5 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
O => \USE_WRITE.write_addr_inst/upsized_length__40\(4)
);
\m_axi_awlen[4]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF00FF808000"
)
port map (
I0 => \m_axi_awlen[1]_INST_0_i_6_n_0\,
I1 => s_axi_awlen_ii(1),
I2 => \m_axi_awlen[4]_INST_0_i_5_n_0\,
I3 => sr_awaddr(3),
I4 => s_axi_awlen_ii(3),
I5 => \m_axi_awlen[0]_INST_0_i_7_n_0\,
O => \m_axi_awlen[4]_INST_0_i_4_n_0\
);
\m_axi_awlen[4]_INST_0_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_awaddr(2),
I1 => s_axi_awlen_ii(2),
O => \m_axi_awlen[4]_INST_0_i_5_n_0\
);
\m_axi_awlen[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F7FF080"
)
port map (
I0 => s_axi_awlen_ii(7),
I1 => \m_axi_awlen[5]_INST_0_i_1_n_0\,
I2 => \m_axi_awlen[6]_INST_0_i_1_n_0\,
I3 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I4 => \USE_WRITE.write_addr_inst/upsized_length__40\(5),
O => \^in\(5)
);
\m_axi_awlen[5]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080000"
)
port map (
I0 => \m_axi_awlen[5]_INST_0_i_3_n_0\,
I1 => sr_awsize(0),
I2 => sr_awsize(2),
I3 => sr_awsize(1),
I4 => s_axi_awlen_ii(3),
O => \m_axi_awlen[5]_INST_0_i_1_n_0\
);
\m_axi_awlen[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA000000C0"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => s_axi_awlen_ii(7),
I2 => sr_awsize(1),
I3 => sr_awsize(0),
I4 => sr_awsize(2),
I5 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
O => \USE_WRITE.write_addr_inst/upsized_length__40\(5)
);
\m_axi_awlen[5]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEA80EA800000"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => s_axi_awlen_ii(0),
I2 => sr_awaddr(1),
I3 => sr_awaddr(2),
I4 => s_axi_awlen_ii(2),
I5 => sr_awaddr(3),
O => \m_axi_awlen[5]_INST_0_i_3_n_0\
);
\m_axi_awlen[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F808080"
)
port map (
I0 => \m_axi_awlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_awlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_awlen_ii(7),
I3 => s_axi_awlen_ii(6),
I4 => \m_axi_awlen[6]_INST_0_i_3_n_0\,
O => \^in\(6)
);
\m_axi_awlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => \^q\(30),
I2 => sr_awburst(0),
I3 => sr_awburst(1),
I4 => s_axi_awlen_ii(4),
I5 => s_axi_awlen_ii(6),
O => \m_axi_awlen[6]_INST_0_i_1_n_0\
);
\m_axi_awlen[6]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \m_axi_awlen[1]_INST_0_i_1_n_0\,
I1 => s_axi_awlen_ii(3),
I2 => s_axi_awlen_ii(2),
O => \m_axi_awlen[6]_INST_0_i_2_n_0\
);
\m_axi_awlen[6]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => \^q\(30),
O => \m_axi_awlen[6]_INST_0_i_3_n_0\
);
\m_axi_awlen[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5700"
)
port map (
I0 => \^q\(30),
I1 => sr_awburst(0),
I2 => sr_awburst(1),
I3 => s_axi_awlen_ii(7),
O => \^in\(7)
);
\m_axi_awsize[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F100"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_axi_awsize[1]_INST_0_i_1_n_0\,
I3 => sr_awsize(0),
O => m_axi_awsize(0)
);
\m_axi_awsize[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F100"
)
port map (
I0 => sr_awburst(0),
I1 => sr_awburst(1),
I2 => \m_axi_awsize[1]_INST_0_i_1_n_0\,
I3 => sr_awsize(1),
O => m_axi_awsize(1)
);
\m_axi_awsize[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000002FFFFFFFF"
)
port map (
I0 => \m_axi_awsize[2]_INST_0_i_2_n_0\,
I1 => s_axi_awlen_ii(7),
I2 => s_axi_awlen_ii(6),
I3 => s_axi_awlen_ii(5),
I4 => s_axi_awlen_ii(4),
I5 => \^q\(30),
O => \m_axi_awsize[1]_INST_0_i_1_n_0\
);
\m_axi_awsize[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFE000"
)
port map (
I0 => sr_awburst(1),
I1 => sr_awburst(0),
I2 => \^q\(30),
I3 => \m_axi_awsize[2]_INST_0_i_1_n_0\,
I4 => sr_awsize(2),
O => m_axi_awsize(2)
);
\m_axi_awsize[2]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => s_axi_awlen_ii(7),
I1 => s_axi_awlen_ii(6),
I2 => s_axi_awlen_ii(5),
I3 => s_axi_awlen_ii(4),
I4 => \m_axi_awsize[2]_INST_0_i_2_n_0\,
O => \m_axi_awsize[2]_INST_0_i_1_n_0\
);
\m_axi_awsize[2]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen_ii(1),
I1 => s_axi_awlen_ii(0),
I2 => s_axi_awlen_ii(3),
I3 => s_axi_awlen_ii(2),
O => \m_axi_awsize[2]_INST_0_i_2_n_0\
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_awvalid\,
O => \m_payload_i[31]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(0),
Q => sr_awaddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(10),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(11),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(12),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(13),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(14),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(15),
Q => \^q\(9),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(16),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(17),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(18),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(19),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(1),
Q => sr_awaddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(20),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(21),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(22),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(23),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(24),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(25),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(26),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(27),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(28),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(29),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(2),
Q => sr_awaddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(30),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(31),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(32),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(33),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(34),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(35),
Q => sr_awsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(36),
Q => sr_awsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(37),
Q => sr_awsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(38),
Q => sr_awburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(39),
Q => sr_awburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(3),
Q => sr_awaddr(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(40),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(41),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(42),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(43),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(44),
Q => s_axi_awlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(45),
Q => s_axi_awlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(46),
Q => s_axi_awlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(47),
Q => s_axi_awlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(48),
Q => s_axi_awlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(49),
Q => s_axi_awlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(4),
Q => sr_awaddr(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(50),
Q => s_axi_awlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(51),
Q => s_axi_awlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(52),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(53),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(54),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(55),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(56),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(57),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(58),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(5),
Q => sr_awaddr(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(59),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(60),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(6),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(7),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(8),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(9),
Q => \^q\(3),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7F007F00000000"
)
port map (
I0 => cmd_push_block_reg,
I1 => m_axi_awready,
I2 => s_axi_aresetn_0,
I3 => \^s_axi_awready\,
I4 => s_axi_awvalid,
I5 => \aresetn_d_reg[1]\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^sr_awvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"757F0000"
)
port map (
I0 => \aresetn_d_reg[1]\,
I1 => \USE_RTL_VALID_WRITE.buffer_Full_q_reg\,
I2 => \^sr_awvalid\,
I3 => s_axi_awvalid,
I4 => \^p_0_in\(0),
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_awready\,
R => '0'
);
sub_sized_wrap0_carry_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00010103"
)
port map (
I0 => sr_awsize(0),
I1 => sr_awsize(1),
I2 => sr_awsize(2),
I3 => s_axi_awlen_ii(2),
I4 => s_axi_awlen_ii(3),
O => DI(1)
);
sub_sized_wrap0_carry_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00131313"
)
port map (
I0 => sr_awsize(1),
I1 => sr_awsize(2),
I2 => sr_awsize(0),
I3 => s_axi_awlen_ii(1),
I4 => s_axi_awlen_ii(0),
O => DI(0)
);
sub_sized_wrap0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awlen_ii(7),
I1 => s_axi_awlen_ii(6),
O => S(3)
);
sub_sized_wrap0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awlen_ii(5),
I1 => s_axi_awlen_ii(4),
O => S(2)
);
sub_sized_wrap0_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"010E100E"
)
port map (
I0 => sr_awsize(2),
I1 => sr_awsize(1),
I2 => s_axi_awlen_ii(3),
I3 => s_axi_awlen_ii(2),
I4 => sr_awsize(0),
O => S(1)
);
sub_sized_wrap0_carry_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"11111888"
)
port map (
I0 => s_axi_awlen_ii(0),
I1 => s_axi_awlen_ii(1),
I2 => sr_awsize(1),
I3 => sr_awsize(0),
I4 => sr_awsize(2),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
mr_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[4]\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 129 downto 0 );
s_ready_i_reg_0 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rvalid : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC;
p_13_in : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \^m_axi_rready\ : STD_LOGIC;
signal \m_payload_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[100]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[101]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[102]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[103]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[104]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[105]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[106]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[107]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[108]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[109]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[110]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[111]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[112]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[113]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[114]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[115]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[116]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[117]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[118]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[119]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[120]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[121]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[122]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[123]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[124]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[125]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[126]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[127]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[128]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[129]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[52]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[65]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[66]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[67]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[68]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[69]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[70]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[71]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[72]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[73]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[74]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[75]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[76]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[77]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[78]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[79]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[80]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[81]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[82]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[83]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[84]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[85]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[86]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[87]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[88]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[89]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[90]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[91]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[92]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[93]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[94]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[95]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[96]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[97]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[98]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[99]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1_n_0\ : STD_LOGIC;
signal mr_rlast : STD_LOGIC;
signal \^mr_rvalid\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[100]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[101]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[102]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[103]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[104]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[105]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[106]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[107]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[108]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[109]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[110]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[111]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[112]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[113]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[114]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[115]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[116]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[117]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[118]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[119]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[120]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[121]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[122]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[123]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[124]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[125]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[126]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[127]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[128]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[129]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[130]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[67]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[68]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[69]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[70]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[71]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[72]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[73]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[74]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[75]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[76]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[77]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[78]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[79]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[80]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[81]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[82]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[83]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[84]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[85]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[86]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[87]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[88]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[89]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[90]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[91]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[92]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[93]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[94]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[95]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[96]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[97]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[98]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[99]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[100]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[101]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[102]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[103]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[104]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[105]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[106]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[107]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[108]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[109]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[110]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[111]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[112]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[113]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[114]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[115]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[116]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[117]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[118]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[119]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[120]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[121]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[122]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[123]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[124]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[125]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[126]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[127]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[128]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[129]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_payload_i[67]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[68]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[69]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[70]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[71]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[72]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[73]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[74]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[75]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[76]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[77]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[78]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[79]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[80]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[81]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[82]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[83]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[84]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[85]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[86]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[87]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[88]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[89]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[90]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[91]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[92]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[93]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[94]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[95]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[96]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[97]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[98]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[99]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair61";
begin
m_axi_rready <= \^m_axi_rready\;
mr_rvalid <= \^mr_rvalid\;
\USE_RTL_LENGTH.first_mi_word_q_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF80000000"
)
port map (
I0 => mr_rlast,
I1 => rd_cmd_valid,
I2 => \^mr_rvalid\,
I3 => s_axi_rready,
I4 => p_13_in,
I5 => first_mi_word_q,
O => \USE_RTL_LENGTH.first_mi_word_q_reg\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mr_rvalid\,
I1 => rd_cmd_valid,
O => \USE_RTL_LENGTH.length_counter_q_reg[4]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1_n_0\
);
\m_payload_i[100]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(100),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[100]\,
O => \m_payload_i[100]_i_1_n_0\
);
\m_payload_i[101]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(101),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[101]\,
O => \m_payload_i[101]_i_1_n_0\
);
\m_payload_i[102]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(102),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[102]\,
O => \m_payload_i[102]_i_1_n_0\
);
\m_payload_i[103]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(103),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[103]\,
O => \m_payload_i[103]_i_1_n_0\
);
\m_payload_i[104]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(104),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[104]\,
O => \m_payload_i[104]_i_1_n_0\
);
\m_payload_i[105]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(105),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[105]\,
O => \m_payload_i[105]_i_1_n_0\
);
\m_payload_i[106]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(106),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[106]\,
O => \m_payload_i[106]_i_1_n_0\
);
\m_payload_i[107]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(107),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[107]\,
O => \m_payload_i[107]_i_1_n_0\
);
\m_payload_i[108]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(108),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[108]\,
O => \m_payload_i[108]_i_1_n_0\
);
\m_payload_i[109]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(109),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[109]\,
O => \m_payload_i[109]_i_1_n_0\
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1_n_0\
);
\m_payload_i[110]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(110),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[110]\,
O => \m_payload_i[110]_i_1_n_0\
);
\m_payload_i[111]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(111),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[111]\,
O => \m_payload_i[111]_i_1_n_0\
);
\m_payload_i[112]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(112),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[112]\,
O => \m_payload_i[112]_i_1_n_0\
);
\m_payload_i[113]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(113),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[113]\,
O => \m_payload_i[113]_i_1_n_0\
);
\m_payload_i[114]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(114),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[114]\,
O => \m_payload_i[114]_i_1_n_0\
);
\m_payload_i[115]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(115),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[115]\,
O => \m_payload_i[115]_i_1_n_0\
);
\m_payload_i[116]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(116),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[116]\,
O => \m_payload_i[116]_i_1_n_0\
);
\m_payload_i[117]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(117),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[117]\,
O => \m_payload_i[117]_i_1_n_0\
);
\m_payload_i[118]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(118),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[118]\,
O => \m_payload_i[118]_i_1_n_0\
);
\m_payload_i[119]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(119),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[119]\,
O => \m_payload_i[119]_i_1_n_0\
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1_n_0\
);
\m_payload_i[120]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(120),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[120]\,
O => \m_payload_i[120]_i_1_n_0\
);
\m_payload_i[121]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(121),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[121]\,
O => \m_payload_i[121]_i_1_n_0\
);
\m_payload_i[122]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(122),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[122]\,
O => \m_payload_i[122]_i_1_n_0\
);
\m_payload_i[123]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(123),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[123]\,
O => \m_payload_i[123]_i_1_n_0\
);
\m_payload_i[124]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(124),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[124]\,
O => \m_payload_i[124]_i_1_n_0\
);
\m_payload_i[125]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(125),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[125]\,
O => \m_payload_i[125]_i_1_n_0\
);
\m_payload_i[126]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(126),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[126]\,
O => \m_payload_i[126]_i_1_n_0\
);
\m_payload_i[127]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(127),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[127]\,
O => \m_payload_i[127]_i_1_n_0\
);
\m_payload_i[128]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[128]\,
O => \m_payload_i[128]_i_1_n_0\
);
\m_payload_i[129]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[129]\,
O => \m_payload_i[129]_i_1_n_0\
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1_n_0\
);
\m_payload_i[130]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast,
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[130]\,
O => \m_payload_i[130]_i_2_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1_n_0\
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1_n_0\
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1_n_0\
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1_n_0\
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1_n_0\
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1_n_0\
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1_n_0\
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1_n_0\
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1_n_0\
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1_n_0\
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1_n_0\
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1_n_0\
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1_n_0\
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1_n_0\
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1_n_0\
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1_n_0\
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1_n_0\
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1_n_0\
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1_n_0\
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1_n_0\
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1_n_0\
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1_n_0\
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1_n_0\
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1_n_0\
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1_n_0\
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1_n_0\
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1_n_0\
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1_n_0\
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1_n_0\
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1_n_0\
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1_n_0\
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1_n_0\
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1_n_0\
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => \m_payload_i[52]_i_1_n_0\
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1_n_0\
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1_n_0\
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1_n_0\
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1_n_0\
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1_n_0\
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1_n_0\
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1_n_0\
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1_n_0\
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1_n_0\
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1_n_0\
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1_n_0\
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1_n_0\
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(64),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1_n_0\
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(65),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => \m_payload_i[65]_i_1_n_0\
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(66),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => \m_payload_i[66]_i_1_n_0\
);
\m_payload_i[67]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(67),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[67]\,
O => \m_payload_i[67]_i_1_n_0\
);
\m_payload_i[68]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(68),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[68]\,
O => \m_payload_i[68]_i_1_n_0\
);
\m_payload_i[69]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(69),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[69]\,
O => \m_payload_i[69]_i_1_n_0\
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1_n_0\
);
\m_payload_i[70]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(70),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[70]\,
O => \m_payload_i[70]_i_1_n_0\
);
\m_payload_i[71]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(71),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[71]\,
O => \m_payload_i[71]_i_1_n_0\
);
\m_payload_i[72]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(72),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[72]\,
O => \m_payload_i[72]_i_1_n_0\
);
\m_payload_i[73]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(73),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[73]\,
O => \m_payload_i[73]_i_1_n_0\
);
\m_payload_i[74]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(74),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[74]\,
O => \m_payload_i[74]_i_1_n_0\
);
\m_payload_i[75]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(75),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[75]\,
O => \m_payload_i[75]_i_1_n_0\
);
\m_payload_i[76]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(76),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[76]\,
O => \m_payload_i[76]_i_1_n_0\
);
\m_payload_i[77]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(77),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[77]\,
O => \m_payload_i[77]_i_1_n_0\
);
\m_payload_i[78]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(78),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[78]\,
O => \m_payload_i[78]_i_1_n_0\
);
\m_payload_i[79]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(79),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[79]\,
O => \m_payload_i[79]_i_1_n_0\
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1_n_0\
);
\m_payload_i[80]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(80),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[80]\,
O => \m_payload_i[80]_i_1_n_0\
);
\m_payload_i[81]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(81),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[81]\,
O => \m_payload_i[81]_i_1_n_0\
);
\m_payload_i[82]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(82),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[82]\,
O => \m_payload_i[82]_i_1_n_0\
);
\m_payload_i[83]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(83),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[83]\,
O => \m_payload_i[83]_i_1_n_0\
);
\m_payload_i[84]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(84),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[84]\,
O => \m_payload_i[84]_i_1_n_0\
);
\m_payload_i[85]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(85),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[85]\,
O => \m_payload_i[85]_i_1_n_0\
);
\m_payload_i[86]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(86),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[86]\,
O => \m_payload_i[86]_i_1_n_0\
);
\m_payload_i[87]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(87),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[87]\,
O => \m_payload_i[87]_i_1_n_0\
);
\m_payload_i[88]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(88),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[88]\,
O => \m_payload_i[88]_i_1_n_0\
);
\m_payload_i[89]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(89),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[89]\,
O => \m_payload_i[89]_i_1_n_0\
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1_n_0\
);
\m_payload_i[90]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(90),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[90]\,
O => \m_payload_i[90]_i_1_n_0\
);
\m_payload_i[91]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(91),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[91]\,
O => \m_payload_i[91]_i_1_n_0\
);
\m_payload_i[92]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(92),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[92]\,
O => \m_payload_i[92]_i_1_n_0\
);
\m_payload_i[93]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(93),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[93]\,
O => \m_payload_i[93]_i_1_n_0\
);
\m_payload_i[94]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(94),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[94]\,
O => \m_payload_i[94]_i_1_n_0\
);
\m_payload_i[95]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(95),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[95]\,
O => \m_payload_i[95]_i_1_n_0\
);
\m_payload_i[96]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(96),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[96]\,
O => \m_payload_i[96]_i_1_n_0\
);
\m_payload_i[97]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(97),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[97]\,
O => \m_payload_i[97]_i_1_n_0\
);
\m_payload_i[98]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(98),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[98]\,
O => \m_payload_i[98]_i_1_n_0\
);
\m_payload_i[99]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(99),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[99]\,
O => \m_payload_i[99]_i_1_n_0\
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[0]_i_1_n_0\,
Q => Q(0),
R => '0'
);
\m_payload_i_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[100]_i_1_n_0\,
Q => Q(100),
R => '0'
);
\m_payload_i_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[101]_i_1_n_0\,
Q => Q(101),
R => '0'
);
\m_payload_i_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[102]_i_1_n_0\,
Q => Q(102),
R => '0'
);
\m_payload_i_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[103]_i_1_n_0\,
Q => Q(103),
R => '0'
);
\m_payload_i_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[104]_i_1_n_0\,
Q => Q(104),
R => '0'
);
\m_payload_i_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[105]_i_1_n_0\,
Q => Q(105),
R => '0'
);
\m_payload_i_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[106]_i_1_n_0\,
Q => Q(106),
R => '0'
);
\m_payload_i_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[107]_i_1_n_0\,
Q => Q(107),
R => '0'
);
\m_payload_i_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[108]_i_1_n_0\,
Q => Q(108),
R => '0'
);
\m_payload_i_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[109]_i_1_n_0\,
Q => Q(109),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[10]_i_1_n_0\,
Q => Q(10),
R => '0'
);
\m_payload_i_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[110]_i_1_n_0\,
Q => Q(110),
R => '0'
);
\m_payload_i_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[111]_i_1_n_0\,
Q => Q(111),
R => '0'
);
\m_payload_i_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[112]_i_1_n_0\,
Q => Q(112),
R => '0'
);
\m_payload_i_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[113]_i_1_n_0\,
Q => Q(113),
R => '0'
);
\m_payload_i_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[114]_i_1_n_0\,
Q => Q(114),
R => '0'
);
\m_payload_i_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[115]_i_1_n_0\,
Q => Q(115),
R => '0'
);
\m_payload_i_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[116]_i_1_n_0\,
Q => Q(116),
R => '0'
);
\m_payload_i_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[117]_i_1_n_0\,
Q => Q(117),
R => '0'
);
\m_payload_i_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[118]_i_1_n_0\,
Q => Q(118),
R => '0'
);
\m_payload_i_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[119]_i_1_n_0\,
Q => Q(119),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[11]_i_1_n_0\,
Q => Q(11),
R => '0'
);
\m_payload_i_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[120]_i_1_n_0\,
Q => Q(120),
R => '0'
);
\m_payload_i_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[121]_i_1_n_0\,
Q => Q(121),
R => '0'
);
\m_payload_i_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[122]_i_1_n_0\,
Q => Q(122),
R => '0'
);
\m_payload_i_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[123]_i_1_n_0\,
Q => Q(123),
R => '0'
);
\m_payload_i_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[124]_i_1_n_0\,
Q => Q(124),
R => '0'
);
\m_payload_i_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[125]_i_1_n_0\,
Q => Q(125),
R => '0'
);
\m_payload_i_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[126]_i_1_n_0\,
Q => Q(126),
R => '0'
);
\m_payload_i_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[127]_i_1_n_0\,
Q => Q(127),
R => '0'
);
\m_payload_i_reg[128]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[128]_i_1_n_0\,
Q => Q(128),
R => '0'
);
\m_payload_i_reg[129]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[129]_i_1_n_0\,
Q => Q(129),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[12]_i_1_n_0\,
Q => Q(12),
R => '0'
);
\m_payload_i_reg[130]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[130]_i_2_n_0\,
Q => mr_rlast,
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[13]_i_1_n_0\,
Q => Q(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[14]_i_1_n_0\,
Q => Q(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[15]_i_1_n_0\,
Q => Q(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[16]_i_1_n_0\,
Q => Q(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[17]_i_1_n_0\,
Q => Q(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[18]_i_1_n_0\,
Q => Q(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[19]_i_1_n_0\,
Q => Q(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[1]_i_1_n_0\,
Q => Q(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[20]_i_1_n_0\,
Q => Q(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[21]_i_1_n_0\,
Q => Q(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[22]_i_1_n_0\,
Q => Q(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[23]_i_1_n_0\,
Q => Q(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[24]_i_1_n_0\,
Q => Q(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[25]_i_1_n_0\,
Q => Q(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[26]_i_1_n_0\,
Q => Q(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[27]_i_1_n_0\,
Q => Q(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[28]_i_1_n_0\,
Q => Q(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[29]_i_1_n_0\,
Q => Q(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[2]_i_1_n_0\,
Q => Q(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[30]_i_1_n_0\,
Q => Q(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[31]_i_1__1_n_0\,
Q => Q(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[32]_i_1_n_0\,
Q => Q(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[33]_i_1_n_0\,
Q => Q(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[34]_i_1_n_0\,
Q => Q(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[35]_i_1_n_0\,
Q => Q(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[36]_i_1_n_0\,
Q => Q(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[37]_i_1_n_0\,
Q => Q(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[38]_i_1_n_0\,
Q => Q(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[39]_i_1_n_0\,
Q => Q(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[3]_i_1_n_0\,
Q => Q(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[40]_i_1_n_0\,
Q => Q(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[41]_i_1_n_0\,
Q => Q(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[42]_i_1_n_0\,
Q => Q(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[43]_i_1_n_0\,
Q => Q(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[44]_i_1_n_0\,
Q => Q(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[45]_i_1_n_0\,
Q => Q(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[46]_i_1_n_0\,
Q => Q(46),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[47]_i_1_n_0\,
Q => Q(47),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[48]_i_1_n_0\,
Q => Q(48),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[49]_i_1_n_0\,
Q => Q(49),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[4]_i_1_n_0\,
Q => Q(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[50]_i_1_n_0\,
Q => Q(50),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[51]_i_1_n_0\,
Q => Q(51),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[52]_i_1_n_0\,
Q => Q(52),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[53]_i_1_n_0\,
Q => Q(53),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[54]_i_1_n_0\,
Q => Q(54),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[55]_i_1_n_0\,
Q => Q(55),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[56]_i_1_n_0\,
Q => Q(56),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[57]_i_1_n_0\,
Q => Q(57),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[58]_i_1_n_0\,
Q => Q(58),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[59]_i_1_n_0\,
Q => Q(59),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[5]_i_1_n_0\,
Q => Q(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[60]_i_1_n_0\,
Q => Q(60),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[61]_i_1_n_0\,
Q => Q(61),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[62]_i_1_n_0\,
Q => Q(62),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[63]_i_1_n_0\,
Q => Q(63),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[64]_i_1_n_0\,
Q => Q(64),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[65]_i_1_n_0\,
Q => Q(65),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[66]_i_1_n_0\,
Q => Q(66),
R => '0'
);
\m_payload_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[67]_i_1_n_0\,
Q => Q(67),
R => '0'
);
\m_payload_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[68]_i_1_n_0\,
Q => Q(68),
R => '0'
);
\m_payload_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[69]_i_1_n_0\,
Q => Q(69),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[6]_i_1_n_0\,
Q => Q(6),
R => '0'
);
\m_payload_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[70]_i_1_n_0\,
Q => Q(70),
R => '0'
);
\m_payload_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[71]_i_1_n_0\,
Q => Q(71),
R => '0'
);
\m_payload_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[72]_i_1_n_0\,
Q => Q(72),
R => '0'
);
\m_payload_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[73]_i_1_n_0\,
Q => Q(73),
R => '0'
);
\m_payload_i_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[74]_i_1_n_0\,
Q => Q(74),
R => '0'
);
\m_payload_i_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[75]_i_1_n_0\,
Q => Q(75),
R => '0'
);
\m_payload_i_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[76]_i_1_n_0\,
Q => Q(76),
R => '0'
);
\m_payload_i_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[77]_i_1_n_0\,
Q => Q(77),
R => '0'
);
\m_payload_i_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[78]_i_1_n_0\,
Q => Q(78),
R => '0'
);
\m_payload_i_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[79]_i_1_n_0\,
Q => Q(79),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[7]_i_1_n_0\,
Q => Q(7),
R => '0'
);
\m_payload_i_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[80]_i_1_n_0\,
Q => Q(80),
R => '0'
);
\m_payload_i_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[81]_i_1_n_0\,
Q => Q(81),
R => '0'
);
\m_payload_i_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[82]_i_1_n_0\,
Q => Q(82),
R => '0'
);
\m_payload_i_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[83]_i_1_n_0\,
Q => Q(83),
R => '0'
);
\m_payload_i_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[84]_i_1_n_0\,
Q => Q(84),
R => '0'
);
\m_payload_i_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[85]_i_1_n_0\,
Q => Q(85),
R => '0'
);
\m_payload_i_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[86]_i_1_n_0\,
Q => Q(86),
R => '0'
);
\m_payload_i_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[87]_i_1_n_0\,
Q => Q(87),
R => '0'
);
\m_payload_i_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[88]_i_1_n_0\,
Q => Q(88),
R => '0'
);
\m_payload_i_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[89]_i_1_n_0\,
Q => Q(89),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[8]_i_1_n_0\,
Q => Q(8),
R => '0'
);
\m_payload_i_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[90]_i_1_n_0\,
Q => Q(90),
R => '0'
);
\m_payload_i_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[91]_i_1_n_0\,
Q => Q(91),
R => '0'
);
\m_payload_i_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[92]_i_1_n_0\,
Q => Q(92),
R => '0'
);
\m_payload_i_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[93]_i_1_n_0\,
Q => Q(93),
R => '0'
);
\m_payload_i_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[94]_i_1_n_0\,
Q => Q(94),
R => '0'
);
\m_payload_i_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[95]_i_1_n_0\,
Q => Q(95),
R => '0'
);
\m_payload_i_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[96]_i_1_n_0\,
Q => Q(96),
R => '0'
);
\m_payload_i_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[97]_i_1_n_0\,
Q => Q(97),
R => '0'
);
\m_payload_i_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[98]_i_1_n_0\,
Q => Q(98),
R => '0'
);
\m_payload_i_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[99]_i_1_n_0\,
Q => Q(99),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => \m_payload_i[9]_i_1_n_0\,
Q => Q(9),
R => '0'
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_reg_0,
Q => \^mr_rvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F400"
)
port map (
I0 => m_axi_rvalid,
I1 => \^m_axi_rready\,
I2 => E(0),
I3 => p_0_in(0),
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^m_axi_rready\,
R => '0'
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(100),
Q => \skid_buffer_reg_n_0_[100]\,
R => '0'
);
\skid_buffer_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(101),
Q => \skid_buffer_reg_n_0_[101]\,
R => '0'
);
\skid_buffer_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(102),
Q => \skid_buffer_reg_n_0_[102]\,
R => '0'
);
\skid_buffer_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(103),
Q => \skid_buffer_reg_n_0_[103]\,
R => '0'
);
\skid_buffer_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(104),
Q => \skid_buffer_reg_n_0_[104]\,
R => '0'
);
\skid_buffer_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(105),
Q => \skid_buffer_reg_n_0_[105]\,
R => '0'
);
\skid_buffer_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(106),
Q => \skid_buffer_reg_n_0_[106]\,
R => '0'
);
\skid_buffer_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(107),
Q => \skid_buffer_reg_n_0_[107]\,
R => '0'
);
\skid_buffer_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(108),
Q => \skid_buffer_reg_n_0_[108]\,
R => '0'
);
\skid_buffer_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(109),
Q => \skid_buffer_reg_n_0_[109]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(110),
Q => \skid_buffer_reg_n_0_[110]\,
R => '0'
);
\skid_buffer_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(111),
Q => \skid_buffer_reg_n_0_[111]\,
R => '0'
);
\skid_buffer_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(112),
Q => \skid_buffer_reg_n_0_[112]\,
R => '0'
);
\skid_buffer_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(113),
Q => \skid_buffer_reg_n_0_[113]\,
R => '0'
);
\skid_buffer_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(114),
Q => \skid_buffer_reg_n_0_[114]\,
R => '0'
);
\skid_buffer_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(115),
Q => \skid_buffer_reg_n_0_[115]\,
R => '0'
);
\skid_buffer_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(116),
Q => \skid_buffer_reg_n_0_[116]\,
R => '0'
);
\skid_buffer_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(117),
Q => \skid_buffer_reg_n_0_[117]\,
R => '0'
);
\skid_buffer_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(118),
Q => \skid_buffer_reg_n_0_[118]\,
R => '0'
);
\skid_buffer_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(119),
Q => \skid_buffer_reg_n_0_[119]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(120),
Q => \skid_buffer_reg_n_0_[120]\,
R => '0'
);
\skid_buffer_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(121),
Q => \skid_buffer_reg_n_0_[121]\,
R => '0'
);
\skid_buffer_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(122),
Q => \skid_buffer_reg_n_0_[122]\,
R => '0'
);
\skid_buffer_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(123),
Q => \skid_buffer_reg_n_0_[123]\,
R => '0'
);
\skid_buffer_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(124),
Q => \skid_buffer_reg_n_0_[124]\,
R => '0'
);
\skid_buffer_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(125),
Q => \skid_buffer_reg_n_0_[125]\,
R => '0'
);
\skid_buffer_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(126),
Q => \skid_buffer_reg_n_0_[126]\,
R => '0'
);
\skid_buffer_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(127),
Q => \skid_buffer_reg_n_0_[127]\,
R => '0'
);
\skid_buffer_reg[128]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[128]\,
R => '0'
);
\skid_buffer_reg[129]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[129]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[130]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rlast,
Q => \skid_buffer_reg_n_0_[130]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(64),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(65),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(66),
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(67),
Q => \skid_buffer_reg_n_0_[67]\,
R => '0'
);
\skid_buffer_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(68),
Q => \skid_buffer_reg_n_0_[68]\,
R => '0'
);
\skid_buffer_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(69),
Q => \skid_buffer_reg_n_0_[69]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(70),
Q => \skid_buffer_reg_n_0_[70]\,
R => '0'
);
\skid_buffer_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(71),
Q => \skid_buffer_reg_n_0_[71]\,
R => '0'
);
\skid_buffer_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(72),
Q => \skid_buffer_reg_n_0_[72]\,
R => '0'
);
\skid_buffer_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(73),
Q => \skid_buffer_reg_n_0_[73]\,
R => '0'
);
\skid_buffer_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(74),
Q => \skid_buffer_reg_n_0_[74]\,
R => '0'
);
\skid_buffer_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(75),
Q => \skid_buffer_reg_n_0_[75]\,
R => '0'
);
\skid_buffer_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(76),
Q => \skid_buffer_reg_n_0_[76]\,
R => '0'
);
\skid_buffer_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(77),
Q => \skid_buffer_reg_n_0_[77]\,
R => '0'
);
\skid_buffer_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(78),
Q => \skid_buffer_reg_n_0_[78]\,
R => '0'
);
\skid_buffer_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(79),
Q => \skid_buffer_reg_n_0_[79]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(80),
Q => \skid_buffer_reg_n_0_[80]\,
R => '0'
);
\skid_buffer_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(81),
Q => \skid_buffer_reg_n_0_[81]\,
R => '0'
);
\skid_buffer_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(82),
Q => \skid_buffer_reg_n_0_[82]\,
R => '0'
);
\skid_buffer_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(83),
Q => \skid_buffer_reg_n_0_[83]\,
R => '0'
);
\skid_buffer_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(84),
Q => \skid_buffer_reg_n_0_[84]\,
R => '0'
);
\skid_buffer_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(85),
Q => \skid_buffer_reg_n_0_[85]\,
R => '0'
);
\skid_buffer_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(86),
Q => \skid_buffer_reg_n_0_[86]\,
R => '0'
);
\skid_buffer_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(87),
Q => \skid_buffer_reg_n_0_[87]\,
R => '0'
);
\skid_buffer_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(88),
Q => \skid_buffer_reg_n_0_[88]\,
R => '0'
);
\skid_buffer_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(89),
Q => \skid_buffer_reg_n_0_[89]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(90),
Q => \skid_buffer_reg_n_0_[90]\,
R => '0'
);
\skid_buffer_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(91),
Q => \skid_buffer_reg_n_0_[91]\,
R => '0'
);
\skid_buffer_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(92),
Q => \skid_buffer_reg_n_0_[92]\,
R => '0'
);
\skid_buffer_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(93),
Q => \skid_buffer_reg_n_0_[93]\,
R => '0'
);
\skid_buffer_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(94),
Q => \skid_buffer_reg_n_0_[94]\,
R => '0'
);
\skid_buffer_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(95),
Q => \skid_buffer_reg_n_0_[95]\,
R => '0'
);
\skid_buffer_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(96),
Q => \skid_buffer_reg_n_0_[96]\,
R => '0'
);
\skid_buffer_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(97),
Q => \skid_buffer_reg_n_0_[97]\,
R => '0'
);
\skid_buffer_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(98),
Q => \skid_buffer_reg_n_0_[98]\,
R => '0'
);
\skid_buffer_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(99),
Q => \skid_buffer_reg_n_0_[99]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo is
port (
\USE_RTL_CURR_WORD.first_word_q_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
p_3_out4_out : out STD_LOGIC;
p_8_out : out STD_LOGIC;
p_11_out : out STD_LOGIC;
p_14_out : out STD_LOGIC;
p_17_out18_out : out STD_LOGIC;
p_22_out : out STD_LOGIC;
p_25_out26_out : out STD_LOGIC;
p_30_out : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ : out STD_LOGIC;
p_33_out : out STD_LOGIC;
p_37_out : out STD_LOGIC;
p_41_out : out STD_LOGIC;
p_44_out : out STD_LOGIC;
p_47_out : out STD_LOGIC;
p_51_out52_out : out STD_LOGIC;
p_55_out56_out : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_RTL_CURR_WORD.current_word_q_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]_0\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[119]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_61_out__2\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[111]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_91_out__2\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[103]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_122_out__2\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[95]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_151_out__2\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[87]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_180_out__2\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[79]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_209_out__2\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[71]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_240_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_269_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_298_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_327_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_358_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_387_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_416_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_445_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_481_out__2\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]_0\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[119]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[14]\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[111]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[13]\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[103]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[12]\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[95]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[11]\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[87]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[10]\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[79]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[9]\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[8]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
wrap_buffer_available_reg : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
sr_awvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wstrb_wrap_buffer_15 : in STD_LOGIC;
wstrb_wrap_buffer_14 : in STD_LOGIC;
wstrb_wrap_buffer_13 : in STD_LOGIC;
wstrb_wrap_buffer_12 : in STD_LOGIC;
wstrb_wrap_buffer_11 : in STD_LOGIC;
wstrb_wrap_buffer_10 : in STD_LOGIC;
wstrb_wrap_buffer_9 : in STD_LOGIC;
wstrb_wrap_buffer_8 : in STD_LOGIC;
wstrb_wrap_buffer_7 : in STD_LOGIC;
wstrb_wrap_buffer_6 : in STD_LOGIC;
wstrb_wrap_buffer_5 : in STD_LOGIC;
wstrb_wrap_buffer_4 : in STD_LOGIC;
wstrb_wrap_buffer_3 : in STD_LOGIC;
wstrb_wrap_buffer_2 : in STD_LOGIC;
wstrb_wrap_buffer_1 : in STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
first_mi_word_q : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\ : in STD_LOGIC;
\sel_first_word__0\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_word_q : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]_0\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[4]\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo;
architecture STRUCTURE of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal M_READY_I : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_4_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_11_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_12_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_5_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_6_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_7_n_0\ : STD_LOGIC;
signal \USE_REGISTER.M_AXI_WVALID_q_i_8_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^use_rtl_curr_word.current_word_q_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^use_rtl_curr_word.first_word_q_reg\ : STD_LOGIC;
signal \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_CURR_WORD.pre_next_word_q[3]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \^use_rtl_length.length_counter_q_reg[1]\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word__1\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/next_word_i__3\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer_enabled__1\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/word_completed__8\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\ : STD_LOGIC;
signal \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\ : STD_LOGIC;
signal \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\ : STD_LOGIC;
signal \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_4_n_0\ : STD_LOGIC;
signal \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[8]_i_3_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_11_n_0\ : STD_LOGIC;
signal \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_8_n_0\ : STD_LOGIC;
signal \^word_lane[3].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wdata_i_reg[127]_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal \buffer_Empty__3\ : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal data_Exists_I : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal \^p_122_out__2\ : STD_LOGIC;
signal \^p_151_out__2\ : STD_LOGIC;
signal \^p_180_out__2\ : STD_LOGIC;
signal \^p_209_out__2\ : STD_LOGIC;
signal \^p_240_out__2\ : STD_LOGIC;
signal \^p_269_out__2\ : STD_LOGIC;
signal \^p_298_out__2\ : STD_LOGIC;
signal \^p_327_out__2\ : STD_LOGIC;
signal \^p_358_out__2\ : STD_LOGIC;
signal \^p_387_out__2\ : STD_LOGIC;
signal \^p_416_out__2\ : STD_LOGIC;
signal \^p_445_out__2\ : STD_LOGIC;
signal \^p_481_out__2\ : STD_LOGIC;
signal \^p_61_out__2\ : STD_LOGIC;
signal \^p_91_out__2\ : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal wr_cmd_complete_wrap : STD_LOGIC;
signal wr_cmd_first_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_cmd_last_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_cmd_mask : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_cmd_modified : STD_LOGIC;
signal wr_cmd_next_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_cmd_offset : STD_LOGIC_VECTOR ( 3 downto 2 );
signal wr_cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_4\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_11\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_12\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \USE_REGISTER.M_AXI_WVALID_q_i_2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \USE_RTL_CURR_WORD.current_word_q[2]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \USE_RTL_CURR_WORD.current_word_q[3]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \USE_RTL_CURR_WORD.pre_next_word_q[3]_i_4\ : label is "soft_lutpair107";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][14]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][30]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][31]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][31]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][31]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][32]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][33]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][34]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.first_mi_word_q_i_1\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_4\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_2\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_4\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_3\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_3\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[8]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_3\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[9]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_3\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[10]_i_2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[11]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_3\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[12]_i_2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_3\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[13]_i_2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_3\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[14]_i_2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_4\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_5\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_9\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_5\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[15]_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair108";
attribute SOFT_HLUTNM of data_Exists_I_i_2 : label is "soft_lutpair105";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair110";
attribute SOFT_HLUTNM of m_valid_i_i_2 : label is "soft_lutpair110";
attribute SOFT_HLUTNM of s_axi_wready_INST_0 : label is "soft_lutpair104";
attribute SOFT_HLUTNM of s_ready_i_i_2 : label is "soft_lutpair108";
attribute SOFT_HLUTNM of wrap_buffer_available_i_2 : label is "soft_lutpair106";
begin
E(0) <= \^e\(0);
Q(9 downto 0) <= \^q\(9 downto 0);
\USE_RTL_CURR_WORD.current_word_q_reg[3]\(3 downto 0) <= \^use_rtl_curr_word.current_word_q_reg[3]\(3 downto 0);
\USE_RTL_CURR_WORD.first_word_q_reg\ <= \^use_rtl_curr_word.first_word_q_reg\;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ <= \^use_rtl_length.length_counter_q_reg[1]\;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\ <= \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ <= \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]_0\ <= \^word_lane[3].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wdata_i_reg[127]_0\;
\p_122_out__2\ <= \^p_122_out__2\;
\p_151_out__2\ <= \^p_151_out__2\;
\p_180_out__2\ <= \^p_180_out__2\;
\p_209_out__2\ <= \^p_209_out__2\;
\p_240_out__2\ <= \^p_240_out__2\;
\p_269_out__2\ <= \^p_269_out__2\;
\p_298_out__2\ <= \^p_298_out__2\;
\p_327_out__2\ <= \^p_327_out__2\;
\p_358_out__2\ <= \^p_358_out__2\;
\p_387_out__2\ <= \^p_387_out__2\;
\p_416_out__2\ <= \^p_416_out__2\;
\p_445_out__2\ <= \^p_445_out__2\;
\p_481_out__2\ <= \^p_481_out__2\;
\p_61_out__2\ <= \^p_61_out__2\;
\p_91_out__2\ <= \^p_91_out__2\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => wr_cmd_step(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => wr_cmd_mask(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => wr_cmd_mask(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => wr_cmd_mask(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\,
Q => wr_cmd_mask(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => wr_cmd_offset(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => wr_cmd_offset(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => wr_cmd_last_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => wr_cmd_last_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => wr_cmd_last_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => wr_cmd_last_word(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => wr_cmd_next_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => wr_cmd_next_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => wr_cmd_next_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => wr_cmd_next_word(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => wr_cmd_first_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => wr_cmd_first_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => wr_cmd_first_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\,
Q => wr_cmd_first_word(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\,
Q => \^q\(8),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\,
Q => wr_cmd_complete_wrap,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\,
Q => wr_cmd_modified,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\,
Q => \^q\(9),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => wr_cmd_step(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => wr_cmd_step(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => s_axi_wlast,
I1 => \^use_rtl_length.length_counter_q_reg[1]\,
I2 => \^use_rtl_curr_word.first_word_q_reg\,
O => M_READY_I
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8AAA8A8A8A8"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_4_n_0\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_i_6_n_0\,
I3 => \USE_REGISTER.M_AXI_WVALID_q_i_5_n_0\,
I4 => \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\,
O => \^use_rtl_length.length_counter_q_reg[1]\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(9),
I1 => wr_cmd_modified,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_4_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => data_Exists_I,
Q => \^use_rtl_curr_word.first_word_q_reg\,
R => SR(0)
);
\USE_REGISTER.M_AXI_WVALID_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer_enabled__1\,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => s_axi_wvalid,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/word_completed__8\,
I4 => m_axi_wready,
I5 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
O => \USE_REGISTER.M_AXI_WVALID_q_reg\
);
\USE_REGISTER.M_AXI_WVALID_q_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FDFFFF"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(3),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_next_word(3),
I4 => wr_cmd_mask(3),
O => \USE_REGISTER.M_AXI_WVALID_q_i_11_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FDFFFF"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(2),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_next_word(2),
I4 => wr_cmd_mask(2),
O => \USE_REGISTER.M_AXI_WVALID_q_i_12_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(8),
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => wrap_buffer_available,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer_enabled__1\
);
\USE_REGISTER.M_AXI_WVALID_q_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF02FFFF"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\,
I1 => \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_i_5_n_0\,
I3 => \USE_REGISTER.M_AXI_WVALID_q_i_6_n_0\,
I4 => wr_cmd_modified,
I5 => \^q\(9),
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/word_completed__8\
);
\USE_REGISTER.M_AXI_WVALID_q_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDDDFFFFDFFFDDD"
)
port map (
I0 => wr_cmd_modified,
I1 => \USE_RTL_LENGTH.length_counter_q_reg[0]\,
I2 => wr_cmd_first_word(2),
I3 => \sel_first_word__0\,
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(2),
I5 => wr_cmd_last_word(2),
O => \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_i_7_n_0\,
I1 => \USE_REGISTER.M_AXI_WVALID_q_i_8_n_0\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg[4]\,
I4 => wr_cmd_last_word(3),
I5 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word__1\(3),
O => \USE_REGISTER.M_AXI_WVALID_q_i_5_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \USE_REGISTER.M_AXI_WVALID_q_i_11_n_0\,
I1 => \USE_REGISTER.M_AXI_WVALID_q_i_12_n_0\,
I2 => wr_cmd_complete_wrap,
I3 => \^q\(9),
I4 => \^use_rtl_curr_word.current_word_q_reg[3]\(0),
I5 => \^use_rtl_curr_word.current_word_q_reg[3]\(1),
O => \USE_REGISTER.M_AXI_WVALID_q_i_6_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FDFE02"
)
port map (
I0 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(0),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_first_word(0),
I4 => wr_cmd_last_word(0),
O => \USE_REGISTER.M_AXI_WVALID_q_i_7_n_0\
);
\USE_REGISTER.M_AXI_WVALID_q_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FDFE02"
)
port map (
I0 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(1),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_first_word(1),
I4 => wr_cmd_last_word(1),
O => \USE_REGISTER.M_AXI_WVALID_q_i_8_n_0\
);
\USE_RTL_ADDR.addr_q[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9999999999999699"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I2 => cmd_push_block,
I3 => sr_awvalid,
I4 => buffer_Full_q,
I5 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9A96AA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I3 => valid_Write,
I4 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9AAA96AAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => valid_Write,
I5 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444434400000000"
)
port map (
I0 => \buffer_Empty__3\,
I1 => M_READY_I,
I2 => buffer_Full_q,
I3 => sr_awvalid,
I4 => cmd_push_block,
I5 => data_Exists_I,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I5 => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\,
O => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFD5FFFF"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => \^use_rtl_length.length_counter_q_reg[1]\,
I2 => s_axi_wlast,
I3 => buffer_Full_q,
I4 => sr_awvalid,
I5 => cmd_push_block,
O => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => SR(0)
);
\USE_RTL_CURR_WORD.current_word_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE020000"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(0),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_next_word(0),
I4 => wr_cmd_mask(0),
O => \^use_rtl_curr_word.current_word_q_reg[3]\(0)
);
\USE_RTL_CURR_WORD.current_word_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE020000"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(1),
I1 => \^q\(9),
I2 => first_word_q,
I3 => wr_cmd_next_word(1),
I4 => wr_cmd_mask(1),
O => \^use_rtl_curr_word.current_word_q_reg[3]\(1)
);
\USE_RTL_CURR_WORD.current_word_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(2),
I1 => wr_cmd_next_word(2),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(2),
O => \^use_rtl_curr_word.current_word_q_reg[3]\(2)
);
\USE_RTL_CURR_WORD.current_word_q[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => wr_cmd_mask(3),
I1 => wr_cmd_next_word(3),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(3),
O => \^use_rtl_curr_word.current_word_q_reg[3]\(3)
);
\USE_RTL_CURR_WORD.first_word_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A00080A0A0A0A0"
)
port map (
I0 => s_axi_wvalid,
I1 => \^q\(8),
I2 => \^use_rtl_curr_word.first_word_q_reg\,
I3 => wrap_buffer_available,
I4 => m_axi_wready,
I5 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
O => \^e\(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"54570000ABA80000"
)
port map (
I0 => wr_cmd_next_word(0),
I1 => first_word_q,
I2 => \^q\(9),
I3 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(0),
I4 => wr_cmd_mask(0),
I5 => wr_cmd_step(0),
O => D(0)
);
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"56A60000A9590000"
)
port map (
I0 => wr_cmd_step(1),
I1 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(1),
I2 => \sel_first_word__0\,
I3 => wr_cmd_next_word(1),
I4 => wr_cmd_mask(1),
I5 => \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2_n_0\,
O => D(1)
);
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5557FFF7"
)
port map (
I0 => wr_cmd_step(0),
I1 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(0),
I2 => \^q\(9),
I3 => first_word_q,
I4 => wr_cmd_next_word(0),
O => \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2_n_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B80047004700B800"
)
port map (
I0 => wr_cmd_next_word(2),
I1 => \sel_first_word__0\,
I2 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(2),
I3 => wr_cmd_mask(2),
I4 => wr_cmd_step(2),
I5 => \USE_RTL_CURR_WORD.pre_next_word_q[3]_i_2_n_0\,
O => D(2)
);
\USE_RTL_CURR_WORD.pre_next_word_q[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10E07080"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q[3]_i_2_n_0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/next_word_i__3\(2),
I2 => wr_cmd_mask(3),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/next_word_i__3\(3),
I4 => wr_cmd_step(2),
O => D(3)
);
\USE_RTL_CURR_WORD.pre_next_word_q[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDFDDD544454440"
)
port map (
I0 => \USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2_n_0\,
I1 => wr_cmd_next_word(1),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(1),
I5 => wr_cmd_step(1),
O => \USE_RTL_CURR_WORD.pre_next_word_q[3]_i_2_n_0\
);
\USE_RTL_CURR_WORD.pre_next_word_q[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wr_cmd_next_word(2),
I1 => first_word_q,
I2 => \^q\(9),
I3 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(2),
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/next_word_i__3\(2)
);
\USE_RTL_CURR_WORD.pre_next_word_q[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wr_cmd_next_word(3),
I1 => first_word_q,
I2 => \^q\(9),
I3 => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(3),
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/next_word_i__3\(3)
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cmd_push_block,
I1 => sr_awvalid,
I2 => buffer_Full_q,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(28),
Q => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(29),
Q => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(30),
Q => \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(31),
Q => \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(32),
Q => \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.first_mi_word_q_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wlast,
I1 => \^use_rtl_length.length_counter_q_reg[1]\,
I2 => first_mi_word_q,
O => \USE_RTL_LENGTH.first_mi_word_q_reg\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5A0DD225F0ADD22"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[1]\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg[1]_1\(0),
I2 => \^q\(0),
I3 => \USE_RTL_LENGTH.length_counter_q_reg[1]_1\(1),
I4 => first_mi_word_q,
I5 => \^q\(1),
O => \USE_RTL_LENGTH.length_counter_q_reg[1]_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00200000"
)
port map (
I0 => sr_awvalid,
I1 => cmd_push_block,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\,
I3 => M_READY_I,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\,
Q => buffer_Full_q,
R => SR(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_481_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_0\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_481_out__2\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I1 => s_axi_wstrb(0),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF800000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(0),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I3 => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\,
I4 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
O => p_55_out56_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => wrap_buffer_available,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => \^q\(8),
I3 => s_axi_wvalid,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000005457"
)
port map (
I0 => wr_cmd_first_word(2),
I1 => first_word_q,
I2 => \^q\(9),
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(2),
I4 => wr_cmd_offset(2),
I5 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_4_n_0\,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F00"
)
port map (
I0 => \^use_rtl_curr_word.first_word_q_reg\,
I1 => \^use_rtl_length.length_counter_q_reg[1]\,
I2 => s_axi_wlast,
I3 => s_axi_aresetn,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_445_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_1,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_445_out__2\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I1 => s_axi_wstrb(1),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(1),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_1,
O => p_51_out52_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_416_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_2,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_416_out__2\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I1 => s_axi_wstrb(2),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(2),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_2,
O => p_47_out
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_387_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_3,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_387_out__2\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I1 => s_axi_wstrb(3),
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0)
);
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => s_axi_wstrb(3),
I2 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_0__0\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_3,
O => p_44_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_358_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_4,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_358_out__2\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[39]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => wrap_buffer_available,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => \^q\(8),
I3 => s_axi_wvalid,
I4 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I5 => s_axi_wstrb(0),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]_0\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I2 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_4,
O => p_41_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_327_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_5,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_327_out__2\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[47]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => wrap_buffer_available,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => \^q\(8),
I3 => s_axi_wvalid,
I4 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I5 => s_axi_wstrb(1),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I2 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_5,
O => p_37_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_298_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_6,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_298_out__2\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFABA8"
)
port map (
I0 => wr_cmd_first_word(2),
I1 => first_word_q,
I2 => \^q\(9),
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(2),
I4 => wr_cmd_offset(2),
I5 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_4_n_0\,
O => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEAAAE"
)
port map (
I0 => wr_cmd_offset(3),
I1 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(3),
I2 => \^q\(9),
I3 => first_word_q,
I4 => wr_cmd_first_word(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_4_n_0\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[55]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => wrap_buffer_available,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => \^q\(8),
I3 => s_axi_wvalid,
I4 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I5 => s_axi_wstrb(2),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I2 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_6,
O => p_33_out
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_269_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_7,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_269_out__2\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I1 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I2 => s_axi_wstrb(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[63]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => wrap_buffer_available,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => \^q\(8),
I3 => s_axi_wvalid,
I4 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I5 => s_axi_wstrb(3),
O => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0)
);
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I2 => \^word_lane[1].use_always_packer.byte_lane[0].use_rtl_data.wdata_wrap_buffer_q_reg[39]\,
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_7,
O => p_30_out
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_240_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_8,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[71]\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[71]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I1 => s_axi_wstrb(0),
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_240_out__2\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I1 => s_axi_wstrb(0),
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[8]\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[71]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I2 => s_axi_wstrb(0),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_8,
O => p_25_out26_out
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFABA8"
)
port map (
I0 => wr_cmd_first_word(3),
I1 => first_word_q,
I2 => \^q\(9),
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(3),
I4 => wr_cmd_offset(3),
I5 => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[8]_i_3_n_0\,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[8]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEAAAE"
)
port map (
I0 => wr_cmd_offset(2),
I1 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(2),
I2 => \^q\(9),
I3 => first_word_q,
I4 => wr_cmd_first_word(2),
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[8]_i_3_n_0\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_209_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_9,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[79]\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[79]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I1 => s_axi_wstrb(1),
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_209_out__2\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I1 => s_axi_wstrb(1),
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[9]\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[79]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[79]\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I2 => s_axi_wstrb(1),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_9,
O => p_22_out
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_180_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_10,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[87]\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[87]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I1 => s_axi_wstrb(2),
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_180_out__2\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I1 => s_axi_wstrb(2),
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[10]\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[87]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[87]\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I2 => s_axi_wstrb(2),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_10,
O => p_17_out18_out
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_151_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_11,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[95]\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[95]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I1 => s_axi_wstrb(3),
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_151_out__2\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[11]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I1 => s_axi_wstrb(3),
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[11]\
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[95]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[95]\(0)
);
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_2__0\,
I2 => s_axi_wstrb(3),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_11,
O => p_14_out
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_122_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_12,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[103]\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[103]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I1 => s_axi_wstrb(0),
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_122_out__2\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I1 => s_axi_wstrb(0),
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[12]\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[103]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[103]\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I2 => s_axi_wstrb(0),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_12,
O => p_11_out
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFABA800000000"
)
port map (
I0 => wr_cmd_first_word(2),
I1 => first_word_q,
I2 => \^q\(9),
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(2),
I4 => wr_cmd_offset(2),
I5 => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_4_n_0\,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_91_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_13,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[111]\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[111]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I1 => s_axi_wstrb(1),
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_91_out__2\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[13]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I1 => s_axi_wstrb(1),
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[13]\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[111]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[111]\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I2 => s_axi_wstrb(1),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_13,
O => p_8_out
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^p_61_out__2\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_14,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[119]\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[119]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I1 => s_axi_wstrb(2),
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^p_61_out__2\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[14]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I1 => s_axi_wstrb(2),
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[14]\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[119]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[119]\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I2 => s_axi_wstrb(2),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_14,
O => p_3_out4_out
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF6665666A"
)
port map (
I0 => wr_cmd_last_word(1),
I1 => wr_cmd_first_word(1),
I2 => first_word_q,
I3 => \^q\(9),
I4 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(1),
I5 => \USE_REGISTER.M_AXI_WVALID_q_i_7_n_0\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_11_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \^word_lane[3].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wdata_i_reg[127]_0\,
I1 => m_axi_wready,
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I3 => wstrb_wrap_buffer_15,
I4 => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8080F080"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I1 => s_axi_wstrb(3),
I2 => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
I3 => \^use_rtl_curr_word.first_word_q_reg\,
I4 => wr_cmd_modified,
O => \^word_lane[3].use_always_packer.byte_lane[3].use_rtl_data.use_register.m_axi_wdata_i_reg[127]_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^e\(0),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\,
I2 => wrap_buffer_available,
I3 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_8_n_0\,
O => \^word_lane[0].use_always_packer.byte_lane[0].use_rtl_data.use_register.m_axi_wdata_i_reg[7]\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF6"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word__1\(3),
I1 => wr_cmd_last_word(3),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]_0\,
I3 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_11_n_0\,
I4 => \USE_REGISTER.M_AXI_WVALID_q_i_4_n_0\,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_8_n_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wr_cmd_first_word(3),
I1 => first_word_q,
I2 => \^q\(9),
I3 => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(3),
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word__1\(3)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[127]_i_8_n_0\,
I1 => wrap_buffer_available,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\,
I3 => \^e\(0),
I4 => s_axi_aresetn,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[15]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I1 => s_axi_wstrb(3),
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]_0\
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[127]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I2 => s_axi_wvalid,
I3 => \^q\(8),
I4 => \^use_rtl_curr_word.first_word_q_reg\,
I5 => wrap_buffer_available,
O => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[127]\(0)
);
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF008000"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/store_in_wrap_buffer__0\,
I1 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/current_word_idx_3__1\,
I2 => s_axi_wstrb(3),
I3 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/p_451_in\,
I4 => wstrb_wrap_buffer_15,
O => p_0_out
);
cmd_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => m_axi_awready,
I1 => sr_awvalid,
I2 => buffer_Full_q,
I3 => cmd_push_block,
O => cmd_push_block0
);
data_Exists_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"5575FFFF00200020"
)
port map (
I0 => \buffer_Empty__3\,
I1 => buffer_Full_q,
I2 => sr_awvalid,
I3 => cmd_push_block,
I4 => M_READY_I,
I5 => data_Exists_I,
O => next_Data_Exists
);
data_Exists_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \buffer_Empty__3\
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => SR(0)
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_awvalid,
O => m_axi_awvalid
);
m_valid_i_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
O => m_valid_i_reg
);
s_axi_wready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F2FF0000"
)
port map (
I0 => \^q\(8),
I1 => wrap_buffer_available,
I2 => m_axi_wready,
I3 => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
I4 => \^use_rtl_curr_word.first_word_q_reg\,
O => s_axi_wready
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"77F7"
)
port map (
I0 => s_axi_aresetn,
I1 => m_axi_awready,
I2 => buffer_Full_q,
I3 => cmd_push_block,
O => s_ready_i_reg
);
wrap_buffer_available_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFAAAA"
)
port map (
I0 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\,
I1 => \^use_rtl_curr_word.first_word_q_reg\,
I2 => \^use_rtl_length.length_counter_q_reg[1]\,
I3 => s_axi_wlast,
I4 => wrap_buffer_available,
O => wrap_buffer_available_reg
);
wrap_buffer_available_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => s_axi_wvalid,
I1 => \^q\(8),
I2 => \^use_rtl_curr_word.first_word_q_reg\,
I3 => wrap_buffer_available,
I4 => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/word_completed__8\,
O => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 is
port (
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]_0\ : out STD_LOGIC;
use_wrap_buffer_reg : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_RTL_LENGTH.length_counter_q_reg[4]\ : out STD_LOGIC;
p_13_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\last_beat__6\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\current_word_1_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
cmd_push_block0 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
use_wrap_buffer_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
use_wrap_buffer : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\sel_first_word__0\ : in STD_LOGIC;
\pre_next_word_1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_word : in STD_LOGIC;
\M_AXI_RDATA_I_reg[127]\ : in STD_LOGIC_VECTOR ( 127 downto 0 );
\m_payload_i_reg[127]\ : in STD_LOGIC_VECTOR ( 127 downto 0 );
\current_word_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1;
architecture STRUCTURE of system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 is
signal M_READY_I : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/next_word_i__3\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal \buffer_Empty__3\ : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal \^current_word_1_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal \^last_beat__6\ : STD_LOGIC;
signal \m_payload_i[130]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_5_n_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_6_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal next_Data_Exists : STD_LOGIC;
signal \pre_next_word_1[1]_i_2_n_0\ : STD_LOGIC;
signal \pre_next_word_1[3]_i_3_n_0\ : STD_LOGIC;
signal rd_cmd_complete_wrap : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_cmd_last_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_cmd_mask : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_cmd_modified : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_cmd_offset : STD_LOGIC_VECTOR ( 3 downto 2 );
signal rd_cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \s_axi_rdata[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[10]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[10]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[12]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[12]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[12]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[13]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[13]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[14]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[14]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[15]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[16]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[16]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[17]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[17]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[18]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[18]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[19]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[20]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[20]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[21]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[21]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[22]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[22]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[22]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[23]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[23]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[23]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[24]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[24]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[24]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[25]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[25]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[25]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[26]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[26]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[26]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[27]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[27]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[27]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[28]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[28]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[28]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[29]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[29]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[29]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[30]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[30]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_13_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_14_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \s_axi_rdata[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_1_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_2_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_4_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_5_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_6_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_3_n_0 : STD_LOGIC;
signal \^use_wrap_buffer_reg\ : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1__0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1__0\ : label is "soft_lutpair75";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][14]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][30]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][31]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][31]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][31]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][32]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][33]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][34]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \cmd_push_block_i_1__0\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \current_word_1[2]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \current_word_1[3]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \data_Exists_I_i_2__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_3\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_5\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_6\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_valid_i_i_2__0\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \pre_next_word_1[3]_i_5\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \s_axi_rdata[31]_INST_0_i_7\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_5 : label is "soft_lutpair73";
attribute SOFT_HLUTNM of s_axi_rvalid_INST_0 : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \s_ready_i_i_2__0\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of use_wrap_buffer_i_3 : label is "soft_lutpair72";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]_0\ <= \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\;
\current_word_1_reg[3]\(3 downto 0) <= \^current_word_1_reg[3]\(3 downto 0);
\last_beat__6\ <= \^last_beat__6\;
\m_payload_i_reg[0]\(0) <= \^m_payload_i_reg[0]\(0);
s_axi_rlast <= \^s_axi_rlast\;
use_wrap_buffer_reg <= \^use_wrap_buffer_reg\;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => rd_cmd_step(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => rd_cmd_mask(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => rd_cmd_mask(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => rd_cmd_mask(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\,
Q => rd_cmd_mask(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => rd_cmd_offset(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => rd_cmd_offset(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => rd_cmd_last_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => rd_cmd_last_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => rd_cmd_last_word(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => rd_cmd_last_word(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => rd_cmd_next_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => rd_cmd_next_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => rd_cmd_next_word(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => rd_cmd_next_word(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => rd_cmd_first_word(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => rd_cmd_first_word(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => rd_cmd_first_word(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\,
Q => rd_cmd_first_word(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\,
Q => \^q\(8),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\,
Q => rd_cmd_complete_wrap,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\,
Q => rd_cmd_modified,
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\,
Q => \^q\(9),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => rd_cmd_step(0),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => rd_cmd_step(1),
R => s_axi_aresetn
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"A800FFFF"
)
port map (
I0 => \^s_axi_rlast\,
I1 => use_wrap_buffer,
I2 => mr_rvalid,
I3 => s_axi_rready,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
O => M_READY_I
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => M_READY_I,
D => data_Exists_I,
Q => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9999999999999699"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg\(1),
I1 => \USE_RTL_ADDR.addr_q_reg\(0),
I2 => cmd_push_block,
I3 => sr_arvalid,
I4 => buffer_Full_q,
I5 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9A96AA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg\(2),
I1 => \USE_RTL_ADDR.addr_q_reg\(0),
I2 => \USE_RTL_ADDR.addr_q_reg\(1),
I3 => valid_Write,
I4 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9AAA96AAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg\(3),
I1 => \USE_RTL_ADDR.addr_q_reg\(2),
I2 => \USE_RTL_ADDR.addr_q_reg\(0),
I3 => \USE_RTL_ADDR.addr_q_reg\(1),
I4 => valid_Write,
I5 => M_READY_I,
O => \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444434400000000"
)
port map (
I0 => \buffer_Empty__3\,
I1 => M_READY_I,
I2 => buffer_Full_q,
I3 => sr_arvalid,
I4 => cmd_push_block,
I5 => data_Exists_I,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg\(4),
I1 => \USE_RTL_ADDR.addr_q_reg\(3),
I2 => \USE_RTL_ADDR.addr_q_reg\(2),
I3 => \USE_RTL_ADDR.addr_q_reg\(0),
I4 => \USE_RTL_ADDR.addr_q_reg\(1),
I5 => \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\,
O => \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDD55555FFFFFFFF"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
I1 => s_axi_rready,
I2 => mr_rvalid,
I3 => use_wrap_buffer,
I4 => \^s_axi_rlast\,
I5 => valid_Write,
O => \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg\(0),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg\(1),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg\(2),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg\(3),
R => s_axi_aresetn
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg\(4),
R => s_axi_aresetn
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cmd_push_block,
I1 => sr_arvalid,
I2 => buffer_Full_q,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(28),
Q => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(29),
Q => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(30),
Q => \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(31),
Q => \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(32),
Q => \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF0F4F0FFF0"
)
port map (
I0 => use_wrap_buffer,
I1 => \^s_axi_rlast\,
I2 => \m_payload_i[130]_i_4_n_0\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
I4 => rd_cmd_modified,
I5 => \^q\(9),
O => p_13_in
);
\USE_RTL_LENGTH.length_counter_q[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"11110111FFFFFFFF"
)
port map (
I0 => \m_payload_i[130]_i_5_n_0\,
I1 => \m_payload_i[130]_i_4_n_0\,
I2 => \^s_axi_rlast\,
I3 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
I4 => use_wrap_buffer,
I5 => s_axi_rready,
O => \USE_RTL_LENGTH.length_counter_q_reg[4]\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00200000"
)
port map (
I0 => sr_arvalid,
I1 => cmd_push_block,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\,
I3 => M_READY_I,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg\(2),
I1 => \USE_RTL_ADDR.addr_q_reg\(3),
I2 => \USE_RTL_ADDR.addr_q_reg\(4),
I3 => \USE_RTL_ADDR.addr_q_reg\(1),
I4 => \USE_RTL_ADDR.addr_q_reg\(0),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0\,
Q => buffer_Full_q,
R => s_axi_aresetn
);
\cmd_push_block_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => m_axi_arready,
I1 => sr_arvalid,
I2 => buffer_Full_q,
I3 => cmd_push_block,
O => cmd_push_block0
);
\current_word_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE020000"
)
port map (
I0 => \pre_next_word_1_reg[3]\(0),
I1 => \^q\(9),
I2 => first_word,
I3 => rd_cmd_next_word(0),
I4 => rd_cmd_mask(0),
O => \^current_word_1_reg[3]\(0)
);
\current_word_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE020000"
)
port map (
I0 => \pre_next_word_1_reg[3]\(1),
I1 => \^q\(9),
I2 => first_word,
I3 => rd_cmd_next_word(1),
I4 => rd_cmd_mask(1),
O => \^current_word_1_reg[3]\(1)
);
\current_word_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(2),
I1 => rd_cmd_next_word(2),
I2 => first_word,
I3 => \^q\(9),
I4 => \pre_next_word_1_reg[3]\(2),
O => \^current_word_1_reg[3]\(2)
);
\current_word_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE020000"
)
port map (
I0 => \pre_next_word_1_reg[3]\(3),
I1 => \^q\(9),
I2 => first_word,
I3 => rd_cmd_next_word(3),
I4 => rd_cmd_mask(3),
O => \^current_word_1_reg[3]\(3)
);
\data_Exists_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5575FFFF00200020"
)
port map (
I0 => \buffer_Empty__3\,
I1 => buffer_Full_q,
I2 => sr_arvalid,
I3 => cmd_push_block,
I4 => M_READY_I,
I5 => data_Exists_I,
O => next_Data_Exists
);
\data_Exists_I_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg\(0),
I1 => \USE_RTL_ADDR.addr_q_reg\(1),
I2 => \USE_RTL_ADDR.addr_q_reg\(2),
I3 => \USE_RTL_ADDR.addr_q_reg\(4),
I4 => \USE_RTL_ADDR.addr_q_reg\(3),
O => \buffer_Empty__3\
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => s_axi_aresetn
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_arvalid,
O => m_axi_arvalid
);
\m_payload_i[130]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA80FFFFFFFF"
)
port map (
I0 => s_axi_rready,
I1 => \m_payload_i[130]_i_3_n_0\,
I2 => \^s_axi_rlast\,
I3 => \m_payload_i[130]_i_4_n_0\,
I4 => \m_payload_i[130]_i_5_n_0\,
I5 => mr_rvalid,
O => \^m_payload_i_reg[0]\(0)
);
\m_payload_i[130]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
I1 => use_wrap_buffer,
O => \m_payload_i[130]_i_3_n_0\
);
\m_payload_i[130]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
I1 => \m_payload_i[130]_i_6_n_0\,
I2 => \^current_word_1_reg[3]\(3),
I3 => rd_cmd_complete_wrap,
I4 => \^current_word_1_reg[3]\(0),
I5 => \^current_word_1_reg[3]\(1),
O => \m_payload_i[130]_i_4_n_0\
);
\m_payload_i[130]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B0"
)
port map (
I0 => \^q\(9),
I1 => rd_cmd_modified,
I2 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
O => \m_payload_i[130]_i_5_n_0\
);
\m_payload_i[130]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FDFFFF"
)
port map (
I0 => \pre_next_word_1_reg[3]\(2),
I1 => \^q\(9),
I2 => first_word,
I3 => rd_cmd_next_word(2),
I4 => rd_cmd_mask(2),
O => \m_payload_i[130]_i_6_n_0\
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF00"
)
port map (
I0 => \^m_payload_i_reg[0]\(0),
I1 => m_axi_rvalid,
I2 => s_ready_i_reg_0,
I3 => \aresetn_d_reg[1]\,
O => m_valid_i_reg_0
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
O => m_valid_i_reg
);
\pre_next_word_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"54570000ABA80000"
)
port map (
I0 => rd_cmd_next_word(0),
I1 => first_word,
I2 => \^q\(9),
I3 => \pre_next_word_1_reg[3]\(0),
I4 => rd_cmd_mask(0),
I5 => rd_cmd_step(0),
O => D(0)
);
\pre_next_word_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"56A60000A9590000"
)
port map (
I0 => rd_cmd_step(1),
I1 => \pre_next_word_1_reg[3]\(1),
I2 => \sel_first_word__0\,
I3 => rd_cmd_next_word(1),
I4 => rd_cmd_mask(1),
I5 => \pre_next_word_1[1]_i_2_n_0\,
O => D(1)
);
\pre_next_word_1[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"5557FFF7"
)
port map (
I0 => rd_cmd_step(0),
I1 => \pre_next_word_1_reg[3]\(0),
I2 => \^q\(9),
I3 => first_word,
I4 => rd_cmd_next_word(0),
O => \pre_next_word_1[1]_i_2_n_0\
);
\pre_next_word_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B80047004700B800"
)
port map (
I0 => rd_cmd_next_word(2),
I1 => \sel_first_word__0\,
I2 => \pre_next_word_1_reg[3]\(2),
I3 => rd_cmd_mask(2),
I4 => rd_cmd_step(2),
I5 => \pre_next_word_1[3]_i_3_n_0\,
O => D(2)
);
\pre_next_word_1[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"17E80000"
)
port map (
I0 => rd_cmd_step(2),
I1 => \pre_next_word_1[3]_i_3_n_0\,
I2 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/next_word_i__3\(2),
I3 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/next_word_i__3\(3),
I4 => rd_cmd_mask(3),
O => D(3)
);
\pre_next_word_1[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDFDDD544454440"
)
port map (
I0 => \pre_next_word_1[1]_i_2_n_0\,
I1 => rd_cmd_next_word(1),
I2 => first_word,
I3 => \^q\(9),
I4 => \pre_next_word_1_reg[3]\(1),
I5 => rd_cmd_step(1),
O => \pre_next_word_1[3]_i_3_n_0\
);
\pre_next_word_1[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => rd_cmd_next_word(2),
I1 => first_word,
I2 => \^q\(9),
I3 => \pre_next_word_1_reg[3]\(2),
O => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/next_word_i__3\(2)
);
\pre_next_word_1[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => rd_cmd_next_word(3),
I1 => first_word,
I2 => \^q\(9),
I3 => \pre_next_word_1_reg[3]\(3),
O => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/next_word_i__3\(3)
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[0]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(96),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(96),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[0]_INST_0_i_2_n_0\,
O => s_axi_rdata(0)
);
\s_axi_rdata[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(64),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(64),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[0]_INST_0_i_1_n_0\
);
\s_axi_rdata[0]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(32),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(32),
I4 => \s_axi_rdata[0]_INST_0_i_3_n_0\,
O => \s_axi_rdata[0]_INST_0_i_2_n_0\
);
\s_axi_rdata[0]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(0),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(0),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[0]_INST_0_i_3_n_0\
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[10]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(106),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(106),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[10]_INST_0_i_2_n_0\,
O => s_axi_rdata(10)
);
\s_axi_rdata[10]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(74),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(74),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[10]_INST_0_i_1_n_0\
);
\s_axi_rdata[10]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(42),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(42),
I4 => \s_axi_rdata[10]_INST_0_i_3_n_0\,
O => \s_axi_rdata[10]_INST_0_i_2_n_0\
);
\s_axi_rdata[10]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(10),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(10),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[10]_INST_0_i_3_n_0\
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[11]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(107),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(107),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[11]_INST_0_i_2_n_0\,
O => s_axi_rdata(11)
);
\s_axi_rdata[11]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(75),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(75),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[11]_INST_0_i_1_n_0\
);
\s_axi_rdata[11]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(43),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(43),
I4 => \s_axi_rdata[11]_INST_0_i_3_n_0\,
O => \s_axi_rdata[11]_INST_0_i_2_n_0\
);
\s_axi_rdata[11]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(11),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(11),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[11]_INST_0_i_3_n_0\
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[12]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(108),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(108),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[12]_INST_0_i_2_n_0\,
O => s_axi_rdata(12)
);
\s_axi_rdata[12]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(76),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(76),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[12]_INST_0_i_1_n_0\
);
\s_axi_rdata[12]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(44),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(44),
I4 => \s_axi_rdata[12]_INST_0_i_3_n_0\,
O => \s_axi_rdata[12]_INST_0_i_2_n_0\
);
\s_axi_rdata[12]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(12),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(12),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[12]_INST_0_i_3_n_0\
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[13]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(109),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(109),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[13]_INST_0_i_2_n_0\,
O => s_axi_rdata(13)
);
\s_axi_rdata[13]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(77),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(77),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[13]_INST_0_i_1_n_0\
);
\s_axi_rdata[13]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(45),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(45),
I4 => \s_axi_rdata[13]_INST_0_i_3_n_0\,
O => \s_axi_rdata[13]_INST_0_i_2_n_0\
);
\s_axi_rdata[13]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(13),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(13),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[13]_INST_0_i_3_n_0\
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[14]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(110),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(110),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[14]_INST_0_i_2_n_0\,
O => s_axi_rdata(14)
);
\s_axi_rdata[14]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(78),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(78),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[14]_INST_0_i_1_n_0\
);
\s_axi_rdata[14]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(46),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(46),
I4 => \s_axi_rdata[14]_INST_0_i_3_n_0\,
O => \s_axi_rdata[14]_INST_0_i_2_n_0\
);
\s_axi_rdata[14]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(14),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(14),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[14]_INST_0_i_3_n_0\
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[15]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(111),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(111),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[15]_INST_0_i_2_n_0\,
O => s_axi_rdata(15)
);
\s_axi_rdata[15]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(79),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(79),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[15]_INST_0_i_1_n_0\
);
\s_axi_rdata[15]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(47),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(47),
I4 => \s_axi_rdata[15]_INST_0_i_3_n_0\,
O => \s_axi_rdata[15]_INST_0_i_2_n_0\
);
\s_axi_rdata[15]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(15),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(15),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[15]_INST_0_i_3_n_0\
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[16]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(112),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(112),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[16]_INST_0_i_2_n_0\,
O => s_axi_rdata(16)
);
\s_axi_rdata[16]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(80),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(80),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[16]_INST_0_i_1_n_0\
);
\s_axi_rdata[16]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(48),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(48),
I4 => \s_axi_rdata[16]_INST_0_i_3_n_0\,
O => \s_axi_rdata[16]_INST_0_i_2_n_0\
);
\s_axi_rdata[16]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(16),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(16),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[16]_INST_0_i_3_n_0\
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[17]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(113),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(113),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[17]_INST_0_i_2_n_0\,
O => s_axi_rdata(17)
);
\s_axi_rdata[17]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(81),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(81),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[17]_INST_0_i_1_n_0\
);
\s_axi_rdata[17]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(49),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(49),
I4 => \s_axi_rdata[17]_INST_0_i_3_n_0\,
O => \s_axi_rdata[17]_INST_0_i_2_n_0\
);
\s_axi_rdata[17]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(17),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(17),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[17]_INST_0_i_3_n_0\
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[18]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(114),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(114),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[18]_INST_0_i_2_n_0\,
O => s_axi_rdata(18)
);
\s_axi_rdata[18]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(82),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(82),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[18]_INST_0_i_1_n_0\
);
\s_axi_rdata[18]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(50),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(50),
I4 => \s_axi_rdata[18]_INST_0_i_3_n_0\,
O => \s_axi_rdata[18]_INST_0_i_2_n_0\
);
\s_axi_rdata[18]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(18),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(18),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[18]_INST_0_i_3_n_0\
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[19]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(115),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(115),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[19]_INST_0_i_2_n_0\,
O => s_axi_rdata(19)
);
\s_axi_rdata[19]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(83),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(83),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[19]_INST_0_i_1_n_0\
);
\s_axi_rdata[19]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(51),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(51),
I4 => \s_axi_rdata[19]_INST_0_i_3_n_0\,
O => \s_axi_rdata[19]_INST_0_i_2_n_0\
);
\s_axi_rdata[19]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(19),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(19),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[19]_INST_0_i_3_n_0\
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[1]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(97),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(97),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[1]_INST_0_i_2_n_0\,
O => s_axi_rdata(1)
);
\s_axi_rdata[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(65),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(65),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[1]_INST_0_i_1_n_0\
);
\s_axi_rdata[1]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(33),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(33),
I4 => \s_axi_rdata[1]_INST_0_i_3_n_0\,
O => \s_axi_rdata[1]_INST_0_i_2_n_0\
);
\s_axi_rdata[1]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(1),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(1),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[1]_INST_0_i_3_n_0\
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[20]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(116),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(116),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[20]_INST_0_i_2_n_0\,
O => s_axi_rdata(20)
);
\s_axi_rdata[20]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(84),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(84),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[20]_INST_0_i_1_n_0\
);
\s_axi_rdata[20]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(52),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(52),
I4 => \s_axi_rdata[20]_INST_0_i_3_n_0\,
O => \s_axi_rdata[20]_INST_0_i_2_n_0\
);
\s_axi_rdata[20]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(20),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(20),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[20]_INST_0_i_3_n_0\
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[21]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(117),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(117),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[21]_INST_0_i_2_n_0\,
O => s_axi_rdata(21)
);
\s_axi_rdata[21]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(85),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(85),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[21]_INST_0_i_1_n_0\
);
\s_axi_rdata[21]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(53),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(53),
I4 => \s_axi_rdata[21]_INST_0_i_3_n_0\,
O => \s_axi_rdata[21]_INST_0_i_2_n_0\
);
\s_axi_rdata[21]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(21),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(21),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[21]_INST_0_i_3_n_0\
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[22]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(118),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(118),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[22]_INST_0_i_2_n_0\,
O => s_axi_rdata(22)
);
\s_axi_rdata[22]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(86),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(86),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[22]_INST_0_i_1_n_0\
);
\s_axi_rdata[22]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(54),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(54),
I4 => \s_axi_rdata[22]_INST_0_i_3_n_0\,
O => \s_axi_rdata[22]_INST_0_i_2_n_0\
);
\s_axi_rdata[22]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(22),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(22),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[22]_INST_0_i_3_n_0\
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[23]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(119),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(119),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[23]_INST_0_i_2_n_0\,
O => s_axi_rdata(23)
);
\s_axi_rdata[23]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(87),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(87),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[23]_INST_0_i_1_n_0\
);
\s_axi_rdata[23]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(55),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(55),
I4 => \s_axi_rdata[23]_INST_0_i_3_n_0\,
O => \s_axi_rdata[23]_INST_0_i_2_n_0\
);
\s_axi_rdata[23]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(23),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(23),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[23]_INST_0_i_3_n_0\
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[24]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(120),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(120),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[24]_INST_0_i_2_n_0\,
O => s_axi_rdata(24)
);
\s_axi_rdata[24]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(88),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(88),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[24]_INST_0_i_1_n_0\
);
\s_axi_rdata[24]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(56),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(56),
I4 => \s_axi_rdata[24]_INST_0_i_3_n_0\,
O => \s_axi_rdata[24]_INST_0_i_2_n_0\
);
\s_axi_rdata[24]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(24),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(24),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[24]_INST_0_i_3_n_0\
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[25]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(121),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(121),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[25]_INST_0_i_2_n_0\,
O => s_axi_rdata(25)
);
\s_axi_rdata[25]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(89),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(89),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[25]_INST_0_i_1_n_0\
);
\s_axi_rdata[25]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(57),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(57),
I4 => \s_axi_rdata[25]_INST_0_i_3_n_0\,
O => \s_axi_rdata[25]_INST_0_i_2_n_0\
);
\s_axi_rdata[25]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(25),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(25),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[25]_INST_0_i_3_n_0\
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[26]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(122),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(122),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[26]_INST_0_i_2_n_0\,
O => s_axi_rdata(26)
);
\s_axi_rdata[26]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(90),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(90),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[26]_INST_0_i_1_n_0\
);
\s_axi_rdata[26]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(58),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(58),
I4 => \s_axi_rdata[26]_INST_0_i_3_n_0\,
O => \s_axi_rdata[26]_INST_0_i_2_n_0\
);
\s_axi_rdata[26]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(26),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(26),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[26]_INST_0_i_3_n_0\
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[27]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(123),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(123),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[27]_INST_0_i_2_n_0\,
O => s_axi_rdata(27)
);
\s_axi_rdata[27]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(91),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(91),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[27]_INST_0_i_1_n_0\
);
\s_axi_rdata[27]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(59),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(59),
I4 => \s_axi_rdata[27]_INST_0_i_3_n_0\,
O => \s_axi_rdata[27]_INST_0_i_2_n_0\
);
\s_axi_rdata[27]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(27),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(27),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[27]_INST_0_i_3_n_0\
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[28]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(124),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(124),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[28]_INST_0_i_2_n_0\,
O => s_axi_rdata(28)
);
\s_axi_rdata[28]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(92),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(92),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[28]_INST_0_i_1_n_0\
);
\s_axi_rdata[28]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(60),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(60),
I4 => \s_axi_rdata[28]_INST_0_i_3_n_0\,
O => \s_axi_rdata[28]_INST_0_i_2_n_0\
);
\s_axi_rdata[28]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(28),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(28),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[28]_INST_0_i_3_n_0\
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[29]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(125),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(125),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[29]_INST_0_i_2_n_0\,
O => s_axi_rdata(29)
);
\s_axi_rdata[29]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(93),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(93),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[29]_INST_0_i_1_n_0\
);
\s_axi_rdata[29]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(61),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(61),
I4 => \s_axi_rdata[29]_INST_0_i_3_n_0\,
O => \s_axi_rdata[29]_INST_0_i_2_n_0\
);
\s_axi_rdata[29]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(29),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(29),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[29]_INST_0_i_3_n_0\
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[2]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(98),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(98),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[2]_INST_0_i_2_n_0\,
O => s_axi_rdata(2)
);
\s_axi_rdata[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(66),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(66),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[2]_INST_0_i_1_n_0\
);
\s_axi_rdata[2]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(34),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(34),
I4 => \s_axi_rdata[2]_INST_0_i_3_n_0\,
O => \s_axi_rdata[2]_INST_0_i_2_n_0\
);
\s_axi_rdata[2]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(2),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(2),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[2]_INST_0_i_3_n_0\
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[30]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(126),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(126),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[30]_INST_0_i_2_n_0\,
O => s_axi_rdata(30)
);
\s_axi_rdata[30]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(94),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(94),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[30]_INST_0_i_1_n_0\
);
\s_axi_rdata[30]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(62),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(62),
I4 => \s_axi_rdata[30]_INST_0_i_3_n_0\,
O => \s_axi_rdata[30]_INST_0_i_2_n_0\
);
\s_axi_rdata[30]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(30),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(30),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[30]_INST_0_i_3_n_0\
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(127),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(127),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[31]_INST_0_i_4_n_0\,
O => s_axi_rdata(31)
);
\s_axi_rdata[31]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(95),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(95),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[31]_INST_0_i_1_n_0\
);
\s_axi_rdata[31]_INST_0_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555540400000000"
)
port map (
I0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(1),
I1 => \current_word_1_reg[3]_0\(2),
I2 => \sel_first_word__0\,
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
I5 => use_wrap_buffer,
O => \s_axi_rdata[31]_INST_0_i_10_n_0\
);
\s_axi_rdata[31]_INST_0_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(31),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(31),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[31]_INST_0_i_11_n_0\
);
\s_axi_rdata[31]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFE02"
)
port map (
I0 => \current_word_1_reg[3]_0\(2),
I1 => \^q\(9),
I2 => first_word,
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
O => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(0)
);
\s_axi_rdata[31]_INST_0_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000015100000000"
)
port map (
I0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(1),
I1 => \current_word_1_reg[3]_0\(2),
I2 => \sel_first_word__0\,
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
I5 => use_wrap_buffer,
O => \s_axi_rdata[31]_INST_0_i_13_n_0\
);
\s_axi_rdata[31]_INST_0_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000151"
)
port map (
I0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(1),
I1 => \current_word_1_reg[3]_0\(2),
I2 => \sel_first_word__0\,
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
I5 => use_wrap_buffer,
O => \s_axi_rdata[31]_INST_0_i_14_n_0\
);
\s_axi_rdata[31]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA80800000000"
)
port map (
I0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(1),
I1 => \current_word_1_reg[3]_0\(2),
I2 => \sel_first_word__0\,
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
I5 => use_wrap_buffer,
O => \s_axi_rdata[31]_INST_0_i_2_n_0\
);
\s_axi_rdata[31]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA808"
)
port map (
I0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(1),
I1 => \current_word_1_reg[3]_0\(2),
I2 => \sel_first_word__0\,
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
I5 => use_wrap_buffer,
O => \s_axi_rdata[31]_INST_0_i_3_n_0\
);
\s_axi_rdata[31]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(63),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(63),
I4 => \s_axi_rdata[31]_INST_0_i_11_n_0\,
O => \s_axi_rdata[31]_INST_0_i_4_n_0\
);
\s_axi_rdata[31]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"5554445400000000"
)
port map (
I0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(0),
I1 => rd_cmd_offset(3),
I2 => \current_word_1_reg[3]_0\(3),
I3 => \sel_first_word__0\,
I4 => rd_cmd_first_word(3),
I5 => use_wrap_buffer,
O => \s_axi_rdata[31]_INST_0_i_5_n_0\
);
\s_axi_rdata[31]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055544454"
)
port map (
I0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(0),
I1 => rd_cmd_offset(3),
I2 => \current_word_1_reg[3]_0\(3),
I3 => \sel_first_word__0\,
I4 => rd_cmd_first_word(3),
I5 => use_wrap_buffer,
O => \s_axi_rdata[31]_INST_0_i_6_n_0\
);
\s_axi_rdata[31]_INST_0_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEAAAE"
)
port map (
I0 => rd_cmd_offset(3),
I1 => \current_word_1_reg[3]_0\(3),
I2 => \^q\(9),
I3 => first_word,
I4 => rd_cmd_first_word(3),
O => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(1)
);
\s_axi_rdata[31]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555404"
)
port map (
I0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst/current_index\(1),
I1 => \current_word_1_reg[3]_0\(2),
I2 => \sel_first_word__0\,
I3 => rd_cmd_first_word(2),
I4 => rd_cmd_offset(2),
I5 => use_wrap_buffer,
O => \s_axi_rdata[31]_INST_0_i_9_n_0\
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[3]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(99),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(99),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[3]_INST_0_i_2_n_0\,
O => s_axi_rdata(3)
);
\s_axi_rdata[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(67),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(67),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[3]_INST_0_i_1_n_0\
);
\s_axi_rdata[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(35),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(35),
I4 => \s_axi_rdata[3]_INST_0_i_3_n_0\,
O => \s_axi_rdata[3]_INST_0_i_2_n_0\
);
\s_axi_rdata[3]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(3),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(3),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[3]_INST_0_i_3_n_0\
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[4]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(100),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(100),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[4]_INST_0_i_2_n_0\,
O => s_axi_rdata(4)
);
\s_axi_rdata[4]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(68),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(68),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[4]_INST_0_i_1_n_0\
);
\s_axi_rdata[4]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(36),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(36),
I4 => \s_axi_rdata[4]_INST_0_i_3_n_0\,
O => \s_axi_rdata[4]_INST_0_i_2_n_0\
);
\s_axi_rdata[4]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(4),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(4),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[4]_INST_0_i_3_n_0\
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[5]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(101),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(101),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[5]_INST_0_i_2_n_0\,
O => s_axi_rdata(5)
);
\s_axi_rdata[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(69),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(69),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[5]_INST_0_i_1_n_0\
);
\s_axi_rdata[5]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(37),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(37),
I4 => \s_axi_rdata[5]_INST_0_i_3_n_0\,
O => \s_axi_rdata[5]_INST_0_i_2_n_0\
);
\s_axi_rdata[5]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(5),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(5),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[5]_INST_0_i_3_n_0\
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[6]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(102),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(102),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[6]_INST_0_i_2_n_0\,
O => s_axi_rdata(6)
);
\s_axi_rdata[6]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(70),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(70),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[6]_INST_0_i_1_n_0\
);
\s_axi_rdata[6]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(38),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(38),
I4 => \s_axi_rdata[6]_INST_0_i_3_n_0\,
O => \s_axi_rdata[6]_INST_0_i_2_n_0\
);
\s_axi_rdata[6]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(6),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(6),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[6]_INST_0_i_3_n_0\
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[7]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(103),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(103),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[7]_INST_0_i_2_n_0\,
O => s_axi_rdata(7)
);
\s_axi_rdata[7]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(71),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(71),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[7]_INST_0_i_1_n_0\
);
\s_axi_rdata[7]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(39),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(39),
I4 => \s_axi_rdata[7]_INST_0_i_3_n_0\,
O => \s_axi_rdata[7]_INST_0_i_2_n_0\
);
\s_axi_rdata[7]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(7),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(7),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[7]_INST_0_i_3_n_0\
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[8]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(104),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(104),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[8]_INST_0_i_2_n_0\,
O => s_axi_rdata(8)
);
\s_axi_rdata[8]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(72),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(72),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[8]_INST_0_i_1_n_0\
);
\s_axi_rdata[8]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(40),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(40),
I4 => \s_axi_rdata[8]_INST_0_i_3_n_0\,
O => \s_axi_rdata[8]_INST_0_i_2_n_0\
);
\s_axi_rdata[8]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(8),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(8),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[8]_INST_0_i_3_n_0\
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \s_axi_rdata[9]_INST_0_i_1_n_0\,
I1 => \M_AXI_RDATA_I_reg[127]\(105),
I2 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
I3 => \m_payload_i_reg[127]\(105),
I4 => \s_axi_rdata[31]_INST_0_i_3_n_0\,
I5 => \s_axi_rdata[9]_INST_0_i_2_n_0\,
O => s_axi_rdata(9)
);
\s_axi_rdata[9]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(73),
I1 => \s_axi_rdata[31]_INST_0_i_5_n_0\,
I2 => \m_payload_i_reg[127]\(73),
I3 => \s_axi_rdata[31]_INST_0_i_6_n_0\,
O => \s_axi_rdata[9]_INST_0_i_1_n_0\
);
\s_axi_rdata[9]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \s_axi_rdata[31]_INST_0_i_9_n_0\,
I1 => \m_payload_i_reg[127]\(41),
I2 => \s_axi_rdata[31]_INST_0_i_10_n_0\,
I3 => \M_AXI_RDATA_I_reg[127]\(41),
I4 => \s_axi_rdata[9]_INST_0_i_3_n_0\,
O => \s_axi_rdata[9]_INST_0_i_2_n_0\
);
\s_axi_rdata[9]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \M_AXI_RDATA_I_reg[127]\(9),
I1 => \s_axi_rdata[31]_INST_0_i_13_n_0\,
I2 => \m_payload_i_reg[127]\(9),
I3 => \s_axi_rdata[31]_INST_0_i_14_n_0\,
O => \s_axi_rdata[9]_INST_0_i_3_n_0\
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"80808880"
)
port map (
I0 => s_axi_rlast_INST_0_i_1_n_0,
I1 => s_axi_rlast_INST_0_i_2_n_0,
I2 => use_wrap_buffer,
I3 => \^last_beat__6\,
I4 => wrap_buffer_available,
O => \^s_axi_rlast\
);
s_axi_rlast_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"999A999500000000"
)
port map (
I0 => rd_cmd_last_word(0),
I1 => rd_cmd_first_word(0),
I2 => first_word,
I3 => \^q\(9),
I4 => \current_word_1_reg[3]_0\(0),
I5 => s_axi_rlast_INST_0_i_4_n_0,
O => s_axi_rlast_INST_0_i_1_n_0
);
s_axi_rlast_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B847B8470000"
)
port map (
I0 => rd_cmd_first_word(2),
I1 => \sel_first_word__0\,
I2 => \current_word_1_reg[3]_0\(2),
I3 => rd_cmd_last_word(2),
I4 => rd_cmd_last_word(3),
I5 => s_axi_rlast_INST_0_i_5_n_0,
O => s_axi_rlast_INST_0_i_2_n_0
);
s_axi_rlast_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF100010001000"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => first_mi_word_q,
I3 => s_axi_rlast_INST_0_i_6_n_0,
I4 => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
I5 => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
O => \^last_beat__6\
);
s_axi_rlast_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FE0201FD"
)
port map (
I0 => \current_word_1_reg[3]_0\(1),
I1 => \^q\(9),
I2 => first_word,
I3 => rd_cmd_first_word(1),
I4 => rd_cmd_last_word(1),
O => s_axi_rlast_INST_0_i_4_n_0
);
s_axi_rlast_INST_0_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"5457"
)
port map (
I0 => rd_cmd_first_word(3),
I1 => first_word,
I2 => \^q\(9),
I3 => \current_word_1_reg[3]_0\(3),
O => s_axi_rlast_INST_0_i_5_n_0
);
s_axi_rlast_INST_0_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
I2 => \^q\(4),
I3 => \^q\(5),
I4 => \^q\(7),
I5 => \^q\(6),
O => s_axi_rlast_INST_0_i_6_n_0
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
I1 => mr_rvalid,
I2 => use_wrap_buffer,
O => s_axi_rvalid
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"77F7"
)
port map (
I0 => s_axi_aresetn_0,
I1 => m_axi_arready,
I2 => buffer_Full_q,
I3 => cmd_push_block,
O => s_ready_i_reg
);
use_wrap_buffer_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"80FF8080"
)
port map (
I0 => \^use_wrap_buffer_reg\,
I1 => \^last_beat__6\,
I2 => wrap_buffer_available,
I3 => use_wrap_buffer_i_3_n_0,
I4 => use_wrap_buffer,
O => use_wrap_buffer_reg_0
);
use_wrap_buffer_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8A8A8AAA8A8A8"
)
port map (
I0 => E(0),
I1 => \m_payload_i[130]_i_5_n_0\,
I2 => \m_payload_i[130]_i_4_n_0\,
I3 => \^s_axi_rlast\,
I4 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
I5 => use_wrap_buffer,
O => \^use_wrap_buffer_reg\
);
use_wrap_buffer_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"A8000000"
)
port map (
I0 => \^use_ff_out.use_rtl_output_pipeline.m_mesg_q_reg[0]_0\,
I1 => use_wrap_buffer,
I2 => mr_rvalid,
I3 => s_axi_rready,
I4 => \^s_axi_rlast\,
O => use_wrap_buffer_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer is
port (
wr_cmd_valid : out STD_LOGIC;
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
p_487_in : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
p_3_out4_out : out STD_LOGIC;
p_8_out : out STD_LOGIC;
p_11_out : out STD_LOGIC;
p_14_out : out STD_LOGIC;
p_17_out18_out : out STD_LOGIC;
p_22_out : out STD_LOGIC;
p_25_out26_out : out STD_LOGIC;
p_30_out : out STD_LOGIC;
\current_word_idx_1__0\ : out STD_LOGIC;
p_33_out : out STD_LOGIC;
p_37_out : out STD_LOGIC;
p_41_out : out STD_LOGIC;
p_44_out : out STD_LOGIC;
p_47_out : out STD_LOGIC;
p_51_out52_out : out STD_LOGIC;
p_55_out56_out : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_RTL_CURR_WORD.current_word_q_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]_0\ : out STD_LOGIC;
p_476_in : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[119]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_61_out__2\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[111]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_91_out__2\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[103]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_122_out__2\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[95]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_151_out__2\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[87]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_180_out__2\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[79]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_209_out__2\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[71]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_240_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_269_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_298_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_327_out__2\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_358_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_387_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_416_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_445_out__2\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\p_481_out__2\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]_0\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[119]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[14]\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[111]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[13]\ : out STD_LOGIC;
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[103]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[12]\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[95]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[11]\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[87]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[10]\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[79]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[9]\ : out STD_LOGIC;
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[8]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ : out STD_LOGIC;
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ : out STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
wrap_buffer_available_reg : out STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 1 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
sr_awvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
wstrb_wrap_buffer_15 : in STD_LOGIC;
wstrb_wrap_buffer_14 : in STD_LOGIC;
wstrb_wrap_buffer_13 : in STD_LOGIC;
wstrb_wrap_buffer_12 : in STD_LOGIC;
wstrb_wrap_buffer_11 : in STD_LOGIC;
wstrb_wrap_buffer_10 : in STD_LOGIC;
wstrb_wrap_buffer_9 : in STD_LOGIC;
wstrb_wrap_buffer_8 : in STD_LOGIC;
wstrb_wrap_buffer_7 : in STD_LOGIC;
wstrb_wrap_buffer_6 : in STD_LOGIC;
wstrb_wrap_buffer_5 : in STD_LOGIC;
wstrb_wrap_buffer_4 : in STD_LOGIC;
wstrb_wrap_buffer_3 : in STD_LOGIC;
wstrb_wrap_buffer_2 : in STD_LOGIC;
wstrb_wrap_buffer_1 : in STD_LOGIC;
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
first_mi_word_q : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\ : in STD_LOGIC;
\sel_first_word__0\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_word_q : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[4]\ : in STD_LOGIC;
\USE_RTL_CURR_WORD.current_word_q_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[0]\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer is
signal cmd_packed_wrap_i1_carry_n_1 : STD_LOGIC;
signal cmd_packed_wrap_i1_carry_n_2 : STD_LOGIC;
signal cmd_packed_wrap_i1_carry_n_3 : STD_LOGIC;
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_1 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_2 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_3 : STD_LOGIC;
signal NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_sub_sized_wrap0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
SR(0) => SR(0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]_0\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\,
\USE_REGISTER.M_AXI_WVALID_q_reg\ => \USE_REGISTER.M_AXI_WVALID_q_reg\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_REGISTER.M_AXI_WVALID_q_reg_0\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \USE_REGISTER.M_AXI_WVALID_q_reg_1\,
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ => \USE_REGISTER.M_AXI_WVALID_q_reg_2\,
\USE_RTL_CURR_WORD.current_word_q_reg[3]\(3 downto 0) => \USE_RTL_CURR_WORD.current_word_q_reg[3]\(3 downto 0),
\USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(3 downto 0) => \USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(3 downto 0),
\USE_RTL_CURR_WORD.first_word_q_reg\ => wr_cmd_valid,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(3 downto 0) => \USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(3 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\USE_RTL_LENGTH.length_counter_q_reg[0]\ => \USE_RTL_LENGTH.length_counter_q_reg[0]\,
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => p_487_in,
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\ => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
\USE_RTL_LENGTH.length_counter_q_reg[1]_1\(1 downto 0) => \USE_RTL_LENGTH.length_counter_q_reg[1]_0\(1 downto 0),
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
\USE_RTL_LENGTH.length_counter_q_reg[4]\ => \USE_RTL_LENGTH.length_counter_q_reg[4]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\ => p_476_in,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_0\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\(0),
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0) => \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\ => \current_word_idx_1__0\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]_0\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\(0),
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0) => \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0),
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[71]\(0) => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[71]\(0),
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[8]\ => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[8]\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]\(0) => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]\(0),
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[79]\(0) => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[79]\(0),
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[9]\ => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[9]\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[79]\(0) => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[79]\(0),
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[87]\(0) => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[87]\(0),
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[10]\ => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[10]\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[87]\(0) => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[87]\(0),
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[95]\(0) => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[95]\(0),
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[11]\ => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[11]\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[95]\(0) => \WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[95]\(0),
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[103]\(0) => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[103]\(0),
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[12]\ => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[12]\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[103]\(0) => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[103]\(0),
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[111]\(0) => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[111]\(0),
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[13]\ => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[13]\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[111]\(0) => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[111]\(0),
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[119]\(0) => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[119]\(0),
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[14]\ => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[14]\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[119]\(0) => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[119]\(0),
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]\(0) => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]\(0),
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]_0\ => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]_0\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]\ => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]_0\ => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]_0\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[127]\(0) => \WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[127]\(0),
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
first_mi_word_q => first_mi_word_q,
first_word_q => first_word_q,
\in\(32 downto 0) => \in\(32 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_wready => m_axi_wready,
m_valid_i_reg => m_valid_i_reg,
\out\ => \out\,
p_0_out => p_0_out,
p_11_out => p_11_out,
\p_122_out__2\ => \p_122_out__2\,
p_14_out => p_14_out,
\p_151_out__2\ => \p_151_out__2\,
p_17_out18_out => p_17_out18_out,
\p_180_out__2\ => \p_180_out__2\,
\p_209_out__2\ => \p_209_out__2\,
p_22_out => p_22_out,
\p_240_out__2\ => \p_240_out__2\,
p_25_out26_out => p_25_out26_out,
\p_269_out__2\ => \p_269_out__2\,
\p_298_out__2\ => \p_298_out__2\,
p_30_out => p_30_out,
\p_327_out__2\ => \p_327_out__2\,
p_33_out => p_33_out,
\p_358_out__2\ => \p_358_out__2\,
p_37_out => p_37_out,
\p_387_out__2\ => \p_387_out__2\,
p_3_out4_out => p_3_out4_out,
\p_416_out__2\ => \p_416_out__2\,
p_41_out => p_41_out,
\p_445_out__2\ => \p_445_out__2\,
p_44_out => p_44_out,
p_47_out => p_47_out,
\p_481_out__2\ => \p_481_out__2\,
p_51_out52_out => p_51_out52_out,
p_55_out56_out => p_55_out56_out,
\p_61_out__2\ => \p_61_out__2\,
p_8_out => p_8_out,
\p_91_out__2\ => \p_91_out__2\,
s_axi_aresetn => s_axi_aresetn,
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
s_ready_i_reg => s_ready_i_reg,
\sel_first_word__0\ => \sel_first_word__0\,
sr_awvalid => sr_awvalid,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => wrap_buffer_available_reg,
wstrb_wrap_buffer_1 => wstrb_wrap_buffer_1,
wstrb_wrap_buffer_10 => wstrb_wrap_buffer_10,
wstrb_wrap_buffer_11 => wstrb_wrap_buffer_11,
wstrb_wrap_buffer_12 => wstrb_wrap_buffer_12,
wstrb_wrap_buffer_13 => wstrb_wrap_buffer_13,
wstrb_wrap_buffer_14 => wstrb_wrap_buffer_14,
wstrb_wrap_buffer_15 => wstrb_wrap_buffer_15,
wstrb_wrap_buffer_2 => wstrb_wrap_buffer_2,
wstrb_wrap_buffer_3 => wstrb_wrap_buffer_3,
wstrb_wrap_buffer_4 => wstrb_wrap_buffer_4,
wstrb_wrap_buffer_5 => wstrb_wrap_buffer_5,
wstrb_wrap_buffer_6 => wstrb_wrap_buffer_6,
wstrb_wrap_buffer_7 => wstrb_wrap_buffer_7,
wstrb_wrap_buffer_8 => wstrb_wrap_buffer_8,
wstrb_wrap_buffer_9 => wstrb_wrap_buffer_9
);
cmd_packed_wrap_i1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
CO(2) => cmd_packed_wrap_i1_carry_n_1,
CO(1) => cmd_packed_wrap_i1_carry_n_2,
CO(0) => cmd_packed_wrap_i1_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => \m_payload_i_reg[50]\(3 downto 0),
O(3 downto 0) => NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0)
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => SR(0)
);
sub_sized_wrap0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => sub_sized_wrap0_carry_n_1,
CO(1) => sub_sized_wrap0_carry_n_2,
CO(0) => sub_sized_wrap0_carry_n_3,
CYINIT => '1',
DI(3 downto 2) => B"00",
DI(1 downto 0) => DI(1 downto 0),
O(3 downto 0) => NLW_sub_sized_wrap0_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ is
port (
rd_cmd_valid : out STD_LOGIC;
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
use_wrap_buffer_reg : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_RTL_LENGTH.length_counter_q_reg[4]\ : out STD_LOGIC;
p_13_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\last_beat__6\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\current_word_1_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_ready_i_reg : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
use_wrap_buffer_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 1 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
use_wrap_buffer : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[2]\ : in STD_LOGIC;
\sel_first_word__0\ : in STD_LOGIC;
\pre_next_word_1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_word : in STD_LOGIC;
\M_AXI_RDATA_I_reg[127]\ : in STD_LOGIC_VECTOR ( 127 downto 0 );
\m_payload_i_reg[127]\ : in STD_LOGIC_VECTOR ( 127 downto 0 );
\current_word_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\;
architecture STRUCTURE of \system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\ is
signal cmd_packed_wrap_i1_carry_n_1 : STD_LOGIC;
signal cmd_packed_wrap_i1_carry_n_2 : STD_LOGIC;
signal cmd_packed_wrap_i1_carry_n_3 : STD_LOGIC;
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_1 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_2 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_3 : STD_LOGIC;
signal NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_sub_sized_wrap0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
\M_AXI_RDATA_I_reg[127]\(127 downto 0) => \M_AXI_RDATA_I_reg[127]\(127 downto 0),
Q(9 downto 0) => Q(9 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]_0\ => rd_cmd_valid,
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_RTL_LENGTH.length_counter_q_reg[2]\,
\USE_RTL_LENGTH.length_counter_q_reg[4]\ => \USE_RTL_LENGTH.length_counter_q_reg[4]\,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
\current_word_1_reg[3]\(3 downto 0) => \current_word_1_reg[3]\(3 downto 0),
\current_word_1_reg[3]_0\(3 downto 0) => \current_word_1_reg[3]_0\(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
\in\(32 downto 0) => \in\(32 downto 0),
\last_beat__6\ => \last_beat__6\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_rvalid => m_axi_rvalid,
\m_payload_i_reg[0]\(0) => \m_payload_i_reg[0]\(0),
\m_payload_i_reg[127]\(127 downto 0) => \m_payload_i_reg[127]\(127 downto 0),
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
mr_rvalid => mr_rvalid,
\out\ => \out\,
p_13_in => p_13_in,
\pre_next_word_1_reg[3]\(3 downto 0) => \pre_next_word_1_reg[3]\(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => s_ready_i_reg_0,
\sel_first_word__0\ => \sel_first_word__0\,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => use_wrap_buffer_reg,
use_wrap_buffer_reg_0 => use_wrap_buffer_reg_0,
wrap_buffer_available => wrap_buffer_available
);
cmd_packed_wrap_i1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
CO(2) => cmd_packed_wrap_i1_carry_n_1,
CO(1) => cmd_packed_wrap_i1_carry_n_2,
CO(0) => cmd_packed_wrap_i1_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => \m_payload_i_reg[50]\(3 downto 0),
O(3 downto 0) => NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0)
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => s_axi_aresetn
);
sub_sized_wrap0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => sub_sized_wrap0_carry_n_1,
CO(1) => sub_sized_wrap0_carry_n_2,
CO(0) => sub_sized_wrap0_carry_n_3,
CYINIT => '1',
DI(3 downto 2) => B"00",
DI(1 downto 0) => DI(1 downto 0),
O(3 downto 0) => NLW_sub_sized_wrap0_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice is
port (
mr_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[4]\ : out STD_LOGIC;
\USE_RTL_LENGTH.first_mi_word_q_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 129 downto 0 );
s_ready_i_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rvalid : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC;
p_13_in : in STD_LOGIC;
first_mi_word_q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice is
begin
r_pipe: entity work.\system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
Q(129 downto 0) => Q(129 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_RTL_LENGTH.first_mi_word_q_reg\,
\USE_RTL_LENGTH.length_counter_q_reg[4]\ => \USE_RTL_LENGTH.length_counter_q_reg[4]\,
first_mi_word_q => first_mi_word_q,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
p_0_in(0) => p_0_in(0),
p_13_in => p_13_in,
rd_cmd_valid => rd_cmd_valid,
s_axi_rready => s_axi_rready,
s_ready_i_reg_0 => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
port (
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
sr_awvalid : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 41 downto 0 );
\m_axi_arregion[3]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 1 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_block_reg : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
cmd_push_block_reg_0 : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
\USE_RTL_VALID_WRITE.buffer_Full_q_reg_0\ : in STD_LOGIC;
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 );
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[37]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[50]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\;
architecture STRUCTURE of \system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_ready_i_reg\ : STD_LOGIC;
begin
p_0_in(0) <= \^p_0_in\(0);
s_ready_i_reg <= \^s_ready_i_reg\;
ar_pipe: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice
port map (
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(32 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(32 downto 0),
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ => \USE_RTL_VALID_WRITE.buffer_Full_q_reg_0\,
\aresetn_d_reg[0]\ => \^p_0_in\(0),
cmd_push_block_reg => cmd_push_block_reg,
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arready => m_axi_arready,
\m_axi_arregion[3]\(43 downto 0) => \m_axi_arregion[3]\(43 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\m_payload_i_reg[37]_0\(0) => \m_payload_i_reg[37]\(0),
\m_payload_i_reg[50]_0\(0) => \m_payload_i_reg[50]_0\(0),
\out\ => \out\,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 0) => \s_axi_arregion[3]\(60 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => \^s_ready_i_reg\,
sr_arvalid => sr_arvalid
);
aw_pipe: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0
port map (
CO(0) => CO(0),
D(60 downto 0) => D(60 downto 0),
DI(1 downto 0) => DI(1 downto 0),
Q(41 downto 0) => Q(41 downto 0),
S(3 downto 0) => S(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(3 downto 0),
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ => \USE_RTL_VALID_WRITE.buffer_Full_q_reg\,
\aresetn_d_reg[1]\ => \^s_ready_i_reg\,
cmd_push_block_reg => cmd_push_block_reg_0,
\in\(32 downto 0) => \in\(32 downto 0),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
\m_payload_i_reg[50]_0\(0) => \m_payload_i_reg[50]\(0),
\out\ => \out\,
p_0_in(0) => \^p_0_in\(0),
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
sr_awvalid => sr_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer is
port (
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rlast : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 41 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arregion[3]\ : out STD_LOGIC_VECTOR ( 43 downto 0 );
m_axi_wvalid : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_awvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_arvalid : in STD_LOGIC;
\s_axi_arregion[3]\ : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer : entity is "axi_dwidth_converter_v2_1_11_axi_upsizer";
end system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer is
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_100\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_101\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_102\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_103\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_104\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_105\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_106\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_107\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_108\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_109\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_110\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_111\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_112\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_113\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_114\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_115\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_116\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_117\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_118\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_119\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_120\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_121\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_122\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_123\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_124\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_125\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_126\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_127\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_128\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_129\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_130\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_131\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_132\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_133\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_134\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_135\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_136\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_137\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_138\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_139\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_140\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_141\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_142\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_143\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_144\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_145\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_146\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_19\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_20\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_21\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_22\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_23\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_24\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_25\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_26\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_27\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_28\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_29\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_30\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_31\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_32\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_33\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_34\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_35\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_36\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_37\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_40\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_41\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_42\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_44\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_46\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_49\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_53\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_54\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_55\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_56\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_57\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_58\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_59\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_60\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_61\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_62\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_63\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_64\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_65\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_66\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_67\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_68\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_69\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_7\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_70\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_71\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_72\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_73\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_74\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_75\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_76\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_77\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_78\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_79\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_80\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_81\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_82\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_83\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_84\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_85\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_86\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_87\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_88\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_89\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_90\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_91\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_92\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_93\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_94\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_95\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_96\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_97\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_98\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_99\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_60\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_62\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_63\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_64\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_7\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_39\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_41\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_42\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_43\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_44\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_45\ : STD_LOGIC;
signal \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_46\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_100\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_102\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_104\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_106\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_108\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_109\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_110\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_111\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_32\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_41\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_43\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_44\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_46\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_48\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_50\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_52\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_54\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_56\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_58\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_60\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_62\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_64\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_66\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_68\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_70\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_72\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_74\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_76\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_77\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_78\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_79\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_81\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_83\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_85\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_87\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_89\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_91\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_92\ : STD_LOGIC;
signal \USE_WRITE.write_addr_inst_n_98\ : STD_LOGIC;
signal cmd_complete_wrap_i : STD_LOGIC;
signal cmd_complete_wrap_i_10 : STD_LOGIC;
signal cmd_first_word_i : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_first_word_i_8 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_fix_i : STD_LOGIC;
signal cmd_fix_i_12 : STD_LOGIC;
signal cmd_modified_i : STD_LOGIC;
signal cmd_modified_i_11 : STD_LOGIC;
signal cmd_packed_wrap_i : STD_LOGIC;
signal cmd_packed_wrap_i1 : STD_LOGIC;
signal cmd_packed_wrap_i1_5 : STD_LOGIC;
signal cmd_packed_wrap_i_9 : STD_LOGIC;
signal current_word_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \current_word_idx_1__0\ : STD_LOGIC;
signal current_word_q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal first_mi_word_q : STD_LOGIC;
signal first_mi_word_q_1 : STD_LOGIC;
signal first_word : STD_LOGIC;
signal first_word_q : STD_LOGIC;
signal \last_beat__6\ : STD_LOGIC;
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_rready\ : STD_LOGIC;
signal \^m_axi_wvalid\ : STD_LOGIC;
signal mr_rdata : STD_LOGIC_VECTOR ( 127 downto 0 );
signal mr_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mr_rvalid : STD_LOGIC;
signal next_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal next_word_3 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal p_0_out : STD_LOGIC;
signal p_102_out : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal \p_122_out__2\ : STD_LOGIC;
signal p_131_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal \p_151_out__2\ : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_160_out : STD_LOGIC;
signal p_17_out18_out : STD_LOGIC;
signal \p_180_out__2\ : STD_LOGIC;
signal p_189_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 26 downto 17 );
signal p_1_out_7 : STD_LOGIC_VECTOR ( 26 downto 17 );
signal \p_209_out__2\ : STD_LOGIC;
signal p_220_out : STD_LOGIC;
signal p_22_out : STD_LOGIC;
signal \p_240_out__2\ : STD_LOGIC;
signal p_249_out : STD_LOGIC;
signal p_25_out26_out : STD_LOGIC;
signal \p_269_out__2\ : STD_LOGIC;
signal p_278_out : STD_LOGIC;
signal \p_298_out__2\ : STD_LOGIC;
signal p_307_out : STD_LOGIC;
signal p_30_out : STD_LOGIC;
signal \p_327_out__2\ : STD_LOGIC;
signal p_338_out : STD_LOGIC;
signal p_33_out : STD_LOGIC;
signal \p_358_out__2\ : STD_LOGIC;
signal p_367_out : STD_LOGIC;
signal p_37_out : STD_LOGIC;
signal \p_387_out__2\ : STD_LOGIC;
signal p_396_out : STD_LOGIC;
signal p_3_out4_out : STD_LOGIC;
signal \p_416_out__2\ : STD_LOGIC;
signal p_41_out : STD_LOGIC;
signal p_425_out : STD_LOGIC;
signal \p_445_out__2\ : STD_LOGIC;
signal p_44_out : STD_LOGIC;
signal p_458_out : STD_LOGIC;
signal p_476_in : STD_LOGIC;
signal p_47_out : STD_LOGIC;
signal \p_481_out__2\ : STD_LOGIC;
signal p_487_in : STD_LOGIC;
signal p_51_out52_out : STD_LOGIC;
signal p_55_out56_out : STD_LOGIC;
signal \p_61_out__2\ : STD_LOGIC;
signal p_71_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal \p_91_out__2\ : STD_LOGIC;
signal pop_si_data : STD_LOGIC;
signal pre_next_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pre_next_word_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pre_next_word_4 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pre_next_word_q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal rd_cmd_fix : STD_LOGIC;
signal rd_cmd_length : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_cmd_packed_wrap : STD_LOGIC;
signal rd_cmd_valid : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC;
signal \sel_first_word__0\ : STD_LOGIC;
signal \sel_first_word__0_0\ : STD_LOGIC;
signal si_register_slice_inst_n_1 : STD_LOGIC;
signal si_register_slice_inst_n_140 : STD_LOGIC;
signal si_register_slice_inst_n_141 : STD_LOGIC;
signal si_register_slice_inst_n_142 : STD_LOGIC;
signal si_register_slice_inst_n_143 : STD_LOGIC;
signal si_register_slice_inst_n_144 : STD_LOGIC;
signal si_register_slice_inst_n_145 : STD_LOGIC;
signal si_register_slice_inst_n_146 : STD_LOGIC;
signal si_register_slice_inst_n_147 : STD_LOGIC;
signal si_register_slice_inst_n_148 : STD_LOGIC;
signal si_register_slice_inst_n_149 : STD_LOGIC;
signal si_register_slice_inst_n_150 : STD_LOGIC;
signal si_register_slice_inst_n_151 : STD_LOGIC;
signal si_register_slice_inst_n_152 : STD_LOGIC;
signal si_register_slice_inst_n_153 : STD_LOGIC;
signal si_register_slice_inst_n_175 : STD_LOGIC;
signal si_register_slice_inst_n_176 : STD_LOGIC;
signal si_register_slice_inst_n_177 : STD_LOGIC;
signal si_register_slice_inst_n_178 : STD_LOGIC;
signal si_register_slice_inst_n_179 : STD_LOGIC;
signal si_register_slice_inst_n_180 : STD_LOGIC;
signal si_register_slice_inst_n_181 : STD_LOGIC;
signal si_register_slice_inst_n_192 : STD_LOGIC;
signal si_register_slice_inst_n_193 : STD_LOGIC;
signal si_register_slice_inst_n_194 : STD_LOGIC;
signal si_register_slice_inst_n_195 : STD_LOGIC;
signal si_register_slice_inst_n_200 : STD_LOGIC;
signal si_register_slice_inst_n_201 : STD_LOGIC;
signal si_register_slice_inst_n_202 : STD_LOGIC;
signal si_register_slice_inst_n_203 : STD_LOGIC;
signal si_register_slice_inst_n_204 : STD_LOGIC;
signal si_register_slice_inst_n_205 : STD_LOGIC;
signal si_register_slice_inst_n_26 : STD_LOGIC;
signal si_register_slice_inst_n_27 : STD_LOGIC;
signal si_register_slice_inst_n_28 : STD_LOGIC;
signal si_register_slice_inst_n_29 : STD_LOGIC;
signal si_register_slice_inst_n_30 : STD_LOGIC;
signal si_register_slice_inst_n_31 : STD_LOGIC;
signal si_register_slice_inst_n_32 : STD_LOGIC;
signal si_register_slice_inst_n_4 : STD_LOGIC;
signal si_register_slice_inst_n_5 : STD_LOGIC;
signal si_register_slice_inst_n_6 : STD_LOGIC;
signal si_register_slice_inst_n_7 : STD_LOGIC;
signal sr_arvalid : STD_LOGIC;
signal sr_awvalid : STD_LOGIC;
signal sub_sized_wrap0 : STD_LOGIC;
signal sub_sized_wrap0_6 : STD_LOGIC;
signal use_wrap_buffer : STD_LOGIC;
signal wdata_wrap_buffer_q : STD_LOGIC;
signal wr_cmd_fix : STD_LOGIC;
signal wr_cmd_length : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wr_cmd_packed_wrap : STD_LOGIC;
signal wr_cmd_valid : STD_LOGIC;
signal wrap_buffer_available : STD_LOGIC;
signal wrap_buffer_available_2 : STD_LOGIC;
signal wstrb_wrap_buffer_1 : STD_LOGIC;
signal wstrb_wrap_buffer_10 : STD_LOGIC;
signal wstrb_wrap_buffer_11 : STD_LOGIC;
signal wstrb_wrap_buffer_12 : STD_LOGIC;
signal wstrb_wrap_buffer_13 : STD_LOGIC;
signal wstrb_wrap_buffer_14 : STD_LOGIC;
signal wstrb_wrap_buffer_15 : STD_LOGIC;
signal wstrb_wrap_buffer_2 : STD_LOGIC;
signal wstrb_wrap_buffer_3 : STD_LOGIC;
signal wstrb_wrap_buffer_4 : STD_LOGIC;
signal wstrb_wrap_buffer_5 : STD_LOGIC;
signal wstrb_wrap_buffer_6 : STD_LOGIC;
signal wstrb_wrap_buffer_7 : STD_LOGIC;
signal wstrb_wrap_buffer_8 : STD_LOGIC;
signal wstrb_wrap_buffer_9 : STD_LOGIC;
begin
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(7 downto 0);
m_axi_rready <= \^m_axi_rready\;
m_axi_wvalid <= \^m_axi_wvalid\;
s_axi_rlast <= \^s_axi_rlast\;
\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst\: entity work.system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice
port map (
E(0) => \r_pipe/p_1_in\,
Q(129 downto 128) => mr_rresp(1 downto 0),
Q(127 downto 0) => mr_rdata(127 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\,
\USE_RTL_LENGTH.length_counter_q_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
first_mi_word_q => first_mi_word_q,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => \^m_axi_rready\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
p_0_in(0) => p_0_in(1),
p_13_in => p_13_in,
rd_cmd_valid => rd_cmd_valid,
s_axi_rready => s_axi_rready,
s_ready_i_reg => \USE_READ.read_addr_inst_n_64\
);
\USE_READ.gen_non_fifo_r_upsizer.read_data_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer
port map (
D(3 downto 0) => pre_next_word(3 downto 0),
E(0) => p_15_in,
Q(9) => rd_cmd_fix,
Q(8) => rd_cmd_packed_wrap,
Q(7 downto 0) => rd_cmd_length(7 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_READ.read_addr_inst_n_7\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ => \USE_READ.read_addr_inst_n_3\,
\USE_RTL_LENGTH.length_counter_q_reg[0]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\current_word_1_reg[3]_0\(3 downto 0) => pre_next_word_1(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\,
first_word_reg_1 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_7\,
first_word_reg_2(3 downto 0) => current_word_1(3 downto 0),
\last_beat__6\ => \last_beat__6\,
\m_payload_i_reg[129]\(129 downto 128) => mr_rresp(1 downto 0),
\m_payload_i_reg[129]\(127 downto 0) => mr_rdata(127 downto 0),
\m_payload_i_reg[130]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_3\,
m_valid_i_reg => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
p_13_in => p_13_in,
\pre_next_word_1_reg[3]_0\(3 downto 0) => next_word(3 downto 0),
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\(127) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_19\,
\s_axi_rdata[31]\(126) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_20\,
\s_axi_rdata[31]\(125) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_21\,
\s_axi_rdata[31]\(124) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_22\,
\s_axi_rdata[31]\(123) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_23\,
\s_axi_rdata[31]\(122) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_24\,
\s_axi_rdata[31]\(121) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_25\,
\s_axi_rdata[31]\(120) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_26\,
\s_axi_rdata[31]\(119) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_27\,
\s_axi_rdata[31]\(118) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_28\,
\s_axi_rdata[31]\(117) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_29\,
\s_axi_rdata[31]\(116) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_30\,
\s_axi_rdata[31]\(115) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_31\,
\s_axi_rdata[31]\(114) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_32\,
\s_axi_rdata[31]\(113) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_33\,
\s_axi_rdata[31]\(112) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_34\,
\s_axi_rdata[31]\(111) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_35\,
\s_axi_rdata[31]\(110) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_36\,
\s_axi_rdata[31]\(109) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_37\,
\s_axi_rdata[31]\(108) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\,
\s_axi_rdata[31]\(107) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\,
\s_axi_rdata[31]\(106) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_40\,
\s_axi_rdata[31]\(105) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_41\,
\s_axi_rdata[31]\(104) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_42\,
\s_axi_rdata[31]\(103) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\,
\s_axi_rdata[31]\(102) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_44\,
\s_axi_rdata[31]\(101) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\,
\s_axi_rdata[31]\(100) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_46\,
\s_axi_rdata[31]\(99) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\,
\s_axi_rdata[31]\(98) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\,
\s_axi_rdata[31]\(97) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_49\,
\s_axi_rdata[31]\(96) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\,
\s_axi_rdata[31]\(95) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\,
\s_axi_rdata[31]\(94) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\,
\s_axi_rdata[31]\(93) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_53\,
\s_axi_rdata[31]\(92) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_54\,
\s_axi_rdata[31]\(91) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_55\,
\s_axi_rdata[31]\(90) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_56\,
\s_axi_rdata[31]\(89) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_57\,
\s_axi_rdata[31]\(88) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_58\,
\s_axi_rdata[31]\(87) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_59\,
\s_axi_rdata[31]\(86) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_60\,
\s_axi_rdata[31]\(85) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_61\,
\s_axi_rdata[31]\(84) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_62\,
\s_axi_rdata[31]\(83) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_63\,
\s_axi_rdata[31]\(82) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_64\,
\s_axi_rdata[31]\(81) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_65\,
\s_axi_rdata[31]\(80) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_66\,
\s_axi_rdata[31]\(79) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_67\,
\s_axi_rdata[31]\(78) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_68\,
\s_axi_rdata[31]\(77) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_69\,
\s_axi_rdata[31]\(76) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_70\,
\s_axi_rdata[31]\(75) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_71\,
\s_axi_rdata[31]\(74) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_72\,
\s_axi_rdata[31]\(73) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_73\,
\s_axi_rdata[31]\(72) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_74\,
\s_axi_rdata[31]\(71) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_75\,
\s_axi_rdata[31]\(70) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_76\,
\s_axi_rdata[31]\(69) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_77\,
\s_axi_rdata[31]\(68) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_78\,
\s_axi_rdata[31]\(67) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_79\,
\s_axi_rdata[31]\(66) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_80\,
\s_axi_rdata[31]\(65) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_81\,
\s_axi_rdata[31]\(64) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_82\,
\s_axi_rdata[31]\(63) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_83\,
\s_axi_rdata[31]\(62) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_84\,
\s_axi_rdata[31]\(61) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_85\,
\s_axi_rdata[31]\(60) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_86\,
\s_axi_rdata[31]\(59) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_87\,
\s_axi_rdata[31]\(58) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_88\,
\s_axi_rdata[31]\(57) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_89\,
\s_axi_rdata[31]\(56) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_90\,
\s_axi_rdata[31]\(55) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_91\,
\s_axi_rdata[31]\(54) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_92\,
\s_axi_rdata[31]\(53) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_93\,
\s_axi_rdata[31]\(52) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_94\,
\s_axi_rdata[31]\(51) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_95\,
\s_axi_rdata[31]\(50) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_96\,
\s_axi_rdata[31]\(49) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_97\,
\s_axi_rdata[31]\(48) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_98\,
\s_axi_rdata[31]\(47) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_99\,
\s_axi_rdata[31]\(46) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_100\,
\s_axi_rdata[31]\(45) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_101\,
\s_axi_rdata[31]\(44) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_102\,
\s_axi_rdata[31]\(43) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_103\,
\s_axi_rdata[31]\(42) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_104\,
\s_axi_rdata[31]\(41) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_105\,
\s_axi_rdata[31]\(40) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_106\,
\s_axi_rdata[31]\(39) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_107\,
\s_axi_rdata[31]\(38) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_108\,
\s_axi_rdata[31]\(37) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_109\,
\s_axi_rdata[31]\(36) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_110\,
\s_axi_rdata[31]\(35) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_111\,
\s_axi_rdata[31]\(34) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_112\,
\s_axi_rdata[31]\(33) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_113\,
\s_axi_rdata[31]\(32) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_114\,
\s_axi_rdata[31]\(31) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_115\,
\s_axi_rdata[31]\(30) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_116\,
\s_axi_rdata[31]\(29) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_117\,
\s_axi_rdata[31]\(28) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_118\,
\s_axi_rdata[31]\(27) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_119\,
\s_axi_rdata[31]\(26) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_120\,
\s_axi_rdata[31]\(25) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_121\,
\s_axi_rdata[31]\(24) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_122\,
\s_axi_rdata[31]\(23) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_123\,
\s_axi_rdata[31]\(22) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_124\,
\s_axi_rdata[31]\(21) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_125\,
\s_axi_rdata[31]\(20) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_126\,
\s_axi_rdata[31]\(19) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_127\,
\s_axi_rdata[31]\(18) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_128\,
\s_axi_rdata[31]\(17) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_129\,
\s_axi_rdata[31]\(16) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_130\,
\s_axi_rdata[31]\(15) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_131\,
\s_axi_rdata[31]\(14) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_132\,
\s_axi_rdata[31]\(13) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_133\,
\s_axi_rdata[31]\(12) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_134\,
\s_axi_rdata[31]\(11) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_135\,
\s_axi_rdata[31]\(10) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_136\,
\s_axi_rdata[31]\(9) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_137\,
\s_axi_rdata[31]\(8) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_138\,
\s_axi_rdata[31]\(7) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_139\,
\s_axi_rdata[31]\(6) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_140\,
\s_axi_rdata[31]\(5) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_141\,
\s_axi_rdata[31]\(4) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_142\,
\s_axi_rdata[31]\(3) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_143\,
\s_axi_rdata[31]\(2) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_144\,
\s_axi_rdata[31]\(1) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_145\,
\s_axi_rdata[31]\(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_146\,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\sel_first_word__0\ => \sel_first_word__0\,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg_0 => \^s_axi_rlast\,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg_0 => \USE_READ.read_addr_inst_n_63\
);
\USE_READ.read_addr_inst\: entity work.\system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0\
port map (
CO(0) => sub_sized_wrap0,
D(3 downto 0) => pre_next_word(3 downto 0),
DI(1) => si_register_slice_inst_n_200,
DI(0) => si_register_slice_inst_n_201,
E(0) => p_15_in,
\M_AXI_RDATA_I_reg[127]\(127) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_19\,
\M_AXI_RDATA_I_reg[127]\(126) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_20\,
\M_AXI_RDATA_I_reg[127]\(125) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_21\,
\M_AXI_RDATA_I_reg[127]\(124) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_22\,
\M_AXI_RDATA_I_reg[127]\(123) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_23\,
\M_AXI_RDATA_I_reg[127]\(122) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_24\,
\M_AXI_RDATA_I_reg[127]\(121) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_25\,
\M_AXI_RDATA_I_reg[127]\(120) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_26\,
\M_AXI_RDATA_I_reg[127]\(119) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_27\,
\M_AXI_RDATA_I_reg[127]\(118) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_28\,
\M_AXI_RDATA_I_reg[127]\(117) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_29\,
\M_AXI_RDATA_I_reg[127]\(116) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_30\,
\M_AXI_RDATA_I_reg[127]\(115) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_31\,
\M_AXI_RDATA_I_reg[127]\(114) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_32\,
\M_AXI_RDATA_I_reg[127]\(113) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_33\,
\M_AXI_RDATA_I_reg[127]\(112) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_34\,
\M_AXI_RDATA_I_reg[127]\(111) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_35\,
\M_AXI_RDATA_I_reg[127]\(110) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_36\,
\M_AXI_RDATA_I_reg[127]\(109) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_37\,
\M_AXI_RDATA_I_reg[127]\(108) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38\,
\M_AXI_RDATA_I_reg[127]\(107) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39\,
\M_AXI_RDATA_I_reg[127]\(106) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_40\,
\M_AXI_RDATA_I_reg[127]\(105) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_41\,
\M_AXI_RDATA_I_reg[127]\(104) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_42\,
\M_AXI_RDATA_I_reg[127]\(103) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43\,
\M_AXI_RDATA_I_reg[127]\(102) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_44\,
\M_AXI_RDATA_I_reg[127]\(101) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\,
\M_AXI_RDATA_I_reg[127]\(100) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_46\,
\M_AXI_RDATA_I_reg[127]\(99) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47\,
\M_AXI_RDATA_I_reg[127]\(98) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48\,
\M_AXI_RDATA_I_reg[127]\(97) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_49\,
\M_AXI_RDATA_I_reg[127]\(96) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\,
\M_AXI_RDATA_I_reg[127]\(95) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\,
\M_AXI_RDATA_I_reg[127]\(94) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\,
\M_AXI_RDATA_I_reg[127]\(93) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_53\,
\M_AXI_RDATA_I_reg[127]\(92) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_54\,
\M_AXI_RDATA_I_reg[127]\(91) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_55\,
\M_AXI_RDATA_I_reg[127]\(90) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_56\,
\M_AXI_RDATA_I_reg[127]\(89) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_57\,
\M_AXI_RDATA_I_reg[127]\(88) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_58\,
\M_AXI_RDATA_I_reg[127]\(87) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_59\,
\M_AXI_RDATA_I_reg[127]\(86) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_60\,
\M_AXI_RDATA_I_reg[127]\(85) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_61\,
\M_AXI_RDATA_I_reg[127]\(84) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_62\,
\M_AXI_RDATA_I_reg[127]\(83) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_63\,
\M_AXI_RDATA_I_reg[127]\(82) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_64\,
\M_AXI_RDATA_I_reg[127]\(81) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_65\,
\M_AXI_RDATA_I_reg[127]\(80) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_66\,
\M_AXI_RDATA_I_reg[127]\(79) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_67\,
\M_AXI_RDATA_I_reg[127]\(78) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_68\,
\M_AXI_RDATA_I_reg[127]\(77) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_69\,
\M_AXI_RDATA_I_reg[127]\(76) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_70\,
\M_AXI_RDATA_I_reg[127]\(75) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_71\,
\M_AXI_RDATA_I_reg[127]\(74) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_72\,
\M_AXI_RDATA_I_reg[127]\(73) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_73\,
\M_AXI_RDATA_I_reg[127]\(72) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_74\,
\M_AXI_RDATA_I_reg[127]\(71) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_75\,
\M_AXI_RDATA_I_reg[127]\(70) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_76\,
\M_AXI_RDATA_I_reg[127]\(69) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_77\,
\M_AXI_RDATA_I_reg[127]\(68) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_78\,
\M_AXI_RDATA_I_reg[127]\(67) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_79\,
\M_AXI_RDATA_I_reg[127]\(66) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_80\,
\M_AXI_RDATA_I_reg[127]\(65) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_81\,
\M_AXI_RDATA_I_reg[127]\(64) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_82\,
\M_AXI_RDATA_I_reg[127]\(63) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_83\,
\M_AXI_RDATA_I_reg[127]\(62) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_84\,
\M_AXI_RDATA_I_reg[127]\(61) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_85\,
\M_AXI_RDATA_I_reg[127]\(60) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_86\,
\M_AXI_RDATA_I_reg[127]\(59) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_87\,
\M_AXI_RDATA_I_reg[127]\(58) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_88\,
\M_AXI_RDATA_I_reg[127]\(57) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_89\,
\M_AXI_RDATA_I_reg[127]\(56) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_90\,
\M_AXI_RDATA_I_reg[127]\(55) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_91\,
\M_AXI_RDATA_I_reg[127]\(54) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_92\,
\M_AXI_RDATA_I_reg[127]\(53) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_93\,
\M_AXI_RDATA_I_reg[127]\(52) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_94\,
\M_AXI_RDATA_I_reg[127]\(51) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_95\,
\M_AXI_RDATA_I_reg[127]\(50) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_96\,
\M_AXI_RDATA_I_reg[127]\(49) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_97\,
\M_AXI_RDATA_I_reg[127]\(48) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_98\,
\M_AXI_RDATA_I_reg[127]\(47) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_99\,
\M_AXI_RDATA_I_reg[127]\(46) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_100\,
\M_AXI_RDATA_I_reg[127]\(45) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_101\,
\M_AXI_RDATA_I_reg[127]\(44) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_102\,
\M_AXI_RDATA_I_reg[127]\(43) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_103\,
\M_AXI_RDATA_I_reg[127]\(42) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_104\,
\M_AXI_RDATA_I_reg[127]\(41) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_105\,
\M_AXI_RDATA_I_reg[127]\(40) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_106\,
\M_AXI_RDATA_I_reg[127]\(39) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_107\,
\M_AXI_RDATA_I_reg[127]\(38) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_108\,
\M_AXI_RDATA_I_reg[127]\(37) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_109\,
\M_AXI_RDATA_I_reg[127]\(36) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_110\,
\M_AXI_RDATA_I_reg[127]\(35) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_111\,
\M_AXI_RDATA_I_reg[127]\(34) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_112\,
\M_AXI_RDATA_I_reg[127]\(33) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_113\,
\M_AXI_RDATA_I_reg[127]\(32) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_114\,
\M_AXI_RDATA_I_reg[127]\(31) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_115\,
\M_AXI_RDATA_I_reg[127]\(30) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_116\,
\M_AXI_RDATA_I_reg[127]\(29) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_117\,
\M_AXI_RDATA_I_reg[127]\(28) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_118\,
\M_AXI_RDATA_I_reg[127]\(27) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_119\,
\M_AXI_RDATA_I_reg[127]\(26) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_120\,
\M_AXI_RDATA_I_reg[127]\(25) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_121\,
\M_AXI_RDATA_I_reg[127]\(24) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_122\,
\M_AXI_RDATA_I_reg[127]\(23) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_123\,
\M_AXI_RDATA_I_reg[127]\(22) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_124\,
\M_AXI_RDATA_I_reg[127]\(21) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_125\,
\M_AXI_RDATA_I_reg[127]\(20) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_126\,
\M_AXI_RDATA_I_reg[127]\(19) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_127\,
\M_AXI_RDATA_I_reg[127]\(18) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_128\,
\M_AXI_RDATA_I_reg[127]\(17) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_129\,
\M_AXI_RDATA_I_reg[127]\(16) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_130\,
\M_AXI_RDATA_I_reg[127]\(15) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_131\,
\M_AXI_RDATA_I_reg[127]\(14) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_132\,
\M_AXI_RDATA_I_reg[127]\(13) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_133\,
\M_AXI_RDATA_I_reg[127]\(12) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_134\,
\M_AXI_RDATA_I_reg[127]\(11) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_135\,
\M_AXI_RDATA_I_reg[127]\(10) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_136\,
\M_AXI_RDATA_I_reg[127]\(9) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_137\,
\M_AXI_RDATA_I_reg[127]\(8) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_138\,
\M_AXI_RDATA_I_reg[127]\(7) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_139\,
\M_AXI_RDATA_I_reg[127]\(6) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_140\,
\M_AXI_RDATA_I_reg[127]\(5) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_141\,
\M_AXI_RDATA_I_reg[127]\(4) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_142\,
\M_AXI_RDATA_I_reg[127]\(3) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_143\,
\M_AXI_RDATA_I_reg[127]\(2) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_144\,
\M_AXI_RDATA_I_reg[127]\(1) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_145\,
\M_AXI_RDATA_I_reg[127]\(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_146\,
Q(9) => rd_cmd_fix,
Q(8) => rd_cmd_packed_wrap,
Q(7 downto 0) => rd_cmd_length(7 downto 0),
S(3) => si_register_slice_inst_n_202,
S(2) => si_register_slice_inst_n_203,
S(1) => si_register_slice_inst_n_204,
S(0) => si_register_slice_inst_n_205,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0) => cmd_packed_wrap_i1,
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\,
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_7\,
\USE_RTL_LENGTH.length_counter_q_reg[4]\ => \USE_READ.read_addr_inst_n_7\,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_1,
\current_word_1_reg[3]\(3 downto 0) => next_word(3 downto 0),
\current_word_1_reg[3]_0\(3 downto 0) => current_word_1(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
\in\(32) => cmd_fix_i,
\in\(31) => cmd_modified_i,
\in\(30) => cmd_complete_wrap_i,
\in\(29) => cmd_packed_wrap_i,
\in\(28 downto 25) => cmd_first_word_i(3 downto 0),
\in\(24 downto 15) => p_1_out(26 downto 17),
\in\(14) => si_register_slice_inst_n_175,
\in\(13) => si_register_slice_inst_n_176,
\in\(12) => si_register_slice_inst_n_177,
\in\(11) => si_register_slice_inst_n_178,
\in\(10) => si_register_slice_inst_n_179,
\in\(9) => si_register_slice_inst_n_180,
\in\(8) => si_register_slice_inst_n_181,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
\last_beat__6\ => \last_beat__6\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_rvalid => m_axi_rvalid,
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[127]\(127 downto 0) => mr_rdata(127 downto 0),
\m_payload_i_reg[50]\(3) => si_register_slice_inst_n_4,
\m_payload_i_reg[50]\(2) => si_register_slice_inst_n_5,
\m_payload_i_reg[50]\(1) => si_register_slice_inst_n_6,
\m_payload_i_reg[50]\(0) => si_register_slice_inst_n_7,
\m_payload_i_reg[51]\(3) => si_register_slice_inst_n_192,
\m_payload_i_reg[51]\(2) => si_register_slice_inst_n_193,
\m_payload_i_reg[51]\(1) => si_register_slice_inst_n_194,
\m_payload_i_reg[51]\(0) => si_register_slice_inst_n_195,
m_valid_i_reg => \USE_READ.read_addr_inst_n_62\,
m_valid_i_reg_0 => \USE_READ.read_addr_inst_n_64\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
p_13_in => p_13_in,
\pre_next_word_1_reg[3]\(3 downto 0) => pre_next_word_1(3 downto 0),
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
s_axi_aresetn_0 => s_axi_aresetn,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => \^s_axi_rlast\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => \USE_READ.read_addr_inst_n_60\,
s_ready_i_reg_0 => \^m_axi_rready\,
\sel_first_word__0\ => \sel_first_word__0\,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => \USE_READ.read_addr_inst_n_3\,
use_wrap_buffer_reg_0 => \USE_READ.read_addr_inst_n_63\,
wrap_buffer_available => wrap_buffer_available
);
\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer
port map (
D(3 downto 0) => pre_next_word_4(3 downto 0),
E(0) => pop_si_data,
Q(9) => wr_cmd_fix,
Q(8) => wr_cmd_packed_wrap,
Q(7 downto 0) => wr_cmd_length(7 downto 0),
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(3 downto 0) => next_word_3(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_WRITE.write_addr_inst_n_77\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0\ => \USE_WRITE.write_addr_inst_n_79\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1\ => \USE_WRITE.write_addr_inst_n_81\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_2\ => \USE_WRITE.write_addr_inst_n_83\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_3\ => \USE_WRITE.write_addr_inst_n_92\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_4\ => \USE_WRITE.write_addr_inst_n_98\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_5\ => \USE_WRITE.write_addr_inst_n_100\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_6\ => \USE_WRITE.write_addr_inst_n_102\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_7\ => \USE_WRITE.write_addr_inst_n_104\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ => \USE_WRITE.write_addr_inst_n_85\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_0\ => \USE_WRITE.write_addr_inst_n_87\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_1\ => \USE_WRITE.write_addr_inst_n_89\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]_2\ => \USE_WRITE.write_addr_inst_n_91\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0) => p_458_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0) => p_425_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0) => p_396_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_10\(0) => \USE_WRITE.write_addr_inst_n_76\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0) => p_367_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_3\(0) => p_220_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_4\(0) => p_189_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_5\(0) => p_160_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_6\(0) => p_131_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_7\(0) => p_102_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_8\(0) => p_71_out,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_9\(0) => \USE_WRITE.write_addr_inst_n_78\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\ => \USE_WRITE.write_addr_inst_n_109\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0\ => \USE_WRITE.write_addr_inst_n_110\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1\ => \USE_WRITE.write_addr_inst_n_44\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2\(0) => wdata_wrap_buffer_q,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_42\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_43\,
\USE_REGISTER.M_AXI_WVALID_q_reg_10\(0) => \USE_WRITE.write_addr_inst_n_58\,
\USE_REGISTER.M_AXI_WVALID_q_reg_11\(0) => \USE_WRITE.write_addr_inst_n_56\,
\USE_REGISTER.M_AXI_WVALID_q_reg_12\(0) => \USE_WRITE.write_addr_inst_n_54\,
\USE_REGISTER.M_AXI_WVALID_q_reg_13\(0) => \USE_WRITE.write_addr_inst_n_52\,
\USE_REGISTER.M_AXI_WVALID_q_reg_14\(0) => \USE_WRITE.write_addr_inst_n_50\,
\USE_REGISTER.M_AXI_WVALID_q_reg_15\(0) => \USE_WRITE.write_addr_inst_n_48\,
\USE_REGISTER.M_AXI_WVALID_q_reg_16\(0) => \USE_WRITE.write_addr_inst_n_46\,
\USE_REGISTER.M_AXI_WVALID_q_reg_17\(0) => \USE_WRITE.write_addr_inst_n_43\,
\USE_REGISTER.M_AXI_WVALID_q_reg_2\(0) => \USE_WRITE.write_addr_inst_n_74\,
\USE_REGISTER.M_AXI_WVALID_q_reg_3\(0) => \USE_WRITE.write_addr_inst_n_72\,
\USE_REGISTER.M_AXI_WVALID_q_reg_4\(0) => \USE_WRITE.write_addr_inst_n_70\,
\USE_REGISTER.M_AXI_WVALID_q_reg_5\(0) => \USE_WRITE.write_addr_inst_n_68\,
\USE_REGISTER.M_AXI_WVALID_q_reg_6\(0) => \USE_WRITE.write_addr_inst_n_66\,
\USE_REGISTER.M_AXI_WVALID_q_reg_7\(0) => \USE_WRITE.write_addr_inst_n_64\,
\USE_REGISTER.M_AXI_WVALID_q_reg_8\(0) => \USE_WRITE.write_addr_inst_n_62\,
\USE_REGISTER.M_AXI_WVALID_q_reg_9\(0) => \USE_WRITE.write_addr_inst_n_60\,
\USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(3 downto 0) => pre_next_word_q(3 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg_0\ => \USE_WRITE.write_addr_inst_n_111\,
\USE_RTL_LENGTH.length_counter_q_reg[0]_0\ => \USE_WRITE.write_addr_inst_n_32\,
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\(1 downto 0) => \USE_RTL_LENGTH.length_counter_q_reg\(1 downto 0),
\USE_RTL_LENGTH.length_counter_q_reg[1]_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_46\,
\USE_RTL_LENGTH.length_counter_q_reg[2]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_39\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_41\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_44\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]_1\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_45\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]_0\(3 downto 0) => current_word_q(3 downto 0),
\current_word_idx_1__0\ => \current_word_idx_1__0\,
first_mi_word_q => first_mi_word_q_1,
first_word_q => first_word_q,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wvalid => \^m_axi_wvalid\,
\out\ => \out\,
p_0_out => p_0_out,
p_11_out => p_11_out,
\p_122_out__2\ => \p_122_out__2\,
p_14_out => p_14_out,
\p_151_out__2\ => \p_151_out__2\,
p_17_out18_out => p_17_out18_out,
\p_180_out__2\ => \p_180_out__2\,
\p_209_out__2\ => \p_209_out__2\,
p_22_out => p_22_out,
\p_240_out__2\ => \p_240_out__2\,
p_25_out26_out => p_25_out26_out,
\p_269_out__2\ => \p_269_out__2\,
\p_298_out__2\ => \p_298_out__2\,
p_30_out => p_30_out,
\p_327_out__2\ => \p_327_out__2\,
p_33_out => p_33_out,
\p_358_out__2\ => \p_358_out__2\,
p_37_out => p_37_out,
\p_387_out__2\ => \p_387_out__2\,
p_3_out4_out => p_3_out4_out,
\p_416_out__2\ => \p_416_out__2\,
p_41_out => p_41_out,
\p_445_out__2\ => \p_445_out__2\,
p_44_out => p_44_out,
p_476_in => p_476_in,
p_47_out => p_47_out,
\p_481_out__2\ => \p_481_out__2\,
p_487_in => p_487_in,
p_51_out52_out => p_51_out52_out,
p_55_out56_out => p_55_out56_out,
\p_61_out__2\ => \p_61_out__2\,
p_8_out => p_8_out,
\p_91_out__2\ => \p_91_out__2\,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
\sel_first_word__0\ => \sel_first_word__0_0\,
wr_cmd_valid => wr_cmd_valid,
wrap_buffer_available => wrap_buffer_available_2,
wrap_buffer_available_reg_0 => \USE_WRITE.write_addr_inst_n_41\,
wrap_buffer_available_reg_1(0) => p_338_out,
wrap_buffer_available_reg_2(0) => p_307_out,
wrap_buffer_available_reg_3(0) => p_278_out,
wrap_buffer_available_reg_4(0) => p_249_out,
wstrb_wrap_buffer_1 => wstrb_wrap_buffer_1,
wstrb_wrap_buffer_10 => wstrb_wrap_buffer_10,
wstrb_wrap_buffer_11 => wstrb_wrap_buffer_11,
wstrb_wrap_buffer_12 => wstrb_wrap_buffer_12,
wstrb_wrap_buffer_13 => wstrb_wrap_buffer_13,
wstrb_wrap_buffer_14 => wstrb_wrap_buffer_14,
wstrb_wrap_buffer_15 => wstrb_wrap_buffer_15,
wstrb_wrap_buffer_2 => wstrb_wrap_buffer_2,
wstrb_wrap_buffer_3 => wstrb_wrap_buffer_3,
wstrb_wrap_buffer_4 => wstrb_wrap_buffer_4,
wstrb_wrap_buffer_5 => wstrb_wrap_buffer_5,
wstrb_wrap_buffer_6 => wstrb_wrap_buffer_6,
wstrb_wrap_buffer_7 => wstrb_wrap_buffer_7,
wstrb_wrap_buffer_8 => wstrb_wrap_buffer_8,
wstrb_wrap_buffer_9 => wstrb_wrap_buffer_9
);
\USE_WRITE.write_addr_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer
port map (
CO(0) => sub_sized_wrap0_6,
D(3 downto 0) => pre_next_word_4(3 downto 0),
DI(1) => si_register_slice_inst_n_148,
DI(0) => si_register_slice_inst_n_149,
E(0) => pop_si_data,
Q(9) => wr_cmd_fix,
Q(8) => wr_cmd_packed_wrap,
Q(7 downto 0) => wr_cmd_length(7 downto 0),
S(3) => si_register_slice_inst_n_150,
S(2) => si_register_slice_inst_n_151,
S(1) => si_register_slice_inst_n_152,
S(0) => si_register_slice_inst_n_153,
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0) => cmd_packed_wrap_i1_5,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_41\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_44\,
\USE_REGISTER.M_AXI_WVALID_q_reg\ => \USE_WRITE.write_addr_inst_n_110\,
\USE_REGISTER.M_AXI_WVALID_q_reg_0\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_46\,
\USE_REGISTER.M_AXI_WVALID_q_reg_1\ => \^m_axi_wvalid\,
\USE_REGISTER.M_AXI_WVALID_q_reg_2\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_45\,
\USE_RTL_CURR_WORD.current_word_q_reg[3]\(3 downto 0) => next_word_3(3 downto 0),
\USE_RTL_CURR_WORD.current_word_q_reg[3]_0\(3 downto 0) => current_word_q(3 downto 0),
\USE_RTL_CURR_WORD.pre_next_word_q_reg[3]\(3 downto 0) => pre_next_word_q(3 downto 0),
\USE_RTL_LENGTH.first_mi_word_q_reg\ => \USE_WRITE.write_addr_inst_n_111\,
\USE_RTL_LENGTH.length_counter_q_reg[0]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_39\,
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => \USE_WRITE.write_addr_inst_n_32\,
\USE_RTL_LENGTH.length_counter_q_reg[1]_0\(1 downto 0) => \USE_RTL_LENGTH.length_counter_q_reg\(1 downto 0),
\USE_RTL_LENGTH.length_counter_q_reg[2]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_43\,
\USE_RTL_LENGTH.length_counter_q_reg[4]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_42\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]\(0) => \USE_WRITE.write_addr_inst_n_74\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]\ => \USE_WRITE.write_addr_inst_n_104\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]\(0) => wdata_wrap_buffer_q,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0\(0) => p_458_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]\ => \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]\(0) => \USE_WRITE.write_addr_inst_n_72\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]\ => \USE_WRITE.write_addr_inst_n_102\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]\(0) => p_425_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]\(0) => \USE_WRITE.write_addr_inst_n_70\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]\ => \USE_WRITE.write_addr_inst_n_100\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]\(0) => p_396_out,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]\(0) => \USE_WRITE.write_addr_inst_n_68\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]\ => \USE_WRITE.write_addr_inst_n_98\,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]\(0) => p_367_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]\(0) => \USE_WRITE.write_addr_inst_n_66\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]\(0) => p_338_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]\(0) => \USE_WRITE.write_addr_inst_n_64\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]\(0) => p_307_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]\(0) => \USE_WRITE.write_addr_inst_n_62\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]\(0) => p_278_out,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]\(0) => \USE_WRITE.write_addr_inst_n_60\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]\ => \USE_WRITE.write_addr_inst_n_92\,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]\(0) => p_249_out,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[71]\(0) => \USE_WRITE.write_addr_inst_n_58\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[8]\ => \USE_WRITE.write_addr_inst_n_91\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[71]\(0) => p_220_out,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[79]\(0) => \USE_WRITE.write_addr_inst_n_56\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[9]\ => \USE_WRITE.write_addr_inst_n_89\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[79]\(0) => p_189_out,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[87]\(0) => \USE_WRITE.write_addr_inst_n_54\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[10]\ => \USE_WRITE.write_addr_inst_n_87\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[87]\(0) => p_160_out,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[95]\(0) => \USE_WRITE.write_addr_inst_n_52\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[11]\ => \USE_WRITE.write_addr_inst_n_85\,
\WORD_LANE[2].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[95]\(0) => p_131_out,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[103]\(0) => \USE_WRITE.write_addr_inst_n_50\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[12]\ => \USE_WRITE.write_addr_inst_n_83\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[103]\(0) => p_102_out,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[111]\(0) => \USE_WRITE.write_addr_inst_n_48\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[13]\ => \USE_WRITE.write_addr_inst_n_81\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[111]\(0) => p_71_out,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[119]\(0) => \USE_WRITE.write_addr_inst_n_46\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[14]\ => \USE_WRITE.write_addr_inst_n_79\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[119]\(0) => \USE_WRITE.write_addr_inst_n_78\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]\(0) => \USE_WRITE.write_addr_inst_n_43\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[127]_0\ => \USE_WRITE.write_addr_inst_n_44\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]\ => \USE_WRITE.write_addr_inst_n_41\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[15]_0\ => \USE_WRITE.write_addr_inst_n_77\,
\WORD_LANE[3].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[127]\(0) => \USE_WRITE.write_addr_inst_n_76\,
\current_word_idx_1__0\ => \current_word_idx_1__0\,
first_mi_word_q => first_mi_word_q_1,
first_word_q => first_word_q,
\in\(32) => cmd_fix_i_12,
\in\(31) => cmd_modified_i_11,
\in\(30) => cmd_complete_wrap_i_10,
\in\(29) => cmd_packed_wrap_i_9,
\in\(28 downto 25) => cmd_first_word_i_8(3 downto 0),
\in\(24 downto 15) => p_1_out_7(26 downto 17),
\in\(14) => si_register_slice_inst_n_26,
\in\(13) => si_register_slice_inst_n_27,
\in\(12) => si_register_slice_inst_n_28,
\in\(11) => si_register_slice_inst_n_29,
\in\(10) => si_register_slice_inst_n_30,
\in\(9) => si_register_slice_inst_n_31,
\in\(8) => si_register_slice_inst_n_32,
\in\(7 downto 0) => \^m_axi_awlen\(7 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_wready => m_axi_wready,
\m_payload_i_reg[50]\(3) => si_register_slice_inst_n_140,
\m_payload_i_reg[50]\(2) => si_register_slice_inst_n_141,
\m_payload_i_reg[50]\(1) => si_register_slice_inst_n_142,
\m_payload_i_reg[50]\(0) => si_register_slice_inst_n_143,
\m_payload_i_reg[51]\(3) => si_register_slice_inst_n_144,
\m_payload_i_reg[51]\(2) => si_register_slice_inst_n_145,
\m_payload_i_reg[51]\(1) => si_register_slice_inst_n_146,
\m_payload_i_reg[51]\(0) => si_register_slice_inst_n_147,
m_valid_i_reg => \USE_WRITE.write_addr_inst_n_108\,
\out\ => \out\,
p_0_out => p_0_out,
p_11_out => p_11_out,
\p_122_out__2\ => \p_122_out__2\,
p_14_out => p_14_out,
\p_151_out__2\ => \p_151_out__2\,
p_17_out18_out => p_17_out18_out,
\p_180_out__2\ => \p_180_out__2\,
\p_209_out__2\ => \p_209_out__2\,
p_22_out => p_22_out,
\p_240_out__2\ => \p_240_out__2\,
p_25_out26_out => p_25_out26_out,
\p_269_out__2\ => \p_269_out__2\,
\p_298_out__2\ => \p_298_out__2\,
p_30_out => p_30_out,
\p_327_out__2\ => \p_327_out__2\,
p_33_out => p_33_out,
\p_358_out__2\ => \p_358_out__2\,
p_37_out => p_37_out,
\p_387_out__2\ => \p_387_out__2\,
p_3_out4_out => p_3_out4_out,
\p_416_out__2\ => \p_416_out__2\,
p_41_out => p_41_out,
\p_445_out__2\ => \p_445_out__2\,
p_44_out => p_44_out,
p_476_in => p_476_in,
p_47_out => p_47_out,
\p_481_out__2\ => \p_481_out__2\,
p_487_in => p_487_in,
p_51_out52_out => p_51_out52_out,
p_55_out56_out => p_55_out56_out,
\p_61_out__2\ => \p_61_out__2\,
p_8_out => p_8_out,
\p_91_out__2\ => \p_91_out__2\,
s_axi_aresetn => s_axi_aresetn,
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
s_ready_i_reg => \USE_WRITE.write_addr_inst_n_106\,
\sel_first_word__0\ => \sel_first_word__0_0\,
sr_awvalid => sr_awvalid,
wr_cmd_valid => wr_cmd_valid,
wrap_buffer_available => wrap_buffer_available_2,
wrap_buffer_available_reg => \USE_WRITE.write_addr_inst_n_109\,
wstrb_wrap_buffer_1 => wstrb_wrap_buffer_1,
wstrb_wrap_buffer_10 => wstrb_wrap_buffer_10,
wstrb_wrap_buffer_11 => wstrb_wrap_buffer_11,
wstrb_wrap_buffer_12 => wstrb_wrap_buffer_12,
wstrb_wrap_buffer_13 => wstrb_wrap_buffer_13,
wstrb_wrap_buffer_14 => wstrb_wrap_buffer_14,
wstrb_wrap_buffer_15 => wstrb_wrap_buffer_15,
wstrb_wrap_buffer_2 => wstrb_wrap_buffer_2,
wstrb_wrap_buffer_3 => wstrb_wrap_buffer_3,
wstrb_wrap_buffer_4 => wstrb_wrap_buffer_4,
wstrb_wrap_buffer_5 => wstrb_wrap_buffer_5,
wstrb_wrap_buffer_6 => wstrb_wrap_buffer_6,
wstrb_wrap_buffer_7 => wstrb_wrap_buffer_7,
wstrb_wrap_buffer_8 => wstrb_wrap_buffer_8,
wstrb_wrap_buffer_9 => wstrb_wrap_buffer_9
);
si_register_slice_inst: entity work.\system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\
port map (
CO(0) => sub_sized_wrap0_6,
D(60 downto 0) => D(60 downto 0),
DI(1) => si_register_slice_inst_n_148,
DI(0) => si_register_slice_inst_n_149,
Q(41 downto 0) => Q(41 downto 0),
S(3) => si_register_slice_inst_n_150,
S(2) => si_register_slice_inst_n_151,
S(1) => si_register_slice_inst_n_152,
S(0) => si_register_slice_inst_n_153,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(1) => si_register_slice_inst_n_200,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\(0) => si_register_slice_inst_n_201,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(3) => si_register_slice_inst_n_202,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(2) => si_register_slice_inst_n_203,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(1) => si_register_slice_inst_n_204,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]_0\(0) => si_register_slice_inst_n_205,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3) => si_register_slice_inst_n_4,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(2) => si_register_slice_inst_n_5,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(1) => si_register_slice_inst_n_6,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0) => si_register_slice_inst_n_7,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3) => si_register_slice_inst_n_140,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(2) => si_register_slice_inst_n_141,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(1) => si_register_slice_inst_n_142,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0) => si_register_slice_inst_n_143,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(3) => si_register_slice_inst_n_144,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(2) => si_register_slice_inst_n_145,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(1) => si_register_slice_inst_n_146,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_1\(0) => si_register_slice_inst_n_147,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(3) => si_register_slice_inst_n_192,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(2) => si_register_slice_inst_n_193,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(1) => si_register_slice_inst_n_194,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_2\(0) => si_register_slice_inst_n_195,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(32) => cmd_fix_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(31) => cmd_modified_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(30) => cmd_complete_wrap_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(29) => cmd_packed_wrap_i,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(28 downto 25) => cmd_first_word_i(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(24 downto 15) => p_1_out(26 downto 17),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(14) => si_register_slice_inst_n_175,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(13) => si_register_slice_inst_n_176,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12) => si_register_slice_inst_n_177,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(11) => si_register_slice_inst_n_178,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(10) => si_register_slice_inst_n_179,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(9) => si_register_slice_inst_n_180,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(8) => si_register_slice_inst_n_181,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\ => \USE_WRITE.write_addr_inst_n_106\,
\USE_RTL_VALID_WRITE.buffer_Full_q_reg_0\ => \USE_READ.read_addr_inst_n_60\,
cmd_push_block_reg => \USE_READ.read_addr_inst_n_62\,
cmd_push_block_reg_0 => \USE_WRITE.write_addr_inst_n_108\,
\in\(32) => cmd_fix_i_12,
\in\(31) => cmd_modified_i_11,
\in\(30) => cmd_complete_wrap_i_10,
\in\(29) => cmd_packed_wrap_i_9,
\in\(28 downto 25) => cmd_first_word_i_8(3 downto 0),
\in\(24 downto 15) => p_1_out_7(26 downto 17),
\in\(14) => si_register_slice_inst_n_26,
\in\(13) => si_register_slice_inst_n_27,
\in\(12) => si_register_slice_inst_n_28,
\in\(11) => si_register_slice_inst_n_29,
\in\(10) => si_register_slice_inst_n_30,
\in\(9) => si_register_slice_inst_n_31,
\in\(8) => si_register_slice_inst_n_32,
\in\(7 downto 0) => \^m_axi_awlen\(7 downto 0),
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arready => m_axi_arready,
\m_axi_arregion[3]\(43 downto 0) => \m_axi_arregion[3]\(43 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
\m_payload_i_reg[37]\(0) => sub_sized_wrap0,
\m_payload_i_reg[50]\(0) => cmd_packed_wrap_i1_5,
\m_payload_i_reg[50]_0\(0) => cmd_packed_wrap_i1,
\out\ => \out\,
p_0_in(0) => p_0_in(1),
s_axi_aresetn => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
s_axi_aresetn_0 => s_axi_aresetn,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 0) => \s_axi_arregion[3]\(60 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg => si_register_slice_inst_n_1,
sr_arvalid => sr_arvalid,
sr_awvalid => sr_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0_axi_dwidth_converter_v2_1_11_top is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "artix7";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 4;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 128;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_RATIO : integer;
attribute C_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is "axi_dwidth_converter_v2_1_11_top";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of system_auto_us_0_axi_dwidth_converter_v2_1_11_top : entity is 16;
end system_auto_us_0_axi_dwidth_converter_v2_1_11_top;
architecture STRUCTURE of system_auto_us_0_axi_dwidth_converter_v2_1_11_top is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
begin
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^s_axi_bready\ <= s_axi_bready;
m_axi_bready <= \^s_axi_bready\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rid(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_upsizer.gen_full_upsizer.axi_upsizer_inst\: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer
port map (
D(60 downto 57) => s_axi_awregion(3 downto 0),
D(56 downto 53) => s_axi_awqos(3 downto 0),
D(52) => s_axi_awlock(0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 40) => s_axi_awcache(3 downto 0),
D(39 downto 38) => s_axi_awburst(1 downto 0),
D(37 downto 35) => s_axi_awsize(2 downto 0),
D(34 downto 32) => s_axi_awprot(2 downto 0),
D(31 downto 0) => s_axi_awaddr(31 downto 0),
Q(41 downto 38) => m_axi_awregion(3 downto 0),
Q(37 downto 34) => m_axi_awqos(3 downto 0),
Q(33) => m_axi_awlock(0),
Q(32 downto 29) => m_axi_awcache(3 downto 0),
Q(28 downto 26) => m_axi_awprot(2 downto 0),
Q(25 downto 0) => m_axi_awaddr(31 downto 6),
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arready => m_axi_arready,
\m_axi_arregion[3]\(43 downto 40) => m_axi_arregion(3 downto 0),
\m_axi_arregion[3]\(39 downto 36) => m_axi_arqos(3 downto 0),
\m_axi_arregion[3]\(35) => m_axi_arlock(0),
\m_axi_arregion[3]\(34 downto 31) => m_axi_arcache(3 downto 0),
\m_axi_arregion[3]\(30 downto 28) => m_axi_arprot(2 downto 0),
\m_axi_arregion[3]\(27 downto 0) => m_axi_araddr(31 downto 4),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(5 downto 0) => m_axi_awaddr(5 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wvalid => m_axi_wvalid,
\out\ => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
\s_axi_arregion[3]\(60 downto 57) => s_axi_arregion(3 downto 0),
\s_axi_arregion[3]\(56 downto 53) => s_axi_arqos(3 downto 0),
\s_axi_arregion[3]\(52) => s_axi_arlock(0),
\s_axi_arregion[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arregion[3]\(43 downto 40) => s_axi_arcache(3 downto 0),
\s_axi_arregion[3]\(39 downto 38) => s_axi_arburst(1 downto 0),
\s_axi_arregion[3]\(37 downto 35) => s_axi_arsize(2 downto 0),
\s_axi_arregion[3]\(34 downto 32) => s_axi_arprot(2 downto 0),
\s_axi_arregion[3]\(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_us_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_us_0 : entity is "system_auto_us_0,axi_dwidth_converter_v2_1_11_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_us_0 : entity is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
end system_auto_us_0;
architecture STRUCTURE of system_auto_us_0 is
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of inst : label is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of inst : label is 4;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of inst : label is 128;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of inst : label is 1;
attribute C_RATIO : integer;
attribute C_RATIO of inst : label is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of inst : label is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of inst : label is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of inst : label is 16;
begin
inst: entity work.system_auto_us_0_axi_dwidth_converter_v2_1_11_top
port map (
m_axi_aclk => '0',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => '0',
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
5fc9617afa7da8f2d0ea52cfbb852a98
| 0.57265 | 2.488761 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/red_diamond_top.vhd
| 1 | 2,801 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 02/26/2015
-- Design Name: red_diamond_top
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This AES3/EBU and SPDIF receiver is compliant with
-- IEC61937, IEC60958-3 and IEC60958-4
-- The input is sampled in by either
-- 49.152 MHz for 48kHz, 96kHz and 192kHz samplerates
-- 45.1584 MHz for 44.1kHz, 88.2kHz or 176.4 kHz
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Added first simple I2S transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.spdif_pkg.all;
use work.i2s_pkg.all;
entity red_diamond_top is
port (
-- clock
clk_48 : in std_logic;
clk_44_1 : in std_logic;
pll_lock : out std_logic;
-- aes3/ebu or spdif input
aes_din : in std_logic;
aes_lock : out std_logic;
-- a/d input
ad_bclk : out std_logic := '0';
ad_lrck : out std_logic := '0';
ad_data : out std_logic := '0';
-- hdmi input
-- d/a output
da_bclk : out std_logic := '0';
da_lrck : out std_logic := '0';
da_data : out std_logic := '0';
-- processor i2c connection
--mcu_i2c_scl : in std_logic;
--mcu_i2c_sda : inout std_logic;
-- LEDs
heartbeat_led : out std_logic
-- display
);
end red_diamond_top;
architecture rtl of red_diamond_top is
signal sl_clk : std_logic;
signal sl_clk1 : std_logic;
component heartbeat
port (
clk : in std_logic;
counter_out : out std_logic
);
end component;
component pll
port (
areset : in std_logic := '0';
clkswitch : in std_logic := '0';
inclk0 : in std_logic := '0';
inclk1 : in std_logic := '0';
c0 : out std_logic;
locked : out std_logic
);
end component pll;
begin
inst_pll: pll
port map (
areset => '0',
clkswitch => '1',
inclk0 => clk_48,
inclk1 => clk_44_1,
c0 => sl_clk,
locked => pll_lock
);
inst_aes3rx: aes3rx
port map (
reset => '0',
clk => sl_clk,
aes_in.data => aes_din,
aes_out.lock => aes_lock
);
inst_i2s_tx : i2s_tx
port map (
reset_n => '1',
mclk => sl_clk,
i2s_in.l_channel => x"00FFFF",
i2s_in.r_channel => x"FFFF00",
i2s_out.wclk => da_lrck,
i2s_out.bclk => da_bclk,
i2s_out.sdata => da_data
);
inst_heartbeat: heartbeat
port map (
clk => sl_clk,
counter_out => heartbeat_led
);
end rtl;
|
gpl-3.0
|
bc079352f597d996c8985ba5e4e2305a
| 0.531239 | 3.136618 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/lib/add_sub/cla_4_bit.vhd
| 1 | 2,374 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cla_4_bit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC;
zero : out STD_LOGIC;
overflow : out STD_LOGIC
);
end cla_4_bit;
architecture Behavioral of cla_4_bit is
--these wire the output of the CLL to each FA.
signal Cin1, Cin2, Cin3 : std_logic:='0';
--these wire the result of the add/sub check to each FA.
signal b0, b1, b2, b3 : std_logic:='0';
signal Bxor : std_logic_vector (3 downto 0);
--doing this trick so that I can get zero and overflow flags.
--see: http://vhdlguru.blogspot.com/2011/02/how-to-stop-using-buffer-ports-in-vhdl.html
--I didn't want to introduce buffers or inouts.
signal Sum_internal : std_logic_vector (3 downto 0);
signal Cout_internal : std_logic;
begin
--make sure the actual outputs get set from the internal wiring.
Sum <= Sum_internal;
Cout <= Cout_internal;
--add/sub control; this flips B if necessary.
Bxor(0) <= B(0) XOR Cin;
Bxor(1) <= B(1) XOR Cin;
Bxor(2) <= B(2) XOR Cin;
Bxor(3) <= B(3) XOR Cin;
--Carry-Look-Ahead Logic
CLL0: entity work.cl_logic port map (A,Bxor,Cin,Cin1,Cin2,Cin3,Cout_internal);
--Full adders; for CLA, then individual Couts dangle; they are
--handled by the CLL module and are technically unnecessary for
--the CLA implementation.
FA0: entity work.full_adder_1_bit port map (A(0),Bxor(0),Cin,open,Sum_internal(0));
FA1: entity work.full_adder_1_bit port map (A(1),Bxor(1),Cin1,open,Sum_internal(1));
FA2: entity work.full_adder_1_bit port map (A(2),Bxor(2),Cin2,open,Sum_internal(2));
FA3: entity work.full_adder_1_bit port map (A(3),Bxor(3),Cin3,open,Sum_internal(3));
--if any bit in sum is non-zero, then zero gets set to zero. Otherwise, zero
--gets set to one.
zero <= NOT(Sum_internal(0) OR Sum_internal(1) OR Sum_internal(2) OR Sum_internal(3));
--detect overflow for signed case.
overflow <= Cout_internal XOR Cin3;
end Behavioral;
|
agpl-3.0
|
83cd2676b77d1be5b0fb381fdb9f4b87
| 0.692502 | 3.063226 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-6-Consecutive-Ones/ones_testBench.vhd
| 1 | 1,620 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY maxOnes_testBench IS
END maxOnes_testBench;
ARCHITECTURE behavior OF maxOnes_testBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT maxOnesCounter
PORT(
x : IN STD_LOGIC;
clock : IN STD_LOGIC;
maxOnes : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal x : std_logic;
signal clock : std_logic;
--Outputs
signal maxOnes : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: maxOnesCounter PORT MAP (
x => x,
clock => clock,
maxOnes => maxOnes
);
-- define clock behaviour
proc_clock: process
begin
clock <= '0';
wait for 10 ns;
clock <= '1';
wait for 10 ns;
end process; --end proc_clock
-- define x input behaviour
proc_input: process
begin
--this should give maxOnes of 4
x <= '1'; wait for 20 ns;
x <= '0'; wait for 20 ns;
x <= '1'; wait for 20 ns;
x <= '1'; wait for 20 ns;
x <= '0'; wait for 20 ns;
x <= '0'; wait for 20 ns;
x <= '1'; wait for 20 ns;
x <= '1'; wait for 20 ns;
x <= '1'; wait for 20 ns;
x <= '1'; wait for 20 ns;
x <= '0'; wait for 20 ns;
x <= '1'; wait for 20 ns;
x <= '1'; wait for 20 ns;
report "Simulation done." severity failure;
end process; --end proc_input
END;
|
agpl-3.0
|
0ff1833cff0b0b76e1245f33232ffdba
| 0.599383 | 3.592018 | false | true | false | false |
daniw/add
|
lab1/Ex1/FIR_1x5_const_coeff/vhd/fir_1d_trn.vhd
| 1 | 3,074 |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 28-Mar-11, 21-Mar-14
-- Project : RT Video Lab 1: Exercise 1
-- Description: 5-tap FIR filter in transposed form
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity fir_1d_trn is
generic
(IN_DW : integer := 8; -- Input word width
OUT_DW : integer := 19; -- Output word width
COEF_DW : integer := 7; -- coefficient word width
TAPS : integer := 5; -- # of taps + 1 output register
DELAY : integer := 8); -- delay line
-- (to adapt latency to system architecture)
port
(ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector(COEF_DW-1 downto 0);
din : in std_logic_vector(IN_DW-1 downto 0);
out_data : out std_logic_vector(OUT_DW-1 downto 0)
);
end fir_1d_trn;
architecture Behavioral of fir_1d_trn is
-- type declarations
type STAGE_TYPE is array(TAPS-1 downto 0) of signed(OUT_DW-1 downto 0);
type DELAY_TYPE is array(DELAY downto 0) of signed(IN_DW-1 downto 0);
type COEFF_TYPE is array(TAPS-1 downto 0) of signed(COEF_DW-1 downto 0);
-- signal declarations (init values for simulation only!!!)
signal inreg : signed(OUT_DW-COEF_DW-1 downto 0) := (others => '0');
signal stage : STAGE_TYPE := (others => (others => '0'));
signal del_line : DELAY_TYPE := (others => (others => '0'));
-- constant declarations
constant C_coef : COEFF_TYPE := (to_signed(2, COEF_DW), -- b4
to_signed(4, COEF_DW), -- b3
to_signed(8, COEF_DW), -- b2
to_signed(4, COEF_DW), -- b1
to_signed(2, COEF_DW)); -- b0
begin
-- comb. output assignment (output register already from stage(0))
out_data <= std_logic_vector(stage(0));
-- sequential process (without reset, because SysGen uses FIR-Compiler without
-- reset signal)
p0_FIR : process(clk_1)
begin
if rising_edge(clk_1) then
if ce_1 = '1' then
-- input delay line
del_line(DELAY) <= signed(din);
del_line(DELAY-1 downto 0) <= del_line(DELAY downto 1);
-- extend width of input sample
inreg(OUT_DW-COEF_DW-1 downto IN_DW) <= (others => '0');
inreg(IN_DW-1 downto 0) <= del_line(0);
-- compute filter taps
stage(TAPS-1) <= inreg * C_coef(TAPS-1);
for k in TAPS-2 downto 0 loop
stage(k) <= (inreg * C_coef(k)) + stage(k+1);
end loop;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
b1d6ccbfd7a65d826639a243961158af
| 0.502277 | 3.703614 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/PSR_tb.vhd
| 1 | 1,597 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PSR_tb IS
END PSR_tb;
ARCHITECTURE behavior OF PSR_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PSR
PORT(
NZVC : IN std_logic_vector(3 downto 0);
nCWP : IN std_logic;
CLK : IN std_logic;
rst : IN std_logic;
CWP : OUT std_logic;
C : OUT std_logic
);
END COMPONENT;
--Inputs
signal NZVC : std_logic_vector(3 downto 0) := (others => '0');
signal nCWP : std_logic := '0';
signal CLK : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal CWP : std_logic;
signal C : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PSR PORT MAP (
NZVC => NZVC,
nCWP => nCWP,
CLK => CLK,
rst => rst,
CWP => CWP,
C => C
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
NZVC<="1000";
wait for 40 ns;
NZVC<="0100";
wait for 40 ns;
NZVC<="1001";
nCWP<='1';
wait for 40 ns;
NZVC<="0000";
wait for 40 ns;
NZVC<="0011";
wait for 40 ns;
nCWP<='0';
wait for 40 ns;
NZVC<="1111";
wait for 40 ns;
rst<='1';
wait;
end process;
END;
|
mit
|
74dd586f93ad15fb85364a03589c098e
| 0.508453 | 3.4869 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_ethernetlite_0_0/system_axi_ethernetlite_0_0_sim_netlist.vhdl
| 1 | 869,087 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:47 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_ethernetlite_0_0/system_axi_ethernetlite_0_0_sim_netlist.vhdl
-- Design : system_axi_ethernetlite_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_axi_interface is
port (
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
\reg_data_out_reg[31]\ : out STD_LOGIC;
reg_data_out0 : out STD_LOGIC;
\reg_data_out_reg[31]_0\ : out STD_LOGIC;
\reg_data_out_reg[3]\ : out STD_LOGIC;
\reg_data_out_reg[1]\ : out STD_LOGIC;
\reg_data_out_reg[1]_0\ : out STD_LOGIC;
\reg_data_out_reg[0]\ : out STD_LOGIC;
\reg_data_out_reg[5]\ : out STD_LOGIC;
\reg_data_out_reg[2]\ : out STD_LOGIC;
\reg_data_out_reg[3]_0\ : out STD_LOGIC;
\reg_data_out_reg[6]\ : out STD_LOGIC;
\reg_data_out_reg[6]_0\ : out STD_LOGIC;
\reg_data_out_reg[6]_1\ : out STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : out STD_LOGIC;
tx_intr_en0 : out STD_LOGIC;
\ping_pkt_lenth_reg[15]\ : out STD_LOGIC;
\reg_data_out_reg[3]_1\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
\reg_data_out_reg[4]\ : out STD_LOGIC;
\reg_data_out_reg[15]\ : out STD_LOGIC;
\reg_data_out_reg[14]\ : out STD_LOGIC;
\reg_data_out_reg[13]\ : out STD_LOGIC;
\reg_data_out_reg[12]\ : out STD_LOGIC;
\reg_data_out_reg[11]\ : out STD_LOGIC;
\reg_data_out_reg[10]\ : out STD_LOGIC;
\reg_data_out_reg[9]\ : out STD_LOGIC;
\reg_data_out_reg[8]\ : out STD_LOGIC;
\reg_data_out_reg[7]\ : out STD_LOGIC;
\reg_data_out_reg[6]_2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\MDIO_GEN.mdio_wr_data_reg_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
rx_intr_en0 : out STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_44_out : out STD_LOGIC;
p_19_out : out STD_LOGIC;
\MDIO_GEN.mdio_reg_addr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\MDIO_GEN.mdio_data_out_reg[11]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[15]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[3]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[11]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
reg_access_reg : out STD_LOGIC;
\MDIO_GEN.mdio_en_i_reg\ : out STD_LOGIC;
gie_enable_reg : out STD_LOGIC;
\TX_PONG_REG_GEN.pong_soft_status_reg\ : out STD_LOGIC;
ping_soft_status_reg : out STD_LOGIC;
tx_intr_en_reg : out STD_LOGIC;
enb : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : out STD_LOGIC;
web : out STD_LOGIC_VECTOR ( 0 to 0 );
rx_intr_en_reg : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[15]_0\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[15]_1\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[14]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[13]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[12]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[11]_1\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[11]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\MDIO_GEN.mdio_data_out_reg[11]_3\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\reg_data_out_reg[31]_1\ : in STD_LOGIC;
pong_soft_status : in STD_LOGIC;
p_21_in144_in : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\reg_data_out_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\reg_data_out_reg[0]_0\ : in STD_LOGIC;
p_33_in182_in : in STD_LOGIC;
\reg_data_out_reg[2]_0\ : in STD_LOGIC;
p_17_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
ping_soft_status : in STD_LOGIC;
p_5_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\ping_pkt_lenth_reg[15]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
p_15_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_tx_status_reg : in STD_LOGIC;
p_9_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
pong_rx_status : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
reg_access : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
mdio_en_i : in STD_LOGIC;
mdio_rd_data_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\MDIO_GEN.mdio_wr_data_reg_reg[15]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_axi_interface : entity is "axi_interface";
end system_axi_ethernetlite_0_0_axi_interface;
architecture STRUCTURE of system_axi_ethernetlite_0_0_axi_interface is
signal \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.bvalid_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.read_in_prog_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.read_req_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.rvalid_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.write_in_prog_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[11]\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[11]_0\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[15]\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[15]_1\ : STD_LOGIC;
signal \^rx_pong_reg_gen.pong_rx_status_reg\ : STD_LOGIC;
signal \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\ : STD_LOGIC;
signal \XEMAC_I/reg_access_i\ : STD_LOGIC;
signal arready_i1 : STD_LOGIC;
signal arready_i2 : STD_LOGIC;
signal bus2ip_rdce : STD_LOGIC;
signal gie_enable_i_2_n_0 : STD_LOGIC;
signal \^p_19_out\ : STD_LOGIC;
signal p_2_in : STD_LOGIC_VECTOR ( 12 downto 2 );
signal \^p_44_out\ : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal \ping_pkt_lenth[15]_i_3_n_0\ : STD_LOGIC;
signal \^ping_pkt_lenth_reg[15]\ : STD_LOGIC;
signal ping_rx_status_i_3_n_0 : STD_LOGIC;
signal read_in_prog : STD_LOGIC;
signal read_req : STD_LOGIC;
signal \^reg_data_out0\ : STD_LOGIC;
signal \reg_data_out[0]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[0]_i_3_n_0\ : STD_LOGIC;
signal \reg_data_out[0]_i_4_n_0\ : STD_LOGIC;
signal \reg_data_out[0]_i_6_n_0\ : STD_LOGIC;
signal \reg_data_out[15]_i_11_n_0\ : STD_LOGIC;
signal \reg_data_out[15]_i_7_n_0\ : STD_LOGIC;
signal \reg_data_out[15]_i_8_n_0\ : STD_LOGIC;
signal \reg_data_out[15]_i_9_n_0\ : STD_LOGIC;
signal \reg_data_out[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[1]_i_3_n_0\ : STD_LOGIC;
signal \reg_data_out[1]_i_4_n_0\ : STD_LOGIC;
signal \reg_data_out[2]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[31]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[31]_i_3_n_0\ : STD_LOGIC;
signal \reg_data_out[31]_i_4_n_0\ : STD_LOGIC;
signal \reg_data_out[31]_i_5_n_0\ : STD_LOGIC;
signal \reg_data_out[3]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[3]_i_3_n_0\ : STD_LOGIC;
signal \reg_data_out[3]_i_4_n_0\ : STD_LOGIC;
signal \reg_data_out[5]_i_3_n_0\ : STD_LOGIC;
signal \^reg_data_out_reg[1]_0\ : STD_LOGIC;
signal \^reg_data_out_reg[31]_0\ : STD_LOGIC;
signal \^reg_data_out_reg[3]_0\ : STD_LOGIC;
signal \^reg_data_out_reg[3]_1\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^reg_data_out_reg[6]\ : STD_LOGIC;
signal \^reg_data_out_reg[6]_0\ : STD_LOGIC;
signal \^rx_intr_en0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal \^tx_intr_en0\ : STD_LOGIC;
signal xpm_memory_base_inst_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.awready_i_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.bvalid_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.read_req_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[10]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[10]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[10]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[15]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[3]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[7]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_en_i_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of gie_enable_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ping_pkt_lenth[15]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ping_pkt_lenth[15]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of ping_rx_status_i_3 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of ping_soft_status_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of reg_access_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \reg_data_out[0]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \reg_data_out[0]_i_6\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \reg_data_out[15]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \reg_data_out[15]_i_7\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \reg_data_out[15]_i_8\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_data_out[15]_i_9\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \reg_data_out[31]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \reg_data_out[4]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of rx_intr_en_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of tx_intr_en_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_2__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_2__2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of xpm_memory_base_inst_i_3 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_3__0\ : label is "soft_lutpair10";
begin
\MDIO_GEN.mdio_data_out_reg[11]\ <= \^mdio_gen.mdio_data_out_reg[11]\;
\MDIO_GEN.mdio_data_out_reg[11]_0\ <= \^mdio_gen.mdio_data_out_reg[11]_0\;
\MDIO_GEN.mdio_data_out_reg[15]\ <= \^mdio_gen.mdio_data_out_reg[15]\;
\MDIO_GEN.mdio_data_out_reg[15]_1\ <= \^mdio_gen.mdio_data_out_reg[15]_1\;
\RX_PONG_REG_GEN.pong_rx_status_reg\ <= \^rx_pong_reg_gen.pong_rx_status_reg\;
p_19_out <= \^p_19_out\;
p_44_out <= \^p_44_out\;
\ping_pkt_lenth_reg[15]\ <= \^ping_pkt_lenth_reg[15]\;
reg_data_out0 <= \^reg_data_out0\;
\reg_data_out_reg[1]_0\ <= \^reg_data_out_reg[1]_0\;
\reg_data_out_reg[31]_0\ <= \^reg_data_out_reg[31]_0\;
\reg_data_out_reg[3]_0\ <= \^reg_data_out_reg[3]_0\;
\reg_data_out_reg[3]_1\(10 downto 0) <= \^reg_data_out_reg[3]_1\(10 downto 0);
\reg_data_out_reg[6]\ <= \^reg_data_out_reg[6]\;
\reg_data_out_reg[6]_0\ <= \^reg_data_out_reg[6]_0\;
rx_intr_en0 <= \^rx_intr_en0\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_wready <= \^s_axi_wready\;
tx_intr_en0 <= \^tx_intr_en0\;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBB7"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(2),
I1 => \XEMAC_I/reg_access_i\,
I2 => \^reg_data_out_reg[3]_1\(0),
I3 => \^reg_data_out_reg[3]_1\(1),
O => \^mdio_gen.mdio_data_out_reg[11]_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(0),
Q => s_axi_rdata(0),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(10),
Q => s_axi_rdata(10),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(11),
Q => s_axi_rdata(11),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(12),
Q => s_axi_rdata(12),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(13),
Q => s_axi_rdata(13),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(14),
Q => s_axi_rdata(14),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(15),
Q => s_axi_rdata(15),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(16),
Q => s_axi_rdata(16),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(17),
Q => s_axi_rdata(17),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(18),
Q => s_axi_rdata(18),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(19),
Q => s_axi_rdata(19),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(1),
Q => s_axi_rdata(1),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(20),
Q => s_axi_rdata(20),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(21),
Q => s_axi_rdata(21),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(22),
Q => s_axi_rdata(22),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(23),
Q => s_axi_rdata(23),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(24),
Q => s_axi_rdata(24),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(25),
Q => s_axi_rdata(25),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(26),
Q => s_axi_rdata(26),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(27),
Q => s_axi_rdata(27),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(28),
Q => s_axi_rdata(28),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(29),
Q => s_axi_rdata(29),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(2),
Q => s_axi_rdata(2),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(30),
Q => s_axi_rdata(30),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(31),
Q => s_axi_rdata(31),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(3),
Q => s_axi_rdata(3),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(4),
Q => s_axi_rdata(4),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(5),
Q => s_axi_rdata(5),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(6),
Q => s_axi_rdata(6),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(7),
Q => s_axi_rdata(7),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(8),
Q => s_axi_rdata(8),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(9),
Q => s_axi_rdata(9),
R => SR(0)
);
\AXI4_LITE_IF_GEN.arready_i2_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => arready_i1,
Q => arready_i2,
R => SR(0)
);
\AXI4_LITE_IF_GEN.awready_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I2 => \^s_axi_wready\,
O => p_8_out
);
\AXI4_LITE_IF_GEN.awready_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_8_out,
Q => \^s_axi_wready\,
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(8),
O => p_2_in(10)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(9),
O => p_2_in(11)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I1 => s_axi_arvalid,
I2 => bus2ip_rdce,
I3 => s_axi_awvalid,
O => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(10),
O => p_2_in(12)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(0),
O => p_2_in(2)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(1),
O => p_2_in(3)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(2),
O => p_2_in(4)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(3),
O => p_2_in(5)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(4),
O => p_2_in(6)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(5),
O => p_2_in(7)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(6),
O => p_2_in(8)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(7),
O => p_2_in(9)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(10),
Q => \^reg_data_out_reg[3]_1\(8),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(11),
Q => \^reg_data_out_reg[3]_1\(9),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(12),
Q => \^reg_data_out_reg[3]_1\(10),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(2),
Q => \^reg_data_out_reg[3]_1\(0),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(3),
Q => \^reg_data_out_reg[3]_1\(1),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(4),
Q => \^reg_data_out_reg[3]_1\(2),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(5),
Q => \^reg_data_out_reg[3]_1\(3),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(6),
Q => \^reg_data_out_reg[3]_1\(4),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(7),
Q => \^reg_data_out_reg[3]_1\(5),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(8),
Q => \^reg_data_out_reg[3]_1\(6),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(9),
Q => \^reg_data_out_reg[3]_1\(7),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_rdce_i_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_rdce,
Q => arready_i1,
R => SR(0)
);
\AXI4_LITE_IF_GEN.bvalid_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
O => \AXI4_LITE_IF_GEN.bvalid_i_1_n_0\
);
\AXI4_LITE_IF_GEN.bvalid_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.bvalid_i_1_n_0\,
Q => \^s_axi_bvalid\,
R => SR(0)
);
\AXI4_LITE_IF_GEN.read_in_prog_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => bus2ip_rdce,
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => read_in_prog,
O => \AXI4_LITE_IF_GEN.read_in_prog_i_1_n_0\
);
\AXI4_LITE_IF_GEN.read_in_prog_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD5D5D5"
)
port map (
I0 => s_axi_aresetn,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => \^s_axi_bvalid\,
I4 => s_axi_bready,
O => read_in_prog
);
\AXI4_LITE_IF_GEN.read_in_prog_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.read_in_prog_i_1_n_0\,
Q => bus2ip_rdce,
R => '0'
);
\AXI4_LITE_IF_GEN.read_req_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7530"
)
port map (
I0 => s_axi_rready,
I1 => arready_i1,
I2 => s_axi_arvalid,
I3 => read_req,
O => \AXI4_LITE_IF_GEN.read_req_i_1_n_0\
);
\AXI4_LITE_IF_GEN.read_req_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.read_req_i_1_n_0\,
Q => read_req,
R => SR(0)
);
\AXI4_LITE_IF_GEN.rvalid_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F08080"
)
port map (
I0 => arready_i1,
I1 => read_req,
I2 => s_axi_aresetn,
I3 => s_axi_rready,
I4 => \^s_axi_rlast\,
O => \AXI4_LITE_IF_GEN.rvalid_i_1_n_0\
);
\AXI4_LITE_IF_GEN.rvalid_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.rvalid_i_1_n_0\,
Q => \^s_axi_rlast\,
R => '0'
);
\AXI4_LITE_IF_GEN.write_in_prog_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAEAA"
)
port map (
I0 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I1 => s_axi_awvalid,
I2 => bus2ip_rdce,
I3 => s_axi_wvalid,
I4 => s_axi_arvalid,
I5 => read_in_prog,
O => \AXI4_LITE_IF_GEN.write_in_prog_i_1_n_0\
);
\AXI4_LITE_IF_GEN.write_in_prog_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.write_in_prog_i_1_n_0\,
Q => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
R => '0'
);
\MDIO_GEN.mdio_data_out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[11]_0\,
I1 => bus2ip_rdce,
I2 => s_axi_aresetn,
O => \MDIO_GEN.mdio_data_out_reg[11]_2\(0)
);
\MDIO_GEN.mdio_data_out[10]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \XEMAC_I/reg_access_i\,
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \^reg_data_out_reg[3]_1\(1),
I4 => bus2ip_rdce,
O => \^mdio_gen.mdio_data_out_reg[15]_1\
);
\MDIO_GEN.mdio_data_out[10]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(0),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \XEMAC_I/reg_access_i\,
O => \^mdio_gen.mdio_data_out_reg[11]\
);
\MDIO_GEN.mdio_data_out[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"44F4"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I1 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(0),
I2 => mdio_rd_data_reg(0),
I3 => \^mdio_gen.mdio_data_out_reg[15]\,
O => \MDIO_GEN.mdio_data_out_reg[11]_1\
);
\MDIO_GEN.mdio_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"44F4"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I1 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(1),
I2 => mdio_rd_data_reg(1),
I3 => \^mdio_gen.mdio_data_out_reg[15]\,
O => \MDIO_GEN.mdio_data_out_reg[12]\
);
\MDIO_GEN.mdio_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"44F4"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I1 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(2),
I2 => mdio_rd_data_reg(2),
I3 => \^mdio_gen.mdio_data_out_reg[15]\,
O => \MDIO_GEN.mdio_data_out_reg[13]\
);
\MDIO_GEN.mdio_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"44F4"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I1 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(3),
I2 => mdio_rd_data_reg(3),
I3 => \^mdio_gen.mdio_data_out_reg[15]\,
O => \MDIO_GEN.mdio_data_out_reg[14]\
);
\MDIO_GEN.mdio_data_out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F0F"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[11]_0\,
I1 => bus2ip_rdce,
I2 => s_axi_aresetn,
I3 => \^mdio_gen.mdio_data_out_reg[11]\,
O => \MDIO_GEN.mdio_data_out_reg[11]_3\
);
\MDIO_GEN.mdio_data_out[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]\,
I1 => mdio_rd_data_reg(4),
I2 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I3 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(4),
O => \MDIO_GEN.mdio_data_out_reg[15]_0\
);
\MDIO_GEN.mdio_data_out[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \XEMAC_I/reg_access_i\,
O => \MDIO_GEN.mdio_data_out_reg[3]\
);
\MDIO_GEN.mdio_data_out[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \XEMAC_I/reg_access_i\,
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \^reg_data_out_reg[3]_1\(1),
I4 => bus2ip_rdce,
O => \^mdio_gen.mdio_data_out_reg[15]\
);
\MDIO_GEN.mdio_en_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^p_19_out\,
I2 => mdio_en_i,
O => \MDIO_GEN.mdio_en_i_reg\
);
\MDIO_GEN.mdio_reg_addr[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => s_axi_wvalid,
I1 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => \^reg_data_out_reg[3]_1\(2),
I5 => \XEMAC_I/reg_access_i\,
O => \MDIO_GEN.mdio_reg_addr_reg[4]\(0)
);
\MDIO_GEN.mdio_reg_addr[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(5),
I1 => \^reg_data_out_reg[3]_1\(3),
I2 => \^reg_data_out_reg[3]_1\(8),
I3 => \^reg_data_out_reg[3]_1\(4),
I4 => \^reg_data_out_reg[3]_1\(6),
I5 => \^reg_data_out_reg[3]_1\(7),
O => \XEMAC_I/reg_access_i\
);
\MDIO_GEN.mdio_req_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => s_axi_wvalid,
I1 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => \^reg_data_out_reg[3]_1\(2),
I5 => \XEMAC_I/reg_access_i\,
O => \^p_19_out\
);
\MDIO_GEN.mdio_wr_data_reg[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(1),
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \XEMAC_I/reg_access_i\,
I3 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I4 => s_axi_wvalid,
I5 => \^reg_data_out_reg[3]_1\(0),
O => \MDIO_GEN.mdio_wr_data_reg_reg[15]\(0)
);
\RX_PONG_REG_GEN.pong_rx_status_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \XEMAC_I/reg_access_i\,
I1 => \^reg_data_out_reg[3]_1\(9),
I2 => \^reg_data_out_reg[3]_1\(10),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => \^reg_data_out_reg[3]_1\(1),
I5 => \^reg_data_out_reg[3]_1\(2),
O => \^rx_pong_reg_gen.pong_rx_status_reg\
);
\TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(10),
I1 => \^reg_data_out_reg[3]_1\(9),
O => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\
);
\TX_PONG_REG_GEN.pong_soft_status_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^p_44_out\,
I2 => pong_soft_status,
O => \TX_PONG_REG_GEN.pong_soft_status_reg\
);
\TX_PONG_REG_GEN.pong_tx_status_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \^p_44_out\
);
gie_enable_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFBF0080"
)
port map (
I0 => s_axi_wdata(1),
I1 => s_axi_wvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => gie_enable_i_2_n_0,
I4 => p_5_in(0),
O => gie_enable_reg
);
gie_enable_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFDFFFFFF"
)
port map (
I0 => \XEMAC_I/reg_access_i\,
I1 => \^reg_data_out_reg[3]_1\(9),
I2 => \^reg_data_out_reg[3]_1\(10),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \^reg_data_out_reg[3]_1\(1),
I5 => \^reg_data_out_reg[3]_1\(0),
O => gie_enable_i_2_n_0
);
\ping_pkt_lenth[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \ping_pkt_lenth[15]_i_3_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => E(0)
);
\ping_pkt_lenth[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I1 => s_axi_wvalid,
O => \^ping_pkt_lenth_reg[15]\
);
\ping_pkt_lenth[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
O => \ping_pkt_lenth[15]_i_3_n_0\
);
ping_rx_status_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => ping_rx_status_i_3_n_0,
I5 => \XEMAC_I/reg_access_i\,
O => \^rx_intr_en0\
);
ping_rx_status_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
O => ping_rx_status_i_3_n_0
);
ping_soft_status_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^tx_intr_en0\,
I2 => ping_soft_status,
O => ping_soft_status_reg
);
ping_tx_status_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \ping_pkt_lenth[15]_i_3_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \^tx_intr_en0\
);
reg_access_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \XEMAC_I/reg_access_i\,
I1 => bus2ip_rdce,
I2 => reg_access,
O => reg_access_reg
);
\reg_data_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2E2EEE2"
)
port map (
I0 => \reg_data_out_reg[0]_0\,
I1 => \^reg_data_out0\,
I2 => \reg_data_out[0]_i_2_n_0\,
I3 => Q(0),
I4 => \^reg_data_out_reg[1]_0\,
I5 => \reg_data_out[0]_i_3_n_0\,
O => \reg_data_out_reg[0]\
);
\reg_data_out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEEEFFFFFEEEFEEE"
)
port map (
I0 => \reg_data_out[0]_i_4_n_0\,
I1 => ping_tx_status_reg,
I2 => \reg_data_out[15]_i_11_n_0\,
I3 => p_9_in(0),
I4 => \^reg_data_out_reg[6]\,
I5 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(0),
O => \reg_data_out[0]_i_2_n_0\
);
\reg_data_out[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => gie_enable_i_2_n_0,
I1 => bus2ip_rdce,
I2 => s_axi_aresetn,
O => \reg_data_out[0]_i_3_n_0\
);
\reg_data_out[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => pong_rx_status,
I1 => \XEMAC_I/reg_access_i\,
I2 => \^reg_data_out_reg[3]_1\(9),
I3 => \^reg_data_out_reg[3]_1\(10),
I4 => \reg_data_out[0]_i_6_n_0\,
I5 => bus2ip_rdce,
O => \reg_data_out[0]_i_4_n_0\
);
\reg_data_out[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
O => \reg_data_out[0]_i_6_n_0\
);
\reg_data_out[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(9),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(8),
O => \reg_data_out_reg[10]\
);
\reg_data_out[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(10),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(9),
O => \reg_data_out_reg[11]\
);
\reg_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(11),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(10),
O => \reg_data_out_reg[12]\
);
\reg_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(12),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(11),
O => \reg_data_out_reg[13]\
);
\reg_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(13),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(12),
O => \reg_data_out_reg[14]\
);
\reg_data_out[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFBBB0000"
)
port map (
I0 => \^reg_data_out_reg[31]_0\,
I1 => s_axi_aresetn,
I2 => \^reg_data_out_reg[6]_0\,
I3 => \^reg_data_out_reg[6]\,
I4 => \reg_data_out[15]_i_7_n_0\,
I5 => \reg_data_out[15]_i_8_n_0\,
O => \reg_data_out_reg[6]_1\
);
\reg_data_out[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7FFFFFFFFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \ping_pkt_lenth[15]_i_3_n_0\,
I4 => \XEMAC_I/reg_access_i\,
I5 => bus2ip_rdce,
O => \^reg_data_out_reg[3]_0\
);
\reg_data_out[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => ping_rx_status_i_3_n_0,
I5 => \XEMAC_I/reg_access_i\,
O => \reg_data_out[15]_i_11_n_0\
);
\reg_data_out[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A8AA"
)
port map (
I0 => bus2ip_rdce,
I1 => \XEMAC_I/reg_access_i\,
I2 => \reg_data_out[15]_i_9_n_0\,
I3 => \^reg_data_out_reg[3]_1\(0),
O => \^reg_data_out0\
);
\reg_data_out[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(14),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(13),
O => \reg_data_out_reg[15]\
);
\reg_data_out[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \^reg_data_out_reg[31]_0\
);
\reg_data_out[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDFFFFFFFFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \ping_pkt_lenth[15]_i_3_n_0\,
I4 => \XEMAC_I/reg_access_i\,
I5 => bus2ip_rdce,
O => \^reg_data_out_reg[6]_0\
);
\reg_data_out[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDFFFFFFFFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\,
I4 => \XEMAC_I/reg_access_i\,
I5 => bus2ip_rdce,
O => \^reg_data_out_reg[6]\
);
\reg_data_out[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
O => \reg_data_out[15]_i_7_n_0\
);
\reg_data_out[15]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_0\,
I1 => \^reg_data_out_reg[31]_0\,
I2 => \reg_data_out[3]_i_3_n_0\,
I3 => \reg_data_out[15]_i_11_n_0\,
I4 => s_axi_aresetn,
O => \reg_data_out[15]_i_8_n_0\
);
\reg_data_out[15]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(2),
I1 => \^reg_data_out_reg[3]_1\(1),
O => \reg_data_out[15]_i_9_n_0\
);
\reg_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2E2EEE2"
)
port map (
I0 => \reg_data_out_reg[1]_1\,
I1 => \^reg_data_out0\,
I2 => \reg_data_out[1]_i_2_n_0\,
I3 => Q(1),
I4 => \^reg_data_out_reg[1]_0\,
I5 => \reg_data_out[1]_i_3_n_0\,
O => \reg_data_out_reg[1]\
);
\reg_data_out[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF22F2"
)
port map (
I0 => \ping_pkt_lenth_reg[15]_0\(0),
I1 => \^reg_data_out_reg[6]_0\,
I2 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(1),
I3 => \^reg_data_out_reg[6]\,
I4 => \reg_data_out[1]_i_4_n_0\,
O => \reg_data_out[1]_i_2_n_0\
);
\reg_data_out[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \reg_data_out[15]_i_11_n_0\,
I2 => \reg_data_out[3]_i_3_n_0\,
O => \reg_data_out[1]_i_3_n_0\
);
\reg_data_out[1]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F444"
)
port map (
I0 => \^reg_data_out_reg[3]_0\,
I1 => p_17_in(0),
I2 => \^reg_data_out_reg[31]_0\,
I3 => p_15_in(0),
O => \reg_data_out[1]_i_4_n_0\
);
\reg_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEEE22E2"
)
port map (
I0 => \reg_data_out_reg[2]_0\,
I1 => \^reg_data_out0\,
I2 => Q(2),
I3 => \^reg_data_out_reg[1]_0\,
I4 => \reg_data_out[2]_i_2_n_0\,
I5 => \reg_data_out[15]_i_8_n_0\,
O => \reg_data_out_reg[2]\
);
\reg_data_out[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(2),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(1),
O => \reg_data_out[2]_i_2_n_0\
);
\reg_data_out[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE2E2E2"
)
port map (
I0 => \reg_data_out_reg[31]_1\,
I1 => \^reg_data_out0\,
I2 => \reg_data_out[31]_i_2_n_0\,
I3 => pong_soft_status,
I4 => \^reg_data_out_reg[31]_0\,
I5 => \reg_data_out[31]_i_3_n_0\,
O => \reg_data_out_reg[31]\
);
\reg_data_out[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444444F4444444"
)
port map (
I0 => \^reg_data_out_reg[3]_0\,
I1 => ping_soft_status,
I2 => p_5_in(0),
I3 => \^rx_pong_reg_gen.pong_rx_status_reg\,
I4 => bus2ip_rdce,
I5 => gie_enable_i_2_n_0,
O => \reg_data_out[31]_i_2_n_0\
);
\reg_data_out[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FFFFFFFFFF"
)
port map (
I0 => gie_enable_i_2_n_0,
I1 => \reg_data_out[15]_i_7_n_0\,
I2 => \reg_data_out[31]_i_4_n_0\,
I3 => \^reg_data_out_reg[6]\,
I4 => \reg_data_out[15]_i_11_n_0\,
I5 => s_axi_aresetn,
O => \reg_data_out[31]_i_3_n_0\
);
\reg_data_out[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => \reg_data_out[31]_i_5_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \reg_data_out[31]_i_4_n_0\
);
\reg_data_out[31]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
O => \reg_data_out[31]_i_5_n_0\
);
\reg_data_out[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000E200"
)
port map (
I0 => p_21_in144_in,
I1 => \^reg_data_out0\,
I2 => \reg_data_out[3]_i_2_n_0\,
I3 => s_axi_aresetn,
I4 => \^reg_data_out_reg[31]_0\,
I5 => \reg_data_out[3]_i_3_n_0\,
O => \reg_data_out_reg[3]\
);
\reg_data_out[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \^reg_data_out_reg[1]_0\,
I1 => Q(3),
I2 => p_17_in(1),
I3 => \^reg_data_out_reg[3]_0\,
I4 => \reg_data_out[3]_i_4_n_0\,
O => \reg_data_out[3]_i_2_n_0\
);
\reg_data_out[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000200000000"
)
port map (
I0 => \XEMAC_I/reg_access_i\,
I1 => \^reg_data_out_reg[3]_1\(9),
I2 => \^reg_data_out_reg[3]_1\(10),
I3 => \reg_data_out[15]_i_9_n_0\,
I4 => \^reg_data_out_reg[3]_1\(0),
I5 => bus2ip_rdce,
O => \reg_data_out[3]_i_3_n_0\
);
\reg_data_out[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB83030FF3030"
)
port map (
I0 => \reg_data_out[15]_i_11_n_0\,
I1 => \^reg_data_out_reg[6]_0\,
I2 => \ping_pkt_lenth_reg[15]_0\(2),
I3 => \^reg_data_out_reg[6]\,
I4 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(3),
I5 => p_9_in(1),
O => \reg_data_out[3]_i_4_n_0\
);
\reg_data_out[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \reg_data_out[15]_i_11_n_0\,
I1 => s_axi_aresetn,
I2 => \^reg_data_out_reg[31]_0\,
I3 => \reg_data_out[3]_i_3_n_0\,
O => \reg_data_out_reg[4]\
);
\reg_data_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEEE22E2"
)
port map (
I0 => p_33_in182_in,
I1 => \^reg_data_out0\,
I2 => Q(4),
I3 => \^reg_data_out_reg[1]_0\,
I4 => \reg_data_out[5]_i_3_n_0\,
I5 => \reg_data_out[15]_i_8_n_0\,
O => \reg_data_out_reg[5]\
);
\reg_data_out[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF7FFFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \^reg_data_out_reg[6]_0\,
I2 => \reg_data_out[15]_i_11_n_0\,
I3 => \reg_data_out[3]_i_3_n_0\,
I4 => \^reg_data_out_reg[31]_0\,
I5 => \^reg_data_out_reg[3]_0\,
O => \^reg_data_out_reg[1]_0\
);
\reg_data_out[5]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(4),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(3),
O => \reg_data_out[5]_i_3_n_0\
);
\reg_data_out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(5),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(4),
O => \reg_data_out_reg[6]_2\
);
\reg_data_out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(6),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(5),
O => \reg_data_out_reg[7]\
);
\reg_data_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(7),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(6),
O => \reg_data_out_reg[8]\
);
\reg_data_out[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(8),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(7),
O => \reg_data_out_reg[9]\
);
rx_intr_en_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^rx_intr_en0\,
I2 => p_9_in(1),
O => rx_intr_en_reg
);
s_axi_arready_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => arready_i1,
I1 => arready_i2,
O => s_axi_arready
);
tx_intr_en_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^tx_intr_en0\,
I2 => p_17_in(1),
O => tx_intr_en_reg
);
\xpm_memory_base_inst_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"10FF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
I2 => xpm_memory_base_inst_i_5_n_0,
I3 => s_axi_aresetn,
O => enb
);
\xpm_memory_base_inst_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"80FF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
I2 => xpm_memory_base_inst_i_5_n_0,
I3 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg\
);
\xpm_memory_base_inst_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(10),
I1 => \^reg_data_out_reg[3]_1\(9),
I2 => xpm_memory_base_inst_i_5_n_0,
I3 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg_0\
);
xpm_memory_base_inst_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
I2 => xpm_memory_base_inst_i_5_n_0,
I3 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg_1\
);
\xpm_memory_base_inst_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_wvalid,
I1 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I2 => s_axi_aresetn,
O => web(0)
);
xpm_memory_base_inst_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"EAAAAAAAAAAAAAAA"
)
port map (
I0 => bus2ip_rdce,
I1 => s_axi_wstrb(3),
I2 => s_axi_wstrb(2),
I3 => s_axi_wstrb(0),
I4 => s_axi_wstrb(1),
I5 => \^ping_pkt_lenth_reg[15]\,
O => xpm_memory_base_inst_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cdc_sync is
port (
scndry_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cdc_sync : entity is "cdc_sync";
end system_axi_ethernetlite_0_0_cdc_sync;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cdc_sync is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => SR(0),
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d3,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cdc_sync_0 is
port (
scndry_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cdc_sync_0 : entity is "cdc_sync";
end system_axi_ethernetlite_0_0_cdc_sync_0;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cdc_sync_0 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => SR(0),
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d3,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cdc_sync_12 is
port (
scndry_out : out STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cdc_sync_12 : entity is "cdc_sync";
end system_axi_ethernetlite_0_0_cdc_sync_12;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cdc_sync_12 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => SS(0),
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d3,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cdc_sync_7 is
port (
scndry_out : out STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cdc_sync_7 : entity is "cdc_sync";
end system_axi_ethernetlite_0_0_cdc_sync_7;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cdc_sync_7 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => phy_tx_clk,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized0\ is
port (
scndry_out : out STD_LOGIC;
prmry_in : in STD_LOGIC;
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized0\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized0\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized0\ is
signal s_level_out_d1_cdc_to : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized1\ is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
prmry_vect_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized1\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized1\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized1\ is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_vect_in(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_vect_in(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_vect_in(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_vect_in(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized2\ is
port (
scndry_out : out STD_LOGIC;
prmry_in : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized2\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized2\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized2\ is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized3\ is
port (
fifo_tx_en_reg : out STD_LOGIC;
scndry_out : in STD_LOGIC;
tx_en_i : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized3\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized3\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized3\ is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal tx_en_i_tx_clk : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => tx_en_i,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => tx_en_i_tx_clk,
R => '0'
);
fifo_tx_en_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => tx_en_i_tx_clk,
I1 => scndry_out,
O => fifo_tx_en_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized4\ is
port (
scndry_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized4\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized4\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized4\ is
signal s_level_out_d1_cdc_to : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => s_axi_aresetn,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cntr5bit is
port (
ifgp1_zero : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\thisState_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\thisState_reg[0]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cntr5bit : entity is "cntr5bit";
end system_axi_ethernetlite_0_0_cntr5bit;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cntr5bit is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \count_reg__0\ : STD_LOGIC_VECTOR ( 0 to 2 );
signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 2 );
signal zero_i_i_1_n_0 : STD_LOGIC;
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\count[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAB"
)
port map (
I0 => \thisState_reg[0]\,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \count_reg__0\(1),
I4 => \count_reg__0\(2),
I5 => \count_reg__0\(0),
O => p_0_in(4)
);
\count[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE01FE01FE010000"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \count_reg__0\(2),
I3 => \count_reg__0\(1),
I4 => \thisState_reg[1]\(1),
I5 => \thisState_reg[1]\(0),
O => p_0_in(3)
);
\count[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1E1E100"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg__0\(2),
I3 => \thisState_reg[1]\(1),
I4 => \thisState_reg[1]\(0),
O => p_0_in(2)
);
\count_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_0_in(4),
Q => \count_reg__0\(0),
S => s_axi_aresetn
);
\count_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_0_in(3),
Q => \count_reg__0\(1),
S => s_axi_aresetn
);
\count_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_0_in(2),
Q => \count_reg__0\(2),
S => s_axi_aresetn
);
\count_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^q\(1),
S => s_axi_aresetn
);
\count_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^q\(0),
S => s_axi_aresetn
);
zero_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg__0\(2),
I3 => \count_reg__0\(1),
I4 => \count_reg__0\(0),
O => zero_i_i_1_n_0
);
zero_i_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => zero_i_i_1_n_0,
Q => ifgp1_zero,
S => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cntr5bit_11 is
port (
ifgp2_zero : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\thisState_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\thisState_reg[0]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cntr5bit_11 : entity is "cntr5bit";
end system_axi_ethernetlite_0_0_cntr5bit_11;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cntr5bit_11 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \count[0]_i_2__0_n_0\ : STD_LOGIC;
signal \count_reg__0\ : STD_LOGIC_VECTOR ( 0 to 2 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \zero_i_i_1__0_n_0\ : STD_LOGIC;
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\count[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555400000001"
)
port map (
I0 => \thisState_reg[0]\,
I1 => \count_reg__0\(1),
I2 => \count_reg__0\(2),
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \count_reg__0\(0),
O => \count[0]_i_2__0_n_0\
);
\count[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF11111111F"
)
port map (
I0 => \thisState_reg[1]\(1),
I1 => \thisState_reg[1]\(0),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \count_reg__0\(2),
I5 => \count_reg__0\(1),
O => \p_0_in__0\(3)
);
\count[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1E1E100"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg__0\(2),
I3 => \thisState_reg[1]\(1),
I4 => \thisState_reg[1]\(0),
O => \p_0_in__0\(2)
);
\count_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \count[0]_i_2__0_n_0\,
Q => \count_reg__0\(0),
S => s_axi_aresetn
);
\count_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \p_0_in__0\(3),
Q => \count_reg__0\(1),
S => s_axi_aresetn
);
\count_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \p_0_in__0\(2),
Q => \count_reg__0\(2),
S => s_axi_aresetn
);
\count_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^q\(1),
S => s_axi_aresetn
);
\count_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^q\(0),
S => s_axi_aresetn
);
\zero_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg__0\(2),
I3 => \count_reg__0\(1),
I4 => \count_reg__0\(0),
O => \zero_i_i_1__0_n_0\
);
zero_i_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \zero_i_i_1__0_n_0\,
Q => ifgp2_zero,
S => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_crcgenrx is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
crcokdelay : out STD_LOGIC;
D_0 : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 6 downto 0 );
\gpr1.dout_i_reg[5]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpr1.dout_i_reg[2]\ : in STD_LOGIC;
crcokr1 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
rxCrcEn : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_crcgenrx : entity is "crcgenrx";
end system_axi_ethernetlite_0_0_crcgenrx;
architecture STRUCTURE of system_axi_ethernetlite_0_0_crcgenrx is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \crc_local_reg_n_0_[27]\ : STD_LOGIC;
signal crcokdelay_i_10_n_0 : STD_LOGIC;
signal crcokdelay_i_3_n_0 : STD_LOGIC;
signal crcokdelay_i_4_n_0 : STD_LOGIC;
signal crcokdelay_i_5_n_0 : STD_LOGIC;
signal crcokdelay_i_6_n_0 : STD_LOGIC;
signal crcokdelay_i_7_n_0 : STD_LOGIC;
signal crcokdelay_i_8_n_0 : STD_LOGIC;
signal crcokdelay_i_9_n_0 : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_19_in : STD_LOGIC;
signal p_20_in : STD_LOGIC;
signal p_21_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_24_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_26_in : STD_LOGIC;
signal p_27_in : STD_LOGIC;
signal p_28_in : STD_LOGIC;
signal p_29_in : STD_LOGIC;
signal p_30_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal parallel_crc : STD_LOGIC_VECTOR ( 29 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \crc_local[15]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \crc_local[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \crc_local[17]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \crc_local[18]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \crc_local[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \crc_local[22]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \crc_local[23]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \crc_local[27]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \crc_local[28]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \crc_local[29]_i_1\ : label is "soft_lutpair19";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\crc_local[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => p_11_in,
I1 => \^q\(8),
I2 => \gpr1.dout_i_reg[5]\(1),
I3 => \^q\(7),
I4 => \gpr1.dout_i_reg[5]\(2),
I5 => D(0),
O => parallel_crc(12)
);
\crc_local[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => p_12_in,
I1 => \^q\(8),
I2 => \gpr1.dout_i_reg[5]\(1),
I3 => \^q\(7),
I4 => \gpr1.dout_i_reg[5]\(2),
I5 => \gpr1.dout_i_reg[2]\,
O => parallel_crc(13)
);
\crc_local[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_13_in,
I1 => \gpr1.dout_i_reg[5]\(1),
I2 => \^q\(8),
I3 => \gpr1.dout_i_reg[5]\(0),
I4 => \^q\(9),
O => parallel_crc(14)
);
\crc_local[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_19_in,
I1 => \^q\(9),
I2 => \gpr1.dout_i_reg[5]\(0),
O => parallel_crc(15)
);
\crc_local[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_20_in,
I1 => \^q\(6),
I2 => \gpr1.dout_i_reg[5]\(3),
O => parallel_crc(16)
);
\crc_local[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_21_in,
I1 => \^q\(7),
I2 => \gpr1.dout_i_reg[5]\(2),
O => parallel_crc(17)
);
\crc_local[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_22_in,
I1 => \^q\(8),
I2 => \gpr1.dout_i_reg[5]\(1),
O => parallel_crc(18)
);
\crc_local[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_23_in,
I1 => \^q\(9),
I2 => \gpr1.dout_i_reg[5]\(0),
O => parallel_crc(19)
);
\crc_local[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^q\(7),
I1 => \gpr1.dout_i_reg[5]\(2),
I2 => \^q\(6),
I3 => \gpr1.dout_i_reg[5]\(3),
O => parallel_crc(1)
);
\crc_local[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_24_in,
I1 => \^q\(6),
I2 => \gpr1.dout_i_reg[5]\(3),
O => parallel_crc(22)
);
\crc_local[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_14_in,
I1 => \gpr1.dout_i_reg[5]\(3),
I2 => \^q\(6),
I3 => \gpr1.dout_i_reg[5]\(2),
I4 => \^q\(7),
O => parallel_crc(23)
);
\crc_local[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_15_in,
I1 => \gpr1.dout_i_reg[5]\(2),
I2 => \^q\(7),
I3 => \gpr1.dout_i_reg[5]\(1),
I4 => \^q\(8),
O => parallel_crc(24)
);
\crc_local[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_16_in,
I1 => \gpr1.dout_i_reg[5]\(1),
I2 => \^q\(8),
I3 => \gpr1.dout_i_reg[5]\(0),
I4 => \^q\(9),
O => parallel_crc(25)
);
\crc_local[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_17_in,
I1 => \gpr1.dout_i_reg[5]\(3),
I2 => \^q\(6),
I3 => \gpr1.dout_i_reg[5]\(0),
I4 => \^q\(9),
O => parallel_crc(26)
);
\crc_local[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_25_in,
I1 => \^q\(7),
I2 => \gpr1.dout_i_reg[5]\(2),
O => parallel_crc(27)
);
\crc_local[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_26_in,
I1 => \^q\(8),
I2 => \gpr1.dout_i_reg[5]\(1),
O => parallel_crc(28)
);
\crc_local[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_27_in,
I1 => \^q\(9),
I2 => \gpr1.dout_i_reg[5]\(0),
O => parallel_crc(29)
);
\crc_local[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(6),
I1 => \gpr1.dout_i_reg[5]\(3),
I2 => \gpr1.dout_i_reg[5]\(2),
I3 => \^q\(7),
I4 => \gpr1.dout_i_reg[5]\(1),
I5 => \^q\(8),
O => parallel_crc(2)
);
\crc_local[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(9),
I1 => \gpr1.dout_i_reg[5]\(0),
I2 => \gpr1.dout_i_reg[5]\(2),
I3 => \^q\(7),
I4 => \gpr1.dout_i_reg[5]\(1),
I5 => \^q\(8),
O => parallel_crc(3)
);
\crc_local[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_5_in,
I1 => \gpr1.dout_i_reg[5]\(2),
I2 => \^q\(7),
I3 => \gpr1.dout_i_reg[5]\(1),
I4 => \^q\(8),
O => parallel_crc(6)
);
\crc_local[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_8_in,
I1 => \gpr1.dout_i_reg[5]\(2),
I2 => \^q\(7),
I3 => \gpr1.dout_i_reg[5]\(1),
I4 => \^q\(8),
O => parallel_crc(9)
);
\crc_local_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^q\(0),
S => SS(0)
);
\crc_local_reg[10]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => p_13_in,
S => SS(0)
);
\crc_local_reg[11]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => p_19_in,
S => SS(0)
);
\crc_local_reg[12]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(12),
Q => p_20_in,
S => SS(0)
);
\crc_local_reg[13]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(13),
Q => p_21_in,
S => SS(0)
);
\crc_local_reg[14]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(14),
Q => p_22_in,
S => SS(0)
);
\crc_local_reg[15]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(15),
Q => p_23_in,
S => SS(0)
);
\crc_local_reg[16]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(16),
Q => p_28_in,
S => SS(0)
);
\crc_local_reg[17]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(17),
Q => p_29_in,
S => SS(0)
);
\crc_local_reg[18]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(18),
Q => p_24_in,
S => SS(0)
);
\crc_local_reg[19]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(19),
Q => p_14_in,
S => SS(0)
);
\crc_local_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(1),
Q => \^q\(1),
S => SS(0)
);
\crc_local_reg[20]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_28_in,
Q => p_15_in,
S => SS(0)
);
\crc_local_reg[21]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_29_in,
Q => p_16_in,
S => SS(0)
);
\crc_local_reg[22]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(22),
Q => p_17_in,
S => SS(0)
);
\crc_local_reg[23]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(23),
Q => p_25_in,
S => SS(0)
);
\crc_local_reg[24]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(24),
Q => p_26_in,
S => SS(0)
);
\crc_local_reg[25]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(25),
Q => p_27_in,
S => SS(0)
);
\crc_local_reg[26]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(26),
Q => p_30_in,
S => SS(0)
);
\crc_local_reg[27]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(27),
Q => \crc_local_reg_n_0_[27]\,
S => SS(0)
);
\crc_local_reg[28]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(28),
Q => \^q\(6),
S => SS(0)
);
\crc_local_reg[29]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(29),
Q => \^q\(7),
S => SS(0)
);
\crc_local_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(2),
Q => p_5_in,
S => SS(0)
);
\crc_local_reg[30]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_30_in,
Q => \^q\(8),
S => SS(0)
);
\crc_local_reg[31]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \crc_local_reg_n_0_[27]\,
Q => \^q\(9),
S => SS(0)
);
\crc_local_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(3),
Q => \^q\(2),
S => SS(0)
);
\crc_local_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^q\(3),
S => SS(0)
);
\crc_local_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => p_8_in,
S => SS(0)
);
\crc_local_reg[6]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(6),
Q => \^q\(4),
S => SS(0)
);
\crc_local_reg[7]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => \^q\(5),
S => SS(0)
);
\crc_local_reg[8]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => p_11_in,
S => SS(0)
);
\crc_local_reg[9]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(9),
Q => p_12_in,
S => SS(0)
);
crcokdelay_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB0000FFFFFFFF"
)
port map (
I0 => crcokdelay_i_3_n_0,
I1 => crcokdelay_i_4_n_0,
I2 => crcokdelay_i_5_n_0,
I3 => crcokdelay_i_6_n_0,
I4 => crcokr1,
I5 => s_axi_aresetn,
O => crcokdelay
);
crcokdelay_i_10: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => p_20_in,
I1 => p_23_in,
I2 => p_19_in,
I3 => p_30_in,
O => crcokdelay_i_10_n_0
);
crcokdelay_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040004"
)
port map (
I0 => crcokdelay_i_3_n_0,
I1 => crcokdelay_i_4_n_0,
I2 => crcokdelay_i_5_n_0,
I3 => crcokdelay_i_6_n_0,
I4 => rxCrcEn,
I5 => crcokr1,
O => D_0
);
crcokdelay_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_17_in,
I1 => p_25_in,
I2 => \^q\(7),
I3 => \crc_local_reg_n_0_[27]\,
I4 => crcokdelay_i_7_n_0,
O => crcokdelay_i_3_n_0
);
crcokdelay_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => p_14_in,
I1 => \^q\(8),
I2 => p_26_in,
I3 => p_11_in,
I4 => crcokdelay_i_8_n_0,
O => crcokdelay_i_4_n_0
);
crcokdelay_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_29_in,
I1 => p_15_in,
I2 => p_28_in,
I3 => p_12_in,
I4 => crcokdelay_i_9_n_0,
O => crcokdelay_i_5_n_0
);
crcokdelay_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF7FF"
)
port map (
I0 => p_24_in,
I1 => \^q\(1),
I2 => \^q\(6),
I3 => p_13_in,
I4 => crcokdelay_i_10_n_0,
O => crcokdelay_i_6_n_0
);
crcokdelay_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => p_8_in,
I1 => p_27_in,
I2 => \^q\(4),
I3 => p_16_in,
O => crcokdelay_i_7_n_0
);
crcokdelay_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
I2 => p_5_in,
I3 => \^q\(5),
O => crcokdelay_i_8_n_0
);
crcokdelay_i_9: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => \^q\(0),
I1 => p_22_in,
I2 => \^q\(9),
I3 => p_21_in,
O => crcokdelay_i_9_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_crcnibshiftreg is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
txCrcEn_reg : in STD_LOGIC;
\emac_tx_wr_data_d1_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_crcnibshiftreg : entity is "crcnibshiftreg";
end system_axi_ethernetlite_0_0_crcnibshiftreg;
architecture STRUCTURE of system_axi_ethernetlite_0_0_crcnibshiftreg is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \nibData[12]_i_1_n_0\ : STD_LOGIC;
signal \nibData[13]_i_1_n_0\ : STD_LOGIC;
signal \nibData[14]_i_1_n_0\ : STD_LOGIC;
signal \nibData[15]_i_1_n_0\ : STD_LOGIC;
signal \nibData[16]_i_1_n_0\ : STD_LOGIC;
signal \nibData[17]_i_1_n_0\ : STD_LOGIC;
signal \nibData[18]_i_1_n_0\ : STD_LOGIC;
signal \nibData[19]_i_1_n_0\ : STD_LOGIC;
signal \nibData[20]_i_1_n_0\ : STD_LOGIC;
signal \nibData[21]_i_1_n_0\ : STD_LOGIC;
signal \nibData[22]_i_1_n_0\ : STD_LOGIC;
signal \nibData[23]_i_1_n_0\ : STD_LOGIC;
signal \nibData[24]_i_1_n_0\ : STD_LOGIC;
signal \nibData[25]_i_1_n_0\ : STD_LOGIC;
signal \nibData[26]_i_1_n_0\ : STD_LOGIC;
signal \nibData[26]_i_2_n_0\ : STD_LOGIC;
signal \nibData[27]_i_1_n_0\ : STD_LOGIC;
signal \nibData[27]_i_2_n_0\ : STD_LOGIC;
signal \nibData[28]_i_1_n_0\ : STD_LOGIC;
signal \nibData[28]_i_2_n_0\ : STD_LOGIC;
signal \nibData[29]_i_1_n_0\ : STD_LOGIC;
signal \nibData[29]_i_2_n_0\ : STD_LOGIC;
signal \nibData[2]_i_1_n_0\ : STD_LOGIC;
signal \nibData[30]_i_1_n_0\ : STD_LOGIC;
signal \nibData[31]_i_3_n_0\ : STD_LOGIC;
signal \nibData[3]_i_1_n_0\ : STD_LOGIC;
signal \nibData[4]_i_1_n_0\ : STD_LOGIC;
signal \nibData[5]_i_1_n_0\ : STD_LOGIC;
signal \nibData[6]_i_1_n_0\ : STD_LOGIC;
signal \nibData[7]_i_1_n_0\ : STD_LOGIC;
signal \nibData[8]_i_1_n_0\ : STD_LOGIC;
signal \nibData[9]_i_1_n_0\ : STD_LOGIC;
signal \nibData_reg_n_0_[10]\ : STD_LOGIC;
signal \nibData_reg_n_0_[11]\ : STD_LOGIC;
signal \nibData_reg_n_0_[12]\ : STD_LOGIC;
signal \nibData_reg_n_0_[13]\ : STD_LOGIC;
signal \nibData_reg_n_0_[14]\ : STD_LOGIC;
signal \nibData_reg_n_0_[15]\ : STD_LOGIC;
signal \nibData_reg_n_0_[16]\ : STD_LOGIC;
signal \nibData_reg_n_0_[17]\ : STD_LOGIC;
signal \nibData_reg_n_0_[18]\ : STD_LOGIC;
signal \nibData_reg_n_0_[19]\ : STD_LOGIC;
signal \nibData_reg_n_0_[20]\ : STD_LOGIC;
signal \nibData_reg_n_0_[21]\ : STD_LOGIC;
signal \nibData_reg_n_0_[22]\ : STD_LOGIC;
signal \nibData_reg_n_0_[23]\ : STD_LOGIC;
signal \nibData_reg_n_0_[24]\ : STD_LOGIC;
signal \nibData_reg_n_0_[25]\ : STD_LOGIC;
signal \nibData_reg_n_0_[26]\ : STD_LOGIC;
signal \nibData_reg_n_0_[27]\ : STD_LOGIC;
signal \nibData_reg_n_0_[28]\ : STD_LOGIC;
signal \nibData_reg_n_0_[29]\ : STD_LOGIC;
signal \nibData_reg_n_0_[30]\ : STD_LOGIC;
signal \nibData_reg_n_0_[31]\ : STD_LOGIC;
signal \nibData_reg_n_0_[4]\ : STD_LOGIC;
signal \nibData_reg_n_0_[5]\ : STD_LOGIC;
signal \nibData_reg_n_0_[6]\ : STD_LOGIC;
signal \nibData_reg_n_0_[7]\ : STD_LOGIC;
signal \nibData_reg_n_0_[8]\ : STD_LOGIC;
signal \nibData_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \nibData[12]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \nibData[13]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \nibData[14]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \nibData[15]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \nibData[19]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \nibData[24]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \nibData[26]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \nibData[27]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \nibData[28]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \nibData[29]_i_2\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \nibData[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \nibData[30]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \nibData[31]_i_3\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \nibData[3]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \nibData[4]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \nibData[9]_i_1\ : label is "soft_lutpair49";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\nibData[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[16]\,
I1 => \^q\(0),
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => txCrcEn_reg,
O => \nibData[12]_i_1_n_0\
);
\nibData[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[17]\,
I1 => \^q\(1),
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => txCrcEn_reg,
O => \nibData[13]_i_1_n_0\
);
\nibData[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[18]\,
I1 => \^q\(2),
I2 => \emac_tx_wr_data_d1_reg[0]\(2),
I3 => txCrcEn_reg,
O => \nibData[14]_i_1_n_0\
);
\nibData[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[19]\,
I1 => \^q\(3),
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => txCrcEn_reg,
O => \nibData[15]_i_1_n_0\
);
\nibData[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[20]\,
I1 => \^q\(0),
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => txCrcEn_reg,
O => \nibData[16]_i_1_n_0\
);
\nibData[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A66A6AA66AA6A66A"
)
port map (
I0 => \nibData_reg_n_0_[21]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => \^q\(1),
I4 => \emac_tx_wr_data_d1_reg[0]\(0),
I5 => \^q\(0),
O => \nibData[17]_i_1_n_0\
);
\nibData[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[22]\,
I1 => \emac_tx_wr_data_d1_reg[0]\(2),
I2 => \^q\(2),
I3 => \nibData[27]_i_2_n_0\,
I4 => txCrcEn_reg,
O => \nibData[18]_i_1_n_0\
);
\nibData[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[23]\,
I1 => \nibData[26]_i_2_n_0\,
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => \^q\(1),
I4 => txCrcEn_reg,
O => \nibData[19]_i_1_n_0\
);
\nibData[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A66A6AA6"
)
port map (
I0 => \nibData_reg_n_0_[24]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => \^q\(0),
I4 => \nibData[26]_i_2_n_0\,
O => \nibData[20]_i_1_n_0\
);
\nibData[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[25]\,
I1 => \nibData[27]_i_2_n_0\,
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => \^q\(3),
I4 => txCrcEn_reg,
O => \nibData[21]_i_1_n_0\
);
\nibData[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96696996AAAAAAAA"
)
port map (
I0 => \nibData_reg_n_0_[26]\,
I1 => \emac_tx_wr_data_d1_reg[0]\(2),
I2 => \^q\(2),
I3 => \emac_tx_wr_data_d1_reg[0]\(1),
I4 => \^q\(1),
I5 => txCrcEn_reg,
O => \nibData[22]_i_1_n_0\
);
\nibData[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A66A6AA6"
)
port map (
I0 => \nibData_reg_n_0_[27]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => \^q\(0),
I4 => \nibData[26]_i_2_n_0\,
O => \nibData[23]_i_1_n_0\
);
\nibData[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[28]\,
I1 => \nibData[27]_i_2_n_0\,
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => \^q\(3),
I4 => txCrcEn_reg,
O => \nibData[24]_i_1_n_0\
);
\nibData[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96696996AAAAAAAA"
)
port map (
I0 => \nibData_reg_n_0_[29]\,
I1 => \emac_tx_wr_data_d1_reg[0]\(2),
I2 => \^q\(2),
I3 => \emac_tx_wr_data_d1_reg[0]\(1),
I4 => \^q\(1),
I5 => txCrcEn_reg,
O => \nibData[25]_i_1_n_0\
);
\nibData[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A66A6AA6"
)
port map (
I0 => \nibData_reg_n_0_[30]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => \^q\(0),
I4 => \nibData[26]_i_2_n_0\,
O => \nibData[26]_i_1_n_0\
);
\nibData[26]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \emac_tx_wr_data_d1_reg[0]\(3),
I1 => \^q\(3),
I2 => \emac_tx_wr_data_d1_reg[0]\(2),
I3 => \^q\(2),
O => \nibData[26]_i_2_n_0\
);
\nibData[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[31]\,
I1 => \nibData[27]_i_2_n_0\,
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => \^q\(3),
I4 => txCrcEn_reg,
O => \nibData[27]_i_1_n_0\
);
\nibData[27]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \emac_tx_wr_data_d1_reg[0]\(1),
I1 => \^q\(1),
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => \^q\(0),
O => \nibData[27]_i_2_n_0\
);
\nibData[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699600000000"
)
port map (
I0 => \nibData[28]_i_2_n_0\,
I1 => \emac_tx_wr_data_d1_reg[0]\(0),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \emac_tx_wr_data_d1_reg[0]\(2),
I5 => txCrcEn_reg,
O => \nibData[28]_i_1_n_0\
);
\nibData[28]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \emac_tx_wr_data_d1_reg[0]\(1),
O => \nibData[28]_i_2_n_0\
);
\nibData[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699600000000"
)
port map (
I0 => \^q\(1),
I1 => \emac_tx_wr_data_d1_reg[0]\(1),
I2 => \nibData[29]_i_2_n_0\,
I3 => \emac_tx_wr_data_d1_reg[0]\(2),
I4 => \^q\(2),
I5 => txCrcEn_reg,
O => \nibData[29]_i_1_n_0\
);
\nibData[29]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(3),
I1 => \emac_tx_wr_data_d1_reg[0]\(3),
O => \nibData[29]_i_2_n_0\
);
\nibData[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[6]\,
I1 => \^q\(0),
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => txCrcEn_reg,
O => \nibData[2]_i_1_n_0\
);
\nibData[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82282882"
)
port map (
I0 => txCrcEn_reg,
I1 => \^q\(2),
I2 => \emac_tx_wr_data_d1_reg[0]\(2),
I3 => \^q\(3),
I4 => \emac_tx_wr_data_d1_reg[0]\(3),
O => \nibData[30]_i_1_n_0\
);
\nibData[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \emac_tx_wr_data_d1_reg[0]\(3),
I1 => \^q\(3),
I2 => txCrcEn_reg,
O => \nibData[31]_i_3_n_0\
);
\nibData[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[7]\,
I1 => \^q\(1),
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => txCrcEn_reg,
O => \nibData[3]_i_1_n_0\
);
\nibData[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[8]\,
I1 => \^q\(2),
I2 => \emac_tx_wr_data_d1_reg[0]\(2),
I3 => txCrcEn_reg,
O => \nibData[4]_i_1_n_0\
);
\nibData[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A66A6AA66AA6A66A"
)
port map (
I0 => \nibData_reg_n_0_[9]\,
I1 => txCrcEn_reg,
I2 => \^q\(0),
I3 => \emac_tx_wr_data_d1_reg[0]\(0),
I4 => \emac_tx_wr_data_d1_reg[0]\(3),
I5 => \^q\(3),
O => \nibData[5]_i_1_n_0\
);
\nibData[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A66A6AA66AA6A66A"
)
port map (
I0 => \nibData_reg_n_0_[10]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => \^q\(1),
I4 => \emac_tx_wr_data_d1_reg[0]\(0),
I5 => \^q\(0),
O => \nibData[6]_i_1_n_0\
);
\nibData[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96696996AAAAAAAA"
)
port map (
I0 => \nibData_reg_n_0_[11]\,
I1 => \emac_tx_wr_data_d1_reg[0]\(2),
I2 => \^q\(2),
I3 => \emac_tx_wr_data_d1_reg[0]\(1),
I4 => \^q\(1),
I5 => txCrcEn_reg,
O => \nibData[7]_i_1_n_0\
);
\nibData[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A66A6AA66AA6A66A"
)
port map (
I0 => \nibData_reg_n_0_[12]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => \^q\(3),
I4 => \emac_tx_wr_data_d1_reg[0]\(2),
I5 => \^q\(2),
O => \nibData[8]_i_1_n_0\
);
\nibData[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[13]\,
I1 => \^q\(3),
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => txCrcEn_reg,
O => \nibData[9]_i_1_n_0\
);
\nibData_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData_reg_n_0_[4]\,
Q => \^q\(0),
R => SR(0)
);
\nibData_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData_reg_n_0_[14]\,
Q => \nibData_reg_n_0_[10]\,
R => SR(0)
);
\nibData_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData_reg_n_0_[15]\,
Q => \nibData_reg_n_0_[11]\,
R => SR(0)
);
\nibData_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[12]_i_1_n_0\,
Q => \nibData_reg_n_0_[12]\,
R => SR(0)
);
\nibData_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[13]_i_1_n_0\,
Q => \nibData_reg_n_0_[13]\,
R => SR(0)
);
\nibData_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[14]_i_1_n_0\,
Q => \nibData_reg_n_0_[14]\,
R => SR(0)
);
\nibData_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[15]_i_1_n_0\,
Q => \nibData_reg_n_0_[15]\,
R => SR(0)
);
\nibData_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[16]_i_1_n_0\,
Q => \nibData_reg_n_0_[16]\,
R => SR(0)
);
\nibData_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[17]_i_1_n_0\,
Q => \nibData_reg_n_0_[17]\,
R => SR(0)
);
\nibData_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[18]_i_1_n_0\,
Q => \nibData_reg_n_0_[18]\,
R => SR(0)
);
\nibData_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[19]_i_1_n_0\,
Q => \nibData_reg_n_0_[19]\,
R => SR(0)
);
\nibData_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData_reg_n_0_[5]\,
Q => \^q\(1),
R => SR(0)
);
\nibData_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[20]_i_1_n_0\,
Q => \nibData_reg_n_0_[20]\,
R => SR(0)
);
\nibData_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[21]_i_1_n_0\,
Q => \nibData_reg_n_0_[21]\,
R => SR(0)
);
\nibData_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[22]_i_1_n_0\,
Q => \nibData_reg_n_0_[22]\,
R => SR(0)
);
\nibData_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[23]_i_1_n_0\,
Q => \nibData_reg_n_0_[23]\,
R => SR(0)
);
\nibData_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[24]_i_1_n_0\,
Q => \nibData_reg_n_0_[24]\,
R => SR(0)
);
\nibData_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[25]_i_1_n_0\,
Q => \nibData_reg_n_0_[25]\,
R => SR(0)
);
\nibData_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[26]_i_1_n_0\,
Q => \nibData_reg_n_0_[26]\,
R => SR(0)
);
\nibData_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[27]_i_1_n_0\,
Q => \nibData_reg_n_0_[27]\,
R => SR(0)
);
\nibData_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[28]_i_1_n_0\,
Q => \nibData_reg_n_0_[28]\,
R => SR(0)
);
\nibData_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[29]_i_1_n_0\,
Q => \nibData_reg_n_0_[29]\,
R => SR(0)
);
\nibData_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[2]_i_1_n_0\,
Q => \^q\(2),
R => SR(0)
);
\nibData_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[30]_i_1_n_0\,
Q => \nibData_reg_n_0_[30]\,
R => SR(0)
);
\nibData_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[31]_i_3_n_0\,
Q => \nibData_reg_n_0_[31]\,
R => SR(0)
);
\nibData_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[3]_i_1_n_0\,
Q => \^q\(3),
R => SR(0)
);
\nibData_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[4]_i_1_n_0\,
Q => \nibData_reg_n_0_[4]\,
R => SR(0)
);
\nibData_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[5]_i_1_n_0\,
Q => \nibData_reg_n_0_[5]\,
R => SR(0)
);
\nibData_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[6]_i_1_n_0\,
Q => \nibData_reg_n_0_[6]\,
R => SR(0)
);
\nibData_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[7]_i_1_n_0\,
Q => \nibData_reg_n_0_[7]\,
R => SR(0)
);
\nibData_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[8]_i_1_n_0\,
Q => \nibData_reg_n_0_[8]\,
R => SR(0)
);
\nibData_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[9]_i_1_n_0\,
Q => \nibData_reg_n_0_[9]\,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_defer_state is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\count_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\count_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\count_reg[0]\ : out STD_LOGIC;
D13_out : out STD_LOGIC;
phy_crs_d2 : in STD_LOGIC;
tx_en_i : in STD_LOGIC;
ifgp1_zero : in STD_LOGIC;
ifgp2_zero : in STD_LOGIC;
tx_clk_reg_d3 : in STD_LOGIC;
tx_clk_reg_d2 : in STD_LOGIC;
\count_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\count_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
ldLngthCntr : in STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : in STD_LOGIC;
enblPreamble : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_defer_state : entity is "defer_state";
end system_axi_ethernetlite_0_0_defer_state;
architecture STRUCTURE of system_axi_ethernetlite_0_0_defer_state is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \thisState[0]_i_1_n_0\ : STD_LOGIC;
signal \thisState[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count[0]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \count[0]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \count[3]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \count[3]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \count[4]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \count[4]_i_1__0\ : label is "soft_lutpair55";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
STATE8A_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"80FF8080"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => ldLngthCntr,
I3 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\,
I4 => enblPreamble,
O => D13_out
);
\count[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000004000400FFFF"
)
port map (
I0 => ifgp2_zero,
I1 => ifgp1_zero,
I2 => tx_clk_reg_d3,
I3 => tx_clk_reg_d2,
I4 => \^q\(1),
I5 => \^q\(0),
O => E(0)
);
\count[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"001010FF"
)
port map (
I0 => ifgp1_zero,
I1 => tx_clk_reg_d3,
I2 => tx_clk_reg_d2,
I3 => \^q\(1),
I4 => \^q\(0),
O => \count_reg[4]\(0)
);
\count[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_reg[0]\
);
\count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E00E"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg[3]_0\(0),
I3 => \count_reg[3]_0\(1),
O => D(1)
);
\count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E00E"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg[3]_1\(0),
I3 => \count_reg[3]_1\(1),
O => \count_reg[3]\(1)
);
\count[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => \count_reg[3]_0\(0),
I1 => \^q\(1),
I2 => \^q\(0),
O => D(0)
);
\count[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => \count_reg[3]_1\(0),
I1 => \^q\(1),
I2 => \^q\(0),
O => \count_reg[3]\(0)
);
\thisState[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3737040400CC00CF"
)
port map (
I0 => phy_crs_d2,
I1 => \^q\(0),
I2 => tx_en_i,
I3 => ifgp1_zero,
I4 => ifgp2_zero,
I5 => \^q\(1),
O => \thisState[0]_i_1_n_0\
);
\thisState[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3704CCCC"
)
port map (
I0 => phy_crs_d2,
I1 => \^q\(1),
I2 => tx_en_i,
I3 => ifgp1_zero,
I4 => \^q\(0),
O => \thisState[1]_i_1_n_0\
);
\thisState_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \thisState[0]_i_1_n_0\,
Q => \^q\(0),
R => s_axi_aresetn
);
\thisState_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \thisState[1]_i_1_n_0\,
Q => \^q\(1),
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_ld_arith_reg is
port (
STATE13A : out STD_LOGIC_VECTOR ( 0 to 0 );
\txNibbleCnt_pad_reg[11]\ : out STD_LOGIC;
D21_out : out STD_LOGIC;
STATE13A_0 : out STD_LOGIC;
enblData : in STD_LOGIC;
S : in STD_LOGIC;
txComboNibbleCntRst : in STD_LOGIC;
CE : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\tx_packet_length_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
checkBusFifoFull : in STD_LOGIC;
\out\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_ld_arith_reg : entity is "ld_arith_reg";
end system_axi_ethernetlite_0_0_ld_arith_reg;
architecture STRUCTURE of system_axi_ethernetlite_0_0_ld_arith_reg is
signal \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[10].MUXCY_i1_i_3_n_0\ : STD_LOGIC;
signal \PERBIT_GEN[10].MUXCY_i1_i_4_n_0\ : STD_LOGIC;
signal \PERBIT_GEN[10].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[3].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[4].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[5].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[6].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[7].MUXCY_i1_i_2_n_0\ : STD_LOGIC;
signal \PERBIT_GEN[7].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[8].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[9].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \^state13a\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^state13a_0\ : STD_LOGIC;
signal STATE13A_i_2_n_0 : STD_LOGIC;
signal STATE13A_i_3_n_0 : STD_LOGIC;
signal cry : STD_LOGIC_VECTOR ( 11 downto 1 );
signal currentTxNibbleCnt : STD_LOGIC_VECTOR ( 0 to 10 );
signal gen_cry_kill_n_0 : STD_LOGIC;
signal gen_cry_kill_n_1 : STD_LOGIC;
signal gen_cry_kill_n_10 : STD_LOGIC;
signal gen_cry_kill_n_2 : STD_LOGIC;
signal gen_cry_kill_n_3 : STD_LOGIC;
signal gen_cry_kill_n_4 : STD_LOGIC;
signal gen_cry_kill_n_5 : STD_LOGIC;
signal gen_cry_kill_n_6 : STD_LOGIC;
signal gen_cry_kill_n_7 : STD_LOGIC;
signal gen_cry_kill_n_8 : STD_LOGIC;
signal gen_cry_kill_n_9 : STD_LOGIC;
signal \^txnibblecnt_pad_reg[11]\ : STD_LOGIC;
signal xorcy_out_0 : STD_LOGIC;
signal xorcy_out_1 : STD_LOGIC;
signal xorcy_out_10 : STD_LOGIC;
signal xorcy_out_11 : STD_LOGIC;
signal xorcy_out_2 : STD_LOGIC;
signal xorcy_out_3 : STD_LOGIC;
signal xorcy_out_4 : STD_LOGIC;
signal xorcy_out_5 : STD_LOGIC;
signal xorcy_out_6 : STD_LOGIC;
signal xorcy_out_7 : STD_LOGIC;
signal xorcy_out_8 : STD_LOGIC;
signal xorcy_out_9 : STD_LOGIC;
signal \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \PERBIT_GEN[0].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[10].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[10].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[10].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[10].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[11].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[11].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[11].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[11].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[11].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[1].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[1].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[1].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[2].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[2].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[2].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[3].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[3].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[3].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[3].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[3].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[4].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[4].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[4].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[4].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[5].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[5].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[5].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[5].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[6].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[6].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[6].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[6].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[7].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[7].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[7].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[7].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[7].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[7].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[8].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[8].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[8].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[9].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[9].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[9].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[9].MULT_AND_i1\ : label is "PRIMITIVE";
begin
STATE13A(0) <= \^state13a\(0);
STATE13A_0 <= \^state13a_0\;
\txNibbleCnt_pad_reg[11]\ <= \^txnibblecnt_pad_reg[11]\;
\PERBIT_GEN[0].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_11,
Q => currentTxNibbleCnt(0),
R => txComboNibbleCntRst
);
\PERBIT_GEN[0].XORCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(10),
I1 => currentTxNibbleCnt(0),
I2 => enblData,
O => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[10].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_1,
Q => currentTxNibbleCnt(10),
R => txComboNibbleCntRst
);
\PERBIT_GEN[10].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(10),
I1 => enblData,
O => gen_cry_kill_n_1
);
\PERBIT_GEN[10].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F44"
)
port map (
I0 => \^txnibblecnt_pad_reg[11]\,
I1 => \tx_packet_length_reg[15]\(0),
I2 => currentTxNibbleCnt(10),
I3 => enblData,
O => \PERBIT_GEN[10].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[10].MUXCY_i1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \PERBIT_GEN[10].MUXCY_i1_i_3_n_0\,
I1 => \tx_packet_length_reg[15]\(9),
I2 => \tx_packet_length_reg[15]\(11),
I3 => \tx_packet_length_reg[15]\(15),
I4 => \tx_packet_length_reg[15]\(7),
I5 => \PERBIT_GEN[10].MUXCY_i1_i_4_n_0\,
O => \^txnibblecnt_pad_reg[11]\
);
\PERBIT_GEN[10].MUXCY_i1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \tx_packet_length_reg[15]\(8),
I1 => \tx_packet_length_reg[15]\(13),
I2 => \tx_packet_length_reg[15]\(14),
I3 => \tx_packet_length_reg[15]\(10),
I4 => \tx_packet_length_reg[15]\(6),
I5 => \tx_packet_length_reg[15]\(12),
O => \PERBIT_GEN[10].MUXCY_i1_i_3_n_0\
);
\PERBIT_GEN[10].MUXCY_i1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000000000000000"
)
port map (
I0 => \tx_packet_length_reg[15]\(0),
I1 => \tx_packet_length_reg[15]\(1),
I2 => \tx_packet_length_reg[15]\(4),
I3 => \tx_packet_length_reg[15]\(3),
I4 => \tx_packet_length_reg[15]\(5),
I5 => \tx_packet_length_reg[15]\(2),
O => \PERBIT_GEN[10].MUXCY_i1_i_4_n_0\
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_0,
Q => \^state13a\(0),
R => txComboNibbleCntRst
);
\PERBIT_GEN[11].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state13a\(0),
I1 => enblData,
O => gen_cry_kill_n_0
);
\PERBIT_GEN[11].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 0) => cry(4 downto 1),
CYINIT => enblData,
DI(3) => gen_cry_kill_n_3,
DI(2) => gen_cry_kill_n_2,
DI(1) => gen_cry_kill_n_1,
DI(0) => gen_cry_kill_n_0,
O(3) => xorcy_out_3,
O(2) => xorcy_out_2,
O(1) => xorcy_out_1,
O(0) => xorcy_out_0,
S(3) => \PERBIT_GEN[8].Q_I_GEN_SUB.q_i_ns_reg\,
S(2) => \PERBIT_GEN[9].Q_I_GEN_SUB.q_i_ns_reg\,
S(1) => \PERBIT_GEN[10].Q_I_GEN_SUB.q_i_ns_reg\,
S(0) => S
);
\PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_10,
Q => currentTxNibbleCnt(1),
R => txComboNibbleCntRst
);
\PERBIT_GEN[1].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(1),
I1 => enblData,
O => gen_cry_kill_n_10
);
\PERBIT_GEN[1].MUXCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(9),
I1 => currentTxNibbleCnt(1),
I2 => enblData,
O => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_9,
Q => currentTxNibbleCnt(2),
R => txComboNibbleCntRst
);
\PERBIT_GEN[2].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(2),
I1 => enblData,
O => gen_cry_kill_n_9
);
\PERBIT_GEN[2].MUXCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(8),
I1 => currentTxNibbleCnt(2),
I2 => enblData,
O => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_8,
Q => currentTxNibbleCnt(3),
R => txComboNibbleCntRst
);
\PERBIT_GEN[3].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(3),
I1 => enblData,
O => gen_cry_kill_n_8
);
\PERBIT_GEN[3].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => cry(8),
CO(3) => \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_CO_UNCONNECTED\(3),
CO(2 downto 0) => cry(11 downto 9),
CYINIT => '0',
DI(3) => \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_DI_UNCONNECTED\(3),
DI(2) => gen_cry_kill_n_10,
DI(1) => gen_cry_kill_n_9,
DI(0) => gen_cry_kill_n_8,
O(3) => xorcy_out_11,
O(2) => xorcy_out_10,
O(1) => xorcy_out_9,
O(0) => xorcy_out_8,
S(3) => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\,
S(2) => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\,
S(1) => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\,
S(0) => \PERBIT_GEN[3].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[3].MUXCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(7),
I1 => currentTxNibbleCnt(3),
I2 => enblData,
O => \PERBIT_GEN[3].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[4].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_7,
Q => currentTxNibbleCnt(4),
R => txComboNibbleCntRst
);
\PERBIT_GEN[4].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(4),
I1 => enblData,
O => gen_cry_kill_n_7
);
\PERBIT_GEN[4].MUXCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(6),
I1 => currentTxNibbleCnt(4),
I2 => enblData,
O => \PERBIT_GEN[4].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[5].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_6,
Q => currentTxNibbleCnt(5),
R => txComboNibbleCntRst
);
\PERBIT_GEN[5].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(5),
I1 => enblData,
O => gen_cry_kill_n_6
);
\PERBIT_GEN[5].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FEE"
)
port map (
I0 => \tx_packet_length_reg[15]\(5),
I1 => \^txnibblecnt_pad_reg[11]\,
I2 => currentTxNibbleCnt(5),
I3 => enblData,
O => \PERBIT_GEN[5].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[6].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_5,
Q => currentTxNibbleCnt(6),
R => txComboNibbleCntRst
);
\PERBIT_GEN[6].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(6),
I1 => enblData,
O => gen_cry_kill_n_5
);
\PERBIT_GEN[6].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FEE"
)
port map (
I0 => \tx_packet_length_reg[15]\(4),
I1 => \^txnibblecnt_pad_reg[11]\,
I2 => currentTxNibbleCnt(6),
I3 => enblData,
O => \PERBIT_GEN[6].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[7].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_4,
Q => currentTxNibbleCnt(7),
R => txComboNibbleCntRst
);
\PERBIT_GEN[7].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(7),
I1 => enblData,
O => gen_cry_kill_n_4
);
\PERBIT_GEN[7].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => cry(4),
CO(3 downto 0) => cry(8 downto 5),
CYINIT => '0',
DI(3) => gen_cry_kill_n_7,
DI(2) => gen_cry_kill_n_6,
DI(1) => gen_cry_kill_n_5,
DI(0) => gen_cry_kill_n_4,
O(3) => xorcy_out_7,
O(2) => xorcy_out_6,
O(1) => xorcy_out_5,
O(0) => xorcy_out_4,
S(3) => \PERBIT_GEN[4].Q_I_GEN_SUB.q_i_ns_reg\,
S(2) => \PERBIT_GEN[5].Q_I_GEN_SUB.q_i_ns_reg\,
S(1) => \PERBIT_GEN[6].Q_I_GEN_SUB.q_i_ns_reg\,
S(0) => \PERBIT_GEN[7].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[7].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FEE"
)
port map (
I0 => \tx_packet_length_reg[15]\(3),
I1 => \PERBIT_GEN[7].MUXCY_i1_i_2_n_0\,
I2 => currentTxNibbleCnt(7),
I3 => enblData,
O => \PERBIT_GEN[7].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[7].MUXCY_i1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \tx_packet_length_reg[15]\(7),
I1 => \tx_packet_length_reg[15]\(15),
I2 => \tx_packet_length_reg[15]\(11),
I3 => \tx_packet_length_reg[15]\(9),
I4 => \PERBIT_GEN[10].MUXCY_i1_i_3_n_0\,
O => \PERBIT_GEN[7].MUXCY_i1_i_2_n_0\
);
\PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_3,
Q => currentTxNibbleCnt(8),
R => txComboNibbleCntRst
);
\PERBIT_GEN[8].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(8),
I1 => enblData,
O => gen_cry_kill_n_3
);
\PERBIT_GEN[8].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FEE"
)
port map (
I0 => \tx_packet_length_reg[15]\(2),
I1 => \^txnibblecnt_pad_reg[11]\,
I2 => currentTxNibbleCnt(8),
I3 => enblData,
O => \PERBIT_GEN[8].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[9].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_2,
Q => currentTxNibbleCnt(9),
R => txComboNibbleCntRst
);
\PERBIT_GEN[9].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(9),
I1 => enblData,
O => gen_cry_kill_n_2
);
\PERBIT_GEN[9].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5530"
)
port map (
I0 => currentTxNibbleCnt(9),
I1 => \^txnibblecnt_pad_reg[11]\,
I2 => \tx_packet_length_reg[15]\(1),
I3 => enblData,
O => \PERBIT_GEN[9].Q_I_GEN_SUB.q_i_ns_reg\
);
STATE12A_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state13a_0\,
I1 => checkBusFifoFull,
I2 => \out\,
O => D21_out
);
STATE13A_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => STATE13A_i_2_n_0,
I1 => STATE13A_i_3_n_0,
I2 => currentTxNibbleCnt(8),
I3 => currentTxNibbleCnt(1),
I4 => currentTxNibbleCnt(2),
O => \^state13a_0\
);
STATE13A_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => currentTxNibbleCnt(3),
I1 => enblData,
I2 => currentTxNibbleCnt(0),
I3 => \^state13a\(0),
I4 => currentTxNibbleCnt(7),
I5 => currentTxNibbleCnt(6),
O => STATE13A_i_2_n_0
);
STATE13A_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => currentTxNibbleCnt(4),
I1 => currentTxNibbleCnt(10),
I2 => currentTxNibbleCnt(5),
I3 => currentTxNibbleCnt(9),
O => STATE13A_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\ is
port (
currentTxBusFifoWrCnt : out STD_LOGIC_VECTOR ( 3 downto 0 );
STATE11A : out STD_LOGIC;
STATE9A : out STD_LOGIC;
emac_tx_wr_i : in STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\ : in STD_LOGIC;
\PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ : in STD_LOGIC;
\PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ : in STD_LOGIC;
\PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ : in STD_LOGIC;
txComboBusFifoWrCntRst : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\ : entity is "ld_arith_reg";
end \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\ is
signal O : STD_LOGIC;
signal \PERBIT_GEN[10].MUXCY_i1_n_0\ : STD_LOGIC;
signal \PERBIT_GEN[9].MUXCY_i1_n_0\ : STD_LOGIC;
signal \^currenttxbusfifowrcnt\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal gen_cry_kill_n_0 : STD_LOGIC;
signal gen_cry_kill_n_1 : STD_LOGIC;
signal gen_cry_kill_n_2 : STD_LOGIC;
signal xorcy_out_0 : STD_LOGIC;
signal xorcy_out_1 : STD_LOGIC;
signal xorcy_out_2 : STD_LOGIC;
signal xorcy_out_3 : STD_LOGIC;
signal \NLW_PERBIT_GEN[11].MUXCY_i1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_PERBIT_GEN[11].MUXCY_i1_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \PERBIT_GEN[10].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[10].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[10].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[10].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[11].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[11].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[11].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[11].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[11].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[9].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[9].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[9].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[9].MULT_AND_i1\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of STATE10A_i_2 : label is "soft_lutpair56";
attribute SOFT_HLUTNM of STATE8A_i_2 : label is "soft_lutpair56";
begin
currentTxBusFifoWrCnt(3 downto 0) <= \^currenttxbusfifowrcnt\(3 downto 0);
\PERBIT_GEN[10].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => emac_tx_wr_i,
D => xorcy_out_1,
Q => \^currenttxbusfifowrcnt\(1),
R => txComboBusFifoWrCntRst
);
\PERBIT_GEN[10].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^currenttxbusfifowrcnt\(1),
I1 => emac_tx_wr_i,
O => gen_cry_kill_n_1
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => emac_tx_wr_i,
D => xorcy_out_0,
Q => \^currenttxbusfifowrcnt\(0),
R => txComboBusFifoWrCntRst
);
\PERBIT_GEN[11].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^currenttxbusfifowrcnt\(0),
I1 => emac_tx_wr_i,
O => gen_cry_kill_n_0
);
\PERBIT_GEN[11].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_PERBIT_GEN[11].MUXCY_i1_CARRY4_CO_UNCONNECTED\(3),
CO(2) => \PERBIT_GEN[9].MUXCY_i1_n_0\,
CO(1) => \PERBIT_GEN[10].MUXCY_i1_n_0\,
CO(0) => O,
CYINIT => '0',
DI(3) => \NLW_PERBIT_GEN[11].MUXCY_i1_CARRY4_DI_UNCONNECTED\(3),
DI(2) => gen_cry_kill_n_2,
DI(1) => gen_cry_kill_n_1,
DI(0) => gen_cry_kill_n_0,
O(3) => xorcy_out_3,
O(2) => xorcy_out_2,
O(1) => xorcy_out_1,
O(0) => xorcy_out_0,
S(3) => \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\,
S(2) => \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\,
S(1) => \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\,
S(0) => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\
);
\PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => emac_tx_wr_i,
D => xorcy_out_3,
Q => \^currenttxbusfifowrcnt\(3),
R => txComboBusFifoWrCntRst
);
\PERBIT_GEN[9].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => emac_tx_wr_i,
D => xorcy_out_2,
Q => \^currenttxbusfifowrcnt\(2),
R => txComboBusFifoWrCntRst
);
\PERBIT_GEN[9].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^currenttxbusfifowrcnt\(2),
I1 => emac_tx_wr_i,
O => gen_cry_kill_n_2
);
STATE10A_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^currenttxbusfifowrcnt\(0),
I1 => \^currenttxbusfifowrcnt\(1),
I2 => \^currenttxbusfifowrcnt\(2),
I3 => \^currenttxbusfifowrcnt\(3),
O => STATE11A
);
STATE8A_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^currenttxbusfifowrcnt\(0),
I1 => \^currenttxbusfifowrcnt\(1),
I2 => \^currenttxbusfifowrcnt\(2),
I3 => \^currenttxbusfifowrcnt\(3),
O => STATE9A
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\ is
port (
crcCnt : out STD_LOGIC_VECTOR ( 0 to 3 );
DIA : out STD_LOGIC_VECTOR ( 0 to 0 );
STATE15A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
enblCRC : in STD_LOGIC;
S : in STD_LOGIC;
\PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ : in STD_LOGIC;
\PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ : in STD_LOGIC;
\PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
CE : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_en_i : in STD_LOGIC;
checkBusFifoFullCrc : in STD_LOGIC;
\out\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\ : entity is "ld_arith_reg";
end \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\ is
signal \^crccnt\ : STD_LOGIC_VECTOR ( 0 to 3 );
signal cry : STD_LOGIC_VECTOR ( 3 downto 1 );
signal gen_cry_kill_n_0 : STD_LOGIC;
signal gen_cry_kill_n_1 : STD_LOGIC;
signal gen_cry_kill_n_2 : STD_LOGIC;
signal xorcy_out_0 : STD_LOGIC;
signal xorcy_out_1 : STD_LOGIC;
signal xorcy_out_2 : STD_LOGIC;
signal xorcy_out_3 : STD_LOGIC;
signal \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[1].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[1].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[1].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[2].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[2].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[2].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[3].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[3].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[3].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[3].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[3].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
begin
crcCnt(0 to 3) <= \^crccnt\(0 to 3);
\PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1\: unisim.vcomponents.FDSE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_S_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_3,
Q => \^crccnt\(0),
S => s_axi_aresetn
);
\PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_2,
Q => \^crccnt\(1),
R => s_axi_aresetn
);
\PERBIT_GEN[1].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^crccnt\(1),
I1 => enblCRC,
O => gen_cry_kill_n_2
);
\PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_1,
Q => \^crccnt\(2),
R => s_axi_aresetn
);
\PERBIT_GEN[2].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^crccnt\(2),
I1 => enblCRC,
O => gen_cry_kill_n_1
);
\PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_0,
Q => \^crccnt\(3),
R => s_axi_aresetn
);
\PERBIT_GEN[3].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^crccnt\(3),
I1 => enblCRC,
O => gen_cry_kill_n_0
);
\PERBIT_GEN[3].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_CO_UNCONNECTED\(3),
CO(2 downto 0) => cry(3 downto 1),
CYINIT => enblCRC,
DI(3) => \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_DI_UNCONNECTED\(3),
DI(2) => gen_cry_kill_n_2,
DI(1) => gen_cry_kill_n_1,
DI(0) => gen_cry_kill_n_0,
O(3) => xorcy_out_3,
O(2) => xorcy_out_2,
O(1) => xorcy_out_1,
O(0) => xorcy_out_0,
S(3) => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\,
S(2) => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\,
S(1) => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\,
S(0) => S
);
RAM_reg_0_15_0_5_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA8AAAAAAAA"
)
port map (
I0 => tx_en_i,
I1 => \^crccnt\(0),
I2 => \^crccnt\(3),
I3 => \^crccnt\(1),
I4 => \^crccnt\(2),
I5 => checkBusFifoFullCrc,
O => DIA(0)
);
STATE15A_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0000"
)
port map (
I0 => \^crccnt\(2),
I1 => \^crccnt\(1),
I2 => \^crccnt\(3),
I3 => \^crccnt\(0),
I4 => checkBusFifoFullCrc,
I5 => \out\,
O => STATE15A
);
STATE16A_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => checkBusFifoFullCrc,
I1 => \^crccnt\(2),
I2 => \^crccnt\(1),
I3 => \^crccnt\(3),
I4 => \^crccnt\(0),
O => \gic0.gc0.count_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_mdio_if is
port (
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 10 downto 0 );
\MDIO_GEN.mdio_req_i_reg\ : out STD_LOGIC;
prmry_in : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\MDIO_GEN.mdio_clk_i_reg\ : in STD_LOGIC;
phy_mdio_i : in STD_LOGIC;
p_6_in : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\AXI4_LITE_IF_GEN.read_in_prog_reg_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_req_i_reg_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\MDIO_GEN.mdio_wr_data_reg_reg[1]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\ : in STD_LOGIC;
mdio_en_i : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[7]\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
p_19_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_mdio_if : entity is "mdio_if";
end system_axi_ethernetlite_0_0_mdio_if;
architecture STRUCTURE of system_axi_ethernetlite_0_0_mdio_if is
signal \FSM_sequential_mdio_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_mdio_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_mdio_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_mdio_state[3]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[10].MDIO_RD_DATA[10]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[11].MDIO_RD_DATA[11]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[13].MDIO_RD_DATA[13]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[14].MDIO_RD_DATA[14]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA[15]_i_1_n_0\ : STD_LOGIC;
signal \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[5].MDIO_RD_DATA[5]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[6].MDIO_RD_DATA[6]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[7].MDIO_RD_DATA[7]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_3_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[0]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[10]_i_3_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[2]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[3]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[4]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[5]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[6]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[8]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[9]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_req_i_i_2_n_0\ : STD_LOGIC;
signal PHY_MDIO_O_i_10_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_11_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_12_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_13_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_1_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_2_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_3_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_4_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_5_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_6_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_7_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_8_n_0 : STD_LOGIC;
signal PHY_MDIO_O_reg_i_9_n_0 : STD_LOGIC;
signal PHY_MDIO_T_i_1_n_0 : STD_LOGIC;
signal clk_cnt : STD_LOGIC;
signal \clk_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \clk_cnt[5]_i_3_n_0\ : STD_LOGIC;
signal \clk_cnt[5]_i_4_n_0\ : STD_LOGIC;
signal \clk_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal data : STD_LOGIC_VECTOR ( 4 downto 1 );
signal ld_cnt_data_cmb : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \ld_cnt_data_reg[4]_i_1_n_0\ : STD_LOGIC;
signal ld_cnt_en_cmb : STD_LOGIC;
signal ld_cnt_en_reg : STD_LOGIC;
signal ld_cnt_en_reg_i_2_n_0 : STD_LOGIC;
signal mdio_clk_reg : STD_LOGIC;
signal mdio_done_i : STD_LOGIC;
signal mdio_en_reg : STD_LOGIC;
signal mdio_en_reg_i_1_n_0 : STD_LOGIC;
signal mdio_idle_i_1_n_0 : STD_LOGIC;
signal mdio_idle_i_3_n_0 : STD_LOGIC;
signal mdio_idle_reg_n_0 : STD_LOGIC;
signal mdio_in_reg1 : STD_LOGIC;
signal mdio_in_reg2 : STD_LOGIC;
signal mdio_rd_data_reg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal mdio_state : STD_LOGIC;
signal \mdio_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \mdio_state__0\ : signal is "yes";
signal mdio_t_comb : STD_LOGIC;
signal next_state : STD_LOGIC;
signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^phy_mdio_o\ : STD_LOGIC;
signal \^phy_mdio_t\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_mdio_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_mdio_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_mdio_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_sequential_mdio_state_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[2]_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[4]_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[5]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[6]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[8]_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[9]_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of PHY_MDIO_O_i_4 : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \clk_cnt[0]_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \clk_cnt[1]_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \clk_cnt[2]_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \clk_cnt[5]_i_4\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of mdio_en_reg_i_1 : label is "soft_lutpair83";
attribute SOFT_HLUTNM of mdio_idle_i_3 : label is "soft_lutpair83";
begin
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\(4 downto 0) <= \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(4 downto 0);
phy_mdio_o <= \^phy_mdio_o\;
phy_mdio_t <= \^phy_mdio_t\;
\FSM_sequential_mdio_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10001F1F"
)
port map (
I0 => \mdio_state__0\(2),
I1 => \mdio_state__0\(1),
I2 => \mdio_state__0\(3),
I3 => p_6_in(10),
I4 => \mdio_state__0\(0),
O => \FSM_sequential_mdio_state[0]_i_1_n_0\
);
\FSM_sequential_mdio_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"112A"
)
port map (
I0 => \mdio_state__0\(0),
I1 => \mdio_state__0\(3),
I2 => \mdio_state__0\(2),
I3 => \mdio_state__0\(1),
O => \FSM_sequential_mdio_state[1]_i_1_n_0\
);
\FSM_sequential_mdio_state[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3464"
)
port map (
I0 => \mdio_state__0\(3),
I1 => \mdio_state__0\(2),
I2 => \mdio_state__0\(1),
I3 => \mdio_state__0\(0),
O => \FSM_sequential_mdio_state[2]_i_1_n_0\
);
\FSM_sequential_mdio_state[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => next_state,
I1 => mdio_clk_reg,
I2 => \MDIO_GEN.mdio_clk_i_reg\,
O => mdio_state
);
\FSM_sequential_mdio_state[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F80"
)
port map (
I0 => \mdio_state__0\(1),
I1 => \mdio_state__0\(0),
I2 => \mdio_state__0\(2),
I3 => \mdio_state__0\(3),
O => \FSM_sequential_mdio_state[3]_i_2_n_0\
);
\FSM_sequential_mdio_state[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F167E563F167F57"
)
port map (
I0 => \mdio_state__0\(1),
I1 => \mdio_state__0\(3),
I2 => \mdio_state__0\(2),
I3 => ld_cnt_en_reg_i_2_n_0,
I4 => \mdio_state__0\(0),
I5 => mdio_idle_reg_n_0,
O => next_state
);
\FSM_sequential_mdio_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => mdio_state,
D => \FSM_sequential_mdio_state[0]_i_1_n_0\,
Q => \mdio_state__0\(0),
R => prmry_in
);
\FSM_sequential_mdio_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => mdio_state,
D => \FSM_sequential_mdio_state[1]_i_1_n_0\,
Q => \mdio_state__0\(1),
R => prmry_in
);
\FSM_sequential_mdio_state_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => mdio_state,
D => \FSM_sequential_mdio_state[2]_i_1_n_0\,
Q => \mdio_state__0\(2),
R => prmry_in
);
\FSM_sequential_mdio_state_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => mdio_state,
D => \FSM_sequential_mdio_state[3]_i_2_n_0\,
Q => \mdio_state__0\(3),
R => prmry_in
);
\MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => ld_cnt_en_reg_i_2_n_0,
I3 => mdio_clk_reg,
I4 => \MDIO_GEN.mdio_clk_i_reg\,
I5 => mdio_rd_data_reg(0),
O => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \mdio_state__0\(3),
I1 => \mdio_state__0\(2),
I2 => \mdio_state__0\(0),
I3 => \mdio_state__0\(1),
O => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[0].MDIO_RD_DATA_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_1_n_0\,
Q => mdio_rd_data_reg(0),
R => prmry_in
);
\MDIO_CAPTURE_DATA[10].MDIO_RD_DATA[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(10),
O => \MDIO_CAPTURE_DATA[10].MDIO_RD_DATA[10]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[10].MDIO_RD_DATA_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[10].MDIO_RD_DATA[10]_i_1_n_0\,
Q => mdio_rd_data_reg(10),
R => prmry_in
);
\MDIO_CAPTURE_DATA[11].MDIO_RD_DATA[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(0),
O => \MDIO_CAPTURE_DATA[11].MDIO_RD_DATA[11]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[11].MDIO_RD_DATA_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[11].MDIO_RD_DATA[11]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(0),
R => prmry_in
);
\MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \clk_cnt[5]_i_4_n_0\,
I3 => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(1),
O => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FDFF"
)
port map (
I0 => \clk_cnt_reg__0\(3),
I1 => \clk_cnt_reg__0\(4),
I2 => \clk_cnt_reg__0\(5),
I3 => \clk_cnt_reg__0\(2),
O => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[12].MDIO_RD_DATA_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(1),
R => prmry_in
);
\MDIO_CAPTURE_DATA[13].MDIO_RD_DATA[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(2),
O => \MDIO_CAPTURE_DATA[13].MDIO_RD_DATA[13]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[13].MDIO_RD_DATA_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[13].MDIO_RD_DATA[13]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(2),
R => prmry_in
);
\MDIO_CAPTURE_DATA[14].MDIO_RD_DATA[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(3),
O => \MDIO_CAPTURE_DATA[14].MDIO_RD_DATA[14]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[14].MDIO_RD_DATA_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[14].MDIO_RD_DATA[14]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(3),
R => prmry_in
);
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(4),
O => \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA[15]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA[15]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(4),
R => prmry_in
);
\MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(1),
O => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \clk_cnt_reg__0\(0),
I1 => \clk_cnt_reg__0\(1),
O => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \clk_cnt_reg__0\(2),
I1 => \clk_cnt_reg__0\(4),
I2 => \clk_cnt_reg__0\(5),
I3 => \clk_cnt_reg__0\(3),
O => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\
);
\MDIO_CAPTURE_DATA[1].MDIO_RD_DATA_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_1_n_0\,
Q => mdio_rd_data_reg(1),
R => prmry_in
);
\MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(2),
O => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \clk_cnt_reg__0\(1),
I1 => \clk_cnt_reg__0\(0),
O => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[2].MDIO_RD_DATA_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_1_n_0\,
Q => mdio_rd_data_reg(2),
R => prmry_in
);
\MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(3),
O => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \clk_cnt_reg__0\(0),
I1 => \clk_cnt_reg__0\(1),
O => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[3].MDIO_RD_DATA_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_1_n_0\,
Q => mdio_rd_data_reg(3),
R => prmry_in
);
\MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \clk_cnt[5]_i_4_n_0\,
I3 => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(4),
O => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => \clk_cnt_reg__0\(4),
I1 => \clk_cnt_reg__0\(5),
I2 => \clk_cnt_reg__0\(3),
I3 => \clk_cnt_reg__0\(2),
O => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[4].MDIO_RD_DATA_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_1_n_0\,
Q => mdio_rd_data_reg(4),
R => prmry_in
);
\MDIO_CAPTURE_DATA[5].MDIO_RD_DATA[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(5),
O => \MDIO_CAPTURE_DATA[5].MDIO_RD_DATA[5]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[5].MDIO_RD_DATA_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[5].MDIO_RD_DATA[5]_i_1_n_0\,
Q => mdio_rd_data_reg(5),
R => prmry_in
);
\MDIO_CAPTURE_DATA[6].MDIO_RD_DATA[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(6),
O => \MDIO_CAPTURE_DATA[6].MDIO_RD_DATA[6]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[6].MDIO_RD_DATA_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[6].MDIO_RD_DATA[6]_i_1_n_0\,
Q => mdio_rd_data_reg(6),
R => prmry_in
);
\MDIO_CAPTURE_DATA[7].MDIO_RD_DATA[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(7),
O => \MDIO_CAPTURE_DATA[7].MDIO_RD_DATA[7]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[7].MDIO_RD_DATA_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[7].MDIO_RD_DATA[7]_i_1_n_0\,
Q => mdio_rd_data_reg(7),
R => prmry_in
);
\MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_3_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(8),
O => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \clk_cnt_reg__0\(1),
I1 => \clk_cnt_reg__0\(0),
I2 => \clk_cnt_reg__0\(2),
O => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \clk_cnt_reg__0\(5),
I1 => \clk_cnt_reg__0\(4),
I2 => \clk_cnt_reg__0\(3),
O => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_3_n_0\
);
\MDIO_CAPTURE_DATA[8].MDIO_RD_DATA_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_1_n_0\,
Q => mdio_rd_data_reg(8),
R => prmry_in
);
\MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(9),
O => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \clk_cnt_reg__0\(2),
I1 => \clk_cnt_reg__0\(3),
I2 => \clk_cnt_reg__0\(4),
I3 => \clk_cnt_reg__0\(5),
O => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[9].MDIO_RD_DATA_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_1_n_0\,
Q => mdio_rd_data_reg(9),
R => prmry_in
);
\MDIO_GEN.mdio_data_out[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8808"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[0]_i_2_n_0\,
I1 => s_axi_aresetn,
I2 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I3 => p_6_in(0),
O => D(0)
);
\MDIO_GEN.mdio_data_out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCCFCCEFECEFEC"
)
port map (
I0 => Q(0),
I1 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I2 => \AXI4_LITE_IF_GEN.read_in_prog_reg_0\,
I3 => \MDIO_GEN.mdio_req_i_reg_0\,
I4 => mdio_rd_data_reg(0),
I5 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\(0),
O => \MDIO_GEN.mdio_data_out[0]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[10]_i_3_n_0\,
I1 => Q(10),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(10),
O => D(10)
);
\MDIO_GEN.mdio_data_out[10]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(10),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[10]_i_3_n_0\
);
\MDIO_GEN.mdio_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_wr_data_reg_reg[1]\,
I1 => mdio_rd_data_reg(1),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(1),
O => D(1)
);
\MDIO_GEN.mdio_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[2]_i_2_n_0\,
I1 => Q(2),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(2),
O => D(2)
);
\MDIO_GEN.mdio_data_out[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(2),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[2]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8808"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[3]_i_2_n_0\,
I1 => s_axi_aresetn,
I2 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I3 => p_6_in(3),
O => D(3)
);
\MDIO_GEN.mdio_data_out[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFECEFECFFFCCFCC"
)
port map (
I0 => mdio_rd_data_reg(3),
I1 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I2 => \AXI4_LITE_IF_GEN.read_in_prog_reg_0\,
I3 => mdio_en_i,
I4 => Q(3),
I5 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\(0),
O => \MDIO_GEN.mdio_data_out[3]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[4]_i_2_n_0\,
I1 => Q(4),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(4),
O => D(4)
);
\MDIO_GEN.mdio_data_out[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(4),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[4]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[5]_i_2_n_0\,
I1 => Q(5),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(5),
O => D(5)
);
\MDIO_GEN.mdio_data_out[5]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(5),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[5]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[6]_i_2_n_0\,
I1 => Q(6),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(6),
O => D(6)
);
\MDIO_GEN.mdio_data_out[6]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(6),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[6]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_wr_data_reg_reg[7]\,
I1 => mdio_rd_data_reg(7),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(7),
O => D(7)
);
\MDIO_GEN.mdio_data_out[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[8]_i_2_n_0\,
I1 => Q(8),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(8),
O => D(8)
);
\MDIO_GEN.mdio_data_out[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(8),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[8]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[9]_i_2_n_0\,
I1 => Q(9),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(9),
O => D(9)
);
\MDIO_GEN.mdio_data_out[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(9),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[9]_i_2_n_0\
);
\MDIO_GEN.mdio_req_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA3FFFAAAA0000"
)
port map (
I0 => s_axi_wdata(0),
I1 => \mdio_state__0\(2),
I2 => \mdio_state__0\(3),
I3 => \MDIO_GEN.mdio_req_i_i_2_n_0\,
I4 => p_19_out,
I5 => \MDIO_GEN.mdio_req_i_reg_0\,
O => \MDIO_GEN.mdio_req_i_reg\
);
\MDIO_GEN.mdio_req_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \mdio_state__0\(1),
I1 => \mdio_state__0\(0),
O => \MDIO_GEN.mdio_req_i_i_2_n_0\
);
PHY_MDIO_O_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF1FF0000F100"
)
port map (
I0 => PHY_MDIO_O_i_2_n_0,
I1 => \mdio_state__0\(3),
I2 => PHY_MDIO_O_i_3_n_0,
I3 => mdio_clk_reg,
I4 => \MDIO_GEN.mdio_clk_i_reg\,
I5 => \^phy_mdio_o\,
O => PHY_MDIO_O_i_1_n_0
);
PHY_MDIO_O_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => Q(11),
I1 => Q(10),
I2 => \clk_cnt_reg__0\(1),
I3 => Q(9),
I4 => \clk_cnt_reg__0\(0),
I5 => Q(8),
O => PHY_MDIO_O_i_10_n_0
);
PHY_MDIO_O_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => Q(15),
I1 => Q(14),
I2 => \clk_cnt_reg__0\(1),
I3 => Q(13),
I4 => \clk_cnt_reg__0\(0),
I5 => Q(12),
O => PHY_MDIO_O_i_11_n_0
);
PHY_MDIO_O_i_12: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => \clk_cnt_reg__0\(1),
I3 => Q(1),
I4 => \clk_cnt_reg__0\(0),
I5 => Q(0),
O => PHY_MDIO_O_i_12_n_0
);
PHY_MDIO_O_i_13: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => Q(7),
I1 => Q(6),
I2 => \clk_cnt_reg__0\(1),
I3 => Q(5),
I4 => \clk_cnt_reg__0\(0),
I5 => Q(4),
O => PHY_MDIO_O_i_13_n_0
);
PHY_MDIO_O_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"3FAF0F0F00AF0F0F"
)
port map (
I0 => p_6_in(10),
I1 => PHY_MDIO_O_i_4_n_0,
I2 => \mdio_state__0\(0),
I3 => \mdio_state__0\(1),
I4 => \mdio_state__0\(2),
I5 => PHY_MDIO_O_i_5_n_0,
O => PHY_MDIO_O_i_2_n_0
);
PHY_MDIO_O_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00FC00CC32333233"
)
port map (
I0 => p_6_in(10),
I1 => \mdio_state__0\(0),
I2 => \mdio_state__0\(3),
I3 => \mdio_state__0\(2),
I4 => PHY_MDIO_O_i_6_n_0,
I5 => \mdio_state__0\(1),
O => PHY_MDIO_O_i_3_n_0
);
PHY_MDIO_O_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"02FF0200"
)
port map (
I0 => p_6_in(4),
I1 => \clk_cnt_reg__0\(1),
I2 => \clk_cnt_reg__0\(0),
I3 => \clk_cnt_reg__0\(2),
I4 => PHY_MDIO_O_i_7_n_0,
O => PHY_MDIO_O_i_4_n_0
);
PHY_MDIO_O_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBABFBFBFBFB"
)
port map (
I0 => \mdio_state__0\(0),
I1 => PHY_MDIO_O_i_8_n_0,
I2 => \clk_cnt_reg__0\(2),
I3 => \clk_cnt_reg__0\(0),
I4 => \clk_cnt_reg__0\(1),
I5 => p_6_in(9),
O => PHY_MDIO_O_i_5_n_0
);
PHY_MDIO_O_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => PHY_MDIO_O_reg_i_9_n_0,
I1 => \clk_cnt_reg__0\(3),
I2 => PHY_MDIO_O_i_10_n_0,
I3 => \clk_cnt_reg__0\(2),
I4 => PHY_MDIO_O_i_11_n_0,
I5 => \clk_cnt_reg__0\(4),
O => PHY_MDIO_O_i_6_n_0
);
PHY_MDIO_O_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => p_6_in(3),
I1 => p_6_in(2),
I2 => \clk_cnt_reg__0\(1),
I3 => p_6_in(1),
I4 => \clk_cnt_reg__0\(0),
I5 => p_6_in(0),
O => PHY_MDIO_O_i_7_n_0
);
PHY_MDIO_O_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => p_6_in(8),
I1 => p_6_in(7),
I2 => \clk_cnt_reg__0\(1),
I3 => p_6_in(6),
I4 => \clk_cnt_reg__0\(0),
I5 => p_6_in(5),
O => PHY_MDIO_O_i_8_n_0
);
PHY_MDIO_O_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => PHY_MDIO_O_i_1_n_0,
Q => \^phy_mdio_o\,
R => prmry_in
);
PHY_MDIO_O_reg_i_9: unisim.vcomponents.MUXF7
port map (
I0 => PHY_MDIO_O_i_12_n_0,
I1 => PHY_MDIO_O_i_13_n_0,
O => PHY_MDIO_O_reg_i_9_n_0,
S => \clk_cnt_reg__0\(2)
);
PHY_MDIO_T_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => mdio_t_comb,
I1 => mdio_clk_reg,
I2 => \MDIO_GEN.mdio_clk_i_reg\,
I3 => \^phy_mdio_t\,
O => PHY_MDIO_T_i_1_n_0
);
PHY_MDIO_T_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"222000B9"
)
port map (
I0 => \mdio_state__0\(3),
I1 => \mdio_state__0\(2),
I2 => p_6_in(10),
I3 => \mdio_state__0\(1),
I4 => \mdio_state__0\(0),
O => mdio_t_comb
);
PHY_MDIO_T_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => PHY_MDIO_T_i_1_n_0,
Q => \^phy_mdio_t\,
S => prmry_in
);
\clk_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => data(1),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(0),
O => \p_0_in__1\(0)
);
\clk_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => data(1),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(0),
I3 => \clk_cnt_reg__0\(1),
O => \p_0_in__1\(1)
);
\clk_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => data(2),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(2),
I3 => \clk_cnt_reg__0\(1),
I4 => \clk_cnt_reg__0\(0),
O => \p_0_in__1\(2)
);
\clk_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => data(1),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(3),
I3 => \clk_cnt_reg__0\(2),
I4 => \clk_cnt_reg__0\(0),
I5 => \clk_cnt_reg__0\(1),
O => \p_0_in__1\(3)
);
\clk_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B88BB8B8"
)
port map (
I0 => data(4),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(4),
I3 => \clk_cnt_reg__0\(3),
I4 => \clk_cnt[5]_i_4_n_0\,
I5 => \clk_cnt_reg__0\(2),
O => \p_0_in__1\(4)
);
\clk_cnt[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => mdio_clk_reg,
I1 => \MDIO_GEN.mdio_clk_i_reg\,
I2 => \clk_cnt[5]_i_3_n_0\,
O => clk_cnt
);
\clk_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555000055450010"
)
port map (
I0 => ld_cnt_en_reg,
I1 => \clk_cnt_reg__0\(2),
I2 => \clk_cnt[5]_i_4_n_0\,
I3 => \clk_cnt_reg__0\(4),
I4 => \clk_cnt_reg__0\(5),
I5 => \clk_cnt_reg__0\(3),
O => \clk_cnt[5]_i_2_n_0\
);
\clk_cnt[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545551455451515"
)
port map (
I0 => ld_cnt_en_reg,
I1 => \mdio_state__0\(2),
I2 => \mdio_state__0\(1),
I3 => ld_cnt_en_reg_i_2_n_0,
I4 => \mdio_state__0\(3),
I5 => \mdio_state__0\(0),
O => \clk_cnt[5]_i_3_n_0\
);
\clk_cnt[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \clk_cnt_reg__0\(0),
I1 => \clk_cnt_reg__0\(1),
O => \clk_cnt[5]_i_4_n_0\
);
\clk_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(0),
Q => \clk_cnt_reg__0\(0),
R => prmry_in
);
\clk_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(1),
Q => \clk_cnt_reg__0\(1),
R => prmry_in
);
\clk_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(2),
Q => \clk_cnt_reg__0\(2),
R => prmry_in
);
\clk_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(3),
Q => \clk_cnt_reg__0\(3),
R => prmry_in
);
\clk_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(4),
Q => \clk_cnt_reg__0\(4),
R => prmry_in
);
\clk_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \clk_cnt[5]_i_2_n_0\,
Q => \clk_cnt_reg__0\(5),
R => prmry_in
);
\ld_cnt_data_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000C01"
)
port map (
I0 => mdio_idle_reg_n_0,
I1 => \mdio_state__0\(3),
I2 => \mdio_state__0\(2),
I3 => \mdio_state__0\(0),
I4 => \mdio_state__0\(1),
O => ld_cnt_data_cmb(1)
);
\ld_cnt_data_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00203C0000203C03"
)
port map (
I0 => ld_cnt_en_reg_i_2_n_0,
I1 => \mdio_state__0\(3),
I2 => \mdio_state__0\(2),
I3 => \mdio_state__0\(0),
I4 => \mdio_state__0\(1),
I5 => mdio_idle_reg_n_0,
O => ld_cnt_data_cmb(2)
);
\ld_cnt_data_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => mdio_idle_reg_n_0,
I1 => \mdio_state__0\(1),
I2 => \mdio_state__0\(0),
I3 => \mdio_state__0\(2),
I4 => \mdio_state__0\(3),
O => \ld_cnt_data_reg[4]_i_1_n_0\
);
\ld_cnt_data_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ld_cnt_data_cmb(1),
Q => data(1),
R => prmry_in
);
\ld_cnt_data_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ld_cnt_data_cmb(2),
Q => data(2),
R => prmry_in
);
\ld_cnt_data_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ld_cnt_data_reg[4]_i_1_n_0\,
Q => data(4),
R => prmry_in
);
ld_cnt_en_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00303803"
)
port map (
I0 => ld_cnt_en_reg_i_2_n_0,
I1 => \mdio_state__0\(1),
I2 => \mdio_state__0\(0),
I3 => \mdio_state__0\(2),
I4 => \mdio_state__0\(3),
O => ld_cnt_en_cmb
);
ld_cnt_en_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \clk_cnt_reg__0\(2),
I1 => \clk_cnt_reg__0\(0),
I2 => \clk_cnt_reg__0\(1),
I3 => \clk_cnt_reg__0\(4),
I4 => \clk_cnt_reg__0\(5),
I5 => \clk_cnt_reg__0\(3),
O => ld_cnt_en_reg_i_2_n_0
);
ld_cnt_en_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ld_cnt_en_cmb,
Q => ld_cnt_en_reg,
R => prmry_in
);
mdio_clk_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.mdio_clk_i_reg\,
Q => mdio_clk_reg,
R => prmry_in
);
mdio_en_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFF2000"
)
port map (
I0 => mdio_en_i,
I1 => \MDIO_GEN.mdio_clk_i_reg\,
I2 => mdio_clk_reg,
I3 => mdio_idle_reg_n_0,
I4 => mdio_en_reg,
O => mdio_en_reg_i_1_n_0
);
mdio_en_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mdio_en_reg_i_1_n_0,
Q => mdio_en_reg,
R => prmry_in
);
mdio_idle_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF70FFF0FFF0FF"
)
port map (
I0 => mdio_en_reg,
I1 => \MDIO_GEN.mdio_req_i_reg_0\,
I2 => mdio_idle_reg_n_0,
I3 => s_axi_aresetn,
I4 => mdio_done_i,
I5 => mdio_idle_i_3_n_0,
O => mdio_idle_i_1_n_0
);
mdio_idle_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \mdio_state__0\(0),
I1 => \mdio_state__0\(1),
I2 => \mdio_state__0\(3),
I3 => \mdio_state__0\(2),
O => mdio_done_i
);
mdio_idle_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \MDIO_GEN.mdio_clk_i_reg\,
I1 => mdio_clk_reg,
O => mdio_idle_i_3_n_0
);
mdio_idle_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mdio_idle_i_1_n_0,
Q => mdio_idle_reg_n_0,
R => '0'
);
mdio_in_reg1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => phy_mdio_i,
Q => mdio_in_reg1,
R => prmry_in
);
mdio_in_reg2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mdio_in_reg1,
Q => mdio_in_reg2,
R => prmry_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_mux_onehot_f is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\txNibbleCnt_pad_reg[11]\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC;
STATE15A : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC;
STATE15A_0 : in STD_LOGIC;
STATE12A : in STD_LOGIC;
STATE15A_1 : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC;
STATE15A_2 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_mux_onehot_f : entity is "mux_onehot_f";
end system_axi_ethernetlite_0_0_mux_onehot_f;
architecture STRUCTURE of system_axi_ethernetlite_0_0_mux_onehot_f is
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal cyout_1 : STD_LOGIC;
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
begin
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(3),
CO(0) => cyout_1,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => STATE15A,
S(0) => \gen_wr_b.gen_word_wide.mem_reg\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(2),
CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => STATE15A_0,
S(0) => \gen_wr_b.gen_word_wide.mem_reg_0\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(1),
CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => STATE15A_1,
S(0) => STATE12A
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => Q(0),
I1 => Q(8),
I2 => Q(6),
I3 => Q(7),
I4 => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3_n_0\,
I5 => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4_n_0\,
O => \txNibbleCnt_pad_reg[11]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => Q(11),
I1 => Q(10),
I2 => Q(4),
I3 => Q(1),
O => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3_n_0\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => Q(5),
I1 => Q(9),
I2 => Q(2),
I3 => Q(3),
O => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4_n_0\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(0),
CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => STATE15A_2,
S(0) => \gen_wr_b.gen_word_wide.mem_reg_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_ram16x4 is
port (
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]_0\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
mac_addr_ram_we : in STD_LOGIC;
mac_addr_ram_addr : in STD_LOGIC_VECTOR ( 0 to 3 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_ram16x4 : entity is "ram16x4";
end system_axi_ethernetlite_0_0_ram16x4;
architecture STRUCTURE of system_axi_ethernetlite_0_0_ram16x4 is
signal mac_addr_ram_data : STD_LOGIC_VECTOR ( 0 to 3 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ram16x1_0 : label is "RAM16X1S";
attribute box_type : string;
attribute box_type of ram16x1_0 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ram16x1_1 : label is "RAM16X1S";
attribute box_type of ram16x1_1 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ram16x1_2 : label is "RAM16X1S";
attribute box_type of ram16x1_2 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ram16x1_3 : label is "RAM16X1S";
attribute box_type of ram16x1_3 : label is "PRIMITIVE";
begin
ram16x1_0: unisim.vcomponents.RAM32X1S
generic map(
INIT => X"00000220",
IS_WCLK_INVERTED => '0'
)
port map (
A0 => mac_addr_ram_addr(3),
A1 => mac_addr_ram_addr(2),
A2 => mac_addr_ram_addr(1),
A3 => mac_addr_ram_addr(0),
A4 => '0',
D => \gen_wr_b.gen_word_wide.mem_reg\(0),
O => mac_addr_ram_data(3),
WCLK => s_axi_aclk,
WE => mac_addr_ram_we
);
ram16x1_1: unisim.vcomponents.RAM32X1S
generic map(
INIT => X"00000710",
IS_WCLK_INVERTED => '0'
)
port map (
A0 => mac_addr_ram_addr(3),
A1 => mac_addr_ram_addr(2),
A2 => mac_addr_ram_addr(1),
A3 => mac_addr_ram_addr(0),
A4 => '0',
D => \gen_wr_b.gen_word_wide.mem_reg\(1),
O => mac_addr_ram_data(2),
WCLK => s_axi_aclk,
WE => mac_addr_ram_we
);
ram16x1_2: unisim.vcomponents.RAM32X1S
generic map(
INIT => X"00000E30",
IS_WCLK_INVERTED => '0'
)
port map (
A0 => mac_addr_ram_addr(3),
A1 => mac_addr_ram_addr(2),
A2 => mac_addr_ram_addr(1),
A3 => mac_addr_ram_addr(0),
A4 => '0',
D => \gen_wr_b.gen_word_wide.mem_reg\(2),
O => mac_addr_ram_data(1),
WCLK => s_axi_aclk,
WE => mac_addr_ram_we
);
ram16x1_3: unisim.vcomponents.RAM32X1S
generic map(
INIT => X"00000F10",
IS_WCLK_INVERTED => '0'
)
port map (
A0 => mac_addr_ram_addr(3),
A1 => mac_addr_ram_addr(2),
A2 => mac_addr_ram_addr(1),
A3 => mac_addr_ram_addr(0),
A4 => '0',
D => \gen_wr_b.gen_word_wide.mem_reg\(3),
O => mac_addr_ram_data(0),
WCLK => s_axi_aclk,
WE => mac_addr_ram_we
);
state22a_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => mac_addr_ram_data(2),
I1 => Q(1),
I2 => mac_addr_ram_data(0),
I3 => Q(3),
O => \rdDestAddrNib_D_t_q_reg[1]_0\
);
state22a_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => mac_addr_ram_data(1),
I1 => Q(2),
I2 => mac_addr_ram_data(3),
I3 => Q(0),
O => \rdDestAddrNib_D_t_q_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rx_statemachine is
port (
crcokr1 : out STD_LOGIC;
rxCrcRst : out STD_LOGIC;
sfd1CheckBusFifoEmpty : out STD_LOGIC;
rx_start : out STD_LOGIC;
startReadDestAdrNib : out STD_LOGIC;
startReadDataNib : out STD_LOGIC;
busFifoData_is_5_d1 : out STD_LOGIC;
rxCrcEn : out STD_LOGIC;
rxCrcEn_d1_reg : out STD_LOGIC;
wea : out STD_LOGIC_VECTOR ( 0 to 0 );
rx_addr_en : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]_0\ : out STD_LOGIC;
ram_valid_i : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
state2a_0 : out STD_LOGIC;
\rxbuffer_addr_reg[0]\ : out STD_LOGIC;
D_5 : out STD_LOGIC;
RX_DONE_D1_I : out STD_LOGIC;
\crc_local_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : out STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : out STD_LOGIC;
ena : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
state17a_0 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
crcokdelay_0 : in STD_LOGIC;
D : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ : in STD_LOGIC;
D5_out : in STD_LOGIC;
D13_out : in STD_LOGIC;
D6_out : in STD_LOGIC;
D11_out : in STD_LOGIC;
\gpr1.dout_i_reg[2]\ : in STD_LOGIC;
\gpr1.dout_i_reg[5]\ : in STD_LOGIC;
rxBusFifoRdAck : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gpr1.dout_i_reg[1]\ : in STD_LOGIC;
\gv.ram_valid_d1_reg\ : in STD_LOGIC;
ram_empty_i_reg : in STD_LOGIC;
goto_readDestAdrNib1 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\gpr1.dout_i_reg[1]_0\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[2]\ : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[1]\ : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_5_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_9_in : in STD_LOGIC_VECTOR ( 0 to 0 );
STATE17A : in STD_LOGIC;
tx_intr_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
rx_intr_en0 : in STD_LOGIC;
rx_pong_ping_l : in STD_LOGIC;
ping_rx_status_reg_0 : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg\ : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rx_statemachine : entity is "rx_statemachine";
end system_axi_ethernetlite_0_0_rx_statemachine;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rx_statemachine is
signal D10_out : STD_LOGIC;
signal D12_out : STD_LOGIC;
signal D18_out : STD_LOGIC;
signal \Mac_addr_ram_addr_rd[0]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_rd[1]_i_2_n_0\ : STD_LOGIC;
signal \^rx_done_d1_i\ : STD_LOGIC;
signal \^busfifodata_is_5_d1\ : STD_LOGIC;
signal checkingBroadcastAdr_reg : STD_LOGIC;
signal checkingBroadcastAdr_reg_i_1_n_0 : STD_LOGIC;
signal checkingBroadcastAdr_reg_i_2_n_0 : STD_LOGIC;
signal checkingBroadcastAdr_reg_i_3_n_0 : STD_LOGIC;
signal crcCheck : STD_LOGIC;
signal \^crcokr1\ : STD_LOGIC;
signal \gv.ram_valid_d1_i_3_n_0\ : STD_LOGIC;
signal mac_addr_ram_addr_rd_D : STD_LOGIC_VECTOR ( 0 to 3 );
signal pkt_length_cnt0 : STD_LOGIC;
signal \pkt_length_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[2]_i_2_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[6]_i_3_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[6]_i_4_n_0\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal preamble_error_reg : STD_LOGIC;
signal rdDestAddrNib_D_t : STD_LOGIC_VECTOR ( 0 to 3 );
signal rdDestAddrNib_D_t_q : STD_LOGIC_VECTOR ( 0 to 3 );
signal \rdDestAddrNib_D_t_q[0]_i_1_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[0]_i_3_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[0]_i_4_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[0]_i_5_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[1]_i_2_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[1]_i_3_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[1]_i_4_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[2]_i_2_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[3]_i_3_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[3]_i_4_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[3]_i_6_n_0\ : STD_LOGIC;
signal \^rddestaddrnib_d_t_q_reg[1]_0\ : STD_LOGIC;
signal rxAbortRst : STD_LOGIC;
signal \^rxcrcen_d1_reg\ : STD_LOGIC;
signal \^rxcrcrst\ : STD_LOGIC;
signal rxDone : STD_LOGIC;
signal \^rx_addr_en\ : STD_LOGIC;
signal \^rx_start\ : STD_LOGIC;
signal \^sfd1checkbusfifoempty\ : STD_LOGIC;
signal \^startreaddatanib\ : STD_LOGIC;
signal \^startreaddestadrnib\ : STD_LOGIC;
signal state0a_i_3_n_0 : STD_LOGIC;
signal state22a_i_1_n_0 : STD_LOGIC;
signal state22a_i_4_n_0 : STD_LOGIC;
signal waitForSfd1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_rd[0]_i_2\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_rd[1]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_rd[2]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_rd[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of checkingBroadcastAdr_reg_i_3 : label is "soft_lutpair44";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of crcokdelay : label is "FDR";
attribute box_type : string;
attribute box_type of crcokdelay : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \gv.ram_valid_d1_i_2\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \gv.ram_valid_d1_i_3\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \pkt_length_cnt[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \pkt_length_cnt[3]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \pkt_length_cnt[5]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \pkt_length_cnt[6]_i_3\ : label is "soft_lutpair34";
attribute XILINX_LEGACY_PRIM of preamble : label is "FDR";
attribute box_type of preamble : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[0]_i_3\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[0]_i_4\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[1]_i_3\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[1]_i_4\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[3]_i_3\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[3]_i_4\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[3]_i_6\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of rxCrcEn_d1_i_1 : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \rxbuffer_addr[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \rxbuffer_addr[11]_i_2\ : label is "soft_lutpair35";
attribute XILINX_LEGACY_PRIM of state0a : label is "FDS";
attribute box_type of state0a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state0a_i_3 : label is "soft_lutpair43";
attribute XILINX_LEGACY_PRIM of state17a_RnM : label is "FDR";
attribute box_type of state17a_RnM : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of state18a : label is "FDR";
attribute box_type of state18a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state18a_i_1 : label is "soft_lutpair32";
attribute XILINX_LEGACY_PRIM of state1a : label is "FDR";
attribute box_type of state1a : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of state20a : label is "FDR";
attribute box_type of state20a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state20a_i_1 : label is "soft_lutpair42";
attribute XILINX_LEGACY_PRIM of state22a : label is "FDR";
attribute box_type of state22a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state22a_i_1 : label is "soft_lutpair42";
attribute SOFT_HLUTNM of state22a_i_4 : label is "soft_lutpair41";
attribute XILINX_LEGACY_PRIM of state2a : label is "FDR";
attribute box_type of state2a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state2a_i_3 : label is "soft_lutpair43";
attribute XILINX_LEGACY_PRIM of state3a : label is "FDR";
attribute box_type of state3a : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of state4a : label is "FDR";
attribute box_type of state4a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of xpm_memory_base_inst_i_1 : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of xpm_memory_base_inst_i_2 : label is "soft_lutpair38";
begin
RX_DONE_D1_I <= \^rx_done_d1_i\;
busFifoData_is_5_d1 <= \^busfifodata_is_5_d1\;
crcokr1 <= \^crcokr1\;
\rdDestAddrNib_D_t_q_reg[1]_0\ <= \^rddestaddrnib_d_t_q_reg[1]_0\;
rxCrcEn_d1_reg <= \^rxcrcen_d1_reg\;
rxCrcRst <= \^rxcrcrst\;
rx_addr_en <= \^rx_addr_en\;
rx_start <= \^rx_start\;
sfd1CheckBusFifoEmpty <= \^sfd1checkbusfifoempty\;
startReadDataNib <= \^startreaddatanib\;
startReadDestAdrNib <= \^startreaddestadrnib\;
IP2INTC_IRPT_REG_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AA808080"
)
port map (
I0 => p_5_in(0),
I1 => p_9_in(0),
I2 => \^rx_done_d1_i\,
I3 => STATE17A,
I4 => tx_intr_en_reg(0),
O => D_5
);
\Mac_addr_ram_addr_rd[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFAABA"
)
port map (
I0 => D10_out,
I1 => rxBusFifoRdAck,
I2 => \^startreaddestadrnib\,
I3 => Q(0),
I4 => \rdDestAddrNib_D_t_q[0]_i_1_n_0\,
O => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
\Mac_addr_ram_addr_rd[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"08A2"
)
port map (
I0 => rdDestAddrNib_D_t(0),
I1 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
I2 => rdDestAddrNib_D_t(3),
I3 => rdDestAddrNib_D_t(1),
O => mac_addr_ram_addr_rd_D(0)
);
\Mac_addr_ram_addr_rd[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"23222022"
)
port map (
I0 => rdDestAddrNib_D_t(1),
I1 => \Mac_addr_ram_addr_rd[1]_i_2_n_0\,
I2 => rdDestAddrNib_D_t(3),
I3 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
I4 => rdDestAddrNib_D_t(0),
O => mac_addr_ram_addr_rd_D(1)
);
\Mac_addr_ram_addr_rd[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"C8C8C8C8C8C808C8"
)
port map (
I0 => \rdDestAddrNib_D_t_q[0]_i_5_n_0\,
I1 => rdDestAddrNib_D_t_q(0),
I2 => rdDestAddrNib_D_t_q(1),
I3 => ram_empty_i_reg,
I4 => rdDestAddrNib_D_t_q(2),
I5 => rdDestAddrNib_D_t_q(3),
O => \Mac_addr_ram_addr_rd[1]_i_2_n_0\
);
\Mac_addr_ram_addr_rd[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0055FC00"
)
port map (
I0 => \Mac_addr_ram_addr_rd[1]_i_2_n_0\,
I1 => rdDestAddrNib_D_t(0),
I2 => rdDestAddrNib_D_t(1),
I3 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
I4 => rdDestAddrNib_D_t(3),
O => mac_addr_ram_addr_rd_D(2)
);
\Mac_addr_ram_addr_rd[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E0EF"
)
port map (
I0 => rdDestAddrNib_D_t(0),
I1 => rdDestAddrNib_D_t(1),
I2 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
I3 => \Mac_addr_ram_addr_rd[1]_i_2_n_0\,
I4 => rdDestAddrNib_D_t(3),
O => mac_addr_ram_addr_rd_D(3)
);
\Mac_addr_ram_addr_rd_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_addr_ram_addr_rd_D(0),
Q => \rdDestAddrNib_D_t_q_reg[1]_1\(3),
R => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
\Mac_addr_ram_addr_rd_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_addr_ram_addr_rd_D(1),
Q => \rdDestAddrNib_D_t_q_reg[1]_1\(2),
R => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
\Mac_addr_ram_addr_rd_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_addr_ram_addr_rd_D(2),
Q => \rdDestAddrNib_D_t_q_reg[1]_1\(1),
R => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
\Mac_addr_ram_addr_rd_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_addr_ram_addr_rd_D(3),
Q => \rdDestAddrNib_D_t_q_reg[1]_1\(0),
R => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
RX_DONE_D1_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[4]\,
I1 => \pkt_length_cnt_reg_n_0_[6]\,
I2 => \pkt_length_cnt_reg_n_0_[5]\,
I3 => \pkt_length_cnt_reg_n_0_[3]\,
I4 => \pkt_length_cnt[3]_i_2_n_0\,
I5 => rxDone,
O => \^rx_done_d1_i\
);
\RX_PONG_REG_GEN.pong_rx_status_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFEFEFEF202020"
)
port map (
I0 => s_axi_wdata(0),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg\,
I3 => rx_pong_ping_l,
I4 => \^rx_done_d1_i\,
I5 => \RX_PONG_REG_GEN.pong_rx_status_reg_1\,
O => \RX_PONG_REG_GEN.pong_rx_status_reg\
);
busFifoData_is_5_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \gpr1.dout_i_reg[5]\,
Q => \^busfifodata_is_5_d1\,
R => SS(0)
);
checkingBroadcastAdr_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444454444"
)
port map (
I0 => \^rxcrcrst\,
I1 => checkingBroadcastAdr_reg,
I2 => checkingBroadcastAdr_reg_i_2_n_0,
I3 => checkingBroadcastAdr_reg_i_3_n_0,
I4 => rdDestAddrNib_D_t_q(3),
I5 => rdDestAddrNib_D_t_q(0),
O => checkingBroadcastAdr_reg_i_1_n_0
);
checkingBroadcastAdr_reg_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \emac_rx_rd_data_d1_reg[0]\(3),
I1 => \emac_rx_rd_data_d1_reg[0]\(0),
I2 => \emac_rx_rd_data_d1_reg[0]\(1),
I3 => \emac_rx_rd_data_d1_reg[0]\(2),
O => checkingBroadcastAdr_reg_i_2_n_0
);
checkingBroadcastAdr_reg_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rdDestAddrNib_D_t_q(2),
I1 => rdDestAddrNib_D_t_q(1),
O => checkingBroadcastAdr_reg_i_3_n_0
);
checkingBroadcastAdr_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => checkingBroadcastAdr_reg_i_1_n_0,
Q => checkingBroadcastAdr_reg,
R => SS(0)
);
\crc_local[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => rxAbortRst,
I1 => s_axi_aresetn,
I2 => \^rxcrcrst\,
O => \crc_local_reg[31]\(0)
);
crcokdelay: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D,
Q => \^crcokr1\,
R => crcokdelay_0
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555515"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => \^rxcrcen_d1_reg\,
I2 => \gv.ram_valid_d1_i_3_n_0\,
I3 => \^rxcrcrst\,
I4 => rxDone,
I5 => rxBusFifoRdAck,
O => E(0)
);
\gv.ram_valid_d1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555515"
)
port map (
I0 => \out\,
I1 => \^rxcrcen_d1_reg\,
I2 => \gv.ram_valid_d1_i_3_n_0\,
I3 => \^rxcrcrst\,
I4 => rxDone,
I5 => rxBusFifoRdAck,
O => ram_valid_i
);
\gv.ram_valid_d1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => rdDestAddrNib_D_t_q(3),
I1 => rdDestAddrNib_D_t_q(2),
I2 => rdDestAddrNib_D_t_q(1),
I3 => rdDestAddrNib_D_t_q(0),
O => \^rxcrcen_d1_reg\
);
\gv.ram_valid_d1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^sfd1checkbusfifoempty\,
I1 => \^startreaddestadrnib\,
I2 => \^startreaddatanib\,
O => \gv.ram_valid_d1_i_3_n_0\
);
ping_rx_status_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBB8B88"
)
port map (
I0 => s_axi_wdata(0),
I1 => rx_intr_en0,
I2 => rx_pong_ping_l,
I3 => \^rx_done_d1_i\,
I4 => ping_rx_status_reg_0,
O => ping_rx_status_reg
);
\pkt_length_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4F444444"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[0]\,
I1 => \pkt_length_cnt[2]_i_2_n_0\,
I2 => Q(0),
I3 => \^startreaddestadrnib\,
I4 => rxBusFifoRdAck,
O => \pkt_length_cnt[0]_i_1_n_0\
);
\pkt_length_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"90FF909090909090"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[1]\,
I1 => \pkt_length_cnt_reg_n_0_[0]\,
I2 => \pkt_length_cnt[2]_i_2_n_0\,
I3 => Q(0),
I4 => \^startreaddestadrnib\,
I5 => rxBusFifoRdAck,
O => \pkt_length_cnt[1]_i_1_n_0\
);
\pkt_length_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFA900"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[2]\,
I1 => \pkt_length_cnt_reg_n_0_[0]\,
I2 => \pkt_length_cnt_reg_n_0_[1]\,
I3 => \pkt_length_cnt[2]_i_2_n_0\,
I4 => goto_readDestAdrNib1,
O => \pkt_length_cnt[2]_i_1_n_0\
);
\pkt_length_cnt[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[4]\,
I1 => \pkt_length_cnt_reg_n_0_[6]\,
I2 => \pkt_length_cnt_reg_n_0_[5]\,
I3 => \pkt_length_cnt_reg_n_0_[3]\,
I4 => \pkt_length_cnt_reg_n_0_[1]\,
I5 => \pkt_length_cnt_reg_n_0_[2]\,
O => \pkt_length_cnt[2]_i_2_n_0\
);
\pkt_length_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF66666662"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[3]\,
I1 => \pkt_length_cnt[3]_i_2_n_0\,
I2 => \pkt_length_cnt_reg_n_0_[5]\,
I3 => \pkt_length_cnt_reg_n_0_[6]\,
I4 => \pkt_length_cnt_reg_n_0_[4]\,
I5 => goto_readDestAdrNib1,
O => \pkt_length_cnt[3]_i_1_n_0\
);
\pkt_length_cnt[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[0]\,
I1 => \pkt_length_cnt_reg_n_0_[1]\,
I2 => \pkt_length_cnt_reg_n_0_[2]\,
O => \pkt_length_cnt[3]_i_2_n_0\
);
\pkt_length_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6662"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[4]\,
I1 => \pkt_length_cnt[6]_i_4_n_0\,
I2 => \pkt_length_cnt_reg_n_0_[6]\,
I3 => \pkt_length_cnt_reg_n_0_[5]\,
I4 => goto_readDestAdrNib1,
O => \pkt_length_cnt[4]_i_1_n_0\
);
\pkt_length_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFCC2C"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[6]\,
I1 => \pkt_length_cnt_reg_n_0_[5]\,
I2 => \pkt_length_cnt[6]_i_4_n_0\,
I3 => \pkt_length_cnt_reg_n_0_[4]\,
I4 => goto_readDestAdrNib1,
O => \pkt_length_cnt[5]_i_1_n_0\
);
\pkt_length_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => preamble_error_reg,
I1 => s_axi_aresetn,
O => pkt_length_cnt0
);
\pkt_length_cnt[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD50000"
)
port map (
I0 => \^rxcrcen_d1_reg\,
I1 => \^startreaddatanib\,
I2 => Q(1),
I3 => \^startreaddestadrnib\,
I4 => rxBusFifoRdAck,
O => \pkt_length_cnt[6]_i_2_n_0\
);
\pkt_length_cnt[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFB00"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[4]\,
I1 => \pkt_length_cnt[6]_i_4_n_0\,
I2 => \pkt_length_cnt_reg_n_0_[5]\,
I3 => \pkt_length_cnt_reg_n_0_[6]\,
I4 => goto_readDestAdrNib1,
O => \pkt_length_cnt[6]_i_3_n_0\
);
\pkt_length_cnt[6]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[2]\,
I1 => \pkt_length_cnt_reg_n_0_[1]\,
I2 => \pkt_length_cnt_reg_n_0_[0]\,
I3 => \pkt_length_cnt_reg_n_0_[3]\,
O => \pkt_length_cnt[6]_i_4_n_0\
);
\pkt_length_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[0]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[0]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[1]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[1]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[2]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[2]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[3]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[3]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[4]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[4]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[5]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[5]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[6]_i_3_n_0\,
Q => \pkt_length_cnt_reg_n_0_[6]\,
R => pkt_length_cnt0
);
preamble: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gpr1.dout_i_reg[2]\,
Q => preamble_error_reg,
R => SS(0)
);
\rdDestAddrNib_D_t_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => \^rx_start\,
I1 => \^busfifodata_is_5_d1\,
I2 => Q(2),
I3 => \gpr1.dout_i_reg[1]\,
I4 => s_axi_aresetn,
O => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
\rdDestAddrNib_D_t_q[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"30F0BFF03000BF00"
)
port map (
I0 => \rdDestAddrNib_D_t_q[0]_i_3_n_0\,
I1 => \rdDestAddrNib_D_t_q[0]_i_4_n_0\,
I2 => rdDestAddrNib_D_t_q(1),
I3 => rdDestAddrNib_D_t_q(0),
I4 => \gpr1.dout_i_reg[1]_0\,
I5 => \rdDestAddrNib_D_t_q[0]_i_5_n_0\,
O => rdDestAddrNib_D_t(0)
);
\rdDestAddrNib_D_t_q[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^rddestaddrnib_d_t_q_reg[1]_0\,
I1 => rxBusFifoRdAck,
O => \rdDestAddrNib_D_t_q[0]_i_3_n_0\
);
\rdDestAddrNib_D_t_q[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rdDestAddrNib_D_t_q(3),
I1 => rdDestAddrNib_D_t_q(2),
O => \rdDestAddrNib_D_t_q[0]_i_4_n_0\
);
\rdDestAddrNib_D_t_q[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000E00000000000"
)
port map (
I0 => \^rxcrcen_d1_reg\,
I1 => Q(1),
I2 => rdDestAddrNib_D_t_q(2),
I3 => rxBusFifoRdAck,
I4 => \^rddestaddrnib_d_t_q_reg[1]_0\,
I5 => rdDestAddrNib_D_t_q(3),
O => \rdDestAddrNib_D_t_q[0]_i_5_n_0\
);
\rdDestAddrNib_D_t_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"80B0808080B08F8F"
)
port map (
I0 => \rdDestAddrNib_D_t_q[1]_i_2_n_0\,
I1 => rdDestAddrNib_D_t_q(0),
I2 => rdDestAddrNib_D_t_q(1),
I3 => \gpr1.dout_i_reg[1]_0\,
I4 => \rdDestAddrNib_D_t_q[1]_i_3_n_0\,
I5 => \rdDestAddrNib_D_t_q[1]_i_4_n_0\,
O => rdDestAddrNib_D_t(1)
);
\rdDestAddrNib_D_t_q[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBB010FFFFFFFF"
)
port map (
I0 => \^rddestaddrnib_d_t_q_reg[1]_0\,
I1 => rxBusFifoRdAck,
I2 => Q(1),
I3 => \out\,
I4 => \^rxcrcen_d1_reg\,
I5 => \rdDestAddrNib_D_t_q[0]_i_4_n_0\,
O => \rdDestAddrNib_D_t_q[1]_i_2_n_0\
);
\rdDestAddrNib_D_t_q[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => rdDestAddrNib_D_t_q(3),
I1 => \^rddestaddrnib_d_t_q_reg[1]_0\,
I2 => rxBusFifoRdAck,
I3 => rdDestAddrNib_D_t_q(2),
O => \rdDestAddrNib_D_t_q[1]_i_3_n_0\
);
\rdDestAddrNib_D_t_q[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => Q(1),
I1 => rdDestAddrNib_D_t_q(0),
I2 => rdDestAddrNib_D_t_q(1),
I3 => rdDestAddrNib_D_t_q(2),
I4 => rdDestAddrNib_D_t_q(3),
O => \rdDestAddrNib_D_t_q[1]_i_4_n_0\
);
\rdDestAddrNib_D_t_q[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
O => rdDestAddrNib_D_t(2)
);
\rdDestAddrNib_D_t_q[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333BBBBFBCB"
)
port map (
I0 => \gpr1.dout_i_reg[1]_0\,
I1 => rdDestAddrNib_D_t_q(2),
I2 => rdDestAddrNib_D_t_q(3),
I3 => \rdDestAddrNib_D_t_q[1]_i_4_n_0\,
I4 => \rdDestAddrNib_D_t_q[0]_i_3_n_0\,
I5 => \rdDestAddrNib_D_t_q[3]_i_3_n_0\,
O => \rdDestAddrNib_D_t_q[2]_i_2_n_0\
);
\rdDestAddrNib_D_t_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDD03003330"
)
port map (
I0 => ram_empty_i_reg,
I1 => \rdDestAddrNib_D_t_q[3]_i_3_n_0\,
I2 => \rdDestAddrNib_D_t_q[3]_i_4_n_0\,
I3 => goto_readDestAdrNib1,
I4 => \rdDestAddrNib_D_t_q[3]_i_6_n_0\,
I5 => rdDestAddrNib_D_t_q(3),
O => rdDestAddrNib_D_t(3)
);
\rdDestAddrNib_D_t_q[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rdDestAddrNib_D_t_q(0),
I1 => rdDestAddrNib_D_t_q(1),
O => \rdDestAddrNib_D_t_q[3]_i_3_n_0\
);
\rdDestAddrNib_D_t_q[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rdDestAddrNib_D_t_q(0),
I1 => rdDestAddrNib_D_t_q(1),
I2 => rdDestAddrNib_D_t_q(2),
O => \rdDestAddrNib_D_t_q[3]_i_4_n_0\
);
\rdDestAddrNib_D_t_q[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF1F"
)
port map (
I0 => \^rxcrcen_d1_reg\,
I1 => Q(1),
I2 => rxBusFifoRdAck,
I3 => \^rddestaddrnib_d_t_q_reg[1]_0\,
O => \rdDestAddrNib_D_t_q[3]_i_6_n_0\
);
\rdDestAddrNib_D_t_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdDestAddrNib_D_t(0),
Q => rdDestAddrNib_D_t_q(0),
R => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
\rdDestAddrNib_D_t_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdDestAddrNib_D_t(1),
Q => rdDestAddrNib_D_t_q(1),
R => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
\rdDestAddrNib_D_t_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdDestAddrNib_D_t(2),
Q => rdDestAddrNib_D_t_q(2),
R => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
\rdDestAddrNib_D_t_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdDestAddrNib_D_t(3),
Q => rdDestAddrNib_D_t_q(3),
R => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
rxCrcEn_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA80AA"
)
port map (
I0 => rxBusFifoRdAck,
I1 => Q(1),
I2 => \^startreaddatanib\,
I3 => \^rxcrcen_d1_reg\,
I4 => \^startreaddestadrnib\,
O => rxCrcEn
);
\rxbuffer_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^rx_start\,
I1 => s_axi_aresetn,
O => \rxbuffer_addr_reg[0]\
);
\rxbuffer_addr[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => rxBusFifoRdAck,
I1 => \^startreaddatanib\,
I2 => \^rxcrcen_d1_reg\,
I3 => \^startreaddestadrnib\,
O => \^rx_addr_en\
);
state0a: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D10_out,
Q => \^rxcrcrst\,
S => SS(0)
);
state0a_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0EFF0EFFFFFF0E"
)
port map (
I0 => \^rx_start\,
I1 => waitForSfd1,
I2 => \gpr1.dout_i_reg[1]\,
I3 => state0a_i_3_n_0,
I4 => \^rxcrcrst\,
I5 => \gv.ram_valid_d1_reg\,
O => D10_out
);
state0a_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF8"
)
port map (
I0 => waitForSfd1,
I1 => Q(2),
I2 => rxAbortRst,
I3 => rxDone,
O => state0a_i_3_n_0
);
state17a_RnM: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D11_out,
Q => \^startreaddatanib\,
R => SS(0)
);
state17a_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000200000000000"
)
port map (
I0 => rdDestAddrNib_D_t_q(3),
I1 => \rdDestAddrNib_D_t_q[0]_i_3_n_0\,
I2 => rdDestAddrNib_D_t_q(2),
I3 => Q(1),
I4 => rdDestAddrNib_D_t_q(1),
I5 => rdDestAddrNib_D_t_q(0),
O => state17a_0
);
state18a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D12_out,
Q => crcCheck,
R => SS(0)
);
state18a_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"DCDCDCD0"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => \^startreaddatanib\,
I3 => \^startreaddestadrnib\,
I4 => \^sfd1checkbusfifoempty\,
O => D12_out
);
state1a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RX_PONG_REG_GEN.pong_rx_status_reg_0\,
Q => waitForSfd1,
R => SS(0)
);
state20a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D18_out,
Q => rxDone,
R => SS(0)
);
state20a_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^crcokr1\,
I1 => crcCheck,
O => D18_out
);
state22a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => state22a_i_1_n_0,
Q => rxAbortRst,
R => SS(0)
);
state22a_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \gpr1.dout_i_reg[1]_0\,
I1 => crcCheck,
I2 => \^crcokr1\,
I3 => preamble_error_reg,
O => state22a_i_1_n_0
);
state22a_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFBFAFBFAFB4040"
)
port map (
I0 => \^rxcrcrst\,
I1 => checkingBroadcastAdr_reg,
I2 => checkingBroadcastAdr_reg_i_2_n_0,
I3 => state22a_i_4_n_0,
I4 => \emac_rx_rd_data_d1_reg[2]\,
I5 => \emac_rx_rd_data_d1_reg[1]\,
O => \^rddestaddrnib_d_t_q_reg[1]_0\
);
state22a_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => rdDestAddrNib_D_t_q(0),
I1 => rdDestAddrNib_D_t_q(3),
I2 => rdDestAddrNib_D_t_q(1),
I3 => rdDestAddrNib_D_t_q(2),
O => state22a_i_4_n_0
);
state2a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D5_out,
Q => \^sfd1checkbusfifoempty\,
R => SS(0)
);
state2a_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^rx_start\,
I1 => waitForSfd1,
O => state2a_0
);
state3a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D13_out,
Q => \^rx_start\,
R => SS(0)
);
state4a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D6_out,
Q => \^startreaddestadrnib\,
R => SS(0)
);
xpm_memory_base_inst_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0EFF"
)
port map (
I0 => \^rxcrcrst\,
I1 => \^rx_addr_en\,
I2 => rx_pong_ping_l,
I3 => s_axi_aresetn,
O => ena
);
\xpm_memory_base_inst_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E0FF"
)
port map (
I0 => \^rxcrcrst\,
I1 => \^rx_addr_en\,
I2 => rx_pong_ping_l,
I3 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg\
);
xpm_memory_base_inst_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => s_axi_aresetn,
I1 => \^startreaddatanib\,
I2 => \^rxcrcen_d1_reg\,
I3 => \^startreaddestadrnib\,
O => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_tx_statemachine is
port (
loopback_en_reg : out STD_LOGIC;
transmit_start_reg_reg_0 : out STD_LOGIC;
ldLngthCntr : out STD_LOGIC;
enblPreamble : out STD_LOGIC;
checkBusFifoFull : out STD_LOGIC;
enblData : out STD_LOGIC;
checkBusFifoFullCrc : out STD_LOGIC;
enblCRC : out STD_LOGIC;
waitFifoEmpty : out STD_LOGIC;
STATE24A_0 : out STD_LOGIC;
tx_en_i : out STD_LOGIC;
mac_addr_ram_we : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\emac_tx_wr_data_d1_reg[3]\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[2]\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[1]\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[0]\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[0]_0\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[1]_0\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[3]_0\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[2]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
CE : out STD_LOGIC;
S : out STD_LOGIC;
\txNibbleCnt_pad_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
txComboBusFifoWrCntRst : out STD_LOGIC;
axi_phy_tx_en_i_p0 : out STD_LOGIC;
CE_0 : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
txCrcEn : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ : out STD_LOGIC;
\PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ : out STD_LOGIC;
\PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ : out STD_LOGIC;
emac_tx_wr_i : out STD_LOGIC;
S_1 : out STD_LOGIC;
\PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ : out STD_LOGIC;
\PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ : out STD_LOGIC;
txComboNibbleCntRst : out STD_LOGIC;
Rst0 : out STD_LOGIC;
\txbuffer_addr_reg[0]\ : out STD_LOGIC;
\PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ : out STD_LOGIC;
\status_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\status_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
loopback_en_reg_0 : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : out STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : out STD_LOGIC;
tx_addr_en : out STD_LOGIC;
mac_addr_ram_addr_wr : out STD_LOGIC_VECTOR ( 0 to 3 );
s_axi_aclk : in STD_LOGIC;
D13_out : in STD_LOGIC;
D21_out : in STD_LOGIC;
\PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\ : in STD_LOGIC;
\PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\ : in STD_LOGIC;
D18_out : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
emac_tx_wr_d1 : in STD_LOGIC;
txCrcEn_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
douta : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\txNibbleCnt_pad_reg[11]_0\ : in STD_LOGIC;
\txNibbleCnt_pad_reg[11]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\tx_packet_length_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
txNibbleCnt_pad0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\tx_packet_length_reg[9]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_1\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
STATE14A_0 : in STD_LOGIC;
currentTxBusFifoWrCnt : in STD_LOGIC_VECTOR ( 3 downto 0 );
crcCnt : in STD_LOGIC_VECTOR ( 0 to 3 );
tx_done_d2 : in STD_LOGIC;
ping_mac_program_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
p_17_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\TX_PONG_REG_GEN.pong_mac_program_reg\ : in STD_LOGIC;
p_15_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_2\ : in STD_LOGIC;
txfifo_empty : in STD_LOGIC;
\thisState_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rx_pong_ping_l : in STD_LOGIC;
rx_done_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_intr_en0 : in STD_LOGIC;
loopback_en_reg_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_tx_statemachine : entity is "tx_statemachine";
end system_axi_ethernetlite_0_0_tx_statemachine;
architecture STRUCTURE of system_axi_ethernetlite_0_0_tx_statemachine is
signal D11_out : STD_LOGIC;
signal D12_out : STD_LOGIC;
signal D14_out : STD_LOGIC;
signal D15_out : STD_LOGIC;
signal D16_out : STD_LOGIC;
signal D17_out : STD_LOGIC;
signal D19_out : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[0]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[0]_i_2_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[0]_i_3_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[1]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[2]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[2]_i_2_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[2]_i_3_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[3]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[3]_i_2_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[3]_i_3_n_0\ : STD_LOGIC;
signal Mac_addr_ram_we0 : STD_LOGIC;
signal Mac_addr_ram_we_i_2_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_3_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_4_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_5_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_6_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_7_n_0 : STD_LOGIC;
signal STATE0A_i_2_n_0 : STD_LOGIC;
signal \^state24a_0\ : STD_LOGIC;
signal STATE26A_i_1_n_0 : STD_LOGIC;
signal axi_fifo_tx_en : STD_LOGIC;
signal busFifoWrCntRst_reg : STD_LOGIC;
signal \^checkbusfifofull\ : STD_LOGIC;
signal \^checkbusfifofullcrc\ : STD_LOGIC;
signal checkBusFifoFullSFD : STD_LOGIC;
signal checkCrc : STD_LOGIC;
signal chgMacAdr1 : STD_LOGIC;
signal chgMacAdr10 : STD_LOGIC;
signal chgMacAdr11 : STD_LOGIC;
signal chgMacAdr12 : STD_LOGIC;
signal chgMacAdr13 : STD_LOGIC;
signal chgMacAdr14 : STD_LOGIC;
signal chgMacAdr2 : STD_LOGIC;
signal chgMacAdr3 : STD_LOGIC;
signal chgMacAdr4 : STD_LOGIC;
signal chgMacAdr5 : STD_LOGIC;
signal chgMacAdr6 : STD_LOGIC;
signal chgMacAdr7 : STD_LOGIC;
signal chgMacAdr8 : STD_LOGIC;
signal chgMacAdr9 : STD_LOGIC;
signal \^enblcrc\ : STD_LOGIC;
signal \^enbldata\ : STD_LOGIC;
signal \^enblpreamble\ : STD_LOGIC;
signal enblSFD : STD_LOGIC;
signal \^ldlngthcntr\ : STD_LOGIC;
signal lngthDelay1 : STD_LOGIC;
signal lngthDelay2 : STD_LOGIC;
signal \^loopback_en_reg\ : STD_LOGIC;
signal mac_program_start : STD_LOGIC;
signal mac_program_start_reg : STD_LOGIC;
signal transmit_start : STD_LOGIC;
signal transmit_start_reg : STD_LOGIC;
signal \^transmit_start_reg_reg_0\ : STD_LOGIC;
signal txBusFifoWrCntRst : STD_LOGIC;
signal txDone2 : STD_LOGIC;
signal txDonePause : STD_LOGIC;
signal \^tx_en_i\ : STD_LOGIC;
signal txcrcen_d1_i_2_n_0 : STD_LOGIC;
signal \^waitfifoempty\ : STD_LOGIC;
signal xpm_memory_base_inst_i_4_n_0 : STD_LOGIC;
signal xpm_memory_base_inst_i_6_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[0]_i_2\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[0]_i_3\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[1]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[2]_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[3]_i_1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of Mac_addr_ram_we_i_1 : label is "soft_lutpair78";
attribute SOFT_HLUTNM of Mac_addr_ram_we_i_3 : label is "soft_lutpair63";
attribute SOFT_HLUTNM of Mac_addr_ram_we_i_5 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_i_1__0\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \PERBIT_GEN[11].MULT_AND_i1_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1_i_1\ : label is "soft_lutpair66";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of STATE0A : label is "FDS";
attribute box_type : string;
attribute box_type of STATE0A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE10A : label is "FDR";
attribute box_type of STATE10A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE11A : label is "FDR";
attribute box_type of STATE11A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE12A : label is "FDR";
attribute box_type of STATE12A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE13A : label is "FDR";
attribute box_type of STATE13A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE14A : label is "FDR";
attribute box_type of STATE14A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE15A : label is "FDR";
attribute box_type of STATE15A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE16A : label is "FDR";
attribute box_type of STATE16A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE17A : label is "FDR";
attribute box_type of STATE17A : label is "PRIMITIVE";
attribute SOFT_HLUTNM of STATE17A_i_1 : label is "soft_lutpair76";
attribute XILINX_LEGACY_PRIM of STATE24A : label is "FDR";
attribute box_type of STATE24A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE25A : label is "FDR";
attribute box_type of STATE25A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE26A : label is "FDR";
attribute box_type of STATE26A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE27A : label is "FDR";
attribute box_type of STATE27A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE28A : label is "FDR";
attribute box_type of STATE28A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE29A : label is "FDR";
attribute box_type of STATE29A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE30A : label is "FDR";
attribute box_type of STATE30A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE31A : label is "FDR";
attribute box_type of STATE31A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE32A : label is "FDR";
attribute box_type of STATE32A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE33A : label is "FDR";
attribute box_type of STATE33A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE34A : label is "FDR";
attribute box_type of STATE34A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE35A : label is "FDR";
attribute box_type of STATE35A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE36A : label is "FDR";
attribute box_type of STATE36A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE37A : label is "FDR";
attribute box_type of STATE37A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE38A : label is "FDR";
attribute box_type of STATE38A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE39A : label is "FDR";
attribute box_type of STATE39A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE5A : label is "FDR";
attribute box_type of STATE5A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE6A : label is "FDR";
attribute box_type of STATE6A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE7A : label is "FDR";
attribute box_type of STATE7A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE8A : label is "FDR";
attribute box_type of STATE8A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE9A : label is "FDR";
attribute box_type of STATE9A : label is "PRIMITIVE";
attribute SOFT_HLUTNM of axi_phy_tx_en_i_p_i_1 : label is "soft_lutpair67";
attribute SOFT_HLUTNM of mac_program_start_reg_i_1 : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \nibData[31]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of pipeIt_i_1 : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \status_reg[0]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \status_reg[1]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \status_reg[2]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \status_reg[3]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \status_reg[4]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \status_reg[5]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \status_reg[5]_i_2\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of transmit_start_reg_i_1 : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \txNibbleCnt_pad[11]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \txNibbleCnt_pad[4]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \txNibbleCnt_pad[8]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \txNibbleCnt_pad[9]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \txbuffer_addr[11]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \txbuffer_addr[11]_i_2\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of txcrcen_d1_i_2 : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_1__2\ : label is "soft_lutpair77";
begin
STATE24A_0 <= \^state24a_0\;
checkBusFifoFull <= \^checkbusfifofull\;
checkBusFifoFullCrc <= \^checkbusfifofullcrc\;
enblCRC <= \^enblcrc\;
enblData <= \^enbldata\;
enblPreamble <= \^enblpreamble\;
ldLngthCntr <= \^ldlngthcntr\;
loopback_en_reg <= \^loopback_en_reg\;
transmit_start_reg_reg_0 <= \^transmit_start_reg_reg_0\;
tx_en_i <= \^tx_en_i\;
waitFifoEmpty <= \^waitfifoempty\;
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F5F7FFF7"
)
port map (
I0 => \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
I1 => douta(3),
I2 => \^loopback_en_reg\,
I3 => tx_pong_ping_l,
I4 => \gen_wr_b.gen_word_wide.mem_reg_1\(3),
I5 => enblSFD,
O => \emac_tx_wr_data_d1_reg[0]_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^enbldata\,
I1 => \txNibbleCnt_pad_reg[11]_0\,
O => \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => Q(3),
O => \emac_tx_wr_data_d1_reg[0]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A2AAA2AAAAAAAA"
)
port map (
I0 => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
I1 => douta(2),
I2 => \^loopback_en_reg\,
I3 => tx_pong_ping_l,
I4 => \gen_wr_b.gen_word_wide.mem_reg_1\(2),
I5 => \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
O => \emac_tx_wr_data_d1_reg[1]_0\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => enblSFD,
I1 => \^enblpreamble\,
O => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => Q(2),
O => \emac_tx_wr_data_d1_reg[1]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBBFFFFBFFF"
)
port map (
I0 => \txNibbleCnt_pad_reg[11]_0\,
I1 => \^enbldata\,
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(1),
I3 => tx_pong_ping_l,
I4 => \^loopback_en_reg\,
I5 => douta(1),
O => \emac_tx_wr_data_d1_reg[2]_0\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => Q(1),
O => \emac_tx_wr_data_d1_reg[2]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A2AAA2AAAAAAAA"
)
port map (
I0 => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
I1 => douta(0),
I2 => \^loopback_en_reg\,
I3 => tx_pong_ping_l,
I4 => \gen_wr_b.gen_word_wide.mem_reg_1\(0),
I5 => \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
O => \emac_tx_wr_data_d1_reg[3]_0\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => Q(0),
O => \emac_tx_wr_data_d1_reg[3]\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1110"
)
port map (
I0 => \^state24a_0\,
I1 => \^loopback_en_reg\,
I2 => axi_fifo_tx_en,
I3 => \^enblpreamble\,
O => \^tx_en_i\
);
IP2INTC_IRPT_REG_I_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^transmit_start_reg_reg_0\
);
\Mac_addr_ram_addr_wr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFE"
)
port map (
I0 => chgMacAdr10,
I1 => chgMacAdr11,
I2 => chgMacAdr13,
I3 => chgMacAdr12,
I4 => \Mac_addr_ram_addr_wr[0]_i_2_n_0\,
I5 => \Mac_addr_ram_addr_wr[0]_i_3_n_0\,
O => \Mac_addr_ram_addr_wr[0]_i_1_n_0\
);
\Mac_addr_ram_addr_wr[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => chgMacAdr7,
I1 => chgMacAdr6,
I2 => chgMacAdr9,
I3 => chgMacAdr8,
O => \Mac_addr_ram_addr_wr[0]_i_2_n_0\
);
\Mac_addr_ram_addr_wr[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => chgMacAdr4,
I1 => chgMacAdr5,
I2 => Mac_addr_ram_we_i_3_n_0,
I3 => chgMacAdr2,
I4 => chgMacAdr3,
O => \Mac_addr_ram_addr_wr[0]_i_3_n_0\
);
\Mac_addr_ram_addr_wr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => chgMacAdr8,
I1 => chgMacAdr9,
I2 => chgMacAdr6,
I3 => chgMacAdr7,
I4 => \Mac_addr_ram_addr_wr[0]_i_3_n_0\,
O => \Mac_addr_ram_addr_wr[1]_i_1_n_0\
);
\Mac_addr_ram_addr_wr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFF01"
)
port map (
I0 => chgMacAdr7,
I1 => chgMacAdr6,
I2 => \Mac_addr_ram_addr_wr[2]_i_2_n_0\,
I3 => chgMacAdr5,
I4 => chgMacAdr4,
I5 => \Mac_addr_ram_addr_wr[2]_i_3_n_0\,
O => \Mac_addr_ram_addr_wr[2]_i_1_n_0\
);
\Mac_addr_ram_addr_wr[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1110111011101111"
)
port map (
I0 => chgMacAdr9,
I1 => chgMacAdr8,
I2 => chgMacAdr10,
I3 => chgMacAdr11,
I4 => chgMacAdr13,
I5 => chgMacAdr12,
O => \Mac_addr_ram_addr_wr[2]_i_2_n_0\
);
\Mac_addr_ram_addr_wr[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => chgMacAdr3,
I1 => chgMacAdr2,
I2 => STATE0A_i_2_n_0,
I3 => txDonePause,
I4 => s_axi_aresetn,
O => \Mac_addr_ram_addr_wr[2]_i_3_n_0\
);
\Mac_addr_ram_addr_wr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \Mac_addr_ram_addr_wr[3]_i_2_n_0\,
I1 => Mac_addr_ram_we_i_3_n_0,
I2 => chgMacAdr2,
O => \Mac_addr_ram_addr_wr[3]_i_1_n_0\
);
\Mac_addr_ram_addr_wr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABBBABBBABBBABA"
)
port map (
I0 => chgMacAdr3,
I1 => chgMacAdr4,
I2 => chgMacAdr5,
I3 => chgMacAdr6,
I4 => chgMacAdr7,
I5 => \Mac_addr_ram_addr_wr[3]_i_3_n_0\,
O => \Mac_addr_ram_addr_wr[3]_i_2_n_0\
);
\Mac_addr_ram_addr_wr[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF00F2"
)
port map (
I0 => chgMacAdr13,
I1 => chgMacAdr12,
I2 => chgMacAdr11,
I3 => chgMacAdr10,
I4 => chgMacAdr9,
I5 => chgMacAdr8,
O => \Mac_addr_ram_addr_wr[3]_i_3_n_0\
);
\Mac_addr_ram_addr_wr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Mac_addr_ram_addr_wr[0]_i_1_n_0\,
Q => mac_addr_ram_addr_wr(0),
R => '0'
);
\Mac_addr_ram_addr_wr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Mac_addr_ram_addr_wr[1]_i_1_n_0\,
Q => mac_addr_ram_addr_wr(1),
R => '0'
);
\Mac_addr_ram_addr_wr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Mac_addr_ram_addr_wr[2]_i_1_n_0\,
Q => mac_addr_ram_addr_wr(2),
R => '0'
);
\Mac_addr_ram_addr_wr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Mac_addr_ram_addr_wr[3]_i_1_n_0\,
Q => mac_addr_ram_addr_wr(3),
R => '0'
);
Mac_addr_ram_we_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Mac_addr_ram_we_i_2_n_0,
I1 => Mac_addr_ram_we_i_3_n_0,
O => Mac_addr_ram_we0
);
Mac_addr_ram_we_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFFFFFFFF"
)
port map (
I0 => Mac_addr_ram_we_i_4_n_0,
I1 => Mac_addr_ram_we_i_5_n_0,
I2 => Mac_addr_ram_we_i_6_n_0,
I3 => chgMacAdr3,
I4 => chgMacAdr2,
I5 => Mac_addr_ram_we_i_7_n_0,
O => Mac_addr_ram_we_i_2_n_0
);
Mac_addr_ram_we_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => txDonePause,
I2 => STATE0A_i_2_n_0,
O => Mac_addr_ram_we_i_3_n_0
);
Mac_addr_ram_we_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => chgMacAdr12,
I1 => chgMacAdr13,
I2 => chgMacAdr11,
I3 => chgMacAdr10,
O => Mac_addr_ram_we_i_4_n_0
);
Mac_addr_ram_we_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => chgMacAdr5,
I1 => chgMacAdr4,
O => Mac_addr_ram_we_i_5_n_0
);
Mac_addr_ram_we_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => chgMacAdr8,
I1 => chgMacAdr9,
O => Mac_addr_ram_we_i_6_n_0
);
Mac_addr_ram_we_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => chgMacAdr6,
I1 => chgMacAdr7,
O => Mac_addr_ram_we_i_7_n_0
);
Mac_addr_ram_we_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Mac_addr_ram_we0,
Q => mac_addr_ram_we,
R => '0'
);
\PERBIT_GEN[0].XORCY_i1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => crcCnt(0),
O => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[10].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => currentTxBusFifoWrCnt(1),
I1 => \^enbldata\,
I2 => \^enblpreamble\,
I3 => enblSFD,
I4 => \^enblcrc\,
O => \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF2FFFF"
)
port map (
I0 => busFifoWrCntRst_reg,
I1 => \^enblpreamble\,
I2 => \^loopback_en_reg\,
I3 => \^state24a_0\,
I4 => s_axi_aresetn,
I5 => txDonePause,
O => txComboBusFifoWrCntRst
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => \^loopback_en_reg\,
I1 => s_axi_aresetn,
I2 => txDonePause,
O => txComboNibbleCntRst
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^enbldata\,
I1 => enblSFD,
O => CE
);
\PERBIT_GEN[11].MULT_AND_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^enbldata\,
I1 => \^enblpreamble\,
I2 => enblSFD,
I3 => \^enblcrc\,
O => emac_tx_wr_i
);
\PERBIT_GEN[11].MUXCY_i1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^enbldata\,
I1 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\(0),
O => S
);
\PERBIT_GEN[11].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => currentTxBusFifoWrCnt(0),
I1 => \^enbldata\,
I2 => \^enblpreamble\,
I3 => enblSFD,
I4 => \^enblcrc\,
O => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\
);
\PERBIT_GEN[1].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^enblcrc\,
I1 => crcCnt(1),
O => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[2].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^enblcrc\,
I1 => crcCnt(2),
O => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFAB"
)
port map (
I0 => \^enblcrc\,
I1 => \^enblpreamble\,
I2 => axi_fifo_tx_en,
I3 => \^loopback_en_reg\,
I4 => \^state24a_0\,
O => CE_0
);
\PERBIT_GEN[3].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^enblcrc\,
I1 => crcCnt(3),
O => S_1
);
\PERBIT_GEN[8].XORCY_i1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => currentTxBusFifoWrCnt(3),
I1 => \^enbldata\,
I2 => \^enblpreamble\,
I3 => enblSFD,
I4 => \^enblcrc\,
O => \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\
);
\PERBIT_GEN[9].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => currentTxBusFifoWrCnt(2),
I1 => \^enbldata\,
I2 => \^enblpreamble\,
I3 => enblSFD,
I4 => \^enblcrc\,
O => \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\
);
STATE0A: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => \^loopback_en_reg\,
S => \^transmit_start_reg_reg_0\
);
STATE0A_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => txDonePause,
I1 => STATE0A_i_2_n_0,
O => D_0
);
STATE0A_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000088808CC08CC"
)
port map (
I0 => tx_done_d2,
I1 => \^loopback_en_reg\,
I2 => ping_mac_program_reg(0),
I3 => p_17_in(0),
I4 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I5 => p_15_in(0),
O => STATE0A_i_2_n_0
);
STATE10A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D15_out,
Q => enblSFD,
R => \^transmit_start_reg_reg_0\
);
STATE10A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \out\,
I1 => checkBusFifoFullSFD,
I2 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_1\,
I3 => enblSFD,
O => D15_out
);
STATE11A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D16_out,
Q => \^checkbusfifofull\,
R => \^transmit_start_reg_reg_0\
);
STATE11A_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF444F444F444"
)
port map (
I0 => \PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\,
I1 => \^enbldata\,
I2 => \^checkbusfifofull\,
I3 => \out\,
I4 => enblSFD,
I5 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_1\,
O => D16_out
);
STATE12A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D21_out,
Q => \^enbldata\,
R => \^transmit_start_reg_reg_0\
);
STATE13A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\,
Q => checkCrc,
R => \^transmit_start_reg_reg_0\
);
STATE14A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D17_out,
Q => \^checkbusfifofullcrc\,
R => \^transmit_start_reg_reg_0\
);
STATE14A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF8"
)
port map (
I0 => \out\,
I1 => \^checkbusfifofullcrc\,
I2 => checkCrc,
I3 => \^enblcrc\,
O => D17_out
);
STATE15A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\,
Q => \^enblcrc\,
R => \^transmit_start_reg_reg_0\
);
STATE16A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D18_out,
Q => \^waitfifoempty\,
R => \^transmit_start_reg_reg_0\
);
STATE17A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D19_out,
Q => \^state24a_0\,
R => \^transmit_start_reg_reg_0\
);
STATE17A_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => chgMacAdr14,
I1 => txfifo_empty,
I2 => \^waitfifoempty\,
O => D19_out
);
STATE24A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^state24a_0\,
Q => txDone2,
R => \^transmit_start_reg_reg_0\
);
STATE25A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => txDone2,
Q => txDonePause,
R => \^transmit_start_reg_reg_0\
);
STATE26A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => STATE26A_i_1_n_0,
Q => chgMacAdr1,
R => \^transmit_start_reg_reg_0\
);
STATE26A_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F8880000"
)
port map (
I0 => p_15_in(0),
I1 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I2 => p_17_in(0),
I3 => ping_mac_program_reg(0),
I4 => \^loopback_en_reg\,
I5 => mac_program_start_reg,
O => STATE26A_i_1_n_0
);
STATE27A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr1,
Q => chgMacAdr2,
R => \^transmit_start_reg_reg_0\
);
STATE28A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr2,
Q => chgMacAdr3,
R => \^transmit_start_reg_reg_0\
);
STATE29A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr3,
Q => chgMacAdr4,
R => \^transmit_start_reg_reg_0\
);
STATE30A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr4,
Q => chgMacAdr5,
R => \^transmit_start_reg_reg_0\
);
STATE31A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr5,
Q => chgMacAdr6,
R => \^transmit_start_reg_reg_0\
);
STATE32A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr6,
Q => chgMacAdr7,
R => \^transmit_start_reg_reg_0\
);
STATE33A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr7,
Q => chgMacAdr8,
R => \^transmit_start_reg_reg_0\
);
STATE34A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr8,
Q => chgMacAdr9,
R => \^transmit_start_reg_reg_0\
);
STATE35A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr9,
Q => chgMacAdr10,
R => \^transmit_start_reg_reg_0\
);
STATE36A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr10,
Q => chgMacAdr11,
R => \^transmit_start_reg_reg_0\
);
STATE37A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr11,
Q => chgMacAdr12,
R => \^transmit_start_reg_reg_0\
);
STATE38A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr12,
Q => chgMacAdr13,
R => \^transmit_start_reg_reg_0\
);
STATE39A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr13,
Q => chgMacAdr14,
R => \^transmit_start_reg_reg_0\
);
STATE5A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D11_out,
Q => lngthDelay1,
R => \^transmit_start_reg_reg_0\
);
STATE5A_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => transmit_start,
I1 => \^loopback_en_reg\,
I2 => transmit_start_reg,
O => D11_out
);
STATE6A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => lngthDelay1,
Q => lngthDelay2,
R => \^transmit_start_reg_reg_0\
);
STATE7A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D12_out,
Q => \^ldlngthcntr\,
R => \^transmit_start_reg_reg_0\
);
STATE7A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BFAA"
)
port map (
I0 => lngthDelay1,
I1 => \thisState_reg[1]\(0),
I2 => \thisState_reg[1]\(1),
I3 => \^ldlngthcntr\,
O => D12_out
);
STATE8A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D13_out,
Q => \^enblpreamble\,
R => \^transmit_start_reg_reg_0\
);
STATE9A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D14_out,
Q => checkBusFifoFullSFD,
R => \^transmit_start_reg_reg_0\
);
STATE9A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_2\,
I1 => \^enblpreamble\,
I2 => \out\,
I3 => checkBusFifoFullSFD,
O => D14_out
);
axi_phy_tx_en_i_p_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => axi_fifo_tx_en,
I1 => \^state24a_0\,
I2 => \^loopback_en_reg\,
O => axi_phy_tx_en_i_p0
);
busFifoWrCntRst_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => \^state24a_0\,
I1 => \^loopback_en_reg\,
I2 => \^enblpreamble\,
I3 => busFifoWrCntRst_reg,
O => txBusFifoWrCntRst
);
busFifoWrCntRst_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => txBusFifoWrCntRst,
Q => busFifoWrCntRst_reg,
R => \^transmit_start_reg_reg_0\
);
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555554"
)
port map (
I0 => ram_full_fb_i_reg,
I1 => STATE14A_0,
I2 => \^enblcrc\,
I3 => enblSFD,
I4 => \^enblpreamble\,
I5 => \^enbldata\,
O => \gic0.gc0.count_reg[0]\(0)
);
loopback_en_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => s_axi_wdata(0),
I1 => tx_intr_en0,
I2 => \^loopback_en_reg\,
I3 => loopback_en_reg_1,
O => loopback_en_reg_0
);
mac_program_start_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => ping_mac_program_reg(0),
I1 => p_17_in(0),
I2 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I3 => p_15_in(0),
O => mac_program_start
);
mac_program_start_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_program_start,
Q => mac_program_start_reg,
R => \^transmit_start_reg_reg_0\
);
\nibData[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF57"
)
port map (
I0 => s_axi_aresetn,
I1 => \^enblpreamble\,
I2 => axi_fifo_tx_en,
I3 => \^loopback_en_reg\,
I4 => \^state24a_0\,
O => SR(0)
);
\nibData[31]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => emac_tx_wr_d1,
I1 => \^checkbusfifofullcrc\,
I2 => \^enblcrc\,
I3 => txCrcEn_reg,
O => E(0)
);
phytx_en_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^tx_en_i\,
Q => axi_fifo_tx_en,
R => \^transmit_start_reg_reg_0\
);
pipeIt_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => txDonePause,
I1 => s_axi_aresetn,
O => Rst0
);
\status_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I1 => tx_pong_ping_l,
I2 => s_axi_aresetn,
I3 => \^state24a_0\,
O => \status_reg_reg[5]\(0)
);
\status_reg[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => ping_mac_program_reg(0),
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
I3 => tx_pong_ping_l,
O => \status_reg_reg[5]\(1)
);
\status_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => rx_pong_ping_l,
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
O => \status_reg_reg[5]\(2)
);
\status_reg[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => rx_pong_ping_l,
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
O => \status_reg_reg[5]\(3)
);
\status_reg[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I1 => tx_pong_ping_l,
I2 => s_axi_aresetn,
I3 => \^state24a_0\,
O => \status_reg_reg[5]\(4)
);
\status_reg[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => rx_done_d1,
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
O => \status_reg_reg[0]\(0)
);
\status_reg[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => ping_mac_program_reg(0),
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
I3 => tx_pong_ping_l,
O => \status_reg_reg[5]\(5)
);
transmit_start_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000044F4"
)
port map (
I0 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I1 => p_15_in(0),
I2 => p_17_in(0),
I3 => ping_mac_program_reg(0),
I4 => tx_done_d2,
O => transmit_start
);
transmit_start_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => transmit_start,
Q => transmit_start_reg,
R => \^transmit_start_reg_reg_0\
);
\txNibbleCnt_pad[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => enblSFD,
I1 => \tx_packet_length_reg[9]\,
I2 => \^enbldata\,
O => \txNibbleCnt_pad_reg[11]\(0)
);
\txNibbleCnt_pad[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(10),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(10),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(11)
);
\txNibbleCnt_pad[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(0),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(0),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(1)
);
\txNibbleCnt_pad[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => enblSFD,
I1 => \txNibbleCnt_pad_reg[11]_1\(0),
I2 => \txNibbleCnt_pad_reg[11]_0\,
O => D(0)
);
\txNibbleCnt_pad[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(9),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(9),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(10)
);
\txNibbleCnt_pad[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(8),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(8),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(9)
);
\txNibbleCnt_pad[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(7),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(7),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(8)
);
\txNibbleCnt_pad[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(6),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(6),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(7)
);
\txNibbleCnt_pad[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(5),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(5),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(6)
);
\txNibbleCnt_pad[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(4),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(4),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(5)
);
\txNibbleCnt_pad[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(3),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(3),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(4)
);
\txNibbleCnt_pad[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(2),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(2),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(3)
);
\txNibbleCnt_pad[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(1),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(1),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(2)
);
\txbuffer_addr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => \^enblpreamble\,
I1 => s_axi_aresetn,
I2 => chgMacAdr1,
O => \txbuffer_addr_reg[0]\
);
\txbuffer_addr[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => chgMacAdr14,
I1 => Mac_addr_ram_we_i_2_n_0,
I2 => \^enbldata\,
O => tx_addr_en
);
txcrcen_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAEAAAAAAAA"
)
port map (
I0 => \^checkbusfifofull\,
I1 => txCrcEn_reg,
I2 => checkBusFifoFullSFD,
I3 => \^loopback_en_reg\,
I4 => \^checkbusfifofullcrc\,
I5 => txcrcen_d1_i_2_n_0,
O => txCrcEn
);
txcrcen_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^enblpreamble\,
I1 => enblSFD,
I2 => \^enblcrc\,
O => txcrcen_d1_i_2_n_0
);
\xpm_memory_base_inst_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xpm_memory_base_inst_i_4_n_0,
I1 => tx_pong_ping_l,
I2 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg\
);
\xpm_memory_base_inst_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => xpm_memory_base_inst_i_4_n_0,
I1 => tx_pong_ping_l,
I2 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg_0\
);
xpm_memory_base_inst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => chgMacAdr14,
I1 => Mac_addr_ram_we_i_2_n_0,
I2 => xpm_memory_base_inst_i_6_n_0,
I3 => txDone2,
I4 => lngthDelay2,
I5 => \^checkbusfifofull\,
O => xpm_memory_base_inst_i_4_n_0
);
xpm_memory_base_inst_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^ldlngthcntr\,
I1 => lngthDelay1,
I2 => txDonePause,
I3 => chgMacAdr1,
I4 => \^loopback_en_reg\,
I5 => \^state24a_0\,
O => xpm_memory_base_inst_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_base is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute VERSION : integer;
attribute VERSION of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "TRUE";
end system_axi_ethernetlite_0_0_xpm_memory_base;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_base is
signal \<const0>\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "COMMON";
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "{SYNTH-6 {cell *THIS*}} {SYNTH-7 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_b.gen_word_wide.mem_reg\ : label is 16384;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_b.gen_word_wide.mem_reg\ : label is "gen_wr_b.gen_word_wide.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_b.gen_word_wide.mem_reg\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 5) => addrb(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => dinb(31 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\,
ENBWREN => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\,
INJECTDBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\,
WEA(3) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(2) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(1) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(0) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(2) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(1) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(0) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rsta,
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rstb,
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => wea(0),
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => web(0),
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_xpm_memory_base__4\ is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "TRUE";
end \system_axi_ethernetlite_0_0_xpm_memory_base__4\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ is
signal \<const0>\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "COMMON";
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "{SYNTH-6 {cell *THIS*}} {SYNTH-7 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_b.gen_word_wide.mem_reg\ : label is 16384;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_b.gen_word_wide.mem_reg\ : label is "gen_wr_b.gen_word_wide.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_b.gen_word_wide.mem_reg\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 5) => addrb(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => dinb(31 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\,
ENBWREN => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\,
INJECTDBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\,
WEA(3) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(2) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(1) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(0) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(2) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(1) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(0) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rsta,
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rstb,
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => wea(0),
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => web(0),
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_xpm_memory_base__5\ is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "TRUE";
end \system_axi_ethernetlite_0_0_xpm_memory_base__5\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ is
signal \<const0>\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "COMMON";
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "{SYNTH-6 {cell *THIS*}} {SYNTH-7 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_b.gen_word_wide.mem_reg\ : label is 16384;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_b.gen_word_wide.mem_reg\ : label is "gen_wr_b.gen_word_wide.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_b.gen_word_wide.mem_reg\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 5) => addrb(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => dinb(31 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\,
ENBWREN => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\,
INJECTDBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\,
WEA(3) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(2) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(1) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(0) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(2) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(1) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(0) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rsta,
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rstb,
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => wea(0),
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => web(0),
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_xpm_memory_base__6\ is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "TRUE";
end \system_axi_ethernetlite_0_0_xpm_memory_base__6\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ is
signal \<const0>\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "COMMON";
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "{SYNTH-6 {cell *THIS*}} {SYNTH-7 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_b.gen_word_wide.mem_reg\ : label is 16384;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_b.gen_word_wide.mem_reg\ : label is "gen_wr_b.gen_word_wide.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_b.gen_word_wide.mem_reg\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 5) => addrb(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => dinb(31 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\,
ENBWREN => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\,
INJECTDBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\,
WEA(3) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(2) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(1) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(0) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(2) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(1) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(0) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rsta,
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rstb,
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => wea(0),
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => web(0),
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_dmem is
port (
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_phy_tx_en_i_p : in STD_LOGIC;
fifo_tx_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_dmem : entity is "dmem";
end system_axi_ethernetlite_0_0_dmem;
architecture STRUCTURE of system_axi_ethernetlite_0_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal bus_combo : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(0),
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\
);
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1) => '0',
DIA(0) => DIA(0),
DIB(1 downto 0) => D(1 downto 0),
DIC(1 downto 0) => D(3 downto 2),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_axi_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_1,
Q => bus_combo(0)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(0)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(1)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(2)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_dmem_27 is
port (
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
CLK : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
startReadDestAdrNib : in STD_LOGIC;
\gv.ram_valid_d1_reg\ : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\out\ : in STD_LOGIC;
state0a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_dmem_27 : entity is "dmem";
end system_axi_ethernetlite_0_0_dmem_27;
architecture STRUCTURE of system_axi_ethernetlite_0_0_dmem_27 is
signal \^d\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal \^state2a\ : STD_LOGIC;
signal state2a_i_2_n_0 : STD_LOGIC;
signal state3a_i_2_n_0 : STD_LOGIC;
signal state4a_i_2_n_0 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \crc_local[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \crc_local[13]_i_2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of preamble_i_1 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of state0a_i_2 : label is "soft_lutpair28";
attribute SOFT_HLUTNM of state3a_i_2 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of state4a_i_2 : label is "soft_lutpair29";
begin
D(6 downto 0) <= \^d\(6 downto 0);
Q(5 downto 0) <= \^q\(5 downto 0);
state2a <= \^state2a\;
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => CLK,
WE => E(0)
);
busFifoData_is_5_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(2),
I2 => \^q\(4),
I3 => \^q\(3),
I4 => \gv.ram_valid_d1_reg\,
I5 => busFifoData_is_5_d1,
O => busFifoData_is_5_d1_reg
);
\crc_local[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(5),
I1 => \crc_local_reg[31]\(6),
O => \^d\(0)
);
\crc_local[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(3),
I1 => \crc_local_reg[31]\(8),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(4),
O => \^d\(5)
);
\crc_local[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(4),
I1 => \crc_local_reg[31]\(7),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(5),
O => \^d\(6)
);
\crc_local[13]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \crc_local_reg[31]\(9),
O => \crc_local_reg[13]\
);
\crc_local[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^d\(0),
I1 => \^q\(2),
I2 => \crc_local_reg[31]\(9),
I3 => \^q\(3),
I4 => \crc_local_reg[31]\(8),
I5 => \crc_local_reg[31]\(0),
O => \^d\(1)
);
\crc_local[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(4),
I1 => \crc_local_reg[31]\(7),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(1),
O => \^d\(2)
);
\crc_local[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(3),
I1 => \crc_local_reg[31]\(8),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(2),
O => \^d\(3)
);
\crc_local[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(4),
I1 => \crc_local_reg[31]\(7),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(3),
O => \^d\(4)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_1,
Q => \^q\(0)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_0,
Q => \^q\(1)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_3,
Q => \^q\(2)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_2,
Q => \^q\(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_5,
Q => \^q\(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_4,
Q => \^q\(5)
);
preamble_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F7000000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(4),
I2 => \^q\(3),
I3 => rx_start,
I4 => busFifoData_is_5_d1,
O => preamble
);
state0a_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
I2 => \^q\(4),
I3 => \^q\(3),
O => \^state2a\
);
state17a_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => startReadDataNib,
I3 => \rdDestAddrNib_D_t_q_reg[3]_0\,
O => D11_out
);
state22a_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"005D"
)
port map (
I0 => \^q\(1),
I1 => state0a,
I2 => \out\,
I3 => \rdDestAddrNib_D_t_q_reg[3]\,
O => \rdDestAddrNib_D_t_q_reg[1]\
);
state2a_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"040404FF04040404"
)
port map (
I0 => \^q\(0),
I1 => sfd1CheckBusFifoEmpty,
I2 => state2a_i_2_n_0,
I3 => \^q\(5),
I4 => state3a,
I5 => \^state2a\,
O => D5_out
);
state2a_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000400040"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
I2 => \^q\(2),
I3 => \^q\(5),
I4 => \gv.ram_valid_d1_reg\,
I5 => \out\,
O => state2a_i_2_n_0
);
state3a_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000D0000"
)
port map (
I0 => \out\,
I1 => \gv.ram_valid_d1_reg\,
I2 => \^q\(5),
I3 => state3a_i_2_n_0,
I4 => sfd1CheckBusFifoEmpty,
I5 => \^q\(0),
O => D13_out
);
state3a_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
I2 => \^q\(2),
O => state3a_i_2_n_0
);
state4a_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AABA"
)
port map (
I0 => state4a_i_2_n_0,
I1 => \^q\(0),
I2 => startReadDestAdrNib,
I3 => \gv.ram_valid_d1_reg\,
O => D6_out
);
state4a_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^state2a\,
I1 => \^q\(5),
I2 => busFifoData_is_5_d1,
I3 => rx_start,
O => state4a_i_2_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_bin_cntr : entity is "rd_bin_cntr";
end system_axi_ethernetlite_0_0_rd_bin_cntr;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__0\ : label is "soft_lutpair60";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__2\(0)
);
\gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__2\(1)
);
\gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__2\(2)
);
\gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__2\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => E(0),
D => \plusOp__2\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_bin_cntr_31 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_bin_cntr_31 : entity is "rd_bin_cntr";
end system_axi_ethernetlite_0_0_rd_bin_cntr_31;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_bin_cntr_31 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair25";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_handshaking_flags is
port (
state1a : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
state0a : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
startReadDestAdrNib : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_handshaking_flags : entity is "rd_handshaking_flags";
end system_axi_ethernetlite_0_0_rd_handshaking_flags;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_handshaking_flags is
signal \^state1a\ : STD_LOGIC;
begin
state1a <= \^state1a\;
\gv.ram_valid_d1_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => ram_valid_i,
Q => \^state1a\
);
\rdDestAddrNib_D_t_q[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^state1a\,
I1 => startReadDestAdrNib,
I2 => Q(0),
O => goto_readDestAdrNib1
);
state0a_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0BBB"
)
port map (
I0 => \^state1a\,
I1 => \out\,
I2 => ping_rx_status_reg,
I3 => \RX_PONG_REG_GEN.pong_rx_status_reg\,
O => state0a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
fifo_tx_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_status_flags_as : entity is "rd_status_flags_as";
end system_axi_ethernetlite_0_0_rd_status_flags_as;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_i;
\gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => fifo_tx_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_status_flags_as_30 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gv.ram_valid_d1_reg\ : in STD_LOGIC;
state0a : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
ping_rx_status_reg : in STD_LOGIC;
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_status_flags_as_30 : entity is "rd_status_flags_as";
end system_axi_ethernetlite_0_0_rd_status_flags_as_30;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_status_flags_as_30 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\gpr1.dout_i_reg[0]\ <= ram_empty_fb_i;
\out\ <= ram_empty_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
PRE => AR(0),
Q => ram_empty_i
);
\rdDestAddrNib_D_t_q[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"1515FF05"
)
port map (
I0 => \rdDestAddrNib_D_t_q_reg[3]_0\,
I1 => ram_empty_i,
I2 => Q(0),
I3 => \gv.ram_valid_d1_reg\,
I4 => state0a,
O => \rdDestAddrNib_D_t_q_reg[3]\
);
state1a_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"77070000"
)
port map (
I0 => \RX_PONG_REG_GEN.pong_rx_status_reg\,
I1 => ping_rx_status_reg,
I2 => ram_empty_i,
I3 => \gv.ram_valid_d1_reg\,
I4 => rxCrcRst,
O => state1a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_10 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_10 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_10;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_23 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_23 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_23;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_23 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_24 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_24 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_24;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_24 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_25 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_25 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_25;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_25 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_26 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
CLK : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_26 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_26;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_26 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_8 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_8 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_8;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_8 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_9 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_9 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_9;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_9 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_bin_cntr : entity is "wr_bin_cntr";
end system_axi_ethernetlite_0_0_wr_bin_cntr;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_full_i_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair61";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
O => \plusOp__0\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => p_13_out(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => p_13_out(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => p_13_out(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => p_13_out(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
ram_full_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3),
I1 => p_13_out(3),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(1),
I3 => p_13_out(1),
I4 => ram_full_i_i_5_n_0,
O => ram_full_fb_i_reg
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_13_out(0),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
I2 => p_13_out(2),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(2),
O => ram_full_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_bin_cntr_29 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_bin_cntr_29 : entity is "wr_bin_cntr";
end system_axi_ethernetlite_0_0_wr_bin_cntr_29;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_bin_cntr_29 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__0\ : label is "soft_lutpair26";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_status_flags_as is
port (
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_status_flags_as : entity is "wr_status_flags_as";
end system_axi_ethernetlite_0_0_wr_status_flags_as;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
STATE16A <= ram_full_i;
\gic0.gc0.count_reg[0]\ <= ram_full_fb_i;
STATE16A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => txfifo_empty,
I1 => waitFifoEmpty,
I2 => ram_full_i,
I3 => STATE14A,
O => D18_out
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \grstd1.grst_full.grst_f.rst_d3_reg\,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \grstd1.grst_full.grst_f.rst_d3_reg\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_status_flags_as_28 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
CLK : in STD_LOGIC;
\out\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_status_flags_as_28 : entity is "wr_status_flags_as";
end system_axi_ethernetlite_0_0_wr_status_flags_as_28;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_status_flags_as_28 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_fb_i,
I1 => ram_full_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1001"
)
port map (
I0 => ram_full_i,
I1 => ram_full_fb_i,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_MacAddrRAM is
port (
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]_0\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
mac_addr_ram_we : in STD_LOGIC;
mac_addr_ram_addr : in STD_LOGIC_VECTOR ( 0 to 3 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_MacAddrRAM : entity is "MacAddrRAM";
end system_axi_ethernetlite_0_0_MacAddrRAM;
architecture STRUCTURE of system_axi_ethernetlite_0_0_MacAddrRAM is
begin
ram16x4i: entity work.system_axi_ethernetlite_0_0_ram16x4
port map (
Q(3 downto 0) => Q(3 downto 0),
\gen_wr_b.gen_word_wide.mem_reg\(3 downto 0) => \gen_wr_b.gen_word_wide.mem_reg\(3 downto 0),
mac_addr_ram_addr(0 to 3) => mac_addr_ram_addr(0 to 3),
mac_addr_ram_we => mac_addr_ram_we,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[1]_0\ => \rdDestAddrNib_D_t_q_reg[1]_0\,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_crcgentx is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
txCrcEn_reg : in STD_LOGIC;
\emac_tx_wr_data_d1_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_crcgentx : entity is "crcgentx";
end system_axi_ethernetlite_0_0_crcgentx;
architecture STRUCTURE of system_axi_ethernetlite_0_0_crcgentx is
begin
NSR: entity work.system_axi_ethernetlite_0_0_crcnibshiftreg
port map (
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
SR(0) => SR(0),
\emac_tx_wr_data_d1_reg[0]\(3 downto 0) => \emac_tx_wr_data_d1_reg[0]\(3 downto 0),
s_axi_aclk => s_axi_aclk,
txCrcEn_reg => txCrcEn_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_deferral is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D13_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_crs_d2 : in STD_LOGIC;
tx_en_i : in STD_LOGIC;
tx_clk_reg_d3 : in STD_LOGIC;
tx_clk_reg_d2 : in STD_LOGIC;
ldLngthCntr : in STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : in STD_LOGIC;
enblPreamble : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_deferral : entity is "deferral";
end system_axi_ethernetlite_0_0_deferral;
architecture STRUCTURE of system_axi_ethernetlite_0_0_deferral is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \count_reg__0\ : STD_LOGIC_VECTOR ( 3 to 4 );
signal \count_reg__0_0\ : STD_LOGIC_VECTOR ( 3 to 4 );
signal ifgp1_zero : STD_LOGIC;
signal ifgp2_zero : STD_LOGIC;
signal inst_deferral_state_n_2 : STD_LOGIC;
signal inst_deferral_state_n_3 : STD_LOGIC;
signal inst_deferral_state_n_8 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
inst_deferral_state: entity work.system_axi_ethernetlite_0_0_defer_state
port map (
D(1 downto 0) => \p_0_in__0\(1 downto 0),
D13_out => D13_out,
E(0) => inst_deferral_state_n_2,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\,
Q(1 downto 0) => \^q\(1 downto 0),
\count_reg[0]\ => inst_deferral_state_n_8,
\count_reg[3]\(1 downto 0) => p_0_in(1 downto 0),
\count_reg[3]_0\(1) => \count_reg__0_0\(3),
\count_reg[3]_0\(0) => \count_reg__0_0\(4),
\count_reg[3]_1\(1) => \count_reg__0\(3),
\count_reg[3]_1\(0) => \count_reg__0\(4),
\count_reg[4]\(0) => inst_deferral_state_n_3,
enblPreamble => enblPreamble,
ifgp1_zero => ifgp1_zero,
ifgp2_zero => ifgp2_zero,
ldLngthCntr => ldLngthCntr,
phy_crs_d2 => phy_crs_d2,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
tx_clk_reg_d2 => tx_clk_reg_d2,
tx_clk_reg_d3 => tx_clk_reg_d3,
tx_en_i => tx_en_i
);
inst_ifgp1_count: entity work.system_axi_ethernetlite_0_0_cntr5bit
port map (
D(1 downto 0) => p_0_in(1 downto 0),
E(0) => inst_deferral_state_n_3,
Q(1) => \count_reg__0\(3),
Q(0) => \count_reg__0\(4),
ifgp1_zero => ifgp1_zero,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\thisState_reg[0]\ => inst_deferral_state_n_8,
\thisState_reg[1]\(1 downto 0) => \^q\(1 downto 0)
);
inst_ifgp2_count: entity work.system_axi_ethernetlite_0_0_cntr5bit_11
port map (
D(1 downto 0) => \p_0_in__0\(1 downto 0),
E(0) => inst_deferral_state_n_2,
Q(1) => \count_reg__0_0\(3),
Q(0) => \count_reg__0_0\(4),
ifgp2_zero => ifgp2_zero,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\thisState_reg[0]\ => inst_deferral_state_n_8,
\thisState_reg[1]\(1 downto 0) => \^q\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_tdpram is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 4 downto 0 );
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 26 downto 0 );
s_axi_aclk : in STD_LOGIC;
\TX_PONG_GEN.tx_pong_ping_l_reg\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
tx_idle : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\reg_data_out_reg[0]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
reg_access_reg : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_2\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\reg_data_out_reg[1]\ : in STD_LOGIC;
p_21_in144_in : in STD_LOGIC;
p_27_in163_in : in STD_LOGIC;
p_33_in182_in : in STD_LOGIC;
p_39_in : in STD_LOGIC;
p_45_in : in STD_LOGIC;
p_57_in : in STD_LOGIC;
p_63_in : in STD_LOGIC;
p_75_in309_in : in STD_LOGIC;
p_74_in307_in : in STD_LOGIC;
p_87_in351_in : in STD_LOGIC;
p_86_in349_in : in STD_LOGIC;
p_93_in : in STD_LOGIC;
p_92_in368_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_tdpram : entity is "xpm_memory_tdpram";
end system_axi_ethernetlite_0_0_xpm_memory_tdpram;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_tdpram is
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_2_n_0\ : STD_LOGIC;
signal \^douta\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 30 downto 0 );
signal xpm_memory_base_inst_n_38 : STD_LOGIC;
signal xpm_memory_base_inst_n_39 : STD_LOGIC;
signal xpm_memory_base_inst_n_4 : STD_LOGIC;
signal xpm_memory_base_inst_n_5 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_1\ : label is "soft_lutpair98";
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of xpm_memory_base_inst : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of xpm_memory_base_inst : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of xpm_memory_base_inst : label is 3;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of xpm_memory_base_inst : label is 4095;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of xpm_memory_base_inst : label is 4;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of xpm_memory_base_inst : label is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of xpm_memory_base_inst : label is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of xpm_memory_base_inst : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of xpm_memory_base_inst : label is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of xpm_memory_base_inst : label is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of xpm_memory_base_inst : label is 1;
attribute VERSION : integer;
attribute VERSION of xpm_memory_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
begin
douta(3 downto 0) <= \^douta\(3 downto 0);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \reg_data_out_reg[0]\,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(0),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_2_n_0\,
O => D(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AACCFFF0AACC00"
)
port map (
I0 => p_1_out(0),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(0),
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(0),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_2\(0),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_63_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(8),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_2_n_0\,
O => D(8)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(10),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(8),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(8),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(8),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_75_in309_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_74_in307_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_2_n_0\,
O => D(9)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(12),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(9),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(9),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(9),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_87_in351_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_86_in349_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_2_n_0\,
O => D(10)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AACCFFF0AACC00"
)
port map (
I0 => p_1_out(14),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(10),
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(10),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_2\(10),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_93_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_92_in368_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_2_n_0\,
O => D(11)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(15),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(11),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(11),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(11),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_2_n_0\,
O => D(12)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(16),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(12),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(12),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(12),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_2_n_0\,
O => D(13)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(17),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(13),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(13),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(13),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_2_n_0\,
O => D(14)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(18),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(14),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(14),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(14),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_2_n_0\,
O => D(15)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(19),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(15),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(15),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(15),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \reg_data_out_reg[1]\,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(1),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_2_n_0\,
O => D(1)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(1),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(1),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(1),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(1),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_2_n_0\,
O => D(16)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(20),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(16),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(16),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(16),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_2_n_0\,
O => D(17)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(21),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(17),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(17),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(17),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_2_n_0\,
O => D(18)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(22),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(18),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(18),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(18),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_2_n_0\,
O => D(19)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(23),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(19),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(19),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(19),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_2_n_0\,
O => D(20)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(24),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(20),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(20),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(20),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_2_n_0\,
O => D(21)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(25),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(21),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(21),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(21),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_2_n_0\,
O => D(22)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(26),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(22),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(22),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(22),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_2_n_0\,
O => D(23)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(27),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(23),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(23),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(23),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_2_n_0\,
O => D(24)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(28),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(24),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(24),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(24),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_2_n_0\,
O => D(25)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(29),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(25),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(25),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(25),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_2_n_0\,
O => D(26)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(30),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(26),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(26),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(26),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_21_in144_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(2),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_2_n_0\,
O => D(2)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(3),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(2),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(2),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(2),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_27_in163_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(3),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_2_n_0\,
O => D(3)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AACCFFF0AACC00"
)
port map (
I0 => p_1_out(4),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(3),
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(3),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_2\(3),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_33_in182_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(4),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_2_n_0\,
O => D(4)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(5),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(4),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(4),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(4),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_39_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(5),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_2_n_0\,
O => D(5)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(6),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(5),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(5),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(5),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_45_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(6),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_2_n_0\,
O => D(6)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(7),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(6),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(6),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(6),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_57_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(7),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_2_n_0\,
O => D(7)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AACCFFF0AACC00"
)
port map (
I0 => p_1_out(9),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(7),
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(7),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_2\(7),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_2_n_0\
);
ram16x1_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0B08"
)
port map (
I0 => \^douta\(0),
I1 => tx_pong_ping_l,
I2 => tx_idle,
I3 => \gen_wr_b.gen_word_wide.mem_reg\(0),
O => \rdDestAddrNib_D_t_q_reg[1]\(0)
);
ram16x1_2_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0B08"
)
port map (
I0 => \^douta\(2),
I1 => tx_pong_ping_l,
I2 => tx_idle,
I3 => \gen_wr_b.gen_word_wide.mem_reg\(1),
O => \rdDestAddrNib_D_t_q_reg[1]\(1)
);
ram16x1_3_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0B08"
)
port map (
I0 => \^douta\(3),
I1 => tx_pong_ping_l,
I2 => tx_idle,
I3 => \gen_wr_b.gen_word_wide.mem_reg\(2),
O => \rdDestAddrNib_D_t_q_reg[1]\(2)
);
xpm_memory_base_inst: entity work.\system_axi_ethernetlite_0_0_xpm_memory_base__6\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(8 downto 0),
clka => s_axi_aclk,
clkb => s_axi_aclk,
dbiterra => xpm_memory_base_inst_n_5,
dbiterrb => xpm_memory_base_inst_n_39,
dina(3 downto 0) => B"0000",
dinb(31 downto 0) => s_axi_wdata(31 downto 0),
douta(3 downto 0) => \^douta\(3 downto 0),
doutb(31) => doutb(4),
doutb(30 downto 14) => p_1_out(30 downto 14),
doutb(13) => doutb(3),
doutb(12) => p_1_out(12),
doutb(11) => doutb(2),
doutb(10 downto 9) => p_1_out(10 downto 9),
doutb(8) => doutb(1),
doutb(7 downto 3) => p_1_out(7 downto 3),
doutb(2) => doutb(0),
doutb(1 downto 0) => p_1_out(1 downto 0),
ena => \TX_PONG_GEN.tx_pong_ping_l_reg\,
enb => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '1',
regceb => '1',
rsta => '0',
rstb => '0',
sbiterra => xpm_memory_base_inst_n_4,
sbiterrb => xpm_memory_base_inst_n_38,
sleep => '0',
wea(0) => '0',
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_tdpram_4 is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\TX_PONG_GEN.tx_pong_ping_l_reg\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
tx_idle : in STD_LOGIC;
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_tdpram_4 : entity is "xpm_memory_tdpram";
end system_axi_ethernetlite_0_0_xpm_memory_tdpram_4;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_tdpram_4 is
signal \^douta\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xpm_memory_base_inst_n_38 : STD_LOGIC;
signal xpm_memory_base_inst_n_39 : STD_LOGIC;
signal xpm_memory_base_inst_n_4 : STD_LOGIC;
signal xpm_memory_base_inst_n_5 : STD_LOGIC;
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of xpm_memory_base_inst : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of xpm_memory_base_inst : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of xpm_memory_base_inst : label is 3;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of xpm_memory_base_inst : label is 4095;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of xpm_memory_base_inst : label is 4;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of xpm_memory_base_inst : label is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of xpm_memory_base_inst : label is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of xpm_memory_base_inst : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of xpm_memory_base_inst : label is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of xpm_memory_base_inst : label is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of xpm_memory_base_inst : label is 1;
attribute VERSION : integer;
attribute VERSION of xpm_memory_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
begin
douta(3 downto 0) <= \^douta\(3 downto 0);
ram16x1_1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"3202"
)
port map (
I0 => \^douta\(1),
I1 => tx_idle,
I2 => tx_pong_ping_l,
I3 => \gen_wr_b.gen_word_wide.mem_reg\(0),
O => \rdDestAddrNib_D_t_q_reg[1]\(0)
);
xpm_memory_base_inst: entity work.\system_axi_ethernetlite_0_0_xpm_memory_base__4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0),
clka => s_axi_aclk,
clkb => s_axi_aclk,
dbiterra => xpm_memory_base_inst_n_5,
dbiterrb => xpm_memory_base_inst_n_39,
dina(3 downto 0) => B"0000",
dinb(31 downto 0) => s_axi_wdata(31 downto 0),
douta(3 downto 0) => \^douta\(3 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => \TX_PONG_GEN.tx_pong_ping_l_reg\,
enb => enb,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '1',
regceb => '1',
rsta => '0',
rstb => '0',
sbiterra => xpm_memory_base_inst_n_4,
sbiterrb => xpm_memory_base_inst_n_38,
sleep => '0',
wea(0) => '0',
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_tdpram_5 is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
state0a : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\rxbuffer_addr_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_tdpram_5 : entity is "xpm_memory_tdpram";
end system_axi_ethernetlite_0_0_xpm_memory_tdpram_5;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_tdpram_5 is
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xpm_memory_base_inst_n_38 : STD_LOGIC;
signal xpm_memory_base_inst_n_39 : STD_LOGIC;
signal xpm_memory_base_inst_n_4 : STD_LOGIC;
signal xpm_memory_base_inst_n_5 : STD_LOGIC;
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of xpm_memory_base_inst : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of xpm_memory_base_inst : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of xpm_memory_base_inst : label is 3;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of xpm_memory_base_inst : label is 4095;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of xpm_memory_base_inst : label is 4;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of xpm_memory_base_inst : label is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of xpm_memory_base_inst : label is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of xpm_memory_base_inst : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of xpm_memory_base_inst : label is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of xpm_memory_base_inst : label is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of xpm_memory_base_inst : label is 1;
attribute VERSION : integer;
attribute VERSION of xpm_memory_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
begin
xpm_memory_base_inst: entity work.system_axi_ethernetlite_0_0_xpm_memory_base
port map (
addra(11 downto 0) => \rxbuffer_addr_reg[0]\(11 downto 0),
addrb(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0),
clka => s_axi_aclk,
clkb => s_axi_aclk,
dbiterra => xpm_memory_base_inst_n_5,
dbiterrb => xpm_memory_base_inst_n_39,
dina(3 downto 0) => Q(3 downto 0),
dinb(31 downto 0) => s_axi_wdata(31 downto 0),
douta(3 downto 0) => p_5_out(3 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => state0a,
enb => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '1',
regceb => '1',
rsta => '0',
rstb => '0',
sbiterra => xpm_memory_base_inst_n_4,
sbiterrb => xpm_memory_base_inst_n_38,
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_tdpram_6 is
port (
doutb : out STD_LOGIC_VECTOR ( 26 downto 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\rxbuffer_addr_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\reg_data_out_reg[2]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg_access_reg : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_51_in : in STD_LOGIC;
p_69_in : in STD_LOGIC;
p_68_in288_in : in STD_LOGIC;
p_81_in330_in : in STD_LOGIC;
p_80_in328_in : in STD_LOGIC;
\reg_data_out_reg[31]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_tdpram_6 : entity is "xpm_memory_tdpram";
end system_axi_ethernetlite_0_0_xpm_memory_tdpram_6;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_tdpram_6 is
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_3_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_2_n_0\ : STD_LOGIC;
signal rx_ping_data_out : STD_LOGIC_VECTOR ( 31 downto 2 );
signal rx_ping_rd_data : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xpm_memory_base_inst_n_38 : STD_LOGIC;
signal xpm_memory_base_inst_n_39 : STD_LOGIC;
signal xpm_memory_base_inst_n_4 : STD_LOGIC;
signal xpm_memory_base_inst_n_5 : STD_LOGIC;
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of xpm_memory_base_inst : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of xpm_memory_base_inst : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of xpm_memory_base_inst : label is 3;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of xpm_memory_base_inst : label is 4095;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of xpm_memory_base_inst : label is 4;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of xpm_memory_base_inst : label is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of xpm_memory_base_inst : label is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of xpm_memory_base_inst : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of xpm_memory_base_inst : label is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of xpm_memory_base_inst : label is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of xpm_memory_base_inst : label is 1;
attribute VERSION : integer;
attribute VERSION of xpm_memory_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
begin
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_69_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_68_in288_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_2_n_0\,
O => D(2)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(11),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(2),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(2),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(2),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_81_in330_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_80_in328_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_2_n_0\,
O => D(3)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(13),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(3),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(3),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(3),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \reg_data_out_reg[2]\,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => \MDIO_GEN.mdio_data_out_reg[8]\(0),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_2_n_0\,
O => D(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(2),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(0),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(0),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(0),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F80"
)
port map (
I0 => \reg_data_out_reg[31]\,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => reg_access_reg,
I3 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_3_n_0\,
O => D(4)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(31),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(4),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(4),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(4),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_3_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_51_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => \MDIO_GEN.mdio_data_out_reg[8]\(1),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_2_n_0\,
O => D(1)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(8),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(1),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(1),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(1),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_2_n_0\
);
xpm_memory_base_inst: entity work.\system_axi_ethernetlite_0_0_xpm_memory_base__5\
port map (
addra(11 downto 0) => \rxbuffer_addr_reg[0]\(11 downto 0),
addrb(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(8 downto 0),
clka => s_axi_aclk,
clkb => s_axi_aclk,
dbiterra => xpm_memory_base_inst_n_5,
dbiterrb => xpm_memory_base_inst_n_39,
dina(3 downto 0) => Q(3 downto 0),
dinb(31 downto 0) => s_axi_wdata(31 downto 0),
douta(3 downto 0) => rx_ping_rd_data(3 downto 0),
doutb(31) => rx_ping_data_out(31),
doutb(30 downto 14) => doutb(26 downto 10),
doutb(13) => rx_ping_data_out(13),
doutb(12) => doutb(9),
doutb(11) => rx_ping_data_out(11),
doutb(10 downto 9) => doutb(8 downto 7),
doutb(8) => rx_ping_data_out(8),
doutb(7 downto 3) => doutb(6 downto 2),
doutb(2) => rx_ping_data_out(2),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '1',
regceb => '1',
rsta => '0',
rstb => '0',
sbiterra => xpm_memory_base_inst_n_4,
sbiterrb => xpm_memory_base_inst_n_38,
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\ : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
fifo_tx_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_clk_x_pntrs : entity is "clk_x_pntrs";
end system_axi_ethernetlite_0_0_clk_x_pntrs;
architecture STRUCTURE of system_axi_ethernetlite_0_0_clk_x_pntrs is
signal \_inferred__0/i__n_0\ : STD_LOGIC;
signal \_inferred__2/i__n_0\ : STD_LOGIC;
signal \_inferred__3/i__n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_4__0_n_0\ : STD_LOGIC;
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_inferred__2/i_\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \_inferred__3/i_\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair58";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(3 downto 0) <= \^ram_full_fb_i_reg_0\(3 downto 0);
\_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \_inferred__0/i__n_0\
);
\_inferred__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(1),
I1 => p_6_out(0),
I2 => p_6_out(3),
I3 => p_6_out(2),
O => \_inferred__2/i__n_0\
);
\_inferred__3/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(1),
I2 => p_6_out(3),
O => \_inferred__3/i__n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
phy_tx_clk => phy_tx_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\
port map (
D(0) => \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
phy_tx_clk => phy_tx_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
\out\(3 downto 0) => p_6_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \_inferred__2/i__n_0\,
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \_inferred__3/i__n_0\,
Q => \^ram_full_fb_i_reg_0\(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => \^ram_full_fb_i_reg_0\(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => p_6_out(3),
Q => \^ram_full_fb_i_reg_0\(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(3),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \_inferred__0/i__n_0\,
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\,
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF41000041"
)
port map (
I0 => \ram_empty_i_i_2__0_n_0\,
I1 => p_22_out(2),
I2 => \gc0.count_d1_reg[3]\(2),
I3 => p_22_out(3),
I4 => \gc0.count_d1_reg[3]\(3),
I5 => \ram_empty_i_i_3__0_n_0\,
O => ram_empty_fb_i_reg
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(1),
I1 => \gc0.count_d1_reg[3]\(1),
I2 => p_22_out(0),
I3 => \gc0.count_d1_reg[3]\(0),
O => \ram_empty_i_i_2__0_n_0\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4100004100000000"
)
port map (
I0 => \ram_empty_i_i_4__0_n_0\,
I1 => p_22_out(2),
I2 => \gc0.count_reg[3]\(2),
I3 => p_22_out(3),
I4 => \gc0.count_reg[3]\(3),
I5 => fifo_tx_en_reg(0),
O => \ram_empty_i_i_3__0_n_0\
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(1),
I1 => \gc0.count_reg[3]\(1),
I2 => p_22_out(0),
I3 => \gc0.count_reg[3]\(0),
O => \ram_empty_i_i_4__0_n_0\
);
ram_full_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00F8"
)
port map (
I0 => E(0),
I1 => ram_full_i_i_2_n_0,
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]_0\,
I3 => \grstd1.grst_full.grst_f.rst_d3_reg\,
O => ram_full_fb_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => Q(2),
I1 => \^ram_full_fb_i_reg_0\(2),
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(3),
I4 => ram_full_i_i_4_n_0,
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^ram_full_fb_i_reg_0\(1),
I1 => Q(1),
I2 => \^ram_full_fb_i_reg_0\(0),
I3 => Q(0),
O => ram_full_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_clk_x_pntrs_18 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_i_reg : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_clk_x_pntrs_18 : entity is "clk_x_pntrs";
end system_axi_ethernetlite_0_0_clk_x_pntrs_18;
architecture STRUCTURE of system_axi_ethernetlite_0_0_clk_x_pntrs_18 is
signal \_inferred__2/i__n_0\ : STD_LOGIC;
signal \_inferred__3/i__n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_inferred__2/i_\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \_inferred__3/i_\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair23";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\_inferred__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(1),
I1 => p_6_out(0),
I2 => p_6_out(3),
I3 => p_6_out(2),
O => \_inferred__2/i__n_0\
);
\_inferred__3/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(1),
I2 => p_6_out(3),
O => \_inferred__3/i__n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\
port map (
AR(0) => AR(0),
CLK => CLK,
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0)
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\
port map (
D(0) => gray2bin(2),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\
port map (
AR(0) => AR(0),
CLK => CLK,
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
\out\(3 downto 0) => p_6_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \_inferred__2/i__n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \_inferred__3/i__n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => p_6_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BAABAAAAAAAABAAB"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => ram_empty_i_i_3_n_0,
I2 => p_22_out(2),
I3 => Q(2),
I4 => p_22_out(1),
I5 => Q(1),
O => ram_empty_fb_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"2002000000002002"
)
port map (
I0 => E(0),
I1 => ram_empty_i_i_4_n_0,
I2 => p_22_out(1),
I3 => \gc0.count_reg[3]\(1),
I4 => p_22_out(0),
I5 => \gc0.count_reg[3]\(0),
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
I2 => p_22_out(0),
I3 => Q(0),
O => ram_empty_i_i_3_n_0
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(2),
I1 => \gc0.count_reg[3]\(2),
I2 => p_22_out(3),
I3 => \gc0.count_reg[3]\(3),
O => ram_empty_i_i_4_n_0
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__0_n_0\,
I1 => ram_full_i_reg,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__0_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__0_n_0\
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_memory is
port (
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_phy_tx_en_i_p : in STD_LOGIC;
fifo_tx_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_memory : entity is "memory";
end system_axi_ethernetlite_0_0_memory;
architecture STRUCTURE of system_axi_ethernetlite_0_0_memory is
begin
\gdm.dm_gen.dm\: entity work.system_axi_ethernetlite_0_0_dmem
port map (
AR(0) => AR(0),
D(3 downto 0) => D(3 downto 0),
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en_reg(0) => fifo_tx_en_reg(0),
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_memory_21 is
port (
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
CLK : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
startReadDestAdrNib : in STD_LOGIC;
\gv.ram_valid_d1_reg\ : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\out\ : in STD_LOGIC;
state0a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_memory_21 : entity is "memory";
end system_axi_ethernetlite_0_0_memory_21;
architecture STRUCTURE of system_axi_ethernetlite_0_0_memory_21 is
begin
\gdm.dm_gen.dm\: entity work.system_axi_ethernetlite_0_0_dmem_27
port map (
AR(0) => AR(0),
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gv.ram_valid_d1_reg\ => \gv.ram_valid_d1_reg\,
\out\ => \out\,
preamble => preamble,
ram_empty_fb_i_reg(0) => ram_empty_fb_i_reg(0),
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_logic is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
fifo_tx_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_logic : entity is "rd_logic";
end system_axi_ethernetlite_0_0_rd_logic;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gras.rsts\: entity work.system_axi_ethernetlite_0_0_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
fifo_tx_en => fifo_tx_en,
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk
);
rpntr: entity work.system_axi_ethernetlite_0_0_rd_bin_cntr
port map (
AR(0) => AR(0),
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3 downto 0) => Q(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
phy_tx_clk => phy_tx_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_logic_19 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
state0a : out STD_LOGIC;
\gc0.count_d1_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
rxCrcRst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_logic_19 : entity is "rd_logic";
end system_axi_ethernetlite_0_0_rd_logic_19;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_logic_19 is
signal \^out\ : STD_LOGIC;
signal \^state1a\ : STD_LOGIC;
begin
\out\ <= \^out\;
state1a <= \^state1a\;
\gras.rsts\: entity work.system_axi_ethernetlite_0_0_rd_status_flags_as_30
port map (
AR(0) => AR(0),
Q(0) => Q(1),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\gv.ram_valid_d1_reg\ => \^state1a\,
\out\ => \^out\,
ping_rx_status_reg => ping_rx_status_reg,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
rxCrcRst => rxCrcRst,
s_axi_aclk => s_axi_aclk,
state0a => state0a_0,
state1a => state1a_0
);
\grhf.rhf\: entity work.system_axi_ethernetlite_0_0_rd_handshaking_flags
port map (
AR(0) => AR(0),
Q(0) => Q(0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\out\ => \^out\,
ping_rx_status_reg => ping_rx_status_reg,
ram_valid_i => ram_valid_i,
s_axi_aclk => s_axi_aclk,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state1a => \^state1a\
);
rpntr: entity work.system_axi_ethernetlite_0_0_rd_bin_cntr_31
port map (
AR(0) => AR(0),
E(0) => E(0),
Q(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end system_axi_ethernetlite_0_0_reset_blk_ramfifo;
architecture STRUCTURE of system_axi_ethernetlite_0_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
phy_tx_clk => phy_tx_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_8
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_9
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
phy_tx_clk => phy_tx_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_10
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => '0',
PRE => Rst0,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => rst_rd_reg1,
PRE => Rst0,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => Rst0,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => Rst0,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_reset_blk_ramfifo_22 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
scndry_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_reset_blk_ramfifo_22 : entity is "reset_blk_ramfifo";
end system_axi_ethernetlite_0_0_reset_blk_ramfifo_22;
architecture STRUCTURE of system_axi_ethernetlite_0_0_reset_blk_ramfifo_22 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_23
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_24
port map (
CLK => CLK,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_25
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_26
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
CLK => CLK,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => scndry_out,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => scndry_out,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => scndry_out,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => rst_wr_reg1,
PRE => scndry_out,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_logic is
port (
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
D18_out : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_logic : entity is "wr_logic";
end system_axi_ethernetlite_0_0_wr_logic;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_logic is
begin
\gwas.wsts\: entity work.system_axi_ethernetlite_0_0_wr_status_flags_as
port map (
D18_out => D18_out,
STATE14A => STATE14A,
STATE16A => STATE16A,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \out\,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
wpntr: entity work.system_axi_ethernetlite_0_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_logic_20 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
CLK : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_logic_20 : entity is "wr_logic";
end system_axi_ethernetlite_0_0_wr_logic_20;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_logic_20 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_axi_ethernetlite_0_0_wr_status_flags_as_28
port map (
CLK => CLK,
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.system_axi_ethernetlite_0_0_wr_bin_cntr_29
port map (
AR(0) => AR(0),
CLK => CLK,
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_emac_dpram is
port (
doutb : out STD_LOGIC_VECTOR ( 26 downto 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\rxbuffer_addr_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\reg_data_out_reg[2]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg_access_reg : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_51_in : in STD_LOGIC;
p_69_in : in STD_LOGIC;
p_68_in288_in : in STD_LOGIC;
p_81_in330_in : in STD_LOGIC;
p_80_in328_in : in STD_LOGIC;
\reg_data_out_reg[31]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_emac_dpram : entity is "emac_dpram";
end system_axi_ethernetlite_0_0_emac_dpram;
architecture STRUCTURE of system_axi_ethernetlite_0_0_emac_dpram is
begin
\xpm_mem_gen.xpm_memory_inst\: entity work.system_axi_ethernetlite_0_0_xpm_memory_tdpram_6
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
D(4 downto 0) => D(4 downto 0),
\MDIO_GEN.mdio_data_out_reg[8]\(1 downto 0) => \MDIO_GEN.mdio_data_out_reg[8]\(1 downto 0),
Q(3 downto 0) => Q(3 downto 0),
doutb(26 downto 0) => doutb(26 downto 0),
ena => ena,
\gen_wr_b.gen_word_wide.mem_reg\(4 downto 0) => \gen_wr_b.gen_word_wide.mem_reg\(4 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_0\(4 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_0\(4 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_1\(4 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_1\(4 downto 0),
p_51_in => p_51_in,
p_68_in288_in => p_68_in288_in,
p_69_in => p_69_in,
p_80_in328_in => p_80_in328_in,
p_81_in330_in => p_81_in330_in,
reg_access_reg => reg_access_reg,
\reg_data_out_reg[2]\ => \reg_data_out_reg[2]\,
\reg_data_out_reg[31]\ => \reg_data_out_reg[31]\,
\rxbuffer_addr_reg[0]\(11 downto 0) => \rxbuffer_addr_reg[0]\(11 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_emac_dpram_1 is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
state0a : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\rxbuffer_addr_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_emac_dpram_1 : entity is "emac_dpram";
end system_axi_ethernetlite_0_0_emac_dpram_1;
architecture STRUCTURE of system_axi_ethernetlite_0_0_emac_dpram_1 is
begin
\xpm_mem_gen.xpm_memory_inst\: entity work.system_axi_ethernetlite_0_0_xpm_memory_tdpram_5
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
Q(3 downto 0) => Q(3 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
\rxbuffer_addr_reg[0]\(11 downto 0) => \rxbuffer_addr_reg[0]\(11 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
state0a => state0a,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_emac_dpram_2 is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\TX_PONG_GEN.tx_pong_ping_l_reg\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
tx_idle : in STD_LOGIC;
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_emac_dpram_2 : entity is "emac_dpram";
end system_axi_ethernetlite_0_0_emac_dpram_2;
architecture STRUCTURE of system_axi_ethernetlite_0_0_emac_dpram_2 is
begin
\xpm_mem_gen.xpm_memory_inst\: entity work.system_axi_ethernetlite_0_0_xpm_memory_tdpram_4
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0),
\TX_PONG_GEN.tx_pong_ping_l_reg\ => \TX_PONG_GEN.tx_pong_ping_l_reg\,
addra(11 downto 0) => addra(11 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
enb => enb,
\gen_wr_b.gen_word_wide.mem_reg\(0) => \gen_wr_b.gen_word_wide.mem_reg\(0),
\rdDestAddrNib_D_t_q_reg[1]\(0) => \rdDestAddrNib_D_t_q_reg[1]\(0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
tx_idle => tx_idle,
tx_pong_ping_l => tx_pong_ping_l,
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_emac_dpram_3 is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 4 downto 0 );
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 26 downto 0 );
s_axi_aclk : in STD_LOGIC;
\TX_PONG_GEN.tx_pong_ping_l_reg\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
tx_idle : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\reg_data_out_reg[0]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
reg_access_reg : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_2\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\reg_data_out_reg[1]\ : in STD_LOGIC;
p_21_in144_in : in STD_LOGIC;
p_27_in163_in : in STD_LOGIC;
p_33_in182_in : in STD_LOGIC;
p_39_in : in STD_LOGIC;
p_45_in : in STD_LOGIC;
p_57_in : in STD_LOGIC;
p_63_in : in STD_LOGIC;
p_75_in309_in : in STD_LOGIC;
p_74_in307_in : in STD_LOGIC;
p_87_in351_in : in STD_LOGIC;
p_86_in349_in : in STD_LOGIC;
p_93_in : in STD_LOGIC;
p_92_in368_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_emac_dpram_3 : entity is "emac_dpram";
end system_axi_ethernetlite_0_0_emac_dpram_3;
architecture STRUCTURE of system_axi_ethernetlite_0_0_emac_dpram_3 is
begin
\xpm_mem_gen.xpm_memory_inst\: entity work.system_axi_ethernetlite_0_0_xpm_memory_tdpram
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
D(26 downto 0) => D(26 downto 0),
Q(8 downto 0) => Q(8 downto 0),
\TX_PONG_GEN.tx_pong_ping_l_reg\ => \TX_PONG_GEN.tx_pong_ping_l_reg\,
addra(11 downto 0) => addra(11 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(4 downto 0) => doutb(4 downto 0),
\gen_wr_b.gen_word_wide.mem_reg\(2 downto 0) => \gen_wr_b.gen_word_wide.mem_reg\(2 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_0\(26 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_0\(26 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_1\(26 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_1\(26 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_2\(26 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_2\(26 downto 0),
p_21_in144_in => p_21_in144_in,
p_27_in163_in => p_27_in163_in,
p_33_in182_in => p_33_in182_in,
p_39_in => p_39_in,
p_45_in => p_45_in,
p_57_in => p_57_in,
p_63_in => p_63_in,
p_74_in307_in => p_74_in307_in,
p_75_in309_in => p_75_in309_in,
p_86_in349_in => p_86_in349_in,
p_87_in351_in => p_87_in351_in,
p_92_in368_in => p_92_in368_in,
p_93_in => p_93_in,
\rdDestAddrNib_D_t_q_reg[1]\(2 downto 0) => \rdDestAddrNib_D_t_q_reg[1]\(2 downto 0),
reg_access_reg => reg_access_reg,
\reg_data_out_reg[0]\ => \reg_data_out_reg[0]\,
\reg_data_out_reg[1]\ => \reg_data_out_reg[1]\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
tx_idle => tx_idle,
tx_pong_ping_l => tx_pong_ping_l,
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_ramfifo is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end system_axi_ethernetlite_0_0_fifo_generator_ramfifo;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_1\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_8\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_7\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rstblk_n_6 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_axi_ethernetlite_0_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_7\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_8\,
E(0) => E(0),
Q(3 downto 0) => wr_pntr_plus2(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
fifo_tx_en_reg(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gc0.count_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\ => \gntv_or_sync_fifo.gl0.wr_n_7\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => rstblk_n_6,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_5_out(3 downto 0),
phy_tx_clk => phy_tx_clk,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(3 downto 0) => p_23_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_5_out(1),
I1 => p_5_out(0),
I2 => p_5_out(3),
I3 => p_5_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_axi_ethernetlite_0_0_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_7\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_8\,
E(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
Q(3 downto 0) => rd_pntr_plus1(3 downto 0),
fifo_tx_en => fifo_tx_en,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_axi_ethernetlite_0_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
D18_out => D18_out,
E(0) => E(0),
Q(3 downto 0) => wr_pntr_plus2(3 downto 0),
STATE14A => STATE14A,
STATE16A => STATE16A,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => p_23_out(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
\gntv_or_sync_fifo.mem\: entity work.system_axi_ethernetlite_0_0_memory
port map (
AR(0) => rd_rst_i(0),
D(3 downto 0) => D(3 downto 0),
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en_reg(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk
);
rstblk: entity work.system_axi_ethernetlite_0_0_reset_blk_ramfifo
port map (
Rst0 => Rst0,
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
phy_tx_clk => phy_tx_clk,
ram_full_fb_i_reg => rstblk_n_6,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17 : entity is "fifo_generator_ramfifo";
end system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17 is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_10\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_11\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^out\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rstblk_n_6 : STD_LOGIC;
signal \^state1a\ : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\out\ <= \^out\;
state1a <= \^state1a\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_axi_ethernetlite_0_0_clk_x_pntrs_18
port map (
AR(0) => wr_rst_i(0),
CLK => CLK,
D(0) => gray2bin(0),
E(0) => E(0),
Q(3 downto 0) => p_0_out(3 downto 0),
\gc0.count_d1_reg[3]\(2) => \gntv_or_sync_fifo.gl0.rd_n_10\,
\gc0.count_d1_reg[3]\(1) => \gntv_or_sync_fifo.gl0.rd_n_11\,
\gc0.count_d1_reg[3]\(0) => \gntv_or_sync_fifo.gl0.rd_n_12\,
\gc0.count_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => rstblk_n_6,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_5_out(3 downto 0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_5\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_5_out(1),
I1 => p_5_out(0),
I2 => p_5_out(3),
I3 => p_5_out(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_axi_ethernetlite_0_0_rd_logic_19
port map (
AR(0) => rd_rst_i(2),
E(0) => E(0),
Q(1 downto 0) => \^q\(1 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
\gc0.count_d1_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_10\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_11\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_12\,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \^out\,
ping_rx_status_reg => ping_rx_status_reg,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
rxCrcRst => rxCrcRst,
s_axi_aclk => s_axi_aclk,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => \^state1a\,
state1a_0 => state1a_0
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_axi_ethernetlite_0_0_wr_logic_20
port map (
AR(0) => wr_rst_i(1),
CLK => CLK,
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_5\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.system_axi_ethernetlite_0_0_memory_21
port map (
AR(0) => rd_rst_i(0),
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => p_18_out,
Q(5 downto 0) => \^q\(5 downto 0),
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gv.ram_valid_d1_reg\ => \^state1a\,
\out\ => \^out\,
preamble => preamble,
ram_empty_fb_i_reg(0) => E(0),
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a_0,
state2a => state2a,
state3a => state3a
);
rstblk: entity work.system_axi_ethernetlite_0_0_reset_blk_ramfifo_22
port map (
CLK => CLK,
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => rstblk_n_6,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_top is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_top : entity is "fifo_generator_top";
end system_axi_ethernetlite_0_0_fifo_generator_top;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_top is
begin
\grf.rf\: entity work.system_axi_ethernetlite_0_0_fifo_generator_ramfifo
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => STATE16A,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_top_16 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_top_16 : entity is "fifo_generator_top";
end system_axi_ethernetlite_0_0_fifo_generator_top_16;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_top_16 is
begin
\grf.rf\: entity work.system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => state1a,
state1a_0 => state1a_0,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.system_axi_ethernetlite_0_0_fifo_generator_top
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => STATE16A,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15 : entity is "fifo_generator_v13_1_3_synth";
end system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15 is
begin
\gconvfifo.rf\: entity work.system_axi_ethernetlite_0_0_fifo_generator_top_16
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => state1a,
state1a_0 => state1a_0,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_v13_1_3 is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end system_axi_ethernetlite_0_0_fifo_generator_v13_1_3;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3 is
begin
inst_fifo_gen: entity work.system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => STATE16A,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14 : entity is "fifo_generator_v13_1_3";
end system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14 is
begin
inst_fifo_gen: entity work.system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => state1a,
state1a_0 => state1a_0,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_async_fifo_fg is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_async_fifo_fg : entity is "async_fifo_fg";
end system_axi_ethernetlite_0_0_async_fifo_fg;
architecture STRUCTURE of system_axi_ethernetlite_0_0_async_fifo_fg is
begin
\LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM\: entity work.system_axi_ethernetlite_0_0_fifo_generator_v13_1_3
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => STATE16A,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_async_fifo_fg_13 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_async_fifo_fg_13 : entity is "async_fifo_fg";
end system_axi_ethernetlite_0_0_async_fifo_fg_13;
architecture STRUCTURE of system_axi_ethernetlite_0_0_async_fifo_fg_13 is
begin
\LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM\: entity work.system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => state1a,
state1a_0 => state1a_0,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rx_intrfce is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
rxBusFifoRdAck : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rx_intrfce : entity is "rx_intrfce";
end system_axi_ethernetlite_0_0_rx_intrfce;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rx_intrfce is
signal rst_s : STD_LOGIC;
begin
CDC_FIFO_RST: entity work.system_axi_ethernetlite_0_0_cdc_sync_12
port map (
CLK => CLK,
SS(0) => SS(0),
scndry_out => rst_s
);
I_RX_FIFO: entity work.system_axi_ethernetlite_0_0_async_fifo_fg_13
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => rst_s,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => rxBusFifoRdAck,
state1a_0 => state1a,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_tx_intrfce is
port (
\out\ : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
txfifo_empty : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
Rst0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_tx_intrfce : entity is "tx_intrfce";
end system_axi_ethernetlite_0_0_tx_intrfce;
architecture STRUCTURE of system_axi_ethernetlite_0_0_tx_intrfce is
signal fifo_empty_c : STD_LOGIC;
signal fifo_empty_i : STD_LOGIC;
signal \^txfifo_empty\ : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of pipeIt : label is "FDR";
attribute box_type : string;
attribute box_type of pipeIt : label is "PRIMITIVE";
begin
txfifo_empty <= \^txfifo_empty\;
CDC_FIFO_EMPTY: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized2\
port map (
prmry_in => fifo_empty_i,
s_axi_aclk => s_axi_aclk,
scndry_out => fifo_empty_c
);
I_TX_FIFO: entity work.system_axi_ethernetlite_0_0_async_fifo_fg
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => \out\,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => fifo_empty_i,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => \^txfifo_empty\,
waitFifoEmpty => waitFifoEmpty
);
pipeIt: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_empty_c,
Q => \^txfifo_empty\,
R => Rst0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_receive is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
wea : out STD_LOGIC_VECTOR ( 0 to 0 );
rx_addr_en : out STD_LOGIC;
checkingBroadcastAdr_reg_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\rxbuffer_addr_reg[0]\ : out STD_LOGIC;
D_5 : out STD_LOGIC;
RX_DONE_D1_I : out STD_LOGIC;
ping_rx_status_reg : out STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : out STD_LOGIC;
ena : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[2]_0\ : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[1]_0\ : in STD_LOGIC;
ping_rx_status_reg_0 : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ : in STD_LOGIC;
p_5_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_9_in : in STD_LOGIC_VECTOR ( 0 to 0 );
STATE17A : in STD_LOGIC;
tx_intr_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
rx_intr_en0 : in STD_LOGIC;
rx_pong_ping_l : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_receive : entity is "receive";
end system_axi_ethernetlite_0_0_receive;
architecture STRUCTURE of system_axi_ethernetlite_0_0_receive is
signal D : STD_LOGIC;
signal D11_out : STD_LOGIC;
signal D13_out : STD_LOGIC;
signal D5_out : STD_LOGIC;
signal D6_out : STD_LOGIC;
signal INST_CRCGENRX_n_10 : STD_LOGIC;
signal INST_CRCGENRX_n_9 : STD_LOGIC;
signal INST_RX_INTRFCE_n_10 : STD_LOGIC;
signal INST_RX_INTRFCE_n_11 : STD_LOGIC;
signal INST_RX_INTRFCE_n_15 : STD_LOGIC;
signal INST_RX_INTRFCE_n_16 : STD_LOGIC;
signal INST_RX_INTRFCE_n_18 : STD_LOGIC;
signal INST_RX_INTRFCE_n_26 : STD_LOGIC;
signal INST_RX_INTRFCE_n_27 : STD_LOGIC;
signal INST_RX_INTRFCE_n_28 : STD_LOGIC;
signal INST_RX_STATE_n_11 : STD_LOGIC;
signal INST_RX_STATE_n_14 : STD_LOGIC;
signal INST_RX_STATE_n_23 : STD_LOGIC;
signal INST_RX_STATE_n_8 : STD_LOGIC;
signal \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_i\ : STD_LOGIC;
signal \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i\ : STD_LOGIC;
signal \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal busFifoData_is_5_d1 : STD_LOGIC;
signal \^checkingbroadcastadr_reg_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal crcokr1 : STD_LOGIC;
signal emac_rx_rd_data_i : STD_LOGIC_VECTOR ( 4 to 5 );
signal fifo_empty_i : STD_LOGIC;
signal goto_readDestAdrNib1 : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_1_in1_in : STD_LOGIC;
signal p_1_in4_in : STD_LOGIC;
signal p_1_in7_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_9_in_0 : STD_LOGIC;
signal parallel_crc : STD_LOGIC_VECTOR ( 11 downto 4 );
signal parallel_crc1 : STD_LOGIC;
signal rxBusFifoRdAck : STD_LOGIC;
signal rxComboCrcRst : STD_LOGIC;
signal rxCrcEn : STD_LOGIC;
signal rxCrcEn_d1 : STD_LOGIC;
signal rxCrcRst : STD_LOGIC;
signal rx_start : STD_LOGIC;
signal sfd1CheckBusFifoEmpty : STD_LOGIC;
signal startReadDataNib : STD_LOGIC;
signal startReadDestAdrNib : STD_LOGIC;
begin
Q(3 downto 0) <= \^q\(3 downto 0);
checkingBroadcastAdr_reg_reg(3 downto 0) <= \^checkingbroadcastadr_reg_reg\(3 downto 0);
INST_CRCGENRX: entity work.system_axi_ethernetlite_0_0_crcgenrx
port map (
D(6 downto 5) => parallel_crc(11 downto 10),
D(4 downto 3) => parallel_crc(8 downto 7),
D(2 downto 1) => parallel_crc(5 downto 4),
D(0) => parallel_crc1,
D_0 => D,
E(0) => rxCrcEn_d1,
Q(9) => p_1_in7_in,
Q(8) => p_1_in4_in,
Q(7) => p_1_in1_in,
Q(6) => p_1_in,
Q(5) => p_10_in,
Q(4) => p_9_in_0,
Q(3) => p_7_in,
Q(2) => p_6_in,
Q(1) => p_4_in,
Q(0) => INST_CRCGENRX_n_9,
SS(0) => rxComboCrcRst,
crcokdelay => INST_CRCGENRX_n_10,
crcokr1 => crcokr1,
\gpr1.dout_i_reg[2]\ => INST_RX_INTRFCE_n_26,
\gpr1.dout_i_reg[5]\(3 downto 0) => \^q\(3 downto 0),
rxCrcEn => rxCrcEn,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn
);
INST_RX_INTRFCE: entity work.system_axi_ethernetlite_0_0_rx_intrfce
port map (
CLK => CLK,
D(6 downto 5) => parallel_crc(11 downto 10),
D(4 downto 3) => parallel_crc(8 downto 7),
D(2 downto 1) => parallel_crc(5 downto 4),
D(0) => parallel_crc1,
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i\,
Q(5 downto 2) => \^q\(3 downto 0),
Q(1) => emac_rx_rd_data_i(4),
Q(0) => emac_rx_rd_data_i(5),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg_0\,
SS(0) => SS(0),
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => INST_RX_INTRFCE_n_27,
\crc_local_reg[13]\ => INST_RX_INTRFCE_n_26,
\crc_local_reg[31]\(9) => p_1_in7_in,
\crc_local_reg[31]\(8) => p_1_in4_in,
\crc_local_reg[31]\(7) => p_1_in1_in,
\crc_local_reg[31]\(6) => p_1_in,
\crc_local_reg[31]\(5) => p_10_in,
\crc_local_reg[31]\(4) => p_9_in_0,
\crc_local_reg[31]\(3) => p_7_in,
\crc_local_reg[31]\(2) => p_6_in,
\crc_local_reg[31]\(1) => p_4_in,
\crc_local_reg[31]\(0) => INST_CRCGENRX_n_9,
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\,
\out\ => fifo_empty_i,
ping_rx_status_reg => ping_rx_status_reg_0,
preamble => INST_RX_INTRFCE_n_11,
ram_valid_i => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_i\,
\rdDestAddrNib_D_t_q_reg[1]\ => INST_RX_INTRFCE_n_16,
\rdDestAddrNib_D_t_q_reg[3]\ => INST_RX_INTRFCE_n_15,
\rdDestAddrNib_D_t_q_reg[3]_0\ => INST_RX_STATE_n_8,
\rdDestAddrNib_D_t_q_reg[3]_1\ => INST_RX_STATE_n_23,
rxBusFifoRdAck => rxBusFifoRdAck,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => INST_RX_INTRFCE_n_18,
state0a_0 => INST_RX_STATE_n_11,
state1a => INST_RX_INTRFCE_n_28,
state2a => INST_RX_INTRFCE_n_10,
state3a => INST_RX_STATE_n_14
);
INST_RX_STATE: entity work.system_axi_ethernetlite_0_0_rx_statemachine
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
\AXI4_LITE_IF_GEN.write_in_prog_reg\ => \AXI4_LITE_IF_GEN.write_in_prog_reg\,
D => D,
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
D_5 => D_5,
E(0) => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i\,
Q(2) => \^q\(3),
Q(1) => emac_rx_rd_data_i(4),
Q(0) => emac_rx_rd_data_i(5),
RX_DONE_D1_I => RX_DONE_D1_I,
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ => INST_RX_INTRFCE_n_28,
\RX_PONG_REG_GEN.pong_rx_status_reg_1\ => \RX_PONG_REG_GEN.pong_rx_status_reg_0\,
SS(0) => SS(0),
STATE17A => STATE17A,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
\crc_local_reg[31]\(0) => rxComboCrcRst,
crcokdelay_0 => INST_CRCGENRX_n_10,
crcokr1 => crcokr1,
\emac_rx_rd_data_d1_reg[0]\(3 downto 0) => \^checkingbroadcastadr_reg_reg\(3 downto 0),
\emac_rx_rd_data_d1_reg[1]\ => \emac_rx_rd_data_d1_reg[1]_0\,
\emac_rx_rd_data_d1_reg[2]\ => \emac_rx_rd_data_d1_reg[2]_0\,
ena => ena,
\gen_wr_b.gen_word_wide.mem_reg\ => \gen_wr_b.gen_word_wide.mem_reg\,
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[1]\ => INST_RX_INTRFCE_n_10,
\gpr1.dout_i_reg[1]_0\ => INST_RX_INTRFCE_n_16,
\gpr1.dout_i_reg[2]\ => INST_RX_INTRFCE_n_11,
\gpr1.dout_i_reg[5]\ => INST_RX_INTRFCE_n_27,
\gv.ram_valid_d1_reg\ => INST_RX_INTRFCE_n_18,
\out\ => fifo_empty_i,
p_5_in(0) => p_5_in(0),
p_9_in(0) => p_9_in(0),
ping_rx_status_reg => ping_rx_status_reg,
ping_rx_status_reg_0 => ping_rx_status_reg_0,
ram_empty_fb_i_reg => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\,
ram_empty_i_reg => INST_RX_INTRFCE_n_15,
ram_valid_i => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_i\,
\rdDestAddrNib_D_t_q_reg[1]_0\ => INST_RX_STATE_n_11,
\rdDestAddrNib_D_t_q_reg[1]_1\(3 downto 0) => \rdDestAddrNib_D_t_q_reg[1]\(3 downto 0),
rxBusFifoRdAck => rxBusFifoRdAck,
rxCrcEn => rxCrcEn,
rxCrcEn_d1_reg => INST_RX_STATE_n_8,
rxCrcRst => rxCrcRst,
rx_addr_en => rx_addr_en,
rx_intr_en0 => rx_intr_en0,
rx_pong_ping_l => rx_pong_ping_l,
rx_start => rx_start,
\rxbuffer_addr_reg[0]\ => \rxbuffer_addr_reg[0]\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(0),
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state17a_0 => INST_RX_STATE_n_23,
state2a_0 => INST_RX_STATE_n_14,
tx_intr_en_reg(0) => tx_intr_en_reg(0),
wea(0) => wea(0)
);
\emac_rx_rd_data_d1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(3),
Q => \^checkingbroadcastadr_reg_reg\(3),
R => SS(0)
);
\emac_rx_rd_data_d1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(2),
Q => \^checkingbroadcastadr_reg_reg\(2),
R => SS(0)
);
\emac_rx_rd_data_d1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(1),
Q => \^checkingbroadcastadr_reg_reg\(1),
R => SS(0)
);
\emac_rx_rd_data_d1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(0),
Q => \^checkingbroadcastadr_reg_reg\(0),
R => SS(0)
);
rxCrcEn_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rxCrcEn,
Q => rxCrcEn_d1,
R => SS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_transmit is
port (
loopback_en_reg : out STD_LOGIC;
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
STATE24A : out STD_LOGIC;
mac_addr_ram_we : out STD_LOGIC;
\txbuffer_addr_reg[0]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
loopback_en_reg_0 : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : out STD_LOGIC;
tx_addr_en : out STD_LOGIC;
mac_addr_ram_addr_wr : out STD_LOGIC_VECTOR ( 0 to 3 );
prmry_vect_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
douta : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\tx_packet_length_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
phy_crs_d2 : in STD_LOGIC;
tx_clk_reg_d3 : in STD_LOGIC;
tx_clk_reg_d2 : in STD_LOGIC;
tx_done_d2 : in STD_LOGIC;
ping_mac_program_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
p_17_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\TX_PONG_REG_GEN.pong_mac_program_reg\ : in STD_LOGIC;
p_15_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rx_pong_ping_l : in STD_LOGIC;
rx_done_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_intr_en0 : in STD_LOGIC;
loopback_en_reg_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_transmit : entity is "transmit";
end system_axi_ethernetlite_0_0_transmit;
architecture STRUCTURE of system_axi_ethernetlite_0_0_transmit is
signal CDC_TX_EN_n_0 : STD_LOGIC;
signal CE : STD_LOGIC;
signal CE_1 : STD_LOGIC;
signal D13_out : STD_LOGIC;
signal D18_out : STD_LOGIC;
signal D21_out : STD_LOGIC;
signal INST_CRCCOUNTER_n_5 : STD_LOGIC;
signal INST_CRCCOUNTER_n_6 : STD_LOGIC;
signal INST_TXBUSFIFOWRITENIBBLECOUNT_n_4 : STD_LOGIC;
signal INST_TXBUSFIFOWRITENIBBLECOUNT_n_5 : STD_LOGIC;
signal INST_TXNIBBLECOUNT_n_1 : STD_LOGIC;
signal INST_TXNIBBLECOUNT_n_3 : STD_LOGIC;
signal INST_TX_INTRFCE_n_1 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_13 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_14 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_15 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_16 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_17 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_18 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_19 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_20 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_35 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_63 : STD_LOGIC;
signal \I_TX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\ : STD_LOGIC;
signal \NSR/nibData\ : STD_LOGIC;
signal ONR_HOT_MUX_n_4 : STD_LOGIC;
signal \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ : STD_LOGIC;
signal Rst0 : STD_LOGIC;
signal S : STD_LOGIC;
signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal S_0 : STD_LOGIC;
signal axi_phy_tx_en_i_p : STD_LOGIC;
signal axi_phy_tx_en_i_p0 : STD_LOGIC;
signal bus_combo : STD_LOGIC_VECTOR ( 5 downto 2 );
signal checkBusFifoFull : STD_LOGIC;
signal checkBusFifoFullCrc : STD_LOGIC;
signal crcCnt : STD_LOGIC_VECTOR ( 0 to 3 );
signal crcComboRst : STD_LOGIC;
signal currentTxBusFifoWrCnt : STD_LOGIC_VECTOR ( 8 to 11 );
signal currentTxNibbleCnt : STD_LOGIC_VECTOR ( 11 to 11 );
signal emac_tx_wr_d1 : STD_LOGIC;
signal emac_tx_wr_data_d1 : STD_LOGIC_VECTOR ( 0 to 3 );
signal emac_tx_wr_data_i : STD_LOGIC_VECTOR ( 0 to 3 );
signal emac_tx_wr_i : STD_LOGIC;
signal enblCRC : STD_LOGIC;
signal enblData : STD_LOGIC;
signal enblPreamble : STD_LOGIC;
signal fifo_tx_en : STD_LOGIC;
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry__1_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal \inst_deferral_state/thisState\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ldLngthCntr : STD_LOGIC;
signal mux_in_data : STD_LOGIC_VECTOR ( 16 to 19 );
signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal txComboBusFifoWrCntRst : STD_LOGIC;
signal txComboNibbleCntRst : STD_LOGIC;
signal txCrcEn : STD_LOGIC;
signal txCrcEn_reg : STD_LOGIC;
signal txNibbleCnt_pad : STD_LOGIC_VECTOR ( 0 to 11 );
signal txNibbleCnt_pad0 : STD_LOGIC_VECTOR ( 11 downto 1 );
signal \txNibbleCnt_pad0_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__1_n_2\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal tx_d_rst : STD_LOGIC;
signal tx_en_i : STD_LOGIC;
signal tx_en_mod : STD_LOGIC;
signal txfifo_empty : STD_LOGIC;
signal txfifo_full : STD_LOGIC;
signal waitFifoEmpty : STD_LOGIC;
signal \NLW_txNibbleCnt_pad0_inferred__0/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_txNibbleCnt_pad0_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair81";
begin
SS(0) <= \^ss\(0);
CDC_PHY_TX_RST: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized4\
port map (
phy_tx_clk => phy_tx_clk,
s_axi_aresetn => \^ss\(0),
scndry_out => tx_d_rst
);
CDC_TX_EN: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized3\
port map (
fifo_tx_en_reg => CDC_TX_EN_n_0,
phy_tx_clk => phy_tx_clk,
scndry_out => tx_d_rst,
tx_en_i => tx_en_i
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(2),
O => prmry_vect_in(0)
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(3),
O => prmry_vect_in(1)
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(4),
O => prmry_vect_in(2)
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(5),
O => prmry_vect_in(3)
);
INST_CRCCOUNTER: entity work.\system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\
port map (
CE => CE,
DIA(0) => tx_en_mod,
\PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\,
S => S,
STATE15A => INST_CRCCOUNTER_n_5,
checkBusFifoFullCrc => checkBusFifoFullCrc,
crcCnt(0 to 3) => crcCnt(0 to 3),
enblCRC => enblCRC,
\gic0.gc0.count_reg[0]\ => INST_CRCCOUNTER_n_6,
\out\ => txfifo_full,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \^ss\(0),
tx_en_i => tx_en_i
);
INST_CRCGENTX: entity work.system_axi_ethernetlite_0_0_crcgentx
port map (
E(0) => \NSR/nibData\,
Q(3) => mux_in_data(16),
Q(2) => mux_in_data(17),
Q(1) => mux_in_data(18),
Q(0) => mux_in_data(19),
SR(0) => crcComboRst,
\emac_tx_wr_data_d1_reg[0]\(3) => emac_tx_wr_data_d1(0),
\emac_tx_wr_data_d1_reg[0]\(2) => emac_tx_wr_data_d1(1),
\emac_tx_wr_data_d1_reg[0]\(1) => emac_tx_wr_data_d1(2),
\emac_tx_wr_data_d1_reg[0]\(0) => emac_tx_wr_data_d1(3),
s_axi_aclk => s_axi_aclk,
txCrcEn_reg => txCrcEn_reg
);
INST_DEFERRAL_CONTROL: entity work.system_axi_ethernetlite_0_0_deferral
port map (
D13_out => D13_out,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ => INST_TXBUSFIFOWRITENIBBLECOUNT_n_5,
Q(1 downto 0) => \inst_deferral_state/thisState\(1 downto 0),
enblPreamble => enblPreamble,
ldLngthCntr => ldLngthCntr,
phy_crs_d2 => phy_crs_d2,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \^ss\(0),
tx_clk_reg_d2 => tx_clk_reg_d2,
tx_clk_reg_d3 => tx_clk_reg_d3,
tx_en_i => tx_en_i
);
INST_TXBUSFIFOWRITENIBBLECOUNT: entity work.\system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\
port map (
\PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\ => INST_TX_STATE_MACHINE_n_63,
\PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\,
\PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\,
STATE11A => INST_TXBUSFIFOWRITENIBBLECOUNT_n_4,
STATE9A => INST_TXBUSFIFOWRITENIBBLECOUNT_n_5,
currentTxBusFifoWrCnt(3) => currentTxBusFifoWrCnt(8),
currentTxBusFifoWrCnt(2) => currentTxBusFifoWrCnt(9),
currentTxBusFifoWrCnt(1) => currentTxBusFifoWrCnt(10),
currentTxBusFifoWrCnt(0) => currentTxBusFifoWrCnt(11),
emac_tx_wr_i => emac_tx_wr_i,
s_axi_aclk => s_axi_aclk,
txComboBusFifoWrCntRst => txComboBusFifoWrCntRst
);
INST_TXNIBBLECOUNT: entity work.system_axi_ethernetlite_0_0_ld_arith_reg
port map (
CE => CE_1,
D21_out => D21_out,
S => S_0,
STATE13A(0) => currentTxNibbleCnt(11),
STATE13A_0 => INST_TXNIBBLECOUNT_n_3,
checkBusFifoFull => checkBusFifoFull,
enblData => enblData,
\out\ => txfifo_full,
s_axi_aclk => s_axi_aclk,
txComboNibbleCntRst => txComboNibbleCntRst,
\txNibbleCnt_pad_reg[11]\ => INST_TXNIBBLECOUNT_n_1,
\tx_packet_length_reg[15]\(15 downto 0) => \tx_packet_length_reg[15]\(15 downto 0)
);
INST_TX_INTRFCE: entity work.system_axi_ethernetlite_0_0_tx_intrfce
port map (
D(3) => emac_tx_wr_data_i(0),
D(2) => emac_tx_wr_data_i(1),
D(1) => emac_tx_wr_data_i(2),
D(0) => emac_tx_wr_data_i(3),
D18_out => D18_out,
DIA(0) => tx_en_mod,
E(0) => \I_TX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => bus_combo(5 downto 2),
Rst0 => Rst0,
STATE14A => INST_CRCCOUNTER_n_6,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => INST_TX_INTRFCE_n_1,
\out\ => txfifo_full,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
INST_TX_STATE_MACHINE: entity work.system_axi_ethernetlite_0_0_tx_statemachine
port map (
CE => CE_1,
CE_0 => CE,
D(11 downto 0) => p_1_in(11 downto 0),
D13_out => D13_out,
D18_out => D18_out,
D21_out => D21_out,
E(0) => \NSR/nibData\,
\PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ => INST_TX_STATE_MACHINE_n_63,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\(0) => currentTxNibbleCnt(11),
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_1\ => INST_TXBUSFIFOWRITENIBBLECOUNT_n_4,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_2\ => INST_TXBUSFIFOWRITENIBBLECOUNT_n_5,
\PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\ => INST_CRCCOUNTER_n_5,
\PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\ => INST_TXNIBBLECOUNT_n_3,
\PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\,
\PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\,
Q(3) => mux_in_data(16),
Q(2) => mux_in_data(17),
Q(1) => mux_in_data(18),
Q(0) => mux_in_data(19),
Rst0 => Rst0,
S => S_0,
SR(0) => crcComboRst,
STATE14A_0 => INST_CRCCOUNTER_n_6,
STATE24A_0 => STATE24A,
S_1 => S,
\TX_PONG_REG_GEN.pong_mac_program_reg\ => \TX_PONG_REG_GEN.pong_mac_program_reg\,
axi_phy_tx_en_i_p0 => axi_phy_tx_en_i_p0,
checkBusFifoFull => checkBusFifoFull,
checkBusFifoFullCrc => checkBusFifoFullCrc,
crcCnt(0 to 3) => crcCnt(0 to 3),
currentTxBusFifoWrCnt(3) => currentTxBusFifoWrCnt(8),
currentTxBusFifoWrCnt(2) => currentTxBusFifoWrCnt(9),
currentTxBusFifoWrCnt(1) => currentTxBusFifoWrCnt(10),
currentTxBusFifoWrCnt(0) => currentTxBusFifoWrCnt(11),
douta(3 downto 0) => douta(3 downto 0),
emac_tx_wr_d1 => emac_tx_wr_d1,
\emac_tx_wr_data_d1_reg[0]\ => INST_TX_STATE_MACHINE_n_16,
\emac_tx_wr_data_d1_reg[0]_0\ => INST_TX_STATE_MACHINE_n_17,
\emac_tx_wr_data_d1_reg[1]\ => INST_TX_STATE_MACHINE_n_15,
\emac_tx_wr_data_d1_reg[1]_0\ => INST_TX_STATE_MACHINE_n_18,
\emac_tx_wr_data_d1_reg[2]\ => INST_TX_STATE_MACHINE_n_14,
\emac_tx_wr_data_d1_reg[2]_0\ => INST_TX_STATE_MACHINE_n_20,
\emac_tx_wr_data_d1_reg[3]\ => INST_TX_STATE_MACHINE_n_13,
\emac_tx_wr_data_d1_reg[3]_0\ => INST_TX_STATE_MACHINE_n_19,
emac_tx_wr_i => emac_tx_wr_i,
enblCRC => enblCRC,
enblData => enblData,
enblPreamble => enblPreamble,
\gen_wr_b.gen_word_wide.mem_reg\ => \gen_wr_b.gen_word_wide.mem_reg\,
\gen_wr_b.gen_word_wide.mem_reg_0\ => \gen_wr_b.gen_word_wide.mem_reg_0\,
\gen_wr_b.gen_word_wide.mem_reg_1\(3 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_1\(3 downto 0),
\gic0.gc0.count_reg[0]\(0) => \I_TX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\,
ldLngthCntr => ldLngthCntr,
loopback_en_reg => loopback_en_reg,
loopback_en_reg_0 => loopback_en_reg_0,
loopback_en_reg_1 => loopback_en_reg_1,
mac_addr_ram_addr_wr(0 to 3) => mac_addr_ram_addr_wr(0 to 3),
mac_addr_ram_we => mac_addr_ram_we,
\out\ => txfifo_full,
p_15_in(0) => p_15_in(0),
p_17_in(0) => p_17_in(0),
ping_mac_program_reg(0) => ping_mac_program_reg(0),
ram_full_fb_i_reg => INST_TX_INTRFCE_n_1,
rx_done_d1 => rx_done_d1,
rx_pong_ping_l => rx_pong_ping_l,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(0),
\status_reg_reg[0]\(0) => E(0),
\status_reg_reg[5]\(5 downto 0) => D(5 downto 0),
\thisState_reg[1]\(1 downto 0) => \inst_deferral_state/thisState\(1 downto 0),
transmit_start_reg_reg_0 => \^ss\(0),
txComboBusFifoWrCntRst => txComboBusFifoWrCntRst,
txComboNibbleCntRst => txComboNibbleCntRst,
txCrcEn => txCrcEn,
txCrcEn_reg => txCrcEn_reg,
txNibbleCnt_pad0(10 downto 0) => txNibbleCnt_pad0(11 downto 1),
\txNibbleCnt_pad_reg[11]\(0) => INST_TX_STATE_MACHINE_n_35,
\txNibbleCnt_pad_reg[11]_0\ => ONR_HOT_MUX_n_4,
\txNibbleCnt_pad_reg[11]_1\(0) => txNibbleCnt_pad(11),
tx_addr_en => tx_addr_en,
tx_done_d2 => tx_done_d2,
tx_en_i => tx_en_i,
tx_intr_en0 => tx_intr_en0,
\tx_packet_length_reg[10]\(10 downto 0) => \tx_packet_length_reg[15]\(10 downto 0),
\tx_packet_length_reg[9]\ => INST_TXNIBBLECOUNT_n_1,
tx_pong_ping_l => tx_pong_ping_l,
\txbuffer_addr_reg[0]\ => \txbuffer_addr_reg[0]\,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
ONR_HOT_MUX: entity work.system_axi_ethernetlite_0_0_mux_onehot_f
port map (
D(3) => emac_tx_wr_data_i(0),
D(2) => emac_tx_wr_data_i(1),
D(1) => emac_tx_wr_data_i(2),
D(0) => emac_tx_wr_data_i(3),
Q(11) => txNibbleCnt_pad(0),
Q(10) => txNibbleCnt_pad(1),
Q(9) => txNibbleCnt_pad(2),
Q(8) => txNibbleCnt_pad(3),
Q(7) => txNibbleCnt_pad(4),
Q(6) => txNibbleCnt_pad(5),
Q(5) => txNibbleCnt_pad(6),
Q(4) => txNibbleCnt_pad(7),
Q(3) => txNibbleCnt_pad(8),
Q(2) => txNibbleCnt_pad(9),
Q(1) => txNibbleCnt_pad(10),
Q(0) => txNibbleCnt_pad(11),
STATE12A => INST_TX_STATE_MACHINE_n_20,
STATE15A => INST_TX_STATE_MACHINE_n_16,
STATE15A_0 => INST_TX_STATE_MACHINE_n_15,
STATE15A_1 => INST_TX_STATE_MACHINE_n_14,
STATE15A_2 => INST_TX_STATE_MACHINE_n_13,
\gen_wr_b.gen_word_wide.mem_reg\ => INST_TX_STATE_MACHINE_n_17,
\gen_wr_b.gen_word_wide.mem_reg_0\ => INST_TX_STATE_MACHINE_n_18,
\gen_wr_b.gen_word_wide.mem_reg_1\ => INST_TX_STATE_MACHINE_n_19,
\txNibbleCnt_pad_reg[11]\ => ONR_HOT_MUX_n_4
);
axi_phy_tx_en_i_p_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => axi_phy_tx_en_i_p0,
Q => axi_phy_tx_en_i_p,
R => \^ss\(0)
);
emac_tx_wr_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_i,
Q => emac_tx_wr_d1,
R => \^ss\(0)
);
\emac_tx_wr_data_d1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_data_i(0),
Q => emac_tx_wr_data_d1(0),
R => \^ss\(0)
);
\emac_tx_wr_data_d1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_data_i(1),
Q => emac_tx_wr_data_d1(1),
R => \^ss\(0)
);
\emac_tx_wr_data_d1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_data_i(2),
Q => emac_tx_wr_data_d1(2),
R => \^ss\(0)
);
\emac_tx_wr_data_d1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_data_i(3),
Q => emac_tx_wr_data_d1(3),
R => \^ss\(0)
);
fifo_tx_en_reg: unisim.vcomponents.FDRE
port map (
C => phy_tx_clk,
CE => '1',
D => CDC_TX_EN_n_0,
Q => fifo_tx_en,
R => '0'
);
\i__carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(3),
O => \i__carry__0_i_1_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(4),
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(5),
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(6),
O => \i__carry__0_i_4_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(0),
O => \i__carry__1_i_1_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(1),
O => \i__carry__1_i_2_n_0\
);
\i__carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(2),
O => \i__carry__1_i_3_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(7),
O => \i__carry_i_1_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(8),
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(9),
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(10),
O => \i__carry_i_4_n_0\
);
\txNibbleCnt_pad0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \txNibbleCnt_pad0_inferred__0/i__carry_n_0\,
CO(2) => \txNibbleCnt_pad0_inferred__0/i__carry_n_1\,
CO(1) => \txNibbleCnt_pad0_inferred__0/i__carry_n_2\,
CO(0) => \txNibbleCnt_pad0_inferred__0/i__carry_n_3\,
CYINIT => txNibbleCnt_pad(11),
DI(3) => txNibbleCnt_pad(7),
DI(2) => txNibbleCnt_pad(8),
DI(1) => txNibbleCnt_pad(9),
DI(0) => txNibbleCnt_pad(10),
O(3 downto 0) => txNibbleCnt_pad0(4 downto 1),
S(3) => \i__carry_i_1_n_0\,
S(2) => \i__carry_i_2_n_0\,
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
\txNibbleCnt_pad0_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \txNibbleCnt_pad0_inferred__0/i__carry_n_0\,
CO(3) => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_0\,
CO(2) => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_1\,
CO(1) => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_2\,
CO(0) => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => txNibbleCnt_pad(3),
DI(2) => txNibbleCnt_pad(4),
DI(1) => txNibbleCnt_pad(5),
DI(0) => txNibbleCnt_pad(6),
O(3 downto 0) => txNibbleCnt_pad0(8 downto 5),
S(3) => \i__carry__0_i_1_n_0\,
S(2) => \i__carry__0_i_2_n_0\,
S(1) => \i__carry__0_i_3_n_0\,
S(0) => \i__carry__0_i_4_n_0\
);
\txNibbleCnt_pad0_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_0\,
CO(3 downto 2) => \NLW_txNibbleCnt_pad0_inferred__0/i__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \txNibbleCnt_pad0_inferred__0/i__carry__1_n_2\,
CO(0) => \txNibbleCnt_pad0_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => txNibbleCnt_pad(1),
DI(0) => txNibbleCnt_pad(2),
O(3) => \NLW_txNibbleCnt_pad0_inferred__0/i__carry__1_O_UNCONNECTED\(3),
O(2 downto 0) => txNibbleCnt_pad0(11 downto 9),
S(3) => '0',
S(2) => \i__carry__1_i_1_n_0\,
S(1) => \i__carry__1_i_2_n_0\,
S(0) => \i__carry__1_i_3_n_0\
);
\txNibbleCnt_pad_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(11),
Q => txNibbleCnt_pad(0),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(1),
Q => txNibbleCnt_pad(10),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(0),
Q => txNibbleCnt_pad(11),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(10),
Q => txNibbleCnt_pad(1),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(9),
Q => txNibbleCnt_pad(2),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(8),
Q => txNibbleCnt_pad(3),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(7),
Q => txNibbleCnt_pad(4),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(6),
Q => txNibbleCnt_pad(5),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(5),
Q => txNibbleCnt_pad(6),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(4),
Q => txNibbleCnt_pad(7),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(3),
Q => txNibbleCnt_pad(8),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(2),
Q => txNibbleCnt_pad(9),
R => \^ss\(0)
);
txcrcen_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => txCrcEn,
Q => txCrcEn_reg,
R => \^ss\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac is
port (
prmry_in : out STD_LOGIC;
tx_idle : out STD_LOGIC;
txDone : out STD_LOGIC;
addra : out STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
wea : out STD_LOGIC_VECTOR ( 0 to 0 );
D_5 : out STD_LOGIC;
rx_done : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
loopback_en_reg : out STD_LOGIC;
ping_rx_status_reg : out STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : out STD_LOGIC;
ena : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_2\ : out STD_LOGIC;
prmry_vect_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ping_rx_status_reg_0 : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ : in STD_LOGIC;
douta : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\tx_packet_length_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_5_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_9_in : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_intr_en_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
tx_done_d2 : in STD_LOGIC;
p_17_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\TX_PONG_REG_GEN.pong_mac_program_reg\ : in STD_LOGIC;
p_15_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rx_pong_ping_l : in STD_LOGIC;
rx_done_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
tx_intr_en0 : in STD_LOGIC;
loopback_en_reg_0 : in STD_LOGIC;
rx_intr_en0 : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg\ : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac : entity is "axi_ethernetlite_v3_0_9_emac";
end system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac;
architecture STRUCTURE of system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac is
signal NODEMACADDRRAMI_n_0 : STD_LOGIC;
signal NODEMACADDRRAMI_n_1 : STD_LOGIC;
signal Phy_tx_clk_axi_d : STD_LOGIC;
signal RX_n_10 : STD_LOGIC;
signal TX_n_4 : STD_LOGIC;
signal \^addra\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal emac_rx_rd_data_d1 : STD_LOGIC_VECTOR ( 5 downto 2 );
signal \^gen_wr_b.gen_word_wide.mem_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal mac_addr_ram_addr : STD_LOGIC_VECTOR ( 0 to 3 );
signal mac_addr_ram_addr_rd : STD_LOGIC_VECTOR ( 0 to 3 );
signal mac_addr_ram_addr_wr : STD_LOGIC_VECTOR ( 0 to 3 );
signal mac_addr_ram_we : STD_LOGIC;
signal phy_crs_d1 : STD_LOGIC;
signal phy_crs_d2 : STD_LOGIC;
signal \^prmry_in\ : STD_LOGIC;
signal rx_addr_en : STD_LOGIC;
signal \rxbuffer_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[11]_i_6_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[11]_i_7_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[3]_i_2_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[7]_i_2_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_0\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_4\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_5\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_6\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_7\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \^txdone\ : STD_LOGIC;
signal tx_addr_en : STD_LOGIC;
signal tx_clk_reg_d1 : STD_LOGIC;
signal tx_clk_reg_d2 : STD_LOGIC;
signal tx_clk_reg_d3 : STD_LOGIC;
signal \txbuffer_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \txbuffer_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \txbuffer_addr[11]_i_6_n_0\ : STD_LOGIC;
signal \txbuffer_addr[11]_i_7_n_0\ : STD_LOGIC;
signal \txbuffer_addr[3]_i_2_n_0\ : STD_LOGIC;
signal \txbuffer_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \txbuffer_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \txbuffer_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \txbuffer_addr[7]_i_2_n_0\ : STD_LOGIC;
signal \txbuffer_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \txbuffer_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \txbuffer_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_0\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_4\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_5\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_6\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_7\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \NLW_rxbuffer_addr_reg[3]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_txbuffer_addr_reg[3]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of C_SENSE_SYNC_1 : label is "FDR";
attribute box_type : string;
attribute box_type of C_SENSE_SYNC_1 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of C_SENSE_SYNC_2 : label is "FDR";
attribute box_type of C_SENSE_SYNC_2 : label is "PRIMITIVE";
begin
addra(11 downto 0) <= \^addra\(11 downto 0);
\gen_wr_b.gen_word_wide.mem_reg\(11 downto 0) <= \^gen_wr_b.gen_word_wide.mem_reg\(11 downto 0);
prmry_in <= \^prmry_in\;
txDone <= \^txdone\;
CDC_TX_CLK: entity work.system_axi_ethernetlite_0_0_cdc_sync_7
port map (
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
scndry_out => Phy_tx_clk_axi_d
);
C_SENSE_SYNC_1: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => phy_crs,
Q => phy_crs_d1,
R => \^prmry_in\
);
C_SENSE_SYNC_2: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => phy_crs_d1,
Q => phy_crs_d2,
R => \^prmry_in\
);
NODEMACADDRRAMI: entity work.system_axi_ethernetlite_0_0_MacAddrRAM
port map (
Q(3 downto 0) => emac_rx_rd_data_d1(5 downto 2),
\gen_wr_b.gen_word_wide.mem_reg\(3 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_4\(3 downto 0),
mac_addr_ram_addr(0 to 3) => mac_addr_ram_addr(0 to 3),
mac_addr_ram_we => mac_addr_ram_we,
\rdDestAddrNib_D_t_q_reg[1]\ => NODEMACADDRRAMI_n_0,
\rdDestAddrNib_D_t_q_reg[1]_0\ => NODEMACADDRRAMI_n_1,
s_axi_aclk => s_axi_aclk
);
RX: entity work.system_axi_ethernetlite_0_0_receive
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
\AXI4_LITE_IF_GEN.write_in_prog_reg\ => \AXI4_LITE_IF_GEN.write_in_prog_reg\,
CLK => CLK,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
D_5 => D_5,
Q(3 downto 0) => Q(3 downto 0),
RX_DONE_D1_I => rx_done,
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ => \RX_PONG_REG_GEN.pong_rx_status_reg_0\,
SS(0) => \^prmry_in\,
STATE17A => \^txdone\,
checkingBroadcastAdr_reg_reg(3 downto 0) => emac_rx_rd_data_d1(5 downto 2),
\emac_rx_rd_data_d1_reg[1]_0\ => NODEMACADDRRAMI_n_0,
\emac_rx_rd_data_d1_reg[2]_0\ => NODEMACADDRRAMI_n_1,
ena => ena,
\gen_wr_b.gen_word_wide.mem_reg\ => \gen_wr_b.gen_word_wide.mem_reg_0\,
p_5_in(0) => p_5_in(0),
p_9_in(0) => p_9_in(0),
ping_rx_status_reg => ping_rx_status_reg,
ping_rx_status_reg_0 => ping_rx_status_reg_0,
\rdDestAddrNib_D_t_q_reg[1]\(3) => mac_addr_ram_addr_rd(0),
\rdDestAddrNib_D_t_q_reg[1]\(2) => mac_addr_ram_addr_rd(1),
\rdDestAddrNib_D_t_q_reg[1]\(1) => mac_addr_ram_addr_rd(2),
\rdDestAddrNib_D_t_q_reg[1]\(0) => mac_addr_ram_addr_rd(3),
rx_addr_en => rx_addr_en,
rx_intr_en0 => rx_intr_en0,
rx_pong_ping_l => rx_pong_ping_l,
\rxbuffer_addr_reg[0]\ => RX_n_10,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(0),
tx_intr_en_reg(0) => tx_intr_en_reg(1),
wea(0) => wea(0)
);
TX: entity work.system_axi_ethernetlite_0_0_transmit
port map (
D(5 downto 0) => D(5 downto 0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
SS(0) => \^prmry_in\,
STATE24A => \^txdone\,
\TX_PONG_REG_GEN.pong_mac_program_reg\ => \TX_PONG_REG_GEN.pong_mac_program_reg\,
douta(3 downto 0) => douta(3 downto 0),
\gen_wr_b.gen_word_wide.mem_reg\ => \gen_wr_b.gen_word_wide.mem_reg_1\,
\gen_wr_b.gen_word_wide.mem_reg_0\ => \gen_wr_b.gen_word_wide.mem_reg_2\,
\gen_wr_b.gen_word_wide.mem_reg_1\(3 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_3\(3 downto 0),
loopback_en_reg => tx_idle,
loopback_en_reg_0 => loopback_en_reg,
loopback_en_reg_1 => loopback_en_reg_0,
mac_addr_ram_addr_wr(0 to 3) => mac_addr_ram_addr_wr(0 to 3),
mac_addr_ram_we => mac_addr_ram_we,
p_15_in(0) => p_15_in(0),
p_17_in(0) => p_17_in(0),
phy_crs_d2 => phy_crs_d2,
phy_tx_clk => phy_tx_clk,
ping_mac_program_reg(0) => tx_intr_en_reg(0),
prmry_vect_in(3 downto 0) => prmry_vect_in(3 downto 0),
rx_done_d1 => rx_done_d1,
rx_pong_ping_l => rx_pong_ping_l,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(1),
tx_addr_en => tx_addr_en,
tx_clk_reg_d2 => tx_clk_reg_d2,
tx_clk_reg_d3 => tx_clk_reg_d3,
tx_done_d2 => tx_done_d2,
tx_intr_en0 => tx_intr_en0,
\tx_packet_length_reg[15]\(15 downto 0) => \tx_packet_length_reg[15]\(15 downto 0),
tx_pong_ping_l => tx_pong_ping_l,
\txbuffer_addr_reg[0]\ => TX_n_4
);
ram16x1_0_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_addr_ram_addr_wr(3),
I1 => mac_addr_ram_we,
I2 => mac_addr_ram_addr_rd(3),
O => mac_addr_ram_addr(3)
);
ram16x1_0_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_addr_ram_addr_wr(2),
I1 => mac_addr_ram_we,
I2 => mac_addr_ram_addr_rd(2),
O => mac_addr_ram_addr(2)
);
ram16x1_0_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_addr_ram_addr_wr(1),
I1 => mac_addr_ram_we,
I2 => mac_addr_ram_addr_rd(1),
O => mac_addr_ram_addr(1)
);
ram16x1_0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_addr_ram_addr_wr(0),
I1 => mac_addr_ram_we,
I2 => mac_addr_ram_addr_rd(0),
O => mac_addr_ram_addr(0)
);
\rxbuffer_addr[11]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(3),
O => \rxbuffer_addr[11]_i_4_n_0\
);
\rxbuffer_addr[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(2),
O => \rxbuffer_addr[11]_i_5_n_0\
);
\rxbuffer_addr[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(1),
O => \rxbuffer_addr[11]_i_6_n_0\
);
\rxbuffer_addr[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(0),
O => \rxbuffer_addr[11]_i_7_n_0\
);
\rxbuffer_addr[3]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(11),
O => \rxbuffer_addr[3]_i_2_n_0\
);
\rxbuffer_addr[3]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(10),
O => \rxbuffer_addr[3]_i_3_n_0\
);
\rxbuffer_addr[3]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(9),
O => \rxbuffer_addr[3]_i_4_n_0\
);
\rxbuffer_addr[3]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(8),
O => \rxbuffer_addr[3]_i_5_n_0\
);
\rxbuffer_addr[7]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(7),
O => \rxbuffer_addr[7]_i_2_n_0\
);
\rxbuffer_addr[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(6),
O => \rxbuffer_addr[7]_i_3_n_0\
);
\rxbuffer_addr[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(5),
O => \rxbuffer_addr[7]_i_4_n_0\
);
\rxbuffer_addr[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(4),
O => \rxbuffer_addr[7]_i_5_n_0\
);
\rxbuffer_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[3]_i_1_n_4\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(11),
R => RX_n_10
);
\rxbuffer_addr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[11]_i_3_n_6\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(1),
R => RX_n_10
);
\rxbuffer_addr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[11]_i_3_n_7\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(0),
R => RX_n_10
);
\rxbuffer_addr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rxbuffer_addr_reg[11]_i_3_n_0\,
CO(2) => \rxbuffer_addr_reg[11]_i_3_n_1\,
CO(1) => \rxbuffer_addr_reg[11]_i_3_n_2\,
CO(0) => \rxbuffer_addr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \rxbuffer_addr_reg[11]_i_3_n_4\,
O(2) => \rxbuffer_addr_reg[11]_i_3_n_5\,
O(1) => \rxbuffer_addr_reg[11]_i_3_n_6\,
O(0) => \rxbuffer_addr_reg[11]_i_3_n_7\,
S(3) => \rxbuffer_addr[11]_i_4_n_0\,
S(2) => \rxbuffer_addr[11]_i_5_n_0\,
S(1) => \rxbuffer_addr[11]_i_6_n_0\,
S(0) => \rxbuffer_addr[11]_i_7_n_0\
);
\rxbuffer_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[3]_i_1_n_5\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(10),
R => RX_n_10
);
\rxbuffer_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[3]_i_1_n_6\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(9),
R => RX_n_10
);
\rxbuffer_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[3]_i_1_n_7\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(8),
R => RX_n_10
);
\rxbuffer_addr_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rxbuffer_addr_reg[7]_i_1_n_0\,
CO(3) => \NLW_rxbuffer_addr_reg[3]_i_1_CO_UNCONNECTED\(3),
CO(2) => \rxbuffer_addr_reg[3]_i_1_n_1\,
CO(1) => \rxbuffer_addr_reg[3]_i_1_n_2\,
CO(0) => \rxbuffer_addr_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rxbuffer_addr_reg[3]_i_1_n_4\,
O(2) => \rxbuffer_addr_reg[3]_i_1_n_5\,
O(1) => \rxbuffer_addr_reg[3]_i_1_n_6\,
O(0) => \rxbuffer_addr_reg[3]_i_1_n_7\,
S(3) => \rxbuffer_addr[3]_i_2_n_0\,
S(2) => \rxbuffer_addr[3]_i_3_n_0\,
S(1) => \rxbuffer_addr[3]_i_4_n_0\,
S(0) => \rxbuffer_addr[3]_i_5_n_0\
);
\rxbuffer_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[7]_i_1_n_4\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(7),
R => RX_n_10
);
\rxbuffer_addr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[7]_i_1_n_5\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(6),
R => RX_n_10
);
\rxbuffer_addr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[7]_i_1_n_6\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(5),
R => RX_n_10
);
\rxbuffer_addr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[7]_i_1_n_7\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(4),
R => RX_n_10
);
\rxbuffer_addr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rxbuffer_addr_reg[11]_i_3_n_0\,
CO(3) => \rxbuffer_addr_reg[7]_i_1_n_0\,
CO(2) => \rxbuffer_addr_reg[7]_i_1_n_1\,
CO(1) => \rxbuffer_addr_reg[7]_i_1_n_2\,
CO(0) => \rxbuffer_addr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rxbuffer_addr_reg[7]_i_1_n_4\,
O(2) => \rxbuffer_addr_reg[7]_i_1_n_5\,
O(1) => \rxbuffer_addr_reg[7]_i_1_n_6\,
O(0) => \rxbuffer_addr_reg[7]_i_1_n_7\,
S(3) => \rxbuffer_addr[7]_i_2_n_0\,
S(2) => \rxbuffer_addr[7]_i_3_n_0\,
S(1) => \rxbuffer_addr[7]_i_4_n_0\,
S(0) => \rxbuffer_addr[7]_i_5_n_0\
);
\rxbuffer_addr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[11]_i_3_n_4\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(3),
R => RX_n_10
);
\rxbuffer_addr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[11]_i_3_n_5\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(2),
R => RX_n_10
);
tx_clk_reg_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Phy_tx_clk_axi_d,
Q => tx_clk_reg_d1,
R => \^prmry_in\
);
tx_clk_reg_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_clk_reg_d1,
Q => tx_clk_reg_d2,
R => \^prmry_in\
);
tx_clk_reg_d3_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_clk_reg_d2,
Q => tx_clk_reg_d3,
R => \^prmry_in\
);
\txbuffer_addr[11]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(3),
O => \txbuffer_addr[11]_i_4_n_0\
);
\txbuffer_addr[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(2),
O => \txbuffer_addr[11]_i_5_n_0\
);
\txbuffer_addr[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(1),
O => \txbuffer_addr[11]_i_6_n_0\
);
\txbuffer_addr[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^addra\(0),
O => \txbuffer_addr[11]_i_7_n_0\
);
\txbuffer_addr[3]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(11),
O => \txbuffer_addr[3]_i_2_n_0\
);
\txbuffer_addr[3]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(10),
O => \txbuffer_addr[3]_i_3_n_0\
);
\txbuffer_addr[3]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(9),
O => \txbuffer_addr[3]_i_4_n_0\
);
\txbuffer_addr[3]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(8),
O => \txbuffer_addr[3]_i_5_n_0\
);
\txbuffer_addr[7]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(7),
O => \txbuffer_addr[7]_i_2_n_0\
);
\txbuffer_addr[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(6),
O => \txbuffer_addr[7]_i_3_n_0\
);
\txbuffer_addr[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(5),
O => \txbuffer_addr[7]_i_4_n_0\
);
\txbuffer_addr[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(4),
O => \txbuffer_addr[7]_i_5_n_0\
);
\txbuffer_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[3]_i_1_n_4\,
Q => \^addra\(11),
R => TX_n_4
);
\txbuffer_addr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[11]_i_3_n_6\,
Q => \^addra\(1),
R => TX_n_4
);
\txbuffer_addr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[11]_i_3_n_7\,
Q => \^addra\(0),
R => TX_n_4
);
\txbuffer_addr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \txbuffer_addr_reg[11]_i_3_n_0\,
CO(2) => \txbuffer_addr_reg[11]_i_3_n_1\,
CO(1) => \txbuffer_addr_reg[11]_i_3_n_2\,
CO(0) => \txbuffer_addr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \txbuffer_addr_reg[11]_i_3_n_4\,
O(2) => \txbuffer_addr_reg[11]_i_3_n_5\,
O(1) => \txbuffer_addr_reg[11]_i_3_n_6\,
O(0) => \txbuffer_addr_reg[11]_i_3_n_7\,
S(3) => \txbuffer_addr[11]_i_4_n_0\,
S(2) => \txbuffer_addr[11]_i_5_n_0\,
S(1) => \txbuffer_addr[11]_i_6_n_0\,
S(0) => \txbuffer_addr[11]_i_7_n_0\
);
\txbuffer_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[3]_i_1_n_5\,
Q => \^addra\(10),
R => TX_n_4
);
\txbuffer_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[3]_i_1_n_6\,
Q => \^addra\(9),
R => TX_n_4
);
\txbuffer_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[3]_i_1_n_7\,
Q => \^addra\(8),
R => TX_n_4
);
\txbuffer_addr_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \txbuffer_addr_reg[7]_i_1_n_0\,
CO(3) => \NLW_txbuffer_addr_reg[3]_i_1_CO_UNCONNECTED\(3),
CO(2) => \txbuffer_addr_reg[3]_i_1_n_1\,
CO(1) => \txbuffer_addr_reg[3]_i_1_n_2\,
CO(0) => \txbuffer_addr_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \txbuffer_addr_reg[3]_i_1_n_4\,
O(2) => \txbuffer_addr_reg[3]_i_1_n_5\,
O(1) => \txbuffer_addr_reg[3]_i_1_n_6\,
O(0) => \txbuffer_addr_reg[3]_i_1_n_7\,
S(3) => \txbuffer_addr[3]_i_2_n_0\,
S(2) => \txbuffer_addr[3]_i_3_n_0\,
S(1) => \txbuffer_addr[3]_i_4_n_0\,
S(0) => \txbuffer_addr[3]_i_5_n_0\
);
\txbuffer_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[7]_i_1_n_4\,
Q => \^addra\(7),
R => TX_n_4
);
\txbuffer_addr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[7]_i_1_n_5\,
Q => \^addra\(6),
R => TX_n_4
);
\txbuffer_addr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[7]_i_1_n_6\,
Q => \^addra\(5),
R => TX_n_4
);
\txbuffer_addr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[7]_i_1_n_7\,
Q => \^addra\(4),
R => TX_n_4
);
\txbuffer_addr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \txbuffer_addr_reg[11]_i_3_n_0\,
CO(3) => \txbuffer_addr_reg[7]_i_1_n_0\,
CO(2) => \txbuffer_addr_reg[7]_i_1_n_1\,
CO(1) => \txbuffer_addr_reg[7]_i_1_n_2\,
CO(0) => \txbuffer_addr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \txbuffer_addr_reg[7]_i_1_n_4\,
O(2) => \txbuffer_addr_reg[7]_i_1_n_5\,
O(1) => \txbuffer_addr_reg[7]_i_1_n_6\,
O(0) => \txbuffer_addr_reg[7]_i_1_n_7\,
S(3) => \txbuffer_addr[7]_i_2_n_0\,
S(2) => \txbuffer_addr[7]_i_3_n_0\,
S(1) => \txbuffer_addr[7]_i_4_n_0\,
S(0) => \txbuffer_addr[7]_i_5_n_0\
);
\txbuffer_addr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[11]_i_3_n_4\,
Q => \^addra\(3),
R => TX_n_4
);
\txbuffer_addr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[11]_i_3_n_5\,
Q => \^addra\(2),
R => TX_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xemac is
port (
ip2intc_irpt : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
phy_mdc : out STD_LOGIC;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[31]\ : out STD_LOGIC;
p_33_in182_in : out STD_LOGIC;
p_21_in144_in : out STD_LOGIC;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[2]\ : out STD_LOGIC;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[1]\ : out STD_LOGIC;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[0]\ : out STD_LOGIC;
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
reg_access : out STD_LOGIC;
mdio_en_i : out STD_LOGIC;
\status_reg_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_IRPT_REG_I_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
p_9_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
pong_rx_status : out STD_LOGIC;
p_5_in : out STD_LOGIC_VECTOR ( 0 to 0 );
ping_soft_status : out STD_LOGIC;
pong_soft_status : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
\tx_packet_length_reg[15]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\tx_packet_length_reg[15]_1\ : out STD_LOGIC_VECTOR ( 14 downto 0 );
\reg_data_out_reg[0]_0\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[15]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
prmry_vect_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
prmry_in : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
phy_tx_clk : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_0\ : in STD_LOGIC;
phy_mdio_i : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.read_in_prog_reg\ : in STD_LOGIC;
reg_data_out0 : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[14]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[13]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[12]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[11]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[10]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[9]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[8]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[7]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[6]_0\ : in STD_LOGIC;
\reg_data_out_reg[31]_0\ : in STD_LOGIC;
\reg_data_out_reg[5]_0\ : in STD_LOGIC;
\reg_data_out_reg[3]_0\ : in STD_LOGIC;
\reg_data_out_reg[2]_0\ : in STD_LOGIC;
\reg_data_out_reg[1]_0\ : in STD_LOGIC;
\reg_data_out_reg[0]_1\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_en_i_reg_0\ : in STD_LOGIC;
tx_intr_en_reg_0 : in STD_LOGIC;
rx_intr_en_reg_0 : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg\ : in STD_LOGIC;
ping_soft_status_reg_0 : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_soft_status_reg_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_1\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_2\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_2\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_3\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_4\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_3\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\ : in STD_LOGIC;
p_19_out : in STD_LOGIC;
tx_intr_en0 : in STD_LOGIC;
rx_intr_en0 : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_1\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg_0\ : in STD_LOGIC;
p_44_out : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.read_in_prog_reg_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.read_in_prog_reg_6\ : in STD_LOGIC;
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[14]_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[13]_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[12]_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[11]_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xemac : entity is "xemac";
end system_axi_ethernetlite_0_0_xemac;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xemac is
signal \^axi4_lite_if_gen.ip2bus_data_sampled_reg[0]\ : STD_LOGIC;
signal \^axi4_lite_if_gen.ip2bus_data_sampled_reg[1]\ : STD_LOGIC;
signal \^axi4_lite_if_gen.ip2bus_data_sampled_reg[2]\ : STD_LOGIC;
signal \^axi4_lite_if_gen.ip2bus_data_sampled_reg[31]\ : STD_LOGIC;
signal D_5 : STD_LOGIC;
signal EMAC_I_n_34 : STD_LOGIC;
signal EMAC_I_n_35 : STD_LOGIC;
signal EMAC_I_n_36 : STD_LOGIC;
signal EMAC_I_n_37 : STD_LOGIC;
signal EMAC_I_n_38 : STD_LOGIC;
signal EMAC_I_n_39 : STD_LOGIC;
signal EMAC_I_n_40 : STD_LOGIC;
signal EMAC_I_n_41 : STD_LOGIC;
signal EMAC_I_n_42 : STD_LOGIC;
signal EMAC_I_n_43 : STD_LOGIC;
signal EMAC_I_n_44 : STD_LOGIC;
signal EMAC_I_n_45 : STD_LOGIC;
signal EMAC_I_n_46 : STD_LOGIC;
signal EMAC_I_n_47 : STD_LOGIC;
signal \^ip2intc_irpt_reg_i_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \MDIO_GEN.MDIO_IF_I_n_10\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_11\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_12\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_13\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_14\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_15\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_16\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_17\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_18\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_7\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_8\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_9\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \MDIO_GEN.mdio_clk_i_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_clk_i_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[1]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[7]_i_2_n_0\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[15]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \MDIO_GEN.mdio_data_out_reg_n_0_[0]\ : STD_LOGIC;
signal \MDIO_GEN.mdio_req_i_reg_n_0\ : STD_LOGIC;
signal Q_4 : STD_LOGIC;
signal \RX_PONG_GEN.rx_pong_ping_l_i_1_n_0\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \TX/INST_TX_STATE_MACHINE/txDone\ : STD_LOGIC;
signal \TX_PONG_GEN.tx_pong_ping_l_i_1_n_0\ : STD_LOGIC;
signal \TX_PONG_REG_GEN.pong_mac_program_i_1_n_0\ : STD_LOGIC;
signal \TX_PONG_REG_GEN.pong_tx_status_i_1_n_0\ : STD_LOGIC;
signal data7 : STD_LOGIC_VECTOR ( 4 to 4 );
signal loopback_en_reg_n_0 : STD_LOGIC;
signal \^mdio_en_i\ : STD_LOGIC;
signal mdio_wr_data_reg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_0_in_6 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_14_in125_in : STD_LOGIC;
signal p_15_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_17_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 31 downto 2 );
signal p_20_in : STD_LOGIC;
signal \^p_21_in144_in\ : STD_LOGIC;
signal p_26_in161_in : STD_LOGIC;
signal p_27_in163_in : STD_LOGIC;
signal p_2_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal p_32_in180_in : STD_LOGIC;
signal \^p_33_in182_in\ : STD_LOGIC;
signal p_38_in : STD_LOGIC;
signal p_39_in : STD_LOGIC;
signal p_44_in : STD_LOGIC;
signal p_45_in : STD_LOGIC;
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_50_in236_in : STD_LOGIC;
signal p_51_in : STD_LOGIC;
signal p_56_in : STD_LOGIC;
signal p_57_in : STD_LOGIC;
signal \^p_5_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_62_in270_in : STD_LOGIC;
signal p_63_in : STD_LOGIC;
signal p_68_in288_in : STD_LOGIC;
signal p_69_in : STD_LOGIC;
signal p_6_in : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_74_in307_in : STD_LOGIC;
signal p_75_in309_in : STD_LOGIC;
signal p_80_in328_in : STD_LOGIC;
signal p_81_in330_in : STD_LOGIC;
signal p_86_in349_in : STD_LOGIC;
signal p_87_in351_in : STD_LOGIC;
signal p_8_in107_in : STD_LOGIC;
signal p_92_in368_in : STD_LOGIC;
signal p_93_in : STD_LOGIC;
signal \^p_9_in\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^phy_mdc\ : STD_LOGIC;
signal ping_mac_program_i_1_n_0 : STD_LOGIC;
signal ping_pkt_lenth : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ping_tx_status_i_1_n_0 : STD_LOGIC;
signal pong_pkt_lenth : STD_LOGIC_VECTOR ( 4 to 4 );
signal \^pong_rx_status\ : STD_LOGIC;
signal \^reg_access\ : STD_LOGIC;
signal \reg_data_out[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_data_out[4]_i_2_n_0\ : STD_LOGIC;
signal rx_DPM_adr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal rx_DPM_wr_data : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rx_done : STD_LOGIC;
signal rx_done_d1 : STD_LOGIC;
signal rx_ping_data_out : STD_LOGIC_VECTOR ( 30 downto 0 );
signal rx_pong_ping_l : STD_LOGIC;
signal \^status_reg_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal tx_DPM_adr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal tx_DPM_rd_data : STD_LOGIC_VECTOR ( 3 downto 0 );
signal tx_done_d2 : STD_LOGIC;
signal tx_idle : STD_LOGIC;
signal tx_packet_length : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^tx_packet_length_reg[15]_0\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \^tx_packet_length_reg[15]_1\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal tx_ping_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal tx_ping_rd_data : STD_LOGIC_VECTOR ( 3 downto 0 );
signal tx_pong_ping_l : STD_LOGIC;
signal wr_rd_n_a_i : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of IP2INTC_IRPT_REG_I : label is "FDR";
attribute box_type : string;
attribute box_type of IP2INTC_IRPT_REG_I : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \MDIO_GEN.clk_cnt[2]_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \MDIO_GEN.clk_cnt[4]_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[1]_i_2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[7]_i_2\ : label is "soft_lutpair108";
attribute XILINX_LEGACY_PRIM of RX_DONE_D1_I : label is "FDR";
attribute box_type of RX_DONE_D1_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of TX_DONE_D1_I : label is "FDR";
attribute box_type of TX_DONE_D1_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of TX_DONE_D2_I : label is "FDR";
attribute box_type of TX_DONE_D2_I : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \tx_packet_length[0]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \tx_packet_length[10]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \tx_packet_length[11]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \tx_packet_length[12]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \tx_packet_length[13]_i_1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \tx_packet_length[14]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \tx_packet_length[15]_i_1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \tx_packet_length[1]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \tx_packet_length[2]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \tx_packet_length[3]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \tx_packet_length[4]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \tx_packet_length[5]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \tx_packet_length[6]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \tx_packet_length[7]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \tx_packet_length[8]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \tx_packet_length[9]_i_1\ : label is "soft_lutpair103";
begin
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[0]\ <= \^axi4_lite_if_gen.ip2bus_data_sampled_reg[0]\;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[1]\ <= \^axi4_lite_if_gen.ip2bus_data_sampled_reg[1]\;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[2]\ <= \^axi4_lite_if_gen.ip2bus_data_sampled_reg[2]\;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[31]\ <= \^axi4_lite_if_gen.ip2bus_data_sampled_reg[31]\;
IP2INTC_IRPT_REG_I_0(1 downto 0) <= \^ip2intc_irpt_reg_i_0\(1 downto 0);
\MDIO_GEN.mdio_data_out_reg[15]_0\(4 downto 0) <= \^mdio_gen.mdio_data_out_reg[15]_0\(4 downto 0);
SR(0) <= \^sr\(0);
mdio_en_i <= \^mdio_en_i\;
p_21_in144_in <= \^p_21_in144_in\;
p_33_in182_in <= \^p_33_in182_in\;
p_5_in(0) <= \^p_5_in\(0);
p_9_in(1 downto 0) <= \^p_9_in\(1 downto 0);
phy_mdc <= \^phy_mdc\;
pong_rx_status <= \^pong_rx_status\;
reg_access <= \^reg_access\;
\status_reg_reg[0]_0\(0) <= \^status_reg_reg[0]_0\(0);
\tx_packet_length_reg[15]_0\(13 downto 0) <= \^tx_packet_length_reg[15]_0\(13 downto 0);
\tx_packet_length_reg[15]_1\(14 downto 0) <= \^tx_packet_length_reg[15]_1\(14 downto 0);
EMAC_I: entity work.system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_1\,
\AXI4_LITE_IF_GEN.write_in_prog_reg\ => \AXI4_LITE_IF_GEN.write_in_prog_reg_0\,
CLK => CLK,
D(5) => EMAC_I_n_34,
D(4) => EMAC_I_n_35,
D(3) => EMAC_I_n_36,
D(2) => EMAC_I_n_37,
D(1) => EMAC_I_n_38,
D(0) => EMAC_I_n_39,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
D_5 => D_5,
E(0) => EMAC_I_n_40,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => prmry_in,
Q(3 downto 0) => rx_DPM_wr_data(3 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => EMAC_I_n_43,
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ => \^pong_rx_status\,
\TX_PONG_REG_GEN.pong_mac_program_reg\ => \^status_reg_reg[0]_0\(0),
addra(11 downto 0) => tx_DPM_adr(11 downto 0),
douta(3 downto 0) => tx_ping_rd_data(3 downto 0),
ena => EMAC_I_n_44,
\gen_wr_b.gen_word_wide.mem_reg\(11 downto 0) => rx_DPM_adr(11 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_0\ => EMAC_I_n_45,
\gen_wr_b.gen_word_wide.mem_reg_1\ => EMAC_I_n_46,
\gen_wr_b.gen_word_wide.mem_reg_2\ => EMAC_I_n_47,
\gen_wr_b.gen_word_wide.mem_reg_3\(3 downto 0) => p_4_out(3 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_4\(3 downto 0) => tx_DPM_rd_data(3 downto 0),
loopback_en_reg => EMAC_I_n_41,
loopback_en_reg_0 => loopback_en_reg_n_0,
p_15_in(0) => p_15_in(0),
p_17_in(0) => p_17_in(0),
p_5_in(0) => \^p_5_in\(0),
p_9_in(0) => \^p_9_in\(1),
phy_crs => phy_crs,
phy_tx_clk => phy_tx_clk,
ping_rx_status_reg => EMAC_I_n_42,
ping_rx_status_reg_0 => \^p_9_in\(0),
prmry_in => \^sr\(0),
prmry_vect_in(3 downto 0) => prmry_vect_in(3 downto 0),
rx_done => rx_done,
rx_done_d1 => rx_done_d1,
rx_intr_en0 => rx_intr_en0,
rx_pong_ping_l => rx_pong_ping_l,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(1) => s_axi_wdata(4),
s_axi_wdata(0) => s_axi_wdata(0),
txDone => \TX/INST_TX_STATE_MACHINE/txDone\,
tx_done_d2 => tx_done_d2,
tx_idle => tx_idle,
tx_intr_en0 => tx_intr_en0,
tx_intr_en_reg(1 downto 0) => \^ip2intc_irpt_reg_i_0\(1 downto 0),
\tx_packet_length_reg[15]\(15 downto 0) => tx_packet_length(15 downto 0),
tx_pong_ping_l => tx_pong_ping_l,
wea(0) => wr_rd_n_a_i
);
IP2INTC_IRPT_REG_I: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_5,
Q => ip2intc_irpt,
R => \^sr\(0)
);
\MDIO_GEN.MDIO_IF_I\: entity work.system_axi_ethernetlite_0_0_mdio_if
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\(0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_3\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\,
\AXI4_LITE_IF_GEN.read_in_prog_reg\ => \AXI4_LITE_IF_GEN.read_in_prog_reg_3\,
\AXI4_LITE_IF_GEN.read_in_prog_reg_0\ => \AXI4_LITE_IF_GEN.read_in_prog_reg_4\,
D(10) => \MDIO_GEN.MDIO_IF_I_n_7\,
D(9) => \MDIO_GEN.MDIO_IF_I_n_8\,
D(8) => \MDIO_GEN.MDIO_IF_I_n_9\,
D(7) => \MDIO_GEN.MDIO_IF_I_n_10\,
D(6) => \MDIO_GEN.MDIO_IF_I_n_11\,
D(5) => \MDIO_GEN.MDIO_IF_I_n_12\,
D(4) => \MDIO_GEN.MDIO_IF_I_n_13\,
D(3) => \MDIO_GEN.MDIO_IF_I_n_14\,
D(2) => \MDIO_GEN.MDIO_IF_I_n_15\,
D(1) => \MDIO_GEN.MDIO_IF_I_n_16\,
D(0) => \MDIO_GEN.MDIO_IF_I_n_17\,
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\(4 downto 0) => \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]\(4 downto 0),
\MDIO_GEN.mdio_clk_i_reg\ => \^phy_mdc\,
\MDIO_GEN.mdio_req_i_reg\ => \MDIO_GEN.MDIO_IF_I_n_18\,
\MDIO_GEN.mdio_req_i_reg_0\ => \MDIO_GEN.mdio_req_i_reg_n_0\,
\MDIO_GEN.mdio_wr_data_reg_reg[1]\ => \MDIO_GEN.mdio_data_out[1]_i_2_n_0\,
\MDIO_GEN.mdio_wr_data_reg_reg[7]\ => \MDIO_GEN.mdio_data_out[7]_i_2_n_0\,
Q(15 downto 11) => \^mdio_gen.mdio_data_out_reg[15]_0\(4 downto 0),
Q(10 downto 0) => mdio_wr_data_reg(10 downto 0),
mdio_en_i => \^mdio_en_i\,
p_19_out => p_19_out,
p_6_in(10 downto 0) => p_6_in(10 downto 0),
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
prmry_in => \^sr\(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(0)
);
\MDIO_GEN.clk_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
O => \MDIO_GEN.clk_cnt[0]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00FF00FF00FF00E"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I5 => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
O => \MDIO_GEN.clk_cnt[1]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
O => \MDIO_GEN.clk_cnt[2]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC9CCC9CCC9CCC8"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I5 => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
O => \MDIO_GEN.clk_cnt[3]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
O => \MDIO_GEN.clk_cnt[4]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000000"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I5 => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
O => \MDIO_GEN.clk_cnt[5]_i_1_n_0\
);
\MDIO_GEN.clk_cnt_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[0]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
S => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[1]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
R => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[2]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
S => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[3]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
R => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[4]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
S => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[5]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
R => \^sr\(0)
);
\MDIO_GEN.mdio_clk_i_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \MDIO_GEN.mdio_clk_i_i_2_n_0\,
I1 => \^phy_mdc\,
O => \MDIO_GEN.mdio_clk_i_i_1_n_0\
);
\MDIO_GEN.mdio_clk_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
I5 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
O => \MDIO_GEN.mdio_clk_i_i_2_n_0\
);
\MDIO_GEN.mdio_clk_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.mdio_clk_i_i_1_n_0\,
Q => \^phy_mdc\,
R => \^sr\(0)
);
\MDIO_GEN.mdio_data_out[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_wr_data_reg(1),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\,
O => \MDIO_GEN.mdio_data_out[1]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_wr_data_reg(7),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\,
O => \MDIO_GEN.mdio_data_out[7]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_17\,
Q => \MDIO_GEN.mdio_data_out_reg_n_0_[0]\,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_7\,
Q => p_62_in270_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.mdio_wr_data_reg_reg[11]_0\,
Q => p_68_in288_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.mdio_wr_data_reg_reg[12]_0\,
Q => p_74_in307_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.mdio_wr_data_reg_reg[13]_0\,
Q => p_80_in328_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.mdio_wr_data_reg_reg[14]_0\,
Q => p_86_in349_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\,
Q => p_92_in368_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_16\,
Q => p_8_in107_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_15\,
Q => p_14_in125_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_14\,
Q => p_20_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_13\,
Q => p_26_in161_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_12\,
Q => p_32_in180_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_11\,
Q => p_38_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_10\,
Q => p_44_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_9\,
Q => p_50_in236_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_8\,
Q => p_56_in,
R => '0'
);
\MDIO_GEN.mdio_en_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.mdio_en_i_reg_0\,
Q => \^mdio_en_i\,
R => \^sr\(0)
);
\MDIO_GEN.mdio_op_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(10),
Q => p_6_in(10),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => p_6_in(5),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => p_6_in(6),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => p_6_in(7),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(8),
Q => p_6_in(8),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(9),
Q => p_6_in(9),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => p_6_in(0),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => p_6_in(1),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => p_6_in(2),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => p_6_in(3),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => p_6_in(4),
R => \^sr\(0)
);
\MDIO_GEN.mdio_req_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.MDIO_IF_I_n_18\,
Q => \MDIO_GEN.mdio_req_i_reg_n_0\,
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(0),
Q => mdio_wr_data_reg(0),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(10),
Q => mdio_wr_data_reg(10),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(11),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(0),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(12),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(1),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(13),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(2),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(14),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(3),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(15),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(4),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(1),
Q => mdio_wr_data_reg(1),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(2),
Q => mdio_wr_data_reg(2),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(3),
Q => mdio_wr_data_reg(3),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(4),
Q => mdio_wr_data_reg(4),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(5),
Q => mdio_wr_data_reg(5),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(6),
Q => mdio_wr_data_reg(6),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(7),
Q => mdio_wr_data_reg(7),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(8),
Q => mdio_wr_data_reg(8),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(9),
Q => mdio_wr_data_reg(9),
R => \^sr\(0)
);
RX_DONE_D1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rx_done,
Q => rx_done_d1,
R => \^sr\(0)
);
RX_PING: entity work.system_axi_ethernetlite_0_0_emac_dpram
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
D(4) => D(31),
D(3) => D(13),
D(2) => D(11),
D(1) => D(8),
D(0) => D(2),
\MDIO_GEN.mdio_data_out_reg[8]\(1) => p_50_in236_in,
\MDIO_GEN.mdio_data_out_reg[8]\(0) => p_14_in125_in,
Q(3 downto 0) => rx_DPM_wr_data(3 downto 0),
doutb(26 downto 10) => rx_ping_data_out(30 downto 14),
doutb(9) => rx_ping_data_out(12),
doutb(8 downto 7) => rx_ping_data_out(10 downto 9),
doutb(6 downto 2) => rx_ping_data_out(7 downto 3),
doutb(1 downto 0) => rx_ping_data_out(1 downto 0),
ena => EMAC_I_n_44,
\gen_wr_b.gen_word_wide.mem_reg\(4) => p_1_out(31),
\gen_wr_b.gen_word_wide.mem_reg\(3) => p_1_out(13),
\gen_wr_b.gen_word_wide.mem_reg\(2) => p_1_out(11),
\gen_wr_b.gen_word_wide.mem_reg\(1) => p_1_out(8),
\gen_wr_b.gen_word_wide.mem_reg\(0) => p_1_out(2),
\gen_wr_b.gen_word_wide.mem_reg_0\(4) => tx_ping_data_out(31),
\gen_wr_b.gen_word_wide.mem_reg_0\(3) => tx_ping_data_out(13),
\gen_wr_b.gen_word_wide.mem_reg_0\(2) => tx_ping_data_out(11),
\gen_wr_b.gen_word_wide.mem_reg_0\(1) => tx_ping_data_out(8),
\gen_wr_b.gen_word_wide.mem_reg_0\(0) => tx_ping_data_out(2),
\gen_wr_b.gen_word_wide.mem_reg_1\(4) => p_2_out(31),
\gen_wr_b.gen_word_wide.mem_reg_1\(3) => p_2_out(13),
\gen_wr_b.gen_word_wide.mem_reg_1\(2) => p_2_out(11),
\gen_wr_b.gen_word_wide.mem_reg_1\(1) => p_2_out(8),
\gen_wr_b.gen_word_wide.mem_reg_1\(0) => p_2_out(2),
p_51_in => p_51_in,
p_68_in288_in => p_68_in288_in,
p_69_in => p_69_in,
p_80_in328_in => p_80_in328_in,
p_81_in330_in => p_81_in330_in,
reg_access_reg => \^reg_access\,
\reg_data_out_reg[2]\ => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[2]\,
\reg_data_out_reg[31]\ => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[31]\,
\rxbuffer_addr_reg[0]\(11 downto 0) => rx_DPM_adr(11 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
wea(0) => wr_rd_n_a_i,
web(0) => web(0)
);
\RX_PONG_GEN.RX_PONG_I\: entity work.system_axi_ethernetlite_0_0_emac_dpram_1
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(8 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_0\,
Q(3 downto 0) => rx_DPM_wr_data(3 downto 0),
doutb(31 downto 0) => p_2_out(31 downto 0),
\rxbuffer_addr_reg[0]\(11 downto 0) => rx_DPM_adr(11 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
state0a => EMAC_I_n_45,
wea(0) => wr_rd_n_a_i,
web(0) => web(0)
);
\RX_PONG_GEN.rx_pong_ping_l_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rx_done_d1,
I1 => rx_pong_ping_l,
O => \RX_PONG_GEN.rx_pong_ping_l_i_1_n_0\
);
\RX_PONG_GEN.rx_pong_ping_l_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RX_PONG_GEN.rx_pong_ping_l_i_1_n_0\,
Q => rx_pong_ping_l,
R => \^sr\(0)
);
\RX_PONG_REG_GEN.pong_rx_status_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => EMAC_I_n_43,
Q => \^pong_rx_status\,
R => \^sr\(0)
);
TX_DONE_D1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TX/INST_TX_STATE_MACHINE/txDone\,
Q => Q_4,
R => \^sr\(0)
);
TX_DONE_D2_I: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Q_4,
Q => tx_done_d2,
R => \^sr\(0)
);
TX_PING: entity work.system_axi_ethernetlite_0_0_emac_dpram_2
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(8 downto 0),
\TX_PONG_GEN.tx_pong_ping_l_reg\ => EMAC_I_n_46,
addra(11 downto 0) => tx_DPM_adr(11 downto 0),
douta(3 downto 0) => tx_ping_rd_data(3 downto 0),
doutb(31 downto 0) => tx_ping_data_out(31 downto 0),
enb => enb,
\gen_wr_b.gen_word_wide.mem_reg\(0) => p_4_out(1),
\rdDestAddrNib_D_t_q_reg[1]\(0) => tx_DPM_rd_data(1),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
tx_idle => tx_idle,
tx_pong_ping_l => tx_pong_ping_l,
web(0) => web(0)
);
\TX_PONG_GEN.TX_PONG_I\: entity work.system_axi_ethernetlite_0_0_emac_dpram_3
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
D(26 downto 10) => D(30 downto 14),
D(9) => D(12),
D(8 downto 7) => D(10 downto 9),
D(6 downto 2) => D(7 downto 3),
D(1 downto 0) => D(1 downto 0),
Q(8) => p_62_in270_in,
Q(7) => p_56_in,
Q(6) => p_44_in,
Q(5) => p_38_in,
Q(4) => p_32_in180_in,
Q(3) => p_26_in161_in,
Q(2) => p_20_in,
Q(1) => p_8_in107_in,
Q(0) => \MDIO_GEN.mdio_data_out_reg_n_0_[0]\,
\TX_PONG_GEN.tx_pong_ping_l_reg\ => EMAC_I_n_47,
addra(11 downto 0) => tx_DPM_adr(11 downto 0),
douta(3 downto 0) => p_4_out(3 downto 0),
doutb(4) => p_1_out(31),
doutb(3) => p_1_out(13),
doutb(2) => p_1_out(11),
doutb(1) => p_1_out(8),
doutb(0) => p_1_out(2),
\gen_wr_b.gen_word_wide.mem_reg\(2 downto 1) => tx_ping_rd_data(3 downto 2),
\gen_wr_b.gen_word_wide.mem_reg\(0) => tx_ping_rd_data(0),
\gen_wr_b.gen_word_wide.mem_reg_0\(26 downto 10) => rx_ping_data_out(30 downto 14),
\gen_wr_b.gen_word_wide.mem_reg_0\(9) => rx_ping_data_out(12),
\gen_wr_b.gen_word_wide.mem_reg_0\(8 downto 7) => rx_ping_data_out(10 downto 9),
\gen_wr_b.gen_word_wide.mem_reg_0\(6 downto 2) => rx_ping_data_out(7 downto 3),
\gen_wr_b.gen_word_wide.mem_reg_0\(1 downto 0) => rx_ping_data_out(1 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_1\(26 downto 10) => p_2_out(30 downto 14),
\gen_wr_b.gen_word_wide.mem_reg_1\(9) => p_2_out(12),
\gen_wr_b.gen_word_wide.mem_reg_1\(8 downto 7) => p_2_out(10 downto 9),
\gen_wr_b.gen_word_wide.mem_reg_1\(6 downto 2) => p_2_out(7 downto 3),
\gen_wr_b.gen_word_wide.mem_reg_1\(1 downto 0) => p_2_out(1 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_2\(26 downto 10) => tx_ping_data_out(30 downto 14),
\gen_wr_b.gen_word_wide.mem_reg_2\(9) => tx_ping_data_out(12),
\gen_wr_b.gen_word_wide.mem_reg_2\(8 downto 7) => tx_ping_data_out(10 downto 9),
\gen_wr_b.gen_word_wide.mem_reg_2\(6 downto 2) => tx_ping_data_out(7 downto 3),
\gen_wr_b.gen_word_wide.mem_reg_2\(1 downto 0) => tx_ping_data_out(1 downto 0),
p_21_in144_in => \^p_21_in144_in\,
p_27_in163_in => p_27_in163_in,
p_33_in182_in => \^p_33_in182_in\,
p_39_in => p_39_in,
p_45_in => p_45_in,
p_57_in => p_57_in,
p_63_in => p_63_in,
p_74_in307_in => p_74_in307_in,
p_75_in309_in => p_75_in309_in,
p_86_in349_in => p_86_in349_in,
p_87_in351_in => p_87_in351_in,
p_92_in368_in => p_92_in368_in,
p_93_in => p_93_in,
\rdDestAddrNib_D_t_q_reg[1]\(2 downto 1) => tx_DPM_rd_data(3 downto 2),
\rdDestAddrNib_D_t_q_reg[1]\(0) => tx_DPM_rd_data(0),
reg_access_reg => \^reg_access\,
\reg_data_out_reg[0]\ => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[0]\,
\reg_data_out_reg[1]\ => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[1]\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
tx_idle => tx_idle,
tx_pong_ping_l => tx_pong_ping_l,
web(0) => web(0)
);
\TX_PONG_GEN.tx_pong_ping_l_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"45AE"
)
port map (
I0 => Q_4,
I1 => p_15_in(0),
I2 => p_17_in(0),
I3 => tx_pong_ping_l,
O => \TX_PONG_GEN.tx_pong_ping_l_i_1_n_0\
);
\TX_PONG_GEN.tx_pong_ping_l_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TX_PONG_GEN.tx_pong_ping_l_i_1_n_0\,
Q => tx_pong_ping_l,
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_mac_program_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8888"
)
port map (
I0 => s_axi_wdata(1),
I1 => p_44_out,
I2 => Q_4,
I3 => tx_pong_ping_l,
I4 => \^status_reg_reg[0]_0\(0),
O => \TX_PONG_REG_GEN.pong_mac_program_i_1_n_0\
);
\TX_PONG_REG_GEN.pong_mac_program_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \TX_PONG_REG_GEN.pong_mac_program_i_1_n_0\,
Q => \^status_reg_reg[0]_0\(0),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(0),
Q => \^tx_packet_length_reg[15]_1\(0),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(10),
Q => \^tx_packet_length_reg[15]_1\(9),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(11),
Q => \^tx_packet_length_reg[15]_1\(10),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(12),
Q => \^tx_packet_length_reg[15]_1\(11),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(13),
Q => \^tx_packet_length_reg[15]_1\(12),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(14),
Q => \^tx_packet_length_reg[15]_1\(13),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(15),
Q => \^tx_packet_length_reg[15]_1\(14),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(1),
Q => \^tx_packet_length_reg[15]_1\(1),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(2),
Q => \^tx_packet_length_reg[15]_1\(2),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(3),
Q => \^tx_packet_length_reg[15]_1\(3),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(4),
Q => pong_pkt_lenth(4),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(5),
Q => \^tx_packet_length_reg[15]_1\(4),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(6),
Q => \^tx_packet_length_reg[15]_1\(5),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(7),
Q => \^tx_packet_length_reg[15]_1\(6),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(8),
Q => \^tx_packet_length_reg[15]_1\(7),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(9),
Q => \^tx_packet_length_reg[15]_1\(8),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_soft_status_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \TX_PONG_REG_GEN.pong_soft_status_reg_0\,
Q => pong_soft_status,
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_tx_status_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8888"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_44_out,
I2 => Q_4,
I3 => tx_pong_ping_l,
I4 => p_15_in(0),
O => \TX_PONG_REG_GEN.pong_tx_status_i_1_n_0\
);
\TX_PONG_REG_GEN.pong_tx_status_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \TX_PONG_REG_GEN.pong_tx_status_i_1_n_0\,
Q => p_15_in(0),
R => \^sr\(0)
);
gie_enable_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.write_in_prog_reg\,
Q => \^p_5_in\(0),
R => \^sr\(0)
);
loopback_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => EMAC_I_n_41,
Q => loopback_en_reg_n_0,
R => \^sr\(0)
);
ping_mac_program_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BB8888"
)
port map (
I0 => s_axi_wdata(1),
I1 => tx_intr_en0,
I2 => tx_pong_ping_l,
I3 => Q_4,
I4 => \^ip2intc_irpt_reg_i_0\(0),
O => ping_mac_program_i_1_n_0
);
ping_mac_program_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ping_mac_program_i_1_n_0,
Q => \^ip2intc_irpt_reg_i_0\(0),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(0),
Q => ping_pkt_lenth(0),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(10),
Q => \^tx_packet_length_reg[15]_0\(8),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(11),
Q => \^tx_packet_length_reg[15]_0\(9),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(12),
Q => \^tx_packet_length_reg[15]_0\(10),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(13),
Q => \^tx_packet_length_reg[15]_0\(11),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(14),
Q => \^tx_packet_length_reg[15]_0\(12),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(15),
Q => \^tx_packet_length_reg[15]_0\(13),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(1),
Q => \^tx_packet_length_reg[15]_0\(0),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(2),
Q => \^tx_packet_length_reg[15]_0\(1),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(3),
Q => \^tx_packet_length_reg[15]_0\(2),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(4),
Q => ping_pkt_lenth(4),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(5),
Q => \^tx_packet_length_reg[15]_0\(3),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(6),
Q => \^tx_packet_length_reg[15]_0\(4),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(7),
Q => \^tx_packet_length_reg[15]_0\(5),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(8),
Q => \^tx_packet_length_reg[15]_0\(6),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(9),
Q => \^tx_packet_length_reg[15]_0\(7),
R => \^sr\(0)
);
ping_rx_status_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => EMAC_I_n_42,
Q => \^p_9_in\(0),
R => \^sr\(0)
);
ping_soft_status_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ping_soft_status_reg_0,
Q => ping_soft_status,
R => \^sr\(0)
);
ping_tx_status_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BB8888"
)
port map (
I0 => s_axi_wdata(0),
I1 => tx_intr_en0,
I2 => tx_pong_ping_l,
I3 => Q_4,
I4 => p_17_in(0),
O => ping_tx_status_i_1_n_0
);
ping_tx_status_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ping_tx_status_i_1_n_0,
Q => p_17_in(0),
R => \^sr\(0)
);
reg_access_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.read_in_prog_reg_0\,
Q => \^reg_access\,
R => \^sr\(0)
);
\reg_data_out[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFF222F222"
)
port map (
I0 => p_17_in(0),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_2\,
I2 => p_15_in(0),
I3 => \AXI4_LITE_IF_GEN.read_in_prog_reg_2\,
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
I5 => ping_pkt_lenth(0),
O => \reg_data_out_reg[0]_0\
);
\reg_data_out[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2E2EEE2"
)
port map (
I0 => p_27_in163_in,
I1 => reg_data_out0,
I2 => \reg_data_out[4]_i_2_n_0\,
I3 => data7(4),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\,
I5 => \AXI4_LITE_IF_GEN.read_in_prog_reg_1\,
O => \reg_data_out[4]_i_1_n_0\
);
\reg_data_out[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFF22F222F2"
)
port map (
I0 => ping_pkt_lenth(4),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
I2 => pong_pkt_lenth(4),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_2\,
I5 => loopback_en_reg_n_0,
O => \reg_data_out[4]_i_2_n_0\
);
\reg_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[0]_1\,
Q => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[0]\,
R => '0'
);
\reg_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[10]_0\,
Q => p_63_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[11]_0\,
Q => p_69_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[12]_0\,
Q => p_75_in309_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[13]_0\,
Q => p_81_in330_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[14]_0\,
Q => p_87_in351_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\,
Q => p_93_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[1]_0\,
Q => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[1]\,
R => '0'
);
\reg_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[2]_0\,
Q => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[2]\,
R => '0'
);
\reg_data_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[31]_0\,
Q => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[31]\,
R => '0'
);
\reg_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[3]_0\,
Q => \^p_21_in144_in\,
R => '0'
);
\reg_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out[4]_i_1_n_0\,
Q => p_27_in163_in,
R => '0'
);
\reg_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[5]_0\,
Q => \^p_33_in182_in\,
R => '0'
);
\reg_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[6]_0\,
Q => p_39_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[7]_0\,
Q => p_45_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[8]_0\,
Q => p_51_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[9]_0\,
Q => p_57_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
rx_intr_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rx_intr_en_reg_0,
Q => \^p_9_in\(1),
R => \^sr\(0)
);
\status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_39,
Q => Q(0),
R => '0'
);
\status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_38,
Q => Q(1),
R => '0'
);
\status_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_37,
Q => Q(2),
R => '0'
);
\status_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_36,
Q => Q(3),
R => '0'
);
\status_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_35,
Q => data7(4),
R => '0'
);
\status_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_34,
Q => Q(4),
R => '0'
);
tx_intr_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_intr_en_reg_0,
Q => \^ip2intc_irpt_reg_i_0\(1),
R => \^sr\(0)
);
\tx_packet_length[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(0),
I1 => tx_pong_ping_l,
I2 => ping_pkt_lenth(0),
O => p_0_in_6(0)
);
\tx_packet_length[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(9),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(8),
O => p_0_in_6(10)
);
\tx_packet_length[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(10),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(9),
O => p_0_in_6(11)
);
\tx_packet_length[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(11),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(10),
O => p_0_in_6(12)
);
\tx_packet_length[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(12),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(11),
O => p_0_in_6(13)
);
\tx_packet_length[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(13),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(12),
O => p_0_in_6(14)
);
\tx_packet_length[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(14),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(13),
O => p_0_in_6(15)
);
\tx_packet_length[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(1),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(0),
O => p_0_in_6(1)
);
\tx_packet_length[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(2),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(1),
O => p_0_in_6(2)
);
\tx_packet_length[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(3),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(2),
O => p_0_in_6(3)
);
\tx_packet_length[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => pong_pkt_lenth(4),
I1 => tx_pong_ping_l,
I2 => ping_pkt_lenth(4),
O => p_0_in_6(4)
);
\tx_packet_length[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(4),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(3),
O => p_0_in_6(5)
);
\tx_packet_length[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(5),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(4),
O => p_0_in_6(6)
);
\tx_packet_length[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(6),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(5),
O => p_0_in_6(7)
);
\tx_packet_length[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(7),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(6),
O => p_0_in_6(8)
);
\tx_packet_length[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(8),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(7),
O => p_0_in_6(9)
);
\tx_packet_length_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(0),
Q => tx_packet_length(0),
R => \^sr\(0)
);
\tx_packet_length_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(10),
Q => tx_packet_length(10),
R => \^sr\(0)
);
\tx_packet_length_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(11),
Q => tx_packet_length(11),
R => \^sr\(0)
);
\tx_packet_length_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(12),
Q => tx_packet_length(12),
R => \^sr\(0)
);
\tx_packet_length_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(13),
Q => tx_packet_length(13),
R => \^sr\(0)
);
\tx_packet_length_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(14),
Q => tx_packet_length(14),
R => \^sr\(0)
);
\tx_packet_length_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(15),
Q => tx_packet_length(15),
R => \^sr\(0)
);
\tx_packet_length_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(1),
Q => tx_packet_length(1),
R => \^sr\(0)
);
\tx_packet_length_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(2),
Q => tx_packet_length(2),
R => \^sr\(0)
);
\tx_packet_length_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(3),
Q => tx_packet_length(3),
R => \^sr\(0)
);
\tx_packet_length_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(4),
Q => tx_packet_length(4),
R => \^sr\(0)
);
\tx_packet_length_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(5),
Q => tx_packet_length(5),
R => \^sr\(0)
);
\tx_packet_length_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(6),
Q => tx_packet_length(6),
R => \^sr\(0)
);
\tx_packet_length_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(7),
Q => tx_packet_length(7),
R => \^sr\(0)
);
\tx_packet_length_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(8),
Q => tx_packet_length(8),
R => \^sr\(0)
);
\tx_packet_length_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(9),
Q => tx_packet_length(9),
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_axi_ethernetlite is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
phy_rx_clk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
phy_dv : in STD_LOGIC;
phy_rx_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_col : in STD_LOGIC;
phy_rx_er : in STD_LOGIC;
phy_rst_n : out STD_LOGIC;
phy_tx_en : out STD_LOGIC;
phy_tx_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_mdio_i : in STD_LOGIC;
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
phy_mdc : out STD_LOGIC
);
attribute C_DUPLEX : integer;
attribute C_DUPLEX of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "artix7";
attribute C_INCLUDE_GLOBAL_BUFFERS : integer;
attribute C_INCLUDE_GLOBAL_BUFFERS of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_INCLUDE_INTERNAL_LOOPBACK : integer;
attribute C_INCLUDE_INTERNAL_LOOPBACK of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 0;
attribute C_INCLUDE_MDIO : integer;
attribute C_INCLUDE_MDIO of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "axi_ethernetlite_inst";
attribute C_RX_PING_PONG : integer;
attribute C_RX_PING_PONG of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_S_AXI_ACLK_PERIOD_PS : integer;
attribute C_S_AXI_ACLK_PERIOD_PS of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 10000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 13;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "AXI4LITE";
attribute C_TX_PING_PONG : integer;
attribute C_TX_PING_PONG of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "axi_ethernetlite";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "yes";
end system_axi_ethernetlite_0_0_axi_ethernetlite;
architecture STRUCTURE of system_axi_ethernetlite_0_0_axi_ethernetlite is
signal \<const0>\ : STD_LOGIC;
signal C : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_10 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_11 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_12 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_13 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_14 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_15 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_16 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_18 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_3 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_30 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_31 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_32 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_33 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_34 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_35 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_36 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_37 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_38 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_39 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_40 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_48 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_49 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_5 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_50 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_51 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_53 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_54 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_55 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_56 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_57 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_58 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_59 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_6 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_60 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_61 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_62 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_63 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_64 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_65 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_66 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_67 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_68 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_69 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_7 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_70 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_71 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_72 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_8 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_9 : STD_LOGIC;
signal \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal Q0_out : STD_LOGIC;
signal Q2_out : STD_LOGIC;
signal Q4_out : STD_LOGIC;
signal XEMAC_I_n_3 : STD_LOGIC;
signal XEMAC_I_n_33 : STD_LOGIC;
signal XEMAC_I_n_34 : STD_LOGIC;
signal XEMAC_I_n_35 : STD_LOGIC;
signal XEMAC_I_n_36 : STD_LOGIC;
signal XEMAC_I_n_37 : STD_LOGIC;
signal XEMAC_I_n_38 : STD_LOGIC;
signal XEMAC_I_n_39 : STD_LOGIC;
signal XEMAC_I_n_40 : STD_LOGIC;
signal XEMAC_I_n_41 : STD_LOGIC;
signal XEMAC_I_n_42 : STD_LOGIC;
signal XEMAC_I_n_43 : STD_LOGIC;
signal XEMAC_I_n_44 : STD_LOGIC;
signal XEMAC_I_n_45 : STD_LOGIC;
signal XEMAC_I_n_46 : STD_LOGIC;
signal XEMAC_I_n_47 : STD_LOGIC;
signal XEMAC_I_n_6 : STD_LOGIC;
signal XEMAC_I_n_7 : STD_LOGIC;
signal XEMAC_I_n_8 : STD_LOGIC;
signal XEMAC_I_n_93 : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 12 downto 2 );
signal bus_rst : STD_LOGIC;
signal bus_rst_rx_sync_core : STD_LOGIC;
signal bus_rst_tx_sync_core : STD_LOGIC;
signal data7 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal ip2bus_data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal mdio_en_i : STD_LOGIC;
signal mdio_rd_data_reg : STD_LOGIC_VECTOR ( 15 downto 11 );
signal mdio_wr_data_reg : STD_LOGIC_VECTOR ( 15 downto 11 );
signal o : STD_LOGIC;
signal p_15_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal p_15_out : STD_LOGIC;
signal p_17_in : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_17_out : STD_LOGIC;
signal p_19_out : STD_LOGIC;
signal p_21_in144_in : STD_LOGIC;
signal p_33_in182_in : STD_LOGIC;
signal p_38_out : STD_LOGIC;
signal p_44_out : STD_LOGIC;
signal p_5_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_9_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal phy_dv_reg : STD_LOGIC;
signal phy_rx_er_reg : STD_LOGIC;
signal phy_tx_clk_core : STD_LOGIC;
signal phy_tx_data_i : STD_LOGIC_VECTOR ( 3 downto 0 );
signal phy_tx_data_i_cdc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal phy_tx_en_i : STD_LOGIC;
signal phy_tx_en_i_cdc : STD_LOGIC;
signal ping_pkt_lenth : STD_LOGIC_VECTOR ( 15 downto 1 );
signal ping_pkt_lenth0 : STD_LOGIC;
signal ping_soft_status : STD_LOGIC;
signal pong_pkt_lenth : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pong_rx_status : STD_LOGIC;
signal pong_soft_status : STD_LOGIC;
signal reg_access : STD_LOGIC;
signal reg_data_out0 : STD_LOGIC;
signal rx_intr_en0 : STD_LOGIC;
signal \^s_axi_aresetn\ : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of s_axi_aresetn : signal is "found";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal tx_intr_en0 : STD_LOGIC;
attribute box_type : string;
attribute box_type of \IOFFS_GEN2.DVD_FF\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN2.RER_FF\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN2.TEN_FF\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[0].RX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[0].TX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[1].RX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[1].TX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[2].RX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[2].TX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[3].RX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[3].TX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_RX\ : label is "PRIMITIVE";
attribute box_type of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_TX\ : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\ : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\ : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\ : label is "AUTO";
attribute box_type of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\ : label is "PRIMITIVE";
attribute CAPACITANCE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\ : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\ : label is "0";
attribute IFD_DELAY_VALUE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\ : label is "AUTO";
attribute box_type of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\ : label is "PRIMITIVE";
begin
\^s_axi_aresetn\ <= s_axi_aresetn;
phy_rst_n <= \^s_axi_aresetn\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \^s_axi_rlast\;
s_axi_wready <= \^s_axi_wready\;
BUS_RST_RX_SYNC_CORE_I: entity work.system_axi_ethernetlite_0_0_cdc_sync
port map (
CLK => C,
SR(0) => bus_rst,
scndry_out => bus_rst_rx_sync_core
);
BUS_RST_TX_SYNC_CORE_I: entity work.system_axi_ethernetlite_0_0_cdc_sync_0
port map (
CLK => phy_tx_clk_core,
SR(0) => bus_rst,
scndry_out => bus_rst_tx_sync_core
);
CDC_PHY_TX_DATA_OUT: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized1\
port map (
CLK => phy_tx_clk_core,
prmry_vect_in(3 downto 0) => phy_tx_data_i(3 downto 0),
scndry_vect_out(3 downto 0) => phy_tx_data_i_cdc(3 downto 0)
);
CDC_PHY_TX_EN_O: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized0\
port map (
CLK => phy_tx_clk_core,
prmry_in => phy_tx_en_i,
scndry_out => phy_tx_en_i_cdc
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\IOFFS_GEN2.DVD_FF\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_dv,
Q => phy_dv_reg,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN2.RER_FF\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_er,
Q => phy_rx_er_reg,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN2.TEN_FF\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_en_i_cdc,
Q => phy_tx_en,
R => bus_rst_tx_sync_core
);
\IOFFS_GEN[0].RX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_data(0),
Q => Q0_out,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN[0].TX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_data_i_cdc(0),
Q => phy_tx_data(0),
R => bus_rst_tx_sync_core
);
\IOFFS_GEN[1].RX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_data(1),
Q => Q2_out,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN[1].TX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_data_i_cdc(1),
Q => phy_tx_data(1),
R => bus_rst_tx_sync_core
);
\IOFFS_GEN[2].RX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_data(2),
Q => Q4_out,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN[2].TX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_data_i_cdc(2),
Q => phy_tx_data(2),
R => bus_rst_tx_sync_core
);
\IOFFS_GEN[3].RX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_data(3),
Q => Q,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN[3].TX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_data_i_cdc(3),
Q => phy_tx_data(3),
R => bus_rst_tx_sync_core
);
I_AXI_NATIVE_IPIF: entity work.system_axi_ethernetlite_0_0_axi_interface
port map (
D(31) => ip2bus_data(31),
D(30) => XEMAC_I_n_33,
D(29) => XEMAC_I_n_34,
D(28) => XEMAC_I_n_35,
D(27) => XEMAC_I_n_36,
D(26) => XEMAC_I_n_37,
D(25) => XEMAC_I_n_38,
D(24) => XEMAC_I_n_39,
D(23) => XEMAC_I_n_40,
D(22) => XEMAC_I_n_41,
D(21) => XEMAC_I_n_42,
D(20) => XEMAC_I_n_43,
D(19) => XEMAC_I_n_44,
D(18) => XEMAC_I_n_45,
D(17) => XEMAC_I_n_46,
D(16) => XEMAC_I_n_47,
D(15 downto 0) => ip2bus_data(15 downto 0),
E(0) => ping_pkt_lenth0,
\MDIO_GEN.mdio_data_out_reg[11]\ => I_AXI_NATIVE_IPIF_n_48,
\MDIO_GEN.mdio_data_out_reg[11]_0\ => I_AXI_NATIVE_IPIF_n_51,
\MDIO_GEN.mdio_data_out_reg[11]_1\ => I_AXI_NATIVE_IPIF_n_70,
\MDIO_GEN.mdio_data_out_reg[11]_2\(0) => I_AXI_NATIVE_IPIF_n_71,
\MDIO_GEN.mdio_data_out_reg[11]_3\ => I_AXI_NATIVE_IPIF_n_72,
\MDIO_GEN.mdio_data_out_reg[12]\ => I_AXI_NATIVE_IPIF_n_69,
\MDIO_GEN.mdio_data_out_reg[13]\ => I_AXI_NATIVE_IPIF_n_68,
\MDIO_GEN.mdio_data_out_reg[14]\ => I_AXI_NATIVE_IPIF_n_67,
\MDIO_GEN.mdio_data_out_reg[15]\ => I_AXI_NATIVE_IPIF_n_49,
\MDIO_GEN.mdio_data_out_reg[15]_0\ => I_AXI_NATIVE_IPIF_n_65,
\MDIO_GEN.mdio_data_out_reg[15]_1\ => I_AXI_NATIVE_IPIF_n_66,
\MDIO_GEN.mdio_data_out_reg[3]\ => I_AXI_NATIVE_IPIF_n_50,
\MDIO_GEN.mdio_en_i_reg\ => I_AXI_NATIVE_IPIF_n_54,
\MDIO_GEN.mdio_reg_addr_reg[4]\(0) => p_17_out,
\MDIO_GEN.mdio_wr_data_reg_reg[15]\(0) => p_15_out,
\MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(4 downto 0) => mdio_wr_data_reg(15 downto 11),
Q(4) => data7(5),
Q(3 downto 0) => data7(3 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => I_AXI_NATIVE_IPIF_n_16,
SR(0) => bus_rst,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]\(0) => p_38_out,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(14 downto 4) => pong_pkt_lenth(15 downto 5),
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(3 downto 0) => pong_pkt_lenth(3 downto 0),
\TX_PONG_REG_GEN.pong_soft_status_reg\ => I_AXI_NATIVE_IPIF_n_56,
enb => I_AXI_NATIVE_IPIF_n_59,
\gen_wr_b.gen_word_wide.mem_reg\ => I_AXI_NATIVE_IPIF_n_60,
\gen_wr_b.gen_word_wide.mem_reg_0\ => I_AXI_NATIVE_IPIF_n_61,
\gen_wr_b.gen_word_wide.mem_reg_1\ => I_AXI_NATIVE_IPIF_n_62,
gie_enable_reg => I_AXI_NATIVE_IPIF_n_55,
mdio_en_i => mdio_en_i,
mdio_rd_data_reg(4 downto 0) => mdio_rd_data_reg(15 downto 11),
p_15_in(0) => p_15_in(1),
p_17_in(1) => p_17_in(3),
p_17_in(0) => p_17_in(1),
p_19_out => p_19_out,
p_21_in144_in => p_21_in144_in,
p_33_in182_in => p_33_in182_in,
p_44_out => p_44_out,
p_5_in(0) => p_5_in(31),
p_9_in(1) => p_9_in(3),
p_9_in(0) => p_9_in(0),
\ping_pkt_lenth_reg[15]\ => I_AXI_NATIVE_IPIF_n_18,
\ping_pkt_lenth_reg[15]_0\(13 downto 3) => ping_pkt_lenth(15 downto 5),
\ping_pkt_lenth_reg[15]_0\(2 downto 0) => ping_pkt_lenth(3 downto 1),
ping_soft_status => ping_soft_status,
ping_soft_status_reg => I_AXI_NATIVE_IPIF_n_57,
ping_tx_status_reg => XEMAC_I_n_93,
pong_rx_status => pong_rx_status,
pong_soft_status => pong_soft_status,
reg_access => reg_access,
reg_access_reg => I_AXI_NATIVE_IPIF_n_53,
reg_data_out0 => reg_data_out0,
\reg_data_out_reg[0]\ => I_AXI_NATIVE_IPIF_n_9,
\reg_data_out_reg[0]_0\ => XEMAC_I_n_8,
\reg_data_out_reg[10]\ => I_AXI_NATIVE_IPIF_n_36,
\reg_data_out_reg[11]\ => I_AXI_NATIVE_IPIF_n_35,
\reg_data_out_reg[12]\ => I_AXI_NATIVE_IPIF_n_34,
\reg_data_out_reg[13]\ => I_AXI_NATIVE_IPIF_n_33,
\reg_data_out_reg[14]\ => I_AXI_NATIVE_IPIF_n_32,
\reg_data_out_reg[15]\ => I_AXI_NATIVE_IPIF_n_31,
\reg_data_out_reg[1]\ => I_AXI_NATIVE_IPIF_n_7,
\reg_data_out_reg[1]_0\ => I_AXI_NATIVE_IPIF_n_8,
\reg_data_out_reg[1]_1\ => XEMAC_I_n_7,
\reg_data_out_reg[2]\ => I_AXI_NATIVE_IPIF_n_11,
\reg_data_out_reg[2]_0\ => XEMAC_I_n_6,
\reg_data_out_reg[31]\ => I_AXI_NATIVE_IPIF_n_3,
\reg_data_out_reg[31]_0\ => I_AXI_NATIVE_IPIF_n_5,
\reg_data_out_reg[31]_1\ => XEMAC_I_n_3,
\reg_data_out_reg[3]\ => I_AXI_NATIVE_IPIF_n_6,
\reg_data_out_reg[3]_0\ => I_AXI_NATIVE_IPIF_n_12,
\reg_data_out_reg[3]_1\(10 downto 0) => bus2ip_addr(12 downto 2),
\reg_data_out_reg[4]\ => I_AXI_NATIVE_IPIF_n_30,
\reg_data_out_reg[5]\ => I_AXI_NATIVE_IPIF_n_10,
\reg_data_out_reg[6]\ => I_AXI_NATIVE_IPIF_n_13,
\reg_data_out_reg[6]_0\ => I_AXI_NATIVE_IPIF_n_14,
\reg_data_out_reg[6]_1\ => I_AXI_NATIVE_IPIF_n_15,
\reg_data_out_reg[6]_2\ => I_AXI_NATIVE_IPIF_n_40,
\reg_data_out_reg[7]\ => I_AXI_NATIVE_IPIF_n_39,
\reg_data_out_reg[8]\ => I_AXI_NATIVE_IPIF_n_38,
\reg_data_out_reg[9]\ => I_AXI_NATIVE_IPIF_n_37,
rx_intr_en0 => rx_intr_en0,
rx_intr_en_reg => I_AXI_NATIVE_IPIF_n_64,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(12 downto 2),
s_axi_aresetn => \^s_axi_aresetn\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(12 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => \^s_axi_rlast\,
s_axi_rready => s_axi_rready,
s_axi_wdata(1) => s_axi_wdata(31),
s_axi_wdata(0) => s_axi_wdata(3),
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
tx_intr_en0 => tx_intr_en0,
tx_intr_en_reg => I_AXI_NATIVE_IPIF_n_58,
web(0) => I_AXI_NATIVE_IPIF_n_63
);
\NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_RX\: unisim.vcomponents.BUFG
port map (
I => \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST_n_0\,
O => C
);
\NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_TX\: unisim.vcomponents.BUFG
port map (
I => o,
O => phy_tx_clk_core
);
\NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => phy_rx_clk,
O => \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST_n_0\
);
\NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => phy_tx_clk,
O => o
);
XEMAC_I: entity work.system_axi_ethernetlite_0_0_xemac
port map (
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[0]\ => XEMAC_I_n_8,
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[1]\ => XEMAC_I_n_7,
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[2]\ => XEMAC_I_n_6,
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[31]\ => XEMAC_I_n_3,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => I_AXI_NATIVE_IPIF_n_62,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_0\ => I_AXI_NATIVE_IPIF_n_60,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_1\ => I_AXI_NATIVE_IPIF_n_16,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0) => bus2ip_addr(12 downto 2),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\ => I_AXI_NATIVE_IPIF_n_61,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\ => I_AXI_NATIVE_IPIF_n_8,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\ => I_AXI_NATIVE_IPIF_n_14,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\ => I_AXI_NATIVE_IPIF_n_13,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_2\ => I_AXI_NATIVE_IPIF_n_12,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_3\ => I_AXI_NATIVE_IPIF_n_49,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\ => I_AXI_NATIVE_IPIF_n_66,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0) => ping_pkt_lenth0,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0) => p_38_out,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0) => p_15_out,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => I_AXI_NATIVE_IPIF_n_51,
\AXI4_LITE_IF_GEN.read_in_prog_reg\ => I_AXI_NATIVE_IPIF_n_15,
\AXI4_LITE_IF_GEN.read_in_prog_reg_0\ => I_AXI_NATIVE_IPIF_n_53,
\AXI4_LITE_IF_GEN.read_in_prog_reg_1\ => I_AXI_NATIVE_IPIF_n_30,
\AXI4_LITE_IF_GEN.read_in_prog_reg_2\ => I_AXI_NATIVE_IPIF_n_5,
\AXI4_LITE_IF_GEN.read_in_prog_reg_3\ => I_AXI_NATIVE_IPIF_n_48,
\AXI4_LITE_IF_GEN.read_in_prog_reg_4\ => I_AXI_NATIVE_IPIF_n_50,
\AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0) => I_AXI_NATIVE_IPIF_n_71,
\AXI4_LITE_IF_GEN.read_in_prog_reg_6\ => I_AXI_NATIVE_IPIF_n_72,
\AXI4_LITE_IF_GEN.write_in_prog_reg\ => I_AXI_NATIVE_IPIF_n_55,
\AXI4_LITE_IF_GEN.write_in_prog_reg_0\ => I_AXI_NATIVE_IPIF_n_18,
CLK => C,
D(31) => ip2bus_data(31),
D(30) => XEMAC_I_n_33,
D(29) => XEMAC_I_n_34,
D(28) => XEMAC_I_n_35,
D(27) => XEMAC_I_n_36,
D(26) => XEMAC_I_n_37,
D(25) => XEMAC_I_n_38,
D(24) => XEMAC_I_n_39,
D(23) => XEMAC_I_n_40,
D(22) => XEMAC_I_n_41,
D(21) => XEMAC_I_n_42,
D(20) => XEMAC_I_n_43,
D(19) => XEMAC_I_n_44,
D(18) => XEMAC_I_n_45,
D(17) => XEMAC_I_n_46,
D(16) => XEMAC_I_n_47,
D(15 downto 0) => ip2bus_data(15 downto 0),
DIA(1) => phy_dv_reg,
DIA(0) => phy_rx_er_reg,
DIB(1) => Q2_out,
DIB(0) => Q0_out,
DIC(1) => Q,
DIC(0) => Q4_out,
E(0) => p_17_out,
IP2INTC_IRPT_REG_I_0(1) => p_17_in(3),
IP2INTC_IRPT_REG_I_0(0) => p_17_in(1),
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]\(4 downto 0) => mdio_rd_data_reg(15 downto 11),
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\ => I_AXI_NATIVE_IPIF_n_65,
\MDIO_GEN.mdio_data_out_reg[15]_0\(4 downto 0) => mdio_wr_data_reg(15 downto 11),
\MDIO_GEN.mdio_en_i_reg_0\ => I_AXI_NATIVE_IPIF_n_54,
\MDIO_GEN.mdio_wr_data_reg_reg[11]_0\ => I_AXI_NATIVE_IPIF_n_70,
\MDIO_GEN.mdio_wr_data_reg_reg[12]_0\ => I_AXI_NATIVE_IPIF_n_69,
\MDIO_GEN.mdio_wr_data_reg_reg[13]_0\ => I_AXI_NATIVE_IPIF_n_68,
\MDIO_GEN.mdio_wr_data_reg_reg[14]_0\ => I_AXI_NATIVE_IPIF_n_67,
Q(4) => data7(5),
Q(3 downto 0) => data7(3 downto 0),
SR(0) => bus_rst,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[10]_0\ => I_AXI_NATIVE_IPIF_n_36,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[11]_0\ => I_AXI_NATIVE_IPIF_n_35,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[12]_0\ => I_AXI_NATIVE_IPIF_n_34,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[13]_0\ => I_AXI_NATIVE_IPIF_n_33,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[14]_0\ => I_AXI_NATIVE_IPIF_n_32,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\ => I_AXI_NATIVE_IPIF_n_31,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[6]_0\ => I_AXI_NATIVE_IPIF_n_40,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[7]_0\ => I_AXI_NATIVE_IPIF_n_39,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[8]_0\ => I_AXI_NATIVE_IPIF_n_38,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[9]_0\ => I_AXI_NATIVE_IPIF_n_37,
\TX_PONG_REG_GEN.pong_soft_status_reg_0\ => I_AXI_NATIVE_IPIF_n_56,
enb => I_AXI_NATIVE_IPIF_n_59,
ip2intc_irpt => ip2intc_irpt,
mdio_en_i => mdio_en_i,
p_19_out => p_19_out,
p_21_in144_in => p_21_in144_in,
p_33_in182_in => p_33_in182_in,
p_44_out => p_44_out,
p_5_in(0) => p_5_in(31),
p_9_in(1) => p_9_in(3),
p_9_in(0) => p_9_in(0),
phy_crs => phy_crs,
phy_mdc => phy_mdc,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_tx_clk => phy_tx_clk_core,
ping_soft_status => ping_soft_status,
ping_soft_status_reg_0 => I_AXI_NATIVE_IPIF_n_57,
pong_rx_status => pong_rx_status,
pong_soft_status => pong_soft_status,
prmry_in => phy_tx_en_i,
prmry_vect_in(3 downto 0) => phy_tx_data_i(3 downto 0),
reg_access => reg_access,
reg_data_out0 => reg_data_out0,
\reg_data_out_reg[0]_0\ => XEMAC_I_n_93,
\reg_data_out_reg[0]_1\ => I_AXI_NATIVE_IPIF_n_9,
\reg_data_out_reg[1]_0\ => I_AXI_NATIVE_IPIF_n_7,
\reg_data_out_reg[2]_0\ => I_AXI_NATIVE_IPIF_n_11,
\reg_data_out_reg[31]_0\ => I_AXI_NATIVE_IPIF_n_3,
\reg_data_out_reg[3]_0\ => I_AXI_NATIVE_IPIF_n_6,
\reg_data_out_reg[5]_0\ => I_AXI_NATIVE_IPIF_n_10,
rx_intr_en0 => rx_intr_en0,
rx_intr_en_reg_0 => I_AXI_NATIVE_IPIF_n_64,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \^s_axi_aresetn\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
\status_reg_reg[0]_0\(0) => p_15_in(1),
tx_intr_en0 => tx_intr_en0,
tx_intr_en_reg_0 => I_AXI_NATIVE_IPIF_n_58,
\tx_packet_length_reg[15]_0\(13 downto 3) => ping_pkt_lenth(15 downto 5),
\tx_packet_length_reg[15]_0\(2 downto 0) => ping_pkt_lenth(3 downto 1),
\tx_packet_length_reg[15]_1\(14 downto 4) => pong_pkt_lenth(15 downto 5),
\tx_packet_length_reg[15]_1\(3 downto 0) => pong_pkt_lenth(3 downto 0),
web(0) => I_AXI_NATIVE_IPIF_n_63
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
phy_rx_clk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
phy_dv : in STD_LOGIC;
phy_rx_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_col : in STD_LOGIC;
phy_rx_er : in STD_LOGIC;
phy_rst_n : out STD_LOGIC;
phy_tx_en : out STD_LOGIC;
phy_tx_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_mdio_i : in STD_LOGIC;
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
phy_mdc : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_ethernetlite_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_ethernetlite_0_0 : entity is "system_axi_ethernetlite_0_0,axi_ethernetlite,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_ethernetlite_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_ethernetlite_0_0 : entity is "axi_ethernetlite,Vivado 2016.4";
end system_axi_ethernetlite_0_0;
architecture STRUCTURE of system_axi_ethernetlite_0_0 is
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_DUPLEX : integer;
attribute C_DUPLEX of U0 : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_INCLUDE_GLOBAL_BUFFERS : integer;
attribute C_INCLUDE_GLOBAL_BUFFERS of U0 : label is 1;
attribute C_INCLUDE_INTERNAL_LOOPBACK : integer;
attribute C_INCLUDE_INTERNAL_LOOPBACK of U0 : label is 0;
attribute C_INCLUDE_MDIO : integer;
attribute C_INCLUDE_MDIO of U0 : label is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of U0 : label is "axi_ethernetlite_inst";
attribute C_RX_PING_PONG : integer;
attribute C_RX_PING_PONG of U0 : label is 1;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 1;
attribute C_S_AXI_ACLK_PERIOD_PS : integer;
attribute C_S_AXI_ACLK_PERIOD_PS of U0 : label is 10000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 13;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4LITE";
attribute C_TX_PING_PONG : integer;
attribute C_TX_PING_PONG of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_axi_ethernetlite_0_0_axi_ethernetlite
port map (
ip2intc_irpt => ip2intc_irpt,
phy_col => phy_col,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_mdc => phy_mdc,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_rst_n => phy_rst_n,
phy_rx_clk => phy_rx_clk,
phy_rx_data(3 downto 0) => phy_rx_data(3 downto 0),
phy_rx_er => phy_rx_er,
phy_tx_clk => phy_tx_clk,
phy_tx_data(3 downto 0) => phy_tx_data(3 downto 0),
phy_tx_en => phy_tx_en,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(12 downto 0) => s_axi_araddr(12 downto 0),
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(12 downto 0) => s_axi_awaddr(12 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => '1',
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
d8de3c2e6bae549c3d33bcfa8f6d68bc
| 0.594145 | 2.791467 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/microblaze_0_wrapper.vhd
| 1 | 87,392 |
-------------------------------------------------------------------------------
-- microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_20_a;
use microblaze_v8_20_a.all;
entity microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 3);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 31);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 31);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 3);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 31);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 31);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of microblaze_0_wrapper : entity is "microblaze_v8_20_a";
end microblaze_0_wrapper;
architecture STRUCTURE of microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 50000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "spartan6",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 1,
C_STREAM_INTERCONNECT => 0,
C_DPLB_DWIDTH => 32,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 32,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 0,
C_D_PLB => 1,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 1,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 0,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 8192,
C_ICACHE_USE_FSL => 1,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 1,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 0,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
|
gpl-2.0
|
21de0f841589a56de930b66943f3fbf9
| 0.605868 | 2.749473 | false | false | false | false |
daniw/add
|
floppy/mcu/tb_mcu.vhd
| 1 | 1,246 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity tb_mcu is
end tb_mcu;
architecture TB of tb_mcu is
signal rst : std_logic;
signal clk : std_logic := '0';
signal LED : std_logic_vector(7 downto 0);
signal SW : std_logic_vector(3 downto 0);
signal ROT_C : std_logic;
signal BTN_EAST : std_logic;
signal BTN_WEST : std_logic;
signal BTN_NORTH : std_logic;
signal LCD : std_logic_vector(LCD_PW-1 downto 0);
signal step_to_floppy : std_logic;
signal dir_to_floppy : std_logic;
begin
-- instantiate MUT
MUT : entity work.mcu
port map(
rst => rst,
clk => clk,
LED => LED,
SW => SW,
ROT_C => ROT_C,
BTN_EAST => BTN_EAST,
BTN_WEST => BTN_WEST,
BTN_NORTH => BTN_NORTH,
LCD => LCD,
step_to_floppy => step_to_floppy,
dir_to_floppy => dir_to_floppy
);
-- generate reset
rst <= '1', '0' after 5us;
ROT_C <= '1', '0' after 1ms;
SW <= "0011";
BTN_EAST <= '0';
BTN_WEST <= '0';
BTN_NORTH <= '0';
-- clock generation
p_clk: process
begin
wait for 1 sec / CF/2;
clk <= not clk;
end process;
end TB;
|
gpl-2.0
|
035ebb4032470305e97becf6064a8833
| 0.550562 | 3.061425 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/alu_toplevel.vhd
| 3 | 2,604 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
mit
|
e56106f7be53fb5600ba6a658f6cee55
| 0.490783 | 3.869242 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/PSR.vhd
| 1 | 845 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( NZVC : in STD_LOGIC_VECTOR (3 downto 0);
nCWP: in STD_LOGIC;
CLK: in STD_LOGIC;
rst: in STD_LOGIC;
icc: out STD_LOGIC_VECTOR(3 downto 0);
CWP: out STD_LOGIC;
C : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
--signal PSRegister: std_logic_vector(4 downto 0):=(others=>'0');
begin
process(NZVC,nCWP,CLK,rst)
begin
if rst='1' then
--PSRegister<=(others=>'0');
C<='0';
CWP<='0';
icc<=(others=>'0');
elsif rising_edge(CLK) then
--if not(NZVC="1111") then
--PSRegister(4 downto 1)<=NZVC;
--end if;
--PSRegister(0)<=nCWP;
--CWP<=PSRegister(0);
CWP<=nCWP;
--C<=PSRegister(1);
C<=NZVC(0);
--icc<=PSRegister(4 downto 1);
icc<=NZVC;
end if;
end process;
end Behavioral;
|
mit
|
7aec5857ba4258db2ce248176fdc6033
| 0.591716 | 2.883959 | false | false | false | false |
hly11/CollisionDetectionFPGA
|
hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_2_0/synth/design_1_axi_vdma_2_0.vhd
| 1 | 28,345 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2;
USE axi_vdma_v6_2.axi_vdma;
ENTITY design_1_axi_vdma_2_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC
);
END design_1_axi_vdma_2_0;
ARCHITECTURE design_1_axi_vdma_2_0_arch OF design_1_axi_vdma_2_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_vdma_2_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_vdma_2_0_arch: ARCHITECTURE IS "axi_vdma,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_vdma_2_0_arch : ARCHITECTURE IS "design_1_axi_vdma_2_0,axi_vdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_vdma_2_0_arch: ARCHITECTURE IS "design_1_axi_vdma_2_0,axi_vdma,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=0,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=3,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=512,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=1,C_S2MM_GENLOCK_MODE=2,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_10=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 0,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 3,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 512,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 1,
C_S2MM_GENLOCK_MODE => 2,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => '0',
mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut
);
END design_1_axi_vdma_2_0_arch;
|
gpl-2.0
|
fbb5da563f2cb6858f12cf10595ed282
| 0.677509 | 2.730995 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/PC_tb.vhd
| 1 | 1,799 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PC_tb IS
END PC_tb;
ARCHITECTURE behavior OF PC_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PC
PORT(
rst : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
DataOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal dataIn : std_logic_vector(31 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal DataOut : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PC PORT MAP (
rst => rst,
dataIn => dataIn,
CLK => CLK,
DataOut => DataOut
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
dataIn<="00100010001000100010001000100010";
wait for 40 ns;
dataIn<="00000000000000000000000000000011";
wait for 80 ns;
rst<='1';
dataIn<="00100010001000100010001000100010";
wait for 40 ns;
dataIn<="00000000000000000000000000000011";
wait for 80 ns;
rst<='0';
dataIn<="11100010001000100010001111100010";
wait for 40 ns;
dataIn<="00000000000000111111100001111111";
wait for 40 ns;
dataIn<="01010010100101001100100100010010";
wait for 40 ns;
dataIn<="01011110100001011110100001101000";
wait for 20 ns;
dataIn<="00000000000000000000000000111010";
wait;
end process;
END;
|
mit
|
97aa1db3aaa167d0125745251d75c31c
| 0.598666 | 3.962555 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_lmb_bram_0/synth/system_lmb_bram_0.vhd
| 1 | 15,532 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY system_lmb_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_lmb_bram_0;
ARCHITECTURE system_lmb_bram_0_arch OF system_lmb_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_lmb_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_lmb_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_lmb_bram_0_arch : ARCHITECTURE IS "system_lmb_bram_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_lmb_bram_0_arch: ARCHITECTURE IS "system_lmb_bram_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_c" &
"oe_file_loaded,C_INIT_FILE=system_lmb_bram_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=8192,C_READ_DEPTH_A=8192,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WI" &
"DTH_B=32,C_WRITE_DEPTH_B=8192,C_READ_DEPTH_B=8192,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAF" &
"ETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 19.3686 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "system_lmb_bram_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 8192,
C_READ_DEPTH_A => 8192,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 8192,
C_READ_DEPTH_B => 8192,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 19.3686 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END system_lmb_bram_0_arch;
|
apache-2.0
|
2fb709658f7bb08238733ec0bfb9dc1f
| 0.633144 | 3.02709 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/lib/add_sub/cl_logic.vhd
| 2 | 2,085 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:41:32 02/12/2014
-- Design Name:
-- Module Name: full_adder_1_bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cl_logic is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Cin1 : out STD_LOGIC;
Cin2 : out STD_LOGIC;
Cin3 : out STD_LOGIC;
Cout : out STD_LOGIC);
end cl_logic;
architecture Behavioral of cl_logic is
begin
-- Cin1 = G_0 + P_0 * Cin0
Cin1 <= ( A(0) AND B(0) )
OR ( (Cin)
AND (A(0) OR B(0)) );
-- Cin2 = G_1 + P_1 * Cin1
Cin2 <= ( A(1) AND B(1) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1)) );
-- Cin3 = G_2 + P_2 * Cin2
Cin3 <= ( A(2) AND B(2) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2)) );
-- Cout = G_3 + P_3 * Cin3
Cout <= ( A(3) AND B(3) )
OR ( (A(2) AND B(2))
AND (A(3) OR B(3)) )
OR ( (A(1) AND B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (A(0) AND B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) )
OR ( (Cin)
AND (A(0) OR B(0))
AND (A(1) OR B(1))
AND (A(2) OR B(2))
AND (A(3) OR B(3)) );
end Behavioral;
|
agpl-3.0
|
44fdc7bd0e4d0bf5b717dfac3c0c4394
| 0.480096 | 2.697283 | false | false | false | false |
hly11/CollisionDetectionFPGA
|
hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_100M_3/synth/design_1_rst_processing_system7_0_100M_3.vhd
| 1 | 6,831 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_processing_system7_0_100M_3 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_processing_system7_0_100M_3;
ARCHITECTURE design_1_rst_processing_system7_0_100M_3_arch OF design_1_rst_processing_system7_0_100M_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_100M_3_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_processing_system7_0_100M_3_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_processing_system7_0_100M_3_arch : ARCHITECTURE IS "design_1_rst_processing_system7_0_100M_3,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_processing_system7_0_100M_3_arch: ARCHITECTURE IS "design_1_rst_processing_system7_0_100M_3,proc_sys_reset,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_processing_system7_0_100M_3_arch;
|
gpl-2.0
|
6341fd361a3d6eae330d4b48faede8d5
| 0.717465 | 3.437846 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/SEUdisp30_tb.vhd
| 1 | 913 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SEUdisp30_tb IS
END SEUdisp30_tb;
ARCHITECTURE behavior OF SEUdisp30_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SEUdisp30
PORT(
disp30 : IN std_logic_vector(29 downto 0);
SEUdisp30 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal disp30 : std_logic_vector(29 downto 0) := (others => '0');
--Outputs
signal SEUdisp30 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SEUdisp30 PORT MAP (
disp30 => disp30,
SEUdisp30 => SEUdisp30
);
-- Stimulus process
stim_proc: process
begin
disp30<="10000000000010000000000000011";
wait for 20 ns;
disp30<="00000000000000000000000001010";
wait;
end process;
END;
|
mit
|
0d4fa13889727e7ca4ed22abba40b714
| 0.605696 | 4.039823 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/lmb_bram_wrapper.vhd
| 1 | 2,861 |
-------------------------------------------------------------------------------
-- lmb_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_elaborate_v1_00_a;
use lmb_bram_elaborate_v1_00_a.all;
entity lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of lmb_bram_wrapper : entity is "lmb_bram_elaborate_v1_00_a";
attribute keep_hierarchy of lmb_bram_wrapper : entity is "yes";
end lmb_bram_wrapper;
architecture STRUCTURE of lmb_bram_wrapper is
component lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
lmb_bram : lmb_bram_elaborate
generic map (
C_MEMSIZE => 16#8000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "spartan6"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
|
gpl-2.0
|
83ca69875055eed59605c06897ab6e8e
| 0.569381 | 2.940391 | false | false | false | false |
daniw/add
|
floppy/mcu/rom.vhd
| 1 | 6,890 |
-------------------------------------------------------------------------------
-- Entity: rom
-- Author: Waj
-- Date : 11-May-13, 26-May-13
-------------------------------------------------------------------------------
-- Total # of FFs: DW
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity rom is
port(clk : in std_logic;
-- ROM bus signals
bus_in : in t_bus2ros;
bus_out : out t_ros2bus
);
end rom;
architecture rtl of rom is
type t_rom is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
constant rom_table : t_rom := (
---------------------------------------------------------------------------
-- program code -----------------------------------------------------------
---------------------------------------------------------------------------
-- addr Opcode Rdest Rsrc1 Rsrc2 description
---------------------------------------------------------------------------
-- auto generated by asmtovhd from floppy.asm
0 => OPC(setih) & reg(0) & std_logic_vector(to_unsigned(0,DW/2)), --
1 => OPC(setih) & reg(1) & std_logic_vector(to_unsigned(0,DW/2)), --
2 => OPC(setih) & reg(2) & std_logic_vector(to_unsigned(0,DW/2)), --
3 => OPC(setih) & reg(3) & std_logic_vector(to_unsigned(0,DW/2)), --
4 => OPC(setih) & reg(4) & std_logic_vector(to_unsigned(16#FF#,DW/2)), --
5 => OPC(setil) & reg(4) & std_logic_vector(to_unsigned(16#FF#,DW/2)), --
6 => OPC(setih) & reg(5) & std_logic_vector(to_unsigned(0,DW/2)), --
7 => OPC(setih) & reg(6) & std_logic_vector(to_unsigned(0,DW/2)), --
8 => OPC(setih) & reg(7) & std_logic_vector(to_unsigned(0,DW/2)), --
9 => OPC(setil) & reg(0) & std_logic_vector(to_unsigned(16#84#,DW/2)), --
10 => OPC(ld) & reg(1) & reg(0) & "---" & "--", --
11 => OPC(add) & reg(1) & reg(1) & reg(3) & "--", --
12 => OPC(bne) & "---" & std_logic_vector(to_signed(-3,DW/2)), --
13 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#86#,DW/2)), --
14 => OPC(setil) & reg(0) & std_logic_vector(to_unsigned(69,DW/2)), --
15 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
16 => OPC(add) & reg(6) & reg(5) & reg(3) & "--", --
17 => OPC(setil) & reg(0) & std_logic_vector(to_unsigned(16#80#,DW/2)), --
18 => OPC(ld) & reg(5) & reg(0) & "---" & "--", --
19 => OPC(add) & reg(0) & reg(3) & reg(4) & "--", --
20 => OPC(add) & reg(1) & reg(3) & reg(3) & "--", --
21 => OPC(setil) & reg(1) & std_logic_vector(to_unsigned(1,DW/2)), --
22 => OPC(andi) & reg(1) & reg(1) & reg(5) & "--", --
23 => OPC(bne) & "---" & std_logic_vector(to_signed(+2,DW/2)), --
24 => OPC(add) & reg(0) & reg(3) & reg(3) & "--", --
25 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#82#,DW/2)), --
26 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
27 => OPC(add) & reg(0) & reg(3) & reg(4) & "--", --
28 => OPC(add) & reg(1) & reg(3) & reg(3) & "--", --
29 => OPC(setil) & reg(1) & std_logic_vector(to_unsigned(2,DW/2)), --
30 => OPC(andi) & reg(1) & reg(1) & reg(5) & "--", --
31 => OPC(bne) & "---" & std_logic_vector(to_signed(+2,DW/2)), --
32 => OPC(add) & reg(0) & reg(3) & reg(3) & "--", --
33 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#83#,DW/2)), --
34 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
35 => OPC(xori) & reg(0) & reg(6) & reg(4) & "--", --
36 => OPC(andi) & reg(0) & reg(0) & reg(5) & "--", --
37 => OPC(add) & reg(1) & reg(3) & reg(3) & "--", --
38 => OPC(setil) & reg(1) & std_logic_vector(to_unsigned(16#10#,DW/2)), --
39 => OPC(andi) & reg(0) & reg(0) & reg(1) & "--", --
40 => OPC(xori) & reg(0) & reg(0) & reg(1) & "--", --
41 => OPC(bne) & "---" & std_logic_vector(to_signed(+6,DW/2)), --
42 => OPC(add) & reg(2) & reg(3) & reg(3) & "--", --
43 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#86#,DW/2)), --
44 => OPC(ld) & reg(0) & reg(2) & "---" & "--", --
45 => OPC(addil) & reg(0) & std_logic_vector(to_unsigned(1,DW/2)), --
46 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
47 => OPC(xori) & reg(0) & reg(6) & reg(4) & "--", --
48 => OPC(andi) & reg(0) & reg(0) & reg(5) & "--", --
49 => OPC(add) & reg(1) & reg(3) & reg(3) & "--", --
50 => OPC(setil) & reg(1) & std_logic_vector(to_unsigned(16#20#,DW/2)), --
51 => OPC(andi) & reg(0) & reg(0) & reg(1) & "--", --
52 => OPC(xori) & reg(0) & reg(0) & reg(1) & "--", --
53 => OPC(bne) & "---" & std_logic_vector(to_signed(+6,DW/2)), --
54 => OPC(add) & reg(2) & reg(3) & reg(3) & "--", --
55 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#86#,DW/2)), --
56 => OPC(ld) & reg(0) & reg(2) & "---" & "--", --
57 => OPC(addil) & reg(0) & std_logic_vector(to_signed(-1,DW/2)), --
58 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
59 => OPC(add) & reg(7) & reg(3) & reg(5) & "--", --
60 => OPC(setil) & reg(0) & std_logic_vector(to_unsigned(16#81#,DW/2)), --
61 => OPC(st) & reg(7) & reg(0) & "---" & "--", --
62 => OPC(jmp) & "---" & std_logic_vector(to_unsigned(16,DW/2)), --
63 => OPC(nop) & "---" & "---" & "---" & "--", --
others => (others => '1')
);
begin
-----------------------------------------------------------------------------
-- sequential process: ROM table with registerd output
-----------------------------------------------------------------------------
P_rom: process(clk)
begin
if rising_edge(clk) then
bus_out.data <= rom_table(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
gpl-2.0
|
26e14a06f391a1ee56830b6007f231ee
| 0.348766 | 3.182448 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/load_store_unit.vhd
| 3 | 1,320 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Load/Store Unit
-- Operations - Load/Store to a register
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Load_Store_Unit is
Port ( CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (7 downto 0);
IMMED : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Load_Store_Unit;
architecture Behavioral of Load_Store_Unit is
signal reg : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal w_en : std_logic := '0';-- '1' = write, '0' = read
begin
w_en <= '1' when OP="1010" else '0';
process(CLK)
begin
if (CLK'event and CLK='1') then
if (w_en = '1') then
reg <= A;
end if;
end if;
end process;
RESULT <= reg;
end Behavioral;
|
mit
|
c6cc869c0678e8d3ce22d24edeb97323
| 0.552273 | 3.65651 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/RF.vhd
| 1 | 1,160 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
DWR : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
WE : in STD_LOGIC;
Crs1 : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0');
Crs2 : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0');
Crd : out STD_LOGIC_VECTOR(31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (63 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type:=(others => "00000000000000000000000000000000");
--registro g0 siempre es cero
begin
process (rs1,rs2,rd,DWR,rst)
begin
if rst='0' then
if rd >"00000" and WE='1' then
RAM(conv_integer(rd)) <= DWR;
end if;
Crs1<=RAM(conv_integer(rs1));
Crs2<=RAM(conv_integer(rs2));
Crd<=RAM(conv_integer(rd));
else
RAM<=(others=>"00000000000000000000000000000000");
Crs1<=(others=>'0');
Crs2<=(others=>'0');
Crd<=(others=>'0');
end if;
end process;
end Behavioral;
|
mit
|
8bba7145d4ddfcf4ce787aad040daa0a
| 0.621552 | 3.068783 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/SEUdisp22_tb.vhd
| 1 | 917 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SEUdisp22_tb IS
END SEUdisp22_tb;
ARCHITECTURE behavior OF SEUdisp22_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SEUdisp22
PORT(
disp22 : IN std_logic_vector(21 downto 0);
SEUdisp22 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal disp22 : std_logic_vector(21 downto 0) := (others => '0');
--Outputs
signal SEUdisp22 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SEUdisp22 PORT MAP (
disp22 => disp22,
SEUdisp22 => SEUdisp22
);
-- Stimulus process
stim_proc: process
begin
disp22<="100000000000100000011";
wait for 20 ns;
disp22<="000000000000000001010";
wait;
wait;
end process;
END;
|
mit
|
11603735f3324d984b2c4304e52f4513
| 0.589967 | 4.02193 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_auto_us_1/system_auto_us_1_sim_netlist.vhdl
| 1 | 423,707 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:43:53 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_us_1/system_auto_us_1_sim_netlist.vhdl
-- Design : system_auto_us_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer is
port (
first_mi_word_q : out STD_LOGIC;
\M_AXI_RDATA_I_reg[0]_0\ : out STD_LOGIC;
first_word : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
use_wrap_buffer : out STD_LOGIC;
wrap_buffer_available : out STD_LOGIC;
\pre_next_word_1_reg[3]_0\ : out STD_LOGIC;
\current_word_1_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\pre_next_word_1_reg[3]_1\ : out STD_LOGIC;
wrap_buffer_available_reg_0 : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
first_word_reg_0 : out STD_LOGIC;
first_word_reg_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
first_word_reg_2 : out STD_LOGIC;
\USE_RTL_ADDR.addr_q_reg[4]\ : out STD_LOGIC;
\m_payload_i_reg[130]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 130 downto 0 );
\out\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_rready : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
rd_cmd_valid : in STD_LOGIC;
\current_word_1_reg[0]_0\ : in STD_LOGIC;
\current_word_1_reg[1]_0\ : in STD_LOGIC;
\m_payload_i_reg[0]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ : in STD_LOGIC;
\m_payload_i_reg[1]\ : in STD_LOGIC;
\m_payload_i_reg[2]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[5]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[7]\ : in STD_LOGIC;
\m_payload_i_reg[8]\ : in STD_LOGIC;
\m_payload_i_reg[9]\ : in STD_LOGIC;
\m_payload_i_reg[10]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC;
\m_payload_i_reg[12]\ : in STD_LOGIC;
\m_payload_i_reg[13]\ : in STD_LOGIC;
\m_payload_i_reg[14]\ : in STD_LOGIC;
\m_payload_i_reg[15]\ : in STD_LOGIC;
\m_payload_i_reg[16]\ : in STD_LOGIC;
\m_payload_i_reg[17]\ : in STD_LOGIC;
\m_payload_i_reg[18]\ : in STD_LOGIC;
\m_payload_i_reg[19]\ : in STD_LOGIC;
\m_payload_i_reg[20]\ : in STD_LOGIC;
\m_payload_i_reg[21]\ : in STD_LOGIC;
\m_payload_i_reg[22]\ : in STD_LOGIC;
\m_payload_i_reg[23]\ : in STD_LOGIC;
\m_payload_i_reg[24]\ : in STD_LOGIC;
\m_payload_i_reg[25]\ : in STD_LOGIC;
\m_payload_i_reg[26]\ : in STD_LOGIC;
\m_payload_i_reg[27]\ : in STD_LOGIC;
\m_payload_i_reg[28]\ : in STD_LOGIC;
\m_payload_i_reg[29]\ : in STD_LOGIC;
\m_payload_i_reg[30]\ : in STD_LOGIC;
\m_payload_i_reg[31]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
use_wrap_buffer_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer : entity is "axi_dwidth_converter_v2_1_11_r_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer is
signal \^m_axi_rdata_i_reg[0]_0\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[0]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[100]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[101]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[102]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[103]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[104]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[105]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[106]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[107]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[108]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[109]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[10]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[110]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[111]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[112]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[113]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[114]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[115]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[116]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[117]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[118]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[119]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[11]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[120]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[121]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[122]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[123]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[124]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[125]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[126]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[127]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[12]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[13]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[14]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[15]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[16]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[17]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[18]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[19]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[1]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[20]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[21]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[22]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[23]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[24]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[25]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[26]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[27]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[28]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[29]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[2]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[30]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[31]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[32]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[33]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[34]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[35]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[36]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[37]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[38]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[39]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[3]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[40]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[41]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[42]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[43]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[44]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[45]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[46]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[47]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[48]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[49]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[4]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[50]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[51]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[52]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[53]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[54]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[55]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[56]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[57]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[58]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[59]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[5]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[60]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[61]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[62]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[63]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[64]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[65]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[66]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[67]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[68]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[69]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[6]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[70]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[71]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[72]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[73]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[74]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[75]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[76]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[77]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[78]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[79]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[7]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[80]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[81]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[82]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[83]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[84]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[85]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[86]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[87]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[88]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[89]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[8]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[90]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[91]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[92]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[93]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[94]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[95]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[96]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[97]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[98]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[99]\ : STD_LOGIC;
signal \M_AXI_RDATA_I_reg_n_0_[9]\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_LENGTH.length_counter_q_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^current_word_1_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^first_mi_word_q\ : STD_LOGIC;
signal \^first_word\ : STD_LOGIC;
signal \^first_word_reg_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \m_payload_i[130]_i_7_n_0\ : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal rresp_wrap_buffer : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \s_axi_rdata[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[12]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[22]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[23]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[24]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[25]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[26]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[27]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[28]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[29]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[30]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[31]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC;
signal s_axi_rlast_INST_0_i_4_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_5_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_6_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_7_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_8_n_0 : STD_LOGIC;
signal s_axi_rlast_INST_0_i_9_n_0 : STD_LOGIC;
signal \^use_wrap_buffer\ : STD_LOGIC;
signal use_wrap_buffer_i_1_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_2_n_0 : STD_LOGIC;
signal use_wrap_buffer_i_3_n_0 : STD_LOGIC;
signal \^wrap_buffer_available\ : STD_LOGIC;
signal wrap_buffer_available_i_1_n_0 : STD_LOGIC;
signal wrap_buffer_available_i_2_n_0 : STD_LOGIC;
signal \^wrap_buffer_available_reg_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[4]_i_5\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[0]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[1]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[2]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[4]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \USE_RTL_LENGTH.length_counter_q[6]_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_7\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_4 : label is "soft_lutpair66";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_5 : label is "soft_lutpair67";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_6 : label is "soft_lutpair71";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_7 : label is "soft_lutpair68";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_8 : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of use_wrap_buffer_i_2 : label is "soft_lutpair70";
attribute SOFT_HLUTNM of use_wrap_buffer_i_3 : label is "soft_lutpair70";
attribute SOFT_HLUTNM of wrap_buffer_available_i_2 : label is "soft_lutpair72";
begin
\M_AXI_RDATA_I_reg[0]_0\ <= \^m_axi_rdata_i_reg[0]_0\;
\current_word_1_reg[3]_0\(3 downto 0) <= \^current_word_1_reg[3]_0\(3 downto 0);
first_mi_word_q <= \^first_mi_word_q\;
first_word <= \^first_word\;
first_word_reg_1(3 downto 0) <= \^first_word_reg_1\(3 downto 0);
s_axi_rlast <= \^s_axi_rlast\;
use_wrap_buffer <= \^use_wrap_buffer\;
wrap_buffer_available <= \^wrap_buffer_available\;
wrap_buffer_available_reg_0 <= \^wrap_buffer_available_reg_0\;
\M_AXI_RDATA_I_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(0),
Q => \M_AXI_RDATA_I_reg_n_0_[0]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(100),
Q => \M_AXI_RDATA_I_reg_n_0_[100]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(101),
Q => \M_AXI_RDATA_I_reg_n_0_[101]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(102),
Q => \M_AXI_RDATA_I_reg_n_0_[102]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(103),
Q => \M_AXI_RDATA_I_reg_n_0_[103]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(104),
Q => \M_AXI_RDATA_I_reg_n_0_[104]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(105),
Q => \M_AXI_RDATA_I_reg_n_0_[105]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(106),
Q => \M_AXI_RDATA_I_reg_n_0_[106]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(107),
Q => \M_AXI_RDATA_I_reg_n_0_[107]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(108),
Q => \M_AXI_RDATA_I_reg_n_0_[108]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(109),
Q => \M_AXI_RDATA_I_reg_n_0_[109]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(10),
Q => \M_AXI_RDATA_I_reg_n_0_[10]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(110),
Q => \M_AXI_RDATA_I_reg_n_0_[110]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(111),
Q => \M_AXI_RDATA_I_reg_n_0_[111]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(112),
Q => \M_AXI_RDATA_I_reg_n_0_[112]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(113),
Q => \M_AXI_RDATA_I_reg_n_0_[113]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(114),
Q => \M_AXI_RDATA_I_reg_n_0_[114]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(115),
Q => \M_AXI_RDATA_I_reg_n_0_[115]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(116),
Q => \M_AXI_RDATA_I_reg_n_0_[116]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(117),
Q => \M_AXI_RDATA_I_reg_n_0_[117]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(118),
Q => \M_AXI_RDATA_I_reg_n_0_[118]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(119),
Q => \M_AXI_RDATA_I_reg_n_0_[119]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(11),
Q => \M_AXI_RDATA_I_reg_n_0_[11]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(120),
Q => \M_AXI_RDATA_I_reg_n_0_[120]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(121),
Q => \M_AXI_RDATA_I_reg_n_0_[121]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(122),
Q => \M_AXI_RDATA_I_reg_n_0_[122]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(123),
Q => \M_AXI_RDATA_I_reg_n_0_[123]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(124),
Q => \M_AXI_RDATA_I_reg_n_0_[124]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(125),
Q => \M_AXI_RDATA_I_reg_n_0_[125]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(126),
Q => \M_AXI_RDATA_I_reg_n_0_[126]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(127),
Q => \M_AXI_RDATA_I_reg_n_0_[127]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(12),
Q => \M_AXI_RDATA_I_reg_n_0_[12]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(13),
Q => \M_AXI_RDATA_I_reg_n_0_[13]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(14),
Q => \M_AXI_RDATA_I_reg_n_0_[14]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(15),
Q => \M_AXI_RDATA_I_reg_n_0_[15]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(16),
Q => \M_AXI_RDATA_I_reg_n_0_[16]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(17),
Q => \M_AXI_RDATA_I_reg_n_0_[17]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(18),
Q => \M_AXI_RDATA_I_reg_n_0_[18]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(19),
Q => \M_AXI_RDATA_I_reg_n_0_[19]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(1),
Q => \M_AXI_RDATA_I_reg_n_0_[1]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(20),
Q => \M_AXI_RDATA_I_reg_n_0_[20]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(21),
Q => \M_AXI_RDATA_I_reg_n_0_[21]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(22),
Q => \M_AXI_RDATA_I_reg_n_0_[22]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(23),
Q => \M_AXI_RDATA_I_reg_n_0_[23]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(24),
Q => \M_AXI_RDATA_I_reg_n_0_[24]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(25),
Q => \M_AXI_RDATA_I_reg_n_0_[25]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(26),
Q => \M_AXI_RDATA_I_reg_n_0_[26]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(27),
Q => \M_AXI_RDATA_I_reg_n_0_[27]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(28),
Q => \M_AXI_RDATA_I_reg_n_0_[28]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(29),
Q => \M_AXI_RDATA_I_reg_n_0_[29]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(2),
Q => \M_AXI_RDATA_I_reg_n_0_[2]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(30),
Q => \M_AXI_RDATA_I_reg_n_0_[30]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(31),
Q => \M_AXI_RDATA_I_reg_n_0_[31]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(32),
Q => \M_AXI_RDATA_I_reg_n_0_[32]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(33),
Q => \M_AXI_RDATA_I_reg_n_0_[33]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(34),
Q => \M_AXI_RDATA_I_reg_n_0_[34]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(35),
Q => \M_AXI_RDATA_I_reg_n_0_[35]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(36),
Q => \M_AXI_RDATA_I_reg_n_0_[36]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(37),
Q => \M_AXI_RDATA_I_reg_n_0_[37]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(38),
Q => \M_AXI_RDATA_I_reg_n_0_[38]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(39),
Q => \M_AXI_RDATA_I_reg_n_0_[39]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(3),
Q => \M_AXI_RDATA_I_reg_n_0_[3]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(40),
Q => \M_AXI_RDATA_I_reg_n_0_[40]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(41),
Q => \M_AXI_RDATA_I_reg_n_0_[41]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(42),
Q => \M_AXI_RDATA_I_reg_n_0_[42]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(43),
Q => \M_AXI_RDATA_I_reg_n_0_[43]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(44),
Q => \M_AXI_RDATA_I_reg_n_0_[44]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(45),
Q => \M_AXI_RDATA_I_reg_n_0_[45]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(46),
Q => \M_AXI_RDATA_I_reg_n_0_[46]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(47),
Q => \M_AXI_RDATA_I_reg_n_0_[47]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(48),
Q => \M_AXI_RDATA_I_reg_n_0_[48]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(49),
Q => \M_AXI_RDATA_I_reg_n_0_[49]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(4),
Q => \M_AXI_RDATA_I_reg_n_0_[4]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(50),
Q => \M_AXI_RDATA_I_reg_n_0_[50]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(51),
Q => \M_AXI_RDATA_I_reg_n_0_[51]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(52),
Q => \M_AXI_RDATA_I_reg_n_0_[52]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(53),
Q => \M_AXI_RDATA_I_reg_n_0_[53]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(54),
Q => \M_AXI_RDATA_I_reg_n_0_[54]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(55),
Q => \M_AXI_RDATA_I_reg_n_0_[55]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(56),
Q => \M_AXI_RDATA_I_reg_n_0_[56]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(57),
Q => \M_AXI_RDATA_I_reg_n_0_[57]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(58),
Q => \M_AXI_RDATA_I_reg_n_0_[58]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(59),
Q => \M_AXI_RDATA_I_reg_n_0_[59]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(5),
Q => \M_AXI_RDATA_I_reg_n_0_[5]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(60),
Q => \M_AXI_RDATA_I_reg_n_0_[60]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(61),
Q => \M_AXI_RDATA_I_reg_n_0_[61]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(62),
Q => \M_AXI_RDATA_I_reg_n_0_[62]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(63),
Q => \M_AXI_RDATA_I_reg_n_0_[63]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(64),
Q => \M_AXI_RDATA_I_reg_n_0_[64]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(65),
Q => \M_AXI_RDATA_I_reg_n_0_[65]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(66),
Q => \M_AXI_RDATA_I_reg_n_0_[66]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(67),
Q => \M_AXI_RDATA_I_reg_n_0_[67]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(68),
Q => \M_AXI_RDATA_I_reg_n_0_[68]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(69),
Q => \M_AXI_RDATA_I_reg_n_0_[69]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(6),
Q => \M_AXI_RDATA_I_reg_n_0_[6]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(70),
Q => \M_AXI_RDATA_I_reg_n_0_[70]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(71),
Q => \M_AXI_RDATA_I_reg_n_0_[71]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(72),
Q => \M_AXI_RDATA_I_reg_n_0_[72]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(73),
Q => \M_AXI_RDATA_I_reg_n_0_[73]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(74),
Q => \M_AXI_RDATA_I_reg_n_0_[74]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(75),
Q => \M_AXI_RDATA_I_reg_n_0_[75]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(76),
Q => \M_AXI_RDATA_I_reg_n_0_[76]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(77),
Q => \M_AXI_RDATA_I_reg_n_0_[77]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(78),
Q => \M_AXI_RDATA_I_reg_n_0_[78]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(79),
Q => \M_AXI_RDATA_I_reg_n_0_[79]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(7),
Q => \M_AXI_RDATA_I_reg_n_0_[7]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(80),
Q => \M_AXI_RDATA_I_reg_n_0_[80]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(81),
Q => \M_AXI_RDATA_I_reg_n_0_[81]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(82),
Q => \M_AXI_RDATA_I_reg_n_0_[82]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(83),
Q => \M_AXI_RDATA_I_reg_n_0_[83]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(84),
Q => \M_AXI_RDATA_I_reg_n_0_[84]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(85),
Q => \M_AXI_RDATA_I_reg_n_0_[85]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(86),
Q => \M_AXI_RDATA_I_reg_n_0_[86]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(87),
Q => \M_AXI_RDATA_I_reg_n_0_[87]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(88),
Q => \M_AXI_RDATA_I_reg_n_0_[88]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(89),
Q => \M_AXI_RDATA_I_reg_n_0_[89]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(8),
Q => \M_AXI_RDATA_I_reg_n_0_[8]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(90),
Q => \M_AXI_RDATA_I_reg_n_0_[90]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(91),
Q => \M_AXI_RDATA_I_reg_n_0_[91]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(92),
Q => \M_AXI_RDATA_I_reg_n_0_[92]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(93),
Q => \M_AXI_RDATA_I_reg_n_0_[93]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(94),
Q => \M_AXI_RDATA_I_reg_n_0_[94]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(95),
Q => \M_AXI_RDATA_I_reg_n_0_[95]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(96),
Q => \M_AXI_RDATA_I_reg_n_0_[96]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(97),
Q => \M_AXI_RDATA_I_reg_n_0_[97]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(98),
Q => \M_AXI_RDATA_I_reg_n_0_[98]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(99),
Q => \M_AXI_RDATA_I_reg_n_0_[99]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\M_AXI_RDATA_I_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(9),
Q => \M_AXI_RDATA_I_reg_n_0_[9]\,
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_ADDR.addr_q[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAAE"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => s_axi_rlast_INST_0_i_4_n_0,
I2 => \m_payload_i[130]_i_7_n_0\,
I3 => \USE_RTL_ADDR.addr_q[4]_i_5_n_0\,
I4 => s_axi_rlast_INST_0_i_9_n_0,
I5 => \^wrap_buffer_available\,
O => \USE_RTL_ADDR.addr_q_reg[4]\
);
\USE_RTL_ADDR.addr_q[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
O => \USE_RTL_ADDR.addr_q[4]_i_5_n_0\
);
\USE_RTL_LENGTH.first_mi_word_q_reg\: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => m_valid_i_reg,
D => Q(130),
Q => \^first_mi_word_q\,
S => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I1 => \^first_mi_word_q\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(0),
O => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA533A5"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(0),
O => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"56A6"
)
port map (
I0 => s_axi_rlast_INST_0_i_4_n_0,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I2 => \^first_mi_word_q\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
O => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I5 => s_axi_rlast_INST_0_i_4_n_0,
O => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B847"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I3 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCAACCAAC3AAC355"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I5 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBBFCB8FFFFFFFF"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3),
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I5 => s_axi_rlast_INST_0_i_4_n_0,
O => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(6),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I5 => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0151"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \^first_mi_word_q\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
O => \USE_RTL_LENGTH.length_counter_q[6]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C3AAC355CCAACCAA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(7),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(6),
I3 => \^first_mi_word_q\,
I4 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I5 => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\,
O => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\
);
\USE_RTL_LENGTH.length_counter_q[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000305050003"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
I1 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
I2 => \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0\,
I3 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
I4 => \^first_mi_word_q\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
O => \USE_RTL_LENGTH.length_counter_q[7]_i_2_n_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(0),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(1),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(2),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(3),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(4),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(5),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(6),
R => \^m_axi_rdata_i_reg[0]_0\
);
\USE_RTL_LENGTH.length_counter_q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => m_valid_i_reg,
D => \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0\,
Q => \USE_RTL_LENGTH.length_counter_q_reg\(7),
R => \^m_axi_rdata_i_reg[0]_0\
);
\current_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(0),
Q => \^first_word_reg_1\(0),
R => \^m_axi_rdata_i_reg[0]_0\
);
\current_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(1),
Q => \^first_word_reg_1\(1),
R => \^m_axi_rdata_i_reg[0]_0\
);
\current_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(2),
Q => \^first_word_reg_1\(2),
R => \^m_axi_rdata_i_reg[0]_0\
);
\current_word_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(3),
Q => \^first_word_reg_1\(3),
R => \^m_axi_rdata_i_reg[0]_0\
);
first_word_reg: unisim.vcomponents.FDSE
port map (
C => \out\,
CE => p_15_in,
D => \^s_axi_rlast\,
Q => \^first_word\,
S => \^m_axi_rdata_i_reg[0]_0\
);
\m_payload_i[130]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => s_axi_rlast_INST_0_i_9_n_0,
I2 => s_axi_rlast_INST_0_i_8_n_0,
I3 => s_axi_rlast_INST_0_i_7_n_0,
I4 => \m_payload_i[130]_i_7_n_0\,
I5 => s_axi_rlast_INST_0_i_4_n_0,
O => \m_payload_i_reg[130]\
);
\m_payload_i[130]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
O => \m_payload_i[130]_i_7_n_0\
);
\pre_next_word_1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A888"
)
port map (
I0 => s_axi_rready,
I1 => \^use_wrap_buffer\,
I2 => mr_rvalid,
I3 => rd_cmd_valid,
O => p_15_in
);
\pre_next_word_1[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => \^current_word_1_reg[3]_0\(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(8),
O => \pre_next_word_1_reg[3]_1\
);
\pre_next_word_1[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^current_word_1_reg[3]_0\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(9),
O => \pre_next_word_1_reg[3]_0\
);
\pre_next_word_1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(0),
Q => \^current_word_1_reg[3]_0\(0),
R => \^m_axi_rdata_i_reg[0]_0\
);
\pre_next_word_1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(1),
Q => \^current_word_1_reg[3]_0\(1),
R => \^m_axi_rdata_i_reg[0]_0\
);
\pre_next_word_1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(2),
Q => \^current_word_1_reg[3]_0\(2),
R => \^m_axi_rdata_i_reg[0]_0\
);
\pre_next_word_1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => p_15_in,
D => D(3),
Q => \^current_word_1_reg[3]_0\(3),
R => \^m_axi_rdata_i_reg[0]_0\
);
\rresp_wrap_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(128),
Q => rresp_wrap_buffer(0),
R => \^m_axi_rdata_i_reg[0]_0\
);
\rresp_wrap_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => Q(129),
Q => rresp_wrap_buffer(1),
R => \^m_axi_rdata_i_reg[0]_0\
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[0]\,
I1 => \s_axi_rdata[0]_INST_0_i_2_n_0\,
O => s_axi_rdata(0),
S => \^use_wrap_buffer\
);
\s_axi_rdata[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[0]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[64]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[32]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[96]\,
O => \s_axi_rdata[0]_INST_0_i_2_n_0\
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[10]\,
I1 => \s_axi_rdata[10]_INST_0_i_2_n_0\,
O => s_axi_rdata(10),
S => \^use_wrap_buffer\
);
\s_axi_rdata[10]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[10]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[74]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[42]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[106]\,
O => \s_axi_rdata[10]_INST_0_i_2_n_0\
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[11]\,
I1 => \s_axi_rdata[11]_INST_0_i_2_n_0\,
O => s_axi_rdata(11),
S => \^use_wrap_buffer\
);
\s_axi_rdata[11]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[11]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[75]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[43]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[107]\,
O => \s_axi_rdata[11]_INST_0_i_2_n_0\
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[12]\,
I1 => \s_axi_rdata[12]_INST_0_i_2_n_0\,
O => s_axi_rdata(12),
S => \^use_wrap_buffer\
);
\s_axi_rdata[12]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[12]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[76]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[44]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[108]\,
O => \s_axi_rdata[12]_INST_0_i_2_n_0\
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[13]\,
I1 => \s_axi_rdata[13]_INST_0_i_2_n_0\,
O => s_axi_rdata(13),
S => \^use_wrap_buffer\
);
\s_axi_rdata[13]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[13]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[77]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[45]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[109]\,
O => \s_axi_rdata[13]_INST_0_i_2_n_0\
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[14]\,
I1 => \s_axi_rdata[14]_INST_0_i_2_n_0\,
O => s_axi_rdata(14),
S => \^use_wrap_buffer\
);
\s_axi_rdata[14]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[14]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[78]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[46]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[110]\,
O => \s_axi_rdata[14]_INST_0_i_2_n_0\
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[15]\,
I1 => \s_axi_rdata[15]_INST_0_i_2_n_0\,
O => s_axi_rdata(15),
S => \^use_wrap_buffer\
);
\s_axi_rdata[15]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[15]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[79]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[47]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[111]\,
O => \s_axi_rdata[15]_INST_0_i_2_n_0\
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[16]\,
I1 => \s_axi_rdata[16]_INST_0_i_2_n_0\,
O => s_axi_rdata(16),
S => \^use_wrap_buffer\
);
\s_axi_rdata[16]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[16]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[80]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[48]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[112]\,
O => \s_axi_rdata[16]_INST_0_i_2_n_0\
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[17]\,
I1 => \s_axi_rdata[17]_INST_0_i_2_n_0\,
O => s_axi_rdata(17),
S => \^use_wrap_buffer\
);
\s_axi_rdata[17]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[17]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[81]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[49]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[113]\,
O => \s_axi_rdata[17]_INST_0_i_2_n_0\
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[18]\,
I1 => \s_axi_rdata[18]_INST_0_i_2_n_0\,
O => s_axi_rdata(18),
S => \^use_wrap_buffer\
);
\s_axi_rdata[18]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[18]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[82]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[50]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[114]\,
O => \s_axi_rdata[18]_INST_0_i_2_n_0\
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[19]\,
I1 => \s_axi_rdata[19]_INST_0_i_2_n_0\,
O => s_axi_rdata(19),
S => \^use_wrap_buffer\
);
\s_axi_rdata[19]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[19]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[83]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[51]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[115]\,
O => \s_axi_rdata[19]_INST_0_i_2_n_0\
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[1]\,
I1 => \s_axi_rdata[1]_INST_0_i_2_n_0\,
O => s_axi_rdata(1),
S => \^use_wrap_buffer\
);
\s_axi_rdata[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[1]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[65]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[33]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[97]\,
O => \s_axi_rdata[1]_INST_0_i_2_n_0\
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[20]\,
I1 => \s_axi_rdata[20]_INST_0_i_2_n_0\,
O => s_axi_rdata(20),
S => \^use_wrap_buffer\
);
\s_axi_rdata[20]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[20]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[84]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[52]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[116]\,
O => \s_axi_rdata[20]_INST_0_i_2_n_0\
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[21]\,
I1 => \s_axi_rdata[21]_INST_0_i_2_n_0\,
O => s_axi_rdata(21),
S => \^use_wrap_buffer\
);
\s_axi_rdata[21]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[21]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[85]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[53]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[117]\,
O => \s_axi_rdata[21]_INST_0_i_2_n_0\
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[22]\,
I1 => \s_axi_rdata[22]_INST_0_i_2_n_0\,
O => s_axi_rdata(22),
S => \^use_wrap_buffer\
);
\s_axi_rdata[22]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[22]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[86]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[54]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[118]\,
O => \s_axi_rdata[22]_INST_0_i_2_n_0\
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[23]\,
I1 => \s_axi_rdata[23]_INST_0_i_2_n_0\,
O => s_axi_rdata(23),
S => \^use_wrap_buffer\
);
\s_axi_rdata[23]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[23]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[87]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[55]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[119]\,
O => \s_axi_rdata[23]_INST_0_i_2_n_0\
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[24]\,
I1 => \s_axi_rdata[24]_INST_0_i_2_n_0\,
O => s_axi_rdata(24),
S => \^use_wrap_buffer\
);
\s_axi_rdata[24]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[24]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[88]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[56]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[120]\,
O => \s_axi_rdata[24]_INST_0_i_2_n_0\
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[25]\,
I1 => \s_axi_rdata[25]_INST_0_i_2_n_0\,
O => s_axi_rdata(25),
S => \^use_wrap_buffer\
);
\s_axi_rdata[25]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[25]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[89]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[57]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[121]\,
O => \s_axi_rdata[25]_INST_0_i_2_n_0\
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[26]\,
I1 => \s_axi_rdata[26]_INST_0_i_2_n_0\,
O => s_axi_rdata(26),
S => \^use_wrap_buffer\
);
\s_axi_rdata[26]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[26]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[90]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[58]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[122]\,
O => \s_axi_rdata[26]_INST_0_i_2_n_0\
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[27]\,
I1 => \s_axi_rdata[27]_INST_0_i_2_n_0\,
O => s_axi_rdata(27),
S => \^use_wrap_buffer\
);
\s_axi_rdata[27]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[27]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[91]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[59]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[123]\,
O => \s_axi_rdata[27]_INST_0_i_2_n_0\
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[28]\,
I1 => \s_axi_rdata[28]_INST_0_i_2_n_0\,
O => s_axi_rdata(28),
S => \^use_wrap_buffer\
);
\s_axi_rdata[28]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[28]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[92]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[60]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[124]\,
O => \s_axi_rdata[28]_INST_0_i_2_n_0\
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[29]\,
I1 => \s_axi_rdata[29]_INST_0_i_2_n_0\,
O => s_axi_rdata(29),
S => \^use_wrap_buffer\
);
\s_axi_rdata[29]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[29]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[93]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[61]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[125]\,
O => \s_axi_rdata[29]_INST_0_i_2_n_0\
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[2]\,
I1 => \s_axi_rdata[2]_INST_0_i_2_n_0\,
O => s_axi_rdata(2),
S => \^use_wrap_buffer\
);
\s_axi_rdata[2]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[2]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[66]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[34]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[98]\,
O => \s_axi_rdata[2]_INST_0_i_2_n_0\
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[30]\,
I1 => \s_axi_rdata[30]_INST_0_i_2_n_0\,
O => s_axi_rdata(30),
S => \^use_wrap_buffer\
);
\s_axi_rdata[30]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[30]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[94]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[62]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[126]\,
O => \s_axi_rdata[30]_INST_0_i_2_n_0\
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[31]\,
I1 => \s_axi_rdata[31]_INST_0_i_2_n_0\,
O => s_axi_rdata(31),
S => \^use_wrap_buffer\
);
\s_axi_rdata[31]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[31]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[95]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[63]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[127]\,
O => \s_axi_rdata[31]_INST_0_i_2_n_0\
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[3]\,
I1 => \s_axi_rdata[3]_INST_0_i_2_n_0\,
O => s_axi_rdata(3),
S => \^use_wrap_buffer\
);
\s_axi_rdata[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[3]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[67]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[35]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[99]\,
O => \s_axi_rdata[3]_INST_0_i_2_n_0\
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[4]\,
I1 => \s_axi_rdata[4]_INST_0_i_2_n_0\,
O => s_axi_rdata(4),
S => \^use_wrap_buffer\
);
\s_axi_rdata[4]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[4]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[68]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[36]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[100]\,
O => \s_axi_rdata[4]_INST_0_i_2_n_0\
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[5]\,
I1 => \s_axi_rdata[5]_INST_0_i_2_n_0\,
O => s_axi_rdata(5),
S => \^use_wrap_buffer\
);
\s_axi_rdata[5]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[5]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[69]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[37]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[101]\,
O => \s_axi_rdata[5]_INST_0_i_2_n_0\
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[6]\,
I1 => \s_axi_rdata[6]_INST_0_i_2_n_0\,
O => s_axi_rdata(6),
S => \^use_wrap_buffer\
);
\s_axi_rdata[6]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[6]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[70]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[38]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[102]\,
O => \s_axi_rdata[6]_INST_0_i_2_n_0\
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[7]\,
I1 => \s_axi_rdata[7]_INST_0_i_2_n_0\,
O => s_axi_rdata(7),
S => \^use_wrap_buffer\
);
\s_axi_rdata[7]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[7]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[71]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[39]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[103]\,
O => \s_axi_rdata[7]_INST_0_i_2_n_0\
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[8]\,
I1 => \s_axi_rdata[8]_INST_0_i_2_n_0\,
O => s_axi_rdata(8),
S => \^use_wrap_buffer\
);
\s_axi_rdata[8]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[8]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[72]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[40]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[104]\,
O => \s_axi_rdata[8]_INST_0_i_2_n_0\
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \m_payload_i_reg[9]\,
I1 => \s_axi_rdata[9]_INST_0_i_2_n_0\,
O => s_axi_rdata(9),
S => \^use_wrap_buffer\
);
\s_axi_rdata[9]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \M_AXI_RDATA_I_reg_n_0_[9]\,
I1 => \M_AXI_RDATA_I_reg_n_0_[73]\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \M_AXI_RDATA_I_reg_n_0_[41]\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \M_AXI_RDATA_I_reg_n_0_[105]\,
O => \s_axi_rdata[9]_INST_0_i_2_n_0\
);
s_axi_rlast_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F1"
)
port map (
I0 => \^wrap_buffer_available\,
I1 => \^wrap_buffer_available_reg_0\,
I2 => \^use_wrap_buffer\,
I3 => \current_word_1_reg[0]_0\,
I4 => \current_word_1_reg[1]_0\,
O => \^s_axi_rlast\
);
s_axi_rlast_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => s_axi_rlast_INST_0_i_4_n_0,
I1 => s_axi_rlast_INST_0_i_5_n_0,
I2 => s_axi_rlast_INST_0_i_6_n_0,
I3 => s_axi_rlast_INST_0_i_7_n_0,
I4 => s_axi_rlast_INST_0_i_8_n_0,
I5 => s_axi_rlast_INST_0_i_9_n_0,
O => \^wrap_buffer_available_reg_0\
);
s_axi_rlast_INST_0_i_11: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^first_word_reg_1\(2),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(10),
O => first_word_reg_2
);
s_axi_rlast_INST_0_i_12: unisim.vcomponents.LUT4
generic map(
INIT => X"01FD"
)
port map (
I0 => \^first_word_reg_1\(3),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12),
I2 => \^first_word\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(11),
O => first_word_reg_0
);
s_axi_rlast_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(1),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(0),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(0),
O => s_axi_rlast_INST_0_i_4_n_0
);
s_axi_rlast_INST_0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(3),
O => s_axi_rlast_INST_0_i_5_n_0
);
s_axi_rlast_INST_0_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(2),
O => s_axi_rlast_INST_0_i_6_n_0
);
s_axi_rlast_INST_0_i_7: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(5),
O => s_axi_rlast_INST_0_i_7_n_0
);
s_axi_rlast_INST_0_i_8: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4),
I1 => \^first_mi_word_q\,
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(4),
O => s_axi_rlast_INST_0_i_8_n_0
);
s_axi_rlast_INST_0_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => \USE_RTL_LENGTH.length_counter_q_reg\(7),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(7),
I2 => \USE_RTL_LENGTH.length_counter_q_reg\(6),
I3 => \^first_mi_word_q\,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(6),
O => s_axi_rlast_INST_0_i_9_n_0
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(0),
I1 => \^use_wrap_buffer\,
I2 => Q(128),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => rresp_wrap_buffer(1),
I1 => \^use_wrap_buffer\,
I2 => Q(129),
O => s_axi_rresp(1)
);
use_wrap_buffer_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BBFBBBBB00F00000"
)
port map (
I0 => use_wrap_buffer_i_2_n_0,
I1 => \^s_axi_rlast\,
I2 => use_wrap_buffer_reg_0,
I3 => use_wrap_buffer_i_3_n_0,
I4 => \^wrap_buffer_available\,
I5 => \^use_wrap_buffer\,
O => use_wrap_buffer_i_1_n_0
);
use_wrap_buffer_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"57FF"
)
port map (
I0 => s_axi_rready,
I1 => \^use_wrap_buffer\,
I2 => mr_rvalid,
I3 => rd_cmd_valid,
O => use_wrap_buffer_i_2_n_0
);
use_wrap_buffer_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"AABF"
)
port map (
I0 => \^wrap_buffer_available_reg_0\,
I1 => rd_cmd_valid,
I2 => mr_rvalid,
I3 => \^use_wrap_buffer\,
O => use_wrap_buffer_i_3_n_0
);
use_wrap_buffer_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => use_wrap_buffer_i_1_n_0,
Q => \^use_wrap_buffer\,
R => \^m_axi_rdata_i_reg[0]_0\
);
wrap_buffer_available_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFAA00"
)
port map (
I0 => E(0),
I1 => \^wrap_buffer_available_reg_0\,
I2 => wrap_buffer_available_i_2_n_0,
I3 => use_wrap_buffer_reg_0,
I4 => \^wrap_buffer_available\,
O => wrap_buffer_available_i_1_n_0
);
wrap_buffer_available_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => \^use_wrap_buffer\,
I1 => mr_rvalid,
I2 => rd_cmd_valid,
O => wrap_buffer_available_i_2_n_0
);
wrap_buffer_available_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => wrap_buffer_available_i_1_n_0,
Q => \^wrap_buffer_available\,
R => \^m_axi_rdata_i_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice is
port (
\aresetn_d_reg[1]_0\ : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 43 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 1 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[50]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 43 downto 0 );
signal \USE_READ.read_addr_inst/mi_word_intra_len__10\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\ : STD_LOGIC;
signal \^aresetn_d_reg[1]_0\ : STD_LOGIC;
signal \^in\ : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \m_axi_araddr[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_araddr[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \m_axi_arlen[1]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \m_axi_arlen[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \m_axi_arlen[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \m_axi_arlen[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arlen[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_axi_arsize[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arsize[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \m_axi_arsize[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1_n_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_arlen_ii : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal sr_araddr : STD_LOGIC_VECTOR ( 3 downto 0 );
signal sr_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sr_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr_arvalid\ : STD_LOGIC;
signal upsized_length : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_axi_araddr[0]_INST_0_i_1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_axi_araddr[3]_INST_0_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_axi_arburst[0]_INST_0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_axi_arburst[1]_INST_0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_4\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_axi_arlen[0]_INST_0_i_7\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_7\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_axi_arlen[1]_INST_0_i_8\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_axi_arlen[2]_INST_0_i_2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_4\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_axi_arlen[3]_INST_0_i_5\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_arlen[4]_INST_0_i_4\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_arlen[5]_INST_0_i_2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_axi_arlen[6]_INST_0_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_axi_arlen[6]_INST_0_i_3\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_axi_arlen[7]_INST_0\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_axi_arsize[0]_INST_0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_axi_arsize[1]_INST_0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_axi_arsize[1]_INST_0_i_2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_axi_arsize[2]_INST_0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_axi_arsize[2]_INST_0_i_2\ : label is "soft_lutpair99";
begin
Q(43 downto 0) <= \^q\(43 downto 0);
\aresetn_d_reg[1]_0\ <= \^aresetn_d_reg[1]_0\;
\in\(32 downto 0) <= \^in\(32 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
sr_arvalid <= \^sr_arvalid\;
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFDFFFDF"
)
port map (
I0 => CO(0),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
O => \^in\(11)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF11011000"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
O => \^in\(12)
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
O => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\,
I1 => CO(0),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
O => \^in\(13)
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000FAC000000AC"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(2),
I2 => sr_arsize(0),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
I5 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFBFBBBBBB"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\,
I1 => CO(0),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\,
O => \^in\(14)
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000CA"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(2),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
I3 => sr_araddr(2),
I4 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
O => \^in\(15)
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
I3 => sr_araddr(3),
I4 => \m_axi_araddr[3]_INST_0_i_1_n_0\,
O => \^in\(16)
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1101115544444400"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => CO(0),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => sr_araddr(0),
O => \^in\(17)
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4888884848884888"
)
port map (
I0 => sr_araddr(1),
I1 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\,
I5 => sr_araddr(0),
O => \^in\(18)
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF11011111"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arburst(1),
I3 => sr_arburst(0),
I4 => CO(0),
I5 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000CA"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA55155555AA2AA"
)
port map (
I0 => sr_araddr(2),
I1 => CO(0),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
I4 => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_2_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\,
O => \^in\(19)
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBAAAAAAAAAAAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\,
I1 => CO(0),
I2 => sr_arburst(1),
I3 => sr_arburst(0),
I4 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0E02020200000000"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I1 => sr_arsize(0),
I2 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I3 => s_axi_arlen_ii(0),
I4 => sr_araddr(1),
I5 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => sr_araddr(1),
I1 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000D0000FFF20000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_5_n_0\,
I2 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\,
I3 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\,
I4 => \^in\(14),
I5 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\,
O => \^in\(20)
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000800080808000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => sr_araddr(0),
I2 => sr_araddr(1),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => CO(0),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0000080800000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_5_n_0\,
I1 => s_axi_arlen_ii(1),
I2 => \^in\(9),
I3 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
I5 => sr_araddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_3_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAEAEEEAAAAAAAAA"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\,
I2 => sr_arburst(0),
I3 => sr_arburst(1),
I4 => CO(0),
I5 => sr_araddr(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_4_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555575AAAAAA8A"
)
port map (
I0 => sr_araddr(3),
I1 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_2_n_0\,
I2 => CO(0),
I3 => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\,
I5 => \USE_READ.read_addr_inst/mi_word_intra_len__10\(3),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_5_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00230020"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(2),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_6_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"54000000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => sr_arburst(1),
I2 => sr_arburst(0),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_7_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"3330303030200000"
)
port map (
I0 => sr_arsize(0),
I1 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I2 => sr_araddr(1),
I3 => sr_araddr(0),
I4 => s_axi_arlen_ii(0),
I5 => s_axi_arlen_ii(1),
O => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_8_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000010000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_3_n_0\,
I5 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\,
O => \USE_READ.read_addr_inst/mi_word_intra_len__10\(3)
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFDF"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
I3 => s_axi_arlen_ii(0),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I5 => sr_araddr(0),
O => \^in\(21)
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA02000000A8"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_2_n_0\,
I1 => sr_araddr(0),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
I5 => sr_araddr(1),
O => \^in\(22)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"802A2A80"
)
port map (
I0 => \^in\(13),
I1 => sr_araddr(1),
I2 => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0\,
I3 => \^in\(10),
I4 => sr_araddr(2),
O => \^in\(23)
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0302"
)
port map (
I0 => sr_araddr(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => sr_arsize(0),
O => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4844444484888888"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\,
I1 => \^in\(14),
I2 => sr_arsize(2),
I3 => sr_arsize(1),
I4 => sr_arsize(0),
I5 => sr_araddr(3),
O => \^in\(24)
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000F000C00080"
)
port map (
I0 => sr_araddr(0),
I1 => sr_araddr(1),
I2 => sr_araddr(2),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
I5 => sr_arsize(1),
O => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545555500000000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => CO(0),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => sr_araddr(0),
O => \^in\(25)
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00CA00000000"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(0),
I3 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I4 => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0\,
I5 => sr_araddr(1),
O => \^in\(26)
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^in\(13),
I1 => sr_araddr(2),
O => \^in\(27)
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_i_3_n_0\,
I1 => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0\,
I2 => CO(0),
I3 => sr_arburst(0),
I4 => sr_arburst(1),
I5 => sr_araddr(3),
O => \^in\(28)
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44400040"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => s_axi_arlen_ii(1),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(0),
O => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\,
I1 => \^q\(32),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => sr_arburst(1),
I4 => sr_arburst(0),
I5 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
O => \^in\(29)
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => sr_araddr(3),
I1 => sr_araddr(2),
I2 => sr_araddr(1),
I3 => sr_araddr(0),
O => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_i_2_n_0\
);
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => CO(0),
I3 => \^q\(32),
I4 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
O => \^in\(30)
);
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I1 => \^q\(32),
I2 => sr_arburst(0),
I3 => sr_arburst(1),
O => \^in\(31)
);
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
O => \^in\(32)
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
O => \^in\(8)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => '1',
Q => \^aresetn_d_reg[1]_0\,
R => s_axi_aresetn
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \^aresetn_d_reg[1]_0\,
Q => \^s_ready_i_reg_0\,
R => s_axi_aresetn
);
cmd_packed_wrap_i1_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3)
);
cmd_packed_wrap_i1_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(2)
);
cmd_packed_wrap_i1_carry_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FAFAFA88"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arsize(0),
I2 => s_axi_arlen_ii(2),
I3 => sr_arsize(1),
I4 => sr_arsize(2),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(1)
);
cmd_packed_wrap_i1_carry_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"EAEAEA00"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
I3 => s_axi_arlen_ii(1),
I4 => s_axi_arlen_ii(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0)
);
cmd_packed_wrap_i1_carry_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(7),
I1 => s_axi_arlen_ii(6),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3)
);
cmd_packed_wrap_i1_carry_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(4),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(2)
);
cmd_packed_wrap_i1_carry_i_7: unisim.vcomponents.LUT5
generic map(
INIT => X"010010EE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(1)
);
cmd_packed_wrap_i1_carry_i_8: unisim.vcomponents.LUT5
generic map(
INIT => X"11181188"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0)
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00B000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(0),
I2 => CO(0),
I3 => sr_araddr(0),
I4 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(0)
);
\m_axi_araddr[0]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
O => \m_axi_araddr[0]_INST_0_i_1_n_0\
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000EF000000"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I3 => CO(0),
I4 => sr_araddr(1),
I5 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(1)
);
\m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_arsize(0),
I2 => s_axi_arlen_ii(1),
O => \m_axi_araddr[1]_INST_0_i_1_n_0\
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F080"
)
port map (
I0 => \m_axi_araddr[2]_INST_0_i_1_n_0\,
I1 => CO(0),
I2 => sr_araddr(2),
I3 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(2)
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF530FFFFF53F"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => s_axi_arlen_ii(2),
O => \m_axi_araddr[2]_INST_0_i_1_n_0\
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F080"
)
port map (
I0 => \m_axi_araddr[3]_INST_0_i_1_n_0\,
I1 => CO(0),
I2 => sr_araddr(3),
I3 => \m_axi_araddr[3]_INST_0_i_2_n_0\,
O => m_axi_araddr(3)
);
\m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F3F3F3F5F5F0FF"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_araddr[1]_INST_0_i_1_n_0\,
I2 => sr_arsize(2),
I3 => s_axi_arlen_ii(3),
I4 => sr_arsize(0),
I5 => sr_arsize(1),
O => \m_axi_araddr[3]_INST_0_i_1_n_0\
);
\m_axi_araddr[3]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFBBBF"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_payload_i_reg[50]_0\(0),
I3 => CO(0),
I4 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
O => \m_axi_araddr[3]_INST_0_i_2_n_0\
);
\m_axi_arburst[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF8000"
)
port map (
I0 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I1 => \^q\(32),
I2 => sr_arburst(1),
I3 => CO(0),
I4 => sr_arburst(0),
O => m_axi_arburst(0)
);
\m_axi_arburst[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F0B0"
)
port map (
I0 => sr_arburst(0),
I1 => CO(0),
I2 => sr_arburst(1),
I3 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
O => m_axi_arburst(1)
);
\m_axi_arlen[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555566665666"
)
port map (
I0 => upsized_length(0),
I1 => \m_axi_arlen[0]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[0]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I5 => \m_axi_arlen[0]_INST_0_i_5_n_0\,
O => \^in\(0)
);
\m_axi_arlen[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABBAAABAABAAAAA"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_6_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => sr_arsize(0),
I3 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I4 => s_axi_arlen_ii(3),
I5 => s_axi_arlen_ii(4),
O => upsized_length(0)
);
\m_axi_arlen[0]_INST_0_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_10_n_0\
);
\m_axi_arlen[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => sr_arburst(1),
I1 => \^q\(32),
I2 => sr_arburst(0),
I3 => sr_araddr(3),
I4 => \m_axi_arlen[0]_INST_0_i_7_n_0\,
I5 => \m_axi_arlen[4]_INST_0_i_6_n_0\,
O => \m_axi_arlen[0]_INST_0_i_2_n_0\
);
\m_axi_arlen[0]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEAEAEAAA"
)
port map (
I0 => sr_araddr(3),
I1 => s_axi_arlen_ii(1),
I2 => sr_araddr(1),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
O => \m_axi_arlen[0]_INST_0_i_3_n_0\
);
\m_axi_arlen[0]_INST_0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => sr_arburst(0),
I1 => \^q\(32),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(3),
O => \m_axi_arlen[0]_INST_0_i_4_n_0\
);
\m_axi_arlen[0]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEEECCCCEEEECCCC"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => \m_axi_arlen[0]_INST_0_i_8_n_0\,
I2 => \m_axi_arlen[0]_INST_0_i_9_n_0\,
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I5 => sr_araddr(0),
O => \m_axi_arlen[0]_INST_0_i_5_n_0\
);
\m_axi_arlen[0]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888B888888888"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => sr_arsize(1),
I3 => sr_arsize(0),
I4 => sr_arsize(2),
I5 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_6_n_0\
);
\m_axi_arlen[0]_INST_0_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
O => \m_axi_arlen[0]_INST_0_i_7_n_0\
);
\m_axi_arlen[0]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888800080000000"
)
port map (
I0 => \^in\(10),
I1 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(2),
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[0]_INST_0_i_8_n_0\
);
\m_axi_arlen[0]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F00000088000000"
)
port map (
I0 => \m_axi_arlen[0]_INST_0_i_10_n_0\,
I1 => sr_araddr(2),
I2 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(0),
I4 => s_axi_arlen_ii(1),
I5 => s_axi_arlen_ii(2),
O => \m_axi_arlen[0]_INST_0_i_9_n_0\
);
\m_axi_arlen[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000100010001FFFE"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[1]_INST_0_i_2_n_0\,
I2 => \m_axi_arlen[1]_INST_0_i_3_n_0\,
I3 => \m_axi_arlen[1]_INST_0_i_4_n_0\,
I4 => \m_axi_arlen[1]_INST_0_i_5_n_0\,
I5 => \m_axi_arlen[1]_INST_0_i_6_n_0\,
O => \^in\(1)
);
\m_axi_arlen[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444040404040"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => sr_araddr(3),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
I5 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
O => \m_axi_arlen[1]_INST_0_i_1_n_0\
);
\m_axi_arlen[1]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0E00000000000000"
)
port map (
I0 => sr_araddr(3),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I5 => \m_axi_arlen[1]_INST_0_i_8_n_0\,
O => \m_axi_arlen[1]_INST_0_i_2_n_0\
);
\m_axi_arlen[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000008800C8"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \m_axi_arlen[1]_INST_0_i_9_n_0\,
I2 => sr_araddr(2),
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_3_n_0\
);
\m_axi_arlen[1]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00000008000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => sr_arburst(1),
I3 => \^q\(32),
I4 => sr_arburst(0),
I5 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
O => \m_axi_arlen[1]_INST_0_i_4_n_0\
);
\m_axi_arlen[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF000002000200"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => sr_arsize(1),
I2 => sr_arsize(2),
I3 => sr_arsize(0),
I4 => s_axi_arlen_ii(1),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => \m_axi_arlen[1]_INST_0_i_5_n_0\
);
\m_axi_arlen[1]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => s_axi_arlen_ii(5),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[1]_INST_0_i_6_n_0\
);
\m_axi_arlen[1]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"EA00"
)
port map (
I0 => sr_araddr(1),
I1 => sr_araddr(0),
I2 => s_axi_arlen_ii(0),
I3 => s_axi_arlen_ii(1),
O => \m_axi_arlen[1]_INST_0_i_7_n_0\
);
\m_axi_arlen[1]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF808000"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => sr_araddr(1),
I2 => sr_araddr(0),
I3 => s_axi_arlen_ii(2),
I4 => sr_araddr(2),
O => \m_axi_arlen[1]_INST_0_i_8_n_0\
);
\m_axi_arlen[1]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \m_axi_arlen[1]_INST_0_i_7_n_0\,
I1 => sr_araddr(3),
I2 => s_axi_arlen_ii(4),
I3 => sr_arburst(0),
I4 => \^q\(32),
I5 => sr_arburst(1),
O => \m_axi_arlen[1]_INST_0_i_9_n_0\
);
\m_axi_arlen[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555AA6A6A"
)
port map (
I0 => \m_axi_arlen[2]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(5),
I2 => \^in\(9),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I5 => \m_axi_arlen[2]_INST_0_i_3_n_0\,
O => \^in\(2)
);
\m_axi_arlen[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFC888C888C888"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[0]_INST_0_i_4_n_0\,
I2 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
I5 => \m_axi_arlen[2]_INST_0_i_4_n_0\,
O => \m_axi_arlen[2]_INST_0_i_1_n_0\
);
\m_axi_arlen[2]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => sr_arsize(0),
I1 => sr_arsize(2),
I2 => sr_arsize(1),
O => \^in\(9)
);
\m_axi_arlen[2]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[2]_INST_0_i_3_n_0\
);
\m_axi_arlen[2]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => sr_arburst(1),
I1 => \^q\(32),
I2 => sr_arburst(0),
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I5 => s_axi_arlen_ii(5),
O => \m_axi_arlen[2]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00551555FFAAEAAA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I4 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I5 => upsized_length(3),
O => \^in\(3)
);
\m_axi_arlen[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
I2 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(4),
I4 => \m_axi_arlen[3]_INST_0_i_4_n_0\,
I5 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
O => \m_axi_arlen[3]_INST_0_i_1_n_0\
);
\m_axi_arlen[3]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010100010000000"
)
port map (
I0 => sr_arsize(1),
I1 => sr_arsize(2),
I2 => sr_arsize(0),
I3 => \m_axi_arlen[3]_INST_0_i_5_n_0\,
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(2),
O => \m_axi_arlen[3]_INST_0_i_2_n_0\
);
\m_axi_arlen[3]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBEAEAEA"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_6_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => \^in\(9),
I4 => s_axi_arlen_ii(6),
O => upsized_length(3)
);
\m_axi_arlen[3]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => sr_arburst(1),
I1 => \^q\(32),
I2 => sr_arburst(0),
O => \m_axi_arlen[3]_INST_0_i_4_n_0\
);
\m_axi_arlen[3]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"E8A0"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => sr_araddr(1),
I2 => sr_araddr(2),
I3 => s_axi_arlen_ii(0),
O => \m_axi_arlen[3]_INST_0_i_5_n_0\
);
\m_axi_arlen[3]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000A000C"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I3 => sr_arsize(0),
I4 => sr_arsize(1),
I5 => sr_arsize(2),
O => \m_axi_arlen[3]_INST_0_i_6_n_0\
);
\m_axi_arlen[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00007FFFFFFF8000"
)
port map (
I0 => \m_axi_arlen[4]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[4]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(7),
I3 => \m_axi_arlen[4]_INST_0_i_3_n_0\,
I4 => \m_axi_arlen[4]_INST_0_i_4_n_0\,
I5 => upsized_length(4),
O => \^in\(4)
);
\m_axi_arlen[4]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \m_axi_araddr[0]_INST_0_i_1_n_0\,
I1 => s_axi_arlen_ii(4),
I2 => sr_arburst(0),
I3 => \^q\(32),
I4 => sr_arburst(1),
O => \m_axi_arlen[4]_INST_0_i_1_n_0\
);
\m_axi_arlen[4]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(6),
O => \m_axi_arlen[4]_INST_0_i_2_n_0\
);
\m_axi_arlen[4]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => sr_araddr(3),
I1 => s_axi_arlen_ii(3),
I2 => \m_axi_arlen[4]_INST_0_i_6_n_0\,
O => \m_axi_arlen[4]_INST_0_i_3_n_0\
);
\m_axi_arlen[4]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EA000000"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(6),
I3 => s_axi_arlen_ii(5),
I4 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[4]_INST_0_i_4_n_0\
);
\m_axi_arlen[4]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000F888F888"
)
port map (
I0 => \^in\(10),
I1 => s_axi_arlen_ii(6),
I2 => \^in\(9),
I3 => s_axi_arlen_ii(7),
I4 => s_axi_arlen_ii(4),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => upsized_length(4)
);
\m_axi_arlen[4]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCE8E8C0E8E8C0C0"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => sr_araddr(2),
I2 => s_axi_arlen_ii(2),
I3 => sr_araddr(0),
I4 => sr_araddr(1),
I5 => s_axi_arlen_ii(0),
O => \m_axi_arlen[4]_INST_0_i_6_n_0\
);
\m_axi_arlen[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"596A6A6A"
)
port map (
I0 => \m_axi_arlen[5]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => \^in\(10),
I4 => s_axi_arlen_ii(7),
O => \^in\(5)
);
\m_axi_arlen[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000000000000"
)
port map (
I0 => \m_axi_arlen[3]_INST_0_i_2_n_0\,
I1 => s_axi_arlen_ii(7),
I2 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I3 => s_axi_arlen_ii(6),
I4 => s_axi_arlen_ii(5),
I5 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
O => \m_axi_arlen[5]_INST_0_i_1_n_0\
);
\m_axi_arlen[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(0),
I2 => sr_arsize(1),
O => \^in\(10)
);
\m_axi_arlen[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFF000080000000"
)
port map (
I0 => \m_axi_arlen[6]_INST_0_i_1_n_0\,
I1 => \m_axi_arlen[6]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(5),
I3 => s_axi_arlen_ii(7),
I4 => s_axi_arlen_ii(6),
I5 => \m_axi_arlen[6]_INST_0_i_3_n_0\,
O => \^in\(6)
);
\m_axi_arlen[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888800080000000"
)
port map (
I0 => s_axi_arlen_ii(2),
I1 => \^in\(10),
I2 => s_axi_arlen_ii(0),
I3 => sr_araddr(2),
I4 => sr_araddr(3),
I5 => s_axi_arlen_ii(1),
O => \m_axi_arlen[6]_INST_0_i_1_n_0\
);
\m_axi_arlen[6]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => s_axi_arlen_ii(3),
I1 => sr_arburst(1),
I2 => \^q\(32),
I3 => sr_arburst(0),
I4 => s_axi_arlen_ii(4),
O => \m_axi_arlen[6]_INST_0_i_2_n_0\
);
\m_axi_arlen[6]_INST_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(32),
O => \m_axi_arlen[6]_INST_0_i_3_n_0\
);
\m_axi_arlen[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"5700"
)
port map (
I0 => \^q\(32),
I1 => sr_arburst(0),
I2 => sr_arburst(1),
I3 => s_axi_arlen_ii(7),
O => \^in\(7)
);
\m_axi_arsize[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F100"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
I3 => sr_arsize(0),
O => m_axi_arsize(0)
);
\m_axi_arsize[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F100"
)
port map (
I0 => sr_arburst(0),
I1 => sr_arburst(1),
I2 => \m_axi_arsize[1]_INST_0_i_1_n_0\,
I3 => sr_arsize(1),
O => m_axi_arsize(1)
);
\m_axi_arsize[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000002FFFFFFFF"
)
port map (
I0 => \m_axi_arsize[1]_INST_0_i_2_n_0\,
I1 => \m_axi_arsize[2]_INST_0_i_2_n_0\,
I2 => s_axi_arlen_ii(3),
I3 => s_axi_arlen_ii(2),
I4 => \m_axi_arsize[2]_INST_0_i_3_n_0\,
I5 => \^q\(32),
O => \m_axi_arsize[1]_INST_0_i_1_n_0\
);
\m_axi_arsize[1]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
O => \m_axi_arsize[1]_INST_0_i_2_n_0\
);
\m_axi_arsize[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFE000"
)
port map (
I0 => sr_arburst(1),
I1 => sr_arburst(0),
I2 => \^q\(32),
I3 => \m_axi_arsize[2]_INST_0_i_1_n_0\,
I4 => sr_arsize(2),
O => m_axi_arsize(2)
);
\m_axi_arsize[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => s_axi_arlen_ii(2),
I3 => s_axi_arlen_ii(3),
I4 => \m_axi_arsize[2]_INST_0_i_2_n_0\,
I5 => \m_axi_arsize[2]_INST_0_i_3_n_0\,
O => \m_axi_arsize[2]_INST_0_i_1_n_0\
);
\m_axi_arsize[2]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(6),
I1 => s_axi_arlen_ii(7),
O => \m_axi_arsize[2]_INST_0_i_2_n_0\
);
\m_axi_arsize[2]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen_ii(4),
I1 => s_axi_arlen_ii(5),
O => \m_axi_arsize[2]_INST_0_i_3_n_0\
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^sr_arvalid\,
O => \m_payload_i[31]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(0),
Q => sr_araddr(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(10),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(11),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(12),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(13),
Q => \^q\(9),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(14),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(15),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(16),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(17),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(18),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(19),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(1),
Q => sr_araddr(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(20),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(21),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(22),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(23),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(24),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(25),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(26),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(27),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(28),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(29),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(2),
Q => sr_araddr(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(30),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(31),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(32),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(33),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(34),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(35),
Q => sr_arsize(0),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(36),
Q => sr_arsize(1),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(37),
Q => sr_arsize(2),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(38),
Q => sr_arburst(0),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(39),
Q => sr_arburst(1),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(3),
Q => sr_araddr(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(40),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(41),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(42),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(43),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(44),
Q => s_axi_arlen_ii(0),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(45),
Q => s_axi_arlen_ii(1),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(46),
Q => s_axi_arlen_ii(2),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(47),
Q => s_axi_arlen_ii(3),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(48),
Q => s_axi_arlen_ii(4),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(49),
Q => s_axi_arlen_ii(5),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(4),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(50),
Q => s_axi_arlen_ii(6),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(51),
Q => s_axi_arlen_ii(7),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(52),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(53),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(54),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(55),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(56),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(57),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(58),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(5),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(59),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(60),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(6),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(7),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(8),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \m_payload_i[31]_i_1_n_0\,
D => D(9),
Q => \^q\(5),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B100"
)
port map (
I0 => \^s_axi_arready\,
I1 => cmd_push_block_reg,
I2 => s_axi_arvalid,
I3 => \^s_ready_i_reg_0\,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_arvalid\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"DD5F0000"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => cmd_push_block_reg,
I2 => s_axi_arvalid,
I3 => \^sr_arvalid\,
I4 => \^aresetn_d_reg[1]_0\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axi_arready\,
R => '0'
);
sub_sized_wrap0_carry_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00010111"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => DI(1)
);
sub_sized_wrap0_carry_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00070077"
)
port map (
I0 => s_axi_arlen_ii(1),
I1 => s_axi_arlen_ii(0),
I2 => sr_arsize(1),
I3 => sr_arsize(2),
I4 => sr_arsize(0),
O => DI(0)
);
sub_sized_wrap0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(7),
I1 => s_axi_arlen_ii(6),
O => S(3)
);
sub_sized_wrap0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arlen_ii(5),
I1 => s_axi_arlen_ii(4),
O => S(2)
);
sub_sized_wrap0_carry_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"010010EE"
)
port map (
I0 => sr_arsize(2),
I1 => sr_arsize(1),
I2 => sr_arsize(0),
I3 => s_axi_arlen_ii(2),
I4 => s_axi_arlen_ii(3),
O => S(1)
);
sub_sized_wrap0_carry_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"11181188"
)
port map (
I0 => s_axi_arlen_ii(0),
I1 => s_axi_arlen_ii(1),
I2 => sr_arsize(0),
I3 => sr_arsize(2),
I4 => sr_arsize(1),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
\s_axi_rdata[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 130 downto 0 );
\s_axi_rdata[1]\ : out STD_LOGIC;
\s_axi_rdata[2]\ : out STD_LOGIC;
\s_axi_rdata[3]\ : out STD_LOGIC;
\s_axi_rdata[4]\ : out STD_LOGIC;
\s_axi_rdata[5]\ : out STD_LOGIC;
\s_axi_rdata[6]\ : out STD_LOGIC;
\s_axi_rdata[7]\ : out STD_LOGIC;
\s_axi_rdata[8]\ : out STD_LOGIC;
\s_axi_rdata[9]\ : out STD_LOGIC;
\s_axi_rdata[10]\ : out STD_LOGIC;
\s_axi_rdata[11]\ : out STD_LOGIC;
\s_axi_rdata[12]\ : out STD_LOGIC;
\s_axi_rdata[13]\ : out STD_LOGIC;
\s_axi_rdata[14]\ : out STD_LOGIC;
\s_axi_rdata[15]\ : out STD_LOGIC;
\s_axi_rdata[16]\ : out STD_LOGIC;
\s_axi_rdata[17]\ : out STD_LOGIC;
\s_axi_rdata[18]\ : out STD_LOGIC;
\s_axi_rdata[19]\ : out STD_LOGIC;
\s_axi_rdata[20]\ : out STD_LOGIC;
\s_axi_rdata[21]\ : out STD_LOGIC;
\s_axi_rdata[22]\ : out STD_LOGIC;
\s_axi_rdata[23]\ : out STD_LOGIC;
\s_axi_rdata[24]\ : out STD_LOGIC;
\s_axi_rdata[25]\ : out STD_LOGIC;
\s_axi_rdata[26]\ : out STD_LOGIC;
\s_axi_rdata[27]\ : out STD_LOGIC;
\s_axi_rdata[28]\ : out STD_LOGIC;
\s_axi_rdata[29]\ : out STD_LOGIC;
\s_axi_rdata[30]\ : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rvalid : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \^q\ : STD_LOGIC_VECTOR ( 130 downto 0 );
signal \^m_axi_rready\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 130 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[100]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[101]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[102]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[103]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[104]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[105]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[106]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[107]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[108]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[109]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[110]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[111]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[112]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[113]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[114]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[115]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[116]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[117]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[118]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[119]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[120]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[121]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[122]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[123]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[124]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[125]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[126]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[127]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[128]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[129]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[130]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[67]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[68]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[69]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[70]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[71]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[72]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[73]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[74]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[75]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[76]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[77]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[78]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[79]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[80]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[81]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[82]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[83]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[84]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[85]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[86]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[87]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[88]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[89]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[90]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[91]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[92]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[93]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[94]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[95]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[96]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[97]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[98]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[99]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[100]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[101]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[102]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[103]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[104]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[105]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[106]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_payload_i[107]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[108]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_payload_i[109]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[110]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_payload_i[111]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[112]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_payload_i[113]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[114]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_payload_i[115]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[116]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_payload_i[117]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[118]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_payload_i[119]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[120]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_payload_i[121]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[122]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_payload_i[123]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[124]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[125]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[126]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_payload_i[127]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[128]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[129]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[67]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[68]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[69]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[70]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[71]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[72]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[73]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[74]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[75]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[76]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[77]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[78]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[79]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[80]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[81]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[82]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[83]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[84]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[85]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[86]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[87]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[88]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[89]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[90]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[91]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[92]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[93]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[94]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[95]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[96]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[97]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[98]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[99]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_valid_i_i_1__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair0";
begin
Q(130 downto 0) <= \^q\(130 downto 0);
m_axi_rready <= \^m_axi_rready\;
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[100]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(100),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[100]\,
O => skid_buffer(100)
);
\m_payload_i[101]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(101),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[101]\,
O => skid_buffer(101)
);
\m_payload_i[102]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(102),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[102]\,
O => skid_buffer(102)
);
\m_payload_i[103]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(103),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[103]\,
O => skid_buffer(103)
);
\m_payload_i[104]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(104),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[104]\,
O => skid_buffer(104)
);
\m_payload_i[105]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(105),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[105]\,
O => skid_buffer(105)
);
\m_payload_i[106]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(106),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[106]\,
O => skid_buffer(106)
);
\m_payload_i[107]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(107),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[107]\,
O => skid_buffer(107)
);
\m_payload_i[108]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(108),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[108]\,
O => skid_buffer(108)
);
\m_payload_i[109]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(109),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[109]\,
O => skid_buffer(109)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[110]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(110),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[110]\,
O => skid_buffer(110)
);
\m_payload_i[111]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(111),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[111]\,
O => skid_buffer(111)
);
\m_payload_i[112]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(112),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[112]\,
O => skid_buffer(112)
);
\m_payload_i[113]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(113),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[113]\,
O => skid_buffer(113)
);
\m_payload_i[114]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(114),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[114]\,
O => skid_buffer(114)
);
\m_payload_i[115]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(115),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[115]\,
O => skid_buffer(115)
);
\m_payload_i[116]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(116),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[116]\,
O => skid_buffer(116)
);
\m_payload_i[117]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(117),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[117]\,
O => skid_buffer(117)
);
\m_payload_i[118]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(118),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[118]\,
O => skid_buffer(118)
);
\m_payload_i[119]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(119),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[119]\,
O => skid_buffer(119)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[120]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(120),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[120]\,
O => skid_buffer(120)
);
\m_payload_i[121]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(121),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[121]\,
O => skid_buffer(121)
);
\m_payload_i[122]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(122),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[122]\,
O => skid_buffer(122)
);
\m_payload_i[123]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(123),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[123]\,
O => skid_buffer(123)
);
\m_payload_i[124]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(124),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[124]\,
O => skid_buffer(124)
);
\m_payload_i[125]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(125),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[125]\,
O => skid_buffer(125)
);
\m_payload_i[126]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(126),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[126]\,
O => skid_buffer(126)
);
\m_payload_i[127]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(127),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[127]\,
O => skid_buffer(127)
);
\m_payload_i[128]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[128]\,
O => skid_buffer(128)
);
\m_payload_i[129]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[129]\,
O => skid_buffer(129)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[130]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast,
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[130]\,
O => skid_buffer(130)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(64),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(65),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => skid_buffer(65)
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(66),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\m_payload_i[67]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(67),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[67]\,
O => skid_buffer(67)
);
\m_payload_i[68]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(68),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[68]\,
O => skid_buffer(68)
);
\m_payload_i[69]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(69),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[69]\,
O => skid_buffer(69)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[70]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(70),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[70]\,
O => skid_buffer(70)
);
\m_payload_i[71]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(71),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[71]\,
O => skid_buffer(71)
);
\m_payload_i[72]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(72),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[72]\,
O => skid_buffer(72)
);
\m_payload_i[73]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(73),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[73]\,
O => skid_buffer(73)
);
\m_payload_i[74]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(74),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[74]\,
O => skid_buffer(74)
);
\m_payload_i[75]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(75),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[75]\,
O => skid_buffer(75)
);
\m_payload_i[76]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(76),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[76]\,
O => skid_buffer(76)
);
\m_payload_i[77]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(77),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[77]\,
O => skid_buffer(77)
);
\m_payload_i[78]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(78),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[78]\,
O => skid_buffer(78)
);
\m_payload_i[79]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(79),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[79]\,
O => skid_buffer(79)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[80]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(80),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[80]\,
O => skid_buffer(80)
);
\m_payload_i[81]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(81),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[81]\,
O => skid_buffer(81)
);
\m_payload_i[82]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(82),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[82]\,
O => skid_buffer(82)
);
\m_payload_i[83]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(83),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[83]\,
O => skid_buffer(83)
);
\m_payload_i[84]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(84),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[84]\,
O => skid_buffer(84)
);
\m_payload_i[85]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(85),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[85]\,
O => skid_buffer(85)
);
\m_payload_i[86]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(86),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[86]\,
O => skid_buffer(86)
);
\m_payload_i[87]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(87),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[87]\,
O => skid_buffer(87)
);
\m_payload_i[88]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(88),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[88]\,
O => skid_buffer(88)
);
\m_payload_i[89]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(89),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[89]\,
O => skid_buffer(89)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[90]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(90),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[90]\,
O => skid_buffer(90)
);
\m_payload_i[91]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(91),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[91]\,
O => skid_buffer(91)
);
\m_payload_i[92]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(92),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[92]\,
O => skid_buffer(92)
);
\m_payload_i[93]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(93),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[93]\,
O => skid_buffer(93)
);
\m_payload_i[94]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(94),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[94]\,
O => skid_buffer(94)
);
\m_payload_i[95]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(95),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[95]\,
O => skid_buffer(95)
);
\m_payload_i[96]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(96),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[96]\,
O => skid_buffer(96)
);
\m_payload_i[97]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(97),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[97]\,
O => skid_buffer(97)
);
\m_payload_i[98]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(98),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[98]\,
O => skid_buffer(98)
);
\m_payload_i[99]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(99),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[99]\,
O => skid_buffer(99)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(100),
Q => \^q\(100),
R => '0'
);
\m_payload_i_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(101),
Q => \^q\(101),
R => '0'
);
\m_payload_i_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(102),
Q => \^q\(102),
R => '0'
);
\m_payload_i_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(103),
Q => \^q\(103),
R => '0'
);
\m_payload_i_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(104),
Q => \^q\(104),
R => '0'
);
\m_payload_i_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(105),
Q => \^q\(105),
R => '0'
);
\m_payload_i_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(106),
Q => \^q\(106),
R => '0'
);
\m_payload_i_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(107),
Q => \^q\(107),
R => '0'
);
\m_payload_i_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(108),
Q => \^q\(108),
R => '0'
);
\m_payload_i_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(109),
Q => \^q\(109),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(110),
Q => \^q\(110),
R => '0'
);
\m_payload_i_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(111),
Q => \^q\(111),
R => '0'
);
\m_payload_i_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(112),
Q => \^q\(112),
R => '0'
);
\m_payload_i_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(113),
Q => \^q\(113),
R => '0'
);
\m_payload_i_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(114),
Q => \^q\(114),
R => '0'
);
\m_payload_i_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(115),
Q => \^q\(115),
R => '0'
);
\m_payload_i_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(116),
Q => \^q\(116),
R => '0'
);
\m_payload_i_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(117),
Q => \^q\(117),
R => '0'
);
\m_payload_i_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(118),
Q => \^q\(118),
R => '0'
);
\m_payload_i_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(119),
Q => \^q\(119),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(120),
Q => \^q\(120),
R => '0'
);
\m_payload_i_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(121),
Q => \^q\(121),
R => '0'
);
\m_payload_i_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(122),
Q => \^q\(122),
R => '0'
);
\m_payload_i_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(123),
Q => \^q\(123),
R => '0'
);
\m_payload_i_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(124),
Q => \^q\(124),
R => '0'
);
\m_payload_i_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(125),
Q => \^q\(125),
R => '0'
);
\m_payload_i_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(126),
Q => \^q\(126),
R => '0'
);
\m_payload_i_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(127),
Q => \^q\(127),
R => '0'
);
\m_payload_i_reg[128]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(128),
Q => \^q\(128),
R => '0'
);
\m_payload_i_reg[129]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(129),
Q => \^q\(129),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[130]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(130),
Q => \^q\(130),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(37),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(40),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(41),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(42),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(43),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(52),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(59),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(60),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(61),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(62),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(63),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(64),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(65),
Q => \^q\(65),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(66),
Q => \^q\(66),
R => '0'
);
\m_payload_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(67),
Q => \^q\(67),
R => '0'
);
\m_payload_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(68),
Q => \^q\(68),
R => '0'
);
\m_payload_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(69),
Q => \^q\(69),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(70),
Q => \^q\(70),
R => '0'
);
\m_payload_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(71),
Q => \^q\(71),
R => '0'
);
\m_payload_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(72),
Q => \^q\(72),
R => '0'
);
\m_payload_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(73),
Q => \^q\(73),
R => '0'
);
\m_payload_i_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(74),
Q => \^q\(74),
R => '0'
);
\m_payload_i_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(75),
Q => \^q\(75),
R => '0'
);
\m_payload_i_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(76),
Q => \^q\(76),
R => '0'
);
\m_payload_i_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(77),
Q => \^q\(77),
R => '0'
);
\m_payload_i_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(78),
Q => \^q\(78),
R => '0'
);
\m_payload_i_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(79),
Q => \^q\(79),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(80),
Q => \^q\(80),
R => '0'
);
\m_payload_i_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(81),
Q => \^q\(81),
R => '0'
);
\m_payload_i_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(82),
Q => \^q\(82),
R => '0'
);
\m_payload_i_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(83),
Q => \^q\(83),
R => '0'
);
\m_payload_i_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(84),
Q => \^q\(84),
R => '0'
);
\m_payload_i_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(85),
Q => \^q\(85),
R => '0'
);
\m_payload_i_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(86),
Q => \^q\(86),
R => '0'
);
\m_payload_i_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(87),
Q => \^q\(87),
R => '0'
);
\m_payload_i_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(88),
Q => \^q\(88),
R => '0'
);
\m_payload_i_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(89),
Q => \^q\(89),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(90),
Q => \^q\(90),
R => '0'
);
\m_payload_i_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(91),
Q => \^q\(91),
R => '0'
);
\m_payload_i_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(92),
Q => \^q\(92),
R => '0'
);
\m_payload_i_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(93),
Q => \^q\(93),
R => '0'
);
\m_payload_i_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(94),
Q => \^q\(94),
R => '0'
);
\m_payload_i_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(95),
Q => \^q\(95),
R => '0'
);
\m_payload_i_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(96),
Q => \^q\(96),
R => '0'
);
\m_payload_i_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(97),
Q => \^q\(97),
R => '0'
);
\m_payload_i_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(98),
Q => \^q\(98),
R => '0'
);
\m_payload_i_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(99),
Q => \^q\(99),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF00"
)
port map (
I0 => \^m_axi_rready\,
I1 => m_axi_rvalid,
I2 => E(0),
I3 => \aresetn_d_reg[1]\,
O => \m_valid_i_i_1__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => mr_rvalid,
R => '0'
);
\s_axi_rdata[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(0),
I1 => \^q\(64),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(32),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(96),
O => \s_axi_rdata[0]\
);
\s_axi_rdata[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(10),
I1 => \^q\(74),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(42),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(106),
O => \s_axi_rdata[10]\
);
\s_axi_rdata[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(11),
I1 => \^q\(75),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(43),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(107),
O => \s_axi_rdata[11]\
);
\s_axi_rdata[12]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(12),
I1 => \^q\(76),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(44),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(108),
O => \s_axi_rdata[12]\
);
\s_axi_rdata[13]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(13),
I1 => \^q\(77),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(45),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(109),
O => \s_axi_rdata[13]\
);
\s_axi_rdata[14]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(14),
I1 => \^q\(78),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(46),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(110),
O => \s_axi_rdata[14]\
);
\s_axi_rdata[15]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(15),
I1 => \^q\(79),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(47),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(111),
O => \s_axi_rdata[15]\
);
\s_axi_rdata[16]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(16),
I1 => \^q\(80),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(48),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(112),
O => \s_axi_rdata[16]\
);
\s_axi_rdata[17]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(17),
I1 => \^q\(81),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(49),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(113),
O => \s_axi_rdata[17]\
);
\s_axi_rdata[18]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(18),
I1 => \^q\(82),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(50),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(114),
O => \s_axi_rdata[18]\
);
\s_axi_rdata[19]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(19),
I1 => \^q\(83),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(51),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(115),
O => \s_axi_rdata[19]\
);
\s_axi_rdata[1]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(1),
I1 => \^q\(65),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(33),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(97),
O => \s_axi_rdata[1]\
);
\s_axi_rdata[20]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(20),
I1 => \^q\(84),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(52),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(116),
O => \s_axi_rdata[20]\
);
\s_axi_rdata[21]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(21),
I1 => \^q\(85),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(53),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(117),
O => \s_axi_rdata[21]\
);
\s_axi_rdata[22]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(22),
I1 => \^q\(86),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(54),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(118),
O => \s_axi_rdata[22]\
);
\s_axi_rdata[23]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(23),
I1 => \^q\(87),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(55),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(119),
O => \s_axi_rdata[23]\
);
\s_axi_rdata[24]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(24),
I1 => \^q\(88),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(56),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(120),
O => \s_axi_rdata[24]\
);
\s_axi_rdata[25]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(25),
I1 => \^q\(89),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(57),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(121),
O => \s_axi_rdata[25]\
);
\s_axi_rdata[26]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(26),
I1 => \^q\(90),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(58),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(122),
O => \s_axi_rdata[26]\
);
\s_axi_rdata[27]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(27),
I1 => \^q\(91),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(59),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(123),
O => \s_axi_rdata[27]\
);
\s_axi_rdata[28]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(28),
I1 => \^q\(92),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(60),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(124),
O => \s_axi_rdata[28]\
);
\s_axi_rdata[29]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(29),
I1 => \^q\(93),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(61),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(125),
O => \s_axi_rdata[29]\
);
\s_axi_rdata[2]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(2),
I1 => \^q\(66),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(34),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(98),
O => \s_axi_rdata[2]\
);
\s_axi_rdata[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(30),
I1 => \^q\(94),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(62),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(126),
O => \s_axi_rdata[30]\
);
\s_axi_rdata[31]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(31),
I1 => \^q\(95),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(63),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(127),
O => \s_axi_rdata[31]\
);
\s_axi_rdata[3]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(67),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(35),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(99),
O => \s_axi_rdata[3]\
);
\s_axi_rdata[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(4),
I1 => \^q\(68),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(36),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(100),
O => \s_axi_rdata[4]\
);
\s_axi_rdata[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(5),
I1 => \^q\(69),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(37),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(101),
O => \s_axi_rdata[5]\
);
\s_axi_rdata[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(70),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(38),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(102),
O => \s_axi_rdata[6]\
);
\s_axi_rdata[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(7),
I1 => \^q\(71),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(39),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(103),
O => \s_axi_rdata[7]\
);
\s_axi_rdata[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(8),
I1 => \^q\(72),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(40),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(104),
O => \s_axi_rdata[8]\
);
\s_axi_rdata[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(9),
I1 => \^q\(73),
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
I3 => \^q\(41),
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
I5 => \^q\(105),
O => \s_axi_rdata[9]\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F200"
)
port map (
I0 => \^m_axi_rready\,
I1 => m_axi_rvalid,
I2 => E(0),
I3 => \aresetn_d_reg[0]\,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^m_axi_rready\,
R => '0'
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[100]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(100),
Q => \skid_buffer_reg_n_0_[100]\,
R => '0'
);
\skid_buffer_reg[101]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(101),
Q => \skid_buffer_reg_n_0_[101]\,
R => '0'
);
\skid_buffer_reg[102]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(102),
Q => \skid_buffer_reg_n_0_[102]\,
R => '0'
);
\skid_buffer_reg[103]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(103),
Q => \skid_buffer_reg_n_0_[103]\,
R => '0'
);
\skid_buffer_reg[104]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(104),
Q => \skid_buffer_reg_n_0_[104]\,
R => '0'
);
\skid_buffer_reg[105]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(105),
Q => \skid_buffer_reg_n_0_[105]\,
R => '0'
);
\skid_buffer_reg[106]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(106),
Q => \skid_buffer_reg_n_0_[106]\,
R => '0'
);
\skid_buffer_reg[107]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(107),
Q => \skid_buffer_reg_n_0_[107]\,
R => '0'
);
\skid_buffer_reg[108]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(108),
Q => \skid_buffer_reg_n_0_[108]\,
R => '0'
);
\skid_buffer_reg[109]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(109),
Q => \skid_buffer_reg_n_0_[109]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[110]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(110),
Q => \skid_buffer_reg_n_0_[110]\,
R => '0'
);
\skid_buffer_reg[111]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(111),
Q => \skid_buffer_reg_n_0_[111]\,
R => '0'
);
\skid_buffer_reg[112]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(112),
Q => \skid_buffer_reg_n_0_[112]\,
R => '0'
);
\skid_buffer_reg[113]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(113),
Q => \skid_buffer_reg_n_0_[113]\,
R => '0'
);
\skid_buffer_reg[114]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(114),
Q => \skid_buffer_reg_n_0_[114]\,
R => '0'
);
\skid_buffer_reg[115]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(115),
Q => \skid_buffer_reg_n_0_[115]\,
R => '0'
);
\skid_buffer_reg[116]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(116),
Q => \skid_buffer_reg_n_0_[116]\,
R => '0'
);
\skid_buffer_reg[117]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(117),
Q => \skid_buffer_reg_n_0_[117]\,
R => '0'
);
\skid_buffer_reg[118]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(118),
Q => \skid_buffer_reg_n_0_[118]\,
R => '0'
);
\skid_buffer_reg[119]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(119),
Q => \skid_buffer_reg_n_0_[119]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[120]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(120),
Q => \skid_buffer_reg_n_0_[120]\,
R => '0'
);
\skid_buffer_reg[121]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(121),
Q => \skid_buffer_reg_n_0_[121]\,
R => '0'
);
\skid_buffer_reg[122]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(122),
Q => \skid_buffer_reg_n_0_[122]\,
R => '0'
);
\skid_buffer_reg[123]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(123),
Q => \skid_buffer_reg_n_0_[123]\,
R => '0'
);
\skid_buffer_reg[124]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(124),
Q => \skid_buffer_reg_n_0_[124]\,
R => '0'
);
\skid_buffer_reg[125]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(125),
Q => \skid_buffer_reg_n_0_[125]\,
R => '0'
);
\skid_buffer_reg[126]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(126),
Q => \skid_buffer_reg_n_0_[126]\,
R => '0'
);
\skid_buffer_reg[127]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(127),
Q => \skid_buffer_reg_n_0_[127]\,
R => '0'
);
\skid_buffer_reg[128]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[128]\,
R => '0'
);
\skid_buffer_reg[129]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[129]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[130]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rlast,
Q => \skid_buffer_reg_n_0_[130]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(64),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(65),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(66),
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[67]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(67),
Q => \skid_buffer_reg_n_0_[67]\,
R => '0'
);
\skid_buffer_reg[68]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(68),
Q => \skid_buffer_reg_n_0_[68]\,
R => '0'
);
\skid_buffer_reg[69]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(69),
Q => \skid_buffer_reg_n_0_[69]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[70]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(70),
Q => \skid_buffer_reg_n_0_[70]\,
R => '0'
);
\skid_buffer_reg[71]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(71),
Q => \skid_buffer_reg_n_0_[71]\,
R => '0'
);
\skid_buffer_reg[72]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(72),
Q => \skid_buffer_reg_n_0_[72]\,
R => '0'
);
\skid_buffer_reg[73]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(73),
Q => \skid_buffer_reg_n_0_[73]\,
R => '0'
);
\skid_buffer_reg[74]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(74),
Q => \skid_buffer_reg_n_0_[74]\,
R => '0'
);
\skid_buffer_reg[75]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(75),
Q => \skid_buffer_reg_n_0_[75]\,
R => '0'
);
\skid_buffer_reg[76]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(76),
Q => \skid_buffer_reg_n_0_[76]\,
R => '0'
);
\skid_buffer_reg[77]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(77),
Q => \skid_buffer_reg_n_0_[77]\,
R => '0'
);
\skid_buffer_reg[78]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(78),
Q => \skid_buffer_reg_n_0_[78]\,
R => '0'
);
\skid_buffer_reg[79]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(79),
Q => \skid_buffer_reg_n_0_[79]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[80]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(80),
Q => \skid_buffer_reg_n_0_[80]\,
R => '0'
);
\skid_buffer_reg[81]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(81),
Q => \skid_buffer_reg_n_0_[81]\,
R => '0'
);
\skid_buffer_reg[82]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(82),
Q => \skid_buffer_reg_n_0_[82]\,
R => '0'
);
\skid_buffer_reg[83]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(83),
Q => \skid_buffer_reg_n_0_[83]\,
R => '0'
);
\skid_buffer_reg[84]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(84),
Q => \skid_buffer_reg_n_0_[84]\,
R => '0'
);
\skid_buffer_reg[85]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(85),
Q => \skid_buffer_reg_n_0_[85]\,
R => '0'
);
\skid_buffer_reg[86]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(86),
Q => \skid_buffer_reg_n_0_[86]\,
R => '0'
);
\skid_buffer_reg[87]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(87),
Q => \skid_buffer_reg_n_0_[87]\,
R => '0'
);
\skid_buffer_reg[88]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(88),
Q => \skid_buffer_reg_n_0_[88]\,
R => '0'
);
\skid_buffer_reg[89]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(89),
Q => \skid_buffer_reg_n_0_[89]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[90]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(90),
Q => \skid_buffer_reg_n_0_[90]\,
R => '0'
);
\skid_buffer_reg[91]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(91),
Q => \skid_buffer_reg_n_0_[91]\,
R => '0'
);
\skid_buffer_reg[92]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(92),
Q => \skid_buffer_reg_n_0_[92]\,
R => '0'
);
\skid_buffer_reg[93]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(93),
Q => \skid_buffer_reg_n_0_[93]\,
R => '0'
);
\skid_buffer_reg[94]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(94),
Q => \skid_buffer_reg_n_0_[94]\,
R => '0'
);
\skid_buffer_reg[95]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(95),
Q => \skid_buffer_reg_n_0_[95]\,
R => '0'
);
\skid_buffer_reg[96]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(96),
Q => \skid_buffer_reg_n_0_[96]\,
R => '0'
);
\skid_buffer_reg[97]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(97),
Q => \skid_buffer_reg_n_0_[97]\,
R => '0'
);
\skid_buffer_reg[98]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(98),
Q => \skid_buffer_reg_n_0_[98]\,
R => '0'
);
\skid_buffer_reg[99]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(99),
Q => \skid_buffer_reg_n_0_[99]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \^m_axi_rready\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo is
port (
\M_AXI_RDATA_I_reg[127]\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\current_word_1_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
first_word_reg : out STD_LOGIC;
first_word_reg_0 : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
\s_axi_rdata[31]_0\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
\M_AXI_RDATA_I_reg[127]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
cmd_push_block0 : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
mr_rvalid : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC;
\pre_next_word_1_reg[3]\ : in STD_LOGIC;
\pre_next_word_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_word : in STD_LOGIC;
cmd_push_block : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\current_word_1_reg[3]_0\ : in STD_LOGIC;
\current_word_1_reg[2]\ : in STD_LOGIC;
\current_word_1_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_mi_word_q : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo : entity is "generic_baseblocks_v2_1_0_command_fifo";
end system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo;
architecture STRUCTURE of system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo is
signal \^m_axi_rdata_i_reg[127]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0\ : STD_LOGIC;
signal \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[0]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[1]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[2]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[3]_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_2_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q[4]_i_3_n_0\ : STD_LOGIC;
signal \USE_RTL_ADDR.addr_q_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\ : STD_LOGIC;
signal \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\ : STD_LOGIC;
signal \^use_rtl_length.length_counter_q_reg[7]_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\ : STD_LOGIC;
signal \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\ : STD_LOGIC;
signal addr_q : STD_LOGIC;
signal buffer_Full_q : STD_LOGIC;
signal cmd_last_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_step : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^current_word_1_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal data_Exists_I : STD_LOGIC;
signal data_Exists_I_i_2_n_0 : STD_LOGIC;
signal \^first_word_reg\ : STD_LOGIC;
signal \^first_word_reg_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[130]_i_6_n_0\ : STD_LOGIC;
signal next_Data_Exists : STD_LOGIC;
signal \pre_next_word_1[1]_i_2_n_0\ : STD_LOGIC;
signal \pre_next_word_1[3]_i_4_n_0\ : STD_LOGIC;
signal rd_cmd_complete_wrap : STD_LOGIC;
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rd_cmd_mask : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_cmd_modified : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rd_cmd_offset : STD_LOGIC_VECTOR ( 3 downto 2 );
signal rd_cmd_packed_wrap : STD_LOGIC;
signal s_axi_rlast_INST_0_i_10_n_0 : STD_LOGIC;
signal valid_Write : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \M_AXI_RDATA_I[127]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[0]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \USE_RTL_ADDR.addr_q[2]_i_1\ : label is "soft_lutpair76";
attribute srl_bus_name : string;
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name : string;
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][0]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][10]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][11]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][12]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][13]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][14]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][14]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][17]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][18]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][19]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][1]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][20]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][21]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][22]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][23]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][24]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][25]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][26]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][27]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][28]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][29]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][2]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][30]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][30]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][31]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][31]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][31]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][32]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][32]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][33]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][33]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][34]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][34]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][3]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][4]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][5]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][6]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][7]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][8]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 ";
attribute srl_bus_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] ";
attribute srl_name of \USE_RTL_FIFO.data_srl_reg[31][9]_srl32\ : label is "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \USE_RTL_VALID_WRITE.buffer_Full_q_i_2\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of cmd_push_block_i_1 : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \current_word_1[0]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of data_Exists_I_i_2 : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_3\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of s_axi_rlast_INST_0_i_10 : label is "soft_lutpair74";
attribute SOFT_HLUTNM of s_axi_rvalid_INST_0 : label is "soft_lutpair77";
attribute SOFT_HLUTNM of s_ready_i_i_2 : label is "soft_lutpair79";
begin
\M_AXI_RDATA_I_reg[127]\ <= \^m_axi_rdata_i_reg[127]\;
Q(12 downto 0) <= \^q\(12 downto 0);
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ <= \^use_rtl_length.length_counter_q_reg[7]_0\;
\current_word_1_reg[3]\(3 downto 0) <= \^current_word_1_reg[3]\(3 downto 0);
first_word_reg <= \^first_word_reg\;
first_word_reg_0 <= \^first_word_reg_0\;
\M_AXI_RDATA_I[127]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => mr_rvalid,
I1 => \^m_axi_rdata_i_reg[127]\,
I2 => first_mi_word_q,
I3 => use_wrap_buffer,
I4 => rd_cmd_packed_wrap,
O => \M_AXI_RDATA_I_reg[127]_0\(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00005501FFFFFFFF"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0\,
I1 => wrap_buffer_available,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
I3 => use_wrap_buffer,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\,
I5 => \^m_axi_rdata_i_reg[127]\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"07FF"
)
port map (
I0 => \^m_axi_rdata_i_reg[127]\,
I1 => mr_rvalid,
I2 => use_wrap_buffer,
I3 => s_axi_rready,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF9F9FF"
)
port map (
I0 => cmd_last_word(3),
I1 => \current_word_1_reg[3]_0\,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0\,
I3 => cmd_last_word(2),
I4 => \current_word_1_reg[2]\,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0\,
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(1),
I1 => rd_cmd_first_word(1),
I2 => first_word,
I3 => \^q\(12),
I4 => \current_word_1_reg[3]_1\(1),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_5_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6665666A"
)
port map (
I0 => cmd_last_word(0),
I1 => rd_cmd_first_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \current_word_1_reg[3]_1\(0),
O => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_6_n_0\
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q => \^q\(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q => cmd_step(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q => rd_cmd_mask(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q => rd_cmd_mask(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q => rd_cmd_mask(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\,
Q => rd_cmd_mask(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q => rd_cmd_offset(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q => rd_cmd_offset(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q => cmd_last_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q => \^q\(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q => cmd_last_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q => cmd_last_word(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q => cmd_last_word(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q => rd_cmd_next_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q => rd_cmd_next_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q => \^q\(8),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q => \^q\(9),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q => rd_cmd_first_word(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q => rd_cmd_first_word(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q => \^q\(10),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q => \^q\(2),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\,
Q => \^q\(11),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\,
Q => rd_cmd_packed_wrap,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[32]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\,
Q => rd_cmd_complete_wrap,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[33]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\,
Q => rd_cmd_modified,
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\,
Q => \^q\(12),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q => \^q\(3),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q => \^q\(4),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q => \^q\(5),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q => \^q\(6),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q => \^q\(7),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q => cmd_step(0),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q => cmd_step(1),
R => SR(0)
);
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
D => data_Exists_I,
Q => \^m_axi_rdata_i_reg[127]\,
R => SR(0)
);
\USE_RTL_ADDR.addr_q[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
O => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA9A55555565"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => buffer_Full_q,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I5 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BF40F40B"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I1 => valid_Write,
I2 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(1),
O => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFFF2000FFBA0045"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I1 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I2 => valid_Write,
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"80808080800C8080"
)
port map (
I0 => data_Exists_I_i_2_n_0,
I1 => data_Exists_I,
I2 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I3 => buffer_Full_q,
I4 => sr_arvalid,
I5 => cmd_push_block,
O => addr_q
);
\USE_RTL_ADDR.addr_q[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAA9"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I3 => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\,
I4 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I5 => \USE_RTL_ADDR.addr_q_reg__0\(2),
O => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\
);
\USE_RTL_ADDR.addr_q[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888888808888"
)
port map (
I0 => valid_Write,
I1 => \^m_axi_rdata_i_reg[127]\,
I2 => \^first_word_reg\,
I3 => \^first_word_reg_0\,
I4 => use_wrap_buffer_reg,
I5 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_3_n_0\,
O => \USE_RTL_ADDR.addr_q[4]_i_3_n_0\
);
\USE_RTL_ADDR.addr_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[0]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(0),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[1]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(1),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[2]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(2),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[3]_i_1_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(3),
R => SR(0)
);
\USE_RTL_ADDR.addr_q_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => addr_q,
D => \USE_RTL_ADDR.addr_q[4]_i_2_n_0\,
Q => \USE_RTL_ADDR.addr_q_reg__0\(4),
R => SR(0)
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(0),
Q => \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => buffer_Full_q,
I1 => sr_arvalid,
I2 => cmd_push_block,
O => valid_Write
);
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(10),
Q => \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(11),
Q => \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(12),
Q => \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(13),
Q => \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(14),
Q => \USE_RTL_FIFO.data_srl_reg[31][14]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(15),
Q => \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(16),
Q => \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(17),
Q => \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(1),
Q => \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(18),
Q => \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(19),
Q => \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(20),
Q => \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(21),
Q => \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(22),
Q => \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(23),
Q => \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(24),
Q => \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(25),
Q => \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(26),
Q => \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(27),
Q => \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(2),
Q => \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(28),
Q => \USE_RTL_FIFO.data_srl_reg[31][30]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(29),
Q => \USE_RTL_FIFO.data_srl_reg[31][31]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(30),
Q => \USE_RTL_FIFO.data_srl_reg[31][32]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(31),
Q => \USE_RTL_FIFO.data_srl_reg[31][33]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][34]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(32),
Q => \USE_RTL_FIFO.data_srl_reg[31][34]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][34]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(3),
Q => \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(4),
Q => \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(5),
Q => \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(6),
Q => \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(7),
Q => \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(8),
Q => \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => \USE_RTL_ADDR.addr_q_reg__0\(4 downto 0),
CE => valid_Write,
CLK => \out\,
D => \in\(9),
Q => \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0\,
Q31 => \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\USE_RTL_LENGTH.first_mi_word_q_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^use_rtl_length.length_counter_q_reg[7]_0\,
I1 => mr_rvalid,
O => \USE_RTL_LENGTH.length_counter_q_reg[7]\
);
\USE_RTL_LENGTH.first_mi_word_q_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF0001"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\,
I1 => use_wrap_buffer,
I2 => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
I3 => wrap_buffer_available,
I4 => \m_payload_i[130]_i_4_n_0\,
I5 => \m_payload_i[130]_i_3_n_0\,
O => \^use_rtl_length.length_counter_q_reg[7]_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FFFFFF00040000"
)
port map (
I0 => cmd_push_block,
I1 => sr_arvalid,
I2 => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\,
I3 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I4 => data_Exists_I,
I5 => buffer_Full_q,
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7FFFFF"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(4),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(3),
O => \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0\
);
\USE_RTL_VALID_WRITE.buffer_Full_q_reg\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0\,
Q => buffer_Full_q,
R => SR(0)
);
cmd_push_block_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => buffer_Full_q,
I1 => cmd_push_block,
I2 => sr_arvalid,
I3 => m_axi_arready,
O => cmd_push_block0
);
\current_word_1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(0),
I1 => rd_cmd_next_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(0),
O => \^current_word_1_reg[3]\(0)
);
\current_word_1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(1),
I1 => rd_cmd_next_word(1),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(1),
O => \^current_word_1_reg[3]\(1)
);
\current_word_1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(2),
I1 => \^q\(8),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(2),
O => \^current_word_1_reg[3]\(2)
);
\current_word_1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => rd_cmd_mask(3),
I1 => \^q\(9),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(3),
O => \^current_word_1_reg[3]\(3)
);
data_Exists_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"C4C4C4C4C4CFC4C4"
)
port map (
I0 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_2_n_0\,
I1 => data_Exists_I,
I2 => data_Exists_I_i_2_n_0,
I3 => buffer_Full_q,
I4 => sr_arvalid,
I5 => cmd_push_block,
O => next_Data_Exists
);
data_Exists_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \USE_RTL_ADDR.addr_q_reg__0\(2),
I1 => \USE_RTL_ADDR.addr_q_reg__0\(1),
I2 => \USE_RTL_ADDR.addr_q_reg__0\(3),
I3 => \USE_RTL_ADDR.addr_q_reg__0\(0),
I4 => \USE_RTL_ADDR.addr_q_reg__0\(4),
O => data_Exists_I_i_2_n_0
);
data_Exists_I_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => next_Data_Exists,
Q => data_Exists_I,
R => SR(0)
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => sr_arvalid,
I1 => cmd_push_block,
I2 => buffer_Full_q,
O => m_axi_arvalid
);
\m_payload_i[130]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444454FFFFFFFF"
)
port map (
I0 => \m_payload_i[130]_i_3_n_0\,
I1 => \m_payload_i[130]_i_4_n_0\,
I2 => wrap_buffer_available_reg,
I3 => use_wrap_buffer,
I4 => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[34]_i_4_n_0\,
I5 => mr_rvalid,
O => E(0)
);
\m_payload_i[130]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_rready,
I1 => \^m_axi_rdata_i_reg[127]\,
O => \m_payload_i[130]_i_3_n_0\
);
\m_payload_i[130]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0100FFFF"
)
port map (
I0 => \^current_word_1_reg[3]\(1),
I1 => \^current_word_1_reg[3]\(2),
I2 => \^current_word_1_reg[3]\(0),
I3 => \m_payload_i[130]_i_6_n_0\,
I4 => rd_cmd_modified,
I5 => \^q\(12),
O => \m_payload_i[130]_i_4_n_0\
);
\m_payload_i[130]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001555155555555"
)
port map (
I0 => rd_cmd_complete_wrap,
I1 => \pre_next_word_1_reg[3]_0\(3),
I2 => \^q\(12),
I3 => first_word,
I4 => \^q\(9),
I5 => rd_cmd_mask(3),
O => \m_payload_i[130]_i_6_n_0\
);
\pre_next_word_1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002AAA2AAA80008"
)
port map (
I0 => rd_cmd_mask(0),
I1 => \pre_next_word_1_reg[3]_0\(0),
I2 => \^q\(12),
I3 => first_word,
I4 => rd_cmd_next_word(0),
I5 => cmd_step(0),
O => D(0)
);
\pre_next_word_1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8882228222288828"
)
port map (
I0 => rd_cmd_mask(1),
I1 => cmd_step(1),
I2 => rd_cmd_next_word(1),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \pre_next_word_1_reg[3]_0\(1),
I5 => \pre_next_word_1[1]_i_2_n_0\,
O => D(1)
);
\pre_next_word_1[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"888A8880"
)
port map (
I0 => cmd_step(0),
I1 => rd_cmd_next_word(0),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(0),
O => \pre_next_word_1[1]_i_2_n_0\
);
\pre_next_word_1[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8882228222288828"
)
port map (
I0 => rd_cmd_mask(2),
I1 => cmd_step(2),
I2 => \^q\(8),
I3 => s_axi_rlast_INST_0_i_10_n_0,
I4 => \pre_next_word_1_reg[3]_0\(2),
I5 => \pre_next_word_1[3]_i_4_n_0\,
O => D(2)
);
\pre_next_word_1[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A880022A"
)
port map (
I0 => rd_cmd_mask(3),
I1 => \pre_next_word_1_reg[2]\,
I2 => \pre_next_word_1[3]_i_4_n_0\,
I3 => cmd_step(2),
I4 => \pre_next_word_1_reg[3]\,
O => D(3)
);
\pre_next_word_1[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEFEEEA888A8880"
)
port map (
I0 => cmd_step(1),
I1 => rd_cmd_next_word(1),
I2 => first_word,
I3 => \^q\(12),
I4 => \pre_next_word_1_reg[3]_0\(1),
I5 => \pre_next_word_1[1]_i_2_n_0\,
O => \pre_next_word_1[3]_i_4_n_0\
);
\s_axi_rdata[31]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005457"
)
port map (
I0 => \^q\(10),
I1 => first_word,
I2 => \^q\(12),
I3 => \current_word_1_reg[3]_1\(2),
I4 => rd_cmd_offset(2),
O => \s_axi_rdata[31]_0\
);
\s_axi_rdata[31]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005457"
)
port map (
I0 => \^q\(11),
I1 => first_word,
I2 => \^q\(12),
I3 => \current_word_1_reg[3]_1\(3),
I4 => rd_cmd_offset(3),
O => \s_axi_rdata[31]\
);
s_axi_rlast_INST_0_i_10: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(12),
I1 => first_word,
O => s_axi_rlast_INST_0_i_10_n_0
);
s_axi_rlast_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47B847B8FFFF"
)
port map (
I0 => \current_word_1_reg[3]_1\(0),
I1 => s_axi_rlast_INST_0_i_10_n_0,
I2 => rd_cmd_first_word(0),
I3 => cmd_last_word(0),
I4 => \current_word_1_reg[2]\,
I5 => cmd_last_word(2),
O => \^first_word_reg_0\
);
s_axi_rlast_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF47B847B8FFFF"
)
port map (
I0 => \current_word_1_reg[3]_1\(1),
I1 => s_axi_rlast_INST_0_i_10_n_0,
I2 => rd_cmd_first_word(1),
I3 => cmd_last_word(1),
I4 => \current_word_1_reg[3]_0\,
I5 => cmd_last_word(3),
O => \^first_word_reg\
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^m_axi_rdata_i_reg[127]\,
I1 => mr_rvalid,
I2 => use_wrap_buffer,
O => s_axi_rvalid
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"B000"
)
port map (
I0 => cmd_push_block,
I1 => buffer_Full_q,
I2 => m_axi_arready,
I3 => s_axi_aresetn,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer is
port (
rd_cmd_valid : out STD_LOGIC;
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\USE_RTL_LENGTH.length_counter_q_reg[7]\ : out STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\current_word_1_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 12 downto 0 );
first_word_reg : out STD_LOGIC;
first_word_reg_0 : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
\s_axi_rdata[31]_0\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
\M_AXI_RDATA_I_reg[127]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 1 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
mr_rvalid : in STD_LOGIC;
wrap_buffer_available_reg : in STD_LOGIC;
use_wrap_buffer : in STD_LOGIC;
wrap_buffer_available : in STD_LOGIC;
\USE_RTL_LENGTH.length_counter_q_reg[1]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
\pre_next_word_1_reg[2]\ : in STD_LOGIC;
\pre_next_word_1_reg[3]\ : in STD_LOGIC;
\pre_next_word_1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_word : in STD_LOGIC;
sr_arvalid : in STD_LOGIC;
use_wrap_buffer_reg : in STD_LOGIC;
\current_word_1_reg[3]_0\ : in STD_LOGIC;
\current_word_1_reg[2]\ : in STD_LOGIC;
\current_word_1_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
first_mi_word_q : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 32 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer : entity is "axi_dwidth_converter_v2_1_11_a_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer is
signal cmd_packed_wrap_i1_carry_n_1 : STD_LOGIC;
signal cmd_packed_wrap_i1_carry_n_2 : STD_LOGIC;
signal cmd_packed_wrap_i1_carry_n_3 : STD_LOGIC;
signal cmd_push_block : STD_LOGIC;
signal cmd_push_block0 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_1 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_2 : STD_LOGIC;
signal sub_sized_wrap0_carry_n_3 : STD_LOGIC;
signal NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_sub_sized_wrap0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\GEN_CMD_QUEUE.cmd_queue\: entity work.system_auto_us_1_generic_baseblocks_v2_1_0_command_fifo
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
\M_AXI_RDATA_I_reg[127]\ => rd_cmd_valid,
\M_AXI_RDATA_I_reg[127]_0\(0) => \M_AXI_RDATA_I_reg[127]\(0),
Q(12 downto 0) => Q(12 downto 0),
SR(0) => SR(0),
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => \USE_RTL_LENGTH.length_counter_q_reg[1]\,
\USE_RTL_LENGTH.length_counter_q_reg[7]\ => \USE_RTL_LENGTH.length_counter_q_reg[7]\,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ => \USE_RTL_LENGTH.length_counter_q_reg[7]_0\,
cmd_push_block => cmd_push_block,
cmd_push_block0 => cmd_push_block0,
\current_word_1_reg[2]\ => \current_word_1_reg[2]\,
\current_word_1_reg[3]\(3 downto 0) => \current_word_1_reg[3]\(3 downto 0),
\current_word_1_reg[3]_0\ => \current_word_1_reg[3]_0\,
\current_word_1_reg[3]_1\(3 downto 0) => \current_word_1_reg[3]_1\(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg => first_word_reg,
first_word_reg_0 => first_word_reg_0,
\in\(32 downto 0) => \in\(32 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[2]\ => \pre_next_word_1_reg[2]\,
\pre_next_word_1_reg[3]\ => \pre_next_word_1_reg[3]\,
\pre_next_word_1_reg[3]_0\(3 downto 0) => \pre_next_word_1_reg[3]_0\(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \s_axi_rdata[31]\,
\s_axi_rdata[31]_0\ => \s_axi_rdata[31]_0\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => s_ready_i_reg,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => use_wrap_buffer_reg,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => wrap_buffer_available_reg
);
cmd_packed_wrap_i1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0),
CO(2) => cmd_packed_wrap_i1_carry_n_1,
CO(1) => cmd_packed_wrap_i1_carry_n_2,
CO(0) => cmd_packed_wrap_i1_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => \m_payload_i_reg[50]\(3 downto 0),
O(3 downto 0) => NLW_cmd_packed_wrap_i1_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0)
);
cmd_push_block_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => cmd_push_block0,
Q => cmd_push_block,
R => SR(0)
);
sub_sized_wrap0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => sub_sized_wrap0_carry_n_1,
CO(1) => sub_sized_wrap0_carry_n_2,
CO(0) => sub_sized_wrap0_carry_n_3,
CYINIT => '1',
DI(3 downto 2) => B"00",
DI(1 downto 0) => DI(1 downto 0),
O(3 downto 0) => NLW_sub_sized_wrap0_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice is
port (
m_axi_rready : out STD_LOGIC;
mr_rvalid : out STD_LOGIC;
\s_axi_rdata[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 130 downto 0 );
\s_axi_rdata[1]\ : out STD_LOGIC;
\s_axi_rdata[2]\ : out STD_LOGIC;
\s_axi_rdata[3]\ : out STD_LOGIC;
\s_axi_rdata[4]\ : out STD_LOGIC;
\s_axi_rdata[5]\ : out STD_LOGIC;
\s_axi_rdata[6]\ : out STD_LOGIC;
\s_axi_rdata[7]\ : out STD_LOGIC;
\s_axi_rdata[8]\ : out STD_LOGIC;
\s_axi_rdata[9]\ : out STD_LOGIC;
\s_axi_rdata[10]\ : out STD_LOGIC;
\s_axi_rdata[11]\ : out STD_LOGIC;
\s_axi_rdata[12]\ : out STD_LOGIC;
\s_axi_rdata[13]\ : out STD_LOGIC;
\s_axi_rdata[14]\ : out STD_LOGIC;
\s_axi_rdata[15]\ : out STD_LOGIC;
\s_axi_rdata[16]\ : out STD_LOGIC;
\s_axi_rdata[17]\ : out STD_LOGIC;
\s_axi_rdata[18]\ : out STD_LOGIC;
\s_axi_rdata[19]\ : out STD_LOGIC;
\s_axi_rdata[20]\ : out STD_LOGIC;
\s_axi_rdata[21]\ : out STD_LOGIC;
\s_axi_rdata[22]\ : out STD_LOGIC;
\s_axi_rdata[23]\ : out STD_LOGIC;
\s_axi_rdata[24]\ : out STD_LOGIC;
\s_axi_rdata[25]\ : out STD_LOGIC;
\s_axi_rdata[26]\ : out STD_LOGIC;
\s_axi_rdata[27]\ : out STD_LOGIC;
\s_axi_rdata[28]\ : out STD_LOGIC;
\s_axi_rdata[29]\ : out STD_LOGIC;
\s_axi_rdata[30]\ : out STD_LOGIC;
\s_axi_rdata[31]\ : out STD_LOGIC;
\out\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ : in STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rvalid : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice is
begin
r_pipe: entity work.\system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
Q(130 downto 0) => Q(130 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\s_axi_rdata[0]\ => \s_axi_rdata[0]\,
\s_axi_rdata[10]\ => \s_axi_rdata[10]\,
\s_axi_rdata[11]\ => \s_axi_rdata[11]\,
\s_axi_rdata[12]\ => \s_axi_rdata[12]\,
\s_axi_rdata[13]\ => \s_axi_rdata[13]\,
\s_axi_rdata[14]\ => \s_axi_rdata[14]\,
\s_axi_rdata[15]\ => \s_axi_rdata[15]\,
\s_axi_rdata[16]\ => \s_axi_rdata[16]\,
\s_axi_rdata[17]\ => \s_axi_rdata[17]\,
\s_axi_rdata[18]\ => \s_axi_rdata[18]\,
\s_axi_rdata[19]\ => \s_axi_rdata[19]\,
\s_axi_rdata[1]\ => \s_axi_rdata[1]\,
\s_axi_rdata[20]\ => \s_axi_rdata[20]\,
\s_axi_rdata[21]\ => \s_axi_rdata[21]\,
\s_axi_rdata[22]\ => \s_axi_rdata[22]\,
\s_axi_rdata[23]\ => \s_axi_rdata[23]\,
\s_axi_rdata[24]\ => \s_axi_rdata[24]\,
\s_axi_rdata[25]\ => \s_axi_rdata[25]\,
\s_axi_rdata[26]\ => \s_axi_rdata[26]\,
\s_axi_rdata[27]\ => \s_axi_rdata[27]\,
\s_axi_rdata[28]\ => \s_axi_rdata[28]\,
\s_axi_rdata[29]\ => \s_axi_rdata[29]\,
\s_axi_rdata[2]\ => \s_axi_rdata[2]\,
\s_axi_rdata[30]\ => \s_axi_rdata[30]\,
\s_axi_rdata[31]\ => \s_axi_rdata[31]\,
\s_axi_rdata[3]\ => \s_axi_rdata[3]\,
\s_axi_rdata[4]\ => \s_axi_rdata[4]\,
\s_axi_rdata[5]\ => \s_axi_rdata[5]\,
\s_axi_rdata[6]\ => \s_axi_rdata[6]\,
\s_axi_rdata[7]\ => \s_axi_rdata[7]\,
\s_axi_rdata[8]\ => \s_axi_rdata[8]\,
\s_axi_rdata[9]\ => \s_axi_rdata[9]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
port (
\aresetn_d_reg[1]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
sr_arvalid : out STD_LOGIC;
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 43 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 32 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 1 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC;
cmd_push_block_reg : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\;
architecture STRUCTURE of \system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\ is
begin
ar_pipe: entity work.system_auto_us_1_axi_register_slice_v2_1_11_axic_register_slice
port map (
CO(0) => CO(0),
D(60 downto 0) => D(60 downto 0),
DI(1 downto 0) => DI(1 downto 0),
Q(43 downto 0) => Q(43 downto 0),
S(3 downto 0) => S(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3 downto 0) => \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3 downto 0),
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]\,
cmd_push_block_reg => cmd_push_block_reg,
\in\(32 downto 0) => \in\(32 downto 0),
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\m_payload_i_reg[50]_0\(0) => \m_payload_i_reg[50]\(0),
\out\ => \out\,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => s_ready_i_reg,
sr_arvalid => sr_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer is
port (
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rready : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 43 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rready : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rlast : in STD_LOGIC;
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
D : in STD_LOGIC_VECTOR ( 60 downto 0 );
s_axi_arvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer : entity is "axi_dwidth_converter_v2_1_11_axi_upsizer";
end system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer is
signal \^m_axi_rlast\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_150\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_151\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\ : STD_LOGIC;
signal \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_19\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_20\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_21\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_22\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_23\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_24\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_25\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_26\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_27\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_28\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_29\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_3\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_30\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_33\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_4\ : STD_LOGIC;
signal \USE_READ.read_addr_inst_n_5\ : STD_LOGIC;
signal cmd_complete_wrap_i : STD_LOGIC;
signal cmd_first_word_i : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_fix_i : STD_LOGIC;
signal cmd_modified_i : STD_LOGIC;
signal cmd_packed_wrap_i : STD_LOGIC;
signal cmd_packed_wrap_i1 : STD_LOGIC;
signal current_word_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal first_mi_word_q : STD_LOGIC;
signal first_word : STD_LOGIC;
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal mr_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mr_rvalid : STD_LOGIC;
signal next_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 26 downto 17 );
signal p_7_in : STD_LOGIC;
signal pre_next_word : STD_LOGIC_VECTOR ( 3 downto 0 );
signal pre_next_word_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_cmd_first_word : STD_LOGIC_VECTOR ( 3 downto 2 );
signal rd_cmd_fix : STD_LOGIC;
signal rd_cmd_next_word : STD_LOGIC_VECTOR ( 3 downto 2 );
signal rd_cmd_valid : STD_LOGIC;
signal si_register_slice_inst_n_0 : STD_LOGIC;
signal si_register_slice_inst_n_1 : STD_LOGIC;
signal si_register_slice_inst_n_100 : STD_LOGIC;
signal si_register_slice_inst_n_101 : STD_LOGIC;
signal si_register_slice_inst_n_102 : STD_LOGIC;
signal si_register_slice_inst_n_103 : STD_LOGIC;
signal si_register_slice_inst_n_3 : STD_LOGIC;
signal si_register_slice_inst_n_4 : STD_LOGIC;
signal si_register_slice_inst_n_5 : STD_LOGIC;
signal si_register_slice_inst_n_6 : STD_LOGIC;
signal si_register_slice_inst_n_73 : STD_LOGIC;
signal si_register_slice_inst_n_74 : STD_LOGIC;
signal si_register_slice_inst_n_75 : STD_LOGIC;
signal si_register_slice_inst_n_76 : STD_LOGIC;
signal si_register_slice_inst_n_77 : STD_LOGIC;
signal si_register_slice_inst_n_78 : STD_LOGIC;
signal si_register_slice_inst_n_79 : STD_LOGIC;
signal si_register_slice_inst_n_90 : STD_LOGIC;
signal si_register_slice_inst_n_91 : STD_LOGIC;
signal si_register_slice_inst_n_92 : STD_LOGIC;
signal si_register_slice_inst_n_93 : STD_LOGIC;
signal si_register_slice_inst_n_98 : STD_LOGIC;
signal si_register_slice_inst_n_99 : STD_LOGIC;
signal sr_arvalid : STD_LOGIC;
signal sub_sized_wrap0 : STD_LOGIC;
signal use_wrap_buffer : STD_LOGIC;
signal wrap_buffer_available : STD_LOGIC;
begin
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst\: entity work.system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice
port map (
E(0) => \USE_READ.read_addr_inst_n_5\,
Q(130) => \^m_axi_rlast\,
Q(129 downto 128) => mr_rresp(1 downto 0),
Q(127) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(126) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(125) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(124) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(123) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(122) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(121) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(120) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(119) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(118) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(117) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(116) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(115) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(114) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(113) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(112) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(111) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(110) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(109) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(108) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(107) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(106) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(105) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(104) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(103) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(102) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(101) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(100) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(99) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(98) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(97) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(96) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(95) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(94) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(93) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(92) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(91) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(90) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(89) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(88) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(87) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(86) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(85) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(84) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(83) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(82) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(81) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(80) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(79) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(78) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(77) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(76) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(75) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(74) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(73) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(72) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(71) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(70) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(69) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(68) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(67) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(66) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(65) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
Q(64) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\,
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_READ.read_addr_inst_n_30\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ => \USE_READ.read_addr_inst_n_29\,
\aresetn_d_reg[0]\ => si_register_slice_inst_n_0,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_1,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\s_axi_rdata[0]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
\s_axi_rdata[10]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143\,
\s_axi_rdata[11]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144\,
\s_axi_rdata[12]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145\,
\s_axi_rdata[13]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146\,
\s_axi_rdata[14]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147\,
\s_axi_rdata[15]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148\,
\s_axi_rdata[16]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149\,
\s_axi_rdata[17]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_150\,
\s_axi_rdata[18]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_151\,
\s_axi_rdata[19]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152\,
\s_axi_rdata[1]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134\,
\s_axi_rdata[20]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153\,
\s_axi_rdata[21]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154\,
\s_axi_rdata[22]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155\,
\s_axi_rdata[23]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156\,
\s_axi_rdata[24]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157\,
\s_axi_rdata[25]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158\,
\s_axi_rdata[26]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159\,
\s_axi_rdata[27]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160\,
\s_axi_rdata[28]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161\,
\s_axi_rdata[29]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162\,
\s_axi_rdata[2]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135\,
\s_axi_rdata[30]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163\,
\s_axi_rdata[31]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164\,
\s_axi_rdata[3]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136\,
\s_axi_rdata[4]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137\,
\s_axi_rdata[5]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138\,
\s_axi_rdata[6]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139\,
\s_axi_rdata[7]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140\,
\s_axi_rdata[8]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141\,
\s_axi_rdata[9]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142\
);
\USE_READ.gen_non_fifo_r_upsizer.read_data_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_r_upsizer
port map (
D(3 downto 0) => pre_next_word(3 downto 0),
E(0) => p_7_in,
\M_AXI_RDATA_I_reg[0]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
Q(130) => \^m_axi_rlast\,
Q(129 downto 128) => mr_rresp(1 downto 0),
Q(127) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6\,
Q(126) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7\,
Q(125) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8\,
Q(124) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9\,
Q(123) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10\,
Q(122) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11\,
Q(121) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12\,
Q(120) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13\,
Q(119) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14\,
Q(118) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15\,
Q(117) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16\,
Q(116) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17\,
Q(115) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18\,
Q(114) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19\,
Q(113) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20\,
Q(112) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21\,
Q(111) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22\,
Q(110) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23\,
Q(109) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24\,
Q(108) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25\,
Q(107) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26\,
Q(106) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27\,
Q(105) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28\,
Q(104) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29\,
Q(103) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30\,
Q(102) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31\,
Q(101) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32\,
Q(100) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33\,
Q(99) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34\,
Q(98) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35\,
Q(97) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36\,
Q(96) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37\,
Q(95) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38\,
Q(94) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39\,
Q(93) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40\,
Q(92) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41\,
Q(91) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42\,
Q(90) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43\,
Q(89) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44\,
Q(88) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45\,
Q(87) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46\,
Q(86) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47\,
Q(85) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48\,
Q(84) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49\,
Q(83) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50\,
Q(82) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51\,
Q(81) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52\,
Q(80) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53\,
Q(79) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54\,
Q(78) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55\,
Q(77) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56\,
Q(76) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57\,
Q(75) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58\,
Q(74) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59\,
Q(73) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60\,
Q(72) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61\,
Q(71) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62\,
Q(70) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63\,
Q(69) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64\,
Q(68) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65\,
Q(67) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66\,
Q(66) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67\,
Q(65) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68\,
Q(64) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_69\,
Q(63) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_70\,
Q(62) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_71\,
Q(61) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_72\,
Q(60) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_73\,
Q(59) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_74\,
Q(58) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_75\,
Q(57) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_76\,
Q(56) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_77\,
Q(55) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_78\,
Q(54) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_79\,
Q(53) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_80\,
Q(52) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_81\,
Q(51) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_82\,
Q(50) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_83\,
Q(49) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_84\,
Q(48) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_85\,
Q(47) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_86\,
Q(46) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_87\,
Q(45) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_88\,
Q(44) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_89\,
Q(43) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_90\,
Q(42) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_91\,
Q(41) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_92\,
Q(40) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_93\,
Q(39) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_94\,
Q(38) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_95\,
Q(37) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_96\,
Q(36) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_97\,
Q(35) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_98\,
Q(34) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_99\,
Q(33) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_100\,
Q(32) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_101\,
Q(31) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_102\,
Q(30) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_103\,
Q(29) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_104\,
Q(28) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_105\,
Q(27) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_106\,
Q(26) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_107\,
Q(25) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_108\,
Q(24) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_109\,
Q(23) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_110\,
Q(22) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_111\,
Q(21) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_112\,
Q(20) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_113\,
Q(19) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_114\,
Q(18) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_115\,
Q(17) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_116\,
Q(16) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_117\,
Q(15) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_118\,
Q(14) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_119\,
Q(13) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_120\,
Q(12) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_121\,
Q(11) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_122\,
Q(10) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_123\,
Q(9) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_124\,
Q(8) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_125\,
Q(7) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_126\,
Q(6) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_127\,
Q(5) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_128\,
Q(4) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_129\,
Q(3) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_130\,
Q(2) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_131\,
Q(1) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_132\,
Q(0) => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_133\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[14]\(3 downto 0) => next_word(3 downto 0),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]\ => \USE_READ.read_addr_inst_n_30\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[30]\ => \USE_READ.read_addr_inst_n_29\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(12) => rd_cmd_fix,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(11 downto 10) => rd_cmd_first_word(3 downto 2),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(9 downto 8) => rd_cmd_next_word(3 downto 2),
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(7) => \USE_READ.read_addr_inst_n_19\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(6) => \USE_READ.read_addr_inst_n_20\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(5) => \USE_READ.read_addr_inst_n_21\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(4) => \USE_READ.read_addr_inst_n_22\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(3) => \USE_READ.read_addr_inst_n_23\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(2) => \USE_READ.read_addr_inst_n_24\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(1) => \USE_READ.read_addr_inst_n_25\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[34]\(0) => \USE_READ.read_addr_inst_n_26\,
\USE_RTL_ADDR.addr_q_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\,
\current_word_1_reg[0]_0\ => \USE_READ.read_addr_inst_n_28\,
\current_word_1_reg[1]_0\ => \USE_READ.read_addr_inst_n_27\,
\current_word_1_reg[3]_0\(3 downto 0) => pre_next_word_1(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\,
first_word_reg_1(3 downto 0) => current_word_1(3 downto 0),
first_word_reg_2 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\,
\m_payload_i_reg[0]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_2\,
\m_payload_i_reg[10]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_143\,
\m_payload_i_reg[11]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_144\,
\m_payload_i_reg[12]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_145\,
\m_payload_i_reg[130]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\,
\m_payload_i_reg[13]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_146\,
\m_payload_i_reg[14]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_147\,
\m_payload_i_reg[15]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_148\,
\m_payload_i_reg[16]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_149\,
\m_payload_i_reg[17]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_150\,
\m_payload_i_reg[18]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_151\,
\m_payload_i_reg[19]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_152\,
\m_payload_i_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_134\,
\m_payload_i_reg[20]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_153\,
\m_payload_i_reg[21]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_154\,
\m_payload_i_reg[22]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_155\,
\m_payload_i_reg[23]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_156\,
\m_payload_i_reg[24]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_157\,
\m_payload_i_reg[25]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_158\,
\m_payload_i_reg[26]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_159\,
\m_payload_i_reg[27]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_160\,
\m_payload_i_reg[28]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_161\,
\m_payload_i_reg[29]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_162\,
\m_payload_i_reg[2]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_135\,
\m_payload_i_reg[30]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_163\,
\m_payload_i_reg[31]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_164\,
\m_payload_i_reg[3]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_136\,
\m_payload_i_reg[4]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_137\,
\m_payload_i_reg[5]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_138\,
\m_payload_i_reg[6]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_139\,
\m_payload_i_reg[7]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_140\,
\m_payload_i_reg[8]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_141\,
\m_payload_i_reg[9]\ => \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_142\,
m_valid_i_reg => \USE_READ.read_addr_inst_n_3\,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[3]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\,
\pre_next_word_1_reg[3]_1\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11\,
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg_0 => \USE_READ.read_addr_inst_n_4\,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg_0 => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12\
);
\USE_READ.read_addr_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_a_upsizer
port map (
CO(0) => sub_sized_wrap0,
D(3 downto 0) => pre_next_word(3 downto 0),
DI(1) => si_register_slice_inst_n_98,
DI(0) => si_register_slice_inst_n_99,
E(0) => \USE_READ.read_addr_inst_n_5\,
\M_AXI_RDATA_I_reg[127]\(0) => p_7_in,
Q(12) => rd_cmd_fix,
Q(11 downto 10) => rd_cmd_first_word(3 downto 2),
Q(9 downto 8) => rd_cmd_next_word(3 downto 2),
Q(7) => \USE_READ.read_addr_inst_n_19\,
Q(6) => \USE_READ.read_addr_inst_n_20\,
Q(5) => \USE_READ.read_addr_inst_n_21\,
Q(4) => \USE_READ.read_addr_inst_n_22\,
Q(3) => \USE_READ.read_addr_inst_n_23\,
Q(2) => \USE_READ.read_addr_inst_n_24\,
Q(1) => \USE_READ.read_addr_inst_n_25\,
Q(0) => \USE_READ.read_addr_inst_n_26\,
S(3) => si_register_slice_inst_n_100,
S(2) => si_register_slice_inst_n_101,
S(1) => si_register_slice_inst_n_102,
S(0) => si_register_slice_inst_n_103,
SR(0) => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0) => cmd_packed_wrap_i1,
\USE_RTL_LENGTH.length_counter_q_reg[1]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_12\,
\USE_RTL_LENGTH.length_counter_q_reg[7]\ => \USE_READ.read_addr_inst_n_3\,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0\ => \USE_READ.read_addr_inst_n_4\,
\current_word_1_reg[2]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_50\,
\current_word_1_reg[3]\(3 downto 0) => next_word(3 downto 0),
\current_word_1_reg[3]_0\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_45\,
\current_word_1_reg[3]_1\(3 downto 0) => current_word_1(3 downto 0),
first_mi_word_q => first_mi_word_q,
first_word => first_word,
first_word_reg => \USE_READ.read_addr_inst_n_27\,
first_word_reg_0 => \USE_READ.read_addr_inst_n_28\,
\in\(32) => cmd_fix_i,
\in\(31) => cmd_modified_i,
\in\(30) => cmd_complete_wrap_i,
\in\(29) => cmd_packed_wrap_i,
\in\(28 downto 25) => cmd_first_word_i(3 downto 0),
\in\(24 downto 15) => p_1_out(26 downto 17),
\in\(14) => si_register_slice_inst_n_73,
\in\(13) => si_register_slice_inst_n_74,
\in\(12) => si_register_slice_inst_n_75,
\in\(11) => si_register_slice_inst_n_76,
\in\(10) => si_register_slice_inst_n_77,
\in\(9) => si_register_slice_inst_n_78,
\in\(8) => si_register_slice_inst_n_79,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[50]\(3) => si_register_slice_inst_n_3,
\m_payload_i_reg[50]\(2) => si_register_slice_inst_n_4,
\m_payload_i_reg[50]\(1) => si_register_slice_inst_n_5,
\m_payload_i_reg[50]\(0) => si_register_slice_inst_n_6,
\m_payload_i_reg[51]\(3) => si_register_slice_inst_n_90,
\m_payload_i_reg[51]\(2) => si_register_slice_inst_n_91,
\m_payload_i_reg[51]\(1) => si_register_slice_inst_n_92,
\m_payload_i_reg[51]\(0) => si_register_slice_inst_n_93,
mr_rvalid => mr_rvalid,
\out\ => \out\,
\pre_next_word_1_reg[2]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_11\,
\pre_next_word_1_reg[3]\ => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_6\,
\pre_next_word_1_reg[3]_0\(3 downto 0) => pre_next_word_1(3 downto 0),
rd_cmd_valid => rd_cmd_valid,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata[31]\ => \USE_READ.read_addr_inst_n_29\,
\s_axi_rdata[31]_0\ => \USE_READ.read_addr_inst_n_30\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_ready_i_reg => \USE_READ.read_addr_inst_n_33\,
sr_arvalid => sr_arvalid,
use_wrap_buffer => use_wrap_buffer,
use_wrap_buffer_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_51\,
wrap_buffer_available => wrap_buffer_available,
wrap_buffer_available_reg => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_52\
);
si_register_slice_inst: entity work.\system_auto_us_1_axi_register_slice_v2_1_11_axi_register_slice__parameterized0\
port map (
CO(0) => sub_sized_wrap0,
D(60 downto 0) => D(60 downto 0),
DI(1) => si_register_slice_inst_n_98,
DI(0) => si_register_slice_inst_n_99,
Q(43 downto 0) => Q(43 downto 0),
S(3) => si_register_slice_inst_n_100,
S(2) => si_register_slice_inst_n_101,
S(1) => si_register_slice_inst_n_102,
S(0) => si_register_slice_inst_n_103,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(3) => si_register_slice_inst_n_3,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(2) => si_register_slice_inst_n_4,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(1) => si_register_slice_inst_n_5,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]\(0) => si_register_slice_inst_n_6,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(3) => si_register_slice_inst_n_90,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(2) => si_register_slice_inst_n_91,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(1) => si_register_slice_inst_n_92,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[31]_0\(0) => si_register_slice_inst_n_93,
\aresetn_d_reg[1]\ => si_register_slice_inst_n_0,
cmd_push_block_reg => \USE_READ.read_addr_inst_n_33\,
\in\(32) => cmd_fix_i,
\in\(31) => cmd_modified_i,
\in\(30) => cmd_complete_wrap_i,
\in\(29) => cmd_packed_wrap_i,
\in\(28 downto 25) => cmd_first_word_i(3 downto 0),
\in\(24 downto 15) => p_1_out(26 downto 17),
\in\(14) => si_register_slice_inst_n_73,
\in\(13) => si_register_slice_inst_n_74,
\in\(12) => si_register_slice_inst_n_75,
\in\(11) => si_register_slice_inst_n_76,
\in\(10) => si_register_slice_inst_n_77,
\in\(9) => si_register_slice_inst_n_78,
\in\(8) => si_register_slice_inst_n_79,
\in\(7 downto 0) => \^m_axi_arlen\(7 downto 0),
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
\m_payload_i_reg[50]\(0) => cmd_packed_wrap_i1,
\out\ => \out\,
s_axi_aresetn => \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_1\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg => si_register_slice_inst_n_1,
sr_arvalid => sr_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1_axi_dwidth_converter_v2_1_11_top is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "artix7";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 4;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 128;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_RATIO : integer;
attribute C_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is "axi_dwidth_converter_v2_1_11_top";
attribute P_AXI3 : integer;
attribute P_AXI3 of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of system_auto_us_1_axi_dwidth_converter_v2_1_11_top : entity is 16;
end system_auto_us_1_axi_dwidth_converter_v2_1_11_top;
architecture STRUCTURE of system_auto_us_1_axi_dwidth_converter_v2_1_11_top is
signal \<const0>\ : STD_LOGIC;
begin
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_wdata(127) <= \<const0>\;
m_axi_wdata(126) <= \<const0>\;
m_axi_wdata(125) <= \<const0>\;
m_axi_wdata(124) <= \<const0>\;
m_axi_wdata(123) <= \<const0>\;
m_axi_wdata(122) <= \<const0>\;
m_axi_wdata(121) <= \<const0>\;
m_axi_wdata(120) <= \<const0>\;
m_axi_wdata(119) <= \<const0>\;
m_axi_wdata(118) <= \<const0>\;
m_axi_wdata(117) <= \<const0>\;
m_axi_wdata(116) <= \<const0>\;
m_axi_wdata(115) <= \<const0>\;
m_axi_wdata(114) <= \<const0>\;
m_axi_wdata(113) <= \<const0>\;
m_axi_wdata(112) <= \<const0>\;
m_axi_wdata(111) <= \<const0>\;
m_axi_wdata(110) <= \<const0>\;
m_axi_wdata(109) <= \<const0>\;
m_axi_wdata(108) <= \<const0>\;
m_axi_wdata(107) <= \<const0>\;
m_axi_wdata(106) <= \<const0>\;
m_axi_wdata(105) <= \<const0>\;
m_axi_wdata(104) <= \<const0>\;
m_axi_wdata(103) <= \<const0>\;
m_axi_wdata(102) <= \<const0>\;
m_axi_wdata(101) <= \<const0>\;
m_axi_wdata(100) <= \<const0>\;
m_axi_wdata(99) <= \<const0>\;
m_axi_wdata(98) <= \<const0>\;
m_axi_wdata(97) <= \<const0>\;
m_axi_wdata(96) <= \<const0>\;
m_axi_wdata(95) <= \<const0>\;
m_axi_wdata(94) <= \<const0>\;
m_axi_wdata(93) <= \<const0>\;
m_axi_wdata(92) <= \<const0>\;
m_axi_wdata(91) <= \<const0>\;
m_axi_wdata(90) <= \<const0>\;
m_axi_wdata(89) <= \<const0>\;
m_axi_wdata(88) <= \<const0>\;
m_axi_wdata(87) <= \<const0>\;
m_axi_wdata(86) <= \<const0>\;
m_axi_wdata(85) <= \<const0>\;
m_axi_wdata(84) <= \<const0>\;
m_axi_wdata(83) <= \<const0>\;
m_axi_wdata(82) <= \<const0>\;
m_axi_wdata(81) <= \<const0>\;
m_axi_wdata(80) <= \<const0>\;
m_axi_wdata(79) <= \<const0>\;
m_axi_wdata(78) <= \<const0>\;
m_axi_wdata(77) <= \<const0>\;
m_axi_wdata(76) <= \<const0>\;
m_axi_wdata(75) <= \<const0>\;
m_axi_wdata(74) <= \<const0>\;
m_axi_wdata(73) <= \<const0>\;
m_axi_wdata(72) <= \<const0>\;
m_axi_wdata(71) <= \<const0>\;
m_axi_wdata(70) <= \<const0>\;
m_axi_wdata(69) <= \<const0>\;
m_axi_wdata(68) <= \<const0>\;
m_axi_wdata(67) <= \<const0>\;
m_axi_wdata(66) <= \<const0>\;
m_axi_wdata(65) <= \<const0>\;
m_axi_wdata(64) <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(15) <= \<const0>\;
m_axi_wstrb(14) <= \<const0>\;
m_axi_wstrb(13) <= \<const0>\;
m_axi_wstrb(12) <= \<const0>\;
m_axi_wstrb(11) <= \<const0>\;
m_axi_wstrb(10) <= \<const0>\;
m_axi_wstrb(9) <= \<const0>\;
m_axi_wstrb(8) <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_wready <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_upsizer.gen_full_upsizer.axi_upsizer_inst\: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_axi_upsizer
port map (
D(60 downto 57) => s_axi_arregion(3 downto 0),
D(56 downto 53) => s_axi_arqos(3 downto 0),
D(52) => s_axi_arlock(0),
D(51 downto 44) => s_axi_arlen(7 downto 0),
D(43 downto 40) => s_axi_arcache(3 downto 0),
D(39 downto 38) => s_axi_arburst(1 downto 0),
D(37 downto 35) => s_axi_arsize(2 downto 0),
D(34 downto 32) => s_axi_arprot(2 downto 0),
D(31 downto 0) => s_axi_araddr(31 downto 0),
Q(43 downto 40) => m_axi_arregion(3 downto 0),
Q(39 downto 36) => m_axi_arqos(3 downto 0),
Q(35) => m_axi_arlock(0),
Q(34 downto 31) => m_axi_arcache(3 downto 0),
Q(30 downto 28) => m_axi_arprot(2 downto 0),
Q(27 downto 0) => m_axi_araddr(31 downto 4),
m_axi_araddr(3 downto 0) => m_axi_araddr(3 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
\out\ => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_auto_us_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_auto_us_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_auto_us_1 : entity is "system_auto_us_1,axi_dwidth_converter_v2_1_11_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_auto_us_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_auto_us_1 : entity is "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4";
end system_auto_us_1;
architecture STRUCTURE of system_auto_us_1 is
signal NLW_inst_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_inst_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 0 );
signal NLW_inst_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 0;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 0;
attribute C_MAX_SPLIT_BEATS : integer;
attribute C_MAX_SPLIT_BEATS of inst : label is 16;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_M_AXI_BYTES_LOG : integer;
attribute C_M_AXI_BYTES_LOG of inst : label is 4;
attribute C_M_AXI_DATA_WIDTH : integer;
attribute C_M_AXI_DATA_WIDTH of inst : label is 128;
attribute C_PACKING_LEVEL : integer;
attribute C_PACKING_LEVEL of inst : label is 1;
attribute C_RATIO : integer;
attribute C_RATIO of inst : label is 0;
attribute C_RATIO_LOG : integer;
attribute C_RATIO_LOG of inst : label is 0;
attribute C_SUPPORTS_ID : integer;
attribute C_SUPPORTS_ID of inst : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_S_AXI_BYTES_LOG : integer;
attribute C_S_AXI_BYTES_LOG of inst : label is 2;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of inst : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_MAX_SPLIT_BEATS : integer;
attribute P_MAX_SPLIT_BEATS of inst : label is 16;
begin
inst: entity work.system_auto_us_1_axi_dwidth_converter_v2_1_11_top
port map (
m_axi_aclk => '0',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => '0',
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => NLW_inst_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_inst_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awvalid => NLW_inst_m_axi_awvalid_UNCONNECTED,
m_axi_bready => NLW_inst_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_bvalid => '0',
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(127 downto 0) => NLW_inst_m_axi_wdata_UNCONNECTED(127 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(15 downto 0) => NLW_inst_m_axi_wstrb_UNCONNECTED(15 downto 0),
m_axi_wvalid => NLW_inst_m_axi_wvalid_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"01",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_inst_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_inst_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_inst_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '1',
s_axi_wready => NLW_inst_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid => '0'
);
end STRUCTURE;
|
apache-2.0
|
b47a70d51759b2dc4eb5a1cce138526a
| 0.54993 | 2.543794 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/SEU_tb.vhd
| 1 | 922 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SEU_tb IS
END SEU_tb;
ARCHITECTURE behavior OF SEU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal imm13 : std_logic_vector(12 downto 0) := (others => '0');
--Outputs
signal SEUimm : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SEU PORT MAP (
imm13 => imm13,
SEUimm => SEUimm
);
-- Stimulus process
stim_proc: process
begin
imm13<="0100101001110";
wait for 20 ns;
imm13<="1011000101011";
wait for 20 ns;
imm13<="0000000000001";
wait for 20 ns;
imm13<="1000000000000";
wait;
end process;
END;
|
mit
|
d7d395e5d627b2d2c4db2d7320d2e169
| 0.575922 | 3.747967 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/alu_shift_unit.vhd
| 3 | 1,193 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Shift_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Shift Unit
-- Operations - Shift Left, Shift Right
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Shift_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
COUNT : in STD_LOGIC_VECTOR (2 downto 0);
OP : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU_Shift_Unit;
architecture Combinational of ALU_Shift_Unit is
signal shift_left, shift_right : std_logic_vector (7 downto 0) := (OTHERS => '0');
begin
shift_left <= to_stdlogicvector(to_bitvector(A) sll conv_integer(COUNT));
shift_right <= to_stdlogicvector(to_bitvector(A) srl conv_integer(COUNT));
RESULT <= shift_left when OP='0' else shift_right;
end Combinational;
|
mit
|
2816d2cce9e8bc40cc5088320d02d492
| 0.618609 | 3.775316 | false | false | false | false |
jeffmagina/ECE368
|
Project1/EXECUTE/ALU/alu_shift_unit.vhd
| 1 | 1,192 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Shift_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Shift Unit
-- Operations - Shift Left, Shift Right
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Shift_Unit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
COUNT : in STD_LOGIC_VECTOR (3 downto 0);
OP : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Shift_Unit;
architecture Combinational of ALU_Shift_Unit is
signal shift_left, shift_right : std_logic_vector (15 downto 0) := (OTHERS => '0');
begin
shift_left <= to_stdlogicvector(to_bitvector(A) sll conv_integer(COUNT));
shift_right <= to_stdlogicvector(to_bitvector(A) srl conv_integer(COUNT));
RESULT <= shift_left when OP='0' else shift_right;
end Combinational;
|
mit
|
703d7882ff4400665ce36c2f668665ee
| 0.619128 | 3.796178 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/CU_tb.vhd
| 1 | 2,210 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CU_tb IS
END CU_tb;
ARCHITECTURE behavior OF CU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CU
PORT(
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal OP : std_logic_vector(1 downto 0) := (others => '0');
signal OP3 : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal ALUOP : std_logic_vector(5 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CU PORT MAP (
OP => OP,
OP3 => OP3,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
---------------Instrucciones Aritmetico Logicas---------------
OP<="10";
OP3<="000001";--0. AND
wait for 20 ns;
OP3<="000101";--1. ANDN
wait for 20 ns;
OP3<="000010";--2. OR
wait for 20 ns;
OP3<="000110";--3. ORN
wait for 20 ns;
OP3<="000011";--4. XOR
wait for 20 ns;
OP3<="000111";--5. XNOR
wait for 20 ns;
OP3<="000000";--6. ADD
wait for 20 ns;
OP3<="000100";--7. SUB
wait for 20 ns;
OP3<="100101";--8. SLL
wait for 20 ns;
OP3<="100110";--9. SRL
wait for 20 ns;
OP3<="100111";--10.SRA
wait for 20 ns;
OP3<="010001";--11. ANDcc
wait for 20 ns;
OP3<="010101";--12. ANDNcc
wait for 20 ns;
OP3<="010010";--13. ORcc
wait for 20 ns;
OP3<="010110";--14. ORNcc
wait for 20 ns;
OP3<="010011";--15. XORcc
wait for 20 ns;
OP3<="010111";--16. XNORcc
wait for 20 ns;
OP3<="010000";--17. ADDcc
wait for 20 ns;
OP3<="001000";--18. ADDX
wait for 20 ns;
OP3<="011000";--19. ADDXcc
wait for 20 ns;
OP3<="010100";--20. SUBcc
wait for 20 ns;
OP3<="001100";--21. SUBX
wait for 20 ns;
OP3<="011100";--22. SUBXcc
wait for 20 ns;
OP3<="111100";--23. SAVE
wait for 20 ns;
OP3<="111101";--24. RESTORE
wait for 20 ns;
-----------------Otras Instrucciones(aun no definidas)-----------------------
OP<="00";
OP3<="010101";
wait;
end process;
END;
|
mit
|
b5b6a8d9bb69ad318a5d5c03e241917e
| 0.541629 | 3.108298 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/system_stub.vhd
| 1 | 1,642 |
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
fpga_0_RS232_USB_RX_pin : in std_logic;
fpga_0_RS232_USB_TX_pin : out std_logic;
fpga_0_LEDs_8Bit_GPIO_IO_O_pin : out std_logic_vector(0 to 7);
fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin : in std_logic_vector(0 to 2);
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
fpga_0_RS232_USB_RX_pin : in std_logic;
fpga_0_RS232_USB_TX_pin : out std_logic;
fpga_0_LEDs_8Bit_GPIO_IO_O_pin : out std_logic_vector(0 to 7);
fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin : in std_logic_vector(0 to 2);
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
fpga_0_RS232_USB_RX_pin => fpga_0_RS232_USB_RX_pin,
fpga_0_RS232_USB_TX_pin => fpga_0_RS232_USB_TX_pin,
fpga_0_LEDs_8Bit_GPIO_IO_O_pin => fpga_0_LEDs_8Bit_GPIO_IO_O_pin,
fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin => fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin,
fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin
);
end architecture STRUCTURE;
|
gpl-2.0
|
3bcf527561ab941f77e547a202591de0
| 0.588916 | 2.806838 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_1_0/system_axi_gpio_1_0_sim_netlist.vhdl
| 1 | 186,871 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:20 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_1_0/system_axi_gpio_1_0_sim_netlist.vhdl
-- Design : system_axi_gpio_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_address_decoder is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[15]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 15 downto 0 );
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 );
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_1_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_1_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\ : STD_LOGIC;
signal \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\ : STD_LOGIC;
signal \^not_dual.gpio_data_out_reg[15]\ : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[0]\ : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[0]\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in_0 : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of intr2bus_wrack_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair3";
begin
\Not_Dual.gpio_Data_Out_reg[15]\ <= \^not_dual.gpio_data_out_reg[15]\;
\ip2bus_data_i_D1_reg[0]\ <= \^ip2bus_data_i_d1_reg[0]\;
\ip_irpt_enable_reg_reg[0]\ <= \^ip_irpt_enable_reg_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ip_irpt_enable_reg_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ip_irpt_enable_reg_reg[0]\,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_10_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_9_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => \^ip2bus_data_i_d1_reg[0]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_7_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => p_6_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_4_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_5_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_4_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_3_in_0,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0\,
Q => p_2_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \^s_axi_arready\,
I2 => \^s_axi_wready\,
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out,
Q => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_16_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_15_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_14_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(3),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_12_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_13_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out,
Q => p_12_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(0),
I4 => \bus2ip_addr_i_reg[8]\(6),
I5 => start2,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out,
Q => p_11_in,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_rd_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FE0000"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => ip2Bus_RdAck_intr_reg_hole_d1,
I4 => \^ip_irpt_enable_reg_reg[0]\,
O => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => intr_wr_ce_or_reduce
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_2_in,
I2 => \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19]\,
I3 => p_14_in,
I4 => p_15_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_12_in,
I1 => p_13_in,
I2 => p_10_in,
I3 => p_11_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_5_in,
I1 => p_7_in,
I2 => p_3_in_0,
I3 => p_4_in,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0\,
I1 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0\,
I2 => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0\,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => ip2Bus_WrAck_intr_reg_hole_d1,
O => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => start2,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(4),
I3 => \bus2ip_addr_i_reg[8]\(5),
I4 => \bus2ip_addr_i_reg[8]\(3),
I5 => \bus2ip_addr_i_reg[8]\(2),
O => pselect_hit_i_1
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => pselect_hit_i_1,
Q => \^not_dual.gpio_data_out_reg[15]\,
R => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(15),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(15),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => GPIO_DBus_i(0)
);
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(5),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(5),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\
);
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(4),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\
);
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\
);
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\
);
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^not_dual.gpio_data_out_reg[15]\,
I1 => GPIO_xferAck_i,
I2 => bus2ip_rnw_i_reg,
I3 => gpio_xferAck_Reg,
O => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(14),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(14),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\
);
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(13),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(13),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\
);
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(12),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(12),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\
);
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(11),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(11),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\
);
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(10),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(10),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\
);
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(9),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(9),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\
);
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(8),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(8),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\
);
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(7),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(7),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\
);
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(6),
I1 => \Not_Dual.gpio_Data_In_reg[0]\(6),
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^not_dual.gpio_data_out_reg[15]\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[15]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => \Not_Dual.gpio_Data_Out_reg[0]\(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(31),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(15),
O => D(15)
);
\Not_Dual.gpio_Data_Out[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(21),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(5),
O => D(5)
);
\Not_Dual.gpio_Data_Out[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(20),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(4),
O => D(4)
);
\Not_Dual.gpio_Data_Out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(19),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(3),
O => D(3)
);
\Not_Dual.gpio_Data_Out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(18),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(2),
O => D(2)
);
\Not_Dual.gpio_Data_Out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(17),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(1),
O => D(1)
);
\Not_Dual.gpio_Data_Out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(16),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(0),
O => D(0)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(30),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(14),
O => D(14)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(29),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(13),
O => D(13)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(28),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(12),
O => D(12)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(27),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(11),
O => D(11)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(26),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(10),
O => D(10)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(25),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(9),
O => D(9)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(24),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(8),
O => D(8)
);
\Not_Dual.gpio_Data_Out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(23),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(7),
O => D(7)
);
\Not_Dual.gpio_Data_Out[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(22),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^not_dual.gpio_data_out_reg[15]\,
I3 => s_axi_wdata(6),
O => D(6)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF01000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^not_dual.gpio_data_out_reg[15]\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => bus2ip_reset,
O => E(0)
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"44444440"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^ip_irpt_enable_reg_reg[0]\,
I2 => p_9_in,
I3 => \^ip2bus_data_i_d1_reg[0]\,
I4 => p_6_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
I4 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => p_0_in(0),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_6_in,
I4 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEAAAAFAAAAAAA"
)
port map (
I0 => ip2bus_data(0),
I1 => p_3_in(0),
I2 => p_1_in(0),
I3 => p_6_in,
I4 => \^ip_irpt_enable_reg_reg[0]\,
I5 => \^ip2bus_data_i_d1_reg[0]\,
O => \ip2bus_data_i_D1_reg[0]_0\(0)
);
\ip_irpt_enable_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_6_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_1_in(0),
O => \ip_irpt_enable_reg_reg[0]_0\
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => p_9_in,
I2 => \^ip_irpt_enable_reg_reg[0]\,
I3 => p_0_in(0),
O => ipif_glbl_irpt_enable_reg_reg
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00FE"
)
port map (
I0 => p_9_in,
I1 => \^ip2bus_data_i_d1_reg[0]\,
I2 => p_6_in,
I3 => \^ip_irpt_enable_reg_reg[0]\,
O => irpt_wrack
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_cdc_sync is
port (
D : out STD_LOGIC_VECTOR ( 15 downto 0 );
scndry_vect_out : out STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_1_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_1_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_10 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_11 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_12 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_13 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_14 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_15 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_8 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_9 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_10 : STD_LOGIC;
signal s_level_out_bus_d2_11 : STD_LOGIC;
signal s_level_out_bus_d2_12 : STD_LOGIC;
signal s_level_out_bus_d2_13 : STD_LOGIC;
signal s_level_out_bus_d2_14 : STD_LOGIC;
signal s_level_out_bus_d2_15 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d2_8 : STD_LOGIC;
signal s_level_out_bus_d2_9 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_10 : STD_LOGIC;
signal s_level_out_bus_d3_11 : STD_LOGIC;
signal s_level_out_bus_d3_12 : STD_LOGIC;
signal s_level_out_bus_d3_13 : STD_LOGIC;
signal s_level_out_bus_d3_14 : STD_LOGIC;
signal s_level_out_bus_d3_15 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
signal s_level_out_bus_d3_8 : STD_LOGIC;
signal s_level_out_bus_d3_9 : STD_LOGIC;
signal \^scndry_vect_out\ : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
scndry_vect_out(15 downto 0) <= \^scndry_vect_out\(15 downto 0);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_10,
Q => s_level_out_bus_d2_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_11,
Q => s_level_out_bus_d2_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_12,
Q => s_level_out_bus_d2_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_13,
Q => s_level_out_bus_d2_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_14,
Q => s_level_out_bus_d2_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_15,
Q => s_level_out_bus_d2_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_8,
Q => s_level_out_bus_d2_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_9,
Q => s_level_out_bus_d2_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_10,
Q => s_level_out_bus_d3_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_11,
Q => s_level_out_bus_d3_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_12,
Q => s_level_out_bus_d3_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_13,
Q => s_level_out_bus_d3_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_14,
Q => s_level_out_bus_d3_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_15,
Q => s_level_out_bus_d3_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_8,
Q => s_level_out_bus_d3_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_9,
Q => s_level_out_bus_d3_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => \^scndry_vect_out\(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_10,
Q => \^scndry_vect_out\(10),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_11,
Q => \^scndry_vect_out\(11),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_12,
Q => \^scndry_vect_out\(12),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_13,
Q => \^scndry_vect_out\(13),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_14,
Q => \^scndry_vect_out\(14),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_15,
Q => \^scndry_vect_out\(15),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => \^scndry_vect_out\(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => \^scndry_vect_out\(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => \^scndry_vect_out\(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => \^scndry_vect_out\(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => \^scndry_vect_out\(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => \^scndry_vect_out\(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => \^scndry_vect_out\(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_8,
Q => \^scndry_vect_out\(8),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_9,
Q => \^scndry_vect_out\(9),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(10),
Q => s_level_out_bus_d1_cdc_to_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(11),
Q => s_level_out_bus_d1_cdc_to_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(12),
Q => s_level_out_bus_d1_cdc_to_12,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(13),
Q => s_level_out_bus_d1_cdc_to_13,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(14),
Q => s_level_out_bus_d1_cdc_to_14,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(15),
Q => s_level_out_bus_d1_cdc_to_15,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(8),
Q => s_level_out_bus_d1_cdc_to_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(9),
Q => s_level_out_bus_d1_cdc_to_9,
R => '0'
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(15),
I1 => \^scndry_vect_out\(15),
O => D(15)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => \^scndry_vect_out\(5),
O => D(5)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => \^scndry_vect_out\(4),
O => D(4)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => \^scndry_vect_out\(3),
O => D(3)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => \^scndry_vect_out\(2),
O => D(2)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => \^scndry_vect_out\(1),
O => D(1)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => \^scndry_vect_out\(0),
O => D(0)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(14),
I1 => \^scndry_vect_out\(14),
O => D(14)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(13),
I1 => \^scndry_vect_out\(13),
O => D(13)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(12),
I1 => \^scndry_vect_out\(12),
O => D(12)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(11),
I1 => \^scndry_vect_out\(11),
O => D(11)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(10),
I1 => \^scndry_vect_out\(10),
O => D(10)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(9),
I1 => \^scndry_vect_out\(9),
O => D(9)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => \^scndry_vect_out\(8),
O => D(8)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => \^scndry_vect_out\(7),
O => D(7)
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => \^scndry_vect_out\(6),
O => D(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
p_3_in : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_Irpt_i : out STD_LOGIC;
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
GPIO_intr : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ : in STD_LOGIC;
p_8_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_interrupt_control : entity is "interrupt_control";
end system_axi_gpio_1_0_interrupt_control;
architecture STRUCTURE of system_axi_gpio_1_0_interrupt_control is
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\ : STD_LOGIC;
signal intr2bus_rdack : STD_LOGIC;
signal intr2bus_wrack : STD_LOGIC;
signal irpt_dly1 : STD_LOGIC;
signal irpt_dly2 : STD_LOGIC;
signal \^irpt_wrack_d1\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_1_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_3_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
irpt_wrack_d1 <= \^irpt_wrack_d1\;
p_0_in(0) <= \^p_0_in\(0);
p_1_in(0) <= \^p_1_in\(0);
p_3_in(0) <= \^p_3_in\(0);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_intr,
Q => irpt_dly1,
S => bus2ip_reset
);
\DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_dly1,
Q => irpt_dly2,
S => bus2ip_reset
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F4F44FF4F4F4"
)
port map (
I0 => irpt_dly2,
I1 => irpt_dly1,
I2 => \^p_3_in\(0),
I3 => p_8_in,
I4 => s_axi_wdata(0),
I5 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^irpt_wrack_d1\,
I1 => Bus_RNW_reg,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0\,
Q => \^p_3_in\(0),
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^p_3_in\(0),
I1 => \^p_1_in\(0),
I2 => \^p_0_in\(0),
O => IP2INTC_Irpt_i
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr2bus_rdack,
R => bus2ip_reset
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr2bus_wrack,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => ip2Bus_RdAck_intr_reg_hole,
I1 => intr2bus_rdack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole,
I1 => intr2bus_wrack,
I2 => bus2ip_rnw,
I3 => GPIO_xferAck_i,
O => ip2bus_wrack_i
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\,
Q => \^p_1_in\(0),
R => bus2ip_reset
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\,
Q => \^p_0_in\(0),
R => bus2ip_reset
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => bus2ip_reset
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => \^irpt_wrack_d1\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_GPIO_Core is
port (
ip2bus_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
GPIO_intr : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[15]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[14]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[13]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[12]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[11]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[10]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[9]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[8]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[7]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[6]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[5]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[4]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[3]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[2]_0\ : in STD_LOGIC;
\Not_Dual.gpio_OE_reg[1]_0\ : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_reset : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC_VECTOR ( 0 to 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 15 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_1_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_1_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal gpio_data_in_xor : STD_LOGIC_VECTOR ( 0 to 15 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 15 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal or_ints : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
Q(15 downto 0) <= \^q\(15 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_12_in,
I1 => p_11_in,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\,
I3 => p_13_in,
I4 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\,
I5 => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\,
O => or_ints
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
I1 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
I2 => p_2_in,
I3 => p_1_in,
I4 => p_3_in,
I5 => p_4_in,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => p_6_in,
I1 => p_5_in,
I2 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\,
I3 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\,
I4 => p_9_in,
I5 => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\,
O => \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0\
);
\Not_Dual.GEN_INTERRUPT.GPIO_intr_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => or_ints,
Q => GPIO_intr,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(0),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(10),
Q => p_9_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(11),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(12),
Q => p_11_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(13),
Q => p_12_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(14),
Q => p_13_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(15),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(1),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(2),
Q => p_1_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(3),
Q => p_2_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(4),
Q => p_3_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(5),
Q => p_4_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(6),
Q => p_5_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(7),
Q => p_6_in,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(8),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8]\,
R => bus2ip_reset
);
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_data_in_xor(9),
Q => \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9]\,
R => bus2ip_reset
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.system_axi_gpio_1_0_cdc_sync
port map (
D(15) => gpio_data_in_xor(0),
D(14) => gpio_data_in_xor(1),
D(13) => gpio_data_in_xor(2),
D(12) => gpio_data_in_xor(3),
D(11) => gpio_data_in_xor(4),
D(10) => gpio_data_in_xor(5),
D(9) => gpio_data_in_xor(6),
D(8) => gpio_data_in_xor(7),
D(7) => gpio_data_in_xor(8),
D(6) => gpio_data_in_xor(9),
D(5) => gpio_data_in_xor(10),
D(4) => gpio_data_in_xor(11),
D(3) => gpio_data_in_xor(12),
D(2) => gpio_data_in_xor(13),
D(1) => gpio_data_in_xor(14),
D(0) => gpio_data_in_xor(15),
Q(15 downto 0) => \^q\(15 downto 0),
gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(15) => gpio_io_i_d2(0),
scndry_vect_out(14) => gpio_io_i_d2(1),
scndry_vect_out(13) => gpio_io_i_d2(2),
scndry_vect_out(12) => gpio_io_i_d2(3),
scndry_vect_out(11) => gpio_io_i_d2(4),
scndry_vect_out(10) => gpio_io_i_d2(5),
scndry_vect_out(9) => gpio_io_i_d2(6),
scndry_vect_out(8) => gpio_io_i_d2(7),
scndry_vect_out(7) => gpio_io_i_d2(8),
scndry_vect_out(6) => gpio_io_i_d2(9),
scndry_vect_out(5) => gpio_io_i_d2(10),
scndry_vect_out(4) => gpio_io_i_d2(11),
scndry_vect_out(3) => gpio_io_i_d2(12),
scndry_vect_out(2) => gpio_io_i_d2(13),
scndry_vect_out(1) => gpio_io_i_d2(14),
scndry_vect_out(0) => gpio_io_i_d2(15)
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus_i(0),
Q => ip2bus_data(15),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[10]_0\,
Q => ip2bus_data(5),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[11]_0\,
Q => ip2bus_data(4),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[12]_0\,
Q => ip2bus_data(3),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[13]_0\,
Q => ip2bus_data(2),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[14]_0\,
Q => ip2bus_data(1),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[15]_0\,
Q => ip2bus_data(0),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[1]_0\,
Q => ip2bus_data(14),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[2]_0\,
Q => ip2bus_data(13),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[3]_0\,
Q => ip2bus_data(12),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[4]_0\,
Q => ip2bus_data(11),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[5]_0\,
Q => ip2bus_data(10),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[6]_0\,
Q => ip2bus_data(9),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[7]_0\,
Q => ip2bus_data(8),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[8]_0\,
Q => ip2bus_data(7),
R => Read_Reg_Rst
);
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE_reg[9]_0\,
Q => ip2bus_data(6),
R => Read_Reg_Rst
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \^q\(15),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(10),
Q => \^q\(5),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(11),
Q => \^q\(4),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(12),
Q => \^q\(3),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(13),
Q => \^q\(2),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(14),
Q => \^q\(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(15),
Q => \^q\(0),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \^q\(14),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \^q\(13),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \^q\(12),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => \^q\(11),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(5),
Q => \^q\(10),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(6),
Q => \^q\(9),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(7),
Q => \^q\(8),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(8),
Q => \^q\(7),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(9),
Q => \^q\(6),
R => '0'
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(15),
Q => gpio_io_o(15),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => gpio_io_o(5),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => gpio_io_o(4),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => gpio_io_o(3),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => gpio_io_o(2),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => gpio_io_o(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => gpio_io_o(0),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(14),
Q => gpio_io_o(14),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(13),
Q => gpio_io_o(13),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(12),
Q => gpio_io_o(12),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(11),
Q => gpio_io_o(11),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(10),
Q => gpio_io_o(10),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(9),
Q => gpio_io_o(9),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => gpio_io_o(8),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(7),
Q => gpio_io_o(7),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => gpio_io_o(6),
R => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(15),
Q => gpio_io_t(15),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(5),
Q => gpio_io_t(5),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(4),
Q => gpio_io_t(4),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(3),
Q => gpio_io_t(3),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(2),
Q => gpio_io_t(2),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(1),
Q => gpio_io_t(1),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(0),
Q => gpio_io_t(0),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(14),
Q => gpio_io_t(14),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(13),
Q => gpio_io_t(13),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(12),
Q => gpio_io_t(12),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(11),
Q => gpio_io_t(11),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(10),
Q => gpio_io_t(10),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(9),
Q => gpio_io_t(9),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(8),
Q => gpio_io_t(8),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(7),
Q => gpio_io_t(7),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(6),
Q => gpio_io_t(6),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => \^gpio_xferack_reg\,
I1 => \^gpio_xferack_i\,
I2 => bus2ip_cs(0),
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_slave_attachment is
port (
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[15]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 15 downto 0 );
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 16 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_1\ : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_1_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_1_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_oe_reg[0]\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 8 downto 2 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair4";
begin
\Not_Dual.gpio_OE_reg[0]\ <= \^not_dual.gpio_oe_reg[0]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_1_0_address_decoder
port map (
D(15 downto 0) => D(15 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\,
\Not_Dual.gpio_Data_In_reg[0]\(15 downto 0) => Q(15 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[15]\ => \Not_Dual.gpio_Data_Out_reg[15]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(6) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(5) => bus2ip_addr(1),
\bus2ip_addr_i_reg[8]\(4) => bus2ip_addr(2),
\bus2ip_addr_i_reg[8]\(3) => bus2ip_addr(3),
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(4),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg => \^not_dual.gpio_oe_reg[0]\,
gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => \ip2bus_data_i_D1_reg[0]\,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(1 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => \ip_irpt_enable_reg_reg[0]\,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]_0\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \p_1_in__0\(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \p_1_in__0\(3)
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \p_1_in__0\(4)
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(3),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(3),
O => \p_1_in__0\(5)
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(4),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(4),
O => \p_1_in__0\(6)
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(5),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(5),
O => \p_1_in__0\(7)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(6),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(6),
O => \p_1_in__0\(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(2),
Q => bus2ip_addr(6),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(3),
Q => bus2ip_addr(5),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(4),
Q => bus2ip_addr(4),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(5),
Q => bus2ip_addr(3),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(6),
Q => bus2ip_addr(2),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(7),
Q => bus2ip_addr(1),
R => bus2ip_reset
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \p_1_in__0\(8),
Q => bus2ip_addr(0),
R => bus2ip_reset
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_oe_reg[0]\,
R => bus2ip_reset
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => bus2ip_reset
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => bus2ip_reset
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => bus2ip_reset
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(0),
Q => s_axi_rdata(0),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(10),
Q => s_axi_rdata(10),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(11),
Q => s_axi_rdata(11),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(12),
Q => s_axi_rdata(12),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(13),
Q => s_axi_rdata(13),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(14),
Q => s_axi_rdata(14),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(15),
Q => s_axi_rdata(15),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(1),
Q => s_axi_rdata(1),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(2),
Q => s_axi_rdata(2),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(16),
Q => s_axi_rdata(16),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(3),
Q => s_axi_rdata(3),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(4),
Q => s_axi_rdata(4),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(5),
Q => s_axi_rdata(5),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(6),
Q => s_axi_rdata(6),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(7),
Q => s_axi_rdata(7),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(8),
Q => s_axi_rdata(8),
R => bus2ip_reset
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[0]_1\(9),
Q => s_axi_rdata(9),
R => bus2ip_reset
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => bus2ip_reset
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => bus2ip_reset
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \p_0_out__0\(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \p_0_out__0\(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(0),
Q => state(0),
R => bus2ip_reset
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \p_0_out__0\(1),
Q => state(1),
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_axi_lite_ipif is
port (
p_8_in : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 15 downto 0 );
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\ip2bus_data_i_D1_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
Read_Reg_Rst : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_rd_ce_or_reduce : out STD_LOGIC;
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ : out STD_LOGIC;
intr_wr_ce_or_reduce : out STD_LOGIC;
\ip_irpt_enable_reg_reg[0]\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 16 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
ip2bus_data : in STD_LOGIC_VECTOR ( 0 to 0 );
p_3_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_1_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_1_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_1_0_slave_attachment
port map (
D(15 downto 0) => D(15 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ => \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ => \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ => \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ => \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ => \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ => \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => \Not_Dual.gpio_Data_Out_reg[0]\(0),
\Not_Dual.gpio_Data_Out_reg[15]\ => bus2ip_cs(0),
\Not_Dual.gpio_OE_reg[0]\ => bus2ip_rnw,
Q(15 downto 0) => Q(15 downto 0),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_reset => bus2ip_reset,
gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(0),
\ip2bus_data_i_D1_reg[0]\ => p_8_in,
\ip2bus_data_i_D1_reg[0]_0\(1 downto 0) => \ip2bus_data_i_D1_reg[0]\(1 downto 0),
\ip2bus_data_i_D1_reg[0]_1\(16 downto 0) => \ip2bus_data_i_D1_reg[0]_0\(16 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => Bus_RNW_reg,
\ip_irpt_enable_reg_reg[0]_0\ => \ip_irpt_enable_reg_reg[0]\,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(0),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(16 downto 0) => s_axi_rdata(16 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_1_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_1_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_1_0_axi_gpio : entity is 16;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_1_0_axi_gpio : entity is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_1_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_1_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_1_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_1_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_1_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_1_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_1_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_1_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_1_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_1_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_24 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_25 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_37 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_38 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_40 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_41 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_51 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_53 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_54 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 15 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 16 to 16 );
signal GPIO_intr : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal IP2INTC_Irpt_i : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\ : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC_VECTOR ( 1 to 1 );
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_reset_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 15 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal interrupt_wrce_strb : STD_LOGIC;
signal intr2bus_rdack0 : STD_LOGIC;
signal intr_rd_ce_or_reduce : STD_LOGIC;
signal intr_wr_ce_or_reduce : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 16 to 31 );
signal ip2bus_data_i : STD_LOGIC_VECTOR ( 31 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal irpt_rdack : STD_LOGIC;
signal irpt_rdack_d1 : STD_LOGIC;
signal irpt_wrack : STD_LOGIC;
signal irpt_wrack_d1 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_0_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_3_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of \INTR_CTRLR_GEN.ip2intc_irpt_reg\ : label is "INTR_LEVEL_HIGH";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(15 downto 0) <= \^gpio_io_t\(15 downto 0);
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15 downto 0) <= \^s_axi_rdata\(15 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_1_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(15) => DBus_Reg(0),
D(14) => DBus_Reg(1),
D(13) => DBus_Reg(2),
D(12) => DBus_Reg(3),
D(11) => DBus_Reg(4),
D(10) => DBus_Reg(5),
D(9) => DBus_Reg(6),
D(8) => DBus_Reg(7),
D(7) => DBus_Reg(8),
D(6) => DBus_Reg(9),
D(5) => DBus_Reg(10),
D(4) => DBus_Reg(11),
D(3) => DBus_Reg(12),
D(2) => DBus_Reg(13),
D(1) => DBus_Reg(14),
D(0) => DBus_Reg(15),
E(0) => AXI_LITE_IPIF_I_n_40,
GPIO_DBus_i(0) => GPIO_DBus_i(16),
GPIO_xferAck_i => GPIO_xferAck_i,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_49,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\ => AXI_LITE_IPIF_I_n_51,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_28,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_27,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_26,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_25,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_24,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]\ => AXI_LITE_IPIF_I_n_38,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]\ => AXI_LITE_IPIF_I_n_37,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]\ => AXI_LITE_IPIF_I_n_36,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]\ => AXI_LITE_IPIF_I_n_35,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]\ => AXI_LITE_IPIF_I_n_34,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]\ => AXI_LITE_IPIF_I_n_33,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]\ => AXI_LITE_IPIF_I_n_32,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_31,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]\ => AXI_LITE_IPIF_I_n_30,
\Not_Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_41,
Q(15) => gpio_Data_In(0),
Q(14) => gpio_Data_In(1),
Q(13) => gpio_Data_In(2),
Q(12) => gpio_Data_In(3),
Q(11) => gpio_Data_In(4),
Q(10) => gpio_Data_In(5),
Q(9) => gpio_Data_In(6),
Q(8) => gpio_Data_In(7),
Q(7) => gpio_Data_In(8),
Q(6) => gpio_Data_In(9),
Q(5) => gpio_Data_In(10),
Q(4) => gpio_Data_In(11),
Q(3) => gpio_Data_In(12),
Q(2) => gpio_Data_In(13),
Q(1) => gpio_Data_In(14),
Q(0) => gpio_Data_In(15),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(15 downto 0) => \^gpio_io_t\(15 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_rd_ce_or_reduce => intr_rd_ce_or_reduce,
intr_wr_ce_or_reduce => intr_wr_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_data(0) => ip2bus_data(31),
\ip2bus_data_i_D1_reg[0]\(1) => p_0_out(0),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i(31),
\ip2bus_data_i_D1_reg[0]_0\(16) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]_0\(15) => ip2bus_data_i_D1(16),
\ip2bus_data_i_D1_reg[0]_0\(14) => ip2bus_data_i_D1(17),
\ip2bus_data_i_D1_reg[0]_0\(13) => ip2bus_data_i_D1(18),
\ip2bus_data_i_D1_reg[0]_0\(12) => ip2bus_data_i_D1(19),
\ip2bus_data_i_D1_reg[0]_0\(11) => ip2bus_data_i_D1(20),
\ip2bus_data_i_D1_reg[0]_0\(10) => ip2bus_data_i_D1(21),
\ip2bus_data_i_D1_reg[0]_0\(9) => ip2bus_data_i_D1(22),
\ip2bus_data_i_D1_reg[0]_0\(8) => ip2bus_data_i_D1(23),
\ip2bus_data_i_D1_reg[0]_0\(7) => ip2bus_data_i_D1(24),
\ip2bus_data_i_D1_reg[0]_0\(6) => ip2bus_data_i_D1(25),
\ip2bus_data_i_D1_reg[0]_0\(5) => ip2bus_data_i_D1(26),
\ip2bus_data_i_D1_reg[0]_0\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[0]_0\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[0]_0\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[0]_0\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]_0\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
\ip_irpt_enable_reg_reg[0]\ => AXI_LITE_IPIF_I_n_53,
ipif_glbl_irpt_enable_reg_reg => AXI_LITE_IPIF_I_n_54,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(16) => \^s_axi_rdata\(31),
s_axi_rdata(15 downto 0) => \^s_axi_rdata\(15 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\INTR_CTRLR_GEN.INTERRUPT_CONTROL_I\: entity work.system_axi_gpio_1_0_interrupt_control
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\ => AXI_LITE_IPIF_I_n_54,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\ => AXI_LITE_IPIF_I_n_53,
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
IP2INTC_Irpt_i => IP2INTC_Irpt_i,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(31),
p_1_in(0) => p_1_in(0),
p_3_in(0) => p_3_in(0),
p_8_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(0)
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_49,
Q => ip2Bus_RdAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => AXI_LITE_IPIF_I_n_51,
Q => ip2Bus_WrAck_intr_reg_hole,
R => bus2ip_reset
);
\INTR_CTRLR_GEN.ip2intc_irpt_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2INTC_Irpt_i,
Q => ip2intc_irpt,
R => bus2ip_reset
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
bus2ip_reset_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => bus2ip_reset_i_1_n_0
);
bus2ip_reset_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset_i_1_n_0,
Q => bus2ip_reset,
R => '0'
);
gpio_core_1: entity work.system_axi_gpio_1_0_GPIO_Core
port map (
D(15) => DBus_Reg(0),
D(14) => DBus_Reg(1),
D(13) => DBus_Reg(2),
D(12) => DBus_Reg(3),
D(11) => DBus_Reg(4),
D(10) => DBus_Reg(5),
D(9) => DBus_Reg(6),
D(8) => DBus_Reg(7),
D(7) => DBus_Reg(8),
D(6) => DBus_Reg(9),
D(5) => DBus_Reg(10),
D(4) => DBus_Reg(11),
D(3) => DBus_Reg(12),
D(2) => DBus_Reg(13),
D(1) => DBus_Reg(14),
D(0) => DBus_Reg(15),
E(0) => AXI_LITE_IPIF_I_n_41,
GPIO_DBus_i(0) => GPIO_DBus_i(16),
GPIO_intr => GPIO_intr,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.gpio_OE_reg[10]_0\ => AXI_LITE_IPIF_I_n_29,
\Not_Dual.gpio_OE_reg[11]_0\ => AXI_LITE_IPIF_I_n_28,
\Not_Dual.gpio_OE_reg[12]_0\ => AXI_LITE_IPIF_I_n_27,
\Not_Dual.gpio_OE_reg[13]_0\ => AXI_LITE_IPIF_I_n_26,
\Not_Dual.gpio_OE_reg[14]_0\ => AXI_LITE_IPIF_I_n_25,
\Not_Dual.gpio_OE_reg[15]_0\ => AXI_LITE_IPIF_I_n_24,
\Not_Dual.gpio_OE_reg[1]_0\ => AXI_LITE_IPIF_I_n_38,
\Not_Dual.gpio_OE_reg[2]_0\ => AXI_LITE_IPIF_I_n_37,
\Not_Dual.gpio_OE_reg[3]_0\ => AXI_LITE_IPIF_I_n_36,
\Not_Dual.gpio_OE_reg[4]_0\ => AXI_LITE_IPIF_I_n_35,
\Not_Dual.gpio_OE_reg[5]_0\ => AXI_LITE_IPIF_I_n_34,
\Not_Dual.gpio_OE_reg[6]_0\ => AXI_LITE_IPIF_I_n_33,
\Not_Dual.gpio_OE_reg[7]_0\ => AXI_LITE_IPIF_I_n_32,
\Not_Dual.gpio_OE_reg[8]_0\ => AXI_LITE_IPIF_I_n_31,
\Not_Dual.gpio_OE_reg[9]_0\ => AXI_LITE_IPIF_I_n_30,
Q(15) => gpio_Data_In(0),
Q(14) => gpio_Data_In(1),
Q(13) => gpio_Data_In(2),
Q(12) => gpio_Data_In(3),
Q(11) => gpio_Data_In(4),
Q(10) => gpio_Data_In(5),
Q(9) => gpio_Data_In(6),
Q(8) => gpio_Data_In(7),
Q(7) => gpio_Data_In(8),
Q(6) => gpio_Data_In(9),
Q(5) => gpio_Data_In(10),
Q(4) => gpio_Data_In(11),
Q(3) => gpio_Data_In(12),
Q(2) => gpio_Data_In(13),
Q(1) => gpio_Data_In(14),
Q(0) => gpio_Data_In(15),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs(0) => bus2ip_cs(1),
bus2ip_reset => bus2ip_reset,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_40,
gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0),
gpio_io_o(15 downto 0) => gpio_io_o(15 downto 0),
gpio_io_t(15 downto 0) => \^gpio_io_t\(15 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_data(15) => ip2bus_data(16),
ip2bus_data(14) => ip2bus_data(17),
ip2bus_data(13) => ip2bus_data(18),
ip2bus_data(12) => ip2bus_data(19),
ip2bus_data(11) => ip2bus_data(20),
ip2bus_data(10) => ip2bus_data(21),
ip2bus_data(9) => ip2bus_data(22),
ip2bus_data(8) => ip2bus_data(23),
ip2bus_data(7) => ip2bus_data(24),
ip2bus_data(6) => ip2bus_data(25),
ip2bus_data(5) => ip2bus_data(26),
ip2bus_data(4) => ip2bus_data(27),
ip2bus_data(3) => ip2bus_data(28),
ip2bus_data(2) => ip2bus_data(29),
ip2bus_data(1) => ip2bus_data(30),
ip2bus_data(0) => ip2bus_data(31),
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(16),
Q => ip2bus_data_i_D1(16),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(17),
Q => ip2bus_data_i_D1(17),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(18),
Q => ip2bus_data_i_D1(18),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(19),
Q => ip2bus_data_i_D1(19),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(20),
Q => ip2bus_data_i_D1(20),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(21),
Q => ip2bus_data_i_D1(21),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(22),
Q => ip2bus_data_i_D1(22),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(23),
Q => ip2bus_data_i_D1(23),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data_i(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_1_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_1_0 : entity is "system_axi_gpio_1_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_1_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_1_0;
architecture STRUCTURE of system_axi_gpio_1_0 is
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 16;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 1;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_1_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(15 downto 0) => gpio_io_i(15 downto 0),
gpio_io_o(15 downto 0) => gpio_io_o(15 downto 0),
gpio_io_t(15 downto 0) => gpio_io_t(15 downto 0),
ip2intc_irpt => ip2intc_irpt,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
dd9f7da2f038c73abf3c2ddaf0e21558
| 0.582375 | 2.549991 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_mdm_1_0/sim/system_mdm_1_0.vhd
| 1 | 95,781 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mdm:3.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mdm_v3_2_8;
USE mdm_v3_2_8.MDM;
ENTITY system_mdm_1_0 IS
PORT (
Debug_SYS_Rst : OUT STD_LOGIC;
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Disable_0 : OUT STD_LOGIC
);
END system_mdm_1_0;
ARCHITECTURE system_mdm_1_0_arch OF system_mdm_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_mdm_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT MDM IS
GENERIC (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_USE_BSCAN : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_INTERCONNECT : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_DBG_REG_ACCESS : INTEGER;
C_DBG_MEM_ACCESS : INTEGER;
C_USE_CROSS_TRIGGER : INTEGER;
C_TRACE_OUTPUT : INTEGER;
C_TRACE_DATA_WIDTH : INTEGER;
C_TRACE_CLK_FREQ_HZ : INTEGER;
C_TRACE_CLK_OUT_PHASE : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_THREAD_ID_WIDTH : INTEGER;
C_DATA_SIZE : INTEGER;
C_M_AXIS_DATA_WIDTH : INTEGER;
C_M_AXIS_ID_WIDTH : INTEGER
);
PORT (
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
Interrupt : OUT STD_LOGIC;
Ext_BRK : OUT STD_LOGIC;
Ext_NM_BRK : OUT STD_LOGIC;
Debug_SYS_Rst : OUT STD_LOGIC;
Trig_In_0 : IN STD_LOGIC;
Trig_Ack_In_0 : OUT STD_LOGIC;
Trig_Out_0 : OUT STD_LOGIC;
Trig_Ack_Out_0 : IN STD_LOGIC;
Trig_In_1 : IN STD_LOGIC;
Trig_Ack_In_1 : OUT STD_LOGIC;
Trig_Out_1 : OUT STD_LOGIC;
Trig_Ack_Out_1 : IN STD_LOGIC;
Trig_In_2 : IN STD_LOGIC;
Trig_Ack_In_2 : OUT STD_LOGIC;
Trig_Out_2 : OUT STD_LOGIC;
Trig_Ack_Out_2 : IN STD_LOGIC;
Trig_In_3 : IN STD_LOGIC;
Trig_Ack_In_3 : OUT STD_LOGIC;
Trig_Out_3 : OUT STD_LOGIC;
Trig_Ack_Out_3 : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC;
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC;
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC;
LMB_Data_Addr_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_0 : OUT STD_LOGIC;
LMB_Ready_0 : IN STD_LOGIC;
LMB_Byte_Enable_0 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_0 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_0 : OUT STD_LOGIC;
LMB_Write_Strobe_0 : OUT STD_LOGIC;
LMB_CE_0 : IN STD_LOGIC;
LMB_UE_0 : IN STD_LOGIC;
LMB_Wait_0 : IN STD_LOGIC;
LMB_Data_Addr_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_1 : OUT STD_LOGIC;
LMB_Ready_1 : IN STD_LOGIC;
LMB_Byte_Enable_1 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_1 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_1 : OUT STD_LOGIC;
LMB_Write_Strobe_1 : OUT STD_LOGIC;
LMB_CE_1 : IN STD_LOGIC;
LMB_UE_1 : IN STD_LOGIC;
LMB_Wait_1 : IN STD_LOGIC;
LMB_Data_Addr_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_2 : OUT STD_LOGIC;
LMB_Ready_2 : IN STD_LOGIC;
LMB_Byte_Enable_2 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_2 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_2 : OUT STD_LOGIC;
LMB_Write_Strobe_2 : OUT STD_LOGIC;
LMB_CE_2 : IN STD_LOGIC;
LMB_UE_2 : IN STD_LOGIC;
LMB_Wait_2 : IN STD_LOGIC;
LMB_Data_Addr_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_3 : OUT STD_LOGIC;
LMB_Ready_3 : IN STD_LOGIC;
LMB_Byte_Enable_3 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_3 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_3 : OUT STD_LOGIC;
LMB_Write_Strobe_3 : OUT STD_LOGIC;
LMB_CE_3 : IN STD_LOGIC;
LMB_UE_3 : IN STD_LOGIC;
LMB_Wait_3 : IN STD_LOGIC;
LMB_Data_Addr_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_4 : OUT STD_LOGIC;
LMB_Ready_4 : IN STD_LOGIC;
LMB_Byte_Enable_4 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_4 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_4 : OUT STD_LOGIC;
LMB_Write_Strobe_4 : OUT STD_LOGIC;
LMB_CE_4 : IN STD_LOGIC;
LMB_UE_4 : IN STD_LOGIC;
LMB_Wait_4 : IN STD_LOGIC;
LMB_Data_Addr_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_5 : OUT STD_LOGIC;
LMB_Ready_5 : IN STD_LOGIC;
LMB_Byte_Enable_5 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_5 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_5 : OUT STD_LOGIC;
LMB_Write_Strobe_5 : OUT STD_LOGIC;
LMB_CE_5 : IN STD_LOGIC;
LMB_UE_5 : IN STD_LOGIC;
LMB_Wait_5 : IN STD_LOGIC;
LMB_Data_Addr_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_6 : OUT STD_LOGIC;
LMB_Ready_6 : IN STD_LOGIC;
LMB_Byte_Enable_6 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_6 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_6 : OUT STD_LOGIC;
LMB_Write_Strobe_6 : OUT STD_LOGIC;
LMB_CE_6 : IN STD_LOGIC;
LMB_UE_6 : IN STD_LOGIC;
LMB_Wait_6 : IN STD_LOGIC;
LMB_Data_Addr_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_7 : OUT STD_LOGIC;
LMB_Ready_7 : IN STD_LOGIC;
LMB_Byte_Enable_7 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_7 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_7 : OUT STD_LOGIC;
LMB_Write_Strobe_7 : OUT STD_LOGIC;
LMB_CE_7 : IN STD_LOGIC;
LMB_UE_7 : IN STD_LOGIC;
LMB_Wait_7 : IN STD_LOGIC;
LMB_Data_Addr_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_8 : OUT STD_LOGIC;
LMB_Ready_8 : IN STD_LOGIC;
LMB_Byte_Enable_8 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_8 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_8 : OUT STD_LOGIC;
LMB_Write_Strobe_8 : OUT STD_LOGIC;
LMB_CE_8 : IN STD_LOGIC;
LMB_UE_8 : IN STD_LOGIC;
LMB_Wait_8 : IN STD_LOGIC;
LMB_Data_Addr_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_9 : OUT STD_LOGIC;
LMB_Ready_9 : IN STD_LOGIC;
LMB_Byte_Enable_9 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_9 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_9 : OUT STD_LOGIC;
LMB_Write_Strobe_9 : OUT STD_LOGIC;
LMB_CE_9 : IN STD_LOGIC;
LMB_UE_9 : IN STD_LOGIC;
LMB_Wait_9 : IN STD_LOGIC;
LMB_Data_Addr_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_10 : OUT STD_LOGIC;
LMB_Ready_10 : IN STD_LOGIC;
LMB_Byte_Enable_10 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_10 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_10 : OUT STD_LOGIC;
LMB_Write_Strobe_10 : OUT STD_LOGIC;
LMB_CE_10 : IN STD_LOGIC;
LMB_UE_10 : IN STD_LOGIC;
LMB_Wait_10 : IN STD_LOGIC;
LMB_Data_Addr_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_11 : OUT STD_LOGIC;
LMB_Ready_11 : IN STD_LOGIC;
LMB_Byte_Enable_11 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_11 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_11 : OUT STD_LOGIC;
LMB_Write_Strobe_11 : OUT STD_LOGIC;
LMB_CE_11 : IN STD_LOGIC;
LMB_UE_11 : IN STD_LOGIC;
LMB_Wait_11 : IN STD_LOGIC;
LMB_Data_Addr_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_12 : OUT STD_LOGIC;
LMB_Ready_12 : IN STD_LOGIC;
LMB_Byte_Enable_12 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_12 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_12 : OUT STD_LOGIC;
LMB_Write_Strobe_12 : OUT STD_LOGIC;
LMB_CE_12 : IN STD_LOGIC;
LMB_UE_12 : IN STD_LOGIC;
LMB_Wait_12 : IN STD_LOGIC;
LMB_Data_Addr_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_13 : OUT STD_LOGIC;
LMB_Ready_13 : IN STD_LOGIC;
LMB_Byte_Enable_13 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_13 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_13 : OUT STD_LOGIC;
LMB_Write_Strobe_13 : OUT STD_LOGIC;
LMB_CE_13 : IN STD_LOGIC;
LMB_UE_13 : IN STD_LOGIC;
LMB_Wait_13 : IN STD_LOGIC;
LMB_Data_Addr_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_14 : OUT STD_LOGIC;
LMB_Ready_14 : IN STD_LOGIC;
LMB_Byte_Enable_14 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_14 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_14 : OUT STD_LOGIC;
LMB_Write_Strobe_14 : OUT STD_LOGIC;
LMB_CE_14 : IN STD_LOGIC;
LMB_UE_14 : IN STD_LOGIC;
LMB_Wait_14 : IN STD_LOGIC;
LMB_Data_Addr_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_15 : OUT STD_LOGIC;
LMB_Ready_15 : IN STD_LOGIC;
LMB_Byte_Enable_15 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_15 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_15 : OUT STD_LOGIC;
LMB_Write_Strobe_15 : OUT STD_LOGIC;
LMB_CE_15 : IN STD_LOGIC;
LMB_UE_15 : IN STD_LOGIC;
LMB_Wait_15 : IN STD_LOGIC;
LMB_Data_Addr_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_16 : OUT STD_LOGIC;
LMB_Ready_16 : IN STD_LOGIC;
LMB_Byte_Enable_16 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_16 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_16 : OUT STD_LOGIC;
LMB_Write_Strobe_16 : OUT STD_LOGIC;
LMB_CE_16 : IN STD_LOGIC;
LMB_UE_16 : IN STD_LOGIC;
LMB_Wait_16 : IN STD_LOGIC;
LMB_Data_Addr_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_17 : OUT STD_LOGIC;
LMB_Ready_17 : IN STD_LOGIC;
LMB_Byte_Enable_17 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_17 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_17 : OUT STD_LOGIC;
LMB_Write_Strobe_17 : OUT STD_LOGIC;
LMB_CE_17 : IN STD_LOGIC;
LMB_UE_17 : IN STD_LOGIC;
LMB_Wait_17 : IN STD_LOGIC;
LMB_Data_Addr_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_18 : OUT STD_LOGIC;
LMB_Ready_18 : IN STD_LOGIC;
LMB_Byte_Enable_18 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_18 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_18 : OUT STD_LOGIC;
LMB_Write_Strobe_18 : OUT STD_LOGIC;
LMB_CE_18 : IN STD_LOGIC;
LMB_UE_18 : IN STD_LOGIC;
LMB_Wait_18 : IN STD_LOGIC;
LMB_Data_Addr_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_19 : OUT STD_LOGIC;
LMB_Ready_19 : IN STD_LOGIC;
LMB_Byte_Enable_19 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_19 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_19 : OUT STD_LOGIC;
LMB_Write_Strobe_19 : OUT STD_LOGIC;
LMB_CE_19 : IN STD_LOGIC;
LMB_UE_19 : IN STD_LOGIC;
LMB_Wait_19 : IN STD_LOGIC;
LMB_Data_Addr_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_20 : OUT STD_LOGIC;
LMB_Ready_20 : IN STD_LOGIC;
LMB_Byte_Enable_20 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_20 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_20 : OUT STD_LOGIC;
LMB_Write_Strobe_20 : OUT STD_LOGIC;
LMB_CE_20 : IN STD_LOGIC;
LMB_UE_20 : IN STD_LOGIC;
LMB_Wait_20 : IN STD_LOGIC;
LMB_Data_Addr_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_21 : OUT STD_LOGIC;
LMB_Ready_21 : IN STD_LOGIC;
LMB_Byte_Enable_21 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_21 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_21 : OUT STD_LOGIC;
LMB_Write_Strobe_21 : OUT STD_LOGIC;
LMB_CE_21 : IN STD_LOGIC;
LMB_UE_21 : IN STD_LOGIC;
LMB_Wait_21 : IN STD_LOGIC;
LMB_Data_Addr_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_22 : OUT STD_LOGIC;
LMB_Ready_22 : IN STD_LOGIC;
LMB_Byte_Enable_22 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_22 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_22 : OUT STD_LOGIC;
LMB_Write_Strobe_22 : OUT STD_LOGIC;
LMB_CE_22 : IN STD_LOGIC;
LMB_UE_22 : IN STD_LOGIC;
LMB_Wait_22 : IN STD_LOGIC;
LMB_Data_Addr_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_23 : OUT STD_LOGIC;
LMB_Ready_23 : IN STD_LOGIC;
LMB_Byte_Enable_23 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_23 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_23 : OUT STD_LOGIC;
LMB_Write_Strobe_23 : OUT STD_LOGIC;
LMB_CE_23 : IN STD_LOGIC;
LMB_UE_23 : IN STD_LOGIC;
LMB_Wait_23 : IN STD_LOGIC;
LMB_Data_Addr_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_24 : OUT STD_LOGIC;
LMB_Ready_24 : IN STD_LOGIC;
LMB_Byte_Enable_24 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_24 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_24 : OUT STD_LOGIC;
LMB_Write_Strobe_24 : OUT STD_LOGIC;
LMB_CE_24 : IN STD_LOGIC;
LMB_UE_24 : IN STD_LOGIC;
LMB_Wait_24 : IN STD_LOGIC;
LMB_Data_Addr_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_25 : OUT STD_LOGIC;
LMB_Ready_25 : IN STD_LOGIC;
LMB_Byte_Enable_25 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_25 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_25 : OUT STD_LOGIC;
LMB_Write_Strobe_25 : OUT STD_LOGIC;
LMB_CE_25 : IN STD_LOGIC;
LMB_UE_25 : IN STD_LOGIC;
LMB_Wait_25 : IN STD_LOGIC;
LMB_Data_Addr_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_26 : OUT STD_LOGIC;
LMB_Ready_26 : IN STD_LOGIC;
LMB_Byte_Enable_26 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_26 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_26 : OUT STD_LOGIC;
LMB_Write_Strobe_26 : OUT STD_LOGIC;
LMB_CE_26 : IN STD_LOGIC;
LMB_UE_26 : IN STD_LOGIC;
LMB_Wait_26 : IN STD_LOGIC;
LMB_Data_Addr_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_27 : OUT STD_LOGIC;
LMB_Ready_27 : IN STD_LOGIC;
LMB_Byte_Enable_27 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_27 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_27 : OUT STD_LOGIC;
LMB_Write_Strobe_27 : OUT STD_LOGIC;
LMB_CE_27 : IN STD_LOGIC;
LMB_UE_27 : IN STD_LOGIC;
LMB_Wait_27 : IN STD_LOGIC;
LMB_Data_Addr_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_28 : OUT STD_LOGIC;
LMB_Ready_28 : IN STD_LOGIC;
LMB_Byte_Enable_28 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_28 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_28 : OUT STD_LOGIC;
LMB_Write_Strobe_28 : OUT STD_LOGIC;
LMB_CE_28 : IN STD_LOGIC;
LMB_UE_28 : IN STD_LOGIC;
LMB_Wait_28 : IN STD_LOGIC;
LMB_Data_Addr_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_29 : OUT STD_LOGIC;
LMB_Ready_29 : IN STD_LOGIC;
LMB_Byte_Enable_29 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_29 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_29 : OUT STD_LOGIC;
LMB_Write_Strobe_29 : OUT STD_LOGIC;
LMB_CE_29 : IN STD_LOGIC;
LMB_UE_29 : IN STD_LOGIC;
LMB_Wait_29 : IN STD_LOGIC;
LMB_Data_Addr_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_30 : OUT STD_LOGIC;
LMB_Ready_30 : IN STD_LOGIC;
LMB_Byte_Enable_30 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_30 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_30 : OUT STD_LOGIC;
LMB_Write_Strobe_30 : OUT STD_LOGIC;
LMB_CE_30 : IN STD_LOGIC;
LMB_UE_30 : IN STD_LOGIC;
LMB_Wait_30 : IN STD_LOGIC;
LMB_Data_Addr_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_31 : OUT STD_LOGIC;
LMB_Ready_31 : IN STD_LOGIC;
LMB_Byte_Enable_31 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_31 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_31 : OUT STD_LOGIC;
LMB_Write_Strobe_31 : OUT STD_LOGIC;
LMB_CE_31 : IN STD_LOGIC;
LMB_UE_31 : IN STD_LOGIC;
LMB_Wait_31 : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TID : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
TRACE_CLK_OUT : OUT STD_LOGIC;
TRACE_CLK : IN STD_LOGIC;
TRACE_CTL : OUT STD_LOGIC;
TRACE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Trig_In_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_0 : OUT STD_LOGIC;
Dbg_TrData_0 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_0 : OUT STD_LOGIC;
Dbg_TrValid_0 : IN STD_LOGIC;
Dbg_Disable_0 : OUT STD_LOGIC;
Dbg_AWADDR_0 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_0 : OUT STD_LOGIC;
Dbg_AWREADY_0 : IN STD_LOGIC;
Dbg_WDATA_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_0 : OUT STD_LOGIC;
Dbg_WREADY_0 : IN STD_LOGIC;
Dbg_BRESP_0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_0 : IN STD_LOGIC;
Dbg_BREADY_0 : OUT STD_LOGIC;
Dbg_ARADDR_0 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_0 : OUT STD_LOGIC;
Dbg_ARREADY_0 : IN STD_LOGIC;
Dbg_RDATA_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_0 : IN STD_LOGIC;
Dbg_RREADY_0 : OUT STD_LOGIC;
Dbg_Clk_1 : OUT STD_LOGIC;
Dbg_TDI_1 : OUT STD_LOGIC;
Dbg_TDO_1 : IN STD_LOGIC;
Dbg_Reg_En_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_1 : OUT STD_LOGIC;
Dbg_Shift_1 : OUT STD_LOGIC;
Dbg_Update_1 : OUT STD_LOGIC;
Dbg_Rst_1 : OUT STD_LOGIC;
Dbg_Trig_In_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_1 : OUT STD_LOGIC;
Dbg_TrData_1 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_1 : OUT STD_LOGIC;
Dbg_TrValid_1 : IN STD_LOGIC;
Dbg_Disable_1 : OUT STD_LOGIC;
Dbg_AWADDR_1 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_1 : OUT STD_LOGIC;
Dbg_AWREADY_1 : IN STD_LOGIC;
Dbg_WDATA_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_1 : OUT STD_LOGIC;
Dbg_WREADY_1 : IN STD_LOGIC;
Dbg_BRESP_1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_1 : IN STD_LOGIC;
Dbg_BREADY_1 : OUT STD_LOGIC;
Dbg_ARADDR_1 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_1 : OUT STD_LOGIC;
Dbg_ARREADY_1 : IN STD_LOGIC;
Dbg_RDATA_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_1 : IN STD_LOGIC;
Dbg_RREADY_1 : OUT STD_LOGIC;
Dbg_Clk_2 : OUT STD_LOGIC;
Dbg_TDI_2 : OUT STD_LOGIC;
Dbg_TDO_2 : IN STD_LOGIC;
Dbg_Reg_En_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_2 : OUT STD_LOGIC;
Dbg_Shift_2 : OUT STD_LOGIC;
Dbg_Update_2 : OUT STD_LOGIC;
Dbg_Rst_2 : OUT STD_LOGIC;
Dbg_Trig_In_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_2 : OUT STD_LOGIC;
Dbg_TrData_2 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_2 : OUT STD_LOGIC;
Dbg_TrValid_2 : IN STD_LOGIC;
Dbg_Disable_2 : OUT STD_LOGIC;
Dbg_AWADDR_2 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_2 : OUT STD_LOGIC;
Dbg_AWREADY_2 : IN STD_LOGIC;
Dbg_WDATA_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_2 : OUT STD_LOGIC;
Dbg_WREADY_2 : IN STD_LOGIC;
Dbg_BRESP_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_2 : IN STD_LOGIC;
Dbg_BREADY_2 : OUT STD_LOGIC;
Dbg_ARADDR_2 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_2 : OUT STD_LOGIC;
Dbg_ARREADY_2 : IN STD_LOGIC;
Dbg_RDATA_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_2 : IN STD_LOGIC;
Dbg_RREADY_2 : OUT STD_LOGIC;
Dbg_Clk_3 : OUT STD_LOGIC;
Dbg_TDI_3 : OUT STD_LOGIC;
Dbg_TDO_3 : IN STD_LOGIC;
Dbg_Reg_En_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_3 : OUT STD_LOGIC;
Dbg_Shift_3 : OUT STD_LOGIC;
Dbg_Update_3 : OUT STD_LOGIC;
Dbg_Rst_3 : OUT STD_LOGIC;
Dbg_Trig_In_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_3 : OUT STD_LOGIC;
Dbg_TrData_3 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_3 : OUT STD_LOGIC;
Dbg_TrValid_3 : IN STD_LOGIC;
Dbg_Disable_3 : OUT STD_LOGIC;
Dbg_AWADDR_3 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_3 : OUT STD_LOGIC;
Dbg_AWREADY_3 : IN STD_LOGIC;
Dbg_WDATA_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_3 : OUT STD_LOGIC;
Dbg_WREADY_3 : IN STD_LOGIC;
Dbg_BRESP_3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_3 : IN STD_LOGIC;
Dbg_BREADY_3 : OUT STD_LOGIC;
Dbg_ARADDR_3 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_3 : OUT STD_LOGIC;
Dbg_ARREADY_3 : IN STD_LOGIC;
Dbg_RDATA_3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_3 : IN STD_LOGIC;
Dbg_RREADY_3 : OUT STD_LOGIC;
Dbg_Clk_4 : OUT STD_LOGIC;
Dbg_TDI_4 : OUT STD_LOGIC;
Dbg_TDO_4 : IN STD_LOGIC;
Dbg_Reg_En_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_4 : OUT STD_LOGIC;
Dbg_Shift_4 : OUT STD_LOGIC;
Dbg_Update_4 : OUT STD_LOGIC;
Dbg_Rst_4 : OUT STD_LOGIC;
Dbg_Trig_In_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_4 : OUT STD_LOGIC;
Dbg_TrData_4 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_4 : OUT STD_LOGIC;
Dbg_TrValid_4 : IN STD_LOGIC;
Dbg_Disable_4 : OUT STD_LOGIC;
Dbg_AWADDR_4 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_4 : OUT STD_LOGIC;
Dbg_AWREADY_4 : IN STD_LOGIC;
Dbg_WDATA_4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_4 : OUT STD_LOGIC;
Dbg_WREADY_4 : IN STD_LOGIC;
Dbg_BRESP_4 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_4 : IN STD_LOGIC;
Dbg_BREADY_4 : OUT STD_LOGIC;
Dbg_ARADDR_4 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_4 : OUT STD_LOGIC;
Dbg_ARREADY_4 : IN STD_LOGIC;
Dbg_RDATA_4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_4 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_4 : IN STD_LOGIC;
Dbg_RREADY_4 : OUT STD_LOGIC;
Dbg_Clk_5 : OUT STD_LOGIC;
Dbg_TDI_5 : OUT STD_LOGIC;
Dbg_TDO_5 : IN STD_LOGIC;
Dbg_Reg_En_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_5 : OUT STD_LOGIC;
Dbg_Shift_5 : OUT STD_LOGIC;
Dbg_Update_5 : OUT STD_LOGIC;
Dbg_Rst_5 : OUT STD_LOGIC;
Dbg_Trig_In_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_5 : OUT STD_LOGIC;
Dbg_TrData_5 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_5 : OUT STD_LOGIC;
Dbg_TrValid_5 : IN STD_LOGIC;
Dbg_Disable_5 : OUT STD_LOGIC;
Dbg_AWADDR_5 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_5 : OUT STD_LOGIC;
Dbg_AWREADY_5 : IN STD_LOGIC;
Dbg_WDATA_5 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_5 : OUT STD_LOGIC;
Dbg_WREADY_5 : IN STD_LOGIC;
Dbg_BRESP_5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_5 : IN STD_LOGIC;
Dbg_BREADY_5 : OUT STD_LOGIC;
Dbg_ARADDR_5 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_5 : OUT STD_LOGIC;
Dbg_ARREADY_5 : IN STD_LOGIC;
Dbg_RDATA_5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_5 : IN STD_LOGIC;
Dbg_RREADY_5 : OUT STD_LOGIC;
Dbg_Clk_6 : OUT STD_LOGIC;
Dbg_TDI_6 : OUT STD_LOGIC;
Dbg_TDO_6 : IN STD_LOGIC;
Dbg_Reg_En_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_6 : OUT STD_LOGIC;
Dbg_Shift_6 : OUT STD_LOGIC;
Dbg_Update_6 : OUT STD_LOGIC;
Dbg_Rst_6 : OUT STD_LOGIC;
Dbg_Trig_In_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_6 : OUT STD_LOGIC;
Dbg_TrData_6 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_6 : OUT STD_LOGIC;
Dbg_TrValid_6 : IN STD_LOGIC;
Dbg_Disable_6 : OUT STD_LOGIC;
Dbg_AWADDR_6 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_6 : OUT STD_LOGIC;
Dbg_AWREADY_6 : IN STD_LOGIC;
Dbg_WDATA_6 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_6 : OUT STD_LOGIC;
Dbg_WREADY_6 : IN STD_LOGIC;
Dbg_BRESP_6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_6 : IN STD_LOGIC;
Dbg_BREADY_6 : OUT STD_LOGIC;
Dbg_ARADDR_6 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_6 : OUT STD_LOGIC;
Dbg_ARREADY_6 : IN STD_LOGIC;
Dbg_RDATA_6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_6 : IN STD_LOGIC;
Dbg_RREADY_6 : OUT STD_LOGIC;
Dbg_Clk_7 : OUT STD_LOGIC;
Dbg_TDI_7 : OUT STD_LOGIC;
Dbg_TDO_7 : IN STD_LOGIC;
Dbg_Reg_En_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_7 : OUT STD_LOGIC;
Dbg_Shift_7 : OUT STD_LOGIC;
Dbg_Update_7 : OUT STD_LOGIC;
Dbg_Rst_7 : OUT STD_LOGIC;
Dbg_Trig_In_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_7 : OUT STD_LOGIC;
Dbg_TrData_7 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_7 : OUT STD_LOGIC;
Dbg_TrValid_7 : IN STD_LOGIC;
Dbg_Disable_7 : OUT STD_LOGIC;
Dbg_AWADDR_7 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_7 : OUT STD_LOGIC;
Dbg_AWREADY_7 : IN STD_LOGIC;
Dbg_WDATA_7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_7 : OUT STD_LOGIC;
Dbg_WREADY_7 : IN STD_LOGIC;
Dbg_BRESP_7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_7 : IN STD_LOGIC;
Dbg_BREADY_7 : OUT STD_LOGIC;
Dbg_ARADDR_7 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_7 : OUT STD_LOGIC;
Dbg_ARREADY_7 : IN STD_LOGIC;
Dbg_RDATA_7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_7 : IN STD_LOGIC;
Dbg_RREADY_7 : OUT STD_LOGIC;
Dbg_Clk_8 : OUT STD_LOGIC;
Dbg_TDI_8 : OUT STD_LOGIC;
Dbg_TDO_8 : IN STD_LOGIC;
Dbg_Reg_En_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_8 : OUT STD_LOGIC;
Dbg_Shift_8 : OUT STD_LOGIC;
Dbg_Update_8 : OUT STD_LOGIC;
Dbg_Rst_8 : OUT STD_LOGIC;
Dbg_Trig_In_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_8 : OUT STD_LOGIC;
Dbg_TrData_8 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_8 : OUT STD_LOGIC;
Dbg_TrValid_8 : IN STD_LOGIC;
Dbg_Disable_8 : OUT STD_LOGIC;
Dbg_AWADDR_8 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_8 : OUT STD_LOGIC;
Dbg_AWREADY_8 : IN STD_LOGIC;
Dbg_WDATA_8 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_8 : OUT STD_LOGIC;
Dbg_WREADY_8 : IN STD_LOGIC;
Dbg_BRESP_8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_8 : IN STD_LOGIC;
Dbg_BREADY_8 : OUT STD_LOGIC;
Dbg_ARADDR_8 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_8 : OUT STD_LOGIC;
Dbg_ARREADY_8 : IN STD_LOGIC;
Dbg_RDATA_8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_8 : IN STD_LOGIC;
Dbg_RREADY_8 : OUT STD_LOGIC;
Dbg_Clk_9 : OUT STD_LOGIC;
Dbg_TDI_9 : OUT STD_LOGIC;
Dbg_TDO_9 : IN STD_LOGIC;
Dbg_Reg_En_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_9 : OUT STD_LOGIC;
Dbg_Shift_9 : OUT STD_LOGIC;
Dbg_Update_9 : OUT STD_LOGIC;
Dbg_Rst_9 : OUT STD_LOGIC;
Dbg_Trig_In_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_9 : OUT STD_LOGIC;
Dbg_TrData_9 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_9 : OUT STD_LOGIC;
Dbg_TrValid_9 : IN STD_LOGIC;
Dbg_Disable_9 : OUT STD_LOGIC;
Dbg_AWADDR_9 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_9 : OUT STD_LOGIC;
Dbg_AWREADY_9 : IN STD_LOGIC;
Dbg_WDATA_9 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_9 : OUT STD_LOGIC;
Dbg_WREADY_9 : IN STD_LOGIC;
Dbg_BRESP_9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_9 : IN STD_LOGIC;
Dbg_BREADY_9 : OUT STD_LOGIC;
Dbg_ARADDR_9 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_9 : OUT STD_LOGIC;
Dbg_ARREADY_9 : IN STD_LOGIC;
Dbg_RDATA_9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_9 : IN STD_LOGIC;
Dbg_RREADY_9 : OUT STD_LOGIC;
Dbg_Clk_10 : OUT STD_LOGIC;
Dbg_TDI_10 : OUT STD_LOGIC;
Dbg_TDO_10 : IN STD_LOGIC;
Dbg_Reg_En_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_10 : OUT STD_LOGIC;
Dbg_Shift_10 : OUT STD_LOGIC;
Dbg_Update_10 : OUT STD_LOGIC;
Dbg_Rst_10 : OUT STD_LOGIC;
Dbg_Trig_In_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_10 : OUT STD_LOGIC;
Dbg_TrData_10 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_10 : OUT STD_LOGIC;
Dbg_TrValid_10 : IN STD_LOGIC;
Dbg_Disable_10 : OUT STD_LOGIC;
Dbg_AWADDR_10 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_10 : OUT STD_LOGIC;
Dbg_AWREADY_10 : IN STD_LOGIC;
Dbg_WDATA_10 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_10 : OUT STD_LOGIC;
Dbg_WREADY_10 : IN STD_LOGIC;
Dbg_BRESP_10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_10 : IN STD_LOGIC;
Dbg_BREADY_10 : OUT STD_LOGIC;
Dbg_ARADDR_10 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_10 : OUT STD_LOGIC;
Dbg_ARREADY_10 : IN STD_LOGIC;
Dbg_RDATA_10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_10 : IN STD_LOGIC;
Dbg_RREADY_10 : OUT STD_LOGIC;
Dbg_Clk_11 : OUT STD_LOGIC;
Dbg_TDI_11 : OUT STD_LOGIC;
Dbg_TDO_11 : IN STD_LOGIC;
Dbg_Reg_En_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_11 : OUT STD_LOGIC;
Dbg_Shift_11 : OUT STD_LOGIC;
Dbg_Update_11 : OUT STD_LOGIC;
Dbg_Rst_11 : OUT STD_LOGIC;
Dbg_Trig_In_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_11 : OUT STD_LOGIC;
Dbg_TrData_11 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_11 : OUT STD_LOGIC;
Dbg_TrValid_11 : IN STD_LOGIC;
Dbg_Disable_11 : OUT STD_LOGIC;
Dbg_AWADDR_11 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_11 : OUT STD_LOGIC;
Dbg_AWREADY_11 : IN STD_LOGIC;
Dbg_WDATA_11 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_11 : OUT STD_LOGIC;
Dbg_WREADY_11 : IN STD_LOGIC;
Dbg_BRESP_11 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_11 : IN STD_LOGIC;
Dbg_BREADY_11 : OUT STD_LOGIC;
Dbg_ARADDR_11 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_11 : OUT STD_LOGIC;
Dbg_ARREADY_11 : IN STD_LOGIC;
Dbg_RDATA_11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_11 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_11 : IN STD_LOGIC;
Dbg_RREADY_11 : OUT STD_LOGIC;
Dbg_Clk_12 : OUT STD_LOGIC;
Dbg_TDI_12 : OUT STD_LOGIC;
Dbg_TDO_12 : IN STD_LOGIC;
Dbg_Reg_En_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_12 : OUT STD_LOGIC;
Dbg_Shift_12 : OUT STD_LOGIC;
Dbg_Update_12 : OUT STD_LOGIC;
Dbg_Rst_12 : OUT STD_LOGIC;
Dbg_Trig_In_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_12 : OUT STD_LOGIC;
Dbg_TrData_12 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_12 : OUT STD_LOGIC;
Dbg_TrValid_12 : IN STD_LOGIC;
Dbg_Disable_12 : OUT STD_LOGIC;
Dbg_AWADDR_12 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_12 : OUT STD_LOGIC;
Dbg_AWREADY_12 : IN STD_LOGIC;
Dbg_WDATA_12 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_12 : OUT STD_LOGIC;
Dbg_WREADY_12 : IN STD_LOGIC;
Dbg_BRESP_12 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_12 : IN STD_LOGIC;
Dbg_BREADY_12 : OUT STD_LOGIC;
Dbg_ARADDR_12 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_12 : OUT STD_LOGIC;
Dbg_ARREADY_12 : IN STD_LOGIC;
Dbg_RDATA_12 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_12 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_12 : IN STD_LOGIC;
Dbg_RREADY_12 : OUT STD_LOGIC;
Dbg_Clk_13 : OUT STD_LOGIC;
Dbg_TDI_13 : OUT STD_LOGIC;
Dbg_TDO_13 : IN STD_LOGIC;
Dbg_Reg_En_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_13 : OUT STD_LOGIC;
Dbg_Shift_13 : OUT STD_LOGIC;
Dbg_Update_13 : OUT STD_LOGIC;
Dbg_Rst_13 : OUT STD_LOGIC;
Dbg_Trig_In_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_13 : OUT STD_LOGIC;
Dbg_TrData_13 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_13 : OUT STD_LOGIC;
Dbg_TrValid_13 : IN STD_LOGIC;
Dbg_Disable_13 : OUT STD_LOGIC;
Dbg_AWADDR_13 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_13 : OUT STD_LOGIC;
Dbg_AWREADY_13 : IN STD_LOGIC;
Dbg_WDATA_13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_13 : OUT STD_LOGIC;
Dbg_WREADY_13 : IN STD_LOGIC;
Dbg_BRESP_13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_13 : IN STD_LOGIC;
Dbg_BREADY_13 : OUT STD_LOGIC;
Dbg_ARADDR_13 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_13 : OUT STD_LOGIC;
Dbg_ARREADY_13 : IN STD_LOGIC;
Dbg_RDATA_13 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_13 : IN STD_LOGIC;
Dbg_RREADY_13 : OUT STD_LOGIC;
Dbg_Clk_14 : OUT STD_LOGIC;
Dbg_TDI_14 : OUT STD_LOGIC;
Dbg_TDO_14 : IN STD_LOGIC;
Dbg_Reg_En_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_14 : OUT STD_LOGIC;
Dbg_Shift_14 : OUT STD_LOGIC;
Dbg_Update_14 : OUT STD_LOGIC;
Dbg_Rst_14 : OUT STD_LOGIC;
Dbg_Trig_In_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_14 : OUT STD_LOGIC;
Dbg_TrData_14 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_14 : OUT STD_LOGIC;
Dbg_TrValid_14 : IN STD_LOGIC;
Dbg_Disable_14 : OUT STD_LOGIC;
Dbg_AWADDR_14 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_14 : OUT STD_LOGIC;
Dbg_AWREADY_14 : IN STD_LOGIC;
Dbg_WDATA_14 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_14 : OUT STD_LOGIC;
Dbg_WREADY_14 : IN STD_LOGIC;
Dbg_BRESP_14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_14 : IN STD_LOGIC;
Dbg_BREADY_14 : OUT STD_LOGIC;
Dbg_ARADDR_14 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_14 : OUT STD_LOGIC;
Dbg_ARREADY_14 : IN STD_LOGIC;
Dbg_RDATA_14 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_14 : IN STD_LOGIC;
Dbg_RREADY_14 : OUT STD_LOGIC;
Dbg_Clk_15 : OUT STD_LOGIC;
Dbg_TDI_15 : OUT STD_LOGIC;
Dbg_TDO_15 : IN STD_LOGIC;
Dbg_Reg_En_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_15 : OUT STD_LOGIC;
Dbg_Shift_15 : OUT STD_LOGIC;
Dbg_Update_15 : OUT STD_LOGIC;
Dbg_Rst_15 : OUT STD_LOGIC;
Dbg_Trig_In_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_15 : OUT STD_LOGIC;
Dbg_TrData_15 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_15 : OUT STD_LOGIC;
Dbg_TrValid_15 : IN STD_LOGIC;
Dbg_Disable_15 : OUT STD_LOGIC;
Dbg_AWADDR_15 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_15 : OUT STD_LOGIC;
Dbg_AWREADY_15 : IN STD_LOGIC;
Dbg_WDATA_15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_15 : OUT STD_LOGIC;
Dbg_WREADY_15 : IN STD_LOGIC;
Dbg_BRESP_15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_15 : IN STD_LOGIC;
Dbg_BREADY_15 : OUT STD_LOGIC;
Dbg_ARADDR_15 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_15 : OUT STD_LOGIC;
Dbg_ARREADY_15 : IN STD_LOGIC;
Dbg_RDATA_15 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_15 : IN STD_LOGIC;
Dbg_RREADY_15 : OUT STD_LOGIC;
Dbg_Clk_16 : OUT STD_LOGIC;
Dbg_TDI_16 : OUT STD_LOGIC;
Dbg_TDO_16 : IN STD_LOGIC;
Dbg_Reg_En_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_16 : OUT STD_LOGIC;
Dbg_Shift_16 : OUT STD_LOGIC;
Dbg_Update_16 : OUT STD_LOGIC;
Dbg_Rst_16 : OUT STD_LOGIC;
Dbg_Trig_In_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_16 : OUT STD_LOGIC;
Dbg_TrData_16 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_16 : OUT STD_LOGIC;
Dbg_TrValid_16 : IN STD_LOGIC;
Dbg_Disable_16 : OUT STD_LOGIC;
Dbg_AWADDR_16 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_16 : OUT STD_LOGIC;
Dbg_AWREADY_16 : IN STD_LOGIC;
Dbg_WDATA_16 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_16 : OUT STD_LOGIC;
Dbg_WREADY_16 : IN STD_LOGIC;
Dbg_BRESP_16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_16 : IN STD_LOGIC;
Dbg_BREADY_16 : OUT STD_LOGIC;
Dbg_ARADDR_16 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_16 : OUT STD_LOGIC;
Dbg_ARREADY_16 : IN STD_LOGIC;
Dbg_RDATA_16 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_16 : IN STD_LOGIC;
Dbg_RREADY_16 : OUT STD_LOGIC;
Dbg_Clk_17 : OUT STD_LOGIC;
Dbg_TDI_17 : OUT STD_LOGIC;
Dbg_TDO_17 : IN STD_LOGIC;
Dbg_Reg_En_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_17 : OUT STD_LOGIC;
Dbg_Shift_17 : OUT STD_LOGIC;
Dbg_Update_17 : OUT STD_LOGIC;
Dbg_Rst_17 : OUT STD_LOGIC;
Dbg_Trig_In_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_17 : OUT STD_LOGIC;
Dbg_TrData_17 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_17 : OUT STD_LOGIC;
Dbg_TrValid_17 : IN STD_LOGIC;
Dbg_Disable_17 : OUT STD_LOGIC;
Dbg_AWADDR_17 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_17 : OUT STD_LOGIC;
Dbg_AWREADY_17 : IN STD_LOGIC;
Dbg_WDATA_17 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_17 : OUT STD_LOGIC;
Dbg_WREADY_17 : IN STD_LOGIC;
Dbg_BRESP_17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_17 : IN STD_LOGIC;
Dbg_BREADY_17 : OUT STD_LOGIC;
Dbg_ARADDR_17 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_17 : OUT STD_LOGIC;
Dbg_ARREADY_17 : IN STD_LOGIC;
Dbg_RDATA_17 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_17 : IN STD_LOGIC;
Dbg_RREADY_17 : OUT STD_LOGIC;
Dbg_Clk_18 : OUT STD_LOGIC;
Dbg_TDI_18 : OUT STD_LOGIC;
Dbg_TDO_18 : IN STD_LOGIC;
Dbg_Reg_En_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_18 : OUT STD_LOGIC;
Dbg_Shift_18 : OUT STD_LOGIC;
Dbg_Update_18 : OUT STD_LOGIC;
Dbg_Rst_18 : OUT STD_LOGIC;
Dbg_Trig_In_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_18 : OUT STD_LOGIC;
Dbg_TrData_18 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_18 : OUT STD_LOGIC;
Dbg_TrValid_18 : IN STD_LOGIC;
Dbg_Disable_18 : OUT STD_LOGIC;
Dbg_AWADDR_18 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_18 : OUT STD_LOGIC;
Dbg_AWREADY_18 : IN STD_LOGIC;
Dbg_WDATA_18 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_18 : OUT STD_LOGIC;
Dbg_WREADY_18 : IN STD_LOGIC;
Dbg_BRESP_18 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_18 : IN STD_LOGIC;
Dbg_BREADY_18 : OUT STD_LOGIC;
Dbg_ARADDR_18 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_18 : OUT STD_LOGIC;
Dbg_ARREADY_18 : IN STD_LOGIC;
Dbg_RDATA_18 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_18 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_18 : IN STD_LOGIC;
Dbg_RREADY_18 : OUT STD_LOGIC;
Dbg_Clk_19 : OUT STD_LOGIC;
Dbg_TDI_19 : OUT STD_LOGIC;
Dbg_TDO_19 : IN STD_LOGIC;
Dbg_Reg_En_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_19 : OUT STD_LOGIC;
Dbg_Shift_19 : OUT STD_LOGIC;
Dbg_Update_19 : OUT STD_LOGIC;
Dbg_Rst_19 : OUT STD_LOGIC;
Dbg_Trig_In_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_19 : OUT STD_LOGIC;
Dbg_TrData_19 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_19 : OUT STD_LOGIC;
Dbg_TrValid_19 : IN STD_LOGIC;
Dbg_Disable_19 : OUT STD_LOGIC;
Dbg_AWADDR_19 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_19 : OUT STD_LOGIC;
Dbg_AWREADY_19 : IN STD_LOGIC;
Dbg_WDATA_19 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_19 : OUT STD_LOGIC;
Dbg_WREADY_19 : IN STD_LOGIC;
Dbg_BRESP_19 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_19 : IN STD_LOGIC;
Dbg_BREADY_19 : OUT STD_LOGIC;
Dbg_ARADDR_19 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_19 : OUT STD_LOGIC;
Dbg_ARREADY_19 : IN STD_LOGIC;
Dbg_RDATA_19 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_19 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_19 : IN STD_LOGIC;
Dbg_RREADY_19 : OUT STD_LOGIC;
Dbg_Clk_20 : OUT STD_LOGIC;
Dbg_TDI_20 : OUT STD_LOGIC;
Dbg_TDO_20 : IN STD_LOGIC;
Dbg_Reg_En_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_20 : OUT STD_LOGIC;
Dbg_Shift_20 : OUT STD_LOGIC;
Dbg_Update_20 : OUT STD_LOGIC;
Dbg_Rst_20 : OUT STD_LOGIC;
Dbg_Trig_In_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_20 : OUT STD_LOGIC;
Dbg_TrData_20 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_20 : OUT STD_LOGIC;
Dbg_TrValid_20 : IN STD_LOGIC;
Dbg_Disable_20 : OUT STD_LOGIC;
Dbg_AWADDR_20 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_20 : OUT STD_LOGIC;
Dbg_AWREADY_20 : IN STD_LOGIC;
Dbg_WDATA_20 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_20 : OUT STD_LOGIC;
Dbg_WREADY_20 : IN STD_LOGIC;
Dbg_BRESP_20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_20 : IN STD_LOGIC;
Dbg_BREADY_20 : OUT STD_LOGIC;
Dbg_ARADDR_20 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_20 : OUT STD_LOGIC;
Dbg_ARREADY_20 : IN STD_LOGIC;
Dbg_RDATA_20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_20 : IN STD_LOGIC;
Dbg_RREADY_20 : OUT STD_LOGIC;
Dbg_Clk_21 : OUT STD_LOGIC;
Dbg_TDI_21 : OUT STD_LOGIC;
Dbg_TDO_21 : IN STD_LOGIC;
Dbg_Reg_En_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_21 : OUT STD_LOGIC;
Dbg_Shift_21 : OUT STD_LOGIC;
Dbg_Update_21 : OUT STD_LOGIC;
Dbg_Rst_21 : OUT STD_LOGIC;
Dbg_Trig_In_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_21 : OUT STD_LOGIC;
Dbg_TrData_21 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_21 : OUT STD_LOGIC;
Dbg_TrValid_21 : IN STD_LOGIC;
Dbg_Disable_21 : OUT STD_LOGIC;
Dbg_AWADDR_21 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_21 : OUT STD_LOGIC;
Dbg_AWREADY_21 : IN STD_LOGIC;
Dbg_WDATA_21 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_21 : OUT STD_LOGIC;
Dbg_WREADY_21 : IN STD_LOGIC;
Dbg_BRESP_21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_21 : IN STD_LOGIC;
Dbg_BREADY_21 : OUT STD_LOGIC;
Dbg_ARADDR_21 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_21 : OUT STD_LOGIC;
Dbg_ARREADY_21 : IN STD_LOGIC;
Dbg_RDATA_21 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_21 : IN STD_LOGIC;
Dbg_RREADY_21 : OUT STD_LOGIC;
Dbg_Clk_22 : OUT STD_LOGIC;
Dbg_TDI_22 : OUT STD_LOGIC;
Dbg_TDO_22 : IN STD_LOGIC;
Dbg_Reg_En_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_22 : OUT STD_LOGIC;
Dbg_Shift_22 : OUT STD_LOGIC;
Dbg_Update_22 : OUT STD_LOGIC;
Dbg_Rst_22 : OUT STD_LOGIC;
Dbg_Trig_In_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_22 : OUT STD_LOGIC;
Dbg_TrData_22 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_22 : OUT STD_LOGIC;
Dbg_TrValid_22 : IN STD_LOGIC;
Dbg_Disable_22 : OUT STD_LOGIC;
Dbg_AWADDR_22 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_22 : OUT STD_LOGIC;
Dbg_AWREADY_22 : IN STD_LOGIC;
Dbg_WDATA_22 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_22 : OUT STD_LOGIC;
Dbg_WREADY_22 : IN STD_LOGIC;
Dbg_BRESP_22 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_22 : IN STD_LOGIC;
Dbg_BREADY_22 : OUT STD_LOGIC;
Dbg_ARADDR_22 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_22 : OUT STD_LOGIC;
Dbg_ARREADY_22 : IN STD_LOGIC;
Dbg_RDATA_22 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_22 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_22 : IN STD_LOGIC;
Dbg_RREADY_22 : OUT STD_LOGIC;
Dbg_Clk_23 : OUT STD_LOGIC;
Dbg_TDI_23 : OUT STD_LOGIC;
Dbg_TDO_23 : IN STD_LOGIC;
Dbg_Reg_En_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_23 : OUT STD_LOGIC;
Dbg_Shift_23 : OUT STD_LOGIC;
Dbg_Update_23 : OUT STD_LOGIC;
Dbg_Rst_23 : OUT STD_LOGIC;
Dbg_Trig_In_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_23 : OUT STD_LOGIC;
Dbg_TrData_23 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_23 : OUT STD_LOGIC;
Dbg_TrValid_23 : IN STD_LOGIC;
Dbg_Disable_23 : OUT STD_LOGIC;
Dbg_AWADDR_23 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_23 : OUT STD_LOGIC;
Dbg_AWREADY_23 : IN STD_LOGIC;
Dbg_WDATA_23 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_23 : OUT STD_LOGIC;
Dbg_WREADY_23 : IN STD_LOGIC;
Dbg_BRESP_23 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_23 : IN STD_LOGIC;
Dbg_BREADY_23 : OUT STD_LOGIC;
Dbg_ARADDR_23 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_23 : OUT STD_LOGIC;
Dbg_ARREADY_23 : IN STD_LOGIC;
Dbg_RDATA_23 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_23 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_23 : IN STD_LOGIC;
Dbg_RREADY_23 : OUT STD_LOGIC;
Dbg_Clk_24 : OUT STD_LOGIC;
Dbg_TDI_24 : OUT STD_LOGIC;
Dbg_TDO_24 : IN STD_LOGIC;
Dbg_Reg_En_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_24 : OUT STD_LOGIC;
Dbg_Shift_24 : OUT STD_LOGIC;
Dbg_Update_24 : OUT STD_LOGIC;
Dbg_Rst_24 : OUT STD_LOGIC;
Dbg_Trig_In_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_24 : OUT STD_LOGIC;
Dbg_TrData_24 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_24 : OUT STD_LOGIC;
Dbg_TrValid_24 : IN STD_LOGIC;
Dbg_Disable_24 : OUT STD_LOGIC;
Dbg_AWADDR_24 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_24 : OUT STD_LOGIC;
Dbg_AWREADY_24 : IN STD_LOGIC;
Dbg_WDATA_24 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_24 : OUT STD_LOGIC;
Dbg_WREADY_24 : IN STD_LOGIC;
Dbg_BRESP_24 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_24 : IN STD_LOGIC;
Dbg_BREADY_24 : OUT STD_LOGIC;
Dbg_ARADDR_24 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_24 : OUT STD_LOGIC;
Dbg_ARREADY_24 : IN STD_LOGIC;
Dbg_RDATA_24 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_24 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_24 : IN STD_LOGIC;
Dbg_RREADY_24 : OUT STD_LOGIC;
Dbg_Clk_25 : OUT STD_LOGIC;
Dbg_TDI_25 : OUT STD_LOGIC;
Dbg_TDO_25 : IN STD_LOGIC;
Dbg_Reg_En_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_25 : OUT STD_LOGIC;
Dbg_Shift_25 : OUT STD_LOGIC;
Dbg_Update_25 : OUT STD_LOGIC;
Dbg_Rst_25 : OUT STD_LOGIC;
Dbg_Trig_In_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_25 : OUT STD_LOGIC;
Dbg_TrData_25 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_25 : OUT STD_LOGIC;
Dbg_TrValid_25 : IN STD_LOGIC;
Dbg_Disable_25 : OUT STD_LOGIC;
Dbg_AWADDR_25 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_25 : OUT STD_LOGIC;
Dbg_AWREADY_25 : IN STD_LOGIC;
Dbg_WDATA_25 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_25 : OUT STD_LOGIC;
Dbg_WREADY_25 : IN STD_LOGIC;
Dbg_BRESP_25 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_25 : IN STD_LOGIC;
Dbg_BREADY_25 : OUT STD_LOGIC;
Dbg_ARADDR_25 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_25 : OUT STD_LOGIC;
Dbg_ARREADY_25 : IN STD_LOGIC;
Dbg_RDATA_25 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_25 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_25 : IN STD_LOGIC;
Dbg_RREADY_25 : OUT STD_LOGIC;
Dbg_Clk_26 : OUT STD_LOGIC;
Dbg_TDI_26 : OUT STD_LOGIC;
Dbg_TDO_26 : IN STD_LOGIC;
Dbg_Reg_En_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_26 : OUT STD_LOGIC;
Dbg_Shift_26 : OUT STD_LOGIC;
Dbg_Update_26 : OUT STD_LOGIC;
Dbg_Rst_26 : OUT STD_LOGIC;
Dbg_Trig_In_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_26 : OUT STD_LOGIC;
Dbg_TrData_26 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_26 : OUT STD_LOGIC;
Dbg_TrValid_26 : IN STD_LOGIC;
Dbg_Disable_26 : OUT STD_LOGIC;
Dbg_AWADDR_26 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_26 : OUT STD_LOGIC;
Dbg_AWREADY_26 : IN STD_LOGIC;
Dbg_WDATA_26 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_26 : OUT STD_LOGIC;
Dbg_WREADY_26 : IN STD_LOGIC;
Dbg_BRESP_26 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_26 : IN STD_LOGIC;
Dbg_BREADY_26 : OUT STD_LOGIC;
Dbg_ARADDR_26 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_26 : OUT STD_LOGIC;
Dbg_ARREADY_26 : IN STD_LOGIC;
Dbg_RDATA_26 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_26 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_26 : IN STD_LOGIC;
Dbg_RREADY_26 : OUT STD_LOGIC;
Dbg_Clk_27 : OUT STD_LOGIC;
Dbg_TDI_27 : OUT STD_LOGIC;
Dbg_TDO_27 : IN STD_LOGIC;
Dbg_Reg_En_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_27 : OUT STD_LOGIC;
Dbg_Shift_27 : OUT STD_LOGIC;
Dbg_Update_27 : OUT STD_LOGIC;
Dbg_Rst_27 : OUT STD_LOGIC;
Dbg_Trig_In_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_27 : OUT STD_LOGIC;
Dbg_TrData_27 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_27 : OUT STD_LOGIC;
Dbg_TrValid_27 : IN STD_LOGIC;
Dbg_Disable_27 : OUT STD_LOGIC;
Dbg_AWADDR_27 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_27 : OUT STD_LOGIC;
Dbg_AWREADY_27 : IN STD_LOGIC;
Dbg_WDATA_27 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_27 : OUT STD_LOGIC;
Dbg_WREADY_27 : IN STD_LOGIC;
Dbg_BRESP_27 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_27 : IN STD_LOGIC;
Dbg_BREADY_27 : OUT STD_LOGIC;
Dbg_ARADDR_27 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_27 : OUT STD_LOGIC;
Dbg_ARREADY_27 : IN STD_LOGIC;
Dbg_RDATA_27 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_27 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_27 : IN STD_LOGIC;
Dbg_RREADY_27 : OUT STD_LOGIC;
Dbg_Clk_28 : OUT STD_LOGIC;
Dbg_TDI_28 : OUT STD_LOGIC;
Dbg_TDO_28 : IN STD_LOGIC;
Dbg_Reg_En_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_28 : OUT STD_LOGIC;
Dbg_Shift_28 : OUT STD_LOGIC;
Dbg_Update_28 : OUT STD_LOGIC;
Dbg_Rst_28 : OUT STD_LOGIC;
Dbg_Trig_In_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_28 : OUT STD_LOGIC;
Dbg_TrData_28 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_28 : OUT STD_LOGIC;
Dbg_TrValid_28 : IN STD_LOGIC;
Dbg_Disable_28 : OUT STD_LOGIC;
Dbg_AWADDR_28 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_28 : OUT STD_LOGIC;
Dbg_AWREADY_28 : IN STD_LOGIC;
Dbg_WDATA_28 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_28 : OUT STD_LOGIC;
Dbg_WREADY_28 : IN STD_LOGIC;
Dbg_BRESP_28 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_28 : IN STD_LOGIC;
Dbg_BREADY_28 : OUT STD_LOGIC;
Dbg_ARADDR_28 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_28 : OUT STD_LOGIC;
Dbg_ARREADY_28 : IN STD_LOGIC;
Dbg_RDATA_28 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_28 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_28 : IN STD_LOGIC;
Dbg_RREADY_28 : OUT STD_LOGIC;
Dbg_Clk_29 : OUT STD_LOGIC;
Dbg_TDI_29 : OUT STD_LOGIC;
Dbg_TDO_29 : IN STD_LOGIC;
Dbg_Reg_En_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_29 : OUT STD_LOGIC;
Dbg_Shift_29 : OUT STD_LOGIC;
Dbg_Update_29 : OUT STD_LOGIC;
Dbg_Rst_29 : OUT STD_LOGIC;
Dbg_Trig_In_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_29 : OUT STD_LOGIC;
Dbg_TrData_29 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_29 : OUT STD_LOGIC;
Dbg_TrValid_29 : IN STD_LOGIC;
Dbg_Disable_29 : OUT STD_LOGIC;
Dbg_AWADDR_29 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_29 : OUT STD_LOGIC;
Dbg_AWREADY_29 : IN STD_LOGIC;
Dbg_WDATA_29 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_29 : OUT STD_LOGIC;
Dbg_WREADY_29 : IN STD_LOGIC;
Dbg_BRESP_29 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_29 : IN STD_LOGIC;
Dbg_BREADY_29 : OUT STD_LOGIC;
Dbg_ARADDR_29 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_29 : OUT STD_LOGIC;
Dbg_ARREADY_29 : IN STD_LOGIC;
Dbg_RDATA_29 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_29 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_29 : IN STD_LOGIC;
Dbg_RREADY_29 : OUT STD_LOGIC;
Dbg_Clk_30 : OUT STD_LOGIC;
Dbg_TDI_30 : OUT STD_LOGIC;
Dbg_TDO_30 : IN STD_LOGIC;
Dbg_Reg_En_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_30 : OUT STD_LOGIC;
Dbg_Shift_30 : OUT STD_LOGIC;
Dbg_Update_30 : OUT STD_LOGIC;
Dbg_Rst_30 : OUT STD_LOGIC;
Dbg_Trig_In_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_30 : OUT STD_LOGIC;
Dbg_TrData_30 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_30 : OUT STD_LOGIC;
Dbg_TrValid_30 : IN STD_LOGIC;
Dbg_Disable_30 : OUT STD_LOGIC;
Dbg_AWADDR_30 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_30 : OUT STD_LOGIC;
Dbg_AWREADY_30 : IN STD_LOGIC;
Dbg_WDATA_30 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_30 : OUT STD_LOGIC;
Dbg_WREADY_30 : IN STD_LOGIC;
Dbg_BRESP_30 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_30 : IN STD_LOGIC;
Dbg_BREADY_30 : OUT STD_LOGIC;
Dbg_ARADDR_30 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_30 : OUT STD_LOGIC;
Dbg_ARREADY_30 : IN STD_LOGIC;
Dbg_RDATA_30 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_30 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_30 : IN STD_LOGIC;
Dbg_RREADY_30 : OUT STD_LOGIC;
Dbg_Clk_31 : OUT STD_LOGIC;
Dbg_TDI_31 : OUT STD_LOGIC;
Dbg_TDO_31 : IN STD_LOGIC;
Dbg_Reg_En_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_31 : OUT STD_LOGIC;
Dbg_Shift_31 : OUT STD_LOGIC;
Dbg_Update_31 : OUT STD_LOGIC;
Dbg_Rst_31 : OUT STD_LOGIC;
Dbg_Trig_In_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_31 : OUT STD_LOGIC;
Dbg_TrData_31 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_31 : OUT STD_LOGIC;
Dbg_TrValid_31 : IN STD_LOGIC;
Dbg_Disable_31 : OUT STD_LOGIC;
Dbg_AWADDR_31 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_31 : OUT STD_LOGIC;
Dbg_AWREADY_31 : IN STD_LOGIC;
Dbg_WDATA_31 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_31 : OUT STD_LOGIC;
Dbg_WREADY_31 : IN STD_LOGIC;
Dbg_BRESP_31 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_31 : IN STD_LOGIC;
Dbg_BREADY_31 : OUT STD_LOGIC;
Dbg_ARADDR_31 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_31 : OUT STD_LOGIC;
Dbg_ARREADY_31 : IN STD_LOGIC;
Dbg_RDATA_31 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_31 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_31 : IN STD_LOGIC;
Dbg_RREADY_31 : OUT STD_LOGIC;
bscan_ext_tdi : IN STD_LOGIC;
bscan_ext_reset : IN STD_LOGIC;
bscan_ext_shift : IN STD_LOGIC;
bscan_ext_update : IN STD_LOGIC;
bscan_ext_capture : IN STD_LOGIC;
bscan_ext_sel : IN STD_LOGIC;
bscan_ext_drck : IN STD_LOGIC;
bscan_ext_tdo : OUT STD_LOGIC;
Ext_JTAG_DRCK : OUT STD_LOGIC;
Ext_JTAG_RESET : OUT STD_LOGIC;
Ext_JTAG_SEL : OUT STD_LOGIC;
Ext_JTAG_CAPTURE : OUT STD_LOGIC;
Ext_JTAG_SHIFT : OUT STD_LOGIC;
Ext_JTAG_UPDATE : OUT STD_LOGIC;
Ext_JTAG_TDI : OUT STD_LOGIC;
Ext_JTAG_TDO : IN STD_LOGIC
);
END COMPONENT MDM;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Debug_SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Rst_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Disable_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 DISABLE";
BEGIN
U0 : MDM
GENERIC MAP (
C_FAMILY => "artix7",
C_JTAG_CHAIN => 2,
C_USE_BSCAN => 0,
C_DEBUG_INTERFACE => 0,
C_USE_CONFIG_RESET => 0,
C_INTERCONNECT => 2,
C_MB_DBG_PORTS => 1,
C_USE_UART => 0,
C_DBG_REG_ACCESS => 0,
C_DBG_MEM_ACCESS => 0,
C_USE_CROSS_TRIGGER => 0,
C_TRACE_OUTPUT => 0,
C_TRACE_DATA_WIDTH => 32,
C_TRACE_CLK_FREQ_HZ => 200000000,
C_TRACE_CLK_OUT_PHASE => 90,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_THREAD_ID_WIDTH => 1,
C_DATA_SIZE => 32,
C_M_AXIS_DATA_WIDTH => 32,
C_M_AXIS_ID_WIDTH => 7
)
PORT MAP (
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
M_AXI_ACLK => '0',
M_AXI_ARESETN => '0',
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
Debug_SYS_Rst => Debug_SYS_Rst,
Trig_In_0 => '0',
Trig_Ack_Out_0 => '0',
Trig_In_1 => '0',
Trig_Ack_Out_1 => '0',
Trig_In_2 => '0',
Trig_Ack_Out_2 => '0',
Trig_In_3 => '0',
Trig_Ack_Out_3 => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
M_AXI_AWREADY => '0',
M_AXI_WREADY => '0',
M_AXI_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_BVALID => '0',
M_AXI_ARREADY => '0',
M_AXI_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_RLAST => '0',
M_AXI_RVALID => '0',
LMB_Ready_0 => '0',
LMB_Data_Read_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_0 => '0',
LMB_UE_0 => '0',
LMB_Wait_0 => '0',
LMB_Ready_1 => '0',
LMB_Data_Read_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_1 => '0',
LMB_UE_1 => '0',
LMB_Wait_1 => '0',
LMB_Ready_2 => '0',
LMB_Data_Read_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_2 => '0',
LMB_UE_2 => '0',
LMB_Wait_2 => '0',
LMB_Ready_3 => '0',
LMB_Data_Read_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_3 => '0',
LMB_UE_3 => '0',
LMB_Wait_3 => '0',
LMB_Ready_4 => '0',
LMB_Data_Read_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_4 => '0',
LMB_UE_4 => '0',
LMB_Wait_4 => '0',
LMB_Ready_5 => '0',
LMB_Data_Read_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_5 => '0',
LMB_UE_5 => '0',
LMB_Wait_5 => '0',
LMB_Ready_6 => '0',
LMB_Data_Read_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_6 => '0',
LMB_UE_6 => '0',
LMB_Wait_6 => '0',
LMB_Ready_7 => '0',
LMB_Data_Read_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_7 => '0',
LMB_UE_7 => '0',
LMB_Wait_7 => '0',
LMB_Ready_8 => '0',
LMB_Data_Read_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_8 => '0',
LMB_UE_8 => '0',
LMB_Wait_8 => '0',
LMB_Ready_9 => '0',
LMB_Data_Read_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_9 => '0',
LMB_UE_9 => '0',
LMB_Wait_9 => '0',
LMB_Ready_10 => '0',
LMB_Data_Read_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_10 => '0',
LMB_UE_10 => '0',
LMB_Wait_10 => '0',
LMB_Ready_11 => '0',
LMB_Data_Read_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_11 => '0',
LMB_UE_11 => '0',
LMB_Wait_11 => '0',
LMB_Ready_12 => '0',
LMB_Data_Read_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_12 => '0',
LMB_UE_12 => '0',
LMB_Wait_12 => '0',
LMB_Ready_13 => '0',
LMB_Data_Read_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_13 => '0',
LMB_UE_13 => '0',
LMB_Wait_13 => '0',
LMB_Ready_14 => '0',
LMB_Data_Read_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_14 => '0',
LMB_UE_14 => '0',
LMB_Wait_14 => '0',
LMB_Ready_15 => '0',
LMB_Data_Read_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_15 => '0',
LMB_UE_15 => '0',
LMB_Wait_15 => '0',
LMB_Ready_16 => '0',
LMB_Data_Read_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_16 => '0',
LMB_UE_16 => '0',
LMB_Wait_16 => '0',
LMB_Ready_17 => '0',
LMB_Data_Read_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_17 => '0',
LMB_UE_17 => '0',
LMB_Wait_17 => '0',
LMB_Ready_18 => '0',
LMB_Data_Read_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_18 => '0',
LMB_UE_18 => '0',
LMB_Wait_18 => '0',
LMB_Ready_19 => '0',
LMB_Data_Read_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_19 => '0',
LMB_UE_19 => '0',
LMB_Wait_19 => '0',
LMB_Ready_20 => '0',
LMB_Data_Read_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_20 => '0',
LMB_UE_20 => '0',
LMB_Wait_20 => '0',
LMB_Ready_21 => '0',
LMB_Data_Read_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_21 => '0',
LMB_UE_21 => '0',
LMB_Wait_21 => '0',
LMB_Ready_22 => '0',
LMB_Data_Read_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_22 => '0',
LMB_UE_22 => '0',
LMB_Wait_22 => '0',
LMB_Ready_23 => '0',
LMB_Data_Read_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_23 => '0',
LMB_UE_23 => '0',
LMB_Wait_23 => '0',
LMB_Ready_24 => '0',
LMB_Data_Read_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_24 => '0',
LMB_UE_24 => '0',
LMB_Wait_24 => '0',
LMB_Ready_25 => '0',
LMB_Data_Read_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_25 => '0',
LMB_UE_25 => '0',
LMB_Wait_25 => '0',
LMB_Ready_26 => '0',
LMB_Data_Read_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_26 => '0',
LMB_UE_26 => '0',
LMB_Wait_26 => '0',
LMB_Ready_27 => '0',
LMB_Data_Read_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_27 => '0',
LMB_UE_27 => '0',
LMB_Wait_27 => '0',
LMB_Ready_28 => '0',
LMB_Data_Read_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_28 => '0',
LMB_UE_28 => '0',
LMB_Wait_28 => '0',
LMB_Ready_29 => '0',
LMB_Data_Read_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_29 => '0',
LMB_UE_29 => '0',
LMB_Wait_29 => '0',
LMB_Ready_30 => '0',
LMB_Data_Read_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_30 => '0',
LMB_UE_30 => '0',
LMB_Wait_30 => '0',
LMB_Ready_31 => '0',
LMB_Data_Read_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_31 => '0',
LMB_UE_31 => '0',
LMB_Wait_31 => '0',
M_AXIS_TREADY => '1',
TRACE_CLK => '0',
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Trig_In_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_0 => '0',
Dbg_Disable_0 => Dbg_Disable_0,
Dbg_AWREADY_0 => '0',
Dbg_WREADY_0 => '0',
Dbg_BRESP_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_0 => '0',
Dbg_ARREADY_0 => '0',
Dbg_RDATA_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_0 => '0',
Dbg_TDO_1 => '0',
Dbg_Trig_In_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_1 => '0',
Dbg_AWREADY_1 => '0',
Dbg_WREADY_1 => '0',
Dbg_BRESP_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_1 => '0',
Dbg_ARREADY_1 => '0',
Dbg_RDATA_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_1 => '0',
Dbg_TDO_2 => '0',
Dbg_Trig_In_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_2 => '0',
Dbg_AWREADY_2 => '0',
Dbg_WREADY_2 => '0',
Dbg_BRESP_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_2 => '0',
Dbg_ARREADY_2 => '0',
Dbg_RDATA_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_2 => '0',
Dbg_TDO_3 => '0',
Dbg_Trig_In_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_3 => '0',
Dbg_AWREADY_3 => '0',
Dbg_WREADY_3 => '0',
Dbg_BRESP_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_3 => '0',
Dbg_ARREADY_3 => '0',
Dbg_RDATA_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_3 => '0',
Dbg_TDO_4 => '0',
Dbg_Trig_In_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_4 => '0',
Dbg_AWREADY_4 => '0',
Dbg_WREADY_4 => '0',
Dbg_BRESP_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_4 => '0',
Dbg_ARREADY_4 => '0',
Dbg_RDATA_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_4 => '0',
Dbg_TDO_5 => '0',
Dbg_Trig_In_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_5 => '0',
Dbg_AWREADY_5 => '0',
Dbg_WREADY_5 => '0',
Dbg_BRESP_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_5 => '0',
Dbg_ARREADY_5 => '0',
Dbg_RDATA_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_5 => '0',
Dbg_TDO_6 => '0',
Dbg_Trig_In_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_6 => '0',
Dbg_AWREADY_6 => '0',
Dbg_WREADY_6 => '0',
Dbg_BRESP_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_6 => '0',
Dbg_ARREADY_6 => '0',
Dbg_RDATA_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_6 => '0',
Dbg_TDO_7 => '0',
Dbg_Trig_In_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_7 => '0',
Dbg_AWREADY_7 => '0',
Dbg_WREADY_7 => '0',
Dbg_BRESP_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_7 => '0',
Dbg_ARREADY_7 => '0',
Dbg_RDATA_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_7 => '0',
Dbg_TDO_8 => '0',
Dbg_Trig_In_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_8 => '0',
Dbg_AWREADY_8 => '0',
Dbg_WREADY_8 => '0',
Dbg_BRESP_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_8 => '0',
Dbg_ARREADY_8 => '0',
Dbg_RDATA_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_8 => '0',
Dbg_TDO_9 => '0',
Dbg_Trig_In_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_9 => '0',
Dbg_AWREADY_9 => '0',
Dbg_WREADY_9 => '0',
Dbg_BRESP_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_9 => '0',
Dbg_ARREADY_9 => '0',
Dbg_RDATA_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_9 => '0',
Dbg_TDO_10 => '0',
Dbg_Trig_In_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_10 => '0',
Dbg_AWREADY_10 => '0',
Dbg_WREADY_10 => '0',
Dbg_BRESP_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_10 => '0',
Dbg_ARREADY_10 => '0',
Dbg_RDATA_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_10 => '0',
Dbg_TDO_11 => '0',
Dbg_Trig_In_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_11 => '0',
Dbg_AWREADY_11 => '0',
Dbg_WREADY_11 => '0',
Dbg_BRESP_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_11 => '0',
Dbg_ARREADY_11 => '0',
Dbg_RDATA_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_11 => '0',
Dbg_TDO_12 => '0',
Dbg_Trig_In_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_12 => '0',
Dbg_AWREADY_12 => '0',
Dbg_WREADY_12 => '0',
Dbg_BRESP_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_12 => '0',
Dbg_ARREADY_12 => '0',
Dbg_RDATA_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_12 => '0',
Dbg_TDO_13 => '0',
Dbg_Trig_In_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_13 => '0',
Dbg_AWREADY_13 => '0',
Dbg_WREADY_13 => '0',
Dbg_BRESP_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_13 => '0',
Dbg_ARREADY_13 => '0',
Dbg_RDATA_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_13 => '0',
Dbg_TDO_14 => '0',
Dbg_Trig_In_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_14 => '0',
Dbg_AWREADY_14 => '0',
Dbg_WREADY_14 => '0',
Dbg_BRESP_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_14 => '0',
Dbg_ARREADY_14 => '0',
Dbg_RDATA_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_14 => '0',
Dbg_TDO_15 => '0',
Dbg_Trig_In_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_15 => '0',
Dbg_AWREADY_15 => '0',
Dbg_WREADY_15 => '0',
Dbg_BRESP_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_15 => '0',
Dbg_ARREADY_15 => '0',
Dbg_RDATA_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_15 => '0',
Dbg_TDO_16 => '0',
Dbg_Trig_In_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_16 => '0',
Dbg_AWREADY_16 => '0',
Dbg_WREADY_16 => '0',
Dbg_BRESP_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_16 => '0',
Dbg_ARREADY_16 => '0',
Dbg_RDATA_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_16 => '0',
Dbg_TDO_17 => '0',
Dbg_Trig_In_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_17 => '0',
Dbg_AWREADY_17 => '0',
Dbg_WREADY_17 => '0',
Dbg_BRESP_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_17 => '0',
Dbg_ARREADY_17 => '0',
Dbg_RDATA_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_17 => '0',
Dbg_TDO_18 => '0',
Dbg_Trig_In_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_18 => '0',
Dbg_AWREADY_18 => '0',
Dbg_WREADY_18 => '0',
Dbg_BRESP_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_18 => '0',
Dbg_ARREADY_18 => '0',
Dbg_RDATA_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_18 => '0',
Dbg_TDO_19 => '0',
Dbg_Trig_In_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_19 => '0',
Dbg_AWREADY_19 => '0',
Dbg_WREADY_19 => '0',
Dbg_BRESP_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_19 => '0',
Dbg_ARREADY_19 => '0',
Dbg_RDATA_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_19 => '0',
Dbg_TDO_20 => '0',
Dbg_Trig_In_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_20 => '0',
Dbg_AWREADY_20 => '0',
Dbg_WREADY_20 => '0',
Dbg_BRESP_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_20 => '0',
Dbg_ARREADY_20 => '0',
Dbg_RDATA_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_20 => '0',
Dbg_TDO_21 => '0',
Dbg_Trig_In_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_21 => '0',
Dbg_AWREADY_21 => '0',
Dbg_WREADY_21 => '0',
Dbg_BRESP_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_21 => '0',
Dbg_ARREADY_21 => '0',
Dbg_RDATA_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_21 => '0',
Dbg_TDO_22 => '0',
Dbg_Trig_In_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_22 => '0',
Dbg_AWREADY_22 => '0',
Dbg_WREADY_22 => '0',
Dbg_BRESP_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_22 => '0',
Dbg_ARREADY_22 => '0',
Dbg_RDATA_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_22 => '0',
Dbg_TDO_23 => '0',
Dbg_Trig_In_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_23 => '0',
Dbg_AWREADY_23 => '0',
Dbg_WREADY_23 => '0',
Dbg_BRESP_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_23 => '0',
Dbg_ARREADY_23 => '0',
Dbg_RDATA_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_23 => '0',
Dbg_TDO_24 => '0',
Dbg_Trig_In_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_24 => '0',
Dbg_AWREADY_24 => '0',
Dbg_WREADY_24 => '0',
Dbg_BRESP_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_24 => '0',
Dbg_ARREADY_24 => '0',
Dbg_RDATA_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_24 => '0',
Dbg_TDO_25 => '0',
Dbg_Trig_In_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_25 => '0',
Dbg_AWREADY_25 => '0',
Dbg_WREADY_25 => '0',
Dbg_BRESP_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_25 => '0',
Dbg_ARREADY_25 => '0',
Dbg_RDATA_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_25 => '0',
Dbg_TDO_26 => '0',
Dbg_Trig_In_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_26 => '0',
Dbg_AWREADY_26 => '0',
Dbg_WREADY_26 => '0',
Dbg_BRESP_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_26 => '0',
Dbg_ARREADY_26 => '0',
Dbg_RDATA_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_26 => '0',
Dbg_TDO_27 => '0',
Dbg_Trig_In_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_27 => '0',
Dbg_AWREADY_27 => '0',
Dbg_WREADY_27 => '0',
Dbg_BRESP_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_27 => '0',
Dbg_ARREADY_27 => '0',
Dbg_RDATA_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_27 => '0',
Dbg_TDO_28 => '0',
Dbg_Trig_In_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_28 => '0',
Dbg_AWREADY_28 => '0',
Dbg_WREADY_28 => '0',
Dbg_BRESP_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_28 => '0',
Dbg_ARREADY_28 => '0',
Dbg_RDATA_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_28 => '0',
Dbg_TDO_29 => '0',
Dbg_Trig_In_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_29 => '0',
Dbg_AWREADY_29 => '0',
Dbg_WREADY_29 => '0',
Dbg_BRESP_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_29 => '0',
Dbg_ARREADY_29 => '0',
Dbg_RDATA_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_29 => '0',
Dbg_TDO_30 => '0',
Dbg_Trig_In_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_30 => '0',
Dbg_AWREADY_30 => '0',
Dbg_WREADY_30 => '0',
Dbg_BRESP_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_30 => '0',
Dbg_ARREADY_30 => '0',
Dbg_RDATA_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_30 => '0',
Dbg_TDO_31 => '0',
Dbg_Trig_In_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_31 => '0',
Dbg_AWREADY_31 => '0',
Dbg_WREADY_31 => '0',
Dbg_BRESP_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_31 => '0',
Dbg_ARREADY_31 => '0',
Dbg_RDATA_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_31 => '0',
bscan_ext_tdi => '0',
bscan_ext_reset => '0',
bscan_ext_shift => '0',
bscan_ext_update => '0',
bscan_ext_capture => '0',
bscan_ext_sel => '0',
bscan_ext_drck => '0',
Ext_JTAG_TDO => '0'
);
END system_mdm_1_0_arch;
|
apache-2.0
|
a184f031f5ee22dc8eacbe2e5eaca8b4
| 0.586557 | 2.883233 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_xlconcat_0/system_microblaze_0_xlconcat_0_sim_netlist.vhdl
| 1 | 2,740 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:44:42 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_xlconcat_0/system_microblaze_0_xlconcat_0_sim_netlist.vhdl
-- Design : system_microblaze_0_xlconcat_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_xlconcat_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
In3 : in STD_LOGIC_VECTOR ( 0 to 0 );
In4 : in STD_LOGIC_VECTOR ( 0 to 0 );
In5 : in STD_LOGIC_VECTOR ( 0 to 0 );
In6 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_microblaze_0_xlconcat_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_microblaze_0_xlconcat_0 : entity is "system_microblaze_0_xlconcat_0,xlconcat,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_microblaze_0_xlconcat_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_microblaze_0_xlconcat_0 : entity is "xlconcat,Vivado 2016.4";
end system_microblaze_0_xlconcat_0;
architecture STRUCTURE of system_microblaze_0_xlconcat_0 is
signal \^in0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^in1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^in2\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^in3\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^in4\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^in5\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^in6\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\^in0\(0) <= In0(0);
\^in1\(0) <= In1(0);
\^in2\(0) <= In2(0);
\^in3\(0) <= In3(0);
\^in4\(0) <= In4(0);
\^in5\(0) <= In5(0);
\^in6\(0) <= In6(0);
dout(6) <= \^in6\(0);
dout(5) <= \^in5\(0);
dout(4) <= \^in4\(0);
dout(3) <= \^in3\(0);
dout(2) <= \^in2\(0);
dout(1) <= \^in1\(0);
dout(0) <= \^in0\(0);
end STRUCTURE;
|
apache-2.0
|
53884639fccf1e65a6c51b38601c88a8
| 0.609124 | 3.309179 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/lib/mux/mux8.vhd
| 1 | 1,027 |
--Helpful resource:
--ftp://www.cs.uregina.ca/pub/class/301/multiplexer/lecture.html
library IEEE;
use IEEE.std_logic_1164.all;
entity mux8 is
port(
bus0 : in std_logic_vector(3 downto 0) := (others => '-');
bus1 : in std_logic_vector(3 downto 0) := (others => '-');
bus2 : in std_logic_vector(3 downto 0) := (others => '-');
bus3 : in std_logic_vector(3 downto 0) := (others => '-');
bus4 : in std_logic_vector(3 downto 0) := (others => '-');
bus5 : in std_logic_vector(3 downto 0) := (others => '-');
bus6 : in std_logic_vector(3 downto 0) := (others => '-');
bus7 : in std_logic_vector(3 downto 0) := (others => '-');
S : in std_logic_vector(2 downto 0);
R : out std_logic_vector(3 downto 0)
);
end mux8;
architecture Behavioural of mux8 is
begin
with S select
R <= bus0 when "000",
bus1 when "001",
bus2 when "010",
bus3 when "011",
bus4 when "100",
bus5 when "101",
bus6 when "110",
bus7 when others;
end Behavioural;
|
agpl-3.0
|
cb1ae789728bd8163c8151b7d7a733fb
| 0.581305 | 3.102719 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/3edf/hdl/axi_timer_v2_0_vh_rfs.vhd
| 1 | 102,160 |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
INFERRED_GEN : if (true) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
--library proc_common_v4_0_2;
--use proc_common_v4_0_2.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
--constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
constant NLS : natural := 6; --native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0_13;
use axi_timer_v2_0_13.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_13.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0_13.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0_13.TC_Types.ARHT0_POS;
use axi_timer_v2_0_13.TC_Types.ARHT1_POS;
use axi_timer_v2_0_13.TC_Types.CAPT0_POS;
use axi_timer_v2_0_13.TC_Types.CAPT1_POS;
use axi_timer_v2_0_13.TC_Types.CMPT0_POS;
use axi_timer_v2_0_13.TC_Types.CMPT1_POS;
use axi_timer_v2_0_13.TC_Types.ENALL_POS;
use axi_timer_v2_0_13.TC_Types.ENIT0_POS;
use axi_timer_v2_0_13.TC_Types.ENIT1_POS;
use axi_timer_v2_0_13.TC_Types.ENT0_POS;
use axi_timer_v2_0_13.TC_Types.ENT1_POS;
use axi_timer_v2_0_13.TC_Types.LOAD0_POS;
use axi_timer_v2_0_13.TC_Types.LOAD1_POS;
use axi_timer_v2_0_13.TC_Types.MDT0_POS;
use axi_timer_v2_0_13.TC_Types.MDT1_POS;
use axi_timer_v2_0_13.TC_Types.PWMA0_POS;
use axi_timer_v2_0_13.TC_Types.PWMB0_POS;
use axi_timer_v2_0_13.TC_Types.T0INT_POS;
use axi_timer_v2_0_13.TC_Types.T1INT_POS;
use axi_timer_v2_0_13.TC_Types.UDT0_POS;
use axi_timer_v2_0_13.TC_Types.UDT1_POS;
use axi_timer_v2_0_13.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
-------------------------------------------------------------------------------
-- count_module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: count_module.vhd
-- Version: v2.0
-- Description: Module with one counter and load register
--
-------------------------------------------------------------------------------
-- Structure:
--
-- count_module.vhd
-- -- counter_f.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_COUNT_WIDTH -- Width of the counter
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- clock
-- Reset -- reset
-- Load_DBus -- Count Load bus
-- Load_Counter_Reg -- Counter load control
-- Load_Load_Reg -- Load register control
-- Write_Load_Reg -- Write Control of TLR reg
-- CaptGen_Mux_Sel -- Mux select for capture and generate data
-- Counter_En -- Counter enable
-- Count_Down -- Count down
-- BE -- Byte enable
-- LoadReg_DBus -- Load reg bus
-- CounterReg_DBus -- Counter reg bus
-- Counter_TC -- counter Carry out signal
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.FDRE;
library axi_timer_v2_0_13;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity count_module is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32
);
port (
Clk : in std_logic;
Reset : in std_logic;
Load_DBus : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Load_Counter_Reg : in std_logic;
Load_Load_Reg : in std_logic;
Write_Load_Reg : in std_logic;
CaptGen_Mux_Sel : in std_logic;
Counter_En : in std_logic;
Count_Down : in std_logic;
BE : in std_Logic_vector(0 to 3);
LoadReg_DBus : out std_logic_vector(0 to C_COUNT_WIDTH-1);
CounterReg_DBus : out std_logic_vector(0 to C_COUNT_WIDTH-1);
Counter_TC : out std_logic
);
end entity count_module;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of count_module is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Signal Declaration
signal iCounterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal loadRegIn : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal load_Reg : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal load_load_reg_be : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal carry_out : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- Architecture imp
-------------------------------------------------------------------------------
--CAPTGEN_MUX_PROCESS : Process to implement mux the Load_DBus and
--iCounterReg_DBus
-------------------------------------------------------------------------------
CAPTGEN_MUX_PROCESS: process (CaptGen_Mux_Sel,Load_DBus,iCounterReg_DBus ) is
begin
if CaptGen_Mux_Sel='1' then
loadRegIn <= Load_DBus;
else
loadRegIn <= iCounterReg_DBus;
end if;
end process CAPTGEN_MUX_PROCESS;
-------------------------------------------------------------------------------
--LOAD_REG_GEN: To generate load register
-------------------------------------------------------------------------------
LOAD_REG_GEN: for i in 0 to C_COUNT_WIDTH-1 generate
load_load_reg_be(i) <= Load_Load_Reg or
(Write_Load_Reg and BE((i-C_COUNT_WIDTH+32)/8));
LOAD_REG_I: component FDRE
port map (
Q => load_Reg(i), -- [out]
C => Clk, -- [in]
CE => load_load_reg_be(i), -- [in]
D => loadRegIn(i), -- [in]
R => Reset -- [in]
);
end generate LOAD_REG_GEN;
-------------------------------------------------------------------------------
--counter_f module is instantiated
-------------------------------------------------------------------------------
COUNTER_I: entity axi_timer_v2_0_13.counter_f
generic map (
C_NUM_BITS => C_COUNT_WIDTH, -- [integer]
C_FAMILY => C_FAMILY -- [string]
)
port map(
Clk => Clk, -- [in std_logic]
Rst => Reset, -- [in std_logic]
Load_In => load_Reg, -- [in std_logic_vector]
Count_Enable => Counter_En, -- [in std_logic]
Count_Load => Load_Counter_Reg, -- [in std_logic]
Count_Down => Count_Down, -- [in std_logic]
Count_Out => iCounterReg_DBus, -- [out std_logic_vector]
Carry_Out => carry_out -- [out std_logic]
);
Counter_TC <= carry_out;
LoadReg_DBus <= load_Reg;
CounterReg_DBus <= iCounterReg_DBus;
end architecture imp;
-------------------------------------------------------------------------------
-- TC_Core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_core.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Dual Timer/Counter for PLB bus
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_AWIDTH -- PLB address bus width
-- C_DWIDTH -- PLB data bus width
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- PLB Clock
-- Rst -- PLB Reset
-- Bus2ip_addr -- bus to ip address bus
-- Bus2ip_be -- byte enables
-- Bus2ip_data -- bus to ip data bus
--
-- TC_DBus -- ip to bus data bus
-- bus2ip_rdce -- read select
-- bus2ip_wrce -- write select
-- ip2bus_rdack -- read acknowledge
-- ip2bus_wrack -- write acknowledge
-- TC_errAck -- error acknowledge
-------------------------------------------------------------------------------
-- Timer/Counter signals
-------------------------------------------------------------------------------
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- PWM0 -- Pulse Width Modulation Ouput 0
-- Interrupt -- Interrupt
-- Freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_13;
use axi_timer_v2_0_13.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_13.TC_Types.PWMA0_POS;
use axi_timer_v2_0_13.TC_Types.PWMB0_POS;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
library unisim;
use unisim.vcomponents.FDRS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity tc_core is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 5;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Rst : in std_logic;
-- PLB signals
Bus2ip_addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2ip_be : in std_logic_vector(0 to 3);
Bus2ip_data : in std_logic_vector(0 to 31);
TC_DBus : out std_logic_vector(0 to 31);
bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
TC_errAck : out std_logic;
-- PTC signals
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic
);
end entity tc_core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of tc_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Attribute declaration
attribute syn_keep : boolean;
--Signal declaration
signal load_Counter_Reg : std_logic_vector(0 to 1);
signal load_Load_Reg : std_logic_vector(0 to 1);
signal write_Load_Reg : std_logic_vector(0 to 1);
signal captGen_Mux_Sel : std_logic_vector(0 to 1);
signal loadReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal counterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal tCSR0_Reg : QUADLET_TYPE;
signal tCSR1_Reg : QUADLET_TYPE;
signal counter_TC : std_logic_vector(0 to 1);
signal counter_En : std_logic_vector(0 to 1);
signal count_Down : std_logic_vector(0 to 1);
attribute syn_keep of count_Down : signal is true;
signal iPWM0 : std_logic;
signal iGenerateOut0 : std_logic;
signal iGenerateOut1 : std_logic;
signal pwm_Reset : std_logic;
signal Read_Reg_In : QUADLET_TYPE;
signal read_Mux_In : std_logic_vector(0 to 6*32-1);
signal read_Mux_S : std_logic_vector(0 to 5);
begin -- architecture imp
-----------------------------------------------------------------------------
-- Generating the acknowledgement/error signals
-----------------------------------------------------------------------------
ip2bus_rdack <= (Bus2ip_rdce(0) or Bus2ip_rdce(1) or Bus2ip_rdce(2) or
Bus2ip_rdce(4) or Bus2ip_rdce(5) or
Bus2ip_rdce(6) or Bus2ip_rdce(7));
ip2bus_wrack <= (Bus2ip_wrce(0) or Bus2ip_wrce(1) or Bus2ip_wrce(2) or
Bus2ip_wrce(4) or Bus2ip_wrce(5) or
Bus2ip_wrce(6) or Bus2ip_wrce(7));
--TCR0 AND TCR1 is read only register, hence writing to these register
--will not generate error ack.
--Modify TC_errAck <= (Bus2ip_wrce(2)or Bus2ip_wrce(6)) on 11/11/08 to;
TC_errAck <= '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--Process :READ_MUX_INPUT
-----------------------------------------------------------------------------
READ_MUX_INPUT: process (TCSR0_Reg,TCSR1_Reg,LoadReg_DBus,CounterReg_DBus) is
begin
read_Mux_In(0 to 19) <= (others => '0');
read_Mux_In(20 to 31) <= TCSR0_Reg(20 to 31);
read_Mux_In(32 to 52) <= (others => '0');
read_Mux_In(53 to 63) <= TCSR1_Reg(21 to 31);
if C_COUNT_WIDTH < C_DWIDTH then
for i in 1 to C_DWIDTH-C_COUNT_WIDTH loop
read_Mux_In(63 +i) <= '0';
read_Mux_In(95 +i) <= '0';
read_Mux_In(127+i) <= '0';
read_Mux_In(159+i) <= '0';
end loop;
end if;
read_Mux_In(64 +C_DWIDTH-C_COUNT_WIDTH to 95) <=
LoadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(96 +C_DWIDTH-C_COUNT_WIDTH to 127) <=
LoadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
read_Mux_In(128+C_DWIDTH-C_COUNT_WIDTH to 159) <=
CounterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(160+C_DWIDTH-C_COUNT_WIDTH to 191) <=
CounterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
end process READ_MUX_INPUT;
---------------------------------------------------------
-- Create read mux select input
-- Bus2ip_rdce(0) -->TCSR0 REG READ ENABLE
-- Bus2ip_rdce(4) -->TCSR1 REG READ ENABLE
-- Bus2ip_rdce(1) -->TLR0 REG READ ENABLE
-- Bus2ip_rdce(5) -->TLR1 REG READ ENABLE
-- Bus2ip_rdce(2) -->TCR0 REG READ ENABLE
-- Bus2ip_rdce(6) -->TCR1 REG READ ENABLE
---------------------------------------------------------
read_Mux_S <= Bus2ip_rdce(0) & Bus2ip_rdce(4)& Bus2ip_rdce(1)
& Bus2ip_rdce(5) & Bus2ip_rdce(2) & Bus2ip_rdce(6);
-- mux_onehot_f
READ_MUX_I: entity axi_timer_v2_0_13.mux_onehot_f
generic map(
C_DW => 32,
C_NB => 6,
C_FAMILY => C_FAMILY)
port map(
D => read_Mux_In, --[in]
S => read_Mux_S, --[in]
Y => Read_Reg_In --[out]
);
--slave to bus data bus assignment
TC_DBus <= Read_Reg_In ;
------------------------------------------------------------------
------------------------------------------------------------------
-- COUNTER MODULE
------------------------------------------------------------------
COUNTER_0_I: entity axi_timer_v2_0_13.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(0), --[in]
Load_Load_Reg => load_Load_Reg(0), --[in]
Write_Load_Reg => write_Load_Reg(0), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(0), --[in]
Counter_En => counter_En(0), --[in]
Count_Down => count_Down(0), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
Counter_TC => counter_TC(0) --[out]
);
----------------------------------------------------------------------
--GEN_SECOND_TIMER:SECOND COUNTER MODULE IS ADDED TO DESIGN
--WHEN C_ONE_TIMER_ONLY /= 1
----------------------------------------------------------------------
GEN_SECOND_TIMER: if C_ONE_TIMER_ONLY /= 1 generate
COUNTER_1_I: entity axi_timer_v2_0_13.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(1), --[in]
Load_Load_Reg => load_Load_Reg(1), --[in]
Write_Load_Reg => write_Load_Reg(1), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(1), --[in]
Counter_En => counter_En(1), --[in]
Count_Down => count_Down(1), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
Counter_TC => counter_TC(1) --[out]
);
end generate GEN_SECOND_TIMER;
----------------------------------------------------------------------
--GEN_NO_SECOND_TIMER: GENERATE WHEN C_ONE_TIMER_ONLY = 1
----------------------------------------------------------------------
GEN_NO_SECOND_TIMER: if C_ONE_TIMER_ONLY = 1 generate
loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counter_TC(1) <= '0';
end generate GEN_NO_SECOND_TIMER;
----------------------------------------------------------------------
--TIMER_CONTROL_I: TIMER_CONTROL MODULE
----------------------------------------------------------------------
TIMER_CONTROL_I: entity axi_timer_v2_0_13.timer_control
generic map (
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Clk => Clk, -- [in]
Reset => Rst, -- [in]
CaptureTrig0 => CaptureTrig0, -- [in]
CaptureTrig1 => CaptureTrig1, -- [in]
GenerateOut0 => iGenerateOut0, -- [out]
GenerateOut1 => iGenerateOut1, -- [out]
Interrupt => Interrupt, -- [out]
Counter_TC => counter_TC, -- [in]
Bus2ip_data => Bus2ip_data, -- [in]
BE => Bus2ip_be, -- [in]
Load_Counter_Reg => load_Counter_Reg, -- [out]
Load_Load_Reg => load_Load_Reg, -- [out]
Write_Load_Reg => write_Load_Reg, -- [out]
CaptGen_Mux_Sel => captGen_Mux_Sel, -- [out]
Counter_En => counter_En, -- [out]
Count_Down => count_Down, -- [out]
Bus2ip_rdce => Bus2ip_rdce, -- [in]
Bus2ip_wrce => Bus2ip_wrce, -- [in]
Freeze => Freeze, -- [in]
TCSR0_Reg => tCSR0_Reg(20 to 31), -- [out]
TCSR1_Reg => tCSR1_Reg(21 to 31) -- [out]
);
tCSR0_Reg (0 to 19) <= (others => '0');
tCSR1_Reg (0 to 20) <= (others => '0');
pwm_Reset <= iGenerateOut1 or
(not tCSR0_Reg(PWMA0_POS) and not tCSR1_Reg(PWMB0_POS));
PWM_FF_I: component FDRS
port map (
Q => iPWM0, -- [out]
C => Clk, -- [in]
D => iPWM0, -- [in]
R => pwm_Reset, -- [in]
S => iGenerateOut0 -- [in]
);
PWM0 <= iPWM0;
GenerateOut0 <= iGenerateOut0;
GenerateOut1 <= iGenerateOut1;
end architecture IMP;
-------------------------------------------------------------------------------
-- xps_timer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :axi_timer.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Timer/Counter for AXI
-- Standard :VHDL-93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_timer.
--
-- axi_timer.vhd
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-- --tc_types.vhd
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
--
--
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-------------------------------------------------------------------------------
-- timer/counter signals
-------------------------------------------------------------------------------
-- capturetrig0 -- Capture Trigger 0
-- capturetrig1 -- Capture Trigger 1
-- generateout0 -- Generate Output 0
-- generateout1 -- Generate Output 1
-- pwm0 -- Pulse Width Modulation Ouput 0
-- interrupt -- Interrupt
-- freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_13;
library axi_lite_ipif_v3_0_4;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity axi_timer is
generic (
C_FAMILY : string := "virtex7";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
-- axi lite ipif block generics
C_S_AXI_DATA_WIDTH: integer := 32;
C_S_AXI_ADDR_WIDTH: integer := 5 --5
);
port
(
--Timer/Counter signals
capturetrig0 : in std_logic;
capturetrig1 : in std_logic;
generateout0 : out std_logic;
generateout1 : out std_logic;
pwm0 : out std_logic;
interrupt : out std_logic;
freeze : in std_logic;
--system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic := '1';
s_axi_awaddr : in std_logic_vector(4 downto 0);
--(c_s_axi_addr_width-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
-- (c_s_axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
-- ((c_s_axi_data_width/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(4 downto 0);
--(c_s_axi_addr_width-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
--(c_s_axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN: signal is "10000";
end entity axi_timer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of axi_timer is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
constant ZEROES : std_logic_vector(0 to 31) := X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- Timer registers Base Address
ZEROES & X"00000000",
ZEROES & X"0000001F"
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8
);
constant C_S_AXI_MIN_SIZE :std_logic_vector(31 downto 0):= X"0000001F";
constant C_USE_WSTRB :integer := 0;
constant C_DPHASE_TIMEOUT :integer range 0 to 256 := 32;
--Signal declaration --------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_reset : std_logic;
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1)
:=(others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
-----------------------------------------------------------------------
signal bus2ip_data : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_be : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH/8-1 );
signal bus2ip_rdce : std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
TC_CORE_I: entity axi_timer_v2_0_13.tc_core
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH,
C_ONE_TIMER_ONLY => C_ONE_TIMER_ONLY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_AWIDTH => C_S_AXI_ADDR_WIDTH,
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
-- IPIF signals
Clk => bus2ip_clk, --[in]
Rst => bus2ip_reset, --[in]
Bus2ip_addr => bus2ip_addr, --[in]
Bus2ip_be => bus2ip_be, --[in]
Bus2ip_data => bus2ip_data, --[in]
TC_DBus => ip2bus_data, --[out]
bus2ip_rdce => bus2ip_rdce, --[in]
bus2ip_wrce => bus2ip_wrce, --[in]
ip2bus_rdack => ip2bus_rdack, --[out]
ip2bus_wrack => ip2bus_wrack, --[out]
TC_errAck => ip2bus_error, --[out]
-- Timer/Counter signals
CaptureTrig0 => capturetrig0, --[in]
CaptureTrig1 => capturetrig1, --[in]
GenerateOut0 => generateout0, --[out]
GenerateOut1 => generateout1, --[out]
PWM0 => pwm0, --[out]
Interrupt => interrupt, --[out]
Freeze => freeze --[in]
);
---------------------------------------------------------------------------
-- INSTANTIATE AXI Lite IPIF
---------------------------------------------------------------------------
AXI4_LITE_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals -------------------------------
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => open,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
bus2ip_reset <= not bus2ip_resetn;
end architecture imp;
|
apache-2.0
|
4f129356977c4a6bbcf5c8341ccc6a3d
| 0.456588 | 4.295866 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/Keyboard/keyboard_controller_tb.vhd
| 1 | 5,600 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: KEYBOARD_CONTROLLER Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY KEYBOARD_CONTROLLER_tb_vhd IS
END KEYBOARD_CONTROLLER_tb_vhd;
ARCHITECTURE behavior OF KEYBOARD_CONTROLLER_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT KEYBOARD_CONTROLLER
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
ASCII_OUT: out STD_LOGIC_VECTOR (7 downto 0);
ASCII_RD : out STD_LOGIC;
ASCII_WE : out STD_LOGIC);
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
SIGNAL PS2_CLK : STD_LOGIC := '1';
SIGNAL PS2_DATA: STD_LOGIC := '1';
SIGNAL ASCII_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL ASCII_RD: STD_LOGIC := '0';
SIGNAL ASCII_WE: STD_LOGIC := '0';
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: KEYBOARD_CONTROLLER PORT MAP( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA=> PS2_DATA,
ASCII_OUT => ASCII_OUT,
ASCII_RD=> ASCII_RD,
ASCII_WE=> ASCII_WE);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 us;
report "Start VGA_Controller Test Bench" severity NOTE;
--Simulate Pressing A
--Sending the Break Code X"F0"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
--Sending the Key Code X"1C"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '0';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
wait; -- will wait forever
END PROCESS;
END;
|
mit
|
2e67508ccc303155a471eaecceb31661
| 0.440536 | 3.408399 | false | false | false | false |
hly11/CollisionDetectionFPGA
|
hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_vdma_0_4/synth/design_1_axi_vdma_0_4.vhd
| 1 | 28,345 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2;
USE axi_vdma_v6_2.axi_vdma;
ENTITY design_1_axi_vdma_0_4 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC
);
END design_1_axi_vdma_0_4;
ARCHITECTURE design_1_axi_vdma_0_4_arch OF design_1_axi_vdma_0_4 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_vdma_0_4_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_vdma_0_4_arch: ARCHITECTURE IS "axi_vdma,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_vdma_0_4_arch : ARCHITECTURE IS "design_1_axi_vdma_0_4,axi_vdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_vdma_0_4_arch: ARCHITECTURE IS "design_1_axi_vdma_0_4,axi_vdma,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=0,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=3,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=512,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=1,C_S2MM_GENLOCK_MODE=2,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_10=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXIS_S2MM_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 S2MM_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 0,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 3,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 512,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 1,
C_S2MM_GENLOCK_MODE => 2,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
s_axis_s2mm_aclk => s_axis_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => '0',
mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
s2mm_frame_ptr_out => s2mm_frame_ptr_out,
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tuser => s_axis_s2mm_tuser,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut
);
END design_1_axi_vdma_0_4_arch;
|
gpl-2.0
|
620606f1db4fc2274c863bedb0441402
| 0.677509 | 2.730995 | false | false | false | false |
daniw/add
|
cpu/cpu_prc.vhd
| 1 | 2,340 |
-------------------------------------------------------------------------------
-- Entity: cpu_prc
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Program Counter unit for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 8 + 2
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_prc is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
ctr_in : in t_ctr2prc;
ctr_out : out t_prc2ctr
);
end cpu_prc;
architecture rtl of cpu_prc is
-- program counter and exception signals
signal pc : std_logic_vector(AW-1 downto 0);
signal exc : t_addr_exc;
begin
-- assign outputs
ctr_out.pc <= pc;
ctr_out.exc <= exc;
-----------------------------------------------------------------------------
-- Program Counter
-----------------------------------------------------------------------------
P_pc: process(clk, rst)
variable v_pc : std_logic_vector(AW-1 downto 0);
variable v_addr : std_logic_vector(AW downto 0);
begin
if rst = '1' then
pc <= (others => '0');
exc <= no_err;
elsif rising_edge(clk) then
if ctr_in.enb = '1' then
exc <= no_err; -- default assignment
case ctr_in.mode is
when linear =>
-- PC := PC + 1
v_pc := std_logic_vector(unsigned(pc) + 1);
if unsigned(v_pc) >= unsigned(BA(RAM)) then
-- PC would leave ROM address space
-- do not increment and issue error
exc <= lin_err;
else
pc <= v_pc;
end if;
when abs_jump =>
-- PC := addr
pc <= ctr_in.addr;
when rel_offset =>
-- PC := PC + addr
v_addr := std_logic_vector(unsigned('0' & pc) + unsigned(ctr_in.addr));
pc <= v_addr(AW-1 downto 0);
if v_addr(AW) = '1' then
exc <= rel_err;
end if;
when others => null;
end case;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
59e70f289f15b28d3bba3eefad721382
| 0.411111 | 4.270073 | false | false | false | false |
jeffmagina/ECE368
|
Project1/WRITE_BACK/write_back.vhd
| 1 | 1,809 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:43:03 03/25/2015
-- Design Name:
-- Module Name: write_back - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
entity write_back is
Port( CLK : IN STD_LOGIC;
DATA_WE : IN STD_LOGIC;
FPU_IN : IN STD_LOGIC_VECTOR (15 downto 0);
REG_A : IN STD_LOGIC_VECTOR (15 downto 0);
D_OUT_SEL : IN STD_LOGIC;
WB_OUT : OUT STD_LOGIC_VECTOR (15 downto 0)
);
end write_back;
architecture Structural of write_back is
signal s_Reg_Out, s_Reg_A_Out, s_Data_Mem_Out, s_MUX_WB_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal InvCLK : STD_LOGIC;
begin
InvCLK <= not CLK;
U0: entity work.Register_RE_16
Port Map( CLK => CLK,
ENB => '1',
D => FPU_IN,
Q => s_Reg_Out
);
U1: entity work.Register_RE_16
Port Map( CLK => CLK,
ENB => '1',
D => REG_A,
Q => s_Reg_A_Out
);
U2: entity work.Data_MEM
Port Map( CLKA => InvCLK,
WEA(0) => DATA_WE,
ADDRA => s_Reg_Out(7 downto 0), -- (7 DOWNTO 0)
DINA => s_Reg_A_Out, -- (15 DOWNTO 0)
CLKB => CLK,
ADDRB => FPU_IN(7 downto 0), -- (7 DOWNTO 0)
DOUTB => s_Data_Mem_Out);
U3: entity work.mux2to1
Port Map( SEL => D_OUT_SEL,
DATA_0 => s_Data_Mem_Out,
DATA_1 => s_Reg_Out,
OUTPUT => WB_OUT
);
end Structural;
|
mit
|
2bc5bd9c05a81a43f8e769735f01f55f
| 0.505252 | 3.040336 | false | false | false | false |
daniw/add
|
floppy/mcu/mcu.vhd
| 1 | 5,071 |
-------------------------------------------------------------------------------
-- Entity: mcu
-- Author: Waj
-------------------------------------------------------------------------------
-- Top-level description of a simple von-Neumann MCU.
-- All top-level component are instantiated here. Also, tri-state buffers for
-- bi-directional GPIO pins are described here.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity mcu is
port(rst : in std_logic;
clk : in std_logic;
-- General-Purpose I/O ports
-- GPIO_0 : inout std_logic_vector(DW-1 downto 0);
-- GPIO_1 : inout std_logic_vector(DW-1 downto 0);
-- GPIO_2 : inout std_logic_vector(DW-1 downto 0);
-- GPIO_3 : inout std_logic_vector(DW-1 downto 0);
-- Dedicated LCD port
LCD : out std_logic_vector(LCD_PW-1 downto 0);
-- LEDs Switches and Buttons
LED : out std_logic_vector(7 downto 0);
SW : in std_logic_vector(3 downto 0);
ROT_C : in std_logic;
BTN_EAST : in std_logic;
BTN_WEST : in std_logic;
BTN_NORTH : in std_logic;
step_to_floppy : out std_logic;
dir_to_floppy : out std_logic
en_to_floppy : out std_logic
);
end mcu;
architecture rtl of mcu is
-- CPU signals
signal cpu2bus : t_cpu2bus;
signal bus2cpu : t_bus2cpu;
-- ROM signals
signal bus2rom : t_bus2ros;
signal rom2bus : t_ros2bus;
-- ROM signals
signal bus2ram : t_bus2rws;
signal ram2bus : t_rws2bus;
-- GPIO signals
signal bus2gpio : t_bus2rws;
signal gpio2bus : t_rws2bus;
--signal gpio_in : t_gpio_pin_in;
--signal gpio_out : t_gpio_pin_out;
-- LCD signals
signal bus2lcd : t_bus2rws;
signal lcd2bus : t_rws2bus;
signal lcd_out : std_logic_vector(LCD_PW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Tri-state buffers for GPIO pins
-----------------------------------------------------------------------------
-- gpio_in.in_0 <= GPIO_0;
-- gpio_in.in_1 <= GPIO_1;
-- gpio_in.in_2 <= GPIO_2;
-- gpio_in.in_3 <= GPIO_3;
-- gen_gpin: for k in 0 to DW-1 generate
-- GPIO_0(k) <= gpio_out.out_0(k) when gpio_out.enb_0(k) = '1' else 'Z';
-- GPIO_1(k) <= gpio_out.out_1(k) when gpio_out.enb_1(k) = '1' else 'Z';
-- GPIO_2(k) <= gpio_out.out_2(k) when gpio_out.enb_2(k) = '1' else 'Z';
-- GPIO_3(k) <= gpio_out.out_3(k) when gpio_out.enb_3(k) = '1' else 'Z';
-- end generate;
-----------------------------------------------------------------------------
-- LCD interface pins
-----------------------------------------------------------------------------
LCD <= lcd_out;
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- CPU ----------------------------------------------------------------------
i_cpu: entity work.cpu
port map(
rst => rst,
clk => clk,
bus_in => bus2cpu,
bus_out => cpu2bus
);
-- BUS ----------------------------------------------------------------------
i_bus: entity work.buss
port map(
rst => rst,
clk => clk,
cpu_in => cpu2bus,
cpu_out => bus2cpu,
rom_in => rom2bus,
rom_out => bus2rom,
ram_in => ram2bus,
ram_out => bus2ram,
gpio_in => gpio2bus,
gpio_out => bus2gpio,
lcd_in => lcd2bus,
lcd_out => bus2lcd
);
-- ROM ----------------------------------------------------------------------
i_rom: entity work.rom
port map(
clk => clk,
bus_in => bus2rom,
bus_out => rom2bus
);
-- RAM ----------------------------------------------------------------------
i_ram: entity work.ram
port map(
clk => clk,
bus_in => bus2ram,
bus_out => ram2bus
);
-- GPIO ---------------------------------------------------------------------
i_gpio: entity work.gpio
port map(
rst => rst,
clk => clk,
bus_in => bus2gpio,
bus_out => gpio2bus,
-- pin_in => gpio_in,
-- pin_out => gpio_out,
to_LED => LED,
from_SW => SW,
from_BTN_ROT_C => ROT_C,
from_BTN_EAST => BTN_EAST,
from_BTN_WEST => BTN_WEST,
from_BTN_NORTH => BTN_NORTH,
step_to_floppy => step_to_floppy,
dir_to_floppy => dir_to_floppy
en_to_floppy => en_to_floppy
);
-- LCD ----------------------------------------------------------------------
i_lcd: entity work.lcd
port map(
rst => rst,
clk => clk,
bus_in => bus2lcd,
bus_out => lcd2bus,
lcd_out => lcd_out
);
end rtl;
|
gpl-2.0
|
796824b7653d7bc00c69f4e7dee37e61
| 0.416486 | 3.764662 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG/ASCII_BUFFER.vhd
| 2 | 3,165 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: DEBUG UNIT
-- Project Name: DEBUG UNIT
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debug Unit for part 4 of Lab 1
-- Takes in a 0 - F on the ASCII_DATA line
-- and outputs it to the BUFFER concatenated
-- together to form the Instruction
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ASCII_BUFFER is
port(
ASCII_DATA : in STD_LOGIC_VECTOR(7 downto 0);
ASCII_RD: in STD_LOGIC;
ASCII_WE: in STD_LOGIC;
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
ASCII_BUFF: out STD_LOGIC_VECTOR(15 downto 0)
);
end ASCII_BUFFER;
architecture dataflow of ASCII_BUFFER is
type StateType is (init, idle, VALID_KEY, SPECIAL_KEY, BACKSPACE, FLUSH);
signal STATE : StateType := init;
type ram_type is array (0 to 4) of STD_LOGIC_VECTOR(3 downto 0);
signal ram_addr : integer range 0 to 4;
signal ram : ram_type;
signal KEY : STD_LOGIC_VECTOR(3 downto 0);
signal INST: STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
with ASCII_DATA select
KEY <=
x"f" when x"66",
x"e" when x"65",
x"d" when x"64",
x"c" when x"63",
x"b" when x"62",
x"a" when x"61",
x"F" when x"46",
x"E" when x"45",
x"D" when x"44",
x"C" when x"43",
x"B" when x"42",
x"A" when x"41",
x"9" when x"39",
x"8" when x"38",
x"7" when x"37",
x"6" when x"36",
x"5" when x"35",
x"4" when x"34",
x"3" when x"33",
x"2" when x"32",
x"1" when x"31",
x"0" when x"30",
x"0" when OTHERS; -- Null
PROCESS(CLK,RST)
BEGIN
if(RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '1' ) then
case STATE is
when init =>
ASCII_BUFF <= (OTHERS => '0');
ram(0) <= x"0";
ram(1) <= x"0";
ram(2) <= x"0";
ram(3) <= x"0";
ram_addr <= 0;
state <= idle;
when idle =>
ASCII_BUFF <= INST;
if ASCII_RD = '1' and ASCII_WE = '1' then
state <= VALID_KEY;
-- A Valid key was pressed
elsif ASCII_RD = '1' and ASCII_WE = '0' then
state <= SPECIAL_KEY;
--Special key was pressed
else
state <= idle;
end if;
when VALID_KEY =>
if ram_addr < 4 then
ram(ram_addr) <= key;
ram_addr <= ram_addr + 1;
else
ram_addr <= 4;
end if;
state <= idle;
when SPECIAL_KEY =>
if ASCII_DATA = x"0D" then --0D = enterkey
state <= FLUSH;
elsif ASCII_DATA = x"08" then -- 08 = backspace
state <= BACKSPACE;
else
state <= idle;
end if;
when BACKSPACE =>
if ram_addr > 0 then
ram_addr <= ram_addr - 1;
end if;
ram(ram_addr) <= x"0";
state <= idle;
when FLUSH =>
INST <= ram(0) & ram(1) & ram(2) & ram(3);
state <= init;
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
|
mit
|
f65cd8e263504d05a33aaf0e1eacef1c
| 0.551027 | 2.901008 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/RF_tb.vhd
| 1 | 2,238 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal rd : std_logic_vector(4 downto 0) := (others => '0');
signal DWR : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal Crs1 : std_logic_vector(31 downto 0);
signal Crs2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RF PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
DWR => DWR,
rst => rst,
Crs1 => Crs1,
Crs2 => Crs2
);
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
rs1<=(others=>'0');
rs2<="01000";
rd<="00001";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="11001";
rd<="00010";
DWR<="11111111111111111111111111111001";
wait for 40 ns;
rs1<="00001";
rs2<="00010";
rd<="01000";
DWR<="00000000000001000101111011111111";
wait for 40 ns;
rd<="01001";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rd<="01010";
DWR<="00000000000000000000000000001001";
wait for 40 ns;
rd<="01011";
DWR<="00000000000000000000000000001010";
wait for 40 ns;
rd<="01100";
DWR<="00000000000000000000000000001011";
wait for 40 ns;
rst<='1';
rs1<="00001";
rs2<="00010";
rd<="01101";
DWR<="00000000000000000000000000001100";
wait for 40 ns;
wait;
end process;
END;
|
mit
|
59ed6839986fb9587481adab3c705f3e
| 0.552726 | 3.546751 | false | false | false | false |
daniw/add
|
rot_enc/cpu_alu.vhd
| 3 | 7,503 |
-------------------------------------------------------------------------------
-- Entity: cpu_alu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- ALU for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_alu is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
alu_in : in t_ctr2alu;
alu_out : out t_alu2ctr;
oper1 : in std_logic_vector(DW-1 downto 0);
oper2 : in std_logic_vector(DW-1 downto 0);
result : out std_logic_vector(DW-1 downto 0)
);
end cpu_alu;
architecture rtl of cpu_alu is
signal result_reg : std_logic_vector(DW-1 downto 0);
signal alu_enb_reg : std_logic;
signal imml : std_logic_vector(DW-1 downto 0);
signal immh : std_logic_vector(DW-1 downto 0);
constant ext_0 : std_logic_vector(IOWW-1 downto 0) := (others => '0');
constant ext_1 : std_logic_vector(IOWW-1 downto 0) := (others => '1');
begin
-- output assignment
result <= result_reg;
-- helper signals for addil/addih instructions with sign extension
imml <= (ext_0 & alu_in.imm) when alu_in.imm(alu_in.imm'left) = '0' else
(ext_1 & alu_in.imm);
immh <= alu_in.imm & ext_0;
-----------------------------------------------------------------------------
-- ALU operations (ISE workaround)
-----------------------------------------------------------------------------
P_alu: process(clk)
begin
if rising_edge(clk) then
if to_integer(unsigned(alu_in.op)) = 0 then -- add
result_reg <= std_logic_vector(unsigned(oper1) + unsigned(oper2));
elsif to_integer(unsigned(alu_in.op)) = 1 then -- sub
result_reg <= std_logic_vector(unsigned(oper1) - unsigned(oper2));
elsif to_integer(unsigned(alu_in.op)) = 2 then -- and
result_reg <= oper1 and oper2;
elsif to_integer(unsigned(alu_in.op)) = 3 then -- or
result_reg <= oper1 or oper2;
elsif to_integer(unsigned(alu_in.op)) = 4 then -- xor
result_reg <= oper1 xor oper2;
elsif to_integer(unsigned(alu_in.op)) = 5 then -- slai
result_reg <= oper1(DW-2 downto 0) & '0';
elsif to_integer(unsigned(alu_in.op)) = 6 then -- srai
result_reg <= oper1(DW-1) & oper1(DW-1 downto 1);
elsif to_integer(unsigned(alu_in.op)) = 7 then -- mov
result_reg <= oper1;
elsif to_integer(unsigned(alu_in.op)) = 12 then -- addil
result_reg <= std_logic_vector(unsigned(oper1) + unsigned(imml));
elsif to_integer(unsigned(alu_in.op)) = 13 then -- addih
result_reg <= std_logic_vector(unsigned(oper1) + unsigned(immh));
elsif to_integer(unsigned(alu_in.op)) = 14 then -- setil
result_reg <= oper1(DW-1 downto DW/2) & alu_in.imm;
elsif to_integer(unsigned(alu_in.op)) = 15 then -- setih
result_reg <= alu_in.imm & oper1(DW/2-1 downto 0);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- More elegant solution using type attribute 'val. Unfortunately, this
-- attribute is not supported by ISE XST, but works fine with Vivado.
-- (also note that the complementary attribute to 'val is 'pos)
-- ToDo: register!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-----------------------------------------------------------------------------
g_NOT_ISE: if not ISE_TOOL generate
with t_alu_instr'val(to_integer(unsigned(alu_in.op))) select result_reg <=
std_logic_vector(unsigned(oper1) + unsigned(oper2)) when add,
std_logic_vector(unsigned(oper1) - unsigned(oper2)) when sub,
oper1 or oper2 when andi,
oper1 or oper2 when ori,
oper1 xor oper2 when xori,
oper1(DW-2 downto 0) & '0' when slai,
oper1(DW-1) & oper1(DW-1 downto 1) when srai,
oper1 when mov,
std_logic_vector(unsigned(oper1) + unsigned(imml)) when addil,
std_logic_vector(unsigned(oper1) + unsigned(immh)) when addih,
(others =>'0') when others;
end generate g_NOT_ISE;
-----------------------------------------------------------------------------
-- Update and register flags N, Z, C, O from registerd ALU results
-----------------------------------------------------------------------------
P_flag: process(clk)
variable v_op2 : std_logic_vector(DW-1 downto 0);
begin
if rising_edge(clk) then
-- regsiter enable from CPU_CTRL ----------------------------------------
alu_enb_reg <= alu_in.enb;
-- flag update with registered enable and registered ALU result ---------
if alu_enb_reg = '1' then
-- get correct Operand 2 for add/addil/addih
if (to_integer(unsigned(alu_in.op)) = 0) then
v_op2 := oper2; --add
elsif (to_integer(unsigned(alu_in.op)) = 12) then
v_op2 := imml; --addil
else
v_op2 := immh; --addih
end if;
-- N, updated with each operation -------------------------------------
alu_out.flag(N) <= result_reg(DW-1);
-- Z, updated with each operation -------------------------------------
alu_out.flag(Z) <= '0';
if to_integer(unsigned(result_reg)) = 0 then
alu_out.flag(Z) <= '1';
end if;
-- C, updated with add/addil/addih/sub only ---------------------------
if (to_integer(unsigned(alu_in.op)) = 0) or
(to_integer(unsigned(alu_in.op)) = 12) or
(to_integer(unsigned(alu_in.op)) = 13) then
-- add/addil/addih (use v_op2)
alu_out.flag(C) <= (oper1(DW-1) and v_op2(DW-1)) or
(oper1(DW-1) and not result_reg(DW-1)) or
(v_op2(DW-1) and not result_reg(DW-1));
elsif to_integer(unsigned(alu_in.op)) = 1 then
-- sub (use oper2)
alu_out.flag(C) <= (oper2(DW-1) and not oper1(DW-1)) or
(result_reg(DW-1) and not oper1(DW-1)) or
(oper2(DW-1) and result_reg(DW-1));
end if;
-- O, updated with add/addil/addih/sub only ---------------------------
if (to_integer(unsigned(alu_in.op)) = 0) or
(to_integer(unsigned(alu_in.op)) = 12) or
(to_integer(unsigned(alu_in.op)) = 13) then
-- add/addil/addih (use v_op2)
alu_out.flag(O) <= (not oper1(DW-1) and not v_op2(DW-1) and result_reg(DW-1)) or
( oper1(DW-1) and v_op2(DW-1) and not result_reg(DW-1));
elsif to_integer(unsigned(alu_in.op)) = 1 then
-- sub (use oper2)
alu_out.flag(O) <= ( oper1(DW-1) and not oper2(DW-1) and not result_reg(DW-1)) or
(not oper1(DW-1) and oper2(DW-1) and result_reg(DW-1));
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
676cbcc6b8f57d1aca16c8aec292cb00
| 0.47461 | 3.744012 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/aes3rx.vhd
| 1 | 4,427 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 02/26/2015
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This AES3/EBU and SPDIF receiver is compliant with
-- IEC61937, IEC60958-3 and IEC60958-4
-- The input is sampled in by either
-- 49.152 MHz for 48kHz, 96kHz and 192kHz samplerates
-- 45.1584 MHz for 44.1kHz, 88.2kHz or 176.4 kHz
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Changed indentation
-- - rewrite of the state machine
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spdif_pkg.all;
entity aes3rx is
port (
-- Synchronous reset
reset : in std_ulogic;
-- Master clock
clk : in std_ulogic;
aes_in : in t_aes_in;
aes_out : out t_aes_out
);
end aes3rx;
architecture rtl of aes3rx is
type t_reg_type is record
slv_aes3 : std_logic_vector(3 downto 0);
sl_aes3_clk : std_logic;
sl_change : std_logic; -- detects
slv_sync_count : std_logic_vector(5 downto 0);
slv_clk_counter : std_logic_vector(7 downto 0);
slv_decoder_shift : std_logic_vector(7 downto 0);
sl_x_detected : std_logic; -- Asserted when x preamble has been detected
sl_y_detected : std_logic; -- Asserted when y preamble has been detected
sl_z_detected : std_logic; -- Asserted when z preamble has been detected
sl_preamble_detected : std_logic; -- Asserted when all preambles
sl_lock : std_logic;
state : t_aes3_state;
end record;
signal r, r_next : t_reg_type;
begin
-- _ _ _ _ _ _ _
-- / \_/ \_/ \_/ \_/ \_/ \_/ \_/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
-- __
-- __/
input_shift_proc: process(aes_in, reset, r)
variable v : t_reg_type;
begin
v := r;
-- getting asynchronous input
v.slv_aes3 := aes_in.data & r.slv_aes3(3 downto 1);
-- detecting signal change
v.sl_change := r.slv_aes3(2) xor r.slv_aes3(1);
-- counts number of aes_clk pulses since last detected preamble
if r.sl_preamble_detected = '1' then
v.slv_sync_count := (others => '0');
else
v.slv_sync_count := std_logic_vector(unsigned(r.slv_sync_count) + 1);
end if;
-- counting
if r.slv_clk_counter = b"0000_0000" then
if r.sl_change = '1' then
v.slv_clk_counter := (others => '1');
else
v.slv_clk_counter := std_logic_vector(unsigned(r.slv_clk_counter) - 1);
end if;
end if;
-- decoder shift register
v.slv_decoder_shift := r.slv_aes3(0) & r.slv_decoder_shift(7 downto 1);
-- Generates a clock pulse when clk_counter counts to zero
if r.slv_clk_counter = x"00" then
v.sl_aes3_clk := '1';
else
v.sl_aes3_clk := '0';
end if;
-- preamble detection
v.sl_x_detected := preamble_detection(r.slv_decoder_shift, X_PREAMBLE);
v.sl_y_detected := preamble_detection(r.slv_decoder_shift, Y_PREAMBLE);
v.sl_z_detected := preamble_detection(r.slv_decoder_shift, Z_PREAMBLE);
v.sl_preamble_detected := v.sl_x_detected or v.sl_y_detected or v.sl_z_detected;
-- preamble detection
if r.sl_preamble_detected = '1' then
end if;
-- Locking state machine for AES3/EBU data stream.
-- The locking for 192kHz, 96kHz and 48kHz will be done in parallel.
-- The clock will be set to 122 MHz
case r.state is
when UNLOCKED =>
if r.sl_preamble_detected = '1' then
v.state := CONFIRMING;
v.sl_lock := '0';
end if;
when CONFIRMING =>
if r.sl_preamble_detected = '1' then
v.state := LOCKED;
end if;
when LOCKED =>
if r.sl_preamble_detected = '0' then
v.state := UNLOCKED;
v.sl_lock := '1';
end if;
end case;
if (reset = '0') then
v.state := UNLOCKED;
end if;
r_next <= v;
aes_out.lock <= r.sl_lock;
end process input_shift_proc;
proc : process (clk)
begin
if rising_edge(clk) then
r <= r_next;
end if;
end process proc;
end rtl;
|
gpl-3.0
|
2f1c866b3b1de2ba65fed8acd18a3f7c
| 0.558843 | 3.376812 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/RF.vhd
| 1 | 1,029 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
DWR : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
Crs1 : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0');
Crs2 : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0'));
end RF;
architecture Behavioral of RF is
type ram_type is array (63 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type:=(others => "00000000000000000000000000000000");
--registro g0 siempre es cero
begin
process (rs1,rs2,rd,DWR,rst,RAM)
begin
if rst='0' then
if rd >"00000" then
RAM(conv_integer(rd)) <= DWR;
end if;
Crs1<=RAM(conv_integer(rs1));
Crs2<=RAM(conv_integer(rs2));
else
RAM<=(others=>"00000000000000000000000000000000");
Crs1<=(others=>'0');
Crs2<=(others=>'0');
end if;
end process;
end Behavioral;
|
mit
|
40da7a0c4a395c94855e765110785a68
| 0.629738 | 3.099398 | false | false | false | false |
daniw/add
|
rot_enc/ram.vhd
| 3 | 1,847 |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 11-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data memory for simple von-Neumann MCU with registered read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: (2**AW)*DW + DW (or equivalent BRAM/distr. memory)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity ram is
port(clk : in std_logic;
-- RAM bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus
);
end ram;
architecture rtl of ram is
type t_ram is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
signal ram_array : t_ram := (
-- prelimenary RAM initialization
0 => std_logic_vector(to_unsigned(16#00_FF#, DW)),
1 => std_logic_vector(to_unsigned(16#FF_01#, DW)),
2 => std_logic_vector(to_unsigned(16#7F_FF#, DW)),
3 => std_logic_vector(to_unsigned(16#7F_FE#, DW)),
others => (others => '0'));
begin
-----------------------------------------------------------------------------
-- sequential process: RAM (read before write)
-----------------------------------------------------------------------------
P_ram: process(clk)
begin
if rising_edge(clk) then
if bus_in.wr_enb = '1' then
ram_array(to_integer(unsigned(bus_in.addr))) <= bus_in.data;
end if;
bus_out.data <= ram_array(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
gpl-2.0
|
21e91f146fe2926d2cde06c2b6a8f8dd
| 0.417975 | 4.236239 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_uartlite_0_0/synth/system_axi_uartlite_0_0.vhd
| 1 | 8,958 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0_15;
USE axi_uartlite_v2_0_15.axi_uartlite;
ENTITY system_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END system_axi_uartlite_0_0;
ARCHITECTURE system_axi_uartlite_0_0_arch OF system_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_uartlite_0_0_arch: ARCHITECTURE IS "axi_uartlite,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_uartlite_0_0_arch : ARCHITECTURE IS "system_axi_uartlite_0_0,axi_uartlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_uartlite_0_0_arch: ARCHITECTURE IS "system_axi_uartlite_0_0,axi_uartlite,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ACLK_FREQ_HZ=100000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=9600,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END system_axi_uartlite_0_0_arch;
|
apache-2.0
|
3e59f7b207d732b27db45ee5d726738b
| 0.6977 | 3.307976 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_dlmb_bram_if_cntlr_0/sim/system_dlmb_bram_if_cntlr_0.vhd
| 1 | 12,257 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0_10;
USE lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_cntlr;
ENTITY system_dlmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END system_dlmb_bram_if_cntlr_0;
ARCHITECTURE system_dlmb_bram_if_cntlr_0_arch OF system_dlmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_BASEADDR : STD_LOGIC_VECTOR;
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR;
C_MASK1 : STD_LOGIC_VECTOR;
C_MASK2 : STD_LOGIC_VECTOR;
C_MASK3 : STD_LOGIC_VECTOR;
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_BRAM_AWIDTH : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"0000000000007FFF",
C_BASEADDR => X"0000000000000000",
C_NUM_LMB => 1,
C_MASK => X"00000000c0000000",
C_MASK1 => X"0000000000800000",
C_MASK2 => X"0000000000800000",
C_MASK3 => X"0000000000800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_BRAM_AWIDTH => 32,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END system_dlmb_bram_if_cntlr_0_arch;
|
apache-2.0
|
406383cc30ff1aa140fb1e43dd92c73d
| 0.652607 | 3.233184 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_pullup_0/system_axi_gpio_pullup_0_sim_netlist.vhdl
| 1 | 55,222 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:11 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_pullup_0/system_axi_gpio_pullup_0_sim_netlist.vhdl
-- Design : system_axi_gpio_pullup_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_pullup_0_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rst_reg : in STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 1 downto 0 );
start2_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_pullup_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_pullup_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_pullup_0_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[31]_i_2_n_0\ : STD_LOGIC;
signal \gpio_core_1/GPIO_DBus_i\ : STD_LOGIC_VECTOR ( 30 to 30 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2_reg,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => \gpio_core_1/GPIO_DBus_i\(30),
I1 => GPIO_xferAck_i,
I2 => gpio_xferAck_Reg,
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
O => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E000000020"
)
port map (
I0 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I1 => Q(0),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(1),
I5 => gpio_io_t(1),
O => \gpio_core_1/GPIO_DBus_i\(30)
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[31]_i_2_n_0\,
I1 => GPIO_xferAck_i,
I2 => gpio_xferAck_Reg,
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
O => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E000000020"
)
port map (
I0 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I1 => Q(0),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(1),
I5 => gpio_io_t(0),
O => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[31]_i_2_n_0\
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAABAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => Q(0),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => Q(2),
I5 => Q(1),
O => \Not_Dual.gpio_Data_Out_reg[0]\
);
\Not_Dual.gpio_OE[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAABAAAAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(0),
I5 => Q(1),
O => \Not_Dual.gpio_OE_reg[0]\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_pullup_0_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_pullup_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_pullup_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_pullup_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_pullup_0_GPIO_Core is
port (
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
iGPIO_xferAck_reg_0 : in STD_LOGIC;
iGPIO_xferAck_reg_1 : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_reg : in STD_LOGIC;
rst_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_pullup_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_pullup_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_pullup_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.gpio_Data_Out[0]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_Data_Out[1]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_OE[0]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_OE[1]_i_1_n_0\ : STD_LOGIC;
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(1 downto 0) <= \^gpio_io_o\(1 downto 0);
gpio_io_t(1 downto 0) <= \^gpio_io_t\(1 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.system_axi_gpio_pullup_0_cdc_sync
port map (
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(1) => gpio_io_i_d2(0),
scndry_vect_out(0) => gpio_io_i_d2(1)
);
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck_reg_1,
Q => D(1),
R => '0'
);
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck_reg_0,
Q => D(0),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]_0\(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]_0\(0),
R => '0'
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCACFFFFCCAC0000"
)
port map (
I0 => s_axi_wdata(1),
I1 => s_axi_wdata(3),
I2 => bus2ip_cs,
I3 => Q(0),
I4 => rst_reg,
I5 => \^gpio_io_o\(1),
O => \Not_Dual.gpio_Data_Out[0]_i_1_n_0\
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCACFFFFCCAC0000"
)
port map (
I0 => s_axi_wdata(0),
I1 => s_axi_wdata(2),
I2 => bus2ip_cs,
I3 => Q(0),
I4 => rst_reg,
I5 => \^gpio_io_o\(0),
O => \Not_Dual.gpio_Data_Out[1]_i_1_n_0\
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_Out[0]_i_1_n_0\,
Q => \^gpio_io_o\(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_Out[1]_i_1_n_0\,
Q => \^gpio_io_o\(0),
R => bus2ip_reset
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCACFFFFCCAC0000"
)
port map (
I0 => s_axi_wdata(1),
I1 => s_axi_wdata(3),
I2 => bus2ip_cs,
I3 => Q(0),
I4 => rst_reg_0,
I5 => \^gpio_io_t\(1),
O => \Not_Dual.gpio_OE[0]_i_1_n_0\
);
\Not_Dual.gpio_OE[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCACFFFFCCAC0000"
)
port map (
I0 => s_axi_wdata(0),
I1 => s_axi_wdata(2),
I2 => bus2ip_cs,
I3 => Q(0),
I4 => rst_reg_0,
I5 => \^gpio_io_t\(0),
O => \Not_Dual.gpio_OE[1]_i_1_n_0\
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE[0]_i_1_n_0\,
Q => \^gpio_io_t\(1),
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE[1]_i_1_n_0\,
Q => \^gpio_io_t\(0),
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_pullup_0_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]_0\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
\ip2bus_data_i_D1_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_pullup_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_pullup_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_pullup_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.read_reg_gen[0].gpio_dbus_i_reg[30]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \s_axi_rdata_i[0]_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1";
begin
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\ <= \^not_dual.read_reg_gen[0].gpio_dbus_i_reg[30]\;
Q(0) <= \^q\(0);
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rdata(1 downto 0) <= \^s_axi_rdata\(1 downto 0);
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_pullup_0_address_decoder
port map (
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\ => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]_0\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_In_reg[0]\(1 downto 0) => \Not_Dual.gpio_Data_In_reg[0]\(1 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\ => \Not_Dual.gpio_Data_Out_reg[0]\,
\Not_Dual.gpio_OE_reg[0]\ => \Not_Dual.gpio_OE_reg[0]\,
Q(2) => bus2ip_addr(0),
Q(1) => \^q\(0),
Q(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^not_dual.read_reg_gen[0].gpio_dbus_i_reg[30]\,
gpio_io_t(1 downto 0) => gpio_io_t(1 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wready => \^s_axi_wready\,
start2_reg => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.read_reg_gen[0].gpio_dbus_i_reg[30]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[30]\(0),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(0),
O => \s_axi_rdata_i[0]_i_1_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[30]\(1),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(1),
O => \s_axi_rdata_i[1]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[0]_i_1_n_0\,
Q => \^s_axi_rdata\(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[1]_i_1_n_0\,
Q => \^s_axi_rdata\(1),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_pullup_0_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_xferAck_i : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
\ip2bus_data_i_D1_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_pullup_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_pullup_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_pullup_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_pullup_0_slave_attachment
port map (
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\ => bus2ip_rnw,
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]_0\ => \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\ => \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_In_reg[0]\(1 downto 0) => \Not_Dual.gpio_Data_In_reg[0]\(1 downto 0),
\Not_Dual.gpio_Data_Out_reg[0]\ => \Not_Dual.gpio_Data_Out_reg[0]\,
\Not_Dual.gpio_OE_reg[0]\ => \Not_Dual.gpio_OE_reg[0]\,
Q(0) => Q(0),
SR => bus2ip_reset,
gpio_io_t(1 downto 0) => gpio_io_t(1 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[30]\(1 downto 0) => \ip2bus_data_i_D1_reg[30]\(1 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(1 downto 0) => s_axi_rdata(1 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_pullup_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_pullup_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_pullup_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_pullup_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_pullup_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_pullup_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_pullup_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_pullup_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_pullup_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_pullup_0_axi_gpio : entity is 2;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_pullup_0_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_pullup_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_pullup_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_pullup_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_pullup_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_pullup_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_pullup_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_pullup_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_pullup_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_pullup_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_pullup_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 5 to 5 );
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 1 );
signal gpio_core_1_n_5 : STD_LOGIC;
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 30 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 30 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(1 downto 0) <= \^gpio_io_t\(1 downto 0);
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1 downto 0) <= \^s_axi_rdata\(1 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_pullup_0_axi_lite_ipif
port map (
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_10,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_11,
\Not_Dual.gpio_Data_In_reg[0]\(1) => gpio_Data_In(0),
\Not_Dual.gpio_Data_In_reg[0]\(0) => gpio_Data_In(1),
\Not_Dual.gpio_Data_Out_reg[0]\ => AXI_LITE_IPIF_I_n_6,
\Not_Dual.gpio_OE_reg[0]\ => AXI_LITE_IPIF_I_n_8,
Q(0) => bus2ip_addr(5),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(1 downto 0) => \^gpio_io_t\(1 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[30]\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[30]\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(1 downto 0) => \^s_axi_rdata\(1 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.system_axi_gpio_pullup_0_GPIO_Core
port map (
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]_0\(1) => gpio_Data_In(0),
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[30]_0\(0) => gpio_Data_In(1),
Q(0) => bus2ip_addr(5),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
gpio_io_o(1 downto 0) => gpio_io_o(1 downto 0),
gpio_io_t(1 downto 0) => \^gpio_io_t\(1 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
iGPIO_xferAck_reg_0 => AXI_LITE_IPIF_I_n_11,
iGPIO_xferAck_reg_1 => AXI_LITE_IPIF_I_n_10,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_5,
rst_reg => AXI_LITE_IPIF_I_n_6,
rst_reg_0 => AXI_LITE_IPIF_I_n_8,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(3 downto 2) => s_axi_wdata(31 downto 30),
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0)
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_5,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_pullup_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_pullup_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_pullup_0 : entity is "system_axi_gpio_pullup_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_pullup_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_pullup_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_pullup_0;
architecture STRUCTURE of system_axi_gpio_pullup_0 is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 2;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_pullup_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
gpio_io_o(1 downto 0) => gpio_io_o(1 downto 0),
gpio_io_t(1 downto 0) => gpio_io_t(1 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
fd63883037a128e0450b0bc38b140fbd
| 0.584658 | 2.651462 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_drp_arbiter.vhd
| 1 | 17,519 |
-------------------------------------------------------------------------------
-- drp_arbiter.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010, 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity drp_arbiter is
port (
reset : in std_logic; -- input clock
clk : in std_logic; -- input clock
jtaglocked : in std_logic; -- input clock
bgrant_A : out std_logic; -- bus grant
bgrant_B : out std_logic; -- bus grant
bbusy_A : in std_logic; -- bus busy
bbusy_B : in std_logic; -- bus busy
daddr_A : in std_logic_vector(7 downto 0);
den_A : in std_logic;
di_A : in std_logic_vector(15 downto 0);
dwe_A : in std_logic;
do_A : out std_logic_vector(15 downto 0);
drdy_A : out std_logic;
daddr_B : in std_logic_vector(7 downto 0);
den_B : in std_logic;
di_B : in std_logic_vector(15 downto 0);
dwe_B : in std_logic;
do_B : out std_logic_vector(15 downto 0);
drdy_B : out std_logic;
daddr_C : out std_logic_vector(7 downto 0);
den_C : out std_logic;
di_C : out std_logic_vector(15 downto 0);
dwe_C : out std_logic;
do_C : in std_logic_vector(15 downto 0);
drdy_C : in std_logic
);
end drp_arbiter;
architecture behv of drp_arbiter is
type fsmstate is (NOGRANT,GRANT_A,GRANT_A_WAIT, GRANT_B,GRANT_B_WAIT);
signal state : fsmstate;
signal daddr_C_reg : std_logic_vector(7 downto 0);
signal di_C_reg : std_logic_vector(15 downto 0);
signal den_C_reg : std_logic;
signal dwe_C_reg : std_logic;
signal daddr_reg : std_logic_vector(7 downto 0);
signal di_reg : std_logic_vector(15 downto 0);
signal den_reg : std_logic;
signal dwe_reg : std_logic;
signal do_A_reg : std_logic_vector(15 downto 0);
signal drdy_A_reg : std_logic;
signal do_B_reg : std_logic_vector(15 downto 0);
signal drdy_B_reg : std_logic;
signal overlap_A : std_logic;
signal overlap_B : std_logic;
begin
daddr_C <= daddr_C_reg;
di_C <= di_C_reg;
den_C <= den_C_reg;
dwe_C <= dwe_C_reg;
do_B <= do_B_reg;
drdy_B <= drdy_B_reg;
drdy_A <= drdy_A_reg;
do_A <= do_A_reg;
arbiter_fsm: process (clk, reset)
begin
if (reset = '1') then
state <= NOGRANT;
daddr_C_reg <= X"00";
di_C_reg <= X"0000";
dwe_C_reg <= '0';
den_C_reg <= '0';
daddr_reg <= X"00";
di_reg <= X"0000";
dwe_reg <= '0';
den_reg <= '0';
drdy_A_reg <= '0';
do_A_reg <= X"0000";
drdy_B_reg <= '0';
do_B_reg <= X"0000";
overlap_A <= '0';
overlap_B <= '0';
bgrant_A <= '0';
bgrant_B <= '0';
elsif clk'event and clk = '1' then
case state is
when NOGRANT =>
if jtaglocked= '0' then
if bbusy_A = '0' and bbusy_B = '0' then
if overlap_B = '1' then
daddr_C_reg <= daddr_reg;
di_C_reg <= di_reg;
dwe_C_reg <= dwe_reg;
den_C_reg <= den_reg;
overlap_B <= '0';
bgrant_A <= '0';
bgrant_B <= '1';
state <= GRANT_B;
elsif overlap_A = '1' then
daddr_C_reg <= daddr_reg;
di_C_reg <= di_reg;
dwe_C_reg <= dwe_reg;
den_C_reg <= den_reg;
overlap_A <= '0';
bgrant_A <= '1';
bgrant_B <= '0';
state <= GRANT_A;
else
if den_A = '1' and den_B = '0' then
daddr_C_reg <= daddr_A;
di_C_reg <= di_A;
dwe_C_reg <= dwe_A;
den_C_reg <= den_A;
overlap_A <= '0';
overlap_B <= '0';
bgrant_A <= '1';
bgrant_B <= '0';
state <= GRANT_A;
end if;
if den_A = '0' and den_B = '1' then
daddr_C_reg <= daddr_B;
di_C_reg <= di_B;
dwe_C_reg <= dwe_B;
den_C_reg <= den_B;
overlap_A <= '0';
overlap_B <= '0';
bgrant_A <= '0';
bgrant_B <= '1';
state <= GRANT_B;
end if;
if den_A = '1' and den_B = '1' then
daddr_C_reg <= daddr_A;
di_C_reg <= di_A;
dwe_C_reg <= dwe_A;
den_C_reg <= den_A;
daddr_reg <= daddr_B;
di_reg <= di_B;
dwe_reg <= dwe_B;
den_reg <= den_B;
overlap_A <= '0';
overlap_B <= '1';
bgrant_A <= '1';
bgrant_B <= '0';
state <= GRANT_A;
end if;
if den_A = '0' and den_B = '0' then
daddr_C_reg <= X"00";
di_C_reg <= X"0000";
dwe_C_reg <= '0';
den_C_reg <= '0';
bgrant_A <= '0';
bgrant_B <= '0';
end if;
end if;
elsif bbusy_A = '1' and bbusy_B = '0' then
if den_A = '1' then
daddr_C_reg <= daddr_A;
di_C_reg <= di_A;
dwe_C_reg <= dwe_A;
den_C_reg <= den_A;
state <= GRANT_A;
bgrant_A <= '1';
end if;
if den_B = '1' then
daddr_reg <= daddr_B;
di_reg <= di_B;
dwe_reg <= dwe_B;
den_reg <= den_B;
overlap_B <= '1';
end if;
elsif bbusy_A = '0' and bbusy_B = '1' then
if den_B = '1' then
daddr_C_reg <= daddr_B;
di_C_reg <= di_B;
dwe_C_reg <= dwe_B;
den_C_reg <= den_B;
state <= GRANT_B;
bgrant_B <= '1';
end if;
if den_A = '1' then
daddr_reg <= daddr_A;
di_reg <= di_A;
dwe_reg <= dwe_A;
den_reg <= den_A;
overlap_A <= '1';
end if;
end if;
end if;
drdy_A_reg <= '0';
do_A_reg <= X"0000";
drdy_B_reg <= '0';
do_B_reg <= X"0000";
when GRANT_A =>
if drdy_C = '1' then
--if (den_B = '1' or req_A_B = '1' or overlap_B = '1') and busy_in /= '1' then
-- if bbusy_A /= '1' and (den_B = '1' or overlap_B = '1') then
if bbusy_A /= '1' and overlap_B = '1' then
daddr_C_reg <= daddr_reg;
di_C_reg <= di_reg;
dwe_C_reg <= dwe_reg;
den_C_reg <= den_reg;
overlap_B <= '0';
bgrant_A <= '0';
bgrant_B <= '1';
state <= GRANT_B;
elsif bbusy_A /= '1' and den_B = '1' then
daddr_C_reg <= daddr_B;
di_C_reg <= di_B;
dwe_C_reg <= dwe_B;
den_C_reg <= den_B;
overlap_B <= '0';
bgrant_A <= '0';
bgrant_B <= '1';
state <= GRANT_B;
else
state <= NOGRANT;
end if;
do_A_reg <= do_C;
else
daddr_C_reg <= daddr_A;
di_C_reg <= di_A;
dwe_C_reg <= dwe_A;
den_C_reg <= den_A;
end if;
if den_B = '1' then
daddr_reg <= daddr_B;
di_reg <= di_B;
dwe_reg <= dwe_B;
den_reg <= den_B;
overlap_B <= '1';
end if;
drdy_A_reg <= drdy_C;
drdy_B_reg <= '0';
when GRANT_B =>
if drdy_C = '1' then
--if (den_A = '1' or overlap_A = '1') and busy_in /= '1' then
if bbusy_B /= '1' and overlap_A = '1' then
daddr_C_reg <= daddr_reg;
di_C_reg <= di_reg;
dwe_C_reg <= dwe_reg;
den_C_reg <= den_reg;
overlap_A <= '0';
bgrant_A <= '1';
bgrant_B <= '0';
state <= GRANT_A;
elsif bbusy_B /= '1' and den_A = '1' then
daddr_C_reg <= daddr_A;
di_C_reg <= di_A;
dwe_C_reg <= dwe_A;
den_C_reg <= den_A;
overlap_A <= '0';
bgrant_A <= '1';
bgrant_B <= '0';
state <= GRANT_A;
else
state <= NOGRANT;
end if;
do_B_reg <= do_C;
else
daddr_C_reg <= daddr_B;
di_C_reg <= di_B;
dwe_C_reg <= dwe_B;
den_C_reg <= den_B;
end if;
if den_A = '1' then
daddr_reg <= daddr_A;
di_reg <= di_A;
dwe_reg <= dwe_A;
den_reg <= den_A;
overlap_A <= '1';
end if;
drdy_B_reg <= drdy_C;
drdy_A_reg <= '0';
when others => Null;
end case;
end if;
end process;
end behv;
|
apache-2.0
|
c6bcfb39bab4e3807af376dc560a4d2e
| 0.287631 | 5.328163 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/And8Bit.vhd
| 1 | 1,459 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 05:14:55 PM
-- Design Name:
-- Module Name: And8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity And8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end And8Bit;
architecture Behavioral of And8Bit is
begin
Output(0) <= InputA(0) and InputB(0);
Output(1) <= InputA(1) and InputB(1);
Output(2) <= InputA(2) and InputB(2);
Output(3) <= InputA(3) and InputB(3);
Output(4) <= InputA(4) and InputB(4);
Output(5) <= InputA(5) and InputB(5);
Output(6) <= InputA(6) and InputB(6);
Output(7) <= InputA(7) and InputB(7);
end Behavioral;
|
mit
|
614d15de347fc84c3d7252a480185405
| 0.578478 | 3.638404 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/f4d9/hdl/lmb_bram_if_cntlr_v4_0_vh_rfs.vhd
| 1 | 157,442 |
-------------------------------------------------------------------------------
-- lmb_bram_if_funcs.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: lmb_bram_if_funcs.vhd
--
-- Description: Support functions for lmb_bram_if_cntlr
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_funcs.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package lmb_bram_if_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
VIRTEX7,
KINTEX7,
ARTIX7,
ZYNQ,
VIRTEXU,
KINTEXU,
ZYNQUPLUS,
VIRTEXUPLUS,
KINTEXUPLUS,
SPARTAN7,
-- pragma xilinx_rtl_on
RTL
);
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
-- Get the maximum number of inputs to a LUT.
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer;
end package lmb_bram_if_funcs;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body lmb_bram_if_funcs is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END Equal_String;
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
begin -- function String_To_Family
if ((Select_RTL) or Equal_String(S, "rtl")) then
return RTL;
elsif Equal_String(S, "virtex7") or Equal_String(S, "qvirtex7") then
return VIRTEX7;
elsif Equal_String(S, "kintex7") or Equal_String(S, "kintex7l") or
Equal_String(S, "qkintex7") or Equal_String(S, "qkintex7l") then
return KINTEX7;
elsif Equal_String(S, "artix7") or Equal_String(S, "artix7l") or Equal_String(S, "aartix7") or
Equal_String(S, "qartix7") or Equal_String(S, "qartix7l") then
return ARTIX7;
elsif Equal_String(S, "zynq") or Equal_String(S, "azynq") or Equal_String(S, "qzynq") then
return ZYNQ;
elsif Equal_String(S, "virtexu") or Equal_String(S, "qvirtexu") then
return VIRTEXU;
elsif Equal_String(S, "kintexu") or Equal_String(S, "kintexul") or
Equal_String(S, "qkintexu") or Equal_String(S, "qkintexul") then
return KINTEXU;
elsif Equal_String(S, "zynquplus") then
return ZYNQUPLUS;
elsif Equal_String(S, "virtexuplus") then
return VIRTEXUPLUS;
elsif Equal_String(S, "kintexuplus") then
return KINTEXUPLUS;
elsif Equal_String(S, "spartan7") then
return SPARTAN7;
else
-- assert (false) report "No known target family" severity failure;
return RTL;
end if;
end function String_To_Family;
function Family_To_LUT_Size(Family : TARGET_FAMILY_TYPE) return integer is
begin
return 6;
end function Family_To_LUT_Size;
end package body lmb_bram_if_funcs;
-------------------------------------------------------------------------------
-- primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: primitives.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- rolandp 2015-01-22 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
----- entity LUT6 -----
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end entity MB_LUT6;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_LUT6 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
constant INIT_reg : std_logic_vector(63 downto 0) := To_StdLogicVector(INIT);
begin
process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
variable I0_v, I1_v, I2_v, I3_v, I4_v, I5_v : std_logic;
begin
-- Filter unknowns
if I0 = '0' then I0_v := '0'; else I0_v := '1'; end if;
if I1 = '0' then I1_v := '0'; else I1_v := '1'; end if;
if I2 = '0' then I2_v := '0'; else I2_v := '1'; end if;
if I3 = '0' then I3_v := '0'; else I3_v := '1'; end if;
if I4 = '0' then I4_v := '0'; else I4_v := '1'; end if;
if I5 = '0' then I5_v := '0'; else I5_v := '1'; end if;
I_reg := TO_STDLOGICVECTOR(I5_v & I4_v & I3_v & I2_v & I1_v & I0_v);
O <= INIT_reg(TO_INTEGER(unsigned(I_reg)));
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: LUT6
generic map(
INIT => INIT
)
port map(
O => O,
I0 => I0,
I1 => I1,
I2 => I2,
I3 => I3,
I4 => I4,
I5 => I5
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end entity MB_MUXCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
LO <= DI when S = '0' else CI;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXCY_L
port map(
LO => LO,
CI => CI,
DI => DI,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity XORCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end entity MB_XORCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_XORCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= (CI xor LI);
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: XORCY
port map(
O => O,
CI => CI,
LI => LI
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXF7 -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end entity MB_MUXF7;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXF7 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= I0 when S = '0' else I1;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXF7
port map(
O => O,
I0 => I0,
I1 => I1,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXF8 -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end entity MB_MUXF8;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXF8 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= I0 when S = '0' else I1;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXF8
port map(
O => O,
I0 => I0,
I1 => I1,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity FDRE -----
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity MB_FDRE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end entity MB_FDRE;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_FDRE is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
function To_StdLogic(A : in bit ) return std_logic is
begin
if( A = '1' ) then
return '1';
end if;
return '0';
end;
signal q_o : std_logic := To_StdLogic(INIT);
begin
Q <= q_o;
process(C)
begin
if (rising_edge(C)) then
if (R = '1') then
q_o <= '0';
elsif (CE = '1') then
q_o <= D;
end if;
end if;
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: FDRE
generic map(
INIT => INIT
)
port map(
Q => Q,
C => C,
CE => CE,
D => D,
R => R
);
end generate Using_FPGA;
end architecture IMP;
-------------------------------------------------------------------------------
-- xor18.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: xor18.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- xor18.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity XOR18 is
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end entity XOR18;
architecture IMP of XOR18 is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
component MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component MB_XORCY;
begin -- architecture IMP
Using_FPGA: if ( C_TARGET /= RTL ) generate
signal xor6_1 : std_logic;
signal xor6_2 : std_logic;
signal xor6_3 : std_logic;
signal xor18_c1 : std_logic;
signal xor18_c2 : std_logic;
begin -- generate Using_LUT6
XOR6_1_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_1,
I0 => InA(17),
I1 => InA(16),
I2 => InA(15),
I3 => InA(14),
I4 => InA(13),
I5 => InA(12));
XOR_1st_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => '1',
CI => '0',
S => xor6_1,
LO => xor18_c1);
XOR6_2_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_2,
I0 => InA(11),
I1 => InA(10),
I2 => InA(9),
I3 => InA(8),
I4 => InA(7),
I5 => InA(6));
XOR_2nd_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => xor6_1,
CI => xor18_c1,
S => xor6_2,
LO => xor18_c2);
XOR6_3_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => xor6_3,
I0 => InA(5),
I1 => InA(4),
I2 => InA(3),
I3 => InA(2),
I4 => InA(1),
I5 => InA(0));
XOR18_XORCY : MB_XORCY
generic map(
C_TARGET => C_TARGET)
port map (
LI => xor6_3,
CI => xor18_c2,
O => res);
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
res <= InA(17) xor InA(16) xor InA(15) xor InA(14) xor InA(13) xor InA(12) xor
InA(11) xor InA(10) xor InA(9) xor InA(8) xor InA(7) xor InA(6) xor
InA(5) xor InA(4) xor InA(3) xor InA(2) xor InA(1) xor InA(0);
end generate Using_RTL;
end architecture IMP;
-------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
-------------------------------------------------------------------------------
-- parityenable.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity ParityEnable is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 4
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic
);
end entity ParityEnable;
architecture IMP of ParityEnable is
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
begin -- architecture IMP
Using_FPGA: if ( C_TARGET /= RTL ) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 5 generate
signal inA5 : std_logic_vector(0 to 4);
begin
Assign_InA : process (InA) is
begin
inA5 <= (others => '0');
inA5(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699600000000")
port map(
O => Res,
I0 => InA5(4),
I1 => inA5(3),
I2 => inA5(2),
I3 => inA5(1),
I4 => inA5(0),
I5 => Enable);
end generate Single_LUT6;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= Enable and ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
-------------------------------------------------------------------------------
-- checkbit_handler.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: gen_checkbits.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- gen_checkbits.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean := true);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
architecture IMP of checkbit_handler is
component XOR18 is
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
component ParityEnable
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic);
end component ParityEnable;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (
C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_TARGET => C_TARGET) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
-- Unused
Syndrome <= (others => '0');
UE <= '0';
CE <= '0';
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6);
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_3_to_5 : std_logic_vector(3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
Parity_chk3_3 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 2)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
Parity_chk6_7 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
Syndrome <= syndrome_i;
syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101") else
'0';
CE <= '0' when (Enable_ECC = '0') else
(syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else
CE_Q;
ue_i_0 <= '0' when (Enable_ECC = '0') else
'1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else
UE_Q;
ue_i_1 <= '0' when (Enable_ECC = '0') else
(syndrome_3_to_5_multi or UE_Q);
Use_FPGA: if (C_TARGET /= RTL) generate
UE_MUXF7 : MB_MUXF7
generic map (
C_TARGET => C_TARGET)
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => syndrome_i(6),
O => UE);
end generate Use_FPGA;
Use_RTL: if (C_TARGET = RTL) generate
UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0;
end generate Use_RTL;
-- Unused
CheckOut <= (others => '0');
end generate Decode_Bits;
end architecture IMP;
-------------------------------------------------------------------------------
-- correct_one_bit.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- correct_one_bit
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity Correct_One_Bit is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
component MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component MB_XORCY;
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MB_MUXCY
generic map(
C_TARGET => C_TARGET)
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : MB_XORCY
generic map(
C_TARGET => C_TARGET)
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
-------------------------------------------------------------------------------
-- pselect_mask.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 63) := X"0000000000020000";
C_MASK : std_logic_vector(0 to 63) := X"000000000007C000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
architecture imp of pselect_mask is
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK(64 - C_AW to 63));
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in 0 to C_AW - 1 loop
if (C_MASK(64 - C_AW + I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(64 - C_AW + I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
CS <= Valid when A_Bus=BAR else '0';
end imp;
-------------------------------------------------------------------------------
-- axi_interface.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: axi_interface.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_interface.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
entity axi_interface is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- lmb_bram_if_cntlr signals
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_interface;
architecture IMP of axi_interface is
component MB_FDRE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component MB_FDRE;
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal ongoing_write : std_logic;
signal ongoing_read : std_logic;
signal S_AXI_RVALID_i : std_logic;
signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Only allow one access at a time
new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Store register address and write data
Reg: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
RegAddr <= (others => '0');
RegWrData <= (others => '0');
elsif new_write_access = '1' then
RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
elsif new_read_access = '1' then
RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
end if;
end if;
end process Reg;
-- Handle write access.
WriteAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_write <= '0';
elsif new_write_access = '1' then
ongoing_write <= '1';
elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
ongoing_write <= '0';
end if;
RegWr <= new_write_access;
end if;
end process WriteAccess;
S_AXI_BVALID <= ongoing_write;
S_AXI_BRESP <= (others => '0');
-- Handle read access
ReadAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
elsif new_read_access = '1' then
ongoing_read <= '1';
S_AXI_RVALID_i <= '0';
elsif ongoing_read = '1' then
if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
else
S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
end if;
end if;
end if;
end process ReadAccess;
S_AXI_RVALID <= S_AXI_RVALID_i;
S_AXI_RRESP <= (others => '0');
Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_Bits_Are_Used;
RegRdData_i <= RegRdData; -- Swap to - downto
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : MB_FDRE
generic map (
C_TARGET => C_TARGET)
port map (
Q => S_AXI_RDATA(I),
C => LMB_Clk,
CE => ongoing_read,
D => RegRdData_i(I),
R => LMB_Rst);
end generate S_AXI_RDATA_DFF;
end architecture IMP;
-------------------------------------------------------------------------------
-- lmb_mux.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_mux.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_mux.vhd
-- pselct_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
C_MASK : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end entity lmb_mux;
architecture imp of lmb_mux is
component pselect_mask
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 63) := X"0000000000000000";
C_MASK : std_logic_vector(0 to 63) := X"0000000000800000");
port (
A : in std_logic_vector(0 to C_AW - 1);
CS : out std_logic;
Valid : in std_logic);
end component;
signal one : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
LMB1_no: if (C_NUM_LMB < 2) generate
Sl1_DBus <= (others => '0');
Sl1_Ready <= '0';
Sl1_Wait <= '0';
Sl1_UE <= '0';
Sl1_CE <= '0';
end generate LMB1_no;
LMB2_no: if (C_NUM_LMB < 3) generate
Sl2_DBus <= (others => '0');
Sl2_Ready <= '0';
Sl2_Wait <= '0';
Sl2_UE <= '0';
Sl2_CE <= '0';
end generate LMB2_no;
LMB3_no: if (C_NUM_LMB < 4) generate
Sl3_DBus <= (others => '0');
Sl3_Ready <= '0';
Sl3_Wait <= '0';
Sl3_UE <= '0';
Sl3_CE <= '0';
end generate LMB3_no;
one <= '1';
one_lmb: if (C_NUM_LMB = 1) generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_MASK)
port map (
A => LMB0_ABus,
CS => lmb_select,
Valid => one);
LMB_ABus <= LMB0_ABus;
LMB_WriteDBus <= LMB0_WriteDBus;
LMB_AddrStrobe <= LMB0_AddrStrobe;
LMB_ReadStrobe <= LMB0_ReadStrobe;
LMB_WriteStrobe <= LMB0_WriteStrobe;
LMB_BE <= LMB0_BE;
Sl0_DBus <= Sl_DBus;
Sl0_Ready <= Sl_Ready;
Sl0_Wait <= Sl_Wait;
Sl0_UE <= Sl_UE;
Sl0_CE <= Sl_CE;
end generate one_lmb;
more_than_one_lmb: if (C_NUM_LMB > 1) generate
type C_Mask_Vec_T is array (0 to 3) of std_logic_vector(0 to 63);
constant C_Mask_Vec : C_MASK_Vec_T := (C_MASK, C_MASK1, C_MASK2, C_MASK3);
type ABus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_AWIDTH - 1);
type DBus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH - 1);
type BE_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH/8 - 1);
signal LMB_ABus_vec : ABus_vec_T;
signal LMB_ABus_vec_i : ABus_vec_T;
signal LMB_ABus_vec_Q : ABus_vec_T;
signal LMB_WriteDBus_vec : DBus_vec_T;
signal LMB_WriteDBus_vec_i : DBus_vec_T;
signal LMB_WriteDBus_vec_Q : DBus_vec_T;
signal LMB_AddrStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_BE_vec : BE_vec_T;
signal LMB_BE_vec_i : BE_vec_T;
signal LMB_BE_vec_Q : BE_vec_T;
signal Sl_DBus_vec : DBus_vec_T;
signal Sl_Ready_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_Wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_UE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_CE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal as_and_lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal ongoing : natural range 0 to C_NUM_LMB-1;
signal ongoing_new : natural range 0 to C_NUM_LMB-1;
signal ongoing_Q : natural range 0 to C_NUM_LMB-1;
begin
LMB_ABus_vec(0) <= LMB0_ABus;
LMB_WriteDBus_vec(0) <= LMB0_WriteDBus;
LMB_AddrStrobe_vec(0) <= LMB0_AddrStrobe;
LMB_ReadStrobe_vec(0) <= LMB0_ReadStrobe;
LMB_WriteStrobe_vec(0) <= LMB0_WriteStrobe;
LMB_BE_vec(0) <= LMB0_BE;
Sl0_DBus <= Sl_DBus_vec(0);
Sl0_Ready <= Sl_Ready_vec(0);
Sl0_Wait <= Sl_Wait_vec(0);
Sl0_UE <= Sl_UE_vec(0);
Sl0_CE <= Sl_CE_vec(0);
LMB_ABus_vec(1) <= LMB1_ABus;
LMB_WriteDBus_vec(1) <= LMB1_WriteDBus;
LMB_AddrStrobe_vec(1) <= LMB1_AddrStrobe;
LMB_ReadStrobe_vec(1) <= LMB1_ReadStrobe;
LMB_WriteStrobe_vec(1) <= LMB1_WriteStrobe;
LMB_BE_vec(1) <= LMB1_BE;
Sl1_DBus <= Sl_DBus_vec(1);
Sl1_Ready <= Sl_Ready_vec(1);
Sl1_Wait <= Sl_Wait_vec(1);
Sl1_UE <= Sl_UE_vec(1);
Sl1_CE <= Sl_CE_vec(1);
LMB2_yes: if (C_NUM_LMB > 2) generate
LMB_ABus_vec(2) <= LMB2_ABus;
LMB_WriteDBus_vec(2) <= LMB2_WriteDBus;
LMB_AddrStrobe_vec(2) <= LMB2_AddrStrobe;
LMB_ReadStrobe_vec(2) <= LMB2_ReadStrobe;
LMB_WriteStrobe_vec(2) <= LMB2_WriteStrobe;
LMB_BE_vec(2) <= LMB2_BE;
Sl2_DBus <= Sl_DBus_vec(2);
Sl2_Ready <= Sl_Ready_vec(2);
Sl2_Wait <= Sl_Wait_vec(2);
Sl2_UE <= Sl_UE_vec(2);
Sl2_CE <= Sl_CE_vec(2);
end generate LMB2_yes;
LMB3_yes: if (C_NUM_LMB > 3) generate
LMB_ABus_vec(3) <= LMB3_ABus;
LMB_WriteDBus_vec(3) <= LMB3_WriteDBus;
LMB_AddrStrobe_vec(3) <= LMB3_AddrStrobe;
LMB_ReadStrobe_vec(3) <= LMB3_ReadStrobe;
LMB_WriteStrobe_vec(3) <= LMB3_WriteStrobe;
LMB_BE_vec(3) <= LMB3_BE;
Sl3_DBus <= Sl_DBus_vec(3);
Sl3_Ready <= Sl_Ready_vec(3);
Sl3_Wait <= Sl_Wait_vec(3);
Sl3_UE <= Sl_UE_vec(3);
Sl3_CE <= Sl_CE_vec(3);
end generate LMB3_yes;
lmb_mux_generate: for I in 0 to C_NUM_LMB-1 generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_Mask_Vec(I))
port map (
A => LMB_ABus_vec(I),
CS => lmb_select_vec(I),
Valid => one);
as_and_lmb_select_vec(I) <= lmb_select_vec(I) and LMB_AddrStrobe_vec(I);
remember_access : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
LMB_ABus_vec_Q(I) <= (others => '0');
LMB_WriteDBus_vec_Q(I) <= (others => '0');
LMB_AddrStrobe_vec_Q(I) <= '0';
LMB_ReadStrobe_vec_Q(I) <= '0';
LMB_WriteStrobe_vec_Q(I) <= '0';
LMB_BE_vec_Q(I) <= (others => '0');
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
LMB_ABus_vec_Q(I) <= LMB_ABus_vec(I);
LMB_WriteDBus_vec_Q(I) <= LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_Q(I) <= LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_Q(I) <= LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_Q(I) <= LMB_WriteStrobe_vec(I);
LMB_BE_vec_Q(I) <= LMB_BE_vec(I);
end if;
end if;
end process remember_access;
wait_proc : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
wait_vec(I) <= '0';
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
wait_vec(I) <= '1';
elsif (wait_vec(I) = '1' and ongoing = I) then
wait_vec(I) <= '0';
end if;
end if;
end process wait_proc;
LMB_ABus_vec_i(I) <= LMB_ABus_vec_Q(I) when wait_vec(I) = '1' else
LMB_ABus_vec(I);
LMB_WriteDBus_vec_i(I) <= LMB_WriteDBus_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_i(I) <= LMB_AddrStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_i(I) <= LMB_ReadStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_i(I) <= LMB_WriteStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteStrobe_vec(I);
LMB_BE_vec_i(I) <= LMB_BE_vec_Q(I) when wait_vec(I) = '1' else
LMB_BE_vec(I);
-- Assign selected LMB from internal signals
Sl_DBus_vec(I) <= Sl_DBus;
Sl_Ready_vec(I) <= Sl_Ready when ongoing_Q = I else
'0';
Sl_Wait_vec(I) <= Sl_Wait when ongoing_Q = I else
wait_vec(I);
Sl_UE_vec(I) <= Sl_UE when ongoing_Q = I else
'0';
Sl_CE_vec(I) <= Sl_CE when ongoing_Q = I else
'0';
end generate lmb_mux_generate;
OnGoing_Reg : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
ongoing_Q <= 0;
else
ongoing_Q <= ongoing;
end if;
end if;
end process OnGoing_Reg;
Arbit : process (as_and_lmb_select_vec, wait_vec) is
variable N : natural range 0 to C_NUM_LMB-1;
begin
ongoing_new <= 0;
for N in 0 to C_NUM_LMB - 1 loop
if as_and_lmb_select_vec(N) = '1' or wait_vec(N) = '1' then
ongoing_new <= N;
exit;
end if;
end loop;
end process Arbit;
ongoing <= ongoing_Q when Sl_Wait = '1' and Sl_Ready = '0' else
ongoing_new;
-- Assign selected LMB
LMB_ABus <= LMB_ABus_vec_i(ongoing);
LMB_WriteDBus <= LMB_WriteDBus_vec_i(ongoing);
LMB_AddrStrobe <= LMB_AddrStrobe_vec_i(ongoing);
LMB_ReadStrobe <= LMB_ReadStrobe_vec_i(ongoing);
LMB_WriteStrobe <= LMB_WriteStrobe_vec_i(ongoing);
LMB_BE <= LMB_BE_vec_i(ongoing);
lmb_select <= lmb_select_vec(ongoing) or wait_vec(ongoing);
end generate more_than_one_lmb;
end imp;
-------------------------------------------------------------------------------
-- lmb_bram_if_cntlr.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 63) := X"0000000000000000";
C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
C_MASK : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- BRAM generic
C_BRAM_AWIDTH : integer := 32;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_BRAM_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library lmb_bram_if_cntlr_v4_0_10;
use lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 63) := X"FFFFFFFFFFFFFFFF";
C_MASK : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK1 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK2 : std_logic_vector(0 to 63) := X"0000000000800000";
C_MASK3 : std_logic_vector(0 to 63) := X"0000000000800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
assert C_LMB_AWIDTH >= C_BRAM_AWIDTH
report "C_LMB_AWIDTH must be greater than or equal to C_BRAM_AWIDTH"
severity failure;
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i(C_LMB_AWIDTH - C_BRAM_AWIDTH to C_LMB_AWIDTH - 1);
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
assert C_LMB_DWIDTH = 32 report "C_LMB_DWIDTH must be 32 when C_ECC = 1" severity failure;
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => false) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_TARGET => C_TARGET,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr(C_LMB_AWIDTH - C_BRAM_AWIDTH to C_LMB_AWIDTH - 1);
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_TARGET => C_TARGET,
C_ENCODE => true) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
BRAM_Dout_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_TARGET => C_TARGET,
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
|
apache-2.0
|
7c24f2efe48e80d771bbcd4e105d015c
| 0.520693 | 3.771066 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/WindowsManager_tb.vhd
| 1 | 2,175 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY WindowsManager_tb IS
END WindowsManager_tb;
ARCHITECTURE behavior OF WindowsManager_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT WindowsManager
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic;
nRs1 : OUT std_logic_vector(5 downto 0);
nRs2 : OUT std_logic_vector(5 downto 0);
nRd : OUT std_logic_vector(5 downto 0);
nCWP : OUT std_logic
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal rd : std_logic_vector(4 downto 0) := (others => '0');
signal op : std_logic_vector(1 downto 0) := (others => '0');
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
signal CWP : std_logic := '0';
--Outputs
signal nRs1 : std_logic_vector(5 downto 0);
signal nRs2 : std_logic_vector(5 downto 0);
signal nRd : std_logic_vector(5 downto 0);
signal nCWP : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: WindowsManager PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
op => op,
op3 => op3,
CWP => CWP,
nRs1 => nRs1,
nRs2 => nRs2,
nRd => nRd,
nCWP => nCWP
);
-- Stimulus process
stim_proc: process
begin
rs1<="01000";
rs2<="10000";
rd<="11000";
op<="10";
op3<="000000"; --suma
CWP<='0';
wait for 20 ns;
CWP<='1';
wait for 20 ns;
op3<="000100"; --resta
wait for 20 ns;
rs1<="00100";
rs2<="00001";
rd<="11011";
op3<="111100"; --save
wait for 20 ns;
op3<="000010"; -- OR
wait for 20 ns;
rs1<="00111";
rs2<="10001";
rd<="10011";
op3<="111101"; --restore
wait;
end process;
END;
|
mit
|
04d8ab50e47b10192f6ecd386e863084
| 0.529655 | 3.361669 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/lib/mux/mux8_bit.vhd
| 1 | 772 |
--Helpful resource:
--ftp://www.cs.uregina.ca/pub/class/301/multiplexer/lecture.html
library IEEE;
use IEEE.std_logic_1164.all;
entity mux8_bit is
port(
bit0 : in std_logic := '-';
bit1 : in std_logic := '-';
bit2 : in std_logic := '-';
bit3 : in std_logic := '-';
bit4 : in std_logic := '-';
bit5 : in std_logic := '-';
bit6 : in std_logic := '-';
bit7 : in std_logic := '-';
S : in std_logic_vector(2 downto 0);
R : out std_logic
);
end mux8_bit;
architecture Behavioural of mux8_bit is
begin
with S select
R <= bit0 when "000",
bit1 when "001",
bit2 when "010",
bit3 when "011",
bit4 when "100",
bit5 when "101",
bit6 when "110",
bit7 when others;
end Behavioural;
|
agpl-3.0
|
86bb2b6307c73268351ee43d779f01cd
| 0.559585 | 3.088 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/InstructionMemory.vhd
| 1 | 3,283 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity InstructionMemory is
Port ( Address : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionMemory;
architecture syn of InstructionMemory is
type rom_type is array (63 downto 0) of std_logic_vector (31 downto 0);
signal ROM : rom_type:= ("00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","00000001000000000000000000000000",
"00000001000000000000000000000000","10010000000100000000000000010000",
"10000100010000000000000000000001","10000000101000000010000000000100",--"10101100100001010100000000010101",
"10000001111000000010000000000000","10100000000000000110000000000011",
"10000001111010000010000000000000","10110011001101000110000000000001",
"10110001001010000110000000000010","10100010000100000010000000000100",
"10100000000100000011111111111000","10000010000100000010000000000101");
begin
process(rst,Address,ROM)
begin
if rst='1' then
Instruction<=(others=>'0');
else
Instruction<=ROM(conv_integer(Address));
end if;
end process;
end syn;
|
mit
|
670b278ff5070e124523928b4765ece4
| 0.757843 | 8.106173 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_rst_mig_7series_0_83M_0/sim/system_rst_mig_7series_0_83M_0.vhd
| 1 | 5,883 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY system_rst_mig_7series_0_83M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_mig_7series_0_83M_0;
ARCHITECTURE system_rst_mig_7series_0_83M_0_arch OF system_rst_mig_7series_0_83M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_mig_7series_0_83M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_mig_7series_0_83M_0_arch;
|
apache-2.0
|
f18edaf80fc9d71211bb33a129d885ae
| 0.707292 | 3.558984 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/RegisterExtended16Bit.vhd
| 1 | 8,106 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/13/2015 12:36:25 PM
-- Design Name:
-- Module Name: RegisterExtended16Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RegisterExtended16Bit is
Port
(
Load_8Bit_L: in BIT; -- Load Line #1 (bits 0 - 7)
Load_8Bit_H: in BIT; -- Load Line #2 (bits 8 - 15)
Load_16Bit: in BIT; -- Load Line #3 (bits 0 - 15)
Select_8Bit_L: in BIT; -- Select Line #1 (bits 0 - 7)
Select_8Bit_H: in BIT; -- Select Line #2 (bits 8 - 15)
Select_16Bit: in BIT; -- Select Line #3 (bits 0 - 15)
Input_8Bit_L: in BIT_VECTOR(7 downto 0); -- 8-bit input value (bits 0 - 7)
Input_8Bit_H: in BIT_VECTOR(7 downto 0); -- 8-bit input value (bits 8 - 15)
Input_16Bit: in BIT_VECTOR(15 downto 0); -- 16-bit input value (bits 0 - 15)
Output_8Bit_L: out BIT_VECTOR(7 downto 0); -- 8-bit output value (bits 0 - 7)
Output_8Bit_H: out BIT_VECTOR(7 downto 0); -- 8-bit output value (bits 8 - 15)
Output_16Bit: out BIT_VECTOR(15 downto 0); -- 16-bit output value (bits 0 - 15)
State_8Bit_L: out BIT_VECTOR(7 downto 0); -- Current state of the Flip Flop (bits 0 - 7)
State_8Bit_H: out BIT_VECTOR(7 downto 0); -- Current state of the Flip Flop (bits 8 - 15)
State_16Bit: out BIT_VECTOR(15 downto 0) -- Current state of the Flip Flop (bits 0 - 15)
);
end RegisterExtended16Bit;
architecture Behavioral of RegisterExtended16Bit is
component Register8Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
State : out BIT_VECTOR(7 downto 0) -- Current state of the Flip Flop
);
end component Register8Bit;
signal Load8Bit_Low: BIT;
signal Load8Bit_High: BIT;
signal Select8Bit_Low: BIT;
signal Select8Bit_High: BIT;
signal Input8Bit_Low: BIT_VECTOR(7 downto 0);
signal Input8Bit_High: BIT_VECTOR(7 downto 0);
signal Output8Bit_Low: BIT_VECTOR(7 downto 0);
signal Output8Bit_High: BIT_VECTOR(7 downto 0);
signal State8Bit_Low: BIT_VECTOR(7 downto 0);
signal State8Bit_High: BIT_VECTOR(7 downto 0);
begin
registerLow: Register8Bit port map (Load8Bit_Low, Select8Bit_Low, Input8Bit_Low, Output8Bit_Low, State8Bit_Low);
registerHigh: Register8Bit port map (Load8Bit_High, Select8Bit_High, Input8Bit_High, Output8Bit_High, State8Bit_High);
-- Provides the Load-Line flags
Load8Bit_Low <= Load_16Bit or Load_8Bit_L;
Load8Bit_High <= Load_16Bit or Load_8Bit_H;
-- Provides the Select-Line flags
Select8Bit_Low <= Select_16Bit or Select_8Bit_L;
Select8Bit_High <= Select_16Bit or Select_8Bit_H;
-- Provides the input for bits 0 - 7
Input8Bit_Low(0) <= (Input_8Bit_L(0) and Load_8Bit_L) or
(Input_16Bit(0) and Load_16Bit);
Input8Bit_Low(1) <= (Input_8Bit_L(1) and Load_8Bit_L) or
(Input_16Bit(1) and Load_16Bit);
Input8Bit_Low(2) <= (Input_8Bit_L(2) and Load_8Bit_L) or
(Input_16Bit(2) and Load_16Bit);
Input8Bit_Low(3) <= (Input_8Bit_L(3) and Load_8Bit_L) or
(Input_16Bit(3) and Load_16Bit);
Input8Bit_Low(4) <= (Input_8Bit_L(4) and Load_8Bit_L) or
(Input_16Bit(4) and Load_16Bit);
Input8Bit_Low(5) <= (Input_8Bit_L(5) and Load_8Bit_L) or
(Input_16Bit(5) and Load_16Bit);
Input8Bit_Low(6) <= (Input_8Bit_L(6) and Load_8Bit_L) or
(Input_16Bit(6) and Load_16Bit);
Input8Bit_Low(7) <= (Input_8Bit_L(7) and Load_8Bit_L) or
(Input_16Bit(7) and Load_16Bit);
-- Provides the input for bits 8 - 15
Input8Bit_High(0) <= (Input_8Bit_H(0) and Load_8Bit_H) or
(Input_16Bit(8) and Load_16Bit);
Input8Bit_High(1) <= (Input_8Bit_H(1) and Load_8Bit_H) or
(Input_16Bit(9) and Load_16Bit);
Input8Bit_High(2) <= (Input_8Bit_H(2) and Load_8Bit_H) or
(Input_16Bit(10) and Load_16Bit);
Input8Bit_High(3) <= (Input_8Bit_H(3) and Load_8Bit_H) or
(Input_16Bit(11) and Load_16Bit);
Input8Bit_High(4) <= (Input_8Bit_H(4) and Load_8Bit_H) or
(Input_16Bit(12) and Load_16Bit);
Input8Bit_High(5) <= (Input_8Bit_H(5) and Load_8Bit_H) or
(Input_16Bit(13) and Load_16Bit);
Input8Bit_High(6) <= (Input_8Bit_H(6) and Load_8Bit_H) or
(Input_16Bit(14) and Load_16Bit);
Input8Bit_High(7) <= (Input_8Bit_H(7) and Load_8Bit_H) or
(Input_16Bit(15) and Load_16Bit);
-- Returns the output for bits 0 - 7 on the data bus
Output_8Bit_L(0) <= Output8Bit_Low(0) and Select_8Bit_L;
Output_8Bit_L(1) <= Output8Bit_Low(1) and Select_8Bit_L;
Output_8Bit_L(2) <= Output8Bit_Low(2) and Select_8Bit_L;
Output_8Bit_L(3) <= Output8Bit_Low(3) and Select_8Bit_L;
Output_8Bit_L(4) <= Output8Bit_Low(4) and Select_8Bit_L;
Output_8Bit_L(5) <= Output8Bit_Low(5) and Select_8Bit_L;
Output_8Bit_L(6) <= Output8Bit_Low(6) and Select_8Bit_L;
Output_8Bit_L(7) <= Output8Bit_Low(7) and Select_8Bit_L;
-- Returns the output for bits 8 - 15 on the data bus
Output_8Bit_H(0) <= Output8Bit_High(0) and Select_8Bit_H;
Output_8Bit_H(1) <= Output8Bit_High(1) and Select_8Bit_H;
Output_8Bit_H(2) <= Output8Bit_High(2) and Select_8Bit_H;
Output_8Bit_H(3) <= Output8Bit_High(3) and Select_8Bit_H;
Output_8Bit_H(4) <= Output8Bit_High(4) and Select_8Bit_H;
Output_8Bit_H(5) <= Output8Bit_High(5) and Select_8Bit_H;
Output_8Bit_H(6) <= Output8Bit_High(6) and Select_8Bit_H;
Output_8Bit_H(7) <= Output8Bit_High(7) and Select_8Bit_H;
-- Returns the output for bits 0 - 7 on the address bus
Output_16Bit(0) <= Output8Bit_Low(0) and Select_16Bit;
Output_16Bit(1) <= Output8Bit_Low(1) and Select_16Bit;
Output_16Bit(2) <= Output8Bit_Low(2) and Select_16Bit;
Output_16Bit(3) <= Output8Bit_Low(3) and Select_16Bit;
Output_16Bit(4) <= Output8Bit_Low(4) and Select_16Bit;
Output_16Bit(5) <= Output8Bit_Low(5) and Select_16Bit;
Output_16Bit(6) <= Output8Bit_Low(6) and Select_16Bit;
Output_16Bit(7) <= Output8Bit_Low(7) and Select_16Bit;
-- Returns the output for bits 8 - 15 on the address bus
Output_16Bit(8) <= Output8Bit_High(0) and Select_16Bit;
Output_16Bit(9) <= Output8Bit_High(1) and Select_16Bit;
Output_16Bit(10) <= Output8Bit_High(2) and Select_16Bit;
Output_16Bit(11) <= Output8Bit_High(3) and Select_16Bit;
Output_16Bit(12) <= Output8Bit_High(4) and Select_16Bit;
Output_16Bit(13) <= Output8Bit_High(5) and Select_16Bit;
Output_16Bit(14) <= Output8Bit_High(6) and Select_16Bit;
Output_16Bit(15) <= Output8Bit_High(7) and Select_16Bit;
-- Returns the current state
State_8Bit_L <= State8Bit_Low;
State_8Bit_H <= State8Bit_High;
State_16Bit(7 downto 0) <= State8Bit_Low;
State_16Bit(15 downto 8) <= State8Bit_High;
end Behavioral;
|
mit
|
b7a4fe76d5dee65909b2aa2edec311f1
| 0.59092 | 3 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_0/sim/system_microblaze_0_0.vhd
| 1 | 62,476 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:10.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v10_0_1;
USE microblaze_v10_0_1.MicroBlaze;
ENTITY system_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END system_microblaze_0_0;
ARCHITECTURE system_microblaze_0_0_arch OF system_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_LOCKSTEP_MASTER : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTR_SIZE : INTEGER;
C_IADDR_SIZE : INTEGER;
C_DADDR_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_NON_SECURE : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_ASYNC_WAKEUP : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR;
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR;
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR;
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR;
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
RAM_Static : IN STD_LOGIC_VECTOR(1023 DOWNTO 0);
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Hibernate : OUT STD_LOGIC;
Suspend : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Dbg_Continue : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
Pause : IN STD_LOGIC;
Pause_Ack : OUT STD_LOGIC;
Non_Secure : IN STD_LOGIC_VECTOR(0 TO 3);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Dbg_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID : IN STD_LOGIC;
Dbg_AWREADY : OUT STD_LOGIC;
Dbg_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID : IN STD_LOGIC;
Dbg_WREADY : OUT STD_LOGIC;
Dbg_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID : OUT STD_LOGIC;
Dbg_BREADY : IN STD_LOGIC;
Dbg_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID : IN STD_LOGIC;
Dbg_ARREADY : OUT STD_LOGIC;
Dbg_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID : OUT STD_LOGIC;
Dbg_RREADY : IN STD_LOGIC;
DEBUG_ACLK : IN STD_LOGIC;
DEBUG_ARESETN : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Disable: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG DISABLE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_LOCKSTEP_MASTER => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTR_SIZE => 32,
C_IADDR_SIZE => 32,
C_DADDR_SIZE => 32,
C_INSTANCE => "system_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"0000000000000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_NON_SECURE => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_DEBUG_INTERFACE => 0,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_ASYNC_WAKEUP => 3,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"0000000080000000",
C_ICACHE_HIGHADDR => X"000000008FFFFFFF",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 14,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"0000000080000000",
C_DCACHE_HIGHADDR => X"000000008fffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 14,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
RAM_Static => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1024)),
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Pause => '0',
Non_Secure => X"0",
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
Dbg_Disable => Dbg_Disable,
Dbg_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
Dbg_AWVALID => '0',
Dbg_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_WVALID => '0',
Dbg_BREADY => '0',
Dbg_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
Dbg_ARVALID => '0',
Dbg_RREADY => '0',
DEBUG_ACLK => '0',
DEBUG_ARESETN => '0',
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END system_microblaze_0_0_arch;
|
apache-2.0
|
ad18260af033e3988bfb1e920a978d33
| 0.634372 | 2.927648 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xbar_1/system_xbar_1_sim_netlist.vhdl
| 1 | 337,684 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:43:26 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xbar_1/system_xbar_1_sim_netlist.vhdl
-- Design : system_xbar_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_sasd is
port (
m_valid_i : out STD_LOGIC;
reset : out STD_LOGIC;
aa_grant_rnw : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\m_atarget_enc_reg[0]\ : out STD_LOGIC;
\m_atarget_enc_reg[1]\ : out STD_LOGIC;
\m_atarget_enc_reg[2]\ : out STD_LOGIC;
\m_atarget_enc_reg[3]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\m_atarget_enc_reg[1]_rep\ : out STD_LOGIC;
\m_atarget_enc_reg[0]_rep\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
\m_ready_d_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]_1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_axilite.s_axi_bvalid_i_reg_0\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC;
\gen_axilite.s_axi_rvalid_i_reg\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 12 downto 0 );
\m_ready_d_reg[0]_2\ : out STD_LOGIC;
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_bvalid_i_reg_1\ : out STD_LOGIC;
aclk : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\m_ready_d_reg[0]_3\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[3]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[0]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_2\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_atarget_enc_reg[2]_3\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_4\ : in STD_LOGIC;
\m_atarget_enc_reg[3]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_5\ : in STD_LOGIC;
\m_atarget_hot_reg[14]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_enc_reg[1]_0\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_atarget_enc_reg[3]_2\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
\m_atarget_enc_reg[2]_6\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_7\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_8\ : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
mi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_sasd : entity is "axi_crossbar_v2_1_12_addr_arbiter_sasd";
end system_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_sasd;
architecture STRUCTURE of system_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_sasd is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal aa_grant_any : STD_LOGIC;
signal \^aa_grant_rnw\ : STD_LOGIC;
signal \gen_axilite.s_axi_bvalid_i_i_2_n_0\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg\ : STD_LOGIC;
signal \^gen_axilite.s_axi_bvalid_i_reg_0\ : STD_LOGIC;
signal \^gen_axilite.s_axi_rvalid_i_reg\ : STD_LOGIC;
signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_6_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_enc[0]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_enc[3]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_enc[3]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_enc[3]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[0]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[11]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[11]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[11]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_hot[12]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[13]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[14]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[14]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[14]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_hot[14]_i_5_n_0\ : STD_LOGIC;
signal \m_atarget_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[3]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[3]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[4]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[4]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[5]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_3_n_0\ : STD_LOGIC;
signal \m_atarget_hot[6]_i_4_n_0\ : STD_LOGIC;
signal \m_atarget_hot[7]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[8]_i_2_n_0\ : STD_LOGIC;
signal \m_atarget_hot[9]_i_2_n_0\ : STD_LOGIC;
signal \m_ready_d[0]_i_4_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_1\ : STD_LOGIC;
signal \^m_ready_d_reg[1]\ : STD_LOGIC;
signal \^m_ready_d_reg[2]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal \^reset\ : STD_LOGIC;
signal s_amesg : STD_LOGIC_VECTOR ( 48 downto 1 );
signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
signal s_awvalid_reg : STD_LOGIC;
signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal s_ready_i : STD_LOGIC;
signal \splitter_aw/m_ready_d0\ : STD_LOGIC_VECTOR ( 1 to 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_axilite.s_axi_bvalid_i_i_4\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_atarget_enc[3]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_atarget_enc[3]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_atarget_hot[0]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_atarget_hot[12]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \m_atarget_hot[13]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_atarget_hot[13]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_atarget_hot[14]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_atarget_hot[14]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_atarget_hot[14]_i_4\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_atarget_hot[14]_i_5\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_atarget_hot[5]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_atarget_hot[6]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_atarget_hot[7]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[8]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_atarget_hot[9]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_axi_arvalid[11]_INST_0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_axi_arvalid[12]_INST_0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_axi_arvalid[13]_INST_0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_axi_arvalid[4]_INST_0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_axi_arvalid[5]_INST_0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_axi_arvalid[6]_INST_0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_axi_arvalid[7]_INST_0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_axi_arvalid[8]_INST_0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_axi_arvalid[9]_INST_0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_axi_awvalid[11]_INST_0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_axi_awvalid[12]_INST_0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_axi_awvalid[13]_INST_0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_axi_awvalid[4]_INST_0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_axi_awvalid[5]_INST_0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_axi_awvalid[6]_INST_0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_axi_awvalid[7]_INST_0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_axi_awvalid[8]_INST_0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_axi_awvalid[9]_INST_0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_axi_bready[8]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_wvalid[11]_INST_0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_axi_wvalid[12]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_axi_wvalid[13]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_axi_wvalid[9]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_ready_d[0]_i_3\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of m_valid_i_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \s_axi_arready[0]_INST_0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \s_axi_wready[0]_INST_0_i_4\ : label is "soft_lutpair2";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
aa_grant_rnw <= \^aa_grant_rnw\;
\gen_axilite.s_axi_bvalid_i_reg\ <= \^gen_axilite.s_axi_bvalid_i_reg\;
\gen_axilite.s_axi_bvalid_i_reg_0\ <= \^gen_axilite.s_axi_bvalid_i_reg_0\;
\gen_axilite.s_axi_rvalid_i_reg\ <= \^gen_axilite.s_axi_rvalid_i_reg\;
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
\m_ready_d_reg[0]_1\ <= \^m_ready_d_reg[0]_1\;
\m_ready_d_reg[1]\ <= \^m_ready_d_reg[1]\;
\m_ready_d_reg[2]\ <= \^m_ready_d_reg[2]\;
m_valid_i <= \^m_valid_i\;
reset <= \^reset\;
\gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5050F0F05C50F0F0"
)
port map (
I0 => \gen_axilite.s_axi_bvalid_i_i_2_n_0\,
I1 => mi_wready(0),
I2 => mi_bvalid(0),
I3 => \^gen_axilite.s_axi_bvalid_i_reg\,
I4 => \m_atarget_hot_reg[14]\(13),
I5 => \^gen_axilite.s_axi_bvalid_i_reg_0\,
O => \gen_axilite.s_axi_bvalid_i_reg_1\
);
\gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_bready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(0),
O => \gen_axilite.s_axi_bvalid_i_i_2_n_0\
);
\gen_axilite.s_axi_bvalid_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(1),
O => \^gen_axilite.s_axi_bvalid_i_reg\
);
\gen_axilite.s_axi_bvalid_i_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => m_ready_d(2),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \^gen_axilite.s_axi_bvalid_i_reg_0\
);
\gen_axilite.s_axi_rvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => m_ready_d_0(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \^gen_axilite.s_axi_rvalid_i_reg\
);
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF5300000050"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_awvalid(0),
I2 => s_axi_arvalid(0),
I3 => aa_grant_any,
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.grant_rnw_i_1_n_0\
);
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
Q => \^aa_grant_rnw\,
R => \^reset\
);
\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(9),
O => s_amesg(10)
);
\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(10),
O => s_amesg(11)
);
\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(11),
O => s_amesg(12)
);
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(12),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(12),
O => s_amesg(13)
);
\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(13),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(13),
O => s_amesg(14)
);
\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(14),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(14),
O => s_amesg(15)
);
\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(15),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(15),
O => s_amesg(16)
);
\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(16),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(16),
O => s_amesg(17)
);
\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(17),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(17),
O => s_amesg(18)
);
\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(18),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(18),
O => s_amesg(19)
);
\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(0),
O => s_amesg(1)
);
\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(19),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(19),
O => s_amesg(20)
);
\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(20),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(20),
O => s_amesg(21)
);
\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(21),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(21),
O => s_amesg(22)
);
\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(22),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(22),
O => s_amesg(23)
);
\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(23),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(23),
O => s_amesg(24)
);
\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(24),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(24),
O => s_amesg(25)
);
\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(25),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(25),
O => s_amesg(26)
);
\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(26),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(26),
O => s_amesg(27)
);
\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(27),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(27),
O => s_amesg(28)
);
\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(28),
O => s_amesg(29)
);
\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(1),
O => s_amesg(2)
);
\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(29),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(29),
O => s_amesg(30)
);
\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(30),
O => s_amesg(31)
);
\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^reset\
);
\gen_no_arbiter.m_amesg_i[32]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aa_grant_any,
O => p_0_in1_in
);
\gen_no_arbiter.m_amesg_i[32]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(31),
O => s_amesg(32)
);
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(2),
O => s_amesg(3)
);
\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(0),
O => s_amesg(46)
);
\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(1),
O => s_amesg(47)
);
\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(2),
O => s_amesg(48)
);
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(3),
O => s_amesg(4)
);
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(4),
O => s_amesg(5)
);
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(5),
O => s_amesg(6)
);
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(6),
O => s_amesg(7)
);
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(7),
O => s_amesg(8)
);
\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(8),
O => s_amesg(9)
);
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(10),
Q => \^q\(9),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(11),
Q => \^q\(10),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(12),
Q => \^q\(11),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(13),
Q => \^q\(12),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(14),
Q => \^q\(13),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(15),
Q => \^q\(14),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(16),
Q => \^q\(15),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(17),
Q => \^q\(16),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(18),
Q => \^q\(17),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(19),
Q => \^q\(18),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(1),
Q => \^q\(0),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(20),
Q => \^q\(19),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(21),
Q => \^q\(20),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(22),
Q => \^q\(21),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(23),
Q => \^q\(22),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(24),
Q => \^q\(23),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(25),
Q => \^q\(24),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(26),
Q => \^q\(25),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(27),
Q => \^q\(26),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(28),
Q => \^q\(27),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(29),
Q => \^q\(28),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(2),
Q => \^q\(1),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(30),
Q => \^q\(29),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(31),
Q => \^q\(30),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(32),
Q => \^q\(31),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(3),
Q => \^q\(2),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(46),
Q => \^q\(32),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(47),
Q => \^q\(33),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(48),
Q => \^q\(34),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(4),
Q => \^q\(3),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(5),
Q => \^q\(4),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(6),
Q => \^q\(5),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(7),
Q => \^q\(6),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(8),
Q => \^q\(7),
R => \^reset\
);
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(9),
Q => \^q\(8),
R => \^reset\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DDDC0000"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => s_axi_arvalid(0),
I3 => s_axi_awvalid(0),
I4 => aresetn_d,
I5 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_grant_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\,
Q => aa_grant_any,
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF02000000020000"
)
port map (
I0 => \splitter_aw/m_ready_d0\(1),
I1 => \m_ready_d_reg[0]_3\,
I2 => \^m_ready_d_reg[2]\,
I3 => \^aa_grant_rnw\,
I4 => \^m_valid_i\,
I5 => \m_ready_d[0]_i_4_n_0\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF47FF44FF00FF00"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_i_4_n_0\,
I1 => m_atarget_enc(0),
I2 => \gen_no_arbiter.m_valid_i_i_5_n_0\,
I3 => m_ready_d(1),
I4 => \m_atarget_enc_reg[1]_0\,
I5 => s_axi_wvalid(0),
O => \splitter_aw/m_ready_d0\(1)
);
\gen_no_arbiter.m_valid_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAE00FFFFAEFF"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_i_6_n_0\,
I1 => m_atarget_enc(3),
I2 => m_axi_wready(5),
I3 => m_atarget_enc(1),
I4 => \s_axi_wready[0]_INST_0_i_4_n_0\,
I5 => \s_axi_wready[0]_INST_0_i_3_n_0\,
O => \gen_no_arbiter.m_valid_i_i_4_n_0\
);
\gen_no_arbiter.m_valid_i_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
O => \gen_no_arbiter.m_valid_i_i_5_n_0\
);
\gen_no_arbiter.m_valid_i_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"C4C7"
)
port map (
I0 => m_axi_wready(3),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_axi_wready(1),
O => \gen_no_arbiter.m_valid_i_i_6_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^m_valid_i\,
R => \^reset\
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => aresetn_d,
O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
Q => s_ready_i,
R => '0'
);
\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => \m_atarget_hot[13]_i_2_n_0\,
I1 => \m_atarget_hot[5]_i_2_n_0\,
I2 => \m_atarget_hot[9]_i_2_n_0\,
I3 => \m_atarget_hot[1]_i_2_n_0\,
I4 => \m_atarget_enc[0]_i_2_n_0\,
O => \m_atarget_enc_reg[0]\
);
\m_atarget_enc[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545555555555545"
)
port map (
I0 => \m_atarget_hot[3]_i_2_n_0\,
I1 => \m_atarget_hot[11]_i_3_n_0\,
I2 => \m_atarget_hot[11]_i_4_n_0\,
I3 => \m_atarget_hot[14]_i_5_n_0\,
I4 => \^q\(17),
I5 => \^q\(16),
O => \m_atarget_enc[0]_i_2_n_0\
);
\m_atarget_enc[0]_rep_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => \m_atarget_hot[13]_i_2_n_0\,
I1 => \m_atarget_hot[5]_i_2_n_0\,
I2 => \m_atarget_hot[9]_i_2_n_0\,
I3 => \m_atarget_hot[1]_i_2_n_0\,
I4 => \m_atarget_enc[0]_i_2_n_0\,
O => \m_atarget_enc_reg[0]_rep\
);
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBBF"
)
port map (
I0 => \m_atarget_hot[6]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_2_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_4_n_0\,
O => \m_atarget_enc_reg[1]\
);
\m_atarget_enc[1]_rep_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBBF"
)
port map (
I0 => \m_atarget_hot[6]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_2_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_4_n_0\,
O => \m_atarget_enc_reg[1]_rep\
);
\m_atarget_enc[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEFFFE"
)
port map (
I0 => \m_atarget_hot[7]_i_2_n_0\,
I1 => \m_atarget_hot[5]_i_2_n_0\,
I2 => \m_atarget_hot[14]_i_2_n_0\,
I3 => \m_atarget_hot[14]_i_3_n_0\,
I4 => \m_atarget_hot[14]_i_4_n_0\,
O => \m_atarget_enc_reg[2]\
);
\m_atarget_enc[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEEEEFE"
)
port map (
I0 => \m_atarget_hot[11]_i_2_n_0\,
I1 => \m_atarget_enc[3]_i_2_n_0\,
I2 => \m_atarget_hot[14]_i_2_n_0\,
I3 => \m_atarget_hot[14]_i_3_n_0\,
I4 => \m_atarget_enc[3]_i_3_n_0\,
I5 => \m_atarget_enc[3]_i_4_n_0\,
O => \m_atarget_enc_reg[3]\
);
\m_atarget_enc[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00100000"
)
port map (
I0 => \^q\(16),
I1 => \^q\(17),
I2 => \^q\(18),
I3 => \^q\(19),
I4 => \m_atarget_hot[8]_i_2_n_0\,
I5 => \m_atarget_hot[13]_i_2_n_0\,
O => \m_atarget_enc[3]_i_2_n_0\
);
\m_atarget_enc[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \m_atarget_hot[0]_i_2_n_0\,
I1 => \m_atarget_hot[5]_i_2_n_0\,
I2 => \m_atarget_hot[1]_i_2_n_0\,
O => \m_atarget_enc[3]_i_3_n_0\
);
\m_atarget_enc[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"01100000"
)
port map (
I0 => \^q\(19),
I1 => \^q\(18),
I2 => \^q\(17),
I3 => \^q\(16),
I4 => \m_atarget_hot[8]_i_2_n_0\,
O => \m_atarget_enc[3]_i_4_n_0\
);
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[0]_i_2_n_0\,
I1 => aa_grant_any,
O => D(0)
);
\m_atarget_hot[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \m_atarget_hot[11]_i_4_n_0\,
I1 => \m_atarget_hot[0]_i_3_n_0\,
I2 => \^q\(16),
I3 => \^q\(17),
I4 => \^q\(19),
I5 => \^q\(18),
O => \m_atarget_hot[0]_i_2_n_0\
);
\m_atarget_hot[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFEFFF"
)
port map (
I0 => \^q\(23),
I1 => \^q\(20),
I2 => \^q\(21),
I3 => \^q\(24),
I4 => \^q\(25),
I5 => \^q\(22),
O => \m_atarget_hot[0]_i_3_n_0\
);
\m_atarget_hot[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[11]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(10)
);
\m_atarget_hot[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => \m_atarget_hot[11]_i_3_n_0\,
I1 => \m_atarget_hot[11]_i_4_n_0\,
I2 => \^q\(16),
I3 => \^q\(18),
I4 => \^q\(19),
I5 => \^q\(17),
O => \m_atarget_hot[11]_i_2_n_0\
);
\m_atarget_hot[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^q\(25),
I1 => \^q\(22),
I2 => \^q\(24),
I3 => \^q\(21),
I4 => \^q\(20),
I5 => \^q\(23),
O => \m_atarget_hot[11]_i_3_n_0\
);
\m_atarget_hot[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^q\(27),
I1 => \^q\(30),
I2 => \^q\(26),
I3 => \^q\(29),
I4 => \^q\(28),
I5 => \^q\(31),
O => \m_atarget_hot[11]_i_4_n_0\
);
\m_atarget_hot[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[12]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(11)
);
\m_atarget_hot[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \m_atarget_hot[8]_i_2_n_0\,
I1 => \^q\(19),
I2 => \^q\(18),
I3 => \^q\(17),
I4 => \^q\(16),
O => \m_atarget_hot[12]_i_2_n_0\
);
\m_atarget_hot[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[13]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(12)
);
\m_atarget_hot[13]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \^q\(16),
I1 => \^q\(17),
I2 => \^q\(18),
I3 => \^q\(19),
I4 => \m_atarget_hot[4]_i_2_n_0\,
O => \m_atarget_hot[13]_i_2_n_0\
);
\m_atarget_hot[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => aa_grant_any,
I1 => \m_atarget_hot[14]_i_2_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_4_n_0\,
O => D(13)
);
\m_atarget_hot[14]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \m_atarget_enc[0]_i_2_n_0\,
I1 => \m_atarget_hot[2]_i_2_n_0\,
O => \m_atarget_hot[14]_i_2_n_0\
);
\m_atarget_hot[14]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFAAAB"
)
port map (
I0 => \m_atarget_hot[12]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_5_n_0\,
I2 => \^q\(16),
I3 => \m_atarget_hot[4]_i_2_n_0\,
I4 => \m_atarget_hot[6]_i_2_n_0\,
O => \m_atarget_hot[14]_i_3_n_0\
);
\m_atarget_hot[14]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \m_atarget_enc[3]_i_4_n_0\,
I1 => \m_atarget_hot[1]_i_2_n_0\,
I2 => \m_atarget_hot[5]_i_2_n_0\,
I3 => \m_atarget_hot[0]_i_2_n_0\,
O => \m_atarget_hot[14]_i_4_n_0\
);
\m_atarget_hot[14]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^q\(18),
I1 => \^q\(19),
O => \m_atarget_hot[14]_i_5_n_0\
);
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[1]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(1)
);
\m_atarget_hot[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000800"
)
port map (
I0 => \m_atarget_hot[11]_i_4_n_0\,
I1 => \^q\(22),
I2 => \^q\(25),
I3 => \^q\(21),
I4 => \^q\(24),
I5 => \m_atarget_hot[2]_i_3_n_0\,
O => \m_atarget_hot[1]_i_2_n_0\
);
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \m_atarget_hot[2]_i_2_n_0\,
I1 => aa_grant_any,
O => D(2)
);
\m_atarget_hot[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000400000"
)
port map (
I0 => \^q\(21),
I1 => \m_atarget_hot[11]_i_4_n_0\,
I2 => \^q\(22),
I3 => \^q\(25),
I4 => \^q\(24),
I5 => \m_atarget_hot[2]_i_3_n_0\,
O => \m_atarget_hot[2]_i_2_n_0\
);
\m_atarget_hot[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFD"
)
port map (
I0 => \^q\(23),
I1 => \^q\(20),
I2 => \^q\(18),
I3 => \^q\(19),
I4 => \^q\(17),
I5 => \^q\(16),
O => \m_atarget_hot[2]_i_3_n_0\
);
\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[3]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(3)
);
\m_atarget_hot[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => \m_atarget_hot[11]_i_4_n_0\,
I1 => \^q\(23),
I2 => \^q\(20),
I3 => \m_atarget_hot[3]_i_3_n_0\,
I4 => \m_atarget_hot[6]_i_4_n_0\,
O => \m_atarget_hot[3]_i_2_n_0\
);
\m_atarget_hot[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(22),
I1 => \^q\(25),
I2 => \^q\(21),
I3 => \^q\(24),
O => \m_atarget_hot[3]_i_3_n_0\
);
\m_atarget_hot[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \^q\(18),
I1 => \^q\(19),
I2 => \^q\(17),
I3 => \^q\(16),
I4 => \m_atarget_hot[4]_i_2_n_0\,
I5 => aa_grant_any,
O => D(4)
);
\m_atarget_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFBFFFFFF"
)
port map (
I0 => \m_atarget_hot[6]_i_3_n_0\,
I1 => \^q\(30),
I2 => \^q\(27),
I3 => \^q\(26),
I4 => \^q\(21),
I5 => \m_atarget_hot[4]_i_3_n_0\,
O => \m_atarget_hot[4]_i_2_n_0\
);
\m_atarget_hot[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^q\(31),
I1 => \^q\(28),
I2 => \^q\(29),
O => \m_atarget_hot[4]_i_3_n_0\
);
\m_atarget_hot[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[5]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(5)
);
\m_atarget_hot[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => \m_atarget_hot[4]_i_2_n_0\,
I1 => \^q\(19),
I2 => \^q\(18),
I3 => \^q\(16),
I4 => \^q\(17),
O => \m_atarget_hot[5]_i_2_n_0\
);
\m_atarget_hot[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[6]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(6)
);
\m_atarget_hot[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \^q\(21),
I1 => \m_atarget_hot[11]_i_4_n_0\,
I2 => \m_atarget_hot[6]_i_3_n_0\,
I3 => \m_atarget_hot[6]_i_4_n_0\,
O => \m_atarget_hot[6]_i_2_n_0\
);
\m_atarget_hot[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^q\(23),
I1 => \^q\(20),
I2 => \^q\(25),
I3 => \^q\(22),
I4 => \^q\(24),
O => \m_atarget_hot[6]_i_3_n_0\
);
\m_atarget_hot[6]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(16),
I1 => \^q\(17),
I2 => \^q\(19),
I3 => \^q\(18),
O => \m_atarget_hot[6]_i_4_n_0\
);
\m_atarget_hot[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[7]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(7)
);
\m_atarget_hot[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => \m_atarget_hot[8]_i_2_n_0\,
I1 => \^q\(18),
I2 => \^q\(19),
I3 => \^q\(17),
I4 => \^q\(16),
O => \m_atarget_hot[7]_i_2_n_0\
);
\m_atarget_hot[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000020000000000"
)
port map (
I0 => \m_atarget_hot[8]_i_2_n_0\,
I1 => \^q\(19),
I2 => \^q\(18),
I3 => \^q\(16),
I4 => \^q\(17),
I5 => aa_grant_any,
O => D(8)
);
\m_atarget_hot[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \m_atarget_hot[11]_i_4_n_0\,
I1 => \m_atarget_hot[11]_i_3_n_0\,
O => \m_atarget_hot[8]_i_2_n_0\
);
\m_atarget_hot[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8AA0000"
)
port map (
I0 => \m_atarget_hot[9]_i_2_n_0\,
I1 => \m_atarget_hot[14]_i_4_n_0\,
I2 => \m_atarget_hot[14]_i_3_n_0\,
I3 => \m_atarget_hot[14]_i_2_n_0\,
I4 => aa_grant_any,
O => D(9)
);
\m_atarget_hot[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \m_atarget_hot[8]_i_2_n_0\,
I1 => \^q\(16),
I2 => \^q\(17),
I3 => \^q\(18),
I4 => \^q\(19),
O => \m_atarget_hot[9]_i_2_n_0\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[11]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(10),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(10)
);
\m_axi_arvalid[12]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(11),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(11)
);
\m_axi_arvalid[13]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(12),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(12)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(3)
);
\m_axi_arvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(4),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(4)
);
\m_axi_arvalid[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(5),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(5)
);
\m_axi_arvalid[6]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(6),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(6)
);
\m_axi_arvalid[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(7),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(7)
);
\m_axi_arvalid[8]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(8),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(8)
);
\m_axi_arvalid[9]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[14]\(9),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(9)
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[11]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(10),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(10)
);
\m_axi_awvalid[12]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(11),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(11)
);
\m_axi_awvalid[13]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(12),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(12)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(3),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(3)
);
\m_axi_awvalid[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(4),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(4)
);
\m_axi_awvalid[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(5),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(5)
);
\m_axi_awvalid[6]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(6),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(6)
);
\m_axi_awvalid[7]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(7),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(7)
);
\m_axi_awvalid[8]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(8),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(8)
);
\m_axi_awvalid[9]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[14]\(9),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(9)
);
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(0),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(0)
);
\m_axi_bready[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(10),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(10)
);
\m_axi_bready[12]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(11),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(11)
);
\m_axi_bready[13]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(12),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(12)
);
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(1),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(1)
);
\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(2),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(2)
);
\m_axi_bready[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(3),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(3)
);
\m_axi_bready[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(4),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(4)
);
\m_axi_bready[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(5),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(5)
);
\m_axi_bready[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(6),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(6)
);
\m_axi_bready[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(7),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(7)
);
\m_axi_bready[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(8),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(8)
);
\m_axi_bready[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(9),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(9)
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(0),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[11]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(10),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(10)
);
\m_axi_wvalid[12]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(11),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(11)
);
\m_axi_wvalid[13]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(12),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(12)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(1),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(2),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(3),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(3)
);
\m_axi_wvalid[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(4),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(4)
);
\m_axi_wvalid[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(5),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(5)
);
\m_axi_wvalid[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(6),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(6)
);
\m_axi_wvalid[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(7),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(7)
);
\m_axi_wvalid[8]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(8),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(8)
);
\m_axi_wvalid[9]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[14]\(9),
I1 => m_ready_d(1),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(9)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0080FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(0),
I4 => sr_rvalid,
O => E(0)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
O => \m_ready_d_reg[0]_2\
);
\m_ready_d[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \m_ready_d[0]_i_4_n_0\,
I1 => aresetn_d,
O => \m_ready_d_reg[0]\
);
\m_ready_d[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF0010"
)
port map (
I0 => \^gen_axilite.s_axi_rvalid_i_reg\,
I1 => \m_atarget_enc_reg[2]_6\,
I2 => \m_atarget_enc_reg[2]_7\,
I3 => \m_atarget_enc_reg[2]_8\,
I4 => m_ready_d_0(1),
I5 => m_valid_i_reg_0,
O => \m_ready_d[0]_i_4_n_0\
);
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555554555555555"
)
port map (
I0 => m_ready_d(2),
I1 => \m_atarget_enc_reg[3]_0\,
I2 => \m_atarget_enc_reg[2]_0\,
I3 => \m_atarget_enc_reg[2]_1\,
I4 => \^aa_grant_rnw\,
I5 => \^m_valid_i\,
O => \^m_ready_d_reg[2]\
);
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F2"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \^m_ready_d_reg[1]\,
I2 => m_ready_d(1),
I3 => \m_ready_d_reg[0]_3\,
I4 => \^m_ready_d_reg[2]\,
O => \m_ready_d_reg[2]_0\
);
m_valid_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAAAAAA"
)
port map (
I0 => sr_rvalid,
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_rready(0),
O => s_ready_i_reg
);
m_valid_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFABFFFFFFFFFFFF"
)
port map (
I0 => \m_atarget_enc_reg[3]_2\,
I1 => m_axi_rvalid(0),
I2 => \m_atarget_enc_reg[2]_5\,
I3 => m_ready_d_0(0),
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => m_valid_i_reg
);
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => aresetn_d,
I3 => s_ready_i,
O => \s_arvalid_reg[0]_i_1_n_0\
);
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_arvalid_reg[0]_i_1_n_0\,
Q => \s_arvalid_reg_reg_n_0_[0]\,
R => '0'
);
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000D00000"
)
port map (
I0 => s_axi_arvalid(0),
I1 => s_awvalid_reg,
I2 => s_axi_awvalid(0),
I3 => \s_arvalid_reg_reg_n_0_[0]\,
I4 => aresetn_d,
I5 => s_ready_i,
O => \s_awvalid_reg[0]_i_1_n_0\
);
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_awvalid_reg[0]_i_1_n_0\,
Q => s_awvalid_reg,
R => '0'
);
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_arready(0)
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_awready(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => aa_grant_any,
I1 => \^m_ready_d_reg[0]_0\,
O => s_axi_bvalid(0)
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAAAABABB"
)
port map (
I0 => \^m_ready_d_reg[0]_1\,
I1 => \m_atarget_enc_reg[0]_0\,
I2 => \m_atarget_enc_reg[2]_2\,
I3 => m_axi_bvalid(1),
I4 => \m_atarget_enc_reg[2]_3\,
I5 => \m_atarget_enc_reg[2]_4\,
O => \^m_ready_d_reg[0]_0\
);
\s_axi_bvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFABFFFF"
)
port map (
I0 => \m_atarget_enc_reg[3]_1\,
I1 => m_axi_bvalid(0),
I2 => \m_atarget_enc_reg[2]_5\,
I3 => m_ready_d(0),
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \^m_ready_d_reg[0]_1\
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_grant_any,
I1 => sr_rvalid,
O => s_axi_rvalid(0)
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => aa_grant_any,
I1 => \^m_ready_d_reg[1]\,
O => s_axi_wready(0)
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBFF8B00BBFF8BFF"
)
port map (
I0 => \s_axi_wready[0]_INST_0_i_2_n_0\,
I1 => m_atarget_enc(1),
I2 => \s_axi_wready[0]_INST_0_i_3_n_0\,
I3 => m_atarget_enc(0),
I4 => \s_axi_wready[0]_INST_0_i_4_n_0\,
I5 => \m_atarget_enc_reg[1]_0\,
O => \^m_ready_d_reg[1]\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFCC1DFF1D"
)
port map (
I0 => m_axi_wready(1),
I1 => m_atarget_enc(2),
I2 => m_axi_wready(3),
I3 => m_atarget_enc(3),
I4 => m_axi_wready(5),
I5 => \s_axi_wready[0]_INST_0_i_4_n_0\,
O => \s_axi_wready[0]_INST_0_i_2_n_0\
);
\s_axi_wready[0]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => m_axi_wready(6),
I1 => m_axi_wready(2),
I2 => m_atarget_enc(2),
I3 => m_axi_wready(4),
I4 => m_atarget_enc(3),
I5 => m_axi_wready(0),
O => \s_axi_wready[0]_INST_0_i_3_n_0\
);
\s_axi_wready[0]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => m_ready_d(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \s_axi_wready[0]_INST_0_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_1_axi_crossbar_v2_1_12_decerr_slave is
port (
mi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[2]\ : out STD_LOGIC;
\m_ready_d_reg[0]\ : out STD_LOGIC;
\gen_no_arbiter.m_grant_hot_i_reg[0]\ : out STD_LOGIC;
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
reset : in STD_LOGIC;
\gen_axilite.s_axi_awready_i_reg_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\m_atarget_enc_reg[3]\ : in STD_LOGIC;
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
\m_atarget_enc_reg[3]_0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[0]_0\ : in STD_LOGIC;
m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_enc_reg[2]\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_enc_reg[0]_1\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_0\ : in STD_LOGIC;
\m_atarget_enc_reg[3]_1\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_enc_reg[0]_2\ : in STD_LOGIC;
\m_atarget_enc_reg[2]_1\ : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[2]_2\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
aa_rready : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
\m_ready_d_reg[2]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_1_axi_crossbar_v2_1_12_decerr_slave : entity is "axi_crossbar_v2_1_12_decerr_slave";
end system_xbar_1_axi_crossbar_v2_1_12_decerr_slave;
architecture STRUCTURE of system_xbar_1_axi_crossbar_v2_1_12_decerr_slave is
signal \gen_axilite.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_rvalid_i_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_9_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_9_n_0\ : STD_LOGIC;
signal m_valid_i_i_10_n_0 : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_rvalid : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \s_axi_bvalid[0]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_7_n_0\ : STD_LOGIC;
begin
mi_bvalid(0) <= \^mi_bvalid\(0);
mi_wready(0) <= \^mi_wready\(0);
\gen_axilite.s_axi_arready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A2A282A2"
)
port map (
I0 => aresetn_d,
I1 => mi_rvalid(14),
I2 => mi_arready(14),
I3 => Q(0),
I4 => \m_ready_d_reg[1]_1\,
O => \gen_axilite.s_axi_arready_i_i_1_n_0\
);
\gen_axilite.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_arready_i_i_1_n_0\,
Q => mi_arready(14),
R => '0'
);
\gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFBF0040"
)
port map (
I0 => \^mi_bvalid\(0),
I1 => \gen_no_arbiter.grant_rnw_reg\,
I2 => Q(0),
I3 => \m_ready_d_reg[2]_0\,
I4 => \^mi_wready\(0),
O => \gen_axilite.s_axi_awready_i_i_1_n_0\
);
\gen_axilite.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_awready_i_i_1_n_0\,
Q => \^mi_wready\(0),
R => reset
);
\gen_axilite.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_awready_i_reg_0\,
Q => \^mi_bvalid\(0),
R => reset
);
\gen_axilite.s_axi_rvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF4400"
)
port map (
I0 => \m_ready_d_reg[1]_1\,
I1 => mi_arready(14),
I2 => aa_rready,
I3 => Q(0),
I4 => mi_rvalid(14),
O => \gen_axilite.s_axi_rvalid_i_i_1_n_0\
);
\gen_axilite.s_axi_rvalid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_rvalid_i_i_1_n_0\,
Q => mi_rvalid(14),
R => reset
);
\m_ready_d[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"4044FFFF40444044"
)
port map (
I0 => \m_atarget_enc_reg[2]_0\,
I1 => \m_atarget_enc_reg[0]\,
I2 => \m_atarget_enc_reg[3]_1\,
I3 => m_axi_arready(3),
I4 => \m_ready_d[1]_i_9_n_0\,
I5 => \m_atarget_enc_reg[0]_2\,
O => \m_ready_d_reg[0]_0\
);
\m_ready_d[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FD00"
)
port map (
I0 => m_axi_arready(0),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => \m_ready_d[1]_i_9_n_0\,
O => \m_ready_d_reg[1]\
);
\m_ready_d[1]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFC0A0C0"
)
port map (
I0 => mi_arready(14),
I1 => m_axi_arready(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => m_axi_arready(2),
O => \m_ready_d[1]_i_9_n_0\
);
\m_ready_d[2]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F700"
)
port map (
I0 => m_axi_bvalid(2),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => \s_axi_bvalid[0]_INST_0_i_11_n_0\,
O => \gen_no_arbiter.m_grant_hot_i_reg[0]\
);
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4044FFFF40444044"
)
port map (
I0 => \m_atarget_enc_reg[3]\,
I1 => \m_atarget_enc_reg[0]\,
I2 => \m_atarget_enc_reg[3]_0\,
I3 => m_axi_awready(0),
I4 => \m_ready_d[2]_i_9_n_0\,
I5 => \m_atarget_enc_reg[0]_0\,
O => \m_ready_d_reg[2]\
);
\m_ready_d[2]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0CA00CA"
)
port map (
I0 => m_axi_awready(1),
I1 => m_axi_awready(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => \^mi_wready\(0),
O => \m_ready_d[2]_i_9_n_0\
);
m_valid_i_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => mi_rvalid(14),
I1 => m_axi_rvalid(1),
I2 => m_atarget_enc(2),
I3 => m_axi_rvalid(2),
I4 => m_atarget_enc(3),
I5 => m_axi_rvalid(0),
O => m_valid_i_i_10_n_0
);
m_valid_i_reg_i_6: unisim.vcomponents.MUXF7
port map (
I0 => \m_atarget_enc_reg[2]_2\,
I1 => m_valid_i_i_10_n_0,
O => m_valid_i_reg,
S => m_atarget_enc(1)
);
\s_axi_bvalid[0]_INST_0_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FA0C0A0C"
)
port map (
I0 => m_axi_bvalid(3),
I1 => m_axi_bvalid(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => \^mi_bvalid\(0),
O => \s_axi_bvalid[0]_INST_0_i_11_n_0\
);
\s_axi_bvalid[0]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4044FFFF40444044"
)
port map (
I0 => \m_atarget_enc_reg[2]\,
I1 => \m_atarget_enc_reg[0]\,
I2 => \m_atarget_enc_reg[3]_0\,
I3 => m_axi_bvalid(0),
I4 => \s_axi_bvalid[0]_INST_0_i_11_n_0\,
I5 => \m_atarget_enc_reg[0]_1\,
O => \m_ready_d_reg[0]\
);
\s_axi_wready[0]_INST_0_i_5\: unisim.vcomponents.MUXF7
port map (
I0 => \m_atarget_enc_reg[2]_1\,
I1 => \s_axi_wready[0]_INST_0_i_7_n_0\,
O => \m_ready_d_reg[1]_0\,
S => m_atarget_enc(1)
);
\s_axi_wready[0]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^mi_wready\(0),
I1 => m_axi_wready(1),
I2 => m_atarget_enc(2),
I3 => m_axi_wready(2),
I4 => m_atarget_enc(3),
I5 => m_axi_wready(0),
O => \s_axi_wready[0]_INST_0_i_7_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_1_axi_crossbar_v2_1_12_splitter is
port (
\gen_no_arbiter.m_grant_hot_i_reg[0]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[2]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]_1\ : out STD_LOGIC;
\m_ready_d_reg[0]_2\ : out STD_LOGIC;
\m_ready_d_reg[2]_1\ : out STD_LOGIC;
\m_ready_d_reg[2]_2\ : out STD_LOGIC;
\m_ready_d_reg[2]_3\ : out STD_LOGIC;
\m_ready_d_reg[0]_3\ : out STD_LOGIC;
\m_ready_d_reg[2]_4\ : out STD_LOGIC;
\m_ready_d_reg[2]_5\ : out STD_LOGIC;
\m_ready_d_reg[0]_4\ : out STD_LOGIC;
\m_ready_d_reg[0]_5\ : out STD_LOGIC;
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]_6\ : in STD_LOGIC;
\m_atarget_enc_reg[2]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 10 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 10 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[2]_6\ : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
\m_ready_d_reg[0]_7\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_1_axi_crossbar_v2_1_12_splitter : entity is "axi_crossbar_v2_1_12_splitter";
end system_xbar_1_axi_crossbar_v2_1_12_splitter;
architecture STRUCTURE of system_xbar_1_axi_crossbar_v2_1_12_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_11_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_13_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_15_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[0]_1\ : STD_LOGIC;
signal \^m_ready_d_reg[2]_2\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_ready_d[2]_i_10\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_12\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_8\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_12\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_4\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_9\ : label is "soft_lutpair63";
begin
m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
\m_ready_d_reg[0]_0\ <= \^m_ready_d_reg[0]_0\;
\m_ready_d_reg[0]_1\ <= \^m_ready_d_reg[0]_1\;
\m_ready_d_reg[2]_2\ <= \^m_ready_d_reg[2]_2\;
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000BA00"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \m_ready_d_reg[0]_7\,
I2 => s_axi_bready(0),
I3 => aresetn_d,
I4 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F200"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \m_atarget_enc_reg[1]\,
I2 => \^m_ready_d\(1),
I3 => aresetn_d,
I4 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \m_ready_d_reg[2]_6\,
I1 => aresetn_d,
I2 => \m_ready_d_reg[1]_1\,
O => \m_ready_d[2]_i_1_n_0\
);
\m_ready_d[2]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"40444444"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_axi_awready(4),
O => \m_ready_d_reg[2]_3\
);
\m_ready_d[2]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0AC00AC"
)
port map (
I0 => m_axi_awready(6),
I1 => m_axi_awready(0),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_axi_awready(9),
O => \m_ready_d[2]_i_11_n_0\
);
\m_ready_d[2]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
O => \^m_ready_d_reg[2]_2\
);
\m_ready_d[2]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000011011111"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_axi_bvalid(6),
I5 => \^m_ready_d_reg[0]_0\,
O => \m_ready_d[2]_i_13_n_0\
);
\m_ready_d[2]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FD00"
)
port map (
I0 => m_axi_bvalid(1),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => \^m_ready_d_reg[0]_1\,
O => \m_ready_d[2]_i_15_n_0\
);
\m_ready_d[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF08"
)
port map (
I0 => m_axi_awready(2),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => \m_ready_d[2]_i_11_n_0\,
O => \m_ready_d_reg[2]_4\
);
\m_ready_d[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF33550F"
)
port map (
I0 => m_axi_awready(5),
I1 => m_axi_awready(8),
I2 => m_axi_awready(1),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(3),
I5 => \^m_ready_d_reg[2]_2\,
O => \m_ready_d_reg[2]_1\
);
\m_ready_d[2]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555455555555"
)
port map (
I0 => \^m_ready_d\(0),
I1 => \m_ready_d_reg[0]_6\,
I2 => \m_ready_d[2]_i_13_n_0\,
I3 => \m_atarget_enc_reg[2]\,
I4 => \m_ready_d[2]_i_15_n_0\,
I5 => s_axi_bready(0),
O => \gen_no_arbiter.m_grant_hot_i_reg[0]\
);
\m_ready_d[2]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFC0A0C0"
)
port map (
I0 => m_axi_awready(10),
I1 => m_axi_awready(7),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_axi_awready(3),
O => \m_ready_d_reg[2]_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[2]_i_1_n_0\,
Q => \^m_ready_d\(2),
R => '0'
);
\s_axi_bvalid[0]_INST_0_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"40444444"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_axi_bvalid(4),
O => \m_ready_d_reg[0]_3\
);
\s_axi_bvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
O => \m_ready_d_reg[0]_5\
);
\s_axi_bvalid[0]_INST_0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
O => \m_ready_d_reg[0]_2\
);
\s_axi_bvalid[0]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FCA00C"
)
port map (
I0 => m_axi_bvalid(9),
I1 => m_axi_bvalid(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => m_axi_bvalid(2),
O => \^m_ready_d_reg[0]_0\
);
\s_axi_bvalid[0]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0C000000000000"
)
port map (
I0 => m_axi_bvalid(5),
I1 => m_atarget_enc(3),
I2 => m_axi_bvalid(8),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(0),
I5 => m_atarget_enc(1),
O => \m_ready_d_reg[0]_4\
);
\s_axi_bvalid[0]_INST_0_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFC0A0C0"
)
port map (
I0 => m_axi_bvalid(10),
I1 => m_axi_bvalid(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => m_axi_bvalid(7),
O => \^m_ready_d_reg[0]_1\
);
\s_axi_bvalid[0]_INST_0_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
O => \m_ready_d_reg[2]_5\
);
\s_axi_wready[0]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => m_axi_wready(3),
I1 => m_axi_wready(1),
I2 => m_atarget_enc(2),
I3 => m_axi_wready(2),
I4 => m_atarget_enc(3),
I5 => m_axi_wready(0),
O => \m_ready_d_reg[1]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_1_axi_crossbar_v2_1_12_splitter__parameterized0\ is
port (
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
\m_ready_d_reg[1]_1\ : out STD_LOGIC;
\m_ready_d_reg[1]_2\ : out STD_LOGIC;
\m_ready_d_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[0]_1\ : out STD_LOGIC;
\m_atarget_enc_reg[2]\ : in STD_LOGIC;
\m_ready_d_reg[1]_3\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
sr_rvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
aresetn_d_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_1_axi_crossbar_v2_1_12_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_12_splitter";
end \system_xbar_1_axi_crossbar_v2_1_12_splitter__parameterized0\;
architecture STRUCTURE of \system_xbar_1_axi_crossbar_v2_1_12_splitter__parameterized0\ is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 to 1 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_10_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_1\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_2\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_ready_d[0]_i_6\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_8\ : label is "soft_lutpair61";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
\m_ready_d_reg[1]_1\ <= \^m_ready_d_reg[1]_1\;
\m_ready_d_reg[1]_2\ <= \^m_ready_d_reg[1]_2\;
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF0080"
)
port map (
I0 => sr_rvalid,
I1 => Q(0),
I2 => s_axi_rready(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => \^m_ready_d\(0),
I5 => aresetn_d_reg,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[0]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => m_atarget_enc(3),
I1 => m_atarget_enc(2),
O => \m_ready_d_reg[0]_1\
);
\m_ready_d[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"44404444"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_axi_arready(2),
O => \m_ready_d_reg[0]_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(1),
I2 => m_valid_i_reg,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[1]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FA0C0A0C"
)
port map (
I0 => m_axi_arready(7),
I1 => m_axi_arready(0),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => m_axi_arready(10),
O => \m_ready_d[1]_i_10_n_0\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAABAA"
)
port map (
I0 => \^m_ready_d\(1),
I1 => \m_ready_d[1]_i_4_n_0\,
I2 => \m_atarget_enc_reg[2]\,
I3 => \^m_ready_d_reg[1]_0\,
I4 => \^m_ready_d_reg[1]_1\,
I5 => \m_ready_d_reg[1]_3\,
O => m_ready_d0(1)
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F00"
)
port map (
I0 => m_axi_arready(11),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => \^m_ready_d_reg[1]_2\,
O => \m_ready_d[1]_i_4_n_0\
);
\m_ready_d[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF08"
)
port map (
I0 => m_axi_arready(4),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => \m_ready_d[1]_i_10_n_0\,
O => \^m_ready_d_reg[1]_0\
);
\m_ready_d[1]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FF33550F"
)
port map (
I0 => m_axi_arready(6),
I1 => m_axi_arready(9),
I2 => m_axi_arready(3),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(3),
I5 => \m_atarget_enc_reg[0]\,
O => \^m_ready_d_reg[1]_1\
);
\m_ready_d[1]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"0ACF0AC0"
)
port map (
I0 => m_axi_arready(8),
I1 => m_axi_arready(5),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => m_axi_arready(1),
O => \^m_ready_d_reg[1]_2\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_1_axi_register_slice_v2_1_11_axic_register_slice is
port (
sr_rvalid : out STD_LOGIC;
aa_rready : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
\m_payload_i_reg[1]_0\ : out STD_LOGIC;
\m_payload_i_reg[1]_1\ : out STD_LOGIC;
\m_payload_i_reg[1]_2\ : out STD_LOGIC;
\m_payload_i_reg[2]_1\ : out STD_LOGIC;
\m_payload_i_reg[2]_2\ : out STD_LOGIC;
\skid_buffer_reg[3]_0\ : out STD_LOGIC;
\skid_buffer_reg[3]_1\ : out STD_LOGIC;
\skid_buffer_reg[3]_2\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_1 : out STD_LOGIC;
m_axi_rready : out STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
m_valid_i_reg_2 : in STD_LOGIC;
\m_ready_d_reg[0]\ : in STD_LOGIC;
m_atarget_enc : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_enc_reg[1]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 447 downto 0 );
\m_atarget_enc_reg[1]_rep\ : in STD_LOGIC;
\m_atarget_enc_reg[0]_rep\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_atarget_hot_reg[13]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
reset : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_1_axi_register_slice_v2_1_11_axic_register_slice : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end system_xbar_1_axi_register_slice_v2_1_11_axic_register_slice;
architecture STRUCTURE of system_xbar_1_axi_register_slice_v2_1_11_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^aa_rready\ : STD_LOGIC;
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \aresetn_d_reg_n_0_[1]\ : STD_LOGIC;
signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_5_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_6_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_7_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_8_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_10_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_3_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_4_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_5_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_6_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_7_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_8_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_9_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[1]_0\ : STD_LOGIC;
signal \^m_payload_i_reg[1]_1\ : STD_LOGIC;
signal \^m_payload_i_reg[1]_2\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_1\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_2\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal m_valid_i_i_4_n_0 : STD_LOGIC;
signal m_valid_i_i_7_n_0 : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \skid_buffer[0]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[10]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_8_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_7_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_2_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_3_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_4_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_5_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_6_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_7_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[3]_0\ : STD_LOGIC;
signal \^skid_buffer_reg[3]_1\ : STD_LOGIC;
signal \^skid_buffer_reg[3]_2\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \^sr_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_rready[11]_INST_0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_axi_rready[12]_INST_0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_axi_rready[13]_INST_0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_rready[3]_INST_0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_axi_rready[4]_INST_0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_axi_rready[5]_INST_0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_axi_rready[6]_INST_0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_axi_rready[7]_INST_0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_axi_rready[8]_INST_0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_axi_rready[9]_INST_0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_8\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_9\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0_i_5\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0_i_6\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0_i_10\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0_i_2\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0_i_6\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair51";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
aa_rready <= \^aa_rready\;
\m_payload_i_reg[1]_0\ <= \^m_payload_i_reg[1]_0\;
\m_payload_i_reg[1]_1\ <= \^m_payload_i_reg[1]_1\;
\m_payload_i_reg[1]_2\ <= \^m_payload_i_reg[1]_2\;
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
\m_payload_i_reg[2]_1\ <= \^m_payload_i_reg[2]_1\;
\m_payload_i_reg[2]_2\ <= \^m_payload_i_reg[2]_2\;
\skid_buffer_reg[3]_0\ <= \^skid_buffer_reg[3]_0\;
\skid_buffer_reg[3]_1\ <= \^skid_buffer_reg[3]_1\;
\skid_buffer_reg[3]_2\ <= \^skid_buffer_reg[3]_2\;
sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => '1',
Q => \aresetn_d_reg_n_0_[0]\,
R => reset
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg_n_0_[0]\,
Q => \aresetn_d_reg_n_0_[1]\,
R => reset
);
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(0),
O => m_axi_rready(0)
);
\m_axi_rready[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(10),
O => m_axi_rready(10)
);
\m_axi_rready[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(11),
O => m_axi_rready(11)
);
\m_axi_rready[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(12),
O => m_axi_rready(12)
);
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(1),
O => m_axi_rready(1)
);
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(2),
O => m_axi_rready(2)
);
\m_axi_rready[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(3),
O => m_axi_rready(3)
);
\m_axi_rready[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(4),
O => m_axi_rready(4)
);
\m_axi_rready[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(5),
O => m_axi_rready(5)
);
\m_axi_rready[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(6),
O => m_axi_rready(6)
);
\m_axi_rready[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(7),
O => m_axi_rready(7)
);
\m_axi_rready[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(8),
O => m_axi_rready(8)
);
\m_axi_rready[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[13]\(9),
O => m_axi_rready(9)
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF7FFF0000"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
I4 => \^aa_rready\,
I5 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[10]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[11]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[12]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[13]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[14]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[15]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[16]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[17]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[18]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[19]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEE0EE"
)
port map (
I0 => \skid_buffer_reg_n_0_[1]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[1]_i_2_n_0\,
I3 => \m_payload_i[1]_i_3_n_0\,
I4 => \m_payload_i[1]_i_4_n_0\,
I5 => \m_payload_i[1]_i_5_n_0\,
O => skid_buffer(1)
);
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEEFFFFEFEEEFEE"
)
port map (
I0 => \m_payload_i[1]_i_6_n_0\,
I1 => \m_payload_i[1]_i_7_n_0\,
I2 => \^m_payload_i_reg[1]_0\,
I3 => m_axi_rresp(18),
I4 => \^m_payload_i_reg[1]_1\,
I5 => m_axi_rresp(12),
O => \m_payload_i[1]_i_2_n_0\
);
\m_payload_i[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"A2A200A2"
)
port map (
I0 => \m_payload_i[1]_i_8_n_0\,
I1 => m_axi_rresp(6),
I2 => \^m_payload_i_reg[1]_2\,
I3 => m_axi_rresp(10),
I4 => \m_payload_i[2]_i_9_n_0\,
O => \m_payload_i[1]_i_3_n_0\
);
\m_payload_i[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0083000000800000"
)
port map (
I0 => m_axi_rresp(26),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rresp(2),
O => \m_payload_i[1]_i_4_n_0\
);
\m_payload_i[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0023000000200000"
)
port map (
I0 => m_axi_rresp(20),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rresp(4),
O => \m_payload_i[1]_i_5_n_0\
);
\m_payload_i[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF44F4FFFFFFFF"
)
port map (
I0 => \^skid_buffer_reg[3]_1\,
I1 => m_axi_rresp(24),
I2 => m_axi_rresp(8),
I3 => \^m_payload_i_reg[2]_0\,
I4 => \^m_payload_i_reg[2]_2\,
I5 => \^aa_rready\,
O => \m_payload_i[1]_i_6_n_0\
);
\m_payload_i[1]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C00000020000000"
)
port map (
I0 => m_axi_rresp(22),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rresp(14),
O => \m_payload_i[1]_i_7_n_0\
);
\m_payload_i[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF1FFFFFFFD"
)
port map (
I0 => m_axi_rresp(0),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rresp(16),
O => \m_payload_i[1]_i_8_n_0\
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[20]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[21]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[22]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[23]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[24]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[25]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[26]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[27]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[28]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[29]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEE0EE"
)
port map (
I0 => \skid_buffer_reg_n_0_[2]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[2]_i_2_n_0\,
I3 => \m_payload_i[2]_i_3_n_0\,
I4 => \m_payload_i[2]_i_4_n_0\,
I5 => \m_payload_i[2]_i_5_n_0\,
O => skid_buffer(2)
);
\m_payload_i[2]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008300000080"
)
port map (
I0 => m_axi_rresp(25),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rresp(1),
O => \m_payload_i[2]_i_10_n_0\
);
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEEFFFFEFEEEFEE"
)
port map (
I0 => \m_payload_i[2]_i_6_n_0\,
I1 => \m_payload_i[2]_i_7_n_0\,
I2 => \m_payload_i[2]_i_8_n_0\,
I3 => m_axi_rresp(21),
I4 => \^m_payload_i_reg[2]_0\,
I5 => m_axi_rresp(9),
O => \m_payload_i[2]_i_2_n_0\
);
\m_payload_i[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000D0DD"
)
port map (
I0 => m_axi_rresp(7),
I1 => \^m_payload_i_reg[1]_2\,
I2 => \m_payload_i[2]_i_9_n_0\,
I3 => m_axi_rresp(11),
I4 => \m_payload_i[2]_i_10_n_0\,
O => \m_payload_i[2]_i_3_n_0\
);
\m_payload_i[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0003080000000800"
)
port map (
I0 => m_axi_rresp(13),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rresp(3),
O => \m_payload_i[2]_i_4_n_0\
);
\m_payload_i[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2003000020000000"
)
port map (
I0 => m_axi_rresp(23),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rresp(5),
O => \m_payload_i[2]_i_5_n_0\
);
\m_payload_i[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4FFF4FFFFFFF4FF"
)
port map (
I0 => \^m_payload_i_reg[2]_1\,
I1 => m_axi_rresp(17),
I2 => \^m_payload_i_reg[2]_2\,
I3 => \^aa_rready\,
I4 => m_axi_rresp(27),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \m_payload_i[2]_i_6_n_0\
);
\m_payload_i[2]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C20000000200000"
)
port map (
I0 => m_axi_rresp(19),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rresp(15),
O => \m_payload_i[2]_i_7_n_0\
);
\m_payload_i[2]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FDFF"
)
port map (
I0 => m_atarget_enc(3),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
O => \m_payload_i[2]_i_8_n_0\
);
\m_payload_i[2]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FDFF"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \m_payload_i[2]_i_9_n_0\
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[30]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[31]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[32]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[33]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[34]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[3]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[4]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[5]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[6]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[7]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[8]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[9]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => \^sr_rvalid\,
I1 => \^q\(0),
I2 => s_axi_rready(0),
I3 => aa_grant_rnw,
I4 => m_valid_i,
I5 => m_ready_d(0),
O => \m_ready_d_reg[1]\
);
m_valid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => \aresetn_d_reg_n_0_[1]\,
I1 => m_valid_i_i_2_n_0,
I2 => m_valid_i_reg_2,
O => m_valid_i_i_1_n_0
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"A8A8A8AA"
)
port map (
I0 => \^aa_rready\,
I1 => m_valid_i_i_4_n_0,
I2 => \m_ready_d_reg[0]\,
I3 => m_atarget_enc(0),
I4 => \m_atarget_enc_reg[1]\,
O => m_valid_i_i_2_n_0
);
m_valid_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F00"
)
port map (
I0 => m_axi_rvalid(9),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_valid_i_i_7_n_0,
O => m_valid_i_i_4_n_0
);
m_valid_i_i_7: unisim.vcomponents.LUT5
generic map(
INIT => X"0AFC0A0C"
)
port map (
I0 => m_axi_rvalid(6),
I1 => m_axi_rvalid(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => m_axi_rvalid(3),
O => m_valid_i_i_7_n_0
);
m_valid_i_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"DD0C000000000000"
)
port map (
I0 => m_axi_rvalid(4),
I1 => m_atarget_enc(3),
I2 => m_axi_rvalid(7),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(0),
I5 => m_atarget_enc(1),
O => m_valid_i_reg_0
);
m_valid_i_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => m_axi_rvalid(8),
I1 => m_axi_rvalid(2),
I2 => m_atarget_enc(2),
I3 => m_axi_rvalid(5),
I4 => m_atarget_enc(3),
I5 => m_axi_rvalid(0),
O => m_valid_i_reg_1
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^sr_rvalid\,
R => '0'
);
\s_axi_bresp[0]_INST_0_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \^skid_buffer_reg[3]_0\
);
\s_axi_bresp[0]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \^m_payload_i_reg[2]_0\
);
\s_axi_bresp[0]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FDFF"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
O => \^m_payload_i_reg[1]_1\
);
\s_axi_bresp[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FDFF"
)
port map (
I0 => m_atarget_enc(3),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \^m_payload_i_reg[1]_0\
);
\s_axi_bresp[1]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => m_atarget_enc(3),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \^m_payload_i_reg[2]_1\
);
\s_axi_bresp[1]_INST_0_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \^skid_buffer_reg[3]_1\
);
\s_axi_bresp[1]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => m_atarget_enc(0),
I1 => m_atarget_enc(1),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
O => \^m_payload_i_reg[2]_2\
);
\s_axi_bresp[1]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \^m_payload_i_reg[1]_2\
);
\s_axi_bvalid[0]_INST_0_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => m_atarget_enc(3),
I1 => m_atarget_enc(2),
O => \^skid_buffer_reg[3]_2\
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => m_valid_i_reg_2,
I2 => m_valid_i_i_2_n_0,
O => s_ready_i_i_1_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^aa_rready\,
R => '0'
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \skid_buffer[0]_i_1_n_0\
);
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[10]_i_2_n_0\,
I1 => \skid_buffer[10]_i_3_n_0\,
I2 => \skid_buffer[10]_i_4_n_0\,
I3 => \skid_buffer[10]_i_5_n_0\,
I4 => \skid_buffer[10]_i_6_n_0\,
I5 => \skid_buffer[10]_i_7_n_0\,
O => \skid_buffer[10]_i_1_n_0\
);
\skid_buffer[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(327),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(359),
O => \skid_buffer[10]_i_2_n_0\
);
\skid_buffer[10]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(263),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(295),
O => \skid_buffer[10]_i_3_n_0\
);
\skid_buffer[10]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(7),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(391),
I4 => m_axi_rdata(423),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[10]_i_4_n_0\
);
\skid_buffer[10]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(71),
I1 => m_axi_rdata(103),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(39),
O => \skid_buffer[10]_i_5_n_0\
);
\skid_buffer[10]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(199),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(231),
O => \skid_buffer[10]_i_6_n_0\
);
\skid_buffer[10]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(135),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(167),
O => \skid_buffer[10]_i_7_n_0\
);
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[11]_i_2_n_0\,
I1 => \skid_buffer[11]_i_3_n_0\,
I2 => \skid_buffer[11]_i_4_n_0\,
I3 => \skid_buffer[11]_i_5_n_0\,
I4 => \skid_buffer[11]_i_6_n_0\,
I5 => \skid_buffer[11]_i_7_n_0\,
O => \skid_buffer[11]_i_1_n_0\
);
\skid_buffer[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(328),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(360),
O => \skid_buffer[11]_i_2_n_0\
);
\skid_buffer[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(296),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(264),
O => \skid_buffer[11]_i_3_n_0\
);
\skid_buffer[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(8),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(392),
I4 => m_axi_rdata(424),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[11]_i_4_n_0\
);
\skid_buffer[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(72),
I1 => m_axi_rdata(104),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(40),
O => \skid_buffer[11]_i_5_n_0\
);
\skid_buffer[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(232),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(200),
O => \skid_buffer[11]_i_6_n_0\
);
\skid_buffer[11]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(168),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(136),
O => \skid_buffer[11]_i_7_n_0\
);
\skid_buffer[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => \skid_buffer[12]_i_2_n_0\,
I1 => \skid_buffer[12]_i_3_n_0\,
I2 => \skid_buffer[12]_i_4_n_0\,
I3 => \skid_buffer[12]_i_5_n_0\,
I4 => \skid_buffer[12]_i_6_n_0\,
I5 => \skid_buffer[12]_i_7_n_0\,
O => \skid_buffer[12]_i_1_n_0\
);
\skid_buffer[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF3FFF7FFFFFFF7"
)
port map (
I0 => m_axi_rdata(265),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(297),
O => \skid_buffer[12]_i_2_n_0\
);
\skid_buffer[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7F3FFFFF7FFFFFF"
)
port map (
I0 => m_axi_rdata(361),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(329),
O => \skid_buffer[12]_i_3_n_0\
);
\skid_buffer[12]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(9),
I2 => m_axi_rdata(393),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(425),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[12]_i_4_n_0\
);
\skid_buffer[12]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(73),
I1 => m_axi_rdata(41),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(105),
O => \skid_buffer[12]_i_5_n_0\
);
\skid_buffer[12]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(201),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(233),
O => \skid_buffer[12]_i_6_n_0\
);
\skid_buffer[12]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(169),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(137),
O => \skid_buffer[12]_i_7_n_0\
);
\skid_buffer[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[13]_i_2_n_0\,
I1 => \skid_buffer[13]_i_3_n_0\,
I2 => \skid_buffer[13]_i_4_n_0\,
I3 => \skid_buffer[13]_i_5_n_0\,
I4 => \skid_buffer[13]_i_6_n_0\,
I5 => \skid_buffer[13]_i_7_n_0\,
O => \skid_buffer[13]_i_1_n_0\
);
\skid_buffer[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(330),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(362),
O => \skid_buffer[13]_i_2_n_0\
);
\skid_buffer[13]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(266),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(298),
O => \skid_buffer[13]_i_3_n_0\
);
\skid_buffer[13]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(10),
I2 => \skid_buffer[34]_i_8_n_0\,
I3 => m_axi_rdata(426),
I4 => m_axi_rdata(394),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[13]_i_4_n_0\
);
\skid_buffer[13]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(74),
I1 => m_axi_rdata(42),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(106),
O => \skid_buffer[13]_i_5_n_0\
);
\skid_buffer[13]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(202),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(234),
O => \skid_buffer[13]_i_6_n_0\
);
\skid_buffer[13]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(138),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(170),
O => \skid_buffer[13]_i_7_n_0\
);
\skid_buffer[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFF"
)
port map (
I0 => \skid_buffer[14]_i_2_n_0\,
I1 => \skid_buffer[14]_i_3_n_0\,
I2 => \skid_buffer[14]_i_4_n_0\,
I3 => \skid_buffer[14]_i_5_n_0\,
I4 => \skid_buffer[14]_i_6_n_0\,
I5 => \skid_buffer[14]_i_7_n_0\,
O => \skid_buffer[14]_i_1_n_0\
);
\skid_buffer[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(363),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(331),
O => \skid_buffer[14]_i_2_n_0\
);
\skid_buffer[14]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(267),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(299),
O => \skid_buffer[14]_i_3_n_0\
);
\skid_buffer[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(11),
I2 => m_axi_rdata(395),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(427),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[14]_i_4_n_0\
);
\skid_buffer[14]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(75),
I1 => m_axi_rdata(43),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(107),
O => \skid_buffer[14]_i_5_n_0\
);
\skid_buffer[14]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F3FFF7FFFFFFF7FF"
)
port map (
I0 => m_axi_rdata(203),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(235),
O => \skid_buffer[14]_i_6_n_0\
);
\skid_buffer[14]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF3FFF7FFFFFFF7"
)
port map (
I0 => m_axi_rdata(139),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(171),
O => \skid_buffer[14]_i_7_n_0\
);
\skid_buffer[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[15]_i_2_n_0\,
I1 => \skid_buffer[15]_i_3_n_0\,
I2 => \skid_buffer[15]_i_4_n_0\,
I3 => \skid_buffer[15]_i_5_n_0\,
I4 => \skid_buffer[15]_i_6_n_0\,
I5 => \skid_buffer[15]_i_7_n_0\,
O => \skid_buffer[15]_i_1_n_0\
);
\skid_buffer[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(332),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(364),
O => \skid_buffer[15]_i_2_n_0\
);
\skid_buffer[15]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(268),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(300),
O => \skid_buffer[15]_i_3_n_0\
);
\skid_buffer[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(12),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(396),
I4 => m_axi_rdata(428),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[15]_i_4_n_0\
);
\skid_buffer[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(76),
I1 => m_axi_rdata(108),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(44),
O => \skid_buffer[15]_i_5_n_0\
);
\skid_buffer[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(204),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(236),
O => \skid_buffer[15]_i_6_n_0\
);
\skid_buffer[15]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(140),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(172),
O => \skid_buffer[15]_i_7_n_0\
);
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[16]_i_2_n_0\,
I1 => \skid_buffer[16]_i_3_n_0\,
I2 => \skid_buffer[16]_i_4_n_0\,
I3 => \skid_buffer[16]_i_5_n_0\,
I4 => \skid_buffer[16]_i_6_n_0\,
I5 => \skid_buffer[16]_i_7_n_0\,
O => \skid_buffer[16]_i_1_n_0\
);
\skid_buffer[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(365),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(333),
O => \skid_buffer[16]_i_2_n_0\
);
\skid_buffer[16]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(301),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(269),
O => \skid_buffer[16]_i_3_n_0\
);
\skid_buffer[16]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(13),
I2 => m_axi_rdata(397),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(429),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[16]_i_4_n_0\
);
\skid_buffer[16]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(77),
I1 => m_axi_rdata(45),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(109),
O => \skid_buffer[16]_i_5_n_0\
);
\skid_buffer[16]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0000000A00000"
)
port map (
I0 => m_axi_rdata(205),
I1 => m_axi_rdata(237),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => \m_atarget_enc_reg[0]_rep\,
O => \skid_buffer[16]_i_6_n_0\
);
\skid_buffer[16]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(173),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(141),
O => \skid_buffer[16]_i_7_n_0\
);
\skid_buffer[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[17]_i_2_n_0\,
I1 => \skid_buffer[17]_i_3_n_0\,
I2 => \skid_buffer[17]_i_4_n_0\,
I3 => \skid_buffer[17]_i_5_n_0\,
I4 => \skid_buffer[17]_i_6_n_0\,
I5 => \skid_buffer[17]_i_7_n_0\,
O => \skid_buffer[17]_i_1_n_0\
);
\skid_buffer[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(334),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(366),
O => \skid_buffer[17]_i_2_n_0\
);
\skid_buffer[17]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(270),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(302),
O => \skid_buffer[17]_i_3_n_0\
);
\skid_buffer[17]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(14),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(398),
I4 => m_axi_rdata(430),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[17]_i_4_n_0\
);
\skid_buffer[17]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(78),
I1 => m_axi_rdata(46),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(110),
O => \skid_buffer[17]_i_5_n_0\
);
\skid_buffer[17]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(206),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(238),
O => \skid_buffer[17]_i_6_n_0\
);
\skid_buffer[17]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(142),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(174),
O => \skid_buffer[17]_i_7_n_0\
);
\skid_buffer[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[18]_i_2_n_0\,
I1 => \skid_buffer[18]_i_3_n_0\,
I2 => \skid_buffer[18]_i_4_n_0\,
I3 => \skid_buffer[18]_i_5_n_0\,
I4 => \skid_buffer[18]_i_6_n_0\,
I5 => \skid_buffer[18]_i_7_n_0\,
O => \skid_buffer[18]_i_1_n_0\
);
\skid_buffer[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(367),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(335),
O => \skid_buffer[18]_i_2_n_0\
);
\skid_buffer[18]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(271),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(303),
O => \skid_buffer[18]_i_3_n_0\
);
\skid_buffer[18]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^skid_buffer_reg[3]_0\,
I2 => m_axi_rdata(431),
I3 => \skid_buffer[34]_i_8_n_0\,
I4 => m_axi_rdata(399),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[18]_i_4_n_0\
);
\skid_buffer[18]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(79),
I1 => m_axi_rdata(47),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(111),
O => \skid_buffer[18]_i_5_n_0\
);
\skid_buffer[18]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(239),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(207),
O => \skid_buffer[18]_i_6_n_0\
);
\skid_buffer[18]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(143),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(175),
O => \skid_buffer[18]_i_7_n_0\
);
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[19]_i_2_n_0\,
I1 => \skid_buffer[19]_i_3_n_0\,
I2 => \skid_buffer[19]_i_4_n_0\,
I3 => \skid_buffer[19]_i_5_n_0\,
I4 => \skid_buffer[19]_i_6_n_0\,
I5 => \skid_buffer[19]_i_7_n_0\,
O => \skid_buffer[19]_i_1_n_0\
);
\skid_buffer[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(336),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(368),
O => \skid_buffer[19]_i_2_n_0\
);
\skid_buffer[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(272),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(304),
O => \skid_buffer[19]_i_3_n_0\
);
\skid_buffer[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(16),
I2 => \skid_buffer[34]_i_8_n_0\,
I3 => m_axi_rdata(432),
I4 => m_axi_rdata(400),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[19]_i_4_n_0\
);
\skid_buffer[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(80),
I1 => m_axi_rdata(48),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(112),
O => \skid_buffer[19]_i_5_n_0\
);
\skid_buffer[19]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(208),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(240),
O => \skid_buffer[19]_i_6_n_0\
);
\skid_buffer[19]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(144),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(176),
O => \skid_buffer[19]_i_7_n_0\
);
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[20]_i_2_n_0\,
I1 => \skid_buffer[20]_i_3_n_0\,
I2 => \skid_buffer[20]_i_4_n_0\,
I3 => \skid_buffer[20]_i_5_n_0\,
I4 => \skid_buffer[20]_i_6_n_0\,
I5 => \skid_buffer[20]_i_7_n_0\,
O => \skid_buffer[20]_i_1_n_0\
);
\skid_buffer[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(369),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(337),
O => \skid_buffer[20]_i_2_n_0\
);
\skid_buffer[20]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(273),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(305),
O => \skid_buffer[20]_i_3_n_0\
);
\skid_buffer[20]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^skid_buffer_reg[3]_0\,
I2 => m_axi_rdata(433),
I3 => \skid_buffer[34]_i_8_n_0\,
I4 => m_axi_rdata(401),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[20]_i_4_n_0\
);
\skid_buffer[20]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(81),
I1 => m_axi_rdata(49),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(113),
O => \skid_buffer[20]_i_5_n_0\
);
\skid_buffer[20]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(209),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(241),
O => \skid_buffer[20]_i_6_n_0\
);
\skid_buffer[20]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(145),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(177),
O => \skid_buffer[20]_i_7_n_0\
);
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[21]_i_2_n_0\,
I1 => \skid_buffer[21]_i_3_n_0\,
I2 => \skid_buffer[21]_i_4_n_0\,
I3 => \skid_buffer[21]_i_5_n_0\,
I4 => \skid_buffer[21]_i_6_n_0\,
I5 => \skid_buffer[21]_i_7_n_0\,
O => \skid_buffer[21]_i_1_n_0\
);
\skid_buffer[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(370),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(338),
O => \skid_buffer[21]_i_2_n_0\
);
\skid_buffer[21]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000C0000000A0"
)
port map (
I0 => m_axi_rdata(274),
I1 => m_axi_rdata(306),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => \m_atarget_enc_reg[0]_rep\,
O => \skid_buffer[21]_i_3_n_0\
);
\skid_buffer[21]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(18),
I2 => m_axi_rdata(402),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(434),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[21]_i_4_n_0\
);
\skid_buffer[21]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(82),
I1 => m_axi_rdata(50),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(114),
O => \skid_buffer[21]_i_5_n_0\
);
\skid_buffer[21]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(242),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(210),
O => \skid_buffer[21]_i_6_n_0\
);
\skid_buffer[21]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(146),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(178),
O => \skid_buffer[21]_i_7_n_0\
);
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[22]_i_2_n_0\,
I1 => \skid_buffer[22]_i_3_n_0\,
I2 => \skid_buffer[22]_i_4_n_0\,
I3 => \skid_buffer[22]_i_5_n_0\,
I4 => \skid_buffer[22]_i_6_n_0\,
I5 => \skid_buffer[22]_i_7_n_0\,
O => \skid_buffer[22]_i_1_n_0\
);
\skid_buffer[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(339),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(371),
O => \skid_buffer[22]_i_2_n_0\
);
\skid_buffer[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(307),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(275),
O => \skid_buffer[22]_i_3_n_0\
);
\skid_buffer[22]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => m_axi_rdata(435),
I1 => \skid_buffer[34]_i_8_n_0\,
I2 => m_axi_rdata(403),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(19),
I5 => \^skid_buffer_reg[3]_0\,
O => \skid_buffer[22]_i_4_n_0\
);
\skid_buffer[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(83),
I1 => m_axi_rdata(51),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(115),
O => \skid_buffer[22]_i_5_n_0\
);
\skid_buffer[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(211),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(243),
O => \skid_buffer[22]_i_6_n_0\
);
\skid_buffer[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(179),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(147),
O => \skid_buffer[22]_i_7_n_0\
);
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[23]_i_2_n_0\,
I1 => \skid_buffer[23]_i_3_n_0\,
I2 => \skid_buffer[23]_i_4_n_0\,
I3 => \skid_buffer[23]_i_5_n_0\,
I4 => \skid_buffer[23]_i_6_n_0\,
I5 => \skid_buffer[23]_i_7_n_0\,
O => \skid_buffer[23]_i_1_n_0\
);
\skid_buffer[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(340),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(372),
O => \skid_buffer[23]_i_2_n_0\
);
\skid_buffer[23]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(308),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(276),
O => \skid_buffer[23]_i_3_n_0\
);
\skid_buffer[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(20),
I2 => \skid_buffer[34]_i_8_n_0\,
I3 => m_axi_rdata(436),
I4 => m_axi_rdata(404),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[23]_i_4_n_0\
);
\skid_buffer[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0F0A000C000A00"
)
port map (
I0 => m_axi_rdata(52),
I1 => m_axi_rdata(116),
I2 => \^skid_buffer_reg[3]_2\,
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(84),
O => \skid_buffer[23]_i_5_n_0\
);
\skid_buffer[23]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(244),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(212),
O => \skid_buffer[23]_i_6_n_0\
);
\skid_buffer[23]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(148),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(180),
O => \skid_buffer[23]_i_7_n_0\
);
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[24]_i_2_n_0\,
I1 => \skid_buffer[24]_i_3_n_0\,
I2 => \skid_buffer[24]_i_4_n_0\,
I3 => \skid_buffer[24]_i_5_n_0\,
I4 => \skid_buffer[24]_i_6_n_0\,
I5 => \skid_buffer[24]_i_7_n_0\,
O => \skid_buffer[24]_i_1_n_0\
);
\skid_buffer[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(341),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(373),
O => \skid_buffer[24]_i_2_n_0\
);
\skid_buffer[24]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(277),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(309),
O => \skid_buffer[24]_i_3_n_0\
);
\skid_buffer[24]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(21),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(405),
I4 => m_axi_rdata(437),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[24]_i_4_n_0\
);
\skid_buffer[24]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(85),
I1 => m_axi_rdata(53),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(117),
O => \skid_buffer[24]_i_5_n_0\
);
\skid_buffer[24]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(213),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(245),
O => \skid_buffer[24]_i_6_n_0\
);
\skid_buffer[24]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(181),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(149),
O => \skid_buffer[24]_i_7_n_0\
);
\skid_buffer[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[25]_i_2_n_0\,
I1 => \skid_buffer[25]_i_3_n_0\,
I2 => \skid_buffer[25]_i_4_n_0\,
I3 => \skid_buffer[25]_i_5_n_0\,
I4 => \skid_buffer[25]_i_6_n_0\,
I5 => \skid_buffer[25]_i_7_n_0\,
O => \skid_buffer[25]_i_1_n_0\
);
\skid_buffer[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(374),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rdata(342),
O => \skid_buffer[25]_i_2_n_0\
);
\skid_buffer[25]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000C0000000A0"
)
port map (
I0 => m_axi_rdata(278),
I1 => m_axi_rdata(310),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_atarget_enc(0),
O => \skid_buffer[25]_i_3_n_0\
);
\skid_buffer[25]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(22),
I2 => m_axi_rdata(406),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(438),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[25]_i_4_n_0\
);
\skid_buffer[25]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(86),
I1 => m_axi_rdata(54),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(118),
O => \skid_buffer[25]_i_5_n_0\
);
\skid_buffer[25]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(246),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rdata(214),
O => \skid_buffer[25]_i_6_n_0\
);
\skid_buffer[25]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(150),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(182),
O => \skid_buffer[25]_i_7_n_0\
);
\skid_buffer[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[26]_i_2_n_0\,
I1 => \skid_buffer[26]_i_3_n_0\,
I2 => \skid_buffer[26]_i_4_n_0\,
I3 => \skid_buffer[26]_i_5_n_0\,
I4 => \skid_buffer[26]_i_6_n_0\,
I5 => \skid_buffer[26]_i_7_n_0\,
O => \skid_buffer[26]_i_1_n_0\
);
\skid_buffer[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(343),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(375),
O => \skid_buffer[26]_i_2_n_0\
);
\skid_buffer[26]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(279),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(311),
O => \skid_buffer[26]_i_3_n_0\
);
\skid_buffer[26]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(23),
I2 => \skid_buffer[34]_i_8_n_0\,
I3 => m_axi_rdata(439),
I4 => m_axi_rdata(407),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[26]_i_4_n_0\
);
\skid_buffer[26]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(87),
I1 => m_axi_rdata(55),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(119),
O => \skid_buffer[26]_i_5_n_0\
);
\skid_buffer[26]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(247),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rdata(215),
O => \skid_buffer[26]_i_6_n_0\
);
\skid_buffer[26]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(151),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(183),
O => \skid_buffer[26]_i_7_n_0\
);
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[27]_i_2_n_0\,
I1 => \skid_buffer[27]_i_3_n_0\,
I2 => \skid_buffer[27]_i_4_n_0\,
I3 => \skid_buffer[27]_i_5_n_0\,
I4 => \skid_buffer[27]_i_6_n_0\,
I5 => \skid_buffer[27]_i_7_n_0\,
O => \skid_buffer[27]_i_1_n_0\
);
\skid_buffer[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A000C000000000"
)
port map (
I0 => m_axi_rdata(376),
I1 => m_axi_rdata(344),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(0),
I5 => m_atarget_enc(1),
O => \skid_buffer[27]_i_2_n_0\
);
\skid_buffer[27]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(312),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(280),
O => \skid_buffer[27]_i_3_n_0\
);
\skid_buffer[27]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(24),
I2 => m_axi_rdata(440),
I3 => \skid_buffer[34]_i_8_n_0\,
I4 => m_axi_rdata(408),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[27]_i_4_n_0\
);
\skid_buffer[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(88),
I1 => m_axi_rdata(56),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(120),
O => \skid_buffer[27]_i_5_n_0\
);
\skid_buffer[27]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(248),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rdata(216),
O => \skid_buffer[27]_i_6_n_0\
);
\skid_buffer[27]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(184),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(152),
O => \skid_buffer[27]_i_7_n_0\
);
\skid_buffer[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[28]_i_2_n_0\,
I1 => \skid_buffer[28]_i_3_n_0\,
I2 => \skid_buffer[28]_i_4_n_0\,
I3 => \skid_buffer[28]_i_5_n_0\,
I4 => \skid_buffer[28]_i_6_n_0\,
I5 => \skid_buffer[28]_i_7_n_0\,
O => \skid_buffer[28]_i_1_n_0\
);
\skid_buffer[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(345),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(377),
O => \skid_buffer[28]_i_2_n_0\
);
\skid_buffer[28]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(313),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(281),
O => \skid_buffer[28]_i_3_n_0\
);
\skid_buffer[28]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => m_axi_rdata(441),
I1 => \skid_buffer[34]_i_8_n_0\,
I2 => m_axi_rdata(409),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(25),
I5 => \^skid_buffer_reg[3]_0\,
O => \skid_buffer[28]_i_4_n_0\
);
\skid_buffer[28]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(89),
I1 => m_axi_rdata(121),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(57),
O => \skid_buffer[28]_i_5_n_0\
);
\skid_buffer[28]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(217),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(249),
O => \skid_buffer[28]_i_6_n_0\
);
\skid_buffer[28]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(153),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(185),
O => \skid_buffer[28]_i_7_n_0\
);
\skid_buffer[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[29]_i_2_n_0\,
I1 => \skid_buffer[29]_i_3_n_0\,
I2 => \skid_buffer[29]_i_4_n_0\,
I3 => \skid_buffer[29]_i_5_n_0\,
I4 => \skid_buffer[29]_i_6_n_0\,
I5 => \skid_buffer[29]_i_7_n_0\,
O => \skid_buffer[29]_i_1_n_0\
);
\skid_buffer[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(346),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(378),
O => \skid_buffer[29]_i_2_n_0\
);
\skid_buffer[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(282),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(314),
O => \skid_buffer[29]_i_3_n_0\
);
\skid_buffer[29]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(26),
I2 => \skid_buffer[34]_i_8_n_0\,
I3 => m_axi_rdata(442),
I4 => m_axi_rdata(410),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[29]_i_4_n_0\
);
\skid_buffer[29]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(90),
I1 => m_axi_rdata(122),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(58),
O => \skid_buffer[29]_i_5_n_0\
);
\skid_buffer[29]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(250),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rdata(218),
O => \skid_buffer[29]_i_6_n_0\
);
\skid_buffer[29]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(154),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(186),
O => \skid_buffer[29]_i_7_n_0\
);
\skid_buffer[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[30]_i_2_n_0\,
I1 => \skid_buffer[30]_i_3_n_0\,
I2 => \skid_buffer[30]_i_4_n_0\,
I3 => \skid_buffer[30]_i_5_n_0\,
I4 => \skid_buffer[30]_i_6_n_0\,
I5 => \skid_buffer[30]_i_7_n_0\,
O => \skid_buffer[30]_i_1_n_0\
);
\skid_buffer[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(347),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(379),
O => \skid_buffer[30]_i_2_n_0\
);
\skid_buffer[30]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(283),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(315),
O => \skid_buffer[30]_i_3_n_0\
);
\skid_buffer[30]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(27),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(411),
I4 => m_axi_rdata(443),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[30]_i_4_n_0\
);
\skid_buffer[30]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(91),
I1 => m_axi_rdata(59),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(123),
O => \skid_buffer[30]_i_5_n_0\
);
\skid_buffer[30]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(219),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(251),
O => \skid_buffer[30]_i_6_n_0\
);
\skid_buffer[30]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(187),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(155),
O => \skid_buffer[30]_i_7_n_0\
);
\skid_buffer[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[31]_i_2_n_0\,
I1 => \skid_buffer[31]_i_3_n_0\,
I2 => \skid_buffer[31]_i_4_n_0\,
I3 => \skid_buffer[31]_i_5_n_0\,
I4 => \skid_buffer[31]_i_6_n_0\,
I5 => \skid_buffer[31]_i_7_n_0\,
O => \skid_buffer[31]_i_1_n_0\
);
\skid_buffer[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(348),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(380),
O => \skid_buffer[31]_i_2_n_0\
);
\skid_buffer[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(284),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(316),
O => \skid_buffer[31]_i_3_n_0\
);
\skid_buffer[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(28),
I2 => \skid_buffer[34]_i_8_n_0\,
I3 => m_axi_rdata(444),
I4 => m_axi_rdata(412),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[31]_i_4_n_0\
);
\skid_buffer[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(92),
I1 => m_axi_rdata(124),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(60),
O => \skid_buffer[31]_i_5_n_0\
);
\skid_buffer[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(252),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rdata(220),
O => \skid_buffer[31]_i_6_n_0\
);
\skid_buffer[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(156),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(188),
O => \skid_buffer[31]_i_7_n_0\
);
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[32]_i_2_n_0\,
I1 => \skid_buffer[32]_i_3_n_0\,
I2 => \skid_buffer[32]_i_4_n_0\,
I3 => \skid_buffer[32]_i_5_n_0\,
I4 => \skid_buffer[32]_i_6_n_0\,
I5 => \skid_buffer[32]_i_7_n_0\,
O => \skid_buffer[32]_i_1_n_0\
);
\skid_buffer[32]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(349),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(381),
O => \skid_buffer[32]_i_2_n_0\
);
\skid_buffer[32]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000C0000000A0"
)
port map (
I0 => m_axi_rdata(285),
I1 => m_axi_rdata(317),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => m_atarget_enc(1),
I5 => m_atarget_enc(0),
O => \skid_buffer[32]_i_3_n_0\
);
\skid_buffer[32]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(29),
I2 => m_axi_rdata(445),
I3 => \skid_buffer[34]_i_8_n_0\,
I4 => m_axi_rdata(413),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[32]_i_4_n_0\
);
\skid_buffer[32]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(93),
I1 => m_axi_rdata(61),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(125),
O => \skid_buffer[32]_i_5_n_0\
);
\skid_buffer[32]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(253),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rdata(221),
O => \skid_buffer[32]_i_6_n_0\
);
\skid_buffer[32]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(157),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(189),
O => \skid_buffer[32]_i_7_n_0\
);
\skid_buffer[33]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[33]_i_2_n_0\,
I1 => \skid_buffer[33]_i_3_n_0\,
I2 => \skid_buffer[33]_i_4_n_0\,
I3 => \skid_buffer[33]_i_5_n_0\,
I4 => \skid_buffer[33]_i_6_n_0\,
I5 => \skid_buffer[33]_i_7_n_0\,
O => \skid_buffer[33]_i_1_n_0\
);
\skid_buffer[33]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(350),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(382),
O => \skid_buffer[33]_i_2_n_0\
);
\skid_buffer[33]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(318),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(286),
O => \skid_buffer[33]_i_3_n_0\
);
\skid_buffer[33]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(30),
I2 => m_axi_rdata(446),
I3 => \skid_buffer[34]_i_8_n_0\,
I4 => m_axi_rdata(414),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[33]_i_4_n_0\
);
\skid_buffer[33]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(94),
I1 => m_axi_rdata(62),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(126),
O => \skid_buffer[33]_i_5_n_0\
);
\skid_buffer[33]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0000000A00000"
)
port map (
I0 => m_axi_rdata(222),
I1 => m_axi_rdata(254),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(3),
I4 => m_atarget_enc(1),
I5 => m_atarget_enc(0),
O => \skid_buffer[33]_i_6_n_0\
);
\skid_buffer[33]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(190),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(158),
O => \skid_buffer[33]_i_7_n_0\
);
\skid_buffer[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[34]_i_2_n_0\,
I1 => \skid_buffer[34]_i_3_n_0\,
I2 => \skid_buffer[34]_i_4_n_0\,
I3 => \skid_buffer[34]_i_5_n_0\,
I4 => \skid_buffer[34]_i_6_n_0\,
I5 => \skid_buffer[34]_i_7_n_0\,
O => \skid_buffer[34]_i_1_n_0\
);
\skid_buffer[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(351),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(383),
O => \skid_buffer[34]_i_2_n_0\
);
\skid_buffer[34]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(287),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(319),
O => \skid_buffer[34]_i_3_n_0\
);
\skid_buffer[34]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(31),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(415),
I4 => m_axi_rdata(447),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[34]_i_4_n_0\
);
\skid_buffer[34]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(95),
I1 => m_axi_rdata(127),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(63),
O => \skid_buffer[34]_i_5_n_0\
);
\skid_buffer[34]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(255),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_rdata(223),
O => \skid_buffer[34]_i_6_n_0\
);
\skid_buffer[34]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(159),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_rdata(191),
O => \skid_buffer[34]_i_7_n_0\
);
\skid_buffer[34]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"F7FF"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \skid_buffer[34]_i_8_n_0\
);
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[3]_i_2_n_0\,
I1 => \skid_buffer[3]_i_3_n_0\,
I2 => \skid_buffer[3]_i_4_n_0\,
I3 => \skid_buffer[3]_i_5_n_0\,
I4 => \skid_buffer[3]_i_6_n_0\,
I5 => \skid_buffer[3]_i_7_n_0\,
O => \skid_buffer[3]_i_1_n_0\
);
\skid_buffer[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(320),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(352),
O => \skid_buffer[3]_i_2_n_0\
);
\skid_buffer[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(256),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(288),
O => \skid_buffer[3]_i_3_n_0\
);
\skid_buffer[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^skid_buffer_reg[3]_0\,
I2 => m_axi_rdata(384),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(416),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[3]_i_4_n_0\
);
\skid_buffer[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(64),
I1 => m_axi_rdata(32),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(96),
O => \skid_buffer[3]_i_5_n_0\
);
\skid_buffer[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(192),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(224),
O => \skid_buffer[3]_i_6_n_0\
);
\skid_buffer[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(160),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(128),
O => \skid_buffer[3]_i_7_n_0\
);
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[4]_i_2_n_0\,
I1 => \skid_buffer[4]_i_3_n_0\,
I2 => \skid_buffer[4]_i_4_n_0\,
I3 => \skid_buffer[4]_i_5_n_0\,
I4 => \skid_buffer[4]_i_6_n_0\,
I5 => \skid_buffer[4]_i_7_n_0\,
O => \skid_buffer[4]_i_1_n_0\
);
\skid_buffer[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A000C000000000"
)
port map (
I0 => m_axi_rdata(353),
I1 => m_axi_rdata(321),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => \m_atarget_enc_reg[1]_rep\,
O => \skid_buffer[4]_i_2_n_0\
);
\skid_buffer[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(289),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(257),
O => \skid_buffer[4]_i_3_n_0\
);
\skid_buffer[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(1),
I2 => m_axi_rdata(417),
I3 => \skid_buffer[34]_i_8_n_0\,
I4 => m_axi_rdata(385),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[4]_i_4_n_0\
);
\skid_buffer[4]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(65),
I1 => m_axi_rdata(33),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(97),
O => \skid_buffer[4]_i_5_n_0\
);
\skid_buffer[4]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(225),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(193),
O => \skid_buffer[4]_i_6_n_0\
);
\skid_buffer[4]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(161),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(129),
O => \skid_buffer[4]_i_7_n_0\
);
\skid_buffer[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[5]_i_2_n_0\,
I1 => \skid_buffer[5]_i_3_n_0\,
I2 => \skid_buffer[5]_i_4_n_0\,
I3 => \skid_buffer[5]_i_5_n_0\,
I4 => \skid_buffer[5]_i_6_n_0\,
I5 => \skid_buffer[5]_i_7_n_0\,
O => \skid_buffer[5]_i_1_n_0\
);
\skid_buffer[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(322),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(354),
O => \skid_buffer[5]_i_2_n_0\
);
\skid_buffer[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(258),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(290),
O => \skid_buffer[5]_i_3_n_0\
);
\skid_buffer[5]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(2),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(386),
I4 => m_axi_rdata(418),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[5]_i_4_n_0\
);
\skid_buffer[5]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(66),
I1 => m_axi_rdata(34),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(98),
O => \skid_buffer[5]_i_5_n_0\
);
\skid_buffer[5]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(194),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(226),
O => \skid_buffer[5]_i_6_n_0\
);
\skid_buffer[5]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(162),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(130),
O => \skid_buffer[5]_i_7_n_0\
);
\skid_buffer[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[6]_i_2_n_0\,
I1 => \skid_buffer[6]_i_3_n_0\,
I2 => \skid_buffer[6]_i_4_n_0\,
I3 => \skid_buffer[6]_i_5_n_0\,
I4 => \skid_buffer[6]_i_6_n_0\,
I5 => \skid_buffer[6]_i_7_n_0\,
O => \skid_buffer[6]_i_1_n_0\
);
\skid_buffer[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(323),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(355),
O => \skid_buffer[6]_i_2_n_0\
);
\skid_buffer[6]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(291),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(259),
O => \skid_buffer[6]_i_3_n_0\
);
\skid_buffer[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F444F44FFFF4F44"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(3),
I2 => \^skid_buffer_reg[3]_1\,
I3 => m_axi_rdata(387),
I4 => m_axi_rdata(419),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[6]_i_4_n_0\
);
\skid_buffer[6]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(67),
I1 => m_axi_rdata(99),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(35),
O => \skid_buffer[6]_i_5_n_0\
);
\skid_buffer[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(227),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(195),
O => \skid_buffer[6]_i_6_n_0\
);
\skid_buffer[6]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(131),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(163),
O => \skid_buffer[6]_i_7_n_0\
);
\skid_buffer[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[7]_i_2_n_0\,
I1 => \skid_buffer[7]_i_3_n_0\,
I2 => \skid_buffer[7]_i_4_n_0\,
I3 => \skid_buffer[7]_i_5_n_0\,
I4 => \skid_buffer[7]_i_6_n_0\,
I5 => \skid_buffer[7]_i_7_n_0\,
O => \skid_buffer[7]_i_1_n_0\
);
\skid_buffer[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(356),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(324),
O => \skid_buffer[7]_i_2_n_0\
);
\skid_buffer[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000A0000000C0"
)
port map (
I0 => m_axi_rdata(292),
I1 => m_axi_rdata(260),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => \m_atarget_enc_reg[0]_rep\,
O => \skid_buffer[7]_i_3_n_0\
);
\skid_buffer[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(4),
I2 => m_axi_rdata(388),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(420),
I5 => \skid_buffer[34]_i_8_n_0\,
O => \skid_buffer[7]_i_4_n_0\
);
\skid_buffer[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(68),
I1 => m_axi_rdata(36),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(100),
O => \skid_buffer[7]_i_5_n_0\
);
\skid_buffer[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(196),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(228),
O => \skid_buffer[7]_i_6_n_0\
);
\skid_buffer[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(132),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(164),
O => \skid_buffer[7]_i_7_n_0\
);
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[8]_i_2_n_0\,
I1 => \skid_buffer[8]_i_3_n_0\,
I2 => \skid_buffer[8]_i_4_n_0\,
I3 => \skid_buffer[8]_i_5_n_0\,
I4 => \skid_buffer[8]_i_6_n_0\,
I5 => \skid_buffer[8]_i_7_n_0\,
O => \skid_buffer[8]_i_1_n_0\
);
\skid_buffer[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C00080000000800"
)
port map (
I0 => m_axi_rdata(325),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(357),
O => \skid_buffer[8]_i_2_n_0\
);
\skid_buffer[8]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(293),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(261),
O => \skid_buffer[8]_i_3_n_0\
);
\skid_buffer[8]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => m_axi_rdata(421),
I1 => \skid_buffer[34]_i_8_n_0\,
I2 => m_axi_rdata(389),
I3 => \^skid_buffer_reg[3]_1\,
I4 => m_axi_rdata(5),
I5 => \^skid_buffer_reg[3]_0\,
O => \skid_buffer[8]_i_4_n_0\
);
\skid_buffer[8]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000CAF00000CA00"
)
port map (
I0 => m_axi_rdata(69),
I1 => m_axi_rdata(101),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(37),
O => \skid_buffer[8]_i_5_n_0\
);
\skid_buffer[8]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(229),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(197),
O => \skid_buffer[8]_i_6_n_0\
);
\skid_buffer[8]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(133),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(165),
O => \skid_buffer[8]_i_7_n_0\
);
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \skid_buffer[9]_i_2_n_0\,
I1 => \skid_buffer[9]_i_3_n_0\,
I2 => \skid_buffer[9]_i_4_n_0\,
I3 => \skid_buffer[9]_i_5_n_0\,
I4 => \skid_buffer[9]_i_6_n_0\,
I5 => \skid_buffer[9]_i_7_n_0\,
O => \skid_buffer[9]_i_1_n_0\
);
\skid_buffer[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A000C000000000"
)
port map (
I0 => m_axi_rdata(358),
I1 => m_axi_rdata(326),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(2),
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => \m_atarget_enc_reg[1]_rep\,
O => \skid_buffer[9]_i_2_n_0\
);
\skid_buffer[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000C00080000"
)
port map (
I0 => m_axi_rdata(294),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(262),
O => \skid_buffer[9]_i_3_n_0\
);
\skid_buffer[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \^skid_buffer_reg[3]_0\,
I1 => m_axi_rdata(6),
I2 => m_axi_rdata(422),
I3 => \skid_buffer[34]_i_8_n_0\,
I4 => m_axi_rdata(390),
I5 => \^skid_buffer_reg[3]_1\,
O => \skid_buffer[9]_i_4_n_0\
);
\skid_buffer[9]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FAC000000AC0"
)
port map (
I0 => m_axi_rdata(70),
I1 => m_axi_rdata(38),
I2 => \m_atarget_enc_reg[0]_rep\,
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \^skid_buffer_reg[3]_2\,
I5 => m_axi_rdata(102),
O => \skid_buffer[9]_i_5_n_0\
);
\skid_buffer[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"080C000008000000"
)
port map (
I0 => m_axi_rdata(230),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[0]_rep\,
I4 => \m_atarget_enc_reg[1]_rep\,
I5 => m_axi_rdata(198),
O => \skid_buffer[9]_i_6_n_0\
);
\skid_buffer[9]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C000800000008"
)
port map (
I0 => m_axi_rdata(134),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => \m_atarget_enc_reg[1]_rep\,
I4 => \m_atarget_enc_reg[0]_rep\,
I5 => m_axi_rdata(166),
O => \skid_buffer[9]_i_7_n_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[0]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[10]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[11]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[12]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[13]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[14]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[15]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[16]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[17]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[18]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[19]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[20]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[21]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[22]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[23]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[24]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[25]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[26]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[27]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[28]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[29]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[30]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[31]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[32]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[33]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[34]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[3]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[4]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[5]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[6]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[7]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[8]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[9]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_1_axi_crossbar_v2_1_12_crossbar_sasd is
port (
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 12 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 12 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 12 downto 0 );
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_1_axi_crossbar_v2_1_12_crossbar_sasd : entity is "axi_crossbar_v2_1_12_crossbar_sasd";
end system_xbar_1_axi_crossbar_v2_1_12_crossbar_sasd;
architecture STRUCTURE of system_xbar_1_axi_crossbar_v2_1_12_crossbar_sasd is
signal aa_grant_rnw : STD_LOGIC;
signal aa_rready : STD_LOGIC;
signal addr_arbiter_inst_n_106 : STD_LOGIC;
signal addr_arbiter_inst_n_107 : STD_LOGIC;
signal addr_arbiter_inst_n_109 : STD_LOGIC;
signal addr_arbiter_inst_n_110 : STD_LOGIC;
signal addr_arbiter_inst_n_124 : STD_LOGIC;
signal addr_arbiter_inst_n_128 : STD_LOGIC;
signal addr_arbiter_inst_n_3 : STD_LOGIC;
signal addr_arbiter_inst_n_4 : STD_LOGIC;
signal addr_arbiter_inst_n_5 : STD_LOGIC;
signal addr_arbiter_inst_n_57 : STD_LOGIC;
signal addr_arbiter_inst_n_58 : STD_LOGIC;
signal addr_arbiter_inst_n_59 : STD_LOGIC;
signal addr_arbiter_inst_n_6 : STD_LOGIC;
signal addr_arbiter_inst_n_60 : STD_LOGIC;
signal addr_arbiter_inst_n_61 : STD_LOGIC;
signal addr_arbiter_inst_n_63 : STD_LOGIC;
signal addr_arbiter_inst_n_64 : STD_LOGIC;
signal addr_arbiter_inst_n_7 : STD_LOGIC;
signal addr_arbiter_inst_n_92 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_3\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_8\ : STD_LOGIC;
signal m_atarget_enc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \m_atarget_enc_reg[0]_rep_n_0\ : STD_LOGIC;
signal \m_atarget_enc_reg[1]_rep_n_0\ : STD_LOGIC;
signal m_atarget_hot : STD_LOGIC_VECTOR ( 14 downto 0 );
signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 14 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_0 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_valid_i : STD_LOGIC;
signal mi_bvalid : STD_LOGIC_VECTOR ( 14 to 14 );
signal mi_wready : STD_LOGIC_VECTOR ( 14 to 14 );
signal p_1_in : STD_LOGIC;
signal reg_slice_r_n_2 : STD_LOGIC;
signal reg_slice_r_n_37 : STD_LOGIC;
signal reg_slice_r_n_38 : STD_LOGIC;
signal reg_slice_r_n_39 : STD_LOGIC;
signal reg_slice_r_n_40 : STD_LOGIC;
signal reg_slice_r_n_41 : STD_LOGIC;
signal reg_slice_r_n_42 : STD_LOGIC;
signal reg_slice_r_n_43 : STD_LOGIC;
signal reg_slice_r_n_44 : STD_LOGIC;
signal reg_slice_r_n_45 : STD_LOGIC;
signal reg_slice_r_n_46 : STD_LOGIC;
signal reg_slice_r_n_47 : STD_LOGIC;
signal reg_slice_r_n_48 : STD_LOGIC;
signal reset : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_12_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \s_axi_bresp[0]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_8_n_0\ : STD_LOGIC;
signal \s_axi_bresp[1]_INST_0_i_9_n_0\ : STD_LOGIC;
signal splitter_ar_n_2 : STD_LOGIC;
signal splitter_ar_n_3 : STD_LOGIC;
signal splitter_ar_n_4 : STD_LOGIC;
signal splitter_ar_n_5 : STD_LOGIC;
signal splitter_ar_n_6 : STD_LOGIC;
signal splitter_aw_n_0 : STD_LOGIC;
signal splitter_aw_n_10 : STD_LOGIC;
signal splitter_aw_n_11 : STD_LOGIC;
signal splitter_aw_n_12 : STD_LOGIC;
signal splitter_aw_n_13 : STD_LOGIC;
signal splitter_aw_n_14 : STD_LOGIC;
signal splitter_aw_n_15 : STD_LOGIC;
signal splitter_aw_n_16 : STD_LOGIC;
signal splitter_aw_n_4 : STD_LOGIC;
signal splitter_aw_n_5 : STD_LOGIC;
signal splitter_aw_n_6 : STD_LOGIC;
signal splitter_aw_n_7 : STD_LOGIC;
signal splitter_aw_n_8 : STD_LOGIC;
signal splitter_aw_n_9 : STD_LOGIC;
signal sr_rvalid : STD_LOGIC;
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \m_atarget_enc_reg[0]\ : label is "m_atarget_enc_reg[0]";
attribute ORIG_CELL_NAME of \m_atarget_enc_reg[0]_rep\ : label is "m_atarget_enc_reg[0]";
attribute ORIG_CELL_NAME of \m_atarget_enc_reg[1]\ : label is "m_atarget_enc_reg[1]";
attribute ORIG_CELL_NAME of \m_atarget_enc_reg[1]_rep\ : label is "m_atarget_enc_reg[1]";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0_i_10\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0_i_12\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0_i_11\ : label is "soft_lutpair66";
begin
addr_arbiter_inst: entity work.system_xbar_1_axi_crossbar_v2_1_12_addr_arbiter_sasd
port map (
D(13 downto 10) => m_atarget_hot0(14 downto 11),
D(9 downto 0) => m_atarget_hot0(9 downto 0),
E(0) => p_1_in,
Q(34 downto 0) => Q(34 downto 0),
aa_grant_rnw => aa_grant_rnw,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_bvalid_i_reg\ => addr_arbiter_inst_n_92,
\gen_axilite.s_axi_bvalid_i_reg_0\ => addr_arbiter_inst_n_106,
\gen_axilite.s_axi_bvalid_i_reg_1\ => addr_arbiter_inst_n_128,
\gen_axilite.s_axi_rvalid_i_reg\ => addr_arbiter_inst_n_110,
m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0),
\m_atarget_enc_reg[0]\ => addr_arbiter_inst_n_4,
\m_atarget_enc_reg[0]_0\ => splitter_aw_n_15,
\m_atarget_enc_reg[0]_rep\ => addr_arbiter_inst_n_58,
\m_atarget_enc_reg[1]\ => addr_arbiter_inst_n_5,
\m_atarget_enc_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_atarget_enc_reg[1]_rep\ => addr_arbiter_inst_n_57,
\m_atarget_enc_reg[2]\ => addr_arbiter_inst_n_6,
\m_atarget_enc_reg[2]_0\ => splitter_aw_n_12,
\m_atarget_enc_reg[2]_1\ => splitter_aw_n_8,
\m_atarget_enc_reg[2]_2\ => splitter_aw_n_7,
\m_atarget_enc_reg[2]_3\ => splitter_aw_n_5,
\m_atarget_enc_reg[2]_4\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_atarget_enc_reg[2]_5\ => reg_slice_r_n_41,
\m_atarget_enc_reg[2]_6\ => splitter_ar_n_3,
\m_atarget_enc_reg[2]_7\ => splitter_ar_n_2,
\m_atarget_enc_reg[2]_8\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_atarget_enc_reg[3]\ => addr_arbiter_inst_n_7,
\m_atarget_enc_reg[3]_0\ => \gen_decerr.decerr_slave_inst_n_2\,
\m_atarget_enc_reg[3]_1\ => splitter_aw_n_14,
\m_atarget_enc_reg[3]_2\ => reg_slice_r_n_47,
\m_atarget_hot_reg[14]\(13 downto 10) => m_atarget_hot(14 downto 11),
\m_atarget_hot_reg[14]\(9 downto 0) => m_atarget_hot(9 downto 0),
m_axi_arvalid(12 downto 0) => m_axi_arvalid(12 downto 0),
m_axi_awvalid(12 downto 0) => m_axi_awvalid(12 downto 0),
m_axi_bready(12 downto 0) => m_axi_bready(12 downto 0),
m_axi_bvalid(1) => m_axi_bvalid(8),
m_axi_bvalid(0) => m_axi_bvalid(3),
m_axi_rvalid(0) => m_axi_rvalid(3),
m_axi_wready(6) => m_axi_wready(13),
m_axi_wready(5) => m_axi_wready(11),
m_axi_wready(4) => m_axi_wready(9),
m_axi_wready(3) => m_axi_wready(7),
m_axi_wready(2) => m_axi_wready(5),
m_axi_wready(1) => m_axi_wready(3),
m_axi_wready(0) => m_axi_wready(1),
m_axi_wvalid(12 downto 0) => m_axi_wvalid(12 downto 0),
m_ready_d(2 downto 0) => m_ready_d_0(2 downto 0),
m_ready_d_0(1 downto 0) => m_ready_d(1 downto 0),
\m_ready_d_reg[0]\ => addr_arbiter_inst_n_3,
\m_ready_d_reg[0]_0\ => addr_arbiter_inst_n_63,
\m_ready_d_reg[0]_1\ => addr_arbiter_inst_n_64,
\m_ready_d_reg[0]_2\ => addr_arbiter_inst_n_124,
\m_ready_d_reg[0]_3\ => splitter_aw_n_0,
\m_ready_d_reg[1]\ => addr_arbiter_inst_n_61,
\m_ready_d_reg[2]\ => addr_arbiter_inst_n_59,
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_60,
m_valid_i => m_valid_i,
m_valid_i_reg => addr_arbiter_inst_n_107,
m_valid_i_reg_0 => reg_slice_r_n_2,
mi_bvalid(0) => mi_bvalid(14),
mi_wready(0) => mi_wready(14),
reset => reset,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => addr_arbiter_inst_n_109,
sr_rvalid => sr_rvalid
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr.decerr_slave_inst\: entity work.system_xbar_1_axi_crossbar_v2_1_12_decerr_slave
port map (
Q(0) => m_atarget_hot(14),
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_awready_i_reg_0\ => addr_arbiter_inst_n_128,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_92,
\gen_no_arbiter.m_grant_hot_i_reg[0]\ => \gen_decerr.decerr_slave_inst_n_4\,
m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0),
\m_atarget_enc_reg[0]\ => splitter_aw_n_13,
\m_atarget_enc_reg[0]_0\ => splitter_aw_n_10,
\m_atarget_enc_reg[0]_1\ => splitter_aw_n_11,
\m_atarget_enc_reg[0]_2\ => splitter_ar_n_5,
\m_atarget_enc_reg[2]\ => splitter_aw_n_6,
\m_atarget_enc_reg[2]_0\ => splitter_ar_n_4,
\m_atarget_enc_reg[2]_1\ => splitter_aw_n_16,
\m_atarget_enc_reg[2]_2\ => reg_slice_r_n_48,
\m_atarget_enc_reg[3]\ => splitter_aw_n_4,
\m_atarget_enc_reg[3]_0\ => reg_slice_r_n_46,
\m_atarget_enc_reg[3]_1\ => splitter_ar_n_6,
m_axi_arready(3) => m_axi_arready(13),
m_axi_arready(2) => m_axi_arready(10),
m_axi_arready(1) => m_axi_arready(6),
m_axi_arready(0) => m_axi_arready(2),
m_axi_awready(2) => m_axi_awready(10),
m_axi_awready(1 downto 0) => m_axi_awready(2 downto 1),
m_axi_bvalid(3) => m_axi_bvalid(10),
m_axi_bvalid(2) => m_axi_bvalid(6),
m_axi_bvalid(1 downto 0) => m_axi_bvalid(2 downto 1),
m_axi_rvalid(2) => m_axi_rvalid(10),
m_axi_rvalid(1) => m_axi_rvalid(6),
m_axi_rvalid(0) => m_axi_rvalid(2),
m_axi_wready(2) => m_axi_wready(10),
m_axi_wready(1) => m_axi_wready(6),
m_axi_wready(0) => m_axi_wready(2),
\m_ready_d_reg[0]\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_ready_d_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_5\,
\m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_ready_d_reg[1]_0\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_110,
\m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_2\,
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_106,
m_valid_i_reg => \gen_decerr.decerr_slave_inst_n_8\,
mi_bvalid(0) => mi_bvalid(14),
mi_wready(0) => mi_wready(14),
reset => reset
);
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_4,
Q => m_atarget_enc(0),
R => reset
);
\m_atarget_enc_reg[0]_rep\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_58,
Q => \m_atarget_enc_reg[0]_rep_n_0\,
R => reset
);
\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_5,
Q => m_atarget_enc(1),
R => reset
);
\m_atarget_enc_reg[1]_rep\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_57,
Q => \m_atarget_enc_reg[1]_rep_n_0\,
R => reset
);
\m_atarget_enc_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_6,
Q => m_atarget_enc(2),
R => reset
);
\m_atarget_enc_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_7,
Q => m_atarget_enc(3),
R => reset
);
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(0),
Q => m_atarget_hot(0),
R => reset
);
\m_atarget_hot_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(11),
Q => m_atarget_hot(11),
R => reset
);
\m_atarget_hot_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(12),
Q => m_atarget_hot(12),
R => reset
);
\m_atarget_hot_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(13),
Q => m_atarget_hot(13),
R => reset
);
\m_atarget_hot_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(14),
Q => m_atarget_hot(14),
R => reset
);
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(1),
Q => m_atarget_hot(1),
R => reset
);
\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(2),
Q => m_atarget_hot(2),
R => reset
);
\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(3),
Q => m_atarget_hot(3),
R => reset
);
\m_atarget_hot_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(4),
Q => m_atarget_hot(4),
R => reset
);
\m_atarget_hot_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(5),
Q => m_atarget_hot(5),
R => reset
);
\m_atarget_hot_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(6),
Q => m_atarget_hot(6),
R => reset
);
\m_atarget_hot_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(7),
Q => m_atarget_hot(7),
R => reset
);
\m_atarget_hot_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(8),
Q => m_atarget_hot(8),
R => reset
);
\m_atarget_hot_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(9),
Q => m_atarget_hot(9),
R => reset
);
reg_slice_r: entity work.system_xbar_1_axi_register_slice_v2_1_11_axic_register_slice
port map (
E(0) => p_1_in,
Q(34 downto 1) => \s_axi_rdata[31]\(33 downto 0),
Q(0) => reg_slice_r_n_37,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0),
\m_atarget_enc_reg[0]_rep\ => \m_atarget_enc_reg[0]_rep_n_0\,
\m_atarget_enc_reg[1]\ => \gen_decerr.decerr_slave_inst_n_8\,
\m_atarget_enc_reg[1]_rep\ => \m_atarget_enc_reg[1]_rep_n_0\,
\m_atarget_hot_reg[13]\(12 downto 10) => m_atarget_hot(13 downto 11),
\m_atarget_hot_reg[13]\(9 downto 0) => m_atarget_hot(9 downto 0),
m_axi_rdata(447 downto 0) => m_axi_rdata(447 downto 0),
m_axi_rready(12 downto 0) => m_axi_rready(12 downto 0),
m_axi_rresp(27 downto 0) => m_axi_rresp(27 downto 0),
m_axi_rvalid(9 downto 7) => m_axi_rvalid(13 downto 11),
m_axi_rvalid(6 downto 4) => m_axi_rvalid(9 downto 7),
m_axi_rvalid(3 downto 2) => m_axi_rvalid(5 downto 4),
m_axi_rvalid(1 downto 0) => m_axi_rvalid(1 downto 0),
\m_payload_i_reg[1]_0\ => reg_slice_r_n_39,
\m_payload_i_reg[1]_1\ => reg_slice_r_n_40,
\m_payload_i_reg[1]_2\ => reg_slice_r_n_41,
\m_payload_i_reg[2]_0\ => reg_slice_r_n_38,
\m_payload_i_reg[2]_1\ => reg_slice_r_n_42,
\m_payload_i_reg[2]_2\ => reg_slice_r_n_43,
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => addr_arbiter_inst_n_107,
\m_ready_d_reg[1]\ => reg_slice_r_n_2,
m_valid_i => m_valid_i,
m_valid_i_reg_0 => reg_slice_r_n_47,
m_valid_i_reg_1 => reg_slice_r_n_48,
m_valid_i_reg_2 => addr_arbiter_inst_n_109,
reset => reset,
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[3]_0\ => reg_slice_r_n_44,
\skid_buffer_reg[3]_1\ => reg_slice_r_n_45,
\skid_buffer_reg[3]_2\ => reg_slice_r_n_46,
sr_rvalid => sr_rvalid
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF2"
)
port map (
I0 => m_axi_bresp(2),
I1 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
I2 => reg_slice_r_n_43,
I3 => \s_axi_bresp[0]_INST_0_i_2_n_0\,
I4 => \s_axi_bresp[0]_INST_0_i_3_n_0\,
I5 => \s_axi_bresp[0]_INST_0_i_4_n_0\,
O => s_axi_bresp(0)
);
\s_axi_bresp[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \s_axi_bresp[0]_INST_0_i_1_n_0\
);
\s_axi_bresp[0]_INST_0_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => m_atarget_enc(3),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \s_axi_bresp[0]_INST_0_i_10_n_0\
);
\s_axi_bresp[0]_INST_0_i_12\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
O => \s_axi_bresp[0]_INST_0_i_12_n_0\
);
\s_axi_bresp[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0308000000080000"
)
port map (
I0 => m_axi_bresp(10),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_bresp(6),
O => \s_axi_bresp[0]_INST_0_i_2_n_0\
);
\s_axi_bresp[0]_INST_0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF22F2"
)
port map (
I0 => m_axi_bresp(8),
I1 => reg_slice_r_n_38,
I2 => m_axi_bresp(12),
I3 => reg_slice_r_n_40,
I4 => \s_axi_bresp[0]_INST_0_i_7_n_0\,
O => \s_axi_bresp[0]_INST_0_i_3_n_0\
);
\s_axi_bresp[0]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEEFFFFEFEEEFEE"
)
port map (
I0 => \s_axi_bresp[0]_INST_0_i_8_n_0\,
I1 => \s_axi_bresp[0]_INST_0_i_9_n_0\,
I2 => \s_axi_bresp[0]_INST_0_i_10_n_0\,
I3 => m_axi_bresp(22),
I4 => reg_slice_r_n_44,
I5 => m_axi_bresp(0),
O => \s_axi_bresp[0]_INST_0_i_4_n_0\
);
\s_axi_bresp[0]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000C00800000"
)
port map (
I0 => m_axi_bresp(26),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_bresp(16),
O => \s_axi_bresp[0]_INST_0_i_7_n_0\
);
\s_axi_bresp[0]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \s_axi_bresp[1]_INST_0_i_11_n_0\,
I1 => m_axi_bresp(4),
I2 => m_axi_bresp(18),
I3 => reg_slice_r_n_39,
I4 => m_axi_bresp(14),
I5 => \s_axi_bresp[0]_INST_0_i_12_n_0\,
O => \s_axi_bresp[0]_INST_0_i_8_n_0\
);
\s_axi_bresp[0]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"000020C000002000"
)
port map (
I0 => m_axi_bresp(20),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_bresp(24),
O => \s_axi_bresp[0]_INST_0_i_9_n_0\
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF2"
)
port map (
I0 => m_axi_bresp(19),
I1 => reg_slice_r_n_39,
I2 => reg_slice_r_n_43,
I3 => \s_axi_bresp[1]_INST_0_i_3_n_0\,
I4 => \s_axi_bresp[1]_INST_0_i_4_n_0\,
I5 => \s_axi_bresp[1]_INST_0_i_5_n_0\,
O => s_axi_bresp(1)
);
\s_axi_bresp[1]_INST_0_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => m_atarget_enc(2),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(0),
I3 => m_atarget_enc(1),
O => \s_axi_bresp[1]_INST_0_i_11_n_0\
);
\s_axi_bresp[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000300080000"
)
port map (
I0 => m_axi_bresp(11),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_bresp(1),
O => \s_axi_bresp[1]_INST_0_i_3_n_0\
);
\s_axi_bresp[1]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF22F2"
)
port map (
I0 => m_axi_bresp(7),
I1 => reg_slice_r_n_41,
I2 => m_axi_bresp(3),
I3 => \s_axi_bresp[0]_INST_0_i_1_n_0\,
I4 => \s_axi_bresp[1]_INST_0_i_7_n_0\,
O => \s_axi_bresp[1]_INST_0_i_4_n_0\
);
\s_axi_bresp[1]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEEFFFFEFEEEFEE"
)
port map (
I0 => \s_axi_bresp[1]_INST_0_i_8_n_0\,
I1 => \s_axi_bresp[1]_INST_0_i_9_n_0\,
I2 => reg_slice_r_n_42,
I3 => m_axi_bresp(17),
I4 => \s_axi_bresp[1]_INST_0_i_11_n_0\,
I5 => m_axi_bresp(5),
O => \s_axi_bresp[1]_INST_0_i_5_n_0\
);
\s_axi_bresp[1]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"200C000020000000"
)
port map (
I0 => m_axi_bresp(15),
I1 => m_atarget_enc(3),
I2 => m_atarget_enc(2),
I3 => m_atarget_enc(0),
I4 => m_atarget_enc(1),
I5 => m_axi_bresp(21),
O => \s_axi_bresp[1]_INST_0_i_7_n_0\
);
\s_axi_bresp[1]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"44F444F4FFFF44F4"
)
port map (
I0 => \s_axi_bresp[0]_INST_0_i_10_n_0\,
I1 => m_axi_bresp(23),
I2 => m_axi_bresp(25),
I3 => reg_slice_r_n_45,
I4 => m_axi_bresp(13),
I5 => reg_slice_r_n_40,
O => \s_axi_bresp[1]_INST_0_i_8_n_0\
);
\s_axi_bresp[1]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0000800000008"
)
port map (
I0 => m_axi_bresp(9),
I1 => m_atarget_enc(2),
I2 => m_atarget_enc(3),
I3 => m_atarget_enc(1),
I4 => m_atarget_enc(0),
I5 => m_axi_bresp(27),
O => \s_axi_bresp[1]_INST_0_i_9_n_0\
);
splitter_ar: entity work.\system_xbar_1_axi_crossbar_v2_1_12_splitter__parameterized0\
port map (
Q(0) => reg_slice_r_n_37,
aclk => aclk,
aresetn_d => aresetn_d,
aresetn_d_reg => addr_arbiter_inst_n_3,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_124,
m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0),
\m_atarget_enc_reg[0]\ => splitter_aw_n_9,
\m_atarget_enc_reg[2]\ => \gen_decerr.decerr_slave_inst_n_6\,
m_axi_arready(11 downto 9) => m_axi_arready(13 downto 11),
m_axi_arready(8 downto 6) => m_axi_arready(9 downto 7),
m_axi_arready(5 downto 0) => m_axi_arready(5 downto 0),
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
\m_ready_d_reg[0]_0\ => splitter_ar_n_5,
\m_ready_d_reg[0]_1\ => splitter_ar_n_6,
\m_ready_d_reg[1]_0\ => splitter_ar_n_2,
\m_ready_d_reg[1]_1\ => splitter_ar_n_3,
\m_ready_d_reg[1]_2\ => splitter_ar_n_4,
\m_ready_d_reg[1]_3\ => addr_arbiter_inst_n_110,
m_valid_i_reg => reg_slice_r_n_2,
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
splitter_aw: entity work.system_xbar_1_axi_crossbar_v2_1_12_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_grant_hot_i_reg[0]\ => splitter_aw_n_0,
m_atarget_enc(3 downto 0) => m_atarget_enc(3 downto 0),
\m_atarget_enc_reg[1]\ => addr_arbiter_inst_n_61,
\m_atarget_enc_reg[2]\ => \gen_decerr.decerr_slave_inst_n_4\,
m_axi_awready(10 downto 8) => m_axi_awready(13 downto 11),
m_axi_awready(7 downto 1) => m_axi_awready(9 downto 3),
m_axi_awready(0) => m_axi_awready(0),
m_axi_bvalid(10 downto 8) => m_axi_bvalid(13 downto 11),
m_axi_bvalid(7 downto 2) => m_axi_bvalid(9 downto 4),
m_axi_bvalid(1 downto 0) => m_axi_bvalid(1 downto 0),
m_axi_wready(3) => m_axi_wready(12),
m_axi_wready(2) => m_axi_wready(8),
m_axi_wready(1) => m_axi_wready(4),
m_axi_wready(0) => m_axi_wready(0),
m_ready_d(2 downto 0) => m_ready_d_0(2 downto 0),
\m_ready_d_reg[0]_0\ => splitter_aw_n_5,
\m_ready_d_reg[0]_1\ => splitter_aw_n_6,
\m_ready_d_reg[0]_2\ => splitter_aw_n_7,
\m_ready_d_reg[0]_3\ => splitter_aw_n_11,
\m_ready_d_reg[0]_4\ => splitter_aw_n_14,
\m_ready_d_reg[0]_5\ => splitter_aw_n_15,
\m_ready_d_reg[0]_6\ => addr_arbiter_inst_n_64,
\m_ready_d_reg[0]_7\ => addr_arbiter_inst_n_63,
\m_ready_d_reg[1]_0\ => splitter_aw_n_16,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_60,
\m_ready_d_reg[2]_0\ => splitter_aw_n_4,
\m_ready_d_reg[2]_1\ => splitter_aw_n_8,
\m_ready_d_reg[2]_2\ => splitter_aw_n_9,
\m_ready_d_reg[2]_3\ => splitter_aw_n_10,
\m_ready_d_reg[2]_4\ => splitter_aw_n_12,
\m_ready_d_reg[2]_5\ => splitter_aw_n_13,
\m_ready_d_reg[2]_6\ => addr_arbiter_inst_n_59,
s_axi_bready(0) => s_axi_bready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 111 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 111 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "artix7";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "448'b0000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "896'b00000000000000000000000000000000010001001010001000000000000000000000000000000000000000000000000001000000000001000000000000000000000000000000000000000000000000000100000000000011000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000001000000000000100000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000100000000000000000000000000000000000000000000000000000000100010010100001000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000011000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000001110000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "448'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 14;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "axi_crossbar_v2_1_12_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "artix7";
attribute P_INCR : string;
attribute P_INCR of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "448'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "14'b11111111111111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "14'b11111111111111";
attribute P_ONES : string;
attribute P_ONES of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar : entity is "1'b1";
end system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar;
architecture STRUCTURE of system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_arvalid\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 447 downto 432 );
signal \^m_axi_awvalid\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \^m_axi_rready\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \^m_axi_wvalid\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(447 downto 432) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(431 downto 416) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(415 downto 400) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(399 downto 384) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(383 downto 368) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(367 downto 352) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(351 downto 336) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(335 downto 320) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(319 downto 304) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(303 downto 288) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(287 downto 272) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(271 downto 256) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(255 downto 240) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(239 downto 224) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(223 downto 208) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(207 downto 192) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(191 downto 176) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(175 downto 160) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(159 downto 144) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(143 downto 128) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(127 downto 112) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(111 downto 96) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(95 downto 80) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(63 downto 48) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(31 downto 16) <= \^m_axi_awaddr\(447 downto 432);
m_axi_araddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0);
m_axi_arburst(27) <= \<const0>\;
m_axi_arburst(26) <= \<const0>\;
m_axi_arburst(25) <= \<const0>\;
m_axi_arburst(24) <= \<const0>\;
m_axi_arburst(23) <= \<const0>\;
m_axi_arburst(22) <= \<const0>\;
m_axi_arburst(21) <= \<const0>\;
m_axi_arburst(20) <= \<const0>\;
m_axi_arburst(19) <= \<const0>\;
m_axi_arburst(18) <= \<const0>\;
m_axi_arburst(17) <= \<const0>\;
m_axi_arburst(16) <= \<const0>\;
m_axi_arburst(15) <= \<const0>\;
m_axi_arburst(14) <= \<const0>\;
m_axi_arburst(13) <= \<const0>\;
m_axi_arburst(12) <= \<const0>\;
m_axi_arburst(11) <= \<const0>\;
m_axi_arburst(10) <= \<const0>\;
m_axi_arburst(9) <= \<const0>\;
m_axi_arburst(8) <= \<const0>\;
m_axi_arburst(7) <= \<const0>\;
m_axi_arburst(6) <= \<const0>\;
m_axi_arburst(5) <= \<const0>\;
m_axi_arburst(4) <= \<const0>\;
m_axi_arburst(3) <= \<const0>\;
m_axi_arburst(2) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(55) <= \<const0>\;
m_axi_arcache(54) <= \<const0>\;
m_axi_arcache(53) <= \<const0>\;
m_axi_arcache(52) <= \<const0>\;
m_axi_arcache(51) <= \<const0>\;
m_axi_arcache(50) <= \<const0>\;
m_axi_arcache(49) <= \<const0>\;
m_axi_arcache(48) <= \<const0>\;
m_axi_arcache(47) <= \<const0>\;
m_axi_arcache(46) <= \<const0>\;
m_axi_arcache(45) <= \<const0>\;
m_axi_arcache(44) <= \<const0>\;
m_axi_arcache(43) <= \<const0>\;
m_axi_arcache(42) <= \<const0>\;
m_axi_arcache(41) <= \<const0>\;
m_axi_arcache(40) <= \<const0>\;
m_axi_arcache(39) <= \<const0>\;
m_axi_arcache(38) <= \<const0>\;
m_axi_arcache(37) <= \<const0>\;
m_axi_arcache(36) <= \<const0>\;
m_axi_arcache(35) <= \<const0>\;
m_axi_arcache(34) <= \<const0>\;
m_axi_arcache(33) <= \<const0>\;
m_axi_arcache(32) <= \<const0>\;
m_axi_arcache(31) <= \<const0>\;
m_axi_arcache(30) <= \<const0>\;
m_axi_arcache(29) <= \<const0>\;
m_axi_arcache(28) <= \<const0>\;
m_axi_arcache(27) <= \<const0>\;
m_axi_arcache(26) <= \<const0>\;
m_axi_arcache(25) <= \<const0>\;
m_axi_arcache(24) <= \<const0>\;
m_axi_arcache(23) <= \<const0>\;
m_axi_arcache(22) <= \<const0>\;
m_axi_arcache(21) <= \<const0>\;
m_axi_arcache(20) <= \<const0>\;
m_axi_arcache(19) <= \<const0>\;
m_axi_arcache(18) <= \<const0>\;
m_axi_arcache(17) <= \<const0>\;
m_axi_arcache(16) <= \<const0>\;
m_axi_arcache(15) <= \<const0>\;
m_axi_arcache(14) <= \<const0>\;
m_axi_arcache(13) <= \<const0>\;
m_axi_arcache(12) <= \<const0>\;
m_axi_arcache(11) <= \<const0>\;
m_axi_arcache(10) <= \<const0>\;
m_axi_arcache(9) <= \<const0>\;
m_axi_arcache(8) <= \<const0>\;
m_axi_arcache(7) <= \<const0>\;
m_axi_arcache(6) <= \<const0>\;
m_axi_arcache(5) <= \<const0>\;
m_axi_arcache(4) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(13) <= \<const0>\;
m_axi_arid(12) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(111) <= \<const0>\;
m_axi_arlen(110) <= \<const0>\;
m_axi_arlen(109) <= \<const0>\;
m_axi_arlen(108) <= \<const0>\;
m_axi_arlen(107) <= \<const0>\;
m_axi_arlen(106) <= \<const0>\;
m_axi_arlen(105) <= \<const0>\;
m_axi_arlen(104) <= \<const0>\;
m_axi_arlen(103) <= \<const0>\;
m_axi_arlen(102) <= \<const0>\;
m_axi_arlen(101) <= \<const0>\;
m_axi_arlen(100) <= \<const0>\;
m_axi_arlen(99) <= \<const0>\;
m_axi_arlen(98) <= \<const0>\;
m_axi_arlen(97) <= \<const0>\;
m_axi_arlen(96) <= \<const0>\;
m_axi_arlen(95) <= \<const0>\;
m_axi_arlen(94) <= \<const0>\;
m_axi_arlen(93) <= \<const0>\;
m_axi_arlen(92) <= \<const0>\;
m_axi_arlen(91) <= \<const0>\;
m_axi_arlen(90) <= \<const0>\;
m_axi_arlen(89) <= \<const0>\;
m_axi_arlen(88) <= \<const0>\;
m_axi_arlen(87) <= \<const0>\;
m_axi_arlen(86) <= \<const0>\;
m_axi_arlen(85) <= \<const0>\;
m_axi_arlen(84) <= \<const0>\;
m_axi_arlen(83) <= \<const0>\;
m_axi_arlen(82) <= \<const0>\;
m_axi_arlen(81) <= \<const0>\;
m_axi_arlen(80) <= \<const0>\;
m_axi_arlen(79) <= \<const0>\;
m_axi_arlen(78) <= \<const0>\;
m_axi_arlen(77) <= \<const0>\;
m_axi_arlen(76) <= \<const0>\;
m_axi_arlen(75) <= \<const0>\;
m_axi_arlen(74) <= \<const0>\;
m_axi_arlen(73) <= \<const0>\;
m_axi_arlen(72) <= \<const0>\;
m_axi_arlen(71) <= \<const0>\;
m_axi_arlen(70) <= \<const0>\;
m_axi_arlen(69) <= \<const0>\;
m_axi_arlen(68) <= \<const0>\;
m_axi_arlen(67) <= \<const0>\;
m_axi_arlen(66) <= \<const0>\;
m_axi_arlen(65) <= \<const0>\;
m_axi_arlen(64) <= \<const0>\;
m_axi_arlen(63) <= \<const0>\;
m_axi_arlen(62) <= \<const0>\;
m_axi_arlen(61) <= \<const0>\;
m_axi_arlen(60) <= \<const0>\;
m_axi_arlen(59) <= \<const0>\;
m_axi_arlen(58) <= \<const0>\;
m_axi_arlen(57) <= \<const0>\;
m_axi_arlen(56) <= \<const0>\;
m_axi_arlen(55) <= \<const0>\;
m_axi_arlen(54) <= \<const0>\;
m_axi_arlen(53) <= \<const0>\;
m_axi_arlen(52) <= \<const0>\;
m_axi_arlen(51) <= \<const0>\;
m_axi_arlen(50) <= \<const0>\;
m_axi_arlen(49) <= \<const0>\;
m_axi_arlen(48) <= \<const0>\;
m_axi_arlen(47) <= \<const0>\;
m_axi_arlen(46) <= \<const0>\;
m_axi_arlen(45) <= \<const0>\;
m_axi_arlen(44) <= \<const0>\;
m_axi_arlen(43) <= \<const0>\;
m_axi_arlen(42) <= \<const0>\;
m_axi_arlen(41) <= \<const0>\;
m_axi_arlen(40) <= \<const0>\;
m_axi_arlen(39) <= \<const0>\;
m_axi_arlen(38) <= \<const0>\;
m_axi_arlen(37) <= \<const0>\;
m_axi_arlen(36) <= \<const0>\;
m_axi_arlen(35) <= \<const0>\;
m_axi_arlen(34) <= \<const0>\;
m_axi_arlen(33) <= \<const0>\;
m_axi_arlen(32) <= \<const0>\;
m_axi_arlen(31) <= \<const0>\;
m_axi_arlen(30) <= \<const0>\;
m_axi_arlen(29) <= \<const0>\;
m_axi_arlen(28) <= \<const0>\;
m_axi_arlen(27) <= \<const0>\;
m_axi_arlen(26) <= \<const0>\;
m_axi_arlen(25) <= \<const0>\;
m_axi_arlen(24) <= \<const0>\;
m_axi_arlen(23) <= \<const0>\;
m_axi_arlen(22) <= \<const0>\;
m_axi_arlen(21) <= \<const0>\;
m_axi_arlen(20) <= \<const0>\;
m_axi_arlen(19) <= \<const0>\;
m_axi_arlen(18) <= \<const0>\;
m_axi_arlen(17) <= \<const0>\;
m_axi_arlen(16) <= \<const0>\;
m_axi_arlen(15) <= \<const0>\;
m_axi_arlen(14) <= \<const0>\;
m_axi_arlen(13) <= \<const0>\;
m_axi_arlen(12) <= \<const0>\;
m_axi_arlen(11) <= \<const0>\;
m_axi_arlen(10) <= \<const0>\;
m_axi_arlen(9) <= \<const0>\;
m_axi_arlen(8) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(13) <= \<const0>\;
m_axi_arlock(12) <= \<const0>\;
m_axi_arlock(11) <= \<const0>\;
m_axi_arlock(10) <= \<const0>\;
m_axi_arlock(9) <= \<const0>\;
m_axi_arlock(8) <= \<const0>\;
m_axi_arlock(7) <= \<const0>\;
m_axi_arlock(6) <= \<const0>\;
m_axi_arlock(5) <= \<const0>\;
m_axi_arlock(4) <= \<const0>\;
m_axi_arlock(3) <= \<const0>\;
m_axi_arlock(2) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(41 downto 39) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(38 downto 36) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(35 downto 33) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(32 downto 30) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(29 downto 27) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(26 downto 24) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(23 downto 21) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(20 downto 18) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(17 downto 15) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_arqos(55) <= \<const0>\;
m_axi_arqos(54) <= \<const0>\;
m_axi_arqos(53) <= \<const0>\;
m_axi_arqos(52) <= \<const0>\;
m_axi_arqos(51) <= \<const0>\;
m_axi_arqos(50) <= \<const0>\;
m_axi_arqos(49) <= \<const0>\;
m_axi_arqos(48) <= \<const0>\;
m_axi_arqos(47) <= \<const0>\;
m_axi_arqos(46) <= \<const0>\;
m_axi_arqos(45) <= \<const0>\;
m_axi_arqos(44) <= \<const0>\;
m_axi_arqos(43) <= \<const0>\;
m_axi_arqos(42) <= \<const0>\;
m_axi_arqos(41) <= \<const0>\;
m_axi_arqos(40) <= \<const0>\;
m_axi_arqos(39) <= \<const0>\;
m_axi_arqos(38) <= \<const0>\;
m_axi_arqos(37) <= \<const0>\;
m_axi_arqos(36) <= \<const0>\;
m_axi_arqos(35) <= \<const0>\;
m_axi_arqos(34) <= \<const0>\;
m_axi_arqos(33) <= \<const0>\;
m_axi_arqos(32) <= \<const0>\;
m_axi_arqos(31) <= \<const0>\;
m_axi_arqos(30) <= \<const0>\;
m_axi_arqos(29) <= \<const0>\;
m_axi_arqos(28) <= \<const0>\;
m_axi_arqos(27) <= \<const0>\;
m_axi_arqos(26) <= \<const0>\;
m_axi_arqos(25) <= \<const0>\;
m_axi_arqos(24) <= \<const0>\;
m_axi_arqos(23) <= \<const0>\;
m_axi_arqos(22) <= \<const0>\;
m_axi_arqos(21) <= \<const0>\;
m_axi_arqos(20) <= \<const0>\;
m_axi_arqos(19) <= \<const0>\;
m_axi_arqos(18) <= \<const0>\;
m_axi_arqos(17) <= \<const0>\;
m_axi_arqos(16) <= \<const0>\;
m_axi_arqos(15) <= \<const0>\;
m_axi_arqos(14) <= \<const0>\;
m_axi_arqos(13) <= \<const0>\;
m_axi_arqos(12) <= \<const0>\;
m_axi_arqos(11) <= \<const0>\;
m_axi_arqos(10) <= \<const0>\;
m_axi_arqos(9) <= \<const0>\;
m_axi_arqos(8) <= \<const0>\;
m_axi_arqos(7) <= \<const0>\;
m_axi_arqos(6) <= \<const0>\;
m_axi_arqos(5) <= \<const0>\;
m_axi_arqos(4) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(55) <= \<const0>\;
m_axi_arregion(54) <= \<const0>\;
m_axi_arregion(53) <= \<const0>\;
m_axi_arregion(52) <= \<const0>\;
m_axi_arregion(51) <= \<const0>\;
m_axi_arregion(50) <= \<const0>\;
m_axi_arregion(49) <= \<const0>\;
m_axi_arregion(48) <= \<const0>\;
m_axi_arregion(47) <= \<const0>\;
m_axi_arregion(46) <= \<const0>\;
m_axi_arregion(45) <= \<const0>\;
m_axi_arregion(44) <= \<const0>\;
m_axi_arregion(43) <= \<const0>\;
m_axi_arregion(42) <= \<const0>\;
m_axi_arregion(41) <= \<const0>\;
m_axi_arregion(40) <= \<const0>\;
m_axi_arregion(39) <= \<const0>\;
m_axi_arregion(38) <= \<const0>\;
m_axi_arregion(37) <= \<const0>\;
m_axi_arregion(36) <= \<const0>\;
m_axi_arregion(35) <= \<const0>\;
m_axi_arregion(34) <= \<const0>\;
m_axi_arregion(33) <= \<const0>\;
m_axi_arregion(32) <= \<const0>\;
m_axi_arregion(31) <= \<const0>\;
m_axi_arregion(30) <= \<const0>\;
m_axi_arregion(29) <= \<const0>\;
m_axi_arregion(28) <= \<const0>\;
m_axi_arregion(27) <= \<const0>\;
m_axi_arregion(26) <= \<const0>\;
m_axi_arregion(25) <= \<const0>\;
m_axi_arregion(24) <= \<const0>\;
m_axi_arregion(23) <= \<const0>\;
m_axi_arregion(22) <= \<const0>\;
m_axi_arregion(21) <= \<const0>\;
m_axi_arregion(20) <= \<const0>\;
m_axi_arregion(19) <= \<const0>\;
m_axi_arregion(18) <= \<const0>\;
m_axi_arregion(17) <= \<const0>\;
m_axi_arregion(16) <= \<const0>\;
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(41) <= \<const0>\;
m_axi_arsize(40) <= \<const0>\;
m_axi_arsize(39) <= \<const0>\;
m_axi_arsize(38) <= \<const0>\;
m_axi_arsize(37) <= \<const0>\;
m_axi_arsize(36) <= \<const0>\;
m_axi_arsize(35) <= \<const0>\;
m_axi_arsize(34) <= \<const0>\;
m_axi_arsize(33) <= \<const0>\;
m_axi_arsize(32) <= \<const0>\;
m_axi_arsize(31) <= \<const0>\;
m_axi_arsize(30) <= \<const0>\;
m_axi_arsize(29) <= \<const0>\;
m_axi_arsize(28) <= \<const0>\;
m_axi_arsize(27) <= \<const0>\;
m_axi_arsize(26) <= \<const0>\;
m_axi_arsize(25) <= \<const0>\;
m_axi_arsize(24) <= \<const0>\;
m_axi_arsize(23) <= \<const0>\;
m_axi_arsize(22) <= \<const0>\;
m_axi_arsize(21) <= \<const0>\;
m_axi_arsize(20) <= \<const0>\;
m_axi_arsize(19) <= \<const0>\;
m_axi_arsize(18) <= \<const0>\;
m_axi_arsize(17) <= \<const0>\;
m_axi_arsize(16) <= \<const0>\;
m_axi_arsize(15) <= \<const0>\;
m_axi_arsize(14) <= \<const0>\;
m_axi_arsize(13) <= \<const0>\;
m_axi_arsize(12) <= \<const0>\;
m_axi_arsize(11) <= \<const0>\;
m_axi_arsize(10) <= \<const0>\;
m_axi_arsize(9) <= \<const0>\;
m_axi_arsize(8) <= \<const0>\;
m_axi_arsize(7) <= \<const0>\;
m_axi_arsize(6) <= \<const0>\;
m_axi_arsize(5) <= \<const0>\;
m_axi_arsize(4) <= \<const0>\;
m_axi_arsize(3) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(13) <= \<const0>\;
m_axi_aruser(12) <= \<const0>\;
m_axi_aruser(11) <= \<const0>\;
m_axi_aruser(10) <= \<const0>\;
m_axi_aruser(9) <= \<const0>\;
m_axi_aruser(8) <= \<const0>\;
m_axi_aruser(7) <= \<const0>\;
m_axi_aruser(6) <= \<const0>\;
m_axi_aruser(5) <= \<const0>\;
m_axi_aruser(4) <= \<const0>\;
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid(13 downto 11) <= \^m_axi_arvalid\(13 downto 11);
m_axi_arvalid(10) <= \<const0>\;
m_axi_arvalid(9 downto 0) <= \^m_axi_arvalid\(9 downto 0);
m_axi_awaddr(447 downto 432) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(431 downto 416) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(415 downto 400) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(399 downto 384) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(383 downto 368) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(367 downto 352) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(351 downto 336) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(335 downto 320) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(319 downto 304) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(303 downto 288) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(287 downto 272) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(271 downto 256) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(255 downto 240) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(239 downto 224) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(223 downto 208) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(207 downto 192) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(191 downto 176) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(175 downto 160) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(159 downto 144) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(143 downto 128) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(127 downto 112) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(111 downto 96) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(95 downto 80) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(63 downto 48) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(31 downto 16) <= \^m_axi_awaddr\(447 downto 432);
m_axi_awaddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0);
m_axi_awburst(27) <= \<const0>\;
m_axi_awburst(26) <= \<const0>\;
m_axi_awburst(25) <= \<const0>\;
m_axi_awburst(24) <= \<const0>\;
m_axi_awburst(23) <= \<const0>\;
m_axi_awburst(22) <= \<const0>\;
m_axi_awburst(21) <= \<const0>\;
m_axi_awburst(20) <= \<const0>\;
m_axi_awburst(19) <= \<const0>\;
m_axi_awburst(18) <= \<const0>\;
m_axi_awburst(17) <= \<const0>\;
m_axi_awburst(16) <= \<const0>\;
m_axi_awburst(15) <= \<const0>\;
m_axi_awburst(14) <= \<const0>\;
m_axi_awburst(13) <= \<const0>\;
m_axi_awburst(12) <= \<const0>\;
m_axi_awburst(11) <= \<const0>\;
m_axi_awburst(10) <= \<const0>\;
m_axi_awburst(9) <= \<const0>\;
m_axi_awburst(8) <= \<const0>\;
m_axi_awburst(7) <= \<const0>\;
m_axi_awburst(6) <= \<const0>\;
m_axi_awburst(5) <= \<const0>\;
m_axi_awburst(4) <= \<const0>\;
m_axi_awburst(3) <= \<const0>\;
m_axi_awburst(2) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(55) <= \<const0>\;
m_axi_awcache(54) <= \<const0>\;
m_axi_awcache(53) <= \<const0>\;
m_axi_awcache(52) <= \<const0>\;
m_axi_awcache(51) <= \<const0>\;
m_axi_awcache(50) <= \<const0>\;
m_axi_awcache(49) <= \<const0>\;
m_axi_awcache(48) <= \<const0>\;
m_axi_awcache(47) <= \<const0>\;
m_axi_awcache(46) <= \<const0>\;
m_axi_awcache(45) <= \<const0>\;
m_axi_awcache(44) <= \<const0>\;
m_axi_awcache(43) <= \<const0>\;
m_axi_awcache(42) <= \<const0>\;
m_axi_awcache(41) <= \<const0>\;
m_axi_awcache(40) <= \<const0>\;
m_axi_awcache(39) <= \<const0>\;
m_axi_awcache(38) <= \<const0>\;
m_axi_awcache(37) <= \<const0>\;
m_axi_awcache(36) <= \<const0>\;
m_axi_awcache(35) <= \<const0>\;
m_axi_awcache(34) <= \<const0>\;
m_axi_awcache(33) <= \<const0>\;
m_axi_awcache(32) <= \<const0>\;
m_axi_awcache(31) <= \<const0>\;
m_axi_awcache(30) <= \<const0>\;
m_axi_awcache(29) <= \<const0>\;
m_axi_awcache(28) <= \<const0>\;
m_axi_awcache(27) <= \<const0>\;
m_axi_awcache(26) <= \<const0>\;
m_axi_awcache(25) <= \<const0>\;
m_axi_awcache(24) <= \<const0>\;
m_axi_awcache(23) <= \<const0>\;
m_axi_awcache(22) <= \<const0>\;
m_axi_awcache(21) <= \<const0>\;
m_axi_awcache(20) <= \<const0>\;
m_axi_awcache(19) <= \<const0>\;
m_axi_awcache(18) <= \<const0>\;
m_axi_awcache(17) <= \<const0>\;
m_axi_awcache(16) <= \<const0>\;
m_axi_awcache(15) <= \<const0>\;
m_axi_awcache(14) <= \<const0>\;
m_axi_awcache(13) <= \<const0>\;
m_axi_awcache(12) <= \<const0>\;
m_axi_awcache(11) <= \<const0>\;
m_axi_awcache(10) <= \<const0>\;
m_axi_awcache(9) <= \<const0>\;
m_axi_awcache(8) <= \<const0>\;
m_axi_awcache(7) <= \<const0>\;
m_axi_awcache(6) <= \<const0>\;
m_axi_awcache(5) <= \<const0>\;
m_axi_awcache(4) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(13) <= \<const0>\;
m_axi_awid(12) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(111) <= \<const0>\;
m_axi_awlen(110) <= \<const0>\;
m_axi_awlen(109) <= \<const0>\;
m_axi_awlen(108) <= \<const0>\;
m_axi_awlen(107) <= \<const0>\;
m_axi_awlen(106) <= \<const0>\;
m_axi_awlen(105) <= \<const0>\;
m_axi_awlen(104) <= \<const0>\;
m_axi_awlen(103) <= \<const0>\;
m_axi_awlen(102) <= \<const0>\;
m_axi_awlen(101) <= \<const0>\;
m_axi_awlen(100) <= \<const0>\;
m_axi_awlen(99) <= \<const0>\;
m_axi_awlen(98) <= \<const0>\;
m_axi_awlen(97) <= \<const0>\;
m_axi_awlen(96) <= \<const0>\;
m_axi_awlen(95) <= \<const0>\;
m_axi_awlen(94) <= \<const0>\;
m_axi_awlen(93) <= \<const0>\;
m_axi_awlen(92) <= \<const0>\;
m_axi_awlen(91) <= \<const0>\;
m_axi_awlen(90) <= \<const0>\;
m_axi_awlen(89) <= \<const0>\;
m_axi_awlen(88) <= \<const0>\;
m_axi_awlen(87) <= \<const0>\;
m_axi_awlen(86) <= \<const0>\;
m_axi_awlen(85) <= \<const0>\;
m_axi_awlen(84) <= \<const0>\;
m_axi_awlen(83) <= \<const0>\;
m_axi_awlen(82) <= \<const0>\;
m_axi_awlen(81) <= \<const0>\;
m_axi_awlen(80) <= \<const0>\;
m_axi_awlen(79) <= \<const0>\;
m_axi_awlen(78) <= \<const0>\;
m_axi_awlen(77) <= \<const0>\;
m_axi_awlen(76) <= \<const0>\;
m_axi_awlen(75) <= \<const0>\;
m_axi_awlen(74) <= \<const0>\;
m_axi_awlen(73) <= \<const0>\;
m_axi_awlen(72) <= \<const0>\;
m_axi_awlen(71) <= \<const0>\;
m_axi_awlen(70) <= \<const0>\;
m_axi_awlen(69) <= \<const0>\;
m_axi_awlen(68) <= \<const0>\;
m_axi_awlen(67) <= \<const0>\;
m_axi_awlen(66) <= \<const0>\;
m_axi_awlen(65) <= \<const0>\;
m_axi_awlen(64) <= \<const0>\;
m_axi_awlen(63) <= \<const0>\;
m_axi_awlen(62) <= \<const0>\;
m_axi_awlen(61) <= \<const0>\;
m_axi_awlen(60) <= \<const0>\;
m_axi_awlen(59) <= \<const0>\;
m_axi_awlen(58) <= \<const0>\;
m_axi_awlen(57) <= \<const0>\;
m_axi_awlen(56) <= \<const0>\;
m_axi_awlen(55) <= \<const0>\;
m_axi_awlen(54) <= \<const0>\;
m_axi_awlen(53) <= \<const0>\;
m_axi_awlen(52) <= \<const0>\;
m_axi_awlen(51) <= \<const0>\;
m_axi_awlen(50) <= \<const0>\;
m_axi_awlen(49) <= \<const0>\;
m_axi_awlen(48) <= \<const0>\;
m_axi_awlen(47) <= \<const0>\;
m_axi_awlen(46) <= \<const0>\;
m_axi_awlen(45) <= \<const0>\;
m_axi_awlen(44) <= \<const0>\;
m_axi_awlen(43) <= \<const0>\;
m_axi_awlen(42) <= \<const0>\;
m_axi_awlen(41) <= \<const0>\;
m_axi_awlen(40) <= \<const0>\;
m_axi_awlen(39) <= \<const0>\;
m_axi_awlen(38) <= \<const0>\;
m_axi_awlen(37) <= \<const0>\;
m_axi_awlen(36) <= \<const0>\;
m_axi_awlen(35) <= \<const0>\;
m_axi_awlen(34) <= \<const0>\;
m_axi_awlen(33) <= \<const0>\;
m_axi_awlen(32) <= \<const0>\;
m_axi_awlen(31) <= \<const0>\;
m_axi_awlen(30) <= \<const0>\;
m_axi_awlen(29) <= \<const0>\;
m_axi_awlen(28) <= \<const0>\;
m_axi_awlen(27) <= \<const0>\;
m_axi_awlen(26) <= \<const0>\;
m_axi_awlen(25) <= \<const0>\;
m_axi_awlen(24) <= \<const0>\;
m_axi_awlen(23) <= \<const0>\;
m_axi_awlen(22) <= \<const0>\;
m_axi_awlen(21) <= \<const0>\;
m_axi_awlen(20) <= \<const0>\;
m_axi_awlen(19) <= \<const0>\;
m_axi_awlen(18) <= \<const0>\;
m_axi_awlen(17) <= \<const0>\;
m_axi_awlen(16) <= \<const0>\;
m_axi_awlen(15) <= \<const0>\;
m_axi_awlen(14) <= \<const0>\;
m_axi_awlen(13) <= \<const0>\;
m_axi_awlen(12) <= \<const0>\;
m_axi_awlen(11) <= \<const0>\;
m_axi_awlen(10) <= \<const0>\;
m_axi_awlen(9) <= \<const0>\;
m_axi_awlen(8) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(13) <= \<const0>\;
m_axi_awlock(12) <= \<const0>\;
m_axi_awlock(11) <= \<const0>\;
m_axi_awlock(10) <= \<const0>\;
m_axi_awlock(9) <= \<const0>\;
m_axi_awlock(8) <= \<const0>\;
m_axi_awlock(7) <= \<const0>\;
m_axi_awlock(6) <= \<const0>\;
m_axi_awlock(5) <= \<const0>\;
m_axi_awlock(4) <= \<const0>\;
m_axi_awlock(3) <= \<const0>\;
m_axi_awlock(2) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(41 downto 39) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(38 downto 36) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(35 downto 33) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(32 downto 30) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(29 downto 27) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(26 downto 24) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(23 downto 21) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(20 downto 18) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(17 downto 15) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(14 downto 12) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(11 downto 9) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_awqos(55) <= \<const0>\;
m_axi_awqos(54) <= \<const0>\;
m_axi_awqos(53) <= \<const0>\;
m_axi_awqos(52) <= \<const0>\;
m_axi_awqos(51) <= \<const0>\;
m_axi_awqos(50) <= \<const0>\;
m_axi_awqos(49) <= \<const0>\;
m_axi_awqos(48) <= \<const0>\;
m_axi_awqos(47) <= \<const0>\;
m_axi_awqos(46) <= \<const0>\;
m_axi_awqos(45) <= \<const0>\;
m_axi_awqos(44) <= \<const0>\;
m_axi_awqos(43) <= \<const0>\;
m_axi_awqos(42) <= \<const0>\;
m_axi_awqos(41) <= \<const0>\;
m_axi_awqos(40) <= \<const0>\;
m_axi_awqos(39) <= \<const0>\;
m_axi_awqos(38) <= \<const0>\;
m_axi_awqos(37) <= \<const0>\;
m_axi_awqos(36) <= \<const0>\;
m_axi_awqos(35) <= \<const0>\;
m_axi_awqos(34) <= \<const0>\;
m_axi_awqos(33) <= \<const0>\;
m_axi_awqos(32) <= \<const0>\;
m_axi_awqos(31) <= \<const0>\;
m_axi_awqos(30) <= \<const0>\;
m_axi_awqos(29) <= \<const0>\;
m_axi_awqos(28) <= \<const0>\;
m_axi_awqos(27) <= \<const0>\;
m_axi_awqos(26) <= \<const0>\;
m_axi_awqos(25) <= \<const0>\;
m_axi_awqos(24) <= \<const0>\;
m_axi_awqos(23) <= \<const0>\;
m_axi_awqos(22) <= \<const0>\;
m_axi_awqos(21) <= \<const0>\;
m_axi_awqos(20) <= \<const0>\;
m_axi_awqos(19) <= \<const0>\;
m_axi_awqos(18) <= \<const0>\;
m_axi_awqos(17) <= \<const0>\;
m_axi_awqos(16) <= \<const0>\;
m_axi_awqos(15) <= \<const0>\;
m_axi_awqos(14) <= \<const0>\;
m_axi_awqos(13) <= \<const0>\;
m_axi_awqos(12) <= \<const0>\;
m_axi_awqos(11) <= \<const0>\;
m_axi_awqos(10) <= \<const0>\;
m_axi_awqos(9) <= \<const0>\;
m_axi_awqos(8) <= \<const0>\;
m_axi_awqos(7) <= \<const0>\;
m_axi_awqos(6) <= \<const0>\;
m_axi_awqos(5) <= \<const0>\;
m_axi_awqos(4) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(55) <= \<const0>\;
m_axi_awregion(54) <= \<const0>\;
m_axi_awregion(53) <= \<const0>\;
m_axi_awregion(52) <= \<const0>\;
m_axi_awregion(51) <= \<const0>\;
m_axi_awregion(50) <= \<const0>\;
m_axi_awregion(49) <= \<const0>\;
m_axi_awregion(48) <= \<const0>\;
m_axi_awregion(47) <= \<const0>\;
m_axi_awregion(46) <= \<const0>\;
m_axi_awregion(45) <= \<const0>\;
m_axi_awregion(44) <= \<const0>\;
m_axi_awregion(43) <= \<const0>\;
m_axi_awregion(42) <= \<const0>\;
m_axi_awregion(41) <= \<const0>\;
m_axi_awregion(40) <= \<const0>\;
m_axi_awregion(39) <= \<const0>\;
m_axi_awregion(38) <= \<const0>\;
m_axi_awregion(37) <= \<const0>\;
m_axi_awregion(36) <= \<const0>\;
m_axi_awregion(35) <= \<const0>\;
m_axi_awregion(34) <= \<const0>\;
m_axi_awregion(33) <= \<const0>\;
m_axi_awregion(32) <= \<const0>\;
m_axi_awregion(31) <= \<const0>\;
m_axi_awregion(30) <= \<const0>\;
m_axi_awregion(29) <= \<const0>\;
m_axi_awregion(28) <= \<const0>\;
m_axi_awregion(27) <= \<const0>\;
m_axi_awregion(26) <= \<const0>\;
m_axi_awregion(25) <= \<const0>\;
m_axi_awregion(24) <= \<const0>\;
m_axi_awregion(23) <= \<const0>\;
m_axi_awregion(22) <= \<const0>\;
m_axi_awregion(21) <= \<const0>\;
m_axi_awregion(20) <= \<const0>\;
m_axi_awregion(19) <= \<const0>\;
m_axi_awregion(18) <= \<const0>\;
m_axi_awregion(17) <= \<const0>\;
m_axi_awregion(16) <= \<const0>\;
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(41) <= \<const0>\;
m_axi_awsize(40) <= \<const0>\;
m_axi_awsize(39) <= \<const0>\;
m_axi_awsize(38) <= \<const0>\;
m_axi_awsize(37) <= \<const0>\;
m_axi_awsize(36) <= \<const0>\;
m_axi_awsize(35) <= \<const0>\;
m_axi_awsize(34) <= \<const0>\;
m_axi_awsize(33) <= \<const0>\;
m_axi_awsize(32) <= \<const0>\;
m_axi_awsize(31) <= \<const0>\;
m_axi_awsize(30) <= \<const0>\;
m_axi_awsize(29) <= \<const0>\;
m_axi_awsize(28) <= \<const0>\;
m_axi_awsize(27) <= \<const0>\;
m_axi_awsize(26) <= \<const0>\;
m_axi_awsize(25) <= \<const0>\;
m_axi_awsize(24) <= \<const0>\;
m_axi_awsize(23) <= \<const0>\;
m_axi_awsize(22) <= \<const0>\;
m_axi_awsize(21) <= \<const0>\;
m_axi_awsize(20) <= \<const0>\;
m_axi_awsize(19) <= \<const0>\;
m_axi_awsize(18) <= \<const0>\;
m_axi_awsize(17) <= \<const0>\;
m_axi_awsize(16) <= \<const0>\;
m_axi_awsize(15) <= \<const0>\;
m_axi_awsize(14) <= \<const0>\;
m_axi_awsize(13) <= \<const0>\;
m_axi_awsize(12) <= \<const0>\;
m_axi_awsize(11) <= \<const0>\;
m_axi_awsize(10) <= \<const0>\;
m_axi_awsize(9) <= \<const0>\;
m_axi_awsize(8) <= \<const0>\;
m_axi_awsize(7) <= \<const0>\;
m_axi_awsize(6) <= \<const0>\;
m_axi_awsize(5) <= \<const0>\;
m_axi_awsize(4) <= \<const0>\;
m_axi_awsize(3) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(13) <= \<const0>\;
m_axi_awuser(12) <= \<const0>\;
m_axi_awuser(11) <= \<const0>\;
m_axi_awuser(10) <= \<const0>\;
m_axi_awuser(9) <= \<const0>\;
m_axi_awuser(8) <= \<const0>\;
m_axi_awuser(7) <= \<const0>\;
m_axi_awuser(6) <= \<const0>\;
m_axi_awuser(5) <= \<const0>\;
m_axi_awuser(4) <= \<const0>\;
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid(13 downto 11) <= \^m_axi_awvalid\(13 downto 11);
m_axi_awvalid(10) <= \<const0>\;
m_axi_awvalid(9 downto 0) <= \^m_axi_awvalid\(9 downto 0);
m_axi_bready(13 downto 11) <= \^m_axi_bready\(13 downto 11);
m_axi_bready(10) <= \<const0>\;
m_axi_bready(9 downto 0) <= \^m_axi_bready\(9 downto 0);
m_axi_rready(13 downto 11) <= \^m_axi_rready\(13 downto 11);
m_axi_rready(10) <= \<const0>\;
m_axi_rready(9 downto 0) <= \^m_axi_rready\(9 downto 0);
m_axi_wdata(447 downto 416) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(415 downto 384) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(383 downto 352) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(351 downto 320) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(319 downto 288) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(287 downto 256) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(255 downto 224) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(223 downto 192) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(191 downto 160) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(159 downto 128) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(13) <= \<const0>\;
m_axi_wlast(12) <= \<const0>\;
m_axi_wlast(11) <= \<const0>\;
m_axi_wlast(10) <= \<const0>\;
m_axi_wlast(9) <= \<const0>\;
m_axi_wlast(8) <= \<const0>\;
m_axi_wlast(7) <= \<const0>\;
m_axi_wlast(6) <= \<const0>\;
m_axi_wlast(5) <= \<const0>\;
m_axi_wlast(4) <= \<const0>\;
m_axi_wlast(3) <= \<const0>\;
m_axi_wlast(2) <= \<const0>\;
m_axi_wlast(1) <= \<const0>\;
m_axi_wlast(0) <= \<const0>\;
m_axi_wstrb(55 downto 52) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(51 downto 48) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(47 downto 44) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(43 downto 40) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(39 downto 36) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(35 downto 32) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(31 downto 28) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(27 downto 24) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(23 downto 20) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(19 downto 16) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(13) <= \<const0>\;
m_axi_wuser(12) <= \<const0>\;
m_axi_wuser(11) <= \<const0>\;
m_axi_wuser(10) <= \<const0>\;
m_axi_wuser(9) <= \<const0>\;
m_axi_wuser(8) <= \<const0>\;
m_axi_wuser(7) <= \<const0>\;
m_axi_wuser(6) <= \<const0>\;
m_axi_wuser(5) <= \<const0>\;
m_axi_wuser(4) <= \<const0>\;
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid(13 downto 11) <= \^m_axi_wvalid\(13 downto 11);
m_axi_wvalid(10) <= \<const0>\;
m_axi_wvalid(9 downto 0) <= \^m_axi_wvalid\(9 downto 0);
s_axi_bid(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_sasd.crossbar_sasd_0\: entity work.system_xbar_1_axi_crossbar_v2_1_12_crossbar_sasd
port map (
Q(34 downto 32) => \^m_axi_arprot\(2 downto 0),
Q(31 downto 16) => \^m_axi_awaddr\(447 downto 432),
Q(15 downto 0) => \^m_axi_araddr\(15 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_arready(13 downto 0) => m_axi_arready(13 downto 0),
m_axi_arvalid(12 downto 10) => \^m_axi_arvalid\(13 downto 11),
m_axi_arvalid(9 downto 0) => \^m_axi_arvalid\(9 downto 0),
m_axi_awready(13 downto 0) => m_axi_awready(13 downto 0),
m_axi_awvalid(12 downto 10) => \^m_axi_awvalid\(13 downto 11),
m_axi_awvalid(9 downto 0) => \^m_axi_awvalid\(9 downto 0),
m_axi_bready(12 downto 10) => \^m_axi_bready\(13 downto 11),
m_axi_bready(9 downto 0) => \^m_axi_bready\(9 downto 0),
m_axi_bresp(27 downto 0) => m_axi_bresp(27 downto 0),
m_axi_bvalid(13 downto 0) => m_axi_bvalid(13 downto 0),
m_axi_rdata(447 downto 0) => m_axi_rdata(447 downto 0),
m_axi_rready(12 downto 10) => \^m_axi_rready\(13 downto 11),
m_axi_rready(9 downto 0) => \^m_axi_rready\(9 downto 0),
m_axi_rresp(27 downto 0) => m_axi_rresp(27 downto 0),
m_axi_rvalid(13 downto 0) => m_axi_rvalid(13 downto 0),
m_axi_wready(13 downto 0) => m_axi_wready(13 downto 0),
m_axi_wvalid(12 downto 10) => \^m_axi_wvalid\(13 downto 11),
m_axi_wvalid(9 downto 0) => \^m_axi_wvalid\(9 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
\s_axi_rdata[31]\(33 downto 2) => s_axi_rdata(31 downto 0),
\s_axi_rdata[31]\(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 55 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 41 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 447 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xbar_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_xbar_1 : entity is "system_xbar_1,axi_crossbar_v2_1_12_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_xbar_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_xbar_1 : entity is "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4";
end system_xbar_1;
architecture STRUCTURE of system_xbar_1 is
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 55 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 111 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 55 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 55 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 41 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 55 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 111 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 55 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 55 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 41 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "448'b0000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "896'b00000000000000000000000000000000010001001010001000000000000000000000000000000000000000000000000001000000000001000000000000000000000000000000000000000000000000000100000000000011000000000000000011111111111111111111111111111111111111111111111111111111111111110000000000000000000000000000000001000000000000100000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000100000000000000000000000000000000000000000000000000000000100010010100001000000000000000000000000000000000000000000000000010001001010000000000000000000000000000000000000000000000000000001000000011000000000000000000000000000000000000000000000000000000100000111000000000000000000000000000000000000000000000000000000010000001110000000000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "448'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "448'b0000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 14;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "artix7";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "448'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "14'b11111111111111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "14'b11111111111111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.system_xbar_1_axi_crossbar_v2_1_12_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(447 downto 0) => m_axi_araddr(447 downto 0),
m_axi_arburst(27 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(27 downto 0),
m_axi_arcache(55 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(55 downto 0),
m_axi_arid(13 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(13 downto 0),
m_axi_arlen(111 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(111 downto 0),
m_axi_arlock(13 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(13 downto 0),
m_axi_arprot(41 downto 0) => m_axi_arprot(41 downto 0),
m_axi_arqos(55 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(55 downto 0),
m_axi_arready(13 downto 0) => m_axi_arready(13 downto 0),
m_axi_arregion(55 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(55 downto 0),
m_axi_arsize(41 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(41 downto 0),
m_axi_aruser(13 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(13 downto 0),
m_axi_arvalid(13 downto 0) => m_axi_arvalid(13 downto 0),
m_axi_awaddr(447 downto 0) => m_axi_awaddr(447 downto 0),
m_axi_awburst(27 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(27 downto 0),
m_axi_awcache(55 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(55 downto 0),
m_axi_awid(13 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(13 downto 0),
m_axi_awlen(111 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(111 downto 0),
m_axi_awlock(13 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(13 downto 0),
m_axi_awprot(41 downto 0) => m_axi_awprot(41 downto 0),
m_axi_awqos(55 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(55 downto 0),
m_axi_awready(13 downto 0) => m_axi_awready(13 downto 0),
m_axi_awregion(55 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(55 downto 0),
m_axi_awsize(41 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(41 downto 0),
m_axi_awuser(13 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(13 downto 0),
m_axi_awvalid(13 downto 0) => m_axi_awvalid(13 downto 0),
m_axi_bid(13 downto 0) => B"00000000000000",
m_axi_bready(13 downto 0) => m_axi_bready(13 downto 0),
m_axi_bresp(27 downto 0) => m_axi_bresp(27 downto 0),
m_axi_buser(13 downto 0) => B"00000000000000",
m_axi_bvalid(13 downto 0) => m_axi_bvalid(13 downto 0),
m_axi_rdata(447 downto 0) => m_axi_rdata(447 downto 0),
m_axi_rid(13 downto 0) => B"00000000000000",
m_axi_rlast(13 downto 0) => B"11111111111111",
m_axi_rready(13 downto 0) => m_axi_rready(13 downto 0),
m_axi_rresp(27 downto 0) => m_axi_rresp(27 downto 0),
m_axi_ruser(13 downto 0) => B"00000000000000",
m_axi_rvalid(13 downto 0) => m_axi_rvalid(13 downto 0),
m_axi_wdata(447 downto 0) => m_axi_wdata(447 downto 0),
m_axi_wid(13 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(13 downto 0),
m_axi_wlast(13 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(13 downto 0),
m_axi_wready(13 downto 0) => m_axi_wready(13 downto 0),
m_axi_wstrb(55 downto 0) => m_axi_wstrb(55 downto 0),
m_axi_wuser(13 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(13 downto 0),
m_axi_wvalid(13 downto 0) => m_axi_wvalid(13 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast(0) => NLW_inst_s_axi_rlast_UNCONNECTED(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast(0) => '1',
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
|
apache-2.0
|
62f60ed31d1b723813c2ac02e27c38ed
| 0.544888 | 2.640281 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_timer_0_0/sim/system_axi_timer_0_0.vhd
| 1 | 8,488 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0_13;
USE axi_timer_v2_0_13.axi_timer;
ENTITY system_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END system_axi_timer_0_0;
ARCHITECTURE system_axi_timer_0_0_arch OF system_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "artix7",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END system_axi_timer_0_0_arch;
|
apache-2.0
|
4b8f162a4c953ba0b8b948a0532f956c
| 0.68532 | 3.352291 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/i2s_pkg.vhd
| 1 | 2,293 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/27/2016
-- Design Name: i2s_pkg.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This I2S package contains a
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Added sinus lookup table creation
------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package i2s_pkg is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant c_addr : integer := 12;
type t_i2s_in is record
l_channel : std_logic_vector(23 downto 0);
r_channel : std_logic_vector(23 downto 0);
end record;
type t_i2s_out is record
wclk : std_ulogic;
bclk : std_ulogic;
sdata : std_logic;
end record;
type mem_array is array(0 to (2**c_addr)-1) of std_logic_vector(23 downto 0);
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function cos_lut
return mem_array;
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component i2s_tx
port (
reset_n : in std_logic;
mclk : in std_logic;
--
i2s_in : in t_i2s_in;
i2s_out : out t_i2s_out
);
end component;
end i2s_pkg;
package body i2s_pkg is
function cos_lut
return mem_array is
constant N : integer := 2**c_addr;
constant N1 : real := real(N);
variable w, k1 : real;
variable memx : mem_array;
begin
for k in 0 to N-1 loop
k1 := (real(k)+0.5)/N1;
w := cos(math_pi_over_2 * k1); -- first quadrant of cosine wave
memx(k) := std_logic_vector(conv_signed(integer(round(8388608.0*w)),24));
end loop;
return memx;
end function cos_lut;
end;
|
gpl-3.0
|
692bba300c4ba8fcc0d310177466ee26
| 0.444396 | 3.967128 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/InstructionMemory_tb.vhd
| 1 | 1,509 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY InstructionMemory_tb IS
END InstructionMemory_tb;
ARCHITECTURE behavior OF InstructionMemory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT InstructionMemory
PORT(
Address : IN std_logic_vector(5 downto 0);
rst: IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Address : std_logic_vector(5 downto 0) := (others => '0');
signal rst : std_logic:= '0';
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: InstructionMemory PORT MAP (
Address => Address,
rst => rst,
Instruction => Instruction
);
-- Stimulus process
stim_proc: process
begin
rst<='0';
Address<=(others=>'0');
wait for 20 ns;
Address<="000001";
wait for 40 ns;
Address<="000010";
wait for 40 ns;
Address<="000011";
wait for 40 ns;
Address<="000100";
wait for 40 ns;
Address<="000101";
wait for 40 ns;
Address<="000110";
wait for 40 ns;
Address<="000111";
wait for 40 ns;
Address<="001000";
wait for 40 ns;
Address<="001001";
wait for 40 ns;
Address<="001010";
wait for 40 ns;
rst<='1';
Address<="000001";
wait for 40 ns;
Address<="000100";
wait;
end process;
END;
|
mit
|
8ad9cc86dcabc198ea89556afb9c3302
| 0.575878 | 3.909326 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/clock_generator_0_wrapper.vhd
| 1 | 3,230 |
-------------------------------------------------------------------------------
-- clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_0_v4_03_a;
use clock_generator_0_v4_03_a.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of clock_generator_0_wrapper : entity is "clock_generator_v4_03_a";
end clock_generator_0_wrapper;
architecture STRUCTURE of clock_generator_0_wrapper is
component clock_generator is
generic (
C_FAMILY : STRING;
C_DEVICE : STRING;
C_PACKAGE : STRING;
C_SPEEDGRADE : STRING
);
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
begin
clock_generator_0 : clock_generator
generic map (
C_FAMILY => "spartan6",
C_DEVICE => "6slx150t",
C_PACKAGE => "fgg676",
C_SPEEDGRADE => "-3"
)
port map (
CLKIN => CLKIN,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1,
CLKOUT2 => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
CLKOUT6 => CLKOUT6,
CLKOUT7 => CLKOUT7,
CLKOUT8 => CLKOUT8,
CLKOUT9 => CLKOUT9,
CLKOUT10 => CLKOUT10,
CLKOUT11 => CLKOUT11,
CLKOUT12 => CLKOUT12,
CLKOUT13 => CLKOUT13,
CLKOUT14 => CLKOUT14,
CLKOUT15 => CLKOUT15,
CLKFBIN => CLKFBIN,
CLKFBOUT => CLKFBOUT,
PSCLK => PSCLK,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
PSDONE => PSDONE,
RST => RST,
LOCKED => LOCKED
);
end architecture STRUCTURE;
|
gpl-2.0
|
bb24fc842feea927156ab6ad8cd7d23f
| 0.573065 | 3.641488 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/MODULOPRINCIPAL.vhd
| 1 | 10,826 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MODULOPRINCIPAL is
Port ( rst : in STD_LOGIC;
CLK : in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end MODULOPRINCIPAL;
architecture Behavioral of MODULOPRINCIPAL is
COMPONENT PC
PORT(
rst : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
DataOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Sumador32bits
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT InstructionMemory
PORT(
Address : IN std_logic_vector(5 downto 0);
rst : IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
WE : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0);
Crd : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
OP : IN std_logic_vector(1 downto 0);
OP2 : IN std_logic_vector(2 downto 0);
Cond : IN std_logic_vector(3 downto 0);
icc : IN std_logic_vector(3 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
WE : OUT std_logic;
RFDEST : OUT std_logic;
RFSOURCE : OUT std_logic_vector(1 downto 0);
WRENMEM : OUT std_logic;
--RDENMEM : OUT std_logic;
PCSOURCE : OUT std_logic_vector(1 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT PSRModifier
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Oper1 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
NZVC : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT PSR
PORT(
NZVC : IN std_logic_vector(3 downto 0);
nCWP : IN std_logic;
CLK : IN std_logic;
rst : IN std_logic;
icc : OUT std_logic_vector(3 downto 0);
CWP : OUT std_logic;
C : OUT std_logic
);
END COMPONENT;
COMPONENT WindowsManager
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic;
nRs1 : OUT std_logic_vector(5 downto 0);
nRs2 : OUT std_logic_vector(5 downto 0);
nRd : OUT std_logic_vector(5 downto 0);
nCWP : OUT std_logic
);
END COMPONENT;
COMPONENT DataMemory
PORT(
Crd : IN std_logic_vector(31 downto 0);
Address : IN std_logic_vector(31 downto 0);
WRENMEM : IN std_logic;
--RDENMEM : IN std_logic;
DATATOMEM : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT MUX_PCSOURCE
PORT(
PCdisp30 : IN std_logic_vector(31 downto 0);
PCSEUdisp22 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
PC : IN std_logic_vector(31 downto 0);
PCSOURCE : IN std_logic_vector(1 downto 0);
nPC : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT MUX_RFDEST
PORT(
RD : IN std_logic_vector(5 downto 0);
RFDEST : IN std_logic;
nRD : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT MUX_RFSOURCE
PORT(
RFSOURCE : IN std_logic_vector(1 downto 0);
DATATOMEM : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
PC : IN std_logic_vector(31 downto 0);
DATATOREG : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT SEUdisp22
PORT(
disp22 : IN std_logic_vector(21 downto 0);
SEUdisp22 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT SEUdisp30
PORT(
disp30 : IN std_logic_vector(29 downto 0);
SEUdisp30 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal B0:std_logic_vector(31 downto 0);--Result: conecta al sumador32bits con el PC(entrada) de MUXPCSOURCE
signal B1:std_logic_vector(31 downto 0);--DataOut(nPC): conecta al nPC con el DataIn de PC
signal B2:std_logic_vector(31 downto 0);--DataOut(PC): conecta al PC con el address del IM, con el Oper1 de sumador32bitsdisp22 y con el Oper2 de sumador32bitsdisp30
signal B3:std_logic_vector(31 downto 0);--Instruction: conecta al IM con el CU(OP(31-30),OP3(24-19),Cond(28-25)),WindowManager(rs1(18-14),rs2(4-0),rd(29-25)),
--SEU(12-0),OMUXT(13), SEUdisp22(21-0) y sumador32bitsdisp30(29-0)
signal B4:std_logic_vector(5 downto 0); --ALUOP: conecta a CU y a la ALU
signal B5:std_logic_vector(31 downto 0);--ALURESULT: conecta a la ALU con el Address del DataMemory, con el ALURESULT de MUXRFSOURCE y con el ALURESULT de MUXPCSOURCE, es la salida del Modulo Principal
signal B6:std_logic_vector(31 downto 0);--Crs1: conecta al RF con Oper1 de la ALU
signal B7:std_logic_vector(31 downto 0);--Crs2: conecta al RF con OMUXT
signal B8:std_logic_vector(31 downto 0);--SEUimm: conecta a SEU con OMUXT
signal B9:std_logic_vector(31 downto 0);--Oper2: conecta a OMUXT con el Oper2 de la ALU
signal B10: std_logic; --Carry: conecta al PSR y a la ALU
signal B11: std_logic_vector(3 downto 0);--NZVC: conecta al PSRModifier con el PSR
signal B12: std_logic_vector(17 downto 0);--InstructionWM: conecta al Windows Manager con el RegisterFile(rs1(17-12),rs2(11-6)) y MUXRFDEST(RD(5-0))
signal B13: std_logic;--CWP: conecta al PSR con el WindowsManager
signal B14: std_logic;--nCWP: conecta al WindowsManager con el PSR
signal B15: std_logic_vector(5 downto 0);--rd(nRD): conecta al MUXRFDEST con el rd del Register File
signal B16: std_logic_vector(31 downto 0);--SEUdisp22(entrada): conecta al SEUdisp22(Modulo) con el Oper2 de sumador32bitsdisp22
signal B17: std_logic_vector(31 downto 0);--Result: conecta al sumador32bitsdisp30 con el PCdisp30 de MUXPCSOURCE
signal B18: std_logic_vector(31 downto 0);--Result: conecta al sumador32bitsdisp22 con el PCSEUdisp22 del MUXPCSOURCE
signal B19: std_logic;--RFDEST: conecta a la UC con el RFDEST DE MUXRFDEST
signal B20: std_logic_vector(1 downto 0);--RFSOURCE: conecta a la UC con el RFSOURCE de MUXRFSOURCE
signal B21: std_logic;--WRENMEM conecta a la UC con el WRENMEM del DataMemory;
signal B22: std_logic_vector(31 downto 0);----SEUdisp30(entrada): conecta al SEUdisp30(Modulo) con el Oper2 de sumador32bitsdisp30
signal B23: std_logic;--WE: conecta a la UC con el WE del Register File
signal B24: std_logic_vector(31 downto 0);--Crd: conecta al Register File con el Crd del DataMemory
signal B25: std_logic_vector(31 downto 0);--DATATOMEM: conecta al DataMemory con el DATATOMEM del MUXRFSOURCE
signal B26: std_logic_vector(31 downto 0);--DATATOREG: conecta al MUXRFSOURCE con el DWR del Register File
signal B27: std_logic_vector(3 downto 0); --icc: Conecta al PSR con el icc de la UC
signal B28: std_logic_vector(1 downto 0);--PCSOURCE: conecta a la UC con el PCSOURCE DE MUXPCSOURCE
signal B29: std_logic_vector(31 downto 0);--nPC(Salida): Conecta al MUXPCSOURCE con el nPC(Modulo)
begin
Inst_PC: PC PORT MAP(
rst => rst,
dataIn => B1,
CLK => CLK,
DataOut => B2
);
Inst_Sumador32bitsdisp30: Sumador32bits PORT MAP(
Oper1 => B22,
Oper2 => B2,
Result => B17
);
Inst_Sumador32bitsdisp22: Sumador32bits PORT MAP(
Oper1 => B2,
Oper2 => B16,
Result => B18
);
Inst_Sumador32bits: Sumador32bits PORT MAP(
Oper1 => "00000000000000000000000000000001",
Oper2 => B1,
Result => B0
);
Inst_nPC: PC PORT MAP(
rst => rst,
CLK => CLK,
DataIn => B29,
DataOut => B1
);
Inst_InstructionMemory: InstructionMemory PORT MAP(
Address => B2(5 downto 0),
rst => rst,
Instruction =>B3
);
Inst_OMUXT: OMUXT PORT MAP(
Crs2 => B7,
SEUimm => B8,
i => B3(13),
oper2 => B9
);
Inst_RF: RF PORT MAP(
rs1 => B12(17 downto 12),
rs2 => B12(11 downto 6),
rd => B15,
DWR => B26,
rst => rst,
WE => B23,
Crs1 => B6,
Crs2 => B7,
Crd => B24
);
Inst_SEU: SEU PORT MAP(
imm13 => B3(12 downto 0),
SEUimm => B8
);
Inst_SEUdisp22: SEUdisp22 PORT MAP(
disp22 => B3(21 downto 0),
SEUdisp22 => B16
);
Inst_SEUdisp30: SEUdisp30 PORT MAP(
disp30 => B3(29 downto 0),
SEUdisp30 => B22
);
Inst_ALU: ALU PORT MAP(
Oper1 => B6,
Oper2 => B9,
ALUOP => B4,
C => B10,
ALURESULT => B5
);
Inst_CU: CU PORT MAP(
OP => B3(31 downto 30),
OP2 => B3(24 downto 22),
Cond => B3(28 downto 25),
icc => B27,
OP3 => B3(24 downto 19) ,
WE => B23,
RFDEST => B19,
RFSOURCE => B20,
WRENMEM => B21,
--RDENMEM => B22,
PCSOURCE => B28,
ALUOP => B4
);
Inst_PSRModifier: PSRModifier PORT MAP(
ALUOP => B4,
Oper2 => B9,
Oper1 => B6,
ALURESULT => B5,
NZVC => B11
);
Inst_PSR: PSR PORT MAP(
NZVC => B11,
nCWP => B14,
CLK => CLK,
rst => rst,
icc => B27,
CWP => B13,
C => B10
);
Inst_WindowsManager: WindowsManager PORT MAP(
rs1 => B3(18 downto 14),
rs2 => B3(4 downto 0),
rd => B3(29 downto 25),
op => B3(31 downto 30),
op3 =>B3(24 downto 19) ,
CWP => B13,
nRs1 => B12(17 downto 12),
nRs2 => B12(11 downto 6),
nRd => B12(5 downto 0),
nCWP => B14
);
Inst_DataMemory: DataMemory PORT MAP(
Crd => B24,
Address => B5,
WRENMEM => B21,
--RDENMEM => B22,
DATATOMEM => B25
);
Inst_MUX_PCSOURCE: MUX_PCSOURCE PORT MAP(
PCdisp30 => B17,
PCSEUdisp22 => B18,
ALURESULT => B5,
PC => B0,
PCSOURCE => B28,
nPC => B29
);
Inst_MUX_RFDEST: MUX_RFDEST PORT MAP(
RD => B12(5 downto 0),
RFDEST => B19,
nRD => B15
);
Inst_MUX_RFSOURCE: MUX_RFSOURCE PORT MAP(
RFSOURCE => B20,
DATATOMEM => B25,
ALURESULT => B5,
PC => B2,
DATATOREG => B26
);
ALURESULT<=B5;
end Behavioral;
|
mit
|
9aa0aebba820cb06994f7c2f56d7babe
| 0.640772 | 3.026559 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/principal_tb.vhd
| 1 | 1,155 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY principal_tb IS
END principal_tb;
ARCHITECTURE behavior OF principal_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MODULOPRINCIPAL
PORT(
rst : IN std_logic;
CLK : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MODULOPRINCIPAL PORT MAP (
rst => rst,
CLK => CLK,
ALURESULT => ALURESULT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 10 ns;
rst<='0';
--wait for 50 ms;
--rst<='1';
wait;
end process;
END;
|
mit
|
7764fc50e713d48afd6c8593034993d5
| 0.553247 | 3.915254 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_sim_netlist.vhdl
| 1 | 136,743 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:50 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_sim_netlist.vhdl
-- Design : system_axi_gpio_led_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_reg : in STD_LOGIC;
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_led_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_led_0_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[10]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[11]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[5]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[9]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[3]_i_1\ : label is "soft_lutpair3";
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(11),
I1 => \Dual.gpio2_Data_In_reg[0]\(11),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(0)
);
\Dual.READ_REG2_GEN[10].GPIO2_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(1),
I1 => \Dual.gpio2_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(10)
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => gpio_xferAck_Reg,
I2 => bus2ip_rnw_i_reg,
I3 => GPIO_xferAck_i,
O => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(0),
I1 => \Dual.gpio2_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(11)
);
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(10),
I1 => \Dual.gpio2_Data_In_reg[0]\(10),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(1)
);
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(9),
I1 => \Dual.gpio2_Data_In_reg[0]\(9),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(2)
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(8),
I1 => \Dual.gpio2_Data_In_reg[0]\(8),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(3)
);
\Dual.READ_REG2_GEN[4].GPIO2_DBus_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(7),
I1 => \Dual.gpio2_Data_In_reg[0]\(7),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(4)
);
\Dual.READ_REG2_GEN[5].GPIO2_DBus_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(6),
I1 => \Dual.gpio2_Data_In_reg[0]\(6),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(5)
);
\Dual.READ_REG2_GEN[6].GPIO2_DBus_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(5),
I1 => \Dual.gpio2_Data_In_reg[0]\(5),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(6)
);
\Dual.READ_REG2_GEN[7].GPIO2_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(4),
I1 => \Dual.gpio2_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(7)
);
\Dual.READ_REG2_GEN[8].GPIO2_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(3),
I1 => \Dual.gpio2_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(8)
);
\Dual.READ_REG2_GEN[9].GPIO2_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(2),
I1 => \Dual.gpio2_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(9)
);
\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(0)
);
\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(1)
);
\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(2)
);
\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(3)
);
\Dual.gpio2_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00001000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio2_Data_Out_reg[0]\(0)
);
\Dual.gpio2_Data_Out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(1),
O => D(1)
);
\Dual.gpio2_Data_Out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(0),
O => D(0)
);
\Dual.gpio2_Data_Out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(7),
O => D(7)
);
\Dual.gpio2_Data_Out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(6),
O => D(6)
);
\Dual.gpio2_Data_Out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(5),
O => D(5)
);
\Dual.gpio2_Data_Out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(4),
O => D(4)
);
\Dual.gpio2_Data_Out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(3),
O => D(3)
);
\Dual.gpio2_Data_Out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(2),
O => D(2)
);
\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF10000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio2_OE_reg[0]\(0)
);
\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio_Data_Out_reg[0]\(0)
);
\Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(11),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(3),
O => D(11)
);
\Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(10),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(2),
O => D(10)
);
\Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(9),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(1),
O => D(9)
);
\Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(8),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(0),
O => D(8)
);
\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00040000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => rst_reg,
O => E(0)
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000E0000"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2,
I2 => \^s_axi_wready\,
I3 => \^s_axi_arready\,
I4 => s_axi_aresetn,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\ip2bus_data_i_D1[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(11),
O => \ip2bus_data_i_D1_reg[20]\(11)
);
\ip2bus_data_i_D1[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(10),
O => \ip2bus_data_i_D1_reg[20]\(10)
);
\ip2bus_data_i_D1[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(9),
O => \ip2bus_data_i_D1_reg[20]\(9)
);
\ip2bus_data_i_D1[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(8),
O => \ip2bus_data_i_D1_reg[20]\(8)
);
\ip2bus_data_i_D1[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(7),
O => \ip2bus_data_i_D1_reg[20]\(7)
);
\ip2bus_data_i_D1[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(6),
O => \ip2bus_data_i_D1_reg[20]\(6)
);
\ip2bus_data_i_D1[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(5),
O => \ip2bus_data_i_D1_reg[20]\(5)
);
\ip2bus_data_i_D1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(4),
O => \ip2bus_data_i_D1_reg[20]\(4)
);
\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(3),
O => \ip2bus_data_i_D1_reg[20]\(3)
);
\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(2),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(2),
O => \ip2bus_data_i_D1_reg[20]\(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(1),
O => \ip2bus_data_i_D1_reg[20]\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(0),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(0),
O => \ip2bus_data_i_D1_reg[20]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_led_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_led_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_gpio_led_0_cdc_sync__parameterized0\ is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_gpio_led_0_cdc_sync__parameterized0\ : entity is "cdc_sync";
end \system_axi_gpio_led_0_cdc_sync__parameterized0\;
architecture STRUCTURE of \system_axi_gpio_led_0_cdc_sync__parameterized0\ is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_10 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_11 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_8 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_9 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_10 : STD_LOGIC;
signal s_level_out_bus_d2_11 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d2_8 : STD_LOGIC;
signal s_level_out_bus_d2_9 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_10 : STD_LOGIC;
signal s_level_out_bus_d3_11 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
signal s_level_out_bus_d3_8 : STD_LOGIC;
signal s_level_out_bus_d3_9 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_10,
Q => s_level_out_bus_d2_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_11,
Q => s_level_out_bus_d2_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_8,
Q => s_level_out_bus_d2_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_9,
Q => s_level_out_bus_d2_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_10,
Q => s_level_out_bus_d3_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_11,
Q => s_level_out_bus_d3_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_8,
Q => s_level_out_bus_d3_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_9,
Q => s_level_out_bus_d3_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_10,
Q => scndry_vect_out(10),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_11,
Q => scndry_vect_out(11),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_8,
Q => scndry_vect_out(8),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_9,
Q => scndry_vect_out(9),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(10),
Q => s_level_out_bus_d1_cdc_to_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(11),
Q => s_level_out_bus_d1_cdc_to_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(8),
Q => s_level_out_bus_d1_cdc_to_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(9),
Q => s_level_out_bus_d1_cdc_to_9,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_GPIO_Core is
port (
GPIO2_DBus_i : out STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
Read_Reg2_In : in STD_LOGIC_VECTOR ( 0 to 11 );
s_axi_aclk : in STD_LOGIC;
Read_Reg_In : in STD_LOGIC_VECTOR ( 0 to 3 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_led_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_led_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal gpio2_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 11 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 3 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair9";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Dual.INPUT_DOUBLE_REGS4\: entity work.system_axi_gpio_led_0_cdc_sync
port map (
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(3) => gpio_io_i_d2(0),
scndry_vect_out(2) => gpio_io_i_d2(1),
scndry_vect_out(1) => gpio_io_i_d2(2),
scndry_vect_out(0) => gpio_io_i_d2(3)
);
\Dual.INPUT_DOUBLE_REGS5\: entity work.\system_axi_gpio_led_0_cdc_sync__parameterized0\
port map (
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(11) => gpio2_io_i_d2(0),
scndry_vect_out(10) => gpio2_io_i_d2(1),
scndry_vect_out(9) => gpio2_io_i_d2(2),
scndry_vect_out(8) => gpio2_io_i_d2(3),
scndry_vect_out(7) => gpio2_io_i_d2(4),
scndry_vect_out(6) => gpio2_io_i_d2(5),
scndry_vect_out(5) => gpio2_io_i_d2(6),
scndry_vect_out(4) => gpio2_io_i_d2(7),
scndry_vect_out(3) => gpio2_io_i_d2(8),
scndry_vect_out(2) => gpio2_io_i_d2(9),
scndry_vect_out(1) => gpio2_io_i_d2(10),
scndry_vect_out(0) => gpio2_io_i_d2(11)
);
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(0),
Q => GPIO2_DBus_i(11),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[10].GPIO2_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(10),
Q => GPIO2_DBus_i(1),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(11),
Q => GPIO2_DBus_i(0),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(1),
Q => GPIO2_DBus_i(10),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(2),
Q => GPIO2_DBus_i(9),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(3),
Q => GPIO2_DBus_i(8),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[4].GPIO2_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(4),
Q => GPIO2_DBus_i(7),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[5].GPIO2_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(5),
Q => GPIO2_DBus_i(6),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[6].GPIO2_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(6),
Q => GPIO2_DBus_i(5),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[7].GPIO2_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(7),
Q => GPIO2_DBus_i(4),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[8].GPIO2_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(8),
Q => GPIO2_DBus_i(3),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[9].GPIO2_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(9),
Q => GPIO2_DBus_i(2),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(0),
Q => GPIO_DBus_i(3),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(1),
Q => GPIO_DBus_i(2),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(2),
Q => GPIO_DBus_i(1),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(3),
Q => GPIO_DBus_i(0),
R => Read_Reg_Rst
);
\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(0),
Q => Q(11),
R => '0'
);
\Dual.gpio2_Data_In_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(10),
Q => Q(1),
R => '0'
);
\Dual.gpio2_Data_In_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(11),
Q => Q(0),
R => '0'
);
\Dual.gpio2_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(1),
Q => Q(10),
R => '0'
);
\Dual.gpio2_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(2),
Q => Q(9),
R => '0'
);
\Dual.gpio2_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(3),
Q => Q(8),
R => '0'
);
\Dual.gpio2_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(4),
Q => Q(7),
R => '0'
);
\Dual.gpio2_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(5),
Q => Q(6),
R => '0'
);
\Dual.gpio2_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(6),
Q => Q(5),
R => '0'
);
\Dual.gpio2_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(7),
Q => Q(4),
R => '0'
);
\Dual.gpio2_Data_In_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(8),
Q => Q(3),
R => '0'
);
\Dual.gpio2_Data_In_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(9),
Q => Q(2),
R => '0'
);
\Dual.gpio2_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(11),
Q => gpio2_io_o(11),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(1),
Q => gpio2_io_o(1),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(0),
Q => gpio2_io_o(0),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(10),
Q => gpio2_io_o(10),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(9),
Q => gpio2_io_o(9),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(8),
Q => gpio2_io_o(8),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(7),
Q => gpio2_io_o(7),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(6),
Q => gpio2_io_o(6),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(5),
Q => gpio2_io_o(5),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(4),
Q => gpio2_io_o(4),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(3),
Q => gpio2_io_o(3),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(2),
Q => gpio2_io_o(2),
R => SS(0)
);
\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(11),
Q => gpio2_io_t(11),
S => SS(0)
);
\Dual.gpio2_OE_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(1),
Q => gpio2_io_t(1),
S => SS(0)
);
\Dual.gpio2_OE_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(0),
Q => gpio2_io_t(0),
S => SS(0)
);
\Dual.gpio2_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(10),
Q => gpio2_io_t(10),
S => SS(0)
);
\Dual.gpio2_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(9),
Q => gpio2_io_t(9),
S => SS(0)
);
\Dual.gpio2_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(8),
Q => gpio2_io_t(8),
S => SS(0)
);
\Dual.gpio2_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(7),
Q => gpio2_io_t(7),
S => SS(0)
);
\Dual.gpio2_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(6),
Q => gpio2_io_t(6),
S => SS(0)
);
\Dual.gpio2_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(5),
Q => gpio2_io_t(5),
S => SS(0)
);
\Dual.gpio2_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(4),
Q => gpio2_io_t(4),
S => SS(0)
);
\Dual.gpio2_OE_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(3),
Q => gpio2_io_t(3),
S => SS(0)
);
\Dual.gpio2_OE_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(2),
Q => gpio2_io_t(2),
S => SS(0)
);
\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(3),
R => '0'
);
\Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(2),
R => '0'
);
\Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(1),
R => '0'
);
\Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(0),
R => '0'
);
\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(11),
Q => gpio_io_o(3),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(10),
Q => gpio_io_o(2),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(9),
Q => gpio_io_o(1),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => gpio_io_o(0),
R => SS(0)
);
\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(11),
Q => gpio_io_t(3),
S => SS(0)
);
\Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(10),
Q => gpio_io_t(2),
S => SS(0)
);
\Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(9),
Q => gpio_io_t(1),
S => SS(0)
);
\Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(8),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_cs,
I2 => \^gpio_xferack_reg\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_slave_attachment is
port (
bus2ip_rnw_i_reg_0 : out STD_LOGIC;
\ip2bus_data_i_D1_reg[31]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[20]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_led_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_led_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal \^bus2ip_rnw_i_reg_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[31]\ : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair6";
begin
bus2ip_rnw_i_reg_0 <= \^bus2ip_rnw_i_reg_0\;
\ip2bus_data_i_D1_reg[31]\ <= \^ip2bus_data_i_d1_reg[31]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_led_0_address_decoder
port map (
D(11 downto 0) => D(11 downto 0),
\Dual.gpio2_Data_In_reg[0]\(11 downto 0) => \Dual.gpio2_Data_In_reg[0]\(11 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_Data_In_reg[0]\(3 downto 0) => Q(3 downto 0),
\Dual.gpio_Data_Out_reg[0]\(0) => \Dual.gpio_Data_Out_reg[0]\(0),
E(0) => E(0),
GPIO2_DBus_i(11 downto 0) => GPIO2_DBus_i(11 downto 0),
GPIO_DBus_i(3 downto 0) => GPIO_DBus_i(3 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^ip2bus_data_i_d1_reg[31]\,
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => \ip2bus_data_i_D1_reg[20]\(11 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^bus2ip_rnw_i_reg_0\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[8]_i_1_n_0\,
Q => bus2ip_addr(0),
R => \^bus2ip_rnw_i_reg_0\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^ip2bus_data_i_d1_reg[31]\,
R => \^bus2ip_rnw_i_reg_0\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^bus2ip_rnw_i_reg_0\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^bus2ip_rnw_i_reg_0\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^bus2ip_rnw_i_reg_0\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(0),
Q => s_axi_rdata(0),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(10),
Q => s_axi_rdata(10),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(11),
Q => s_axi_rdata(11),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(1),
Q => s_axi_rdata(1),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(2),
Q => s_axi_rdata(2),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(3),
Q => s_axi_rdata(3),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(4),
Q => s_axi_rdata(4),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(5),
Q => s_axi_rdata(5),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(6),
Q => s_axi_rdata(6),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(7),
Q => s_axi_rdata(7),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(8),
Q => s_axi_rdata(8),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(9),
Q => s_axi_rdata(9),
R => \^bus2ip_rnw_i_reg_0\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^bus2ip_rnw_i_reg_0\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^bus2ip_rnw_i_reg_0\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => \^bus2ip_rnw_i_reg_0\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => \^bus2ip_rnw_i_reg_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[20]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_led_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_led_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_led_0_slave_attachment
port map (
D(11 downto 0) => D(11 downto 0),
\Dual.gpio2_Data_In_reg[0]\(11 downto 0) => \Dual.gpio2_Data_In_reg[0]\(11 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_Data_Out_reg[0]\(0) => \Dual.gpio_Data_Out_reg[0]\(0),
E(0) => E(0),
GPIO2_DBus_i(11 downto 0) => GPIO2_DBus_i(11 downto 0),
GPIO_DBus_i(3 downto 0) => GPIO_DBus_i(3 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
Q(3 downto 0) => Q(3 downto 0),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_rnw_i_reg_0 => bus2ip_reset,
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => \ip2bus_data_i_D1_reg[20]\(11 downto 0),
\ip2bus_data_i_D1_reg[20]_0\(11 downto 0) => \ip2bus_data_i_D1_reg[20]_0\(11 downto 0),
\ip2bus_data_i_D1_reg[31]\ => bus2ip_rnw,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(11 downto 0) => s_axi_rdata(11 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_led_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 12;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 4;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_led_0_axi_gpio : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_led_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_led_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_led_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_led_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_led_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_led_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_50 : STD_LOGIC;
signal GPIO2_DBus_i : STD_LOGIC_VECTOR ( 20 to 31 );
signal GPIO_DBus : STD_LOGIC_VECTOR ( 11 downto 0 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 28 to 31 );
signal GPIO_xferAck_i : STD_LOGIC;
signal Read_Reg2_In : STD_LOGIC_VECTOR ( 0 to 11 );
signal Read_Reg_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio2_Data_In : STD_LOGIC_VECTOR ( 0 to 11 );
signal \^gpio2_io_t\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal gpio_core_1_n_19 : STD_LOGIC;
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_t(11 downto 0) <= \^gpio2_io_t\(11 downto 0);
gpio_io_t(3 downto 0) <= \^gpio_io_t\(3 downto 0);
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11 downto 0) <= \^s_axi_rdata\(11 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_led_0_axi_lite_ipif
port map (
D(11 downto 8) => p_0_out(3 downto 0),
D(7) => AXI_LITE_IPIF_I_n_11,
D(6) => AXI_LITE_IPIF_I_n_12,
D(5) => AXI_LITE_IPIF_I_n_13,
D(4) => AXI_LITE_IPIF_I_n_14,
D(3) => AXI_LITE_IPIF_I_n_15,
D(2) => AXI_LITE_IPIF_I_n_16,
D(1) => AXI_LITE_IPIF_I_n_17,
D(0) => AXI_LITE_IPIF_I_n_18,
\Dual.gpio2_Data_In_reg[0]\(11) => gpio2_Data_In(0),
\Dual.gpio2_Data_In_reg[0]\(10) => gpio2_Data_In(1),
\Dual.gpio2_Data_In_reg[0]\(9) => gpio2_Data_In(2),
\Dual.gpio2_Data_In_reg[0]\(8) => gpio2_Data_In(3),
\Dual.gpio2_Data_In_reg[0]\(7) => gpio2_Data_In(4),
\Dual.gpio2_Data_In_reg[0]\(6) => gpio2_Data_In(5),
\Dual.gpio2_Data_In_reg[0]\(5) => gpio2_Data_In(6),
\Dual.gpio2_Data_In_reg[0]\(4) => gpio2_Data_In(7),
\Dual.gpio2_Data_In_reg[0]\(3) => gpio2_Data_In(8),
\Dual.gpio2_Data_In_reg[0]\(2) => gpio2_Data_In(9),
\Dual.gpio2_Data_In_reg[0]\(1) => gpio2_Data_In(10),
\Dual.gpio2_Data_In_reg[0]\(0) => gpio2_Data_In(11),
\Dual.gpio2_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_50,
\Dual.gpio2_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_49,
\Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_36,
E(0) => AXI_LITE_IPIF_I_n_35,
GPIO2_DBus_i(11) => GPIO2_DBus_i(20),
GPIO2_DBus_i(10) => GPIO2_DBus_i(21),
GPIO2_DBus_i(9) => GPIO2_DBus_i(22),
GPIO2_DBus_i(8) => GPIO2_DBus_i(23),
GPIO2_DBus_i(7) => GPIO2_DBus_i(24),
GPIO2_DBus_i(6) => GPIO2_DBus_i(25),
GPIO2_DBus_i(5) => GPIO2_DBus_i(26),
GPIO2_DBus_i(4) => GPIO2_DBus_i(27),
GPIO2_DBus_i(3) => GPIO2_DBus_i(28),
GPIO2_DBus_i(2) => GPIO2_DBus_i(29),
GPIO2_DBus_i(1) => GPIO2_DBus_i(30),
GPIO2_DBus_i(0) => GPIO2_DBus_i(31),
GPIO_DBus_i(3) => GPIO_DBus_i(28),
GPIO_DBus_i(2) => GPIO_DBus_i(29),
GPIO_DBus_i(1) => GPIO_DBus_i(30),
GPIO_DBus_i(0) => GPIO_DBus_i(31),
GPIO_xferAck_i => GPIO_xferAck_i,
Q(3) => gpio_Data_In(0),
Q(2) => gpio_Data_In(1),
Q(1) => gpio_Data_In(2),
Q(0) => gpio_Data_In(3),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio2_io_t(11 downto 0) => \^gpio2_io_t\(11 downto 0),
gpio_io_t(3 downto 0) => \^gpio_io_t\(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => GPIO_DBus(11 downto 0),
\ip2bus_data_i_D1_reg[20]_0\(11 downto 0) => ip2bus_data_i_D1(11 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(11 downto 0) => \^s_axi_rdata\(11 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
gpio_core_1: entity work.system_axi_gpio_led_0_GPIO_Core
port map (
D(11 downto 8) => p_0_out(3 downto 0),
D(7) => AXI_LITE_IPIF_I_n_11,
D(6) => AXI_LITE_IPIF_I_n_12,
D(5) => AXI_LITE_IPIF_I_n_13,
D(4) => AXI_LITE_IPIF_I_n_14,
D(3) => AXI_LITE_IPIF_I_n_15,
D(2) => AXI_LITE_IPIF_I_n_16,
D(1) => AXI_LITE_IPIF_I_n_17,
D(0) => AXI_LITE_IPIF_I_n_18,
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(3) => gpio_Data_In(0),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(2) => gpio_Data_In(1),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(1) => gpio_Data_In(2),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(0) => gpio_Data_In(3),
E(0) => AXI_LITE_IPIF_I_n_36,
GPIO2_DBus_i(11) => GPIO2_DBus_i(20),
GPIO2_DBus_i(10) => GPIO2_DBus_i(21),
GPIO2_DBus_i(9) => GPIO2_DBus_i(22),
GPIO2_DBus_i(8) => GPIO2_DBus_i(23),
GPIO2_DBus_i(7) => GPIO2_DBus_i(24),
GPIO2_DBus_i(6) => GPIO2_DBus_i(25),
GPIO2_DBus_i(5) => GPIO2_DBus_i(26),
GPIO2_DBus_i(4) => GPIO2_DBus_i(27),
GPIO2_DBus_i(3) => GPIO2_DBus_i(28),
GPIO2_DBus_i(2) => GPIO2_DBus_i(29),
GPIO2_DBus_i(1) => GPIO2_DBus_i(30),
GPIO2_DBus_i(0) => GPIO2_DBus_i(31),
GPIO_DBus_i(3) => GPIO_DBus_i(28),
GPIO_DBus_i(2) => GPIO_DBus_i(29),
GPIO_DBus_i(1) => GPIO_DBus_i(30),
GPIO_DBus_i(0) => GPIO_DBus_i(31),
GPIO_xferAck_i => GPIO_xferAck_i,
Q(11) => gpio2_Data_In(0),
Q(10) => gpio2_Data_In(1),
Q(9) => gpio2_Data_In(2),
Q(8) => gpio2_Data_In(3),
Q(7) => gpio2_Data_In(4),
Q(6) => gpio2_Data_In(5),
Q(5) => gpio2_Data_In(6),
Q(4) => gpio2_Data_In(7),
Q(3) => gpio2_Data_In(8),
Q(2) => gpio2_Data_In(9),
Q(1) => gpio2_Data_In(10),
Q(0) => gpio2_Data_In(11),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_35,
bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_50,
bus2ip_rnw_i_reg_1(0) => AXI_LITE_IPIF_I_n_49,
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
gpio2_io_o(11 downto 0) => gpio2_io_o(11 downto 0),
gpio2_io_t(11 downto 0) => \^gpio2_io_t\(11 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
gpio_io_o(3 downto 0) => gpio_io_o(3 downto 0),
gpio_io_t(3 downto 0) => \^gpio_io_t\(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(11),
Q => ip2bus_data_i_D1(11),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(10),
Q => ip2bus_data_i_D1(10),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(9),
Q => ip2bus_data_i_D1(9),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(8),
Q => ip2bus_data_i_D1(8),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(7),
Q => ip2bus_data_i_D1(7),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(6),
Q => ip2bus_data_i_D1(6),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(5),
Q => ip2bus_data_i_D1(5),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(4),
Q => ip2bus_data_i_D1(4),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(3),
Q => ip2bus_data_i_D1(3),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(2),
Q => ip2bus_data_i_D1(2),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(1),
Q => ip2bus_data_i_D1(1),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_led_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_led_0 : entity is "system_axi_gpio_led_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_led_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_led_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_led_0;
architecture STRUCTURE of system_axi_gpio_led_0 is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 12;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 4;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_led_0_axi_gpio
port map (
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
gpio2_io_o(11 downto 0) => gpio2_io_o(11 downto 0),
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
gpio_io_o(3 downto 0) => gpio_io_o(3 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
177e37ec5dddc5fd6701c164f119e731
| 0.592001 | 2.565679 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/MUX_RFSOURCE_tb.vhd
| 1 | 2,001 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MUX_RFSOURCE_tb IS
END MUX_RFSOURCE_tb;
ARCHITECTURE behavior OF MUX_RFSOURCE_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX_RFSOURCE
PORT(
RFSOURCE : IN std_logic_vector(1 downto 0);
DATATOMEM : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
PC : IN std_logic_vector(31 downto 0);
DATATOREG : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal RFSOURCE : std_logic_vector(1 downto 0) := (others => '0');
signal DATATOMEM : std_logic_vector(31 downto 0) := (others => '0');
signal ALURESULT : std_logic_vector(31 downto 0) := (others => '0');
signal PC : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal DATATOREG : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX_RFSOURCE PORT MAP (
RFSOURCE => RFSOURCE,
DATATOMEM => DATATOMEM,
ALURESULT => ALURESULT,
PC => PC,
DATATOREG => DATATOREG
);
-- Stimulus process
stim_proc: process
begin
RFSOURCE<="00";
DATATOMEM<="00000000000000000011010000111111";
ALURESULT<="00000000000000000000000000010111";
PC<="00000000000000000000000000000011";
wait for 20 ns;
RFSOURCE<="01";
DATATOMEM<="00000000000000000010000000100001";
ALURESULT<="00000000000000000000000100010000";
PC<="00000000000000000000000000000111";
wait for 20 ns;
RFSOURCE<="10";
DATATOMEM<="00000000000000000000001100000000";
ALURESULT<="00000000000000000000000111110000";
PC<="00000000000000000000000000001011";
wait for 20 ns;
RFSOURCE<="11";
DATATOMEM<="00000000000000000000000000101000";
ALURESULT<="00000000000000000000000000000101";
PC<="00000000000000000000000000001111";
wait;
end process;
END;
|
mit
|
10ab3877118c2c6ddd97300447afd3db
| 0.643678 | 4.45657 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/rs232_usb_wrapper.vhd
| 1 | 6,691 |
-------------------------------------------------------------------------------
-- rs232_usb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_uartlite_v1_02_a;
use xps_uartlite_v1_02_a.all;
entity rs232_usb_wrapper is
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 1);
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of rs232_usb_wrapper : entity is "xps_uartlite_v1_02_a";
end rs232_usb_wrapper;
architecture STRUCTURE of rs232_usb_wrapper is
component xps_uartlite is
generic (
C_FAMILY : STRING;
C_SPLB_CLK_FREQ_HZ : INTEGER;
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
port (
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end component;
begin
RS232_USB : xps_uartlite
generic map (
C_FAMILY => "spartan6",
C_SPLB_CLK_FREQ_HZ => 50000000,
C_BASEADDR => X"84000000",
C_HIGHADDR => X"8400ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_NATIVE_DWIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
port map (
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_masterID => PLB_masterID,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrDBus => PLB_wrDBus,
PLB_UABus => PLB_UABus,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_MSize => PLB_MSize,
PLB_lockErr => PLB_lockErr,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_rdDBus => Sl_rdDBus,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MIRQ => Sl_MIRQ,
RX => RX,
TX => TX,
Interrupt => Interrupt
);
end architecture STRUCTURE;
|
gpl-2.0
|
24e635c7308ae282ee21210ca7749b7b
| 0.581677 | 3.223025 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_temperature_update.vhd
| 1 | 5,397 |
-- file: system_xadc_wiz_0_0_temperature_update.vhd
-- (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity temperature_update is
port (
reset : in std_logic; -- Active High Reset
clk : in std_logic; -- Async Clock input from Slave
temp_bus_update : in std_logic;
wait_cycle : in std_logic_vector(15 downto 0);
temp_out : out std_logic_vector(11 downto 0);
-- DRP signals for Arbiter
daddr_o : out std_logic_vector(7 downto 0);
den_o : out std_logic;
di_o : out std_logic_vector(15 downto 0);
dwe_o : out std_logic;
do_i : in std_logic_vector(15 downto 0);
drdy_i : in std_logic;
busy_o : out std_logic
);
end temperature_update;
architecture beh of temperature_update is
type fsmstate_temp_rd is (WAIT_TIMER_UPDATE, WAIT_UPDATE_ENABLE,RD_EN_CTRL_REG_TEMP,RD_CTRL_REG_TEMP );
signal state : fsmstate_temp_rd;
type ram_type is array (1 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
signal timer_cntr : std_logic_vector(15 downto 0);
begin
di_o <= (others => '0');
drp_fsm: process (clk, reset)
begin
if (reset = '1') then
state <= WAIT_UPDATE_ENABLE;
daddr_o <= (others => '0');
dwe_o <= '0';
den_o <= '0';
busy_o <= '0';
temp_out <= (others => '0');
elsif clk'event and clk = '1' then
case state is
when WAIT_UPDATE_ENABLE =>
busy_o <= '0';
state <= RD_EN_CTRL_REG_TEMP;
busy_o <= '1';
den_o <= '0';
when RD_EN_CTRL_REG_TEMP =>
state <= RD_CTRL_REG_TEMP;
daddr_o <= X"00";
dwe_o <= '0';
den_o <= '1';
when RD_CTRL_REG_TEMP =>
den_o <= '0';
if drdy_i = '1' then
state <= WAIT_TIMER_UPDATE;
temp_out <= do_i(15 downto 4);
busy_o <= '0';
end if;
when WAIT_TIMER_UPDATE =>
dwe_o <= '0';
if timer_cntr >= X"0000" and timer_cntr <= X"0008" then
state <= WAIT_UPDATE_ENABLE;
end if;
when others => Null;
end case;
end if;
end process;
timer_cntr_proc: process (clk, reset)
begin
if (reset = '1') then
timer_cntr <= (others => '0');
elsif clk'event and clk = '1' then
if timer_cntr = X"0000" then
timer_cntr <= wait_cycle;
else
timer_cntr <= timer_cntr - 1;
end if;
end if;
end process;
end beh;
|
apache-2.0
|
dd731510feece0d1f858bcc9bc11631e
| 0.56587 | 4.249606 | false | false | false | false |
daniw/add
|
rot_enc/mcu_pkg.vhd
| 1 | 10,097 |
-------------------------------------------------------------------------------
-- Entity: mcu_pkg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- VHDL package for definition of design parameters and types used throughout
-- the MCU.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mcu_pkg is
-----------------------------------------------------------------------------
-- tool chain selection (because no suppoprt of 'val attritube in ISE XST)
-----------------------------------------------------------------------------
constant ISE_TOOL : boolean := true; -- true = ISE XST
-- false = other synthesizer (e.g. Vivado)
-- system clock frequency in Hz
constant CF : natural := 50_000_000; -- 50 MHz
-----------------------------------------------------------------------------
-- Helper functions (prototypes)
-----------------------------------------------------------------------------
-- std_logic_vector(to_signed(i,w))
function i2slv(i : integer; w : positive) return std_logic_vector;
-- std_logic_vector(to_unsigned(n,w))
function n2slv(n : natural; w : positive) return std_logic_vector;
-----------------------------------------------------------------------------
-- design parameters: Memory Map
-----------------------------------------------------------------------------
-- bus architecture parameters
constant DW : natural range 4 to 64 := 16; -- data word width
constant AW : natural range 2 to 64 := 10; -- total address width
constant AWH : natural range 1 to 64 := 4; -- high address width
constant AWL : natural range 1 to 64 := AW-AWH; -- low address width
-- memory map
type t_bus_slave is (ROM, RAM, GPIO, FMC, TIM, UART); -- list of bus slaves
type t_ba is array (t_bus_slave) of std_logic_vector(AW-1 downto 0);
constant BA : t_ba := ( -- full base addresses
ROM => "0-" & "----" & "----",
RAM => "10" & "----" & "----",
GPIO => "11" & "00--" & "----",
FMC => "11" & "01--" & "----",
TIM => "11" & "10--" & "----",
UART => "11" & "11--" & "----"
);
type t_hba is array (t_bus_slave) of std_logic_vector(AWH-1 downto 0);
constant HBA : t_hba := ( -- high base address for decoding
ROM => BA(ROM) (AW-1 downto AW-AWH),
RAM => BA(RAM) (AW-1 downto AW-AWH),
GPIO => BA(GPIO)(AW-1 downto AW-AWH),
FMC => BA(FMC) (AW-1 downto AW-AWH),
TIM => BA(TIM) (AW-1 downto AW-AWH),
UART => BA(UART)(AW-1 downto AW-AWH)
);
-- Relative Register Addresses of Peripherals
-- GPIO
constant c_addr_gpio_data_in : std_logic_vector(AWL-1 downto 0) := n2slv( 0, AWL);
constant c_addr_gpio_data_out : std_logic_vector(AWL-1 downto 0) := n2slv( 1, AWL);
constant c_addr_gpio_out_enb : std_logic_vector(AWL-1 downto 0) := n2slv( 2, AWL);
constant c_addr_enc_ctrl : std_logic_vector(AWL-1 downto 0) := n2slv( 3, AWL);
constant c_addr_enc_dist : std_logic_vector(AWL-1 downto 0) := n2slv( 4, AWL);
constant c_addr_enc_pos : std_logic_vector(AWL-1 downto 0) := n2slv( 5, AWL);
constant c_addr_enc_neg : std_logic_vector(AWL-1 downto 0) := n2slv( 6, AWL);
type t_gpio_addr_sel is (none, gpio_data_in, gpio_data_out, gpio_enb, enc_ctrl, enc_dist, enc_pos, enc_neg);
-- FMC
-- TIM
-- UART
-----------------------------------------------------------------------------
-- design parameters: CPU Instructions
-----------------------------------------------------------------------------
-- CPU instruction set
-- Note: Defining the OPcode in the way shown below, allows assembler-style
-- programming with mnemonics rather than machine coding (see rom.vhd).
constant OPCW : natural range 1 to DW := 5; -- Opcode word width
constant OPAW : natural range 1 to DW := 4; -- ALU operation word width
constant IOWW : natural range 1 to DW := 8; -- immediate operand word width
type t_instr is (add, sub, andi, ori, xori, slai, srai, mov,
ld, st,
addil, addih, setil, setih,
jmp, bne, bge, blt, bca, bov,
nop);
-- Instructions targeted at the ALU are defined by means of a sub-type.
-- This allows changing the opcode of instructions without having to
-- modify the source code of the ALU.
subtype t_alu_instr is t_instr range add to mov;
type t_opcode is array (t_instr) of std_logic_vector(OPCW-1 downto 0);
constant OPC : t_opcode := ( -- OPcode
-- ALU operations -------------------------------
add => "00000", -- 0: addition
sub => "00001", -- 1: subtraction
andi => "00010", -- 2: bit-wise AND
ori => "00011", -- 3: bit-wise OR
xori => "00100", -- 4: bit-wise XOR
slai => "00101", -- 5: shift-left arithmetically
srai => "00110", -- 6: shift-right arithmetically
mov => "00111", -- 7: move between register
-- Immediate Operands ---------------------------
addil => "01100", -- 12: add imm. constant low
addih => "01101", -- 13: add imm. constant high
setil => "01110", -- 14: set imm. constant low
setih => "01111", -- 15: set imm. constant high
-- Memory load/store ----------------------------
ld => "10000", -- 16: load from memory
st => "10001", -- 17: store to memory
-- Jump/Branch ----------------------------------
jmp => "11000", -- 24: absolute jump
bne => "11001", -- 25: branch if not equal (not Z)
bge => "11010", -- 26: branch if greater/equal (not N or Z)
blt => "11011", -- 27: branch if less than (N)
bca => "11100", -- 28: branch if carry set (C)
bov => "11101", -- 29: branch if overflow set (O)
-- Others ---------------------------------------
nop => "11111" -- 31: no operation
);
type t_flags is (Z, N, C, O); -- ALU flags (zero, negative, carry, overflow)
type t_flag_arr is array (t_flags) of std_logic;
-- register block
constant RIDW : natural range 1 to DW := 3; -- register ID word width
type t_regid is array(0 to 7) of std_logic_vector(RIDW-1 downto 0);
constant reg : t_regid := ("000","001","010","011","100","101","110","111");
type t_regblk is array(0 to 7) of std_logic_vector(DW-1 downto 0);
-- CPU address generation
type t_pc_mode is (linear, abs_jump, rel_offset); -- addr calcultion modi
type t_addr_exc is (no_err, lin_err, rel_err); -- address exceptions
-----------------------------------------------------------------------------
-- global types
-----------------------------------------------------------------------------
-- Master bus interface -----------------------------------------------------
type t_bus2cpu is record
data : std_logic_vector(DW-1 downto 0);
end record;
type t_cpu2bus is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
rd_enb : std_logic;
wr_enb : std_logic;
end record;
-- Read-only slave bus interface -------------------------------------------
type t_bus2ros is record
addr : std_logic_vector(AWL-1 downto 0);
rd_enb : std_logic;
end record;
type t_ros2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- read/write slave bus interface -------------------------------------------
type t_bus2rws is record
addr : std_logic_vector(AWL-1 downto 0);
data : std_logic_vector(DW-1 downto 0);
rd_enb : std_logic; -- use of this signal is optional, depending on slave
wr_enb : std_logic;
end record;
type t_rws2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- CPU internal types
-----------------------------------------------------------------------------
-- Control Unit / Register Block interface ----------------------------------
type t_ctr2reg is record
src1 : std_logic_vector(RIDW-1 downto 0);
src2 : std_logic_vector(RIDW-1 downto 0);
dest : std_logic_vector(RIDW-1 downto 0);
enb_res : std_logic;
data : std_logic_vector(DW-1 downto 0);
enb_data : std_logic;
end record;
type t_reg2ctr is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
end record;
-- Control Unit / Program Counter interface --------------------------------
type t_ctr2prc is record
enb : std_logic;
mode : t_pc_mode;
addr : std_logic_vector(AW-1 downto 0);
end record;
type t_prc2ctr is record
pc : std_logic_vector(AW-1 downto 0);
exc : t_addr_exc;
end record;
-- Control Unit / ALU interface ---------------------------------------------
type t_ctr2alu is record
op : std_logic_vector(OPAW-1 downto 0); -- operation
imm : std_logic_vector(IOWW-1 downto 0); -- immediate operand
enb : std_logic; -- enable flag update
end record;
type t_alu2ctr is record
flag : t_flag_arr;
end record;
end package mcu_pkg;
package body mcu_pkg is
-----------------------------------------------------------------------------
-- Function Implementations
-----------------------------------------------------------------------------
function i2slv(i : integer;w : positive) return std_logic_vector is
begin
return std_logic_vector(to_signed(i,w));
end function i2slv;
function n2slv(n : natural;w : positive) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(n,w));
end function n2slv;
end package body mcu_pkg;
|
gpl-2.0
|
4e2279eb2c44a0a8b4ffe4201e0b6d9f
| 0.484996 | 4.05014 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/InstructionMemory.vhd
| 1 | 3,187 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity InstructionMemory is
Port ( Address : in STD_LOGIC_VECTOR (5 downto 0);
rst : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end InstructionMemory;
architecture syn of InstructionMemory is
type rom_type is array (63 downto 0) of std_logic_vector (31 downto 0);
signal ROM : rom_type:= ("00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","00000000000000000000000000000000",
"00000000000000000000000000000000","10011000001000000100000000000010",
"10010110001110000100000000000010","10010100001010000100000000000010",
"10010010000110000100000000000010","10010000000000000100000000000010",
"10000100000100000011111111111001","10000010000100000010000000001000");
begin
process(rst,Address,ROM)
begin
if rst='1' then
Instruction<=(others=>'0');
else
Instruction<=ROM(conv_integer(Address));
end if;
end process;
end syn;
|
mit
|
d0e75647a4b7b930326c6c7394fdf70b
| 0.770631 | 8.192802 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/a811/hdl/axi_intc_v4_1_vh_rfs.vhd
| 1 | 182,883 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : double_synchronizer.vhd
-- Version : v3.0
-- Description: The double_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- RESET_2 signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity double_synchronizer is
generic (
C_DWIDTH : integer range 1 to 32 := 1
);
port (
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active_low
DATA_IN : in std_logic_vector(C_DWIDTH-1 downto 0);
SYNC_DATA_OUT : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity;
-------------------------------------------------------------------------------
architecture RTL of double_synchronizer is
signal RESET_2_p : std_logic;
signal data_in_d1 : std_logic_vector(C_DWIDTH-1 downto 0);
-----
begin
-----
-- active high Reset
RESET_2_p <= not RESET_2_n;
REG_GEN : for i in 0 to (C_DWIDTH - 1) generate
BLOCK_GEN: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FIRST_FLOP_i : label is "TRUE";
begin
FIRST_FLOP_i: component FDR
port map (
Q => data_in_d1(i),
C => CLK_2,
D => DATA_IN(i),
R => RESET_2_p
);
SECOND_FLOP_i: component FDR
port map (
Q => SYNC_DATA_OUT(i),
C => CLK_2,
D => data_in_d1(i),
R => RESET_2_p
);
end block BLOCK_GEN;
end generate REG_GEN;
-------------------------------------------------------------------------------
end RTL;
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : pulse_synchronizer.vhd
-- Version : v3.0
-- Description: The pulse_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.all;
entity pulse_synchronizer is
port (
CLK_1 : in std_logic;
RESET_1_n : in std_logic; -- active low reset
DATA_IN : in std_logic;
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active low reset
SYNC_DATA_OUT : out std_logic
);
end entity;
architecture RTL of pulse_synchronizer is
signal data_in_toggle : std_logic;
signal data_in_toggle_sync : std_logic;
signal data_in_toggle_sync_d1 : std_logic;
signal data_in_toggle_sync_vec : std_logic_vector(0 downto 0);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
begin
TOGGLE_DATA_IN_REG:process(CLK_1)
begin
if(CLK_1'event and CLK_1 = '1') then
if(RESET_1_n = '0') then
data_in_toggle <= '0';
else
data_in_toggle <= DATA_IN xor data_in_toggle;
end if;
end if;
end process TOGGLE_DATA_IN_REG;
DOUBLE_SYNC_I : entity axi_intc_v4_1_9.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => CLK_2,
RESET_2_n => RESET_2_n,
DATA_IN => scalar_to_vector(data_in_toggle),
SYNC_DATA_OUT => data_in_toggle_sync_vec
);
data_in_toggle_sync <= data_in_toggle_sync_vec(0);
SYNC_DATA_REG:process(CLK_2)
begin
if(CLK_2'event and CLK_2 = '1') then
if(RESET_2_n = '0') then
data_in_toggle_sync_d1 <= '0';
else
data_in_toggle_sync_d1 <= data_in_toggle_sync;
end if;
end if;
end process SYNC_DATA_REG;
SYNC_DATA_OUT <= data_in_toggle_sync xor data_in_toggle_sync_d1;
end RTL;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: intc_core.vhd
-- Version: v3.1
-- Description: Interrupt controller without a bus interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- ~~~~~~
-- - Initial release of v2.00.a
-- - Updated by pkaruna
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support in v3.1 version of the core
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.std_logic_misc.all;
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- -- Intc Parameters
-- C_DWIDTH -- Data bus width
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits
-- Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits
-- Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- Clk -- Clock
-- Rst -- Reset
-- Intc Interface Signals
-- Intr -- Input Interruput request
-- Reg_addr -- Address bus
-- Bus2ip_rdce -- Read
-- Bus2ip_wrce -- Write
-- Wr_data -- Write data bus
-- Rd_data -- Read data bus
-- Irq -- Output Interruput request
-- Processor_clk -- input same as processor clock
-- Processor_rst -- input same as processor reset
-- Processor_ack -- input Connected to processor ACK
-- Interrupt_address -- output Connected to processor interrupt address pins
-- Interrupt_address_in -- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- Processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------
entity intc_core is
generic
(
C_FAMILY : string := "virtex6";
C_DWIDTH : integer := 32;
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0)
:= "11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 0;
C_HAS_FAST : integer range 0 to 1 := 0;
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
);
port
(
-- Inputs
Clk : in std_logic; --- AXI Clock
Rst_n : in std_logic; --- active low AXI Reset
Intr : in std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
Reg_addr : in std_logic_vector(6 downto 0);
Bus2ip_rdce : in std_logic_vector(0 to 16);
Bus2ip_wrce : in std_logic_vector(0 to 16);
Wr_data : in std_logic_vector(C_DWIDTH - 1 downto 0);
-- Outputs
Rd_data : out std_logic_vector(C_DWIDTH - 1 downto 0);
Processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- active high MB rst, reset from MicroBlaze
Irq : out std_logic;
Processor_ack : in std_logic_vector(1 downto 0); --- added for fast interrupt mode
Interrupt_address : out std_logic_vector(31 downto 0); --- added for fast interrupt mode
--
Interrupt_address_in : in std_logic_vector(31 downto 0);
Processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
attribute buffer_type: string;
attribute buffer_type of Intr: signal is "none";
end intc_core;
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture imp of intc_core is
-- Component Declarations
-- ======================
constant C_NUM_INTR : integer := C_NUM_INTR_INPUTS + C_NUM_SW_INTR;
constant RESET_ACTIVE : std_logic := '0';
CONSTANT INDEX_BIT : INTEGER := INTEGER(CEIL(LOG2(REAL(C_NUM_INTR+1))));
constant MICROBLAZE_FIXED_ADDRESS : std_logic_vector := X"00000010";
CONSTANT IVR_ALL_ONES : std_logic_vector(INDEX_BIT-1 downto 0) := (others => '1');
--- *** --- Decision is pending for logic used - mail sent to Bsb on 3rd Oct, 2012
CONSTANT C_USE_METHOD : integer := 1;
--- *** ---
-- Signal declaration
-- ==================
signal processor_rst_n : std_logic;
signal ack_b01 : std_logic;
signal first_ack : std_logic;
signal first_ack_active : std_logic;
signal second_ack : std_logic;
signal first_ack_sync : std_logic;
signal second_ack_sync : std_logic;
signal second_ack_sync_d1 : std_logic;
signal second_ack_sync_d2 : std_logic;
signal second_ack_sync_d3 : std_logic;
signal second_ack_sync_mb_clk : std_logic;
signal Irq_i : std_logic;
signal ivr_data_in : std_logic_vector(INDEX_BIT - 1 downto 0);
signal wr_data_int : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal mer_int : std_logic_vector(1 downto 0);
signal mer : std_logic_vector(C_DWIDTH - 1 downto 0);
signal sie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal cie : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal iar : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ier : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal isr_en : std_logic;
signal hw_intr : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr_data_in : std_logic_vector(C_NUM_INTR_INPUTS - 1 downto 0);
signal isr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal ivr : std_logic_vector(INDEX_BIT - 1 downto 0);
signal ivr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ilr : std_logic_vector(INDEX_BIT downto 0);
signal ilr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal imr : std_logic_vector(C_NUM_INTR - 1 downto 0);
signal imr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ipr : std_logic_vector(C_DWIDTH - 1 downto 0);
signal irq_gen_i : std_logic;
signal irq_gen : std_logic;
signal irq_gen_sync : std_logic;
signal read : std_logic;
signal ier_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_out : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ack_or_i : std_logic;
signal ack_or : std_logic;
signal ack_or_sync : std_logic;
signal read_ivar : std_logic;
signal write_ivar : std_logic;
signal isr_or : std_logic;
signal ivar_index_mb_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal ivar_index_axi_clk : std_logic_vector(INDEX_BIT-1 downto 0);
signal in_idle : std_logic;
signal in_idle_axi_clk : std_logic;
signal idle_and_irq : std_logic;
signal idle_and_irq_d1 : std_logic;
signal ivar_index_sample_en_i : std_logic;
signal ivar_index_sample_en : std_logic;
signal ivar_index_sample_en_mb_clk : std_logic;
signal irq_dis_sample_mb_clk : std_logic;
signal ivar_rd_addr_mb_clk : std_logic_vector(4 downto 0);
signal mer_0_sync : std_logic;
--signal bus2ip_rdce_fast : std_logic_vector(0 to 31);
--signal bus2ip_wrce_fast : std_logic_vector(0 to 31);
signal bus2ip_rdce_fast : std_logic;
signal bus2ip_wrce_fast : std_logic;
signal ivar_rd_data_axi_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal ivar_rd_data_mb_clk : std_logic_vector(C_DWIDTH - 1 downto 0);
signal isr_ored_30_0_bits : std_logic;
signal Interrupt_address_in_reg_int : std_logic_vector(31 downto 0);
signal intr_31_deassert_info : std_logic;
signal intr_31_deasserted_d1 : std_logic;
signal intr_31_deasserted : std_logic;
-- --------------------------------------------------------------------------------------
-- -- Function to find logic OR of 32 bit width vector
-- --------------------------------------------------------------------------------------
-- Function OR32_VEC2STDLOGIC (vec_in : std_logic_vector) return std_logic is
-- variable or_out : std_logic := '0';
-- begin
-- for i in 0 to 31 loop
-- or_out := vec_in(i) or or_out;
-- end loop;
-- return or_out;
-- end function Or32_vec2stdlogic;
-- --------------------------------------------------------------------------------------
FUNCTION calc_ivar_ram_addr_bits (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 5;
else
RETURN 4;
end if;
end FUNCTION calc_ivar_ram_addr_bits;
-------------------------------------
FUNCTION calc_ivar_ram_depth (
constant C_NUM_INTR : integer)
RETURN integer is
begin
if (C_NUM_INTR > 16) then
RETURN 32;
else
RETURN 16;
end if;
end FUNCTION calc_ivar_ram_depth;
---------------------------------
CONSTANT IVAR_MEM_ADDR_LINES : INTEGER := calc_ivar_ram_addr_bits (C_NUM_INTR);
CONSTANT IVAR_MEM_DEPTH : INTEGER := calc_ivar_ram_depth (C_NUM_INTR);
--------------------------------------------------------------------------------------
-- Function to convert std_logic to std_logic_vector
--------------------------------------------------------------------------------------
Function scalar_to_vector (scalar_in : std_logic) return std_logic_vector is
variable vec_out : std_logic_vector(0 downto 0) := "0";
begin
vec_out(0) := scalar_in;
return vec_out;
end function scalar_to_vector;
-- Begin of architecture
begin
-----
-- active low reset
processor_rst_n <= not Processor_rst;
read <= bus2ip_rdce(0) or -- for ISR
bus2ip_rdce(1) or -- for IPR
bus2ip_rdce(2) or -- for IER
bus2ip_rdce(6) or -- for IVR
bus2ip_rdce(7) or -- for MER
bus2ip_rdce(8) or -- for IMR
bus2ip_rdce(9); -- for ILR
--------------------------------------------------------------------------
-- GENERATING ALL REGISTERS
--------------------------------------------------------------------------
wr_data_int <= Wr_data(C_NUM_INTR - 1 downto 0);
-------------------------------------------------------------------------
-- GENERATING IVAR READ ENABLES
-------------------------------------------------------------------------
bus2ip_rdce_fast <= bus2ip_rdce(16);
bus2ip_wrce_fast <= bus2ip_wrce(16);
write_ivar <= bus2ip_wrce_fast;
read_ivar <= bus2ip_rdce_fast;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------
NO_CASCADE_MASTER_MODE : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------------------------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
-----------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
-----------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
-----------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
-----------------------------------------
end generate NO_CASCADE_MASTER_MODE;
-----------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) & -- to avoide any delay the processor is
(Processor_ack(0) and (not isr_ored_30_0_bits)) ; -- simply passed to below modules
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--------------------------------------------
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
--------------------------------------------
end generate ACK_EN_SYNC_EN_GEN;
--------------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
--------------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
--------------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
--------------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
--------------------------------------------
end generate CASCADE_MASTER_MODE_10;
-----------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1')then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
) then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
---------------------------
first_second_ack_REG_P: process (Processor_clk) is
-----
begin
-----
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
ACK_EN_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize first_ack to AXI clock domain
Processor_first_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => first_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => first_ack_sync
);
--Synchronize second_ack to AXI clock domain
Processor_second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Processor_clk,
RESET_1_n => processor_rst_n,
DATA_IN => second_ack,
CLK_2 => Clk,
RESET_2_n => Rst_n,
SYNC_DATA_OUT => second_ack_sync
);
end generate ACK_EN_SYNC_EN_GEN;
------------------------------------
ACK_EN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
end generate ACK_EN_SYNC_DISABLE_GEN;
------------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
------------------------------------
SECOND_ACK_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--Synchronize Second_ack_sync_d2 back to processor clock domain
Second_ack_EN_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => second_ack_sync_d2,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => second_ack_sync_mb_clk
);
end generate SECOND_ACK_SYNC_EN_GEN;
------------------------------------
SECOND_ACK_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
end generate SECOND_ACK_SYNC_DISABLE_GEN;
------------------------------------
end generate CASCADE_MASTER_MODE_11;
-----------------------------
end generate ACK_EN_SYNC_ON_MB_CLK_GEN;
--------------------------------------------------------------------------
-- Process for generating ACK enable and type and syncing them to ACLK
--------------------------------------------------------------------------
ACK_EN_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
NO_CASCADE_MASTER : if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
-----
begin
-----
-- dont bypass the processor ack to output
Processor_ack_out <= (others => '0');
-----------------
Processor_ack_EN_REG_P: process (Processor_ack) is
-----
begin
-----
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
end process Processor_ack_EN_REG_P;
-----------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif (Processor_ack(1) = '1') then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate NO_CASCADE_MASTER;
-------------------------------
CASCADE_MASTER_MODE_10 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
------------------------
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
-----------------------------------
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
end generate CASCADE_MASTER_MODE_10;
-------------------------------
CASCADE_MASTER_MODE_11 : if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-----
begin
-----
--------------------------------------------------
Processor_ack_out <= (Processor_ack(1) and (not isr_ored_30_0_bits)) &
(Processor_ack(0) and (not isr_ored_30_0_bits)) ;
ack_b01 <= (not Processor_ack(1)) and Processor_ack(0); -- ack = b01
--------------------------------------------------
first_ack_active_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack_active <= '0';
else
if (ack_b01 = '1') then
first_ack_active <= '1';
elsif((Processor_ack(1) = '1')-- and
--(isr(31) = '0') and
--(ier(31) = '0') -- and
-- (isr_ored_30_0_bits = '1')
)then
first_ack_active <= '0';
else
first_ack_active <= first_ack_active;
end if;
end if;
end if;
end process first_ack_active_REG_P;
first_second_ack_REG_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
first_ack <= '0';
second_ack <= '0';
else
first_ack <= ack_b01;
second_ack <= first_ack_active and Processor_ack(1);
end if;
end if;
end process first_second_ack_REG_P;
-----------------------------------
first_ack_sync <= first_ack;
second_ack_sync <= second_ack;
-----------------------------------
second_ack_d2_reg_p: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
second_ack_sync_d1 <= '0';
second_ack_sync_d2 <= '0';
second_ack_sync_d3 <= '0';
else
second_ack_sync_d1 <= second_ack_sync;
second_ack_sync_d2 <= second_ack_sync_d1;
second_ack_sync_d3 <= second_ack_sync_d2;
end if;
end if;
end process second_ack_d2_reg_p;
-----------------------------------
second_ack_sync_mb_clk <= second_ack_sync_d2;
--second_ack_sync_mb_clk <= second_ack_sync;
-----------------------------------
end generate CASCADE_MASTER_MODE_11;
-------------------------------
----------------------------------------
end generate ACK_EN_SYNC_ON_AXI_CLK_GEN;
SECOND_ACK_FAST_0_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
second_ack_sync_mb_clk <= ack_or_sync;
Processor_ack_out <= (others => '0');
end generate SECOND_ACK_FAST_0_GEN;
--------------------------------------------------------------------------
-- Process MER_ME_P for MER ME bit generation
--------------------------------------------------------------------------
MER_ME_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(0) <= '0';
elsif (bus2ip_wrce(7) = '1') then
mer_int(0) <= Wr_data(0);
end if;
end if;
end process MER_ME_P;
--------------------------------------------------------------------------
-- Process MER_HIE_P for generating MER HIE bit
--------------------------------------------------------------------------
MER_HIE_P: process (Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
mer_int(1) <= '0';
elsif ((bus2ip_wrce(7) = '1') and (mer_int(1) = '0')) then
mer_int(1) <= Wr_data(1);
end if;
end if;
end process MER_HIE_P;
-----------------------------------
mer(1 downto 0) <= mer_int;
mer(C_DWIDTH - 1 downto 2) <= (others => '0');
-----------------------------------
----------------------------------------------------------------------
-- Generate SIE if (C_HAS_SIE = 1)
----------------------------------------------------------------------
SIE_GEN: if (C_HAS_SIE = 1) generate
-----
begin
-----
SIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
--------------------------------------------------------------
-- Process SIE_P for generating SIE register
--------------------------------------------------------------
SIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (sie(i) = '1')) then
sie(i) <= '0';
elsif (bus2ip_wrce(4) = '1') then
sie(i) <= wr_data_int(i);
end if;
end if;
end process SIE_P;
end generate SIE_BIT_GEN;
end generate SIE_GEN;
----------------------------------------------------------------------
-- Assign sie_out ALL ZEROS if (C_HAS_SIE = 0)
----------------------------------------------------------------------
SIE_NO_GEN: if (C_HAS_SIE = 0) generate
-----
begin
-----
sie <= (others => '0');
end generate SIE_NO_GEN;
----------------------------------------------------------------------
-- Generate CIE if (C_HAS_CIE = 1)
----------------------------------------------------------------------
CIE_GEN: if (C_HAS_CIE = 1) generate
-----
begin
-----
CIE_BIT_GEN : for i in 0 to (C_NUM_INTR - 1) generate
------------------------------------------------------------------
-- Process CIE_P for generating CIE register
------------------------------------------------------------------
CIE_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
cie(i) <= '0';
elsif (bus2ip_wrce(5) = '1') then
cie(i) <= wr_data_int(i);
end if;
end if;
end process CIE_P;
end generate CIE_BIT_GEN;
end generate CIE_GEN;
----------------------------------------------------------------------
-- Assign cie_out ALL ZEROS if (C_HAS_CIE = 0)
----------------------------------------------------------------------
CIE_NO_GEN: if (C_HAS_CIE = 0) generate
cie <= (others => '0');
end generate CIE_NO_GEN;
-- Generating write enable & data input for ISR
isr_en <= mer(1) or bus2ip_wrce(0);
isr_data_in <= hw_intr when mer(1) = '1' else
Wr_data(C_NUM_INTR_INPUTS - 1 downto 0);
--------------------------------------------------------------------------
-- Generate Registers of width equal C_NUM_INTR
--------------------------------------------------------------------------
REG_GEN : for i in 0 to (C_NUM_INTR - 1) generate
-----
begin
-----
--IAR_NORMAL_MODE_GEN: if ((C_HAS_FAST = 0) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
IAR_NORMAL_MODE_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_NORMAL_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1')) then
iar(i) <= wr_data_int(i);
else
iar(i) <= '0';
end if;
end if;
end process IAR_NORMAL_BIT_P;
-----------------------------------
end generate IAR_NORMAL_MODE_GEN;
---------------------------------
IAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
----------------------------------------------------------------------
-- Process FAST_IAR_BIT_P for generating IAR register
----------------------------------------------------------------------
IAR_FAST_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
iar(i) <= '0';
elsif ((bus2ip_wrce(3) = '1') and (imr(i) = '0')) then
iar(i) <= wr_data_int(i);
elsif (imr(i) = '1') then
if (((C_KIND_OF_INTR(i) = '1') and (first_ack_sync = '1')) or
((C_KIND_OF_INTR(i) = '0') and (second_ack_sync = '1'))) then
if (i = TO_INTEGER(unsigned(ivar_index_axi_clk))) then -- -- clearing IAR based on Processor_ack in FAST_INTERRUPT mode
iar(i) <= '1';
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
else
iar(i) <= iar(i);
end if;
end if;
end process IAR_FAST_BIT_P;
-----------------------------------
end generate IAR_FAST_MODE_GEN;
-------------------------------
----------------------------------------------------------------------
-- Process IER_BIT_P for generating IER register
----------------------------------------------------------------------
IER_BIT_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (cie(i) = '1')) then
ier(i) <= '0';
elsif (sie(i) = '1') then
ier(i) <= '1';
elsif (bus2ip_wrce(2) = '1') then
ier(i) <= wr_data_int(i);
end if;
end if;
end process IER_BIT_P;
----------------------------------------------------------------------
-- Process ISR_P for generating ISR register
----------------------------------------------------------------------
ISR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (iar(i) = '1')) then
isr(i) <= '0';
elsif (i < C_NUM_INTR_INPUTS) then
if (isr_en = '1') then
isr(i) <= isr_data_in(i);
end if;
elsif (i >= C_NUM_INTR_INPUTS) then
if (bus2ip_wrce(0) = '1') then
isr(i) <= Wr_data(i);
end if;
end if;
end if;
end process ISR_P;
----------------------------------------------------------------------
-- Process IMR_P for generating IMR(Interrrupt Mode Register) Register
----------------------------------------------------------------------
IMR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IMR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
imr(i) <= '0';
elsif bus2ip_wrce(8) = '1' then
imr(i) <= wr_data_int(i);
end if;
end if;
end process IMR_P;
end generate IMR_FAST_MODE_GEN;
-----------------------------------
end generate REG_GEN;
---------------------
---------------------------------------------------------------------------
-- Proces IVAR_REG_P for generating IVAR Registers
---------------------------------------------------------------------------
IVAR_FAST_MODE_GEN: if (C_HAS_FAST = 1) generate
-----
begin
-----
IVAR_REG_MEM_MB_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 0) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1_9.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Processor_clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_MB_CLK_GEN;
IVAR_REG_MEM_AXI_CLK_GEN: if (C_MB_CLK_NOT_CONNECTED = 1) generate
IVAR_REG_MEM_I: entity axi_intc_v4_1_9.shared_ram_ivar
generic map (
C_WIDTH => C_DWIDTH,
C_DPRAM_DEPTH => IVAR_MEM_DEPTH,
C_ADDR_LINES => IVAR_MEM_ADDR_LINES,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE
)
port map (
Addra => Reg_addr(IVAR_MEM_ADDR_LINES-1 downto 0),
Addrb => ivar_rd_addr_mb_clk(IVAR_MEM_ADDR_LINES-1 downto 0),
Clka => Clk,
Clkb => Clk,
Dina => wr_data,
--Dinb => (others => '0'),
--Ena => '1',
--Enb => '1',
Wea => write_ivar,
--Web => '0',
Douta => ivar_rd_data_axi_clk,
Doutb => ivar_rd_data_mb_clk
);
end generate IVAR_REG_MEM_AXI_CLK_GEN;
end generate IVAR_FAST_MODE_GEN;
-----------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR /= C_DWIDTH
-----------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR: if (C_NUM_INTR /= C_DWIDTH) generate
-----
begin
-----
ier_out(C_NUM_INTR - 1 downto 0) <= ier;
ier_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_out(C_NUM_INTR - 1 downto 0) <= isr;
isr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
imr_out(C_NUM_INTR - 1 downto 0) <= imr;
imr_out(C_DWIDTH - 1 downto C_NUM_INTR) <= (others => '0');
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-1 downto 0));
end generate REG_OUT_GEN_DWIDTH_NOT_EQ_NUM_INTR;
------------------------------------------------------------------------
-- Generating ier_out & isr_out if C_NUM_INTR = C_DWIDTH
------------------------------------------------------------------------
REG_OUT_GEN_DWIDTH_EQ_NUM_INTR: if (C_NUM_INTR = C_DWIDTH) generate
-----
begin
-----
ier_out <= ier;
isr_out <= isr;
imr_out <= imr;
isr_ored_30_0_bits <= or_reduce(isr(C_NUM_INTR-2 downto 0));
end generate REG_OUT_GEN_DWIDTH_EQ_NUM_INTR;
ilr_out (INDEX_BIT-1 downto 0) <= ilr(INDEX_BIT - 1 downto 0);
ilr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ilr(INDEX_BIT) = '1' else
(others => '0');
ivr_out (INDEX_BIT-1 downto 0) <= ivr;
ivr_out (C_DWIDTH-1 downto INDEX_BIT) <= (others => '1') when ((ivr = IVR_ALL_ONES)) else
(others => '0');
--------------------------------------------------------------------------
-- Generate IPR if (C_HAS_IPR = 1)
--------------------------------------------------------------------------
IPR_GEN: if (C_HAS_IPR = 1) generate
----------------------------------------------------------------------
-- Process IPR_P for generating IPR register
----------------------------------------------------------------------
IPR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ipr <= (others => '0');
else
ipr <= isr_out and ier_out;
end if;
end if;
end process IPR_P;
------------------
end generate IPR_GEN;
---------------------
--------------------------------------------------------------------------
-- Assign IPR ALL ZEROS if (C_HAS_IPR = 0)
--------------------------------------------------------------------------
IPR_NO_GEN: if (C_HAS_IPR = 0) generate
ipr <= (others => '0');
end generate IPR_NO_GEN;
--------------------------------------------------------------------------
-- Generate IVR if (C_HAS_IVR = 1 or C_HAS_FAST = 1)
--------------------------------------------------------------------------
IVR_GEN: if ((C_HAS_IVR = 1) or (C_HAS_FAST = 1)) generate
begin
----------------------------------------------------------------------
-- Process IVR_DATA_GEN_P for generating interrupt vector address
----------------------------------------------------------------------
IVR_DATA_GEN_P: process (isr, ier) is
variable ivr_in : std_logic_vector(INDEX_BIT - 1 downto 0)
:= (others => '1');
-----
begin
-----
for i in natural range 0 to (C_NUM_INTR - 1) loop
if ((isr(i) = '1') and (ier(i) = '1')) then
--ivr_in := CONV_STD_LOGIC_VECTOR(i, INDEX_BIT);
ivr_in := std_logic_vector(to_unsigned(i, INDEX_BIT));
exit;
else
ivr_in := (others => '1');
end if;
end loop;
ivr_data_in <= ivr_in;
end process IVR_DATA_GEN_P;
----------------------------------------------------------------------
-- Process IVR_P for generating IVR register
----------------------------------------------------------------------
IVR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivr <= (others => '1');
else
ivr <= ivr_data_in;
end if;
end if;
end process IVR_P;
end generate IVR_GEN;
--------------------------------------------------------------------------
-- Assign IVR ALL ONES if (C_HAS_IVR = 0) and (C_HAS_FAST = 0)
--------------------------------------------------------------------------
IVR_NO_GEN: if ((C_HAS_IVR = 0) and (C_HAS_FAST = 0)) generate
ivr <= (others => '1');
end generate IVR_NO_GEN;
--------------------------------------------------------------------------
-- Generate ILR if (C_HAS_ILR = 1)
--------------------------------------------------------------------------
ILR_GEN: if (C_HAS_ILR = 1) generate
begin
----------------------------------------------------------------------
-- Process ILR_P for generating ILR register
----------------------------------------------------------------------
ILR_P: process (Clk) is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ilr <= (others => '1');
elsif (bus2ip_wrce(9) = '1') then
ilr <= Wr_data(INDEX_BIT downto 0);
end if;
end if;
end process ILR_P;
end generate ILR_GEN;
--------------------------------------------------------------------------
-- Assign ILR ALL ONES if (C_HAS_ILR = 0)
--------------------------------------------------------------------------
ILR_NO_GEN: if (C_HAS_ILR = 0) generate
begin
ilr <= (others => '1');
end generate ILR_NO_GEN;
--------------------------------------------------------------------------
-- DETECTING HW INTERRUPT
--------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Detecting the interrupts
---------------------------------------------------------------------------
INTR_DETECT_GEN: for i in 0 to C_NUM_INTR_INPUTS - 1 generate
signal synced_intr : std_logic := '0';
begin
-----------------------------------------------------------------------
-- Generating the synchronization flip-flops if C_ASYNC_INTR(i) = 1
-----------------------------------------------------------------------
ASYNC_GEN: if C_ASYNC_INTR(i) = '1' and C_NUM_SYNC_FF > 0 generate
signal intr_ff : std_logic_vector(0 to C_NUM_SYNC_FF - 1) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of intr_ff : signal is "TRUE";
begin
--------------------------------------------
-- Process SYNC_P to synchronize hw_intr
--------------------------------------------
SYNC_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
intr_ff(0) <= Intr(i);
for k in intr_ff'left to intr_ff'right - 1 loop
intr_ff(k + 1) <= intr_ff(k);
end loop;
end if;
end process SYNC_P;
synced_intr <= intr_ff(intr_ff'right);
------------------------------
end generate ASYNC_GEN;
-----------------------------------------------------------------------
-- No synchronization flip-flops if C_ASYNC_INTR(i) = 0
-----------------------------------------------------------------------
SYNC_GEN: if C_ASYNC_INTR(i) = '0' or C_NUM_SYNC_FF = 0 generate
begin
synced_intr <= Intr(i);
end generate SYNC_GEN;
-----------------------------------------------------------------------
-- Generating the edge triggered interrupts if C_KIND_OF_INTR(i) = 1
-----------------------------------------------------------------------
EDGE_DETECT_GEN: if C_KIND_OF_INTR(i) = '1' generate
signal intr_d1 : std_logic;
signal intr_edge : std_logic;
begin
----------------------------------------------------------------
-- Process REG_INTR_EDGE_P to register the interrupt signal edge
----------------------------------------------------------------
REG_INTR_EDGE_P : process (Clk) is
begin
if(Clk'event and Clk='1') then
if Rst_n = RESET_ACTIVE then
intr_d1 <= not C_KIND_OF_EDGE(i);
else
intr_d1 <= synced_intr;
end if;
end if;
end process REG_INTR_EDGE_P;
-- Creating one-shot edge triggered interrupt
intr_edge <= '1' when (synced_intr = C_KIND_OF_EDGE(i)) and
(intr_d1 = not C_KIND_OF_EDGE(i)) else
'0';
-----------------------------------------------------------------
-- Process DETECT_INTR_P to generate the edge triggered interrupt
-----------------------------------------------------------------
DETECT_INTR_P : process (Clk) is
begin
if Clk'event and Clk='1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif (intr_edge = '1') then
hw_intr(i) <= '1';
end if;
end if;
end process DETECT_INTR_P;
--------------------------
end generate EDGE_DETECT_GEN;
----------------------------------------------------------------------
-- Generating the Level trigeered interrupts if C_KIND_OF_INTR(i) = 0
----------------------------------------------------------------------
LVL_DETECT_GEN: if C_KIND_OF_INTR(i) = '0' generate
begin
------------------------------------------------------------------
-- Process LVL_P to generate hw_intr (active high or low)
------------------------------------------------------------------
LVL_P : process (Clk) is
begin
if Clk'event and Clk = '1' then
if (Rst_n = RESET_ACTIVE) or (iar(i) = '1') then
hw_intr(i) <= '0';
elsif synced_intr = C_KIND_OF_LVL(i) then
hw_intr(i) <= '1';
end if;
end if;
end process LVL_P;
------------------
end generate LVL_DETECT_GEN;
end generate INTR_DETECT_GEN;
--------------------------------------------------------------------------
-- Checking Active Interrupt/Interrupts
--------------------------------------------------------------------------
IRQ_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
-----
begin
-----
irq_gen_i<= isr(0) and ier(0) and ilr(0);
end generate IRQ_ONE_INTR_GEN;
IRQ_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process IRQ_GEN_P to generate irq_gen
--------------------------------------------------------------
IRQ_GEN_P: process (isr, ier, ilr) is
variable ilr_value : integer;
variable irq_gen_int : std_logic;
-----
begin
-----
ilr_value := TO_INTEGER(unsigned( ilr(INDEX_BIT - 1 downto 0) ));
irq_gen_int := '0';
for i in 0 to (isr'length - 1) loop
if (C_HAS_ILR = 1) then
exit when (i = ilr_value) and (ilr(INDEX_BIT) = '0');
end if;
irq_gen_int := irq_gen_int or (isr(i) and ier(i));
end loop;
irq_gen_i <= irq_gen_int;
end process IRQ_GEN_P;
----------------------
end generate IRQ_MULTI_INTR_GEN;
--------------------------------
-- Registering irq_gen_i as it will be going through double synchronizer
IRQ_GEN_REG_P : Process(Clk)is
-----
begin
-----
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_gen <= '0';
else
irq_gen <= irq_gen_i;
end if;
end if;
end process IRQ_GEN_REG_P;
--------------------------
--------------------------------------------------------------
-- Synchronizing irq_gen
--------------------------------------------------------------
IRQ_GEN_SYNC_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
signal irq_gen_sync_vec : std_logic_vector(0 downto 0);
-----
begin
-----
-- Synchronize irq_gen to Processor clock domain
IRQ_GEN_DOUBLE_SYNC_I: entity axi_intc_v4_1_9.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(irq_gen),
SYNC_DATA_OUT => irq_gen_sync_vec
);
irq_gen_sync <= irq_gen_sync_vec(0);
end generate IRQ_GEN_SYNC_GEN;
IRQ_GEN_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
irq_gen_sync <= irq_gen;
end generate IRQ_GEN_SYNC_DISABLE_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-----
begin
-----
IN_IDLE_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
signal in_idle_axi_clk_vec : std_logic_vector(0 downto 0);
begin
IN_IDLE_DOUBLE_SYNC_I: entity axi_intc_v4_1_9.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Clk,
RESET_2_n => Rst_n,
DATA_IN => scalar_to_vector(in_idle),
SYNC_DATA_OUT => in_idle_axi_clk_vec
);
in_idle_axi_clk <= in_idle_axi_clk_vec(0);
end generate IN_IDLE_SYNC_EN_GEN;
---------------------------------
IN_IDLE_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
in_idle_axi_clk <= in_idle;
end generate IN_IDLE_SYNC_DISABLE_GEN;
--------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen_i and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
------------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
------------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
------------------------------------
IVAR_INDEX_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ivar_index_sample_en,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ivar_index_sample_en_mb_clk
);
end generate IVAR_INDEX_SYNC_EN_GEN;
------------------------------------
IVAR_INDEX_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
end generate IVAR_INDEX_SYNC_DISABLE_GEN;
------------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr_data_in;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
------------------------------------
IVAR_INDEX_MB_REG_P : Process(Processor_clk)
begin
if (Processor_clk'event and Processor_clk = '1') then
if (processor_rst_n = RESET_ACTIVE) then
ivar_index_mb_clk <= (others => '0');
else
if (ivar_index_sample_en_mb_clk = '1') then
ivar_index_mb_clk <= ivar_index_axi_clk;
else
ivar_index_mb_clk <= ivar_index_mb_clk;
end if;
end if;
end if;
end process IVAR_INDEX_MB_REG_P;
------------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
------------------------------------
end generate IVAR_INDEX_SYNC_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen_i;
IDLE_NOT_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_NOT_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
IRQ_DIS_SYNC_EN_GEN: if (C_DISABLE_SYNCHRONIZERS = 0) generate
IRQ_GEN_EDGE_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => irq_dis_sample,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => irq_dis_sample_mb_clk
);
end generate IRQ_DIS_SYNC_EN_GEN;
IRQ_DIS_SYNC_DISABLE_GEN: if (C_DISABLE_SYNCHRONIZERS = 1) generate
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_DISABLE_GEN;
end generate IRQ_DIS_SYNC_GEN;
---------------------------------------------------------------
-- Process to synchronize irq_gen and "ivar" to Processor Clock
---------------------------------------------------------------
IVAR_INDEX_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-----
begin
-----
in_idle_axi_clk <= in_idle;
------------------------------------
idle_and_irq <= in_idle_axi_clk and irq_gen and mer(0);
------------------------------------
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
idle_and_irq_d1 <= '0';
else
idle_and_irq_d1 <= idle_and_irq;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
--------------------------------
ivar_index_sample_en_i <= idle_and_irq and (not idle_and_irq_d1);
--------------------------------
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_sample_en <= '0';
else
ivar_index_sample_en <= ivar_index_sample_en_i;
end if;
end if;
end process SAMPLE_REG_P;
--------------------------------
ivar_index_sample_en_mb_clk <= ivar_index_sample_en;
--------------------------------
IVAR_INDEX_AXI_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ivar_index_axi_clk <= (others => '0');
else
if (ivar_index_sample_en_i = '1') then
ivar_index_axi_clk <= ivr;
else
ivar_index_axi_clk <= ivar_index_axi_clk;
end if;
end if;
end if;
end process IVAR_INDEX_AXI_REG_P;
--------------------------------
ivar_index_mb_clk <= ivar_index_axi_clk;
--------------------------------
ivar_rd_addr_mb_clk <= std_logic_vector(to_unsigned(TO_INTEGER(unsigned(ivar_index_mb_clk)), 5));
end generate IVAR_INDEX_SYNC_ON_AXI_CLK_GEN;
---------------------------------------------------------------------
-- Process to synchronize irq_gen disable to Processor Clock with ILR
---------------------------------------------------------------------
IRQ_DIS_SYNC_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1) and (C_HAS_ILR = 1)) generate
signal irq_dis : std_logic;
signal irq_dis_d1 : std_logic;
signal irq_dis_sample_i : std_logic;
signal irq_dis_sample : std_logic;
begin
irq_dis <= not irq_gen;
IDLE_IRQ_DELAY_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_d1 <= '0';
else
irq_dis_d1 <= irq_dis;
end if;
end if;
end process IDLE_IRQ_DELAY_P;
irq_dis_sample_i <= irq_dis and (not irq_dis_d1);
SAMPLE_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
irq_dis_sample <= '0';
else
irq_dis_sample <= irq_dis_sample_i;
end if;
end if;
end process SAMPLE_REG_P;
irq_dis_sample_mb_clk <= irq_dis_sample;
end generate IRQ_DIS_SYNC_ON_AXI_CLK_GEN;
NO_IRQ_DIS_SYNC: if (C_HAS_FAST = 0) or (C_HAS_ILR = 0) generate
begin
irq_dis_sample_mb_clk <= '0';
end generate NO_IRQ_DIS_SYNC;
----------------------------------------------------------------------
-- MER_0_DOUBLE_SYNC_I to synchronize MER(0) with Processor_clk
----------------------------------------------------------------------
MER_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
signal mer_0_sync_vec : std_logic_vector(0 downto 0);
begin
--Synchronize mer(0) to Processor clock domain
MER_0_DOUBLE_SYNC_I: entity axi_intc_v4_1_9.double_synchronizer
generic map (
C_DWIDTH => 1
)
port map (
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
DATA_IN => scalar_to_vector(mer(0)),
SYNC_DATA_OUT => mer_0_sync_vec
);
mer_0_sync <= mer_0_sync_vec(0);
end generate MER_SYNC_EN_GEN;
------------------------------
MER_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
mer_0_sync <= mer(0);
end generate MER_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating LEVEL interrupt if C_IRQ_IS_LEVEL = 1
--------------------------------------------------------------------------
IRQ_LEVEL_GEN: if (C_IRQ_IS_LEVEL = 1) generate
-- Level IRQ generation if C_HAS_FAST is 1
IRQ_LEVEL_FAST_ON_MB_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((ivar_index_sample_en_mb_clk = '1')) then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-----------------------------
GEN_LEVEL_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
-----------------------------
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
-- local signal declaration
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
end generate IRQ_LEVEL_FAST_ON_MB_CLK_GEN;
------------------------------------------------------------------
IRQ_LEVEL_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_LEVEL_IRQ, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_LEVEL_IRQ;
else
current_state <= IDLE;
end if;
when GEN_LEVEL_IRQ =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_LEVEL_IRQ;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_LEVEL_IRQ;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_LEVEL_IRQ) else
not C_IRQ_ACTIVE;
-------------------------------
GEN_LEVEL_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_LEVEL_IRQ_P;
----------------------------
-- Interrupt_address <= ivar_rd_data_mb_clk;
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
----------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
-------------------------------------------
end generate IRQ_LEVEL_FAST_ON_AXI_CLK_GEN;
-- Level IRQ generation if C_HAS_FAST is 0
IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_P: process (Processor_clk) is
begin
if(Processor_clk'event and Processor_clk = '1') then
if ((processor_rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_P;
-------------------------------------
Interrupt_address <= (others => '0');
-------------------------------------
end generate IRQ_LEVEL_NORMAL_ON_MB_CLK_GEN;
IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
--------------------------------------------------------------------
-- Process IRQ_LEVEL_P for generating LEVEL interrupt
--------------------------------------------------------------------
IRQ_LEVEL_ON_AXI_P: process (Clk) is
begin
if(Clk'event and Clk = '1') then
if ((Rst_n = RESET_ACTIVE) or (irq_gen_sync = '0')) then
Irq <= not C_IRQ_ACTIVE;
elsif ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
Irq <= C_IRQ_ACTIVE;
end if;
end if;
end process IRQ_LEVEL_ON_AXI_P;
Interrupt_address <= (others => '0');
end generate IRQ_LEVEL_NORMAL_ON_AXI_CLK_GEN;
end generate IRQ_LEVEL_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR = 1
----------------------------------------------------------------------
ACK_OR_ONE_INTR_GEN: if (C_NUM_INTR = 1) generate
ack_or_i <= iar(0);
end generate ACK_OR_ONE_INTR_GEN;
----------------------------------------------------------------------
-- Generating ack_or for C_NUM_INTR > 1
----------------------------------------------------------------------
ACK_OR_MULTI_INTR_GEN: if (C_NUM_INTR > 1) generate
-----
begin
-----
--------------------------------------------------------------
-- Process ACK_OR_GEN_P to generate ack_or (ORed Acks)
--------------------------------------------------------------
ACK_OR_GEN_P: process (iar)
variable ack_or_int : std_logic := '0';
begin
ack_or_int := iar(0);
for i in 1 to (iar'length - 1) loop
ack_or_int := ack_or_int or (iar(i));
end loop;
ack_or_i <= ack_or_int;
end process ACK_OR_GEN_P;
end generate ACK_OR_MULTI_INTR_GEN;
----------------------------------
ACK_OR_REG_P : Process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst_n = RESET_ACTIVE) then
ack_or <= '0';
else
ack_or <= ack_or_i;
end if;
end if;
end process ACK_OR_REG_P;
-------------------------
ACK_OR_SYNC_EN_GEN: if ((C_DISABLE_SYNCHRONIZERS = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
ACK_OR_PULSE_SYNC_I: entity axi_intc_v4_1_9.pulse_synchronizer
port map (
CLK_1 => Clk,
RESET_1_n => Rst_n,
DATA_IN => ack_or,
CLK_2 => Processor_clk,
RESET_2_n => processor_rst_n,
SYNC_DATA_OUT => ack_or_sync
);
end generate ACK_OR_SYNC_EN_GEN;
ACK_OR_SYNC_DISABLE_GEN: if ((C_DISABLE_SYNCHRONIZERS = 1) or (C_MB_CLK_NOT_CONNECTED = 1)) generate
ack_or_sync <= ack_or;
end generate ACK_OR_SYNC_DISABLE_GEN;
--------------------------------------------------------------------------
-- Generating EDGE interrupt if C_IRQ_IS_LEVEL = 0
--------------------------------------------------------------------------
IRQ_EDGE_GEN: if (C_IRQ_IS_LEVEL = 0) generate
IRQ_EDGE_FAST_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
GEN_IRQ_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Processor_clk)is
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------
end generate IRQ_EDGE_FAST_GEN;
IRQ_EDGE_FAST_ON_AXI_CLK_GEN: if ((C_HAS_FAST = 1) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
-- generate in_idle signal
GEN_IN_IDLE_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
in_idle <= '0';
else
if (current_state = IDLE) then
in_idle <= '1';
else
in_idle <= '0';
end if;
end if;
end if;
end process GEN_IN_IDLE_P;
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if (ivar_index_sample_en_mb_clk = '1') then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
if (imr(TO_INTEGER(unsigned(ivar_index_mb_clk))) = '1') then
if (first_ack = '1') then
current_state <= WAIT_ACK;
else
current_state <= GEN_PULSE;
end if;
else
if (ack_or_sync = '1') or (irq_dis_sample_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= GEN_PULSE;
end if;
end if;
when WAIT_ACK => if (second_ack_sync_mb_clk = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
---------------------------
Irq_i <= C_IRQ_ACTIVE when (current_state = GEN_PULSE) else
(not C_IRQ_ACTIVE);
---------------------------
GEN_IRQ_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
Irq <= Irq_i;
end if;
end if;
end process GEN_IRQ_P;
-----------------------
-- Interrupt_address <= ivar_rd_data_mb_clk; -- 09-09-2012
NO_CASCADE_IVAR_ADDRESS: -- if (C_CASCADE_MASTER = 0) generate
if (C_EN_CASCADE_MODE = 0) and (C_CASCADE_MASTER = 0) generate
begin
-----
Interrupt_address <= ivar_rd_data_mb_clk;
end generate NO_CASCADE_IVAR_ADDRESS;
-------------------------------------
CASCADE_IVAR_ADDRESS: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 0) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS;
---------------------------------------------------------------
CASCADE_IVAR_ADDRESS_MST_MD: if (C_EN_CASCADE_MODE = 1) and (C_CASCADE_MASTER = 1) generate
signal Interrupt_address_in_reg : std_logic_vector(31 downto 0);
-----
begin
-----
REG_IP_INTR_ADDR_IN: process(Clk)is
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Interrupt_address_in_reg <= (others => '0');
else
Interrupt_address_in_reg <= Interrupt_address_in;
end if;
end if;
end process REG_IP_INTR_ADDR_IN;
--------------------------------
Interrupt_address_in_reg_int <= Interrupt_address_in_reg;
--------------------------------
Interrupt_address <= Interrupt_address_in_reg when ((isr(31) = '1') and
(ier(31) = '1') and
(isr_ored_30_0_bits = '0')
)
else
ivar_rd_data_mb_clk;
end generate CASCADE_IVAR_ADDRESS_MST_MD;
---------------------------------------------------------------
end generate IRQ_EDGE_FAST_ON_AXI_CLK_GEN;
--IRQ_EDGE_NORMAL_GEN: if (C_HAS_FAST = 0) generate
IRQ_EDGE_NO_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 1)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
current_state <= IDLE;
else
current_state <= WAIT_ACK;
end if;
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Clk)
begin
if(Clk'event and Clk='1') then
if (Rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_NO_MB_CLK_GEN;
IRQ_EDGE_MB_CLK_GEN: if ((C_HAS_FAST = 0) and (C_MB_CLK_NOT_CONNECTED = 0)) generate
-- Type declaration
type STATE_TYPE is (IDLE, GEN_PULSE, WAIT_ACK, WAIT_SYNC);
-- Signal declaration
signal current_state : STATE_TYPE;
begin
--------------------------------------------------------------
--The sequential process below maintains the current_state
--------------------------------------------------------------
GEN_CS_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
current_state <= IDLE;
else
case current_state is
when IDLE => if ((irq_gen_sync = '1') and (mer_0_sync = '1')) then
current_state <= GEN_PULSE;
else
current_state <= IDLE;
end if;
when GEN_PULSE =>
current_state <= WAIT_ACK;
when WAIT_ACK => if (ack_or_sync = '1') then
if (C_DISABLE_SYNCHRONIZERS = 1) then
current_state <= IDLE;
else
current_state <= WAIT_SYNC;
end if;
else
current_state <= WAIT_ACK;
end if;
when WAIT_SYNC => current_state <= IDLE;
-- coverage off
when others => current_state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process GEN_CS_P;
GEN_IRQ_AND_ADDR_P : process (Processor_clk)
begin
if(Processor_clk'event and Processor_clk='1') then
if (processor_rst_n = RESET_ACTIVE) then
Irq <= (not C_IRQ_ACTIVE);
else
if (current_state = GEN_PULSE) then
Irq <= C_IRQ_ACTIVE;
else
Irq <= not C_IRQ_ACTIVE;
end if;
end if;
end if;
end process GEN_IRQ_AND_ADDR_P;
Interrupt_address <= (others => '0');
end generate IRQ_EDGE_MB_CLK_GEN;
--end generate IRQ_EDGE_NORMAL_GEN;
end generate IRQ_EDGE_GEN;
--Read data in Normal mode (C_HAS_FAST = 0)
OUTPUT_DATA_NORMAL_GEN: if (C_HAS_FAST = 0) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read, Reg_addr, isr_out, ipr, ier_out,
ilr_out, ivr_out, mer) is
-----
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate OUTPUT_DATA_NORMAL_GEN;
--Read data in mixed mode (C_HAS_FAST = 1) and C_EN_CASCADE_MODE = 1 and C_CASCADE_MASTER = 1
CASCADE_OP_DATA_FAST_GEN: if ((C_HAS_FAST = 1) and
(C_EN_CASCADE_MODE = 1)
) generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk,
Interrupt_address_in_reg_int,
ier ,
isr ,
isr_ored_30_0_bits) is
begin
-----
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then -- read IVAR of 31st bit in case the interrupt is present
if((isr(31) = '1') and -- else to read IVAR of lower modules the processor has to
(ier(31) = '1') and -- initiate the transaction for lower module separately
(isr_ored_30_0_bits = '0')
)then
Rd_data <= Interrupt_address_in_reg_int;
else
Rd_data <= ivar_rd_data_axi_clk;
end if;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
NO_CASCADE_OP_DATA_FAST_GEN: if (C_HAS_FAST = 1) and
(C_CASCADE_MASTER = 0) and
(C_EN_CASCADE_MODE = 0)
generate
-----
begin
-----
------------------------------------------------------------------------
-- Process OUTPUT_DATA_GEN_P for generating Rd_data
------------------------------------------------------------------------
OUTPUT_DATA_GEN_P: process (read ,
read_ivar ,
Reg_addr ,
isr_out ,
ipr ,
ier_out ,
ilr_out ,
ivr_out ,
mer ,
imr_out ,
ivar_rd_data_axi_clk) is
begin
if (read = '1') then
case Reg_addr(6 downto 0) is
when "0000000" => Rd_data <= isr_out; -- ISR (R/W)
when "0000001" => Rd_data <= ipr; -- IPR (Read only)
when "0000010" => Rd_data <= ier_out; -- IER (R/W)
when "0000110" => Rd_data <= ivr_out; -- IVR (Read only)
when "0000111" => Rd_data <= mer; -- MER (R/W)
when "0001000" => Rd_data <= imr_out; -- IMR (R/W)
when "0001001" => Rd_data <= ilr_out; -- ILR (R(W)
-- IAR, SIE, CIE (Write only)
-- coverage off
when others => Rd_data <= (others => '0');
-- coverage on
end case;
elsif (read_ivar = '1') then
Rd_data <= ivar_rd_data_axi_clk;
else
Rd_data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
end generate NO_CASCADE_OP_DATA_FAST_GEN;
--------------------------------------------------------------------------
end imp;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_intc.vhd
-- Version: v3.1
-- Description: Interrupt controller interfaced to AXI.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_intc.vhd (wrapper for top level)
-- -- axi_lite_ipif.vhd
-- -- intc_core.vhd
--
-------------------------------------------------------------------------------
-- Author: PB
-- History:
-- PB 07/29/09
-- ^^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
-- PB 03/26/10
--
-- - updated based on the xps_intc_v2_01_a
-- PB 09/21/10
--
-- - updated the axi_lite_ipif from v1.00.a to v1.01.a
-- ~~~~~~
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-- ^^^^^^^
-- SA 03/25/13
--
-- 1. Added software interrupt support
-- ~~~~~~
-- SA 09/05/13
--
-- 1. Added support for nested interrupts using ILR register in v4.1
-- ~~~~~~
-- SA 12/26/15
--
-- 1. Simplified cascade connections by adding Irq_in port
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------
-- Library axi_lite_ipif_v3_0_4 is used because it contains the
-- axi_lite_ipif which interraces intc_core to AXI.
-------------------------------------------------------------------------
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------
-- Library axi_intc_v4_1_9 is used because it contains the intc_core.
-- The complete interrupt controller logic is designed in intc_core.
-------------------------------------------------------------------------
library axi_intc_v4_1_9;
use axi_intc_v4_1_9.intc_core;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- System Parameter
-- C_FAMILY -- Target FPGA family
-- AXI Parameters
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- Intc Parameters
-- C_NUM_INTR_INPUTS -- Number of interrupt inputs
-- C_NUM_SW_INTR -- Number of software interrupts
-- C_KIND_OF_INTR -- Kind of interrupt (0-Level/1-Edge)
-- C_KIND_OF_EDGE -- Kind of edge (0-falling/1-rising)
-- C_KIND_OF_LVL -- Kind of level (0-low/1-high)
-- C_ASYNC_INTR -- Interrupt is asynchronous (0-sync/1-async)
-- C_NUM_SYNC_FF -- Number of synchronization flip-flops for async interrupts
-- C_HAS_IPR -- Set to 1 if has Interrupt Pending Register
-- C_HAS_SIE -- Set to 1 if has Set Interrupt Enable Bits Register
-- C_HAS_CIE -- Set to 1 if has Clear Interrupt Enable Bits Register
-- C_HAS_IVR -- Set to 1 if has Interrupt Vector Register
-- C_HAS_ILR -- Set to 1 if has Interrupt Level Register for nested interupt support
-- C_IRQ_IS_LEVEL -- If set to 0 generates edge interrupt
-- -- If set to 1 generates level interrupt
-- C_IRQ_ACTIVE -- Defines the edge for output interrupt if
-- -- C_IRQ_IS_LEVEL=0 (0-FALLING/1-RISING)
-- -- Defines the level for output interrupt if
-- -- C_IRQ_IS_LEVEL=1 (0-LOW/1-HIGH)
-- C_IVR_RESET_VALUE -- Reset value for the vectroed interrupt registers in RAM
-- C_DISABLE_SYNCHRONIZERS -- If the processor clock and axi clock are of same
-- value then user can decide to disable this
-- C_MB_CLK_NOT_CONNECTED -- If the processor clock is not connected or used in design
-- C_HAS_FAST -- If user wants to choose the fast interrupt mode of the core
-- -- then it is needed to have this paraemter set. Default is Standard Mode interrupt
-- C_ENABLE_ASYNC -- This parameter is used only for Vivado standalone mode of the core, not used in RTL
-- C_EN_CASCADE_MODE -- If no. of interrupts goes beyond 32, then this parameter need to set
-- C_CASCADE_MASTER -- If cascade mode is set, then this parameter should be set to the first instance
-- -- of the core which is connected to the processor
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clocks and reset
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - Active Low Reset
-- Axi interface signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Intc Interface Signals
-- intr -- Input Interruput request
-- irq -- Output Interruput request
-- processor_clk -- in put same as processor clock
-- processor_rst -- in put same as processor reset
-- processor_ack -- input Connected to processor ACK
-- interrupt_address -- output Connected to processor interrupt address pins
-- interrupt_address_in-- Input this is coming from lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-- processor_ack_out -- Output this is going to lower level module in case
-- -- the cascade mode is set and all AXI INTC instances are marked
-- -- as C_HAS_FAST = 1
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity axi_intc is
generic
(
-- System Parameter
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_intc_inst";
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 9; -- 9
C_S_AXI_DATA_WIDTH : integer := 32;
-- Intc Parameters
C_NUM_INTR_INPUTS : integer range 1 to 32 := 2;
C_NUM_SW_INTR : integer range 0 to 31 := 0;
C_KIND_OF_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_EDGE : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_KIND_OF_LVL : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_ASYNC_INTR : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
C_NUM_SYNC_FF : integer range 0 to 7 := 2;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000";
C_HAS_IPR : integer range 0 to 1 := 1;
C_HAS_SIE : integer range 0 to 1 := 1;
C_HAS_CIE : integer range 0 to 1 := 1;
C_HAS_IVR : integer range 0 to 1 := 1;
C_HAS_ILR : integer range 0 to 1 := 0;
C_IRQ_IS_LEVEL : integer range 0 to 1 := 1;
C_IRQ_ACTIVE : std_logic := '1';
C_DISABLE_SYNCHRONIZERS : integer range 0 to 1 := 0;
C_MB_CLK_NOT_CONNECTED : integer range 0 to 1 := 1;
C_HAS_FAST : integer range 0 to 1 := 0;
-- The below parameter is unused in RTL but required in Vivado Native
C_ENABLE_ASYNC : integer range 0 to 1 := 0; --not used for EDK, used only for Vivado
--
C_EN_CASCADE_MODE : integer range 0 to 1 := 0; -- default no cascade mode, if set enable cascade mode
C_CASCADE_MASTER : integer range 0 to 1 := 0 -- default slave, if set become cascade master and connects ports to Processor
--
);
port
(
-- system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi interface signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector (8 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Intc Interface signals
intr : in std_logic_vector(C_NUM_INTR_INPUTS-1 downto 0);
processor_clk : in std_logic; --- MB Clk, clock from MicroBlaze
processor_rst : in std_logic; --- MB rst, reset from MicroBlaze
irq : out std_logic;
processor_ack : in std_logic_vector(1 downto 0);
interrupt_address : out std_logic_vector(31 downto 0);
-- Cascade Interface signals
irq_in : in std_logic;
interrupt_address_in : in std_logic_vector(31 downto 0);
processor_ack_out : out std_logic_vector(1 downto 0)
--
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of S_AXI_ACLK : signal is "10000";
ATTRIBUTE MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
-- SIGIS attribute for specifying clocks,interrupts,resets for EDK
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of axi_intc : entity is "LOGICORE";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of axi_intc : entity is "PERIPHERAL";
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of axi_intc : entity is "VHDL";
ATTRIBUTE STYLE : string;
ATTRIBUTE STYLE of axi_intc : entity is "HDL";
ATTRIBUTE IMP_NETLIST : string;
ATTRIBUTE IMP_NETLIST of axi_intc : entity is "TRUE";
ATTRIBUTE RUN_NGCBUILD : string;
ATTRIBUTE RUN_NGCBUILD of axi_intc : entity is "TRUE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of S_AXI_ACLK : signal is "Clk";
ATTRIBUTE SIGIS of S_AXI_ARESETN : signal is "Rstn";
end axi_intc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_intc is
---------------------------------------------------------------------------
-- Constant Declarations
---------------------------------------------------------------------------
function calc_num_intr_inputs return integer is
begin -- function calc_num_intr_inputs
if C_EN_CASCADE_MODE = 1 and C_NUM_INTR_INPUTS = 31 then
return 32; -- add input for cascaded interrupt from Irq_in
end if;
return C_NUM_INTR_INPUTS;
end function calc_num_intr_inputs;
constant ZERO_ADDR_PAD : std_logic_vector(31 downto 0)
:= (others => '0');
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE := (0 => 1);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= (
ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & (X"00000000" or X"0000003F"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"00000100"), --- changed the high address
ZERO_ADDR_PAD & (X"00000000" or X"0000017F") --- changed the high address
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (16, 1); --- changed no. of chip enables
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000017F"; --- changed min memory size required
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 8;
constant RESET_ACTIVE : std_logic := '0';
constant NUM_INTR_INPUTS : integer := calc_num_intr_inputs;
---------------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------------
signal register_addr : std_logic_vector(6 downto 0); -- changed
signal read_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal write_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector((
(ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector(
calc_num_ce(ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal word_access : std_logic;
signal ip2bus_rdack_int : std_logic;
signal ip2bus_wrack_int : std_logic;
signal ip2bus_rdack_int_d1 : std_logic;
signal ip2bus_wrack_int_d1 : std_logic;
signal ip2bus_rdack_prev2 : std_logic;
signal ip2bus_wrack_prev2 : std_logic;
signal intr_i : std_logic_vector(NUM_INTR_INPUTS-1 downto 0);
function Or128_vec2stdlogic (vec_in : std_logic_vector) return std_logic is
variable or_out : std_logic := '0';
begin
for i in 0 to 16 loop
or_out := vec_in(i) or or_out;
end loop;
return or_out;
end function Or128_vec2stdlogic;
------------------------------------------------------------------------------
-----
begin
-----
assert C_NUM_SW_INTR + C_NUM_INTR_INPUTS <= 32
report "C_NUM_SW_INTR + C_NUM_INTR_INPUTS must be less than or equal to 32"
severity error;
register_addr <= bus2ip_addr(8 downto 2); -- changed the range as no. of register increased
--- Internal ack signals
ip2bus_rdack_int <= Or128_vec2stdlogic(bus2ip_rdce); -- changed, utilized function as no. chip enables increased
ip2bus_wrack_int <= Or128_vec2stdlogic(bus2ip_wrce); -- changed, utilized function as no. chip enables increased
-- Error signal generation
word_access <= bus2ip_be(0) and
bus2ip_be(1) and
bus2ip_be(2) and
bus2ip_be(3);
ip2bus_error <= not word_access;
-- Intr input signal generation
Combine_Intr: process (Intr, Irq_in) is
begin -- process Combine_Intr
intr_i(C_NUM_INTR_INPUTS - 1 downto 0) <= Intr;
if C_EN_CASCADE_MODE = 1 and C_NUM_INTR_INPUTS = 31 then
intr_i(NUM_INTR_INPUTS - 1) <= Irq_in;
end if;
end process Combine_Intr;
--------------------------------------------------------------------------
-- Process DACK_DELAY_P for generating write and read data acknowledge
-- signals.
--------------------------------------------------------------------------
DACK_DELAY_P: process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk='1' then
if bus2ip_resetn = RESET_ACTIVE then
ip2bus_rdack_int_d1 <= '0';
ip2bus_wrack_int_d1 <= '0';
ip2bus_rdack <= '0';
ip2bus_wrack <= '0';
else
ip2bus_rdack_int_d1 <= ip2bus_rdack_int;
ip2bus_wrack_int_d1 <= ip2bus_wrack_int;
ip2bus_rdack <= ip2bus_rdack_prev2;
ip2bus_wrack <= ip2bus_wrack_prev2;
end if;
end if;
end process DACK_DELAY_P;
-- Detecting rising edge by creating one shot
ip2bus_rdack_prev2 <= ip2bus_rdack_int and (not ip2bus_rdack_int_d1);
ip2bus_wrack_prev2 <= ip2bus_wrack_int and (not ip2bus_wrack_int_d1);
---------------------------------------------------------------------------
-- Component Instantiations
---------------------------------------------------------------------------
-----------------------------------------------------------------
-- Instantiating intc_core from axi_intc_v4_1_9
-----------------------------------------------------------------
INTC_CORE_I : entity axi_intc_v4_1_9.intc_core
generic map
(
C_FAMILY => C_FAMILY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_INTR_INPUTS => NUM_INTR_INPUTS,
C_NUM_SW_INTR => C_NUM_SW_INTR,
C_KIND_OF_INTR => C_KIND_OF_INTR,
C_KIND_OF_EDGE => C_KIND_OF_EDGE,
C_KIND_OF_LVL => C_KIND_OF_LVL,
C_ASYNC_INTR => C_ASYNC_INTR,
C_NUM_SYNC_FF => C_NUM_SYNC_FF,
C_HAS_IPR => C_HAS_IPR,
C_HAS_SIE => C_HAS_SIE,
C_HAS_CIE => C_HAS_CIE,
C_HAS_IVR => C_HAS_IVR,
C_HAS_ILR => C_HAS_ILR,
C_IRQ_IS_LEVEL => C_IRQ_IS_LEVEL,
C_IRQ_ACTIVE => C_IRQ_ACTIVE,
C_DISABLE_SYNCHRONIZERS => C_DISABLE_SYNCHRONIZERS,
C_MB_CLK_NOT_CONNECTED => C_MB_CLK_NOT_CONNECTED,
C_HAS_FAST => C_HAS_FAST,
C_IVAR_RESET_VALUE => C_IVAR_RESET_VALUE,
--
C_EN_CASCADE_MODE => C_EN_CASCADE_MODE,
C_CASCADE_MASTER => C_CASCADE_MASTER
--
)
port map
(
-- Intc Interface Signals
Clk => bus2ip_clk,
Rst_n => bus2ip_resetn,
Intr => intr_i,
Reg_addr => register_addr,
Bus2ip_rdce => bus2ip_rdce,
Bus2ip_wrce => bus2ip_wrce,
Wr_data => write_data,
Rd_data => read_data,
Processor_clk => processor_clk,
Processor_rst => processor_rst,
Irq => Irq,
Processor_ack => processor_ack,
Interrupt_address => interrupt_address,
Interrupt_address_in => interrupt_address_in,
Processor_ack_out => processor_ack_out
);
-----------------------------------------------------------------
--Instantiating axi_lite_ipif from axi_lite_ipif_v3_0_4
-----------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
--System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
-- AXI interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- Controls to the IP/IPIF modules
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
Bus2IP_Data => write_data,
IP2Bus_Data => read_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error
);
end imp;
|
apache-2.0
|
de26e72d45743ed2f8df6898eecb5219
| 0.39779 | 4.775138 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/WindowsManager_tb.vhd
| 1 | 1,926 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY WindowsManager_tb IS
END WindowsManager_tb;
ARCHITECTURE behavior OF WindowsManager_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT WindowsManager
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic;
nRs1 : OUT std_logic_vector(5 downto 0);
nRs2 : OUT std_logic_vector(5 downto 0);
nRd : OUT std_logic_vector(5 downto 0);
nCWP : OUT std_logic
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal rd : std_logic_vector(4 downto 0) := (others => '0');
signal op : std_logic_vector(1 downto 0) := (others => '0');
signal op3 : std_logic_vector(5 downto 0) := (others => '0');
signal CWP : std_logic := '0';
--Outputs
signal nRs1 : std_logic_vector(5 downto 0);
signal nRs2 : std_logic_vector(5 downto 0);
signal nRd : std_logic_vector(5 downto 0);
signal nCWP : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: WindowsManager PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
op => op,
op3 => op3,
CWP => CWP,
nRs1 => nRs1,
nRs2 => nRs2,
nRd => nRd,
nCWP => nCWP
);
-- Stimulus process
stim_proc: process
begin
rs1<="01000";
rs2<="10000";
rd<="11000";
op<="10";
op3<="000000";
CWP<='0';
wait for 20 ns;
CWP<='1';
wait for 20 ns;
op3<="111100";
wait;
end process;
END;
|
mit
|
c8b472f3bfa25e3b34361a6e5d451d61
| 0.531672 | 3.47027 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_mdm_1_0/synth/system_mdm_1_0.vhd
| 1 | 96,824 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mdm:3.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mdm_v3_2_8;
USE mdm_v3_2_8.MDM;
ENTITY system_mdm_1_0 IS
PORT (
Debug_SYS_Rst : OUT STD_LOGIC;
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Disable_0 : OUT STD_LOGIC
);
END system_mdm_1_0;
ARCHITECTURE system_mdm_1_0_arch OF system_mdm_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_mdm_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT MDM IS
GENERIC (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_USE_BSCAN : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_INTERCONNECT : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_DBG_REG_ACCESS : INTEGER;
C_DBG_MEM_ACCESS : INTEGER;
C_USE_CROSS_TRIGGER : INTEGER;
C_TRACE_OUTPUT : INTEGER;
C_TRACE_DATA_WIDTH : INTEGER;
C_TRACE_CLK_FREQ_HZ : INTEGER;
C_TRACE_CLK_OUT_PHASE : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_THREAD_ID_WIDTH : INTEGER;
C_DATA_SIZE : INTEGER;
C_M_AXIS_DATA_WIDTH : INTEGER;
C_M_AXIS_ID_WIDTH : INTEGER
);
PORT (
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
Interrupt : OUT STD_LOGIC;
Ext_BRK : OUT STD_LOGIC;
Ext_NM_BRK : OUT STD_LOGIC;
Debug_SYS_Rst : OUT STD_LOGIC;
Trig_In_0 : IN STD_LOGIC;
Trig_Ack_In_0 : OUT STD_LOGIC;
Trig_Out_0 : OUT STD_LOGIC;
Trig_Ack_Out_0 : IN STD_LOGIC;
Trig_In_1 : IN STD_LOGIC;
Trig_Ack_In_1 : OUT STD_LOGIC;
Trig_Out_1 : OUT STD_LOGIC;
Trig_Ack_Out_1 : IN STD_LOGIC;
Trig_In_2 : IN STD_LOGIC;
Trig_Ack_In_2 : OUT STD_LOGIC;
Trig_Out_2 : OUT STD_LOGIC;
Trig_Ack_Out_2 : IN STD_LOGIC;
Trig_In_3 : IN STD_LOGIC;
Trig_Ack_In_3 : OUT STD_LOGIC;
Trig_Out_3 : OUT STD_LOGIC;
Trig_Ack_Out_3 : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC;
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC;
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC;
LMB_Data_Addr_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_0 : OUT STD_LOGIC;
LMB_Ready_0 : IN STD_LOGIC;
LMB_Byte_Enable_0 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_0 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_0 : OUT STD_LOGIC;
LMB_Write_Strobe_0 : OUT STD_LOGIC;
LMB_CE_0 : IN STD_LOGIC;
LMB_UE_0 : IN STD_LOGIC;
LMB_Wait_0 : IN STD_LOGIC;
LMB_Data_Addr_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_1 : OUT STD_LOGIC;
LMB_Ready_1 : IN STD_LOGIC;
LMB_Byte_Enable_1 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_1 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_1 : OUT STD_LOGIC;
LMB_Write_Strobe_1 : OUT STD_LOGIC;
LMB_CE_1 : IN STD_LOGIC;
LMB_UE_1 : IN STD_LOGIC;
LMB_Wait_1 : IN STD_LOGIC;
LMB_Data_Addr_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_2 : OUT STD_LOGIC;
LMB_Ready_2 : IN STD_LOGIC;
LMB_Byte_Enable_2 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_2 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_2 : OUT STD_LOGIC;
LMB_Write_Strobe_2 : OUT STD_LOGIC;
LMB_CE_2 : IN STD_LOGIC;
LMB_UE_2 : IN STD_LOGIC;
LMB_Wait_2 : IN STD_LOGIC;
LMB_Data_Addr_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_3 : OUT STD_LOGIC;
LMB_Ready_3 : IN STD_LOGIC;
LMB_Byte_Enable_3 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_3 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_3 : OUT STD_LOGIC;
LMB_Write_Strobe_3 : OUT STD_LOGIC;
LMB_CE_3 : IN STD_LOGIC;
LMB_UE_3 : IN STD_LOGIC;
LMB_Wait_3 : IN STD_LOGIC;
LMB_Data_Addr_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_4 : OUT STD_LOGIC;
LMB_Ready_4 : IN STD_LOGIC;
LMB_Byte_Enable_4 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_4 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_4 : OUT STD_LOGIC;
LMB_Write_Strobe_4 : OUT STD_LOGIC;
LMB_CE_4 : IN STD_LOGIC;
LMB_UE_4 : IN STD_LOGIC;
LMB_Wait_4 : IN STD_LOGIC;
LMB_Data_Addr_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_5 : OUT STD_LOGIC;
LMB_Ready_5 : IN STD_LOGIC;
LMB_Byte_Enable_5 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_5 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_5 : OUT STD_LOGIC;
LMB_Write_Strobe_5 : OUT STD_LOGIC;
LMB_CE_5 : IN STD_LOGIC;
LMB_UE_5 : IN STD_LOGIC;
LMB_Wait_5 : IN STD_LOGIC;
LMB_Data_Addr_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_6 : OUT STD_LOGIC;
LMB_Ready_6 : IN STD_LOGIC;
LMB_Byte_Enable_6 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_6 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_6 : OUT STD_LOGIC;
LMB_Write_Strobe_6 : OUT STD_LOGIC;
LMB_CE_6 : IN STD_LOGIC;
LMB_UE_6 : IN STD_LOGIC;
LMB_Wait_6 : IN STD_LOGIC;
LMB_Data_Addr_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_7 : OUT STD_LOGIC;
LMB_Ready_7 : IN STD_LOGIC;
LMB_Byte_Enable_7 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_7 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_7 : OUT STD_LOGIC;
LMB_Write_Strobe_7 : OUT STD_LOGIC;
LMB_CE_7 : IN STD_LOGIC;
LMB_UE_7 : IN STD_LOGIC;
LMB_Wait_7 : IN STD_LOGIC;
LMB_Data_Addr_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_8 : OUT STD_LOGIC;
LMB_Ready_8 : IN STD_LOGIC;
LMB_Byte_Enable_8 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_8 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_8 : OUT STD_LOGIC;
LMB_Write_Strobe_8 : OUT STD_LOGIC;
LMB_CE_8 : IN STD_LOGIC;
LMB_UE_8 : IN STD_LOGIC;
LMB_Wait_8 : IN STD_LOGIC;
LMB_Data_Addr_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_9 : OUT STD_LOGIC;
LMB_Ready_9 : IN STD_LOGIC;
LMB_Byte_Enable_9 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_9 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_9 : OUT STD_LOGIC;
LMB_Write_Strobe_9 : OUT STD_LOGIC;
LMB_CE_9 : IN STD_LOGIC;
LMB_UE_9 : IN STD_LOGIC;
LMB_Wait_9 : IN STD_LOGIC;
LMB_Data_Addr_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_10 : OUT STD_LOGIC;
LMB_Ready_10 : IN STD_LOGIC;
LMB_Byte_Enable_10 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_10 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_10 : OUT STD_LOGIC;
LMB_Write_Strobe_10 : OUT STD_LOGIC;
LMB_CE_10 : IN STD_LOGIC;
LMB_UE_10 : IN STD_LOGIC;
LMB_Wait_10 : IN STD_LOGIC;
LMB_Data_Addr_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_11 : OUT STD_LOGIC;
LMB_Ready_11 : IN STD_LOGIC;
LMB_Byte_Enable_11 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_11 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_11 : OUT STD_LOGIC;
LMB_Write_Strobe_11 : OUT STD_LOGIC;
LMB_CE_11 : IN STD_LOGIC;
LMB_UE_11 : IN STD_LOGIC;
LMB_Wait_11 : IN STD_LOGIC;
LMB_Data_Addr_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_12 : OUT STD_LOGIC;
LMB_Ready_12 : IN STD_LOGIC;
LMB_Byte_Enable_12 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_12 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_12 : OUT STD_LOGIC;
LMB_Write_Strobe_12 : OUT STD_LOGIC;
LMB_CE_12 : IN STD_LOGIC;
LMB_UE_12 : IN STD_LOGIC;
LMB_Wait_12 : IN STD_LOGIC;
LMB_Data_Addr_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_13 : OUT STD_LOGIC;
LMB_Ready_13 : IN STD_LOGIC;
LMB_Byte_Enable_13 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_13 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_13 : OUT STD_LOGIC;
LMB_Write_Strobe_13 : OUT STD_LOGIC;
LMB_CE_13 : IN STD_LOGIC;
LMB_UE_13 : IN STD_LOGIC;
LMB_Wait_13 : IN STD_LOGIC;
LMB_Data_Addr_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_14 : OUT STD_LOGIC;
LMB_Ready_14 : IN STD_LOGIC;
LMB_Byte_Enable_14 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_14 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_14 : OUT STD_LOGIC;
LMB_Write_Strobe_14 : OUT STD_LOGIC;
LMB_CE_14 : IN STD_LOGIC;
LMB_UE_14 : IN STD_LOGIC;
LMB_Wait_14 : IN STD_LOGIC;
LMB_Data_Addr_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_15 : OUT STD_LOGIC;
LMB_Ready_15 : IN STD_LOGIC;
LMB_Byte_Enable_15 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_15 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_15 : OUT STD_LOGIC;
LMB_Write_Strobe_15 : OUT STD_LOGIC;
LMB_CE_15 : IN STD_LOGIC;
LMB_UE_15 : IN STD_LOGIC;
LMB_Wait_15 : IN STD_LOGIC;
LMB_Data_Addr_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_16 : OUT STD_LOGIC;
LMB_Ready_16 : IN STD_LOGIC;
LMB_Byte_Enable_16 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_16 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_16 : OUT STD_LOGIC;
LMB_Write_Strobe_16 : OUT STD_LOGIC;
LMB_CE_16 : IN STD_LOGIC;
LMB_UE_16 : IN STD_LOGIC;
LMB_Wait_16 : IN STD_LOGIC;
LMB_Data_Addr_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_17 : OUT STD_LOGIC;
LMB_Ready_17 : IN STD_LOGIC;
LMB_Byte_Enable_17 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_17 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_17 : OUT STD_LOGIC;
LMB_Write_Strobe_17 : OUT STD_LOGIC;
LMB_CE_17 : IN STD_LOGIC;
LMB_UE_17 : IN STD_LOGIC;
LMB_Wait_17 : IN STD_LOGIC;
LMB_Data_Addr_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_18 : OUT STD_LOGIC;
LMB_Ready_18 : IN STD_LOGIC;
LMB_Byte_Enable_18 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_18 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_18 : OUT STD_LOGIC;
LMB_Write_Strobe_18 : OUT STD_LOGIC;
LMB_CE_18 : IN STD_LOGIC;
LMB_UE_18 : IN STD_LOGIC;
LMB_Wait_18 : IN STD_LOGIC;
LMB_Data_Addr_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_19 : OUT STD_LOGIC;
LMB_Ready_19 : IN STD_LOGIC;
LMB_Byte_Enable_19 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_19 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_19 : OUT STD_LOGIC;
LMB_Write_Strobe_19 : OUT STD_LOGIC;
LMB_CE_19 : IN STD_LOGIC;
LMB_UE_19 : IN STD_LOGIC;
LMB_Wait_19 : IN STD_LOGIC;
LMB_Data_Addr_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_20 : OUT STD_LOGIC;
LMB_Ready_20 : IN STD_LOGIC;
LMB_Byte_Enable_20 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_20 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_20 : OUT STD_LOGIC;
LMB_Write_Strobe_20 : OUT STD_LOGIC;
LMB_CE_20 : IN STD_LOGIC;
LMB_UE_20 : IN STD_LOGIC;
LMB_Wait_20 : IN STD_LOGIC;
LMB_Data_Addr_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_21 : OUT STD_LOGIC;
LMB_Ready_21 : IN STD_LOGIC;
LMB_Byte_Enable_21 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_21 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_21 : OUT STD_LOGIC;
LMB_Write_Strobe_21 : OUT STD_LOGIC;
LMB_CE_21 : IN STD_LOGIC;
LMB_UE_21 : IN STD_LOGIC;
LMB_Wait_21 : IN STD_LOGIC;
LMB_Data_Addr_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_22 : OUT STD_LOGIC;
LMB_Ready_22 : IN STD_LOGIC;
LMB_Byte_Enable_22 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_22 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_22 : OUT STD_LOGIC;
LMB_Write_Strobe_22 : OUT STD_LOGIC;
LMB_CE_22 : IN STD_LOGIC;
LMB_UE_22 : IN STD_LOGIC;
LMB_Wait_22 : IN STD_LOGIC;
LMB_Data_Addr_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_23 : OUT STD_LOGIC;
LMB_Ready_23 : IN STD_LOGIC;
LMB_Byte_Enable_23 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_23 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_23 : OUT STD_LOGIC;
LMB_Write_Strobe_23 : OUT STD_LOGIC;
LMB_CE_23 : IN STD_LOGIC;
LMB_UE_23 : IN STD_LOGIC;
LMB_Wait_23 : IN STD_LOGIC;
LMB_Data_Addr_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_24 : OUT STD_LOGIC;
LMB_Ready_24 : IN STD_LOGIC;
LMB_Byte_Enable_24 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_24 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_24 : OUT STD_LOGIC;
LMB_Write_Strobe_24 : OUT STD_LOGIC;
LMB_CE_24 : IN STD_LOGIC;
LMB_UE_24 : IN STD_LOGIC;
LMB_Wait_24 : IN STD_LOGIC;
LMB_Data_Addr_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_25 : OUT STD_LOGIC;
LMB_Ready_25 : IN STD_LOGIC;
LMB_Byte_Enable_25 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_25 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_25 : OUT STD_LOGIC;
LMB_Write_Strobe_25 : OUT STD_LOGIC;
LMB_CE_25 : IN STD_LOGIC;
LMB_UE_25 : IN STD_LOGIC;
LMB_Wait_25 : IN STD_LOGIC;
LMB_Data_Addr_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_26 : OUT STD_LOGIC;
LMB_Ready_26 : IN STD_LOGIC;
LMB_Byte_Enable_26 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_26 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_26 : OUT STD_LOGIC;
LMB_Write_Strobe_26 : OUT STD_LOGIC;
LMB_CE_26 : IN STD_LOGIC;
LMB_UE_26 : IN STD_LOGIC;
LMB_Wait_26 : IN STD_LOGIC;
LMB_Data_Addr_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_27 : OUT STD_LOGIC;
LMB_Ready_27 : IN STD_LOGIC;
LMB_Byte_Enable_27 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_27 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_27 : OUT STD_LOGIC;
LMB_Write_Strobe_27 : OUT STD_LOGIC;
LMB_CE_27 : IN STD_LOGIC;
LMB_UE_27 : IN STD_LOGIC;
LMB_Wait_27 : IN STD_LOGIC;
LMB_Data_Addr_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_28 : OUT STD_LOGIC;
LMB_Ready_28 : IN STD_LOGIC;
LMB_Byte_Enable_28 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_28 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_28 : OUT STD_LOGIC;
LMB_Write_Strobe_28 : OUT STD_LOGIC;
LMB_CE_28 : IN STD_LOGIC;
LMB_UE_28 : IN STD_LOGIC;
LMB_Wait_28 : IN STD_LOGIC;
LMB_Data_Addr_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_29 : OUT STD_LOGIC;
LMB_Ready_29 : IN STD_LOGIC;
LMB_Byte_Enable_29 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_29 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_29 : OUT STD_LOGIC;
LMB_Write_Strobe_29 : OUT STD_LOGIC;
LMB_CE_29 : IN STD_LOGIC;
LMB_UE_29 : IN STD_LOGIC;
LMB_Wait_29 : IN STD_LOGIC;
LMB_Data_Addr_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_30 : OUT STD_LOGIC;
LMB_Ready_30 : IN STD_LOGIC;
LMB_Byte_Enable_30 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_30 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_30 : OUT STD_LOGIC;
LMB_Write_Strobe_30 : OUT STD_LOGIC;
LMB_CE_30 : IN STD_LOGIC;
LMB_UE_30 : IN STD_LOGIC;
LMB_Wait_30 : IN STD_LOGIC;
LMB_Data_Addr_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_31 : OUT STD_LOGIC;
LMB_Ready_31 : IN STD_LOGIC;
LMB_Byte_Enable_31 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_31 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_31 : OUT STD_LOGIC;
LMB_Write_Strobe_31 : OUT STD_LOGIC;
LMB_CE_31 : IN STD_LOGIC;
LMB_UE_31 : IN STD_LOGIC;
LMB_Wait_31 : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TID : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
TRACE_CLK_OUT : OUT STD_LOGIC;
TRACE_CLK : IN STD_LOGIC;
TRACE_CTL : OUT STD_LOGIC;
TRACE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Trig_In_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_0 : OUT STD_LOGIC;
Dbg_TrData_0 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_0 : OUT STD_LOGIC;
Dbg_TrValid_0 : IN STD_LOGIC;
Dbg_Disable_0 : OUT STD_LOGIC;
Dbg_AWADDR_0 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_0 : OUT STD_LOGIC;
Dbg_AWREADY_0 : IN STD_LOGIC;
Dbg_WDATA_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_0 : OUT STD_LOGIC;
Dbg_WREADY_0 : IN STD_LOGIC;
Dbg_BRESP_0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_0 : IN STD_LOGIC;
Dbg_BREADY_0 : OUT STD_LOGIC;
Dbg_ARADDR_0 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_0 : OUT STD_LOGIC;
Dbg_ARREADY_0 : IN STD_LOGIC;
Dbg_RDATA_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_0 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_0 : IN STD_LOGIC;
Dbg_RREADY_0 : OUT STD_LOGIC;
Dbg_Clk_1 : OUT STD_LOGIC;
Dbg_TDI_1 : OUT STD_LOGIC;
Dbg_TDO_1 : IN STD_LOGIC;
Dbg_Reg_En_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_1 : OUT STD_LOGIC;
Dbg_Shift_1 : OUT STD_LOGIC;
Dbg_Update_1 : OUT STD_LOGIC;
Dbg_Rst_1 : OUT STD_LOGIC;
Dbg_Trig_In_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_1 : OUT STD_LOGIC;
Dbg_TrData_1 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_1 : OUT STD_LOGIC;
Dbg_TrValid_1 : IN STD_LOGIC;
Dbg_Disable_1 : OUT STD_LOGIC;
Dbg_AWADDR_1 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_1 : OUT STD_LOGIC;
Dbg_AWREADY_1 : IN STD_LOGIC;
Dbg_WDATA_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_1 : OUT STD_LOGIC;
Dbg_WREADY_1 : IN STD_LOGIC;
Dbg_BRESP_1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_1 : IN STD_LOGIC;
Dbg_BREADY_1 : OUT STD_LOGIC;
Dbg_ARADDR_1 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_1 : OUT STD_LOGIC;
Dbg_ARREADY_1 : IN STD_LOGIC;
Dbg_RDATA_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_1 : IN STD_LOGIC;
Dbg_RREADY_1 : OUT STD_LOGIC;
Dbg_Clk_2 : OUT STD_LOGIC;
Dbg_TDI_2 : OUT STD_LOGIC;
Dbg_TDO_2 : IN STD_LOGIC;
Dbg_Reg_En_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_2 : OUT STD_LOGIC;
Dbg_Shift_2 : OUT STD_LOGIC;
Dbg_Update_2 : OUT STD_LOGIC;
Dbg_Rst_2 : OUT STD_LOGIC;
Dbg_Trig_In_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_2 : OUT STD_LOGIC;
Dbg_TrData_2 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_2 : OUT STD_LOGIC;
Dbg_TrValid_2 : IN STD_LOGIC;
Dbg_Disable_2 : OUT STD_LOGIC;
Dbg_AWADDR_2 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_2 : OUT STD_LOGIC;
Dbg_AWREADY_2 : IN STD_LOGIC;
Dbg_WDATA_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_2 : OUT STD_LOGIC;
Dbg_WREADY_2 : IN STD_LOGIC;
Dbg_BRESP_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_2 : IN STD_LOGIC;
Dbg_BREADY_2 : OUT STD_LOGIC;
Dbg_ARADDR_2 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_2 : OUT STD_LOGIC;
Dbg_ARREADY_2 : IN STD_LOGIC;
Dbg_RDATA_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_2 : IN STD_LOGIC;
Dbg_RREADY_2 : OUT STD_LOGIC;
Dbg_Clk_3 : OUT STD_LOGIC;
Dbg_TDI_3 : OUT STD_LOGIC;
Dbg_TDO_3 : IN STD_LOGIC;
Dbg_Reg_En_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_3 : OUT STD_LOGIC;
Dbg_Shift_3 : OUT STD_LOGIC;
Dbg_Update_3 : OUT STD_LOGIC;
Dbg_Rst_3 : OUT STD_LOGIC;
Dbg_Trig_In_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_3 : OUT STD_LOGIC;
Dbg_TrData_3 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_3 : OUT STD_LOGIC;
Dbg_TrValid_3 : IN STD_LOGIC;
Dbg_Disable_3 : OUT STD_LOGIC;
Dbg_AWADDR_3 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_3 : OUT STD_LOGIC;
Dbg_AWREADY_3 : IN STD_LOGIC;
Dbg_WDATA_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_3 : OUT STD_LOGIC;
Dbg_WREADY_3 : IN STD_LOGIC;
Dbg_BRESP_3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_3 : IN STD_LOGIC;
Dbg_BREADY_3 : OUT STD_LOGIC;
Dbg_ARADDR_3 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_3 : OUT STD_LOGIC;
Dbg_ARREADY_3 : IN STD_LOGIC;
Dbg_RDATA_3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_3 : IN STD_LOGIC;
Dbg_RREADY_3 : OUT STD_LOGIC;
Dbg_Clk_4 : OUT STD_LOGIC;
Dbg_TDI_4 : OUT STD_LOGIC;
Dbg_TDO_4 : IN STD_LOGIC;
Dbg_Reg_En_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_4 : OUT STD_LOGIC;
Dbg_Shift_4 : OUT STD_LOGIC;
Dbg_Update_4 : OUT STD_LOGIC;
Dbg_Rst_4 : OUT STD_LOGIC;
Dbg_Trig_In_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_4 : OUT STD_LOGIC;
Dbg_TrData_4 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_4 : OUT STD_LOGIC;
Dbg_TrValid_4 : IN STD_LOGIC;
Dbg_Disable_4 : OUT STD_LOGIC;
Dbg_AWADDR_4 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_4 : OUT STD_LOGIC;
Dbg_AWREADY_4 : IN STD_LOGIC;
Dbg_WDATA_4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_4 : OUT STD_LOGIC;
Dbg_WREADY_4 : IN STD_LOGIC;
Dbg_BRESP_4 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_4 : IN STD_LOGIC;
Dbg_BREADY_4 : OUT STD_LOGIC;
Dbg_ARADDR_4 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_4 : OUT STD_LOGIC;
Dbg_ARREADY_4 : IN STD_LOGIC;
Dbg_RDATA_4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_4 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_4 : IN STD_LOGIC;
Dbg_RREADY_4 : OUT STD_LOGIC;
Dbg_Clk_5 : OUT STD_LOGIC;
Dbg_TDI_5 : OUT STD_LOGIC;
Dbg_TDO_5 : IN STD_LOGIC;
Dbg_Reg_En_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_5 : OUT STD_LOGIC;
Dbg_Shift_5 : OUT STD_LOGIC;
Dbg_Update_5 : OUT STD_LOGIC;
Dbg_Rst_5 : OUT STD_LOGIC;
Dbg_Trig_In_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_5 : OUT STD_LOGIC;
Dbg_TrData_5 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_5 : OUT STD_LOGIC;
Dbg_TrValid_5 : IN STD_LOGIC;
Dbg_Disable_5 : OUT STD_LOGIC;
Dbg_AWADDR_5 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_5 : OUT STD_LOGIC;
Dbg_AWREADY_5 : IN STD_LOGIC;
Dbg_WDATA_5 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_5 : OUT STD_LOGIC;
Dbg_WREADY_5 : IN STD_LOGIC;
Dbg_BRESP_5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_5 : IN STD_LOGIC;
Dbg_BREADY_5 : OUT STD_LOGIC;
Dbg_ARADDR_5 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_5 : OUT STD_LOGIC;
Dbg_ARREADY_5 : IN STD_LOGIC;
Dbg_RDATA_5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_5 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_5 : IN STD_LOGIC;
Dbg_RREADY_5 : OUT STD_LOGIC;
Dbg_Clk_6 : OUT STD_LOGIC;
Dbg_TDI_6 : OUT STD_LOGIC;
Dbg_TDO_6 : IN STD_LOGIC;
Dbg_Reg_En_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_6 : OUT STD_LOGIC;
Dbg_Shift_6 : OUT STD_LOGIC;
Dbg_Update_6 : OUT STD_LOGIC;
Dbg_Rst_6 : OUT STD_LOGIC;
Dbg_Trig_In_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_6 : OUT STD_LOGIC;
Dbg_TrData_6 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_6 : OUT STD_LOGIC;
Dbg_TrValid_6 : IN STD_LOGIC;
Dbg_Disable_6 : OUT STD_LOGIC;
Dbg_AWADDR_6 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_6 : OUT STD_LOGIC;
Dbg_AWREADY_6 : IN STD_LOGIC;
Dbg_WDATA_6 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_6 : OUT STD_LOGIC;
Dbg_WREADY_6 : IN STD_LOGIC;
Dbg_BRESP_6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_6 : IN STD_LOGIC;
Dbg_BREADY_6 : OUT STD_LOGIC;
Dbg_ARADDR_6 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_6 : OUT STD_LOGIC;
Dbg_ARREADY_6 : IN STD_LOGIC;
Dbg_RDATA_6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_6 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_6 : IN STD_LOGIC;
Dbg_RREADY_6 : OUT STD_LOGIC;
Dbg_Clk_7 : OUT STD_LOGIC;
Dbg_TDI_7 : OUT STD_LOGIC;
Dbg_TDO_7 : IN STD_LOGIC;
Dbg_Reg_En_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_7 : OUT STD_LOGIC;
Dbg_Shift_7 : OUT STD_LOGIC;
Dbg_Update_7 : OUT STD_LOGIC;
Dbg_Rst_7 : OUT STD_LOGIC;
Dbg_Trig_In_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_7 : OUT STD_LOGIC;
Dbg_TrData_7 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_7 : OUT STD_LOGIC;
Dbg_TrValid_7 : IN STD_LOGIC;
Dbg_Disable_7 : OUT STD_LOGIC;
Dbg_AWADDR_7 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_7 : OUT STD_LOGIC;
Dbg_AWREADY_7 : IN STD_LOGIC;
Dbg_WDATA_7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_7 : OUT STD_LOGIC;
Dbg_WREADY_7 : IN STD_LOGIC;
Dbg_BRESP_7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_7 : IN STD_LOGIC;
Dbg_BREADY_7 : OUT STD_LOGIC;
Dbg_ARADDR_7 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_7 : OUT STD_LOGIC;
Dbg_ARREADY_7 : IN STD_LOGIC;
Dbg_RDATA_7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_7 : IN STD_LOGIC;
Dbg_RREADY_7 : OUT STD_LOGIC;
Dbg_Clk_8 : OUT STD_LOGIC;
Dbg_TDI_8 : OUT STD_LOGIC;
Dbg_TDO_8 : IN STD_LOGIC;
Dbg_Reg_En_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_8 : OUT STD_LOGIC;
Dbg_Shift_8 : OUT STD_LOGIC;
Dbg_Update_8 : OUT STD_LOGIC;
Dbg_Rst_8 : OUT STD_LOGIC;
Dbg_Trig_In_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_8 : OUT STD_LOGIC;
Dbg_TrData_8 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_8 : OUT STD_LOGIC;
Dbg_TrValid_8 : IN STD_LOGIC;
Dbg_Disable_8 : OUT STD_LOGIC;
Dbg_AWADDR_8 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_8 : OUT STD_LOGIC;
Dbg_AWREADY_8 : IN STD_LOGIC;
Dbg_WDATA_8 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_8 : OUT STD_LOGIC;
Dbg_WREADY_8 : IN STD_LOGIC;
Dbg_BRESP_8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_8 : IN STD_LOGIC;
Dbg_BREADY_8 : OUT STD_LOGIC;
Dbg_ARADDR_8 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_8 : OUT STD_LOGIC;
Dbg_ARREADY_8 : IN STD_LOGIC;
Dbg_RDATA_8 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_8 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_8 : IN STD_LOGIC;
Dbg_RREADY_8 : OUT STD_LOGIC;
Dbg_Clk_9 : OUT STD_LOGIC;
Dbg_TDI_9 : OUT STD_LOGIC;
Dbg_TDO_9 : IN STD_LOGIC;
Dbg_Reg_En_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_9 : OUT STD_LOGIC;
Dbg_Shift_9 : OUT STD_LOGIC;
Dbg_Update_9 : OUT STD_LOGIC;
Dbg_Rst_9 : OUT STD_LOGIC;
Dbg_Trig_In_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_9 : OUT STD_LOGIC;
Dbg_TrData_9 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_9 : OUT STD_LOGIC;
Dbg_TrValid_9 : IN STD_LOGIC;
Dbg_Disable_9 : OUT STD_LOGIC;
Dbg_AWADDR_9 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_9 : OUT STD_LOGIC;
Dbg_AWREADY_9 : IN STD_LOGIC;
Dbg_WDATA_9 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_9 : OUT STD_LOGIC;
Dbg_WREADY_9 : IN STD_LOGIC;
Dbg_BRESP_9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_9 : IN STD_LOGIC;
Dbg_BREADY_9 : OUT STD_LOGIC;
Dbg_ARADDR_9 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_9 : OUT STD_LOGIC;
Dbg_ARREADY_9 : IN STD_LOGIC;
Dbg_RDATA_9 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_9 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_9 : IN STD_LOGIC;
Dbg_RREADY_9 : OUT STD_LOGIC;
Dbg_Clk_10 : OUT STD_LOGIC;
Dbg_TDI_10 : OUT STD_LOGIC;
Dbg_TDO_10 : IN STD_LOGIC;
Dbg_Reg_En_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_10 : OUT STD_LOGIC;
Dbg_Shift_10 : OUT STD_LOGIC;
Dbg_Update_10 : OUT STD_LOGIC;
Dbg_Rst_10 : OUT STD_LOGIC;
Dbg_Trig_In_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_10 : OUT STD_LOGIC;
Dbg_TrData_10 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_10 : OUT STD_LOGIC;
Dbg_TrValid_10 : IN STD_LOGIC;
Dbg_Disable_10 : OUT STD_LOGIC;
Dbg_AWADDR_10 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_10 : OUT STD_LOGIC;
Dbg_AWREADY_10 : IN STD_LOGIC;
Dbg_WDATA_10 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_10 : OUT STD_LOGIC;
Dbg_WREADY_10 : IN STD_LOGIC;
Dbg_BRESP_10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_10 : IN STD_LOGIC;
Dbg_BREADY_10 : OUT STD_LOGIC;
Dbg_ARADDR_10 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_10 : OUT STD_LOGIC;
Dbg_ARREADY_10 : IN STD_LOGIC;
Dbg_RDATA_10 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_10 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_10 : IN STD_LOGIC;
Dbg_RREADY_10 : OUT STD_LOGIC;
Dbg_Clk_11 : OUT STD_LOGIC;
Dbg_TDI_11 : OUT STD_LOGIC;
Dbg_TDO_11 : IN STD_LOGIC;
Dbg_Reg_En_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_11 : OUT STD_LOGIC;
Dbg_Shift_11 : OUT STD_LOGIC;
Dbg_Update_11 : OUT STD_LOGIC;
Dbg_Rst_11 : OUT STD_LOGIC;
Dbg_Trig_In_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_11 : OUT STD_LOGIC;
Dbg_TrData_11 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_11 : OUT STD_LOGIC;
Dbg_TrValid_11 : IN STD_LOGIC;
Dbg_Disable_11 : OUT STD_LOGIC;
Dbg_AWADDR_11 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_11 : OUT STD_LOGIC;
Dbg_AWREADY_11 : IN STD_LOGIC;
Dbg_WDATA_11 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_11 : OUT STD_LOGIC;
Dbg_WREADY_11 : IN STD_LOGIC;
Dbg_BRESP_11 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_11 : IN STD_LOGIC;
Dbg_BREADY_11 : OUT STD_LOGIC;
Dbg_ARADDR_11 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_11 : OUT STD_LOGIC;
Dbg_ARREADY_11 : IN STD_LOGIC;
Dbg_RDATA_11 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_11 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_11 : IN STD_LOGIC;
Dbg_RREADY_11 : OUT STD_LOGIC;
Dbg_Clk_12 : OUT STD_LOGIC;
Dbg_TDI_12 : OUT STD_LOGIC;
Dbg_TDO_12 : IN STD_LOGIC;
Dbg_Reg_En_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_12 : OUT STD_LOGIC;
Dbg_Shift_12 : OUT STD_LOGIC;
Dbg_Update_12 : OUT STD_LOGIC;
Dbg_Rst_12 : OUT STD_LOGIC;
Dbg_Trig_In_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_12 : OUT STD_LOGIC;
Dbg_TrData_12 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_12 : OUT STD_LOGIC;
Dbg_TrValid_12 : IN STD_LOGIC;
Dbg_Disable_12 : OUT STD_LOGIC;
Dbg_AWADDR_12 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_12 : OUT STD_LOGIC;
Dbg_AWREADY_12 : IN STD_LOGIC;
Dbg_WDATA_12 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_12 : OUT STD_LOGIC;
Dbg_WREADY_12 : IN STD_LOGIC;
Dbg_BRESP_12 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_12 : IN STD_LOGIC;
Dbg_BREADY_12 : OUT STD_LOGIC;
Dbg_ARADDR_12 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_12 : OUT STD_LOGIC;
Dbg_ARREADY_12 : IN STD_LOGIC;
Dbg_RDATA_12 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_12 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_12 : IN STD_LOGIC;
Dbg_RREADY_12 : OUT STD_LOGIC;
Dbg_Clk_13 : OUT STD_LOGIC;
Dbg_TDI_13 : OUT STD_LOGIC;
Dbg_TDO_13 : IN STD_LOGIC;
Dbg_Reg_En_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_13 : OUT STD_LOGIC;
Dbg_Shift_13 : OUT STD_LOGIC;
Dbg_Update_13 : OUT STD_LOGIC;
Dbg_Rst_13 : OUT STD_LOGIC;
Dbg_Trig_In_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_13 : OUT STD_LOGIC;
Dbg_TrData_13 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_13 : OUT STD_LOGIC;
Dbg_TrValid_13 : IN STD_LOGIC;
Dbg_Disable_13 : OUT STD_LOGIC;
Dbg_AWADDR_13 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_13 : OUT STD_LOGIC;
Dbg_AWREADY_13 : IN STD_LOGIC;
Dbg_WDATA_13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_13 : OUT STD_LOGIC;
Dbg_WREADY_13 : IN STD_LOGIC;
Dbg_BRESP_13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_13 : IN STD_LOGIC;
Dbg_BREADY_13 : OUT STD_LOGIC;
Dbg_ARADDR_13 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_13 : OUT STD_LOGIC;
Dbg_ARREADY_13 : IN STD_LOGIC;
Dbg_RDATA_13 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_13 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_13 : IN STD_LOGIC;
Dbg_RREADY_13 : OUT STD_LOGIC;
Dbg_Clk_14 : OUT STD_LOGIC;
Dbg_TDI_14 : OUT STD_LOGIC;
Dbg_TDO_14 : IN STD_LOGIC;
Dbg_Reg_En_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_14 : OUT STD_LOGIC;
Dbg_Shift_14 : OUT STD_LOGIC;
Dbg_Update_14 : OUT STD_LOGIC;
Dbg_Rst_14 : OUT STD_LOGIC;
Dbg_Trig_In_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_14 : OUT STD_LOGIC;
Dbg_TrData_14 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_14 : OUT STD_LOGIC;
Dbg_TrValid_14 : IN STD_LOGIC;
Dbg_Disable_14 : OUT STD_LOGIC;
Dbg_AWADDR_14 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_14 : OUT STD_LOGIC;
Dbg_AWREADY_14 : IN STD_LOGIC;
Dbg_WDATA_14 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_14 : OUT STD_LOGIC;
Dbg_WREADY_14 : IN STD_LOGIC;
Dbg_BRESP_14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_14 : IN STD_LOGIC;
Dbg_BREADY_14 : OUT STD_LOGIC;
Dbg_ARADDR_14 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_14 : OUT STD_LOGIC;
Dbg_ARREADY_14 : IN STD_LOGIC;
Dbg_RDATA_14 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_14 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_14 : IN STD_LOGIC;
Dbg_RREADY_14 : OUT STD_LOGIC;
Dbg_Clk_15 : OUT STD_LOGIC;
Dbg_TDI_15 : OUT STD_LOGIC;
Dbg_TDO_15 : IN STD_LOGIC;
Dbg_Reg_En_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_15 : OUT STD_LOGIC;
Dbg_Shift_15 : OUT STD_LOGIC;
Dbg_Update_15 : OUT STD_LOGIC;
Dbg_Rst_15 : OUT STD_LOGIC;
Dbg_Trig_In_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_15 : OUT STD_LOGIC;
Dbg_TrData_15 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_15 : OUT STD_LOGIC;
Dbg_TrValid_15 : IN STD_LOGIC;
Dbg_Disable_15 : OUT STD_LOGIC;
Dbg_AWADDR_15 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_15 : OUT STD_LOGIC;
Dbg_AWREADY_15 : IN STD_LOGIC;
Dbg_WDATA_15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_15 : OUT STD_LOGIC;
Dbg_WREADY_15 : IN STD_LOGIC;
Dbg_BRESP_15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_15 : IN STD_LOGIC;
Dbg_BREADY_15 : OUT STD_LOGIC;
Dbg_ARADDR_15 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_15 : OUT STD_LOGIC;
Dbg_ARREADY_15 : IN STD_LOGIC;
Dbg_RDATA_15 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_15 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_15 : IN STD_LOGIC;
Dbg_RREADY_15 : OUT STD_LOGIC;
Dbg_Clk_16 : OUT STD_LOGIC;
Dbg_TDI_16 : OUT STD_LOGIC;
Dbg_TDO_16 : IN STD_LOGIC;
Dbg_Reg_En_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_16 : OUT STD_LOGIC;
Dbg_Shift_16 : OUT STD_LOGIC;
Dbg_Update_16 : OUT STD_LOGIC;
Dbg_Rst_16 : OUT STD_LOGIC;
Dbg_Trig_In_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_16 : OUT STD_LOGIC;
Dbg_TrData_16 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_16 : OUT STD_LOGIC;
Dbg_TrValid_16 : IN STD_LOGIC;
Dbg_Disable_16 : OUT STD_LOGIC;
Dbg_AWADDR_16 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_16 : OUT STD_LOGIC;
Dbg_AWREADY_16 : IN STD_LOGIC;
Dbg_WDATA_16 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_16 : OUT STD_LOGIC;
Dbg_WREADY_16 : IN STD_LOGIC;
Dbg_BRESP_16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_16 : IN STD_LOGIC;
Dbg_BREADY_16 : OUT STD_LOGIC;
Dbg_ARADDR_16 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_16 : OUT STD_LOGIC;
Dbg_ARREADY_16 : IN STD_LOGIC;
Dbg_RDATA_16 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_16 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_16 : IN STD_LOGIC;
Dbg_RREADY_16 : OUT STD_LOGIC;
Dbg_Clk_17 : OUT STD_LOGIC;
Dbg_TDI_17 : OUT STD_LOGIC;
Dbg_TDO_17 : IN STD_LOGIC;
Dbg_Reg_En_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_17 : OUT STD_LOGIC;
Dbg_Shift_17 : OUT STD_LOGIC;
Dbg_Update_17 : OUT STD_LOGIC;
Dbg_Rst_17 : OUT STD_LOGIC;
Dbg_Trig_In_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_17 : OUT STD_LOGIC;
Dbg_TrData_17 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_17 : OUT STD_LOGIC;
Dbg_TrValid_17 : IN STD_LOGIC;
Dbg_Disable_17 : OUT STD_LOGIC;
Dbg_AWADDR_17 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_17 : OUT STD_LOGIC;
Dbg_AWREADY_17 : IN STD_LOGIC;
Dbg_WDATA_17 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_17 : OUT STD_LOGIC;
Dbg_WREADY_17 : IN STD_LOGIC;
Dbg_BRESP_17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_17 : IN STD_LOGIC;
Dbg_BREADY_17 : OUT STD_LOGIC;
Dbg_ARADDR_17 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_17 : OUT STD_LOGIC;
Dbg_ARREADY_17 : IN STD_LOGIC;
Dbg_RDATA_17 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_17 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_17 : IN STD_LOGIC;
Dbg_RREADY_17 : OUT STD_LOGIC;
Dbg_Clk_18 : OUT STD_LOGIC;
Dbg_TDI_18 : OUT STD_LOGIC;
Dbg_TDO_18 : IN STD_LOGIC;
Dbg_Reg_En_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_18 : OUT STD_LOGIC;
Dbg_Shift_18 : OUT STD_LOGIC;
Dbg_Update_18 : OUT STD_LOGIC;
Dbg_Rst_18 : OUT STD_LOGIC;
Dbg_Trig_In_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_18 : OUT STD_LOGIC;
Dbg_TrData_18 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_18 : OUT STD_LOGIC;
Dbg_TrValid_18 : IN STD_LOGIC;
Dbg_Disable_18 : OUT STD_LOGIC;
Dbg_AWADDR_18 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_18 : OUT STD_LOGIC;
Dbg_AWREADY_18 : IN STD_LOGIC;
Dbg_WDATA_18 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_18 : OUT STD_LOGIC;
Dbg_WREADY_18 : IN STD_LOGIC;
Dbg_BRESP_18 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_18 : IN STD_LOGIC;
Dbg_BREADY_18 : OUT STD_LOGIC;
Dbg_ARADDR_18 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_18 : OUT STD_LOGIC;
Dbg_ARREADY_18 : IN STD_LOGIC;
Dbg_RDATA_18 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_18 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_18 : IN STD_LOGIC;
Dbg_RREADY_18 : OUT STD_LOGIC;
Dbg_Clk_19 : OUT STD_LOGIC;
Dbg_TDI_19 : OUT STD_LOGIC;
Dbg_TDO_19 : IN STD_LOGIC;
Dbg_Reg_En_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_19 : OUT STD_LOGIC;
Dbg_Shift_19 : OUT STD_LOGIC;
Dbg_Update_19 : OUT STD_LOGIC;
Dbg_Rst_19 : OUT STD_LOGIC;
Dbg_Trig_In_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_19 : OUT STD_LOGIC;
Dbg_TrData_19 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_19 : OUT STD_LOGIC;
Dbg_TrValid_19 : IN STD_LOGIC;
Dbg_Disable_19 : OUT STD_LOGIC;
Dbg_AWADDR_19 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_19 : OUT STD_LOGIC;
Dbg_AWREADY_19 : IN STD_LOGIC;
Dbg_WDATA_19 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_19 : OUT STD_LOGIC;
Dbg_WREADY_19 : IN STD_LOGIC;
Dbg_BRESP_19 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_19 : IN STD_LOGIC;
Dbg_BREADY_19 : OUT STD_LOGIC;
Dbg_ARADDR_19 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_19 : OUT STD_LOGIC;
Dbg_ARREADY_19 : IN STD_LOGIC;
Dbg_RDATA_19 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_19 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_19 : IN STD_LOGIC;
Dbg_RREADY_19 : OUT STD_LOGIC;
Dbg_Clk_20 : OUT STD_LOGIC;
Dbg_TDI_20 : OUT STD_LOGIC;
Dbg_TDO_20 : IN STD_LOGIC;
Dbg_Reg_En_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_20 : OUT STD_LOGIC;
Dbg_Shift_20 : OUT STD_LOGIC;
Dbg_Update_20 : OUT STD_LOGIC;
Dbg_Rst_20 : OUT STD_LOGIC;
Dbg_Trig_In_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_20 : OUT STD_LOGIC;
Dbg_TrData_20 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_20 : OUT STD_LOGIC;
Dbg_TrValid_20 : IN STD_LOGIC;
Dbg_Disable_20 : OUT STD_LOGIC;
Dbg_AWADDR_20 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_20 : OUT STD_LOGIC;
Dbg_AWREADY_20 : IN STD_LOGIC;
Dbg_WDATA_20 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_20 : OUT STD_LOGIC;
Dbg_WREADY_20 : IN STD_LOGIC;
Dbg_BRESP_20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_20 : IN STD_LOGIC;
Dbg_BREADY_20 : OUT STD_LOGIC;
Dbg_ARADDR_20 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_20 : OUT STD_LOGIC;
Dbg_ARREADY_20 : IN STD_LOGIC;
Dbg_RDATA_20 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_20 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_20 : IN STD_LOGIC;
Dbg_RREADY_20 : OUT STD_LOGIC;
Dbg_Clk_21 : OUT STD_LOGIC;
Dbg_TDI_21 : OUT STD_LOGIC;
Dbg_TDO_21 : IN STD_LOGIC;
Dbg_Reg_En_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_21 : OUT STD_LOGIC;
Dbg_Shift_21 : OUT STD_LOGIC;
Dbg_Update_21 : OUT STD_LOGIC;
Dbg_Rst_21 : OUT STD_LOGIC;
Dbg_Trig_In_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_21 : OUT STD_LOGIC;
Dbg_TrData_21 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_21 : OUT STD_LOGIC;
Dbg_TrValid_21 : IN STD_LOGIC;
Dbg_Disable_21 : OUT STD_LOGIC;
Dbg_AWADDR_21 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_21 : OUT STD_LOGIC;
Dbg_AWREADY_21 : IN STD_LOGIC;
Dbg_WDATA_21 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_21 : OUT STD_LOGIC;
Dbg_WREADY_21 : IN STD_LOGIC;
Dbg_BRESP_21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_21 : IN STD_LOGIC;
Dbg_BREADY_21 : OUT STD_LOGIC;
Dbg_ARADDR_21 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_21 : OUT STD_LOGIC;
Dbg_ARREADY_21 : IN STD_LOGIC;
Dbg_RDATA_21 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_21 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_21 : IN STD_LOGIC;
Dbg_RREADY_21 : OUT STD_LOGIC;
Dbg_Clk_22 : OUT STD_LOGIC;
Dbg_TDI_22 : OUT STD_LOGIC;
Dbg_TDO_22 : IN STD_LOGIC;
Dbg_Reg_En_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_22 : OUT STD_LOGIC;
Dbg_Shift_22 : OUT STD_LOGIC;
Dbg_Update_22 : OUT STD_LOGIC;
Dbg_Rst_22 : OUT STD_LOGIC;
Dbg_Trig_In_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_22 : OUT STD_LOGIC;
Dbg_TrData_22 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_22 : OUT STD_LOGIC;
Dbg_TrValid_22 : IN STD_LOGIC;
Dbg_Disable_22 : OUT STD_LOGIC;
Dbg_AWADDR_22 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_22 : OUT STD_LOGIC;
Dbg_AWREADY_22 : IN STD_LOGIC;
Dbg_WDATA_22 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_22 : OUT STD_LOGIC;
Dbg_WREADY_22 : IN STD_LOGIC;
Dbg_BRESP_22 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_22 : IN STD_LOGIC;
Dbg_BREADY_22 : OUT STD_LOGIC;
Dbg_ARADDR_22 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_22 : OUT STD_LOGIC;
Dbg_ARREADY_22 : IN STD_LOGIC;
Dbg_RDATA_22 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_22 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_22 : IN STD_LOGIC;
Dbg_RREADY_22 : OUT STD_LOGIC;
Dbg_Clk_23 : OUT STD_LOGIC;
Dbg_TDI_23 : OUT STD_LOGIC;
Dbg_TDO_23 : IN STD_LOGIC;
Dbg_Reg_En_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_23 : OUT STD_LOGIC;
Dbg_Shift_23 : OUT STD_LOGIC;
Dbg_Update_23 : OUT STD_LOGIC;
Dbg_Rst_23 : OUT STD_LOGIC;
Dbg_Trig_In_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_23 : OUT STD_LOGIC;
Dbg_TrData_23 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_23 : OUT STD_LOGIC;
Dbg_TrValid_23 : IN STD_LOGIC;
Dbg_Disable_23 : OUT STD_LOGIC;
Dbg_AWADDR_23 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_23 : OUT STD_LOGIC;
Dbg_AWREADY_23 : IN STD_LOGIC;
Dbg_WDATA_23 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_23 : OUT STD_LOGIC;
Dbg_WREADY_23 : IN STD_LOGIC;
Dbg_BRESP_23 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_23 : IN STD_LOGIC;
Dbg_BREADY_23 : OUT STD_LOGIC;
Dbg_ARADDR_23 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_23 : OUT STD_LOGIC;
Dbg_ARREADY_23 : IN STD_LOGIC;
Dbg_RDATA_23 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_23 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_23 : IN STD_LOGIC;
Dbg_RREADY_23 : OUT STD_LOGIC;
Dbg_Clk_24 : OUT STD_LOGIC;
Dbg_TDI_24 : OUT STD_LOGIC;
Dbg_TDO_24 : IN STD_LOGIC;
Dbg_Reg_En_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_24 : OUT STD_LOGIC;
Dbg_Shift_24 : OUT STD_LOGIC;
Dbg_Update_24 : OUT STD_LOGIC;
Dbg_Rst_24 : OUT STD_LOGIC;
Dbg_Trig_In_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_24 : OUT STD_LOGIC;
Dbg_TrData_24 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_24 : OUT STD_LOGIC;
Dbg_TrValid_24 : IN STD_LOGIC;
Dbg_Disable_24 : OUT STD_LOGIC;
Dbg_AWADDR_24 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_24 : OUT STD_LOGIC;
Dbg_AWREADY_24 : IN STD_LOGIC;
Dbg_WDATA_24 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_24 : OUT STD_LOGIC;
Dbg_WREADY_24 : IN STD_LOGIC;
Dbg_BRESP_24 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_24 : IN STD_LOGIC;
Dbg_BREADY_24 : OUT STD_LOGIC;
Dbg_ARADDR_24 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_24 : OUT STD_LOGIC;
Dbg_ARREADY_24 : IN STD_LOGIC;
Dbg_RDATA_24 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_24 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_24 : IN STD_LOGIC;
Dbg_RREADY_24 : OUT STD_LOGIC;
Dbg_Clk_25 : OUT STD_LOGIC;
Dbg_TDI_25 : OUT STD_LOGIC;
Dbg_TDO_25 : IN STD_LOGIC;
Dbg_Reg_En_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_25 : OUT STD_LOGIC;
Dbg_Shift_25 : OUT STD_LOGIC;
Dbg_Update_25 : OUT STD_LOGIC;
Dbg_Rst_25 : OUT STD_LOGIC;
Dbg_Trig_In_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_25 : OUT STD_LOGIC;
Dbg_TrData_25 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_25 : OUT STD_LOGIC;
Dbg_TrValid_25 : IN STD_LOGIC;
Dbg_Disable_25 : OUT STD_LOGIC;
Dbg_AWADDR_25 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_25 : OUT STD_LOGIC;
Dbg_AWREADY_25 : IN STD_LOGIC;
Dbg_WDATA_25 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_25 : OUT STD_LOGIC;
Dbg_WREADY_25 : IN STD_LOGIC;
Dbg_BRESP_25 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_25 : IN STD_LOGIC;
Dbg_BREADY_25 : OUT STD_LOGIC;
Dbg_ARADDR_25 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_25 : OUT STD_LOGIC;
Dbg_ARREADY_25 : IN STD_LOGIC;
Dbg_RDATA_25 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_25 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_25 : IN STD_LOGIC;
Dbg_RREADY_25 : OUT STD_LOGIC;
Dbg_Clk_26 : OUT STD_LOGIC;
Dbg_TDI_26 : OUT STD_LOGIC;
Dbg_TDO_26 : IN STD_LOGIC;
Dbg_Reg_En_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_26 : OUT STD_LOGIC;
Dbg_Shift_26 : OUT STD_LOGIC;
Dbg_Update_26 : OUT STD_LOGIC;
Dbg_Rst_26 : OUT STD_LOGIC;
Dbg_Trig_In_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_26 : OUT STD_LOGIC;
Dbg_TrData_26 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_26 : OUT STD_LOGIC;
Dbg_TrValid_26 : IN STD_LOGIC;
Dbg_Disable_26 : OUT STD_LOGIC;
Dbg_AWADDR_26 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_26 : OUT STD_LOGIC;
Dbg_AWREADY_26 : IN STD_LOGIC;
Dbg_WDATA_26 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_26 : OUT STD_LOGIC;
Dbg_WREADY_26 : IN STD_LOGIC;
Dbg_BRESP_26 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_26 : IN STD_LOGIC;
Dbg_BREADY_26 : OUT STD_LOGIC;
Dbg_ARADDR_26 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_26 : OUT STD_LOGIC;
Dbg_ARREADY_26 : IN STD_LOGIC;
Dbg_RDATA_26 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_26 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_26 : IN STD_LOGIC;
Dbg_RREADY_26 : OUT STD_LOGIC;
Dbg_Clk_27 : OUT STD_LOGIC;
Dbg_TDI_27 : OUT STD_LOGIC;
Dbg_TDO_27 : IN STD_LOGIC;
Dbg_Reg_En_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_27 : OUT STD_LOGIC;
Dbg_Shift_27 : OUT STD_LOGIC;
Dbg_Update_27 : OUT STD_LOGIC;
Dbg_Rst_27 : OUT STD_LOGIC;
Dbg_Trig_In_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_27 : OUT STD_LOGIC;
Dbg_TrData_27 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_27 : OUT STD_LOGIC;
Dbg_TrValid_27 : IN STD_LOGIC;
Dbg_Disable_27 : OUT STD_LOGIC;
Dbg_AWADDR_27 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_27 : OUT STD_LOGIC;
Dbg_AWREADY_27 : IN STD_LOGIC;
Dbg_WDATA_27 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_27 : OUT STD_LOGIC;
Dbg_WREADY_27 : IN STD_LOGIC;
Dbg_BRESP_27 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_27 : IN STD_LOGIC;
Dbg_BREADY_27 : OUT STD_LOGIC;
Dbg_ARADDR_27 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_27 : OUT STD_LOGIC;
Dbg_ARREADY_27 : IN STD_LOGIC;
Dbg_RDATA_27 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_27 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_27 : IN STD_LOGIC;
Dbg_RREADY_27 : OUT STD_LOGIC;
Dbg_Clk_28 : OUT STD_LOGIC;
Dbg_TDI_28 : OUT STD_LOGIC;
Dbg_TDO_28 : IN STD_LOGIC;
Dbg_Reg_En_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_28 : OUT STD_LOGIC;
Dbg_Shift_28 : OUT STD_LOGIC;
Dbg_Update_28 : OUT STD_LOGIC;
Dbg_Rst_28 : OUT STD_LOGIC;
Dbg_Trig_In_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_28 : OUT STD_LOGIC;
Dbg_TrData_28 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_28 : OUT STD_LOGIC;
Dbg_TrValid_28 : IN STD_LOGIC;
Dbg_Disable_28 : OUT STD_LOGIC;
Dbg_AWADDR_28 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_28 : OUT STD_LOGIC;
Dbg_AWREADY_28 : IN STD_LOGIC;
Dbg_WDATA_28 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_28 : OUT STD_LOGIC;
Dbg_WREADY_28 : IN STD_LOGIC;
Dbg_BRESP_28 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_28 : IN STD_LOGIC;
Dbg_BREADY_28 : OUT STD_LOGIC;
Dbg_ARADDR_28 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_28 : OUT STD_LOGIC;
Dbg_ARREADY_28 : IN STD_LOGIC;
Dbg_RDATA_28 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_28 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_28 : IN STD_LOGIC;
Dbg_RREADY_28 : OUT STD_LOGIC;
Dbg_Clk_29 : OUT STD_LOGIC;
Dbg_TDI_29 : OUT STD_LOGIC;
Dbg_TDO_29 : IN STD_LOGIC;
Dbg_Reg_En_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_29 : OUT STD_LOGIC;
Dbg_Shift_29 : OUT STD_LOGIC;
Dbg_Update_29 : OUT STD_LOGIC;
Dbg_Rst_29 : OUT STD_LOGIC;
Dbg_Trig_In_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_29 : OUT STD_LOGIC;
Dbg_TrData_29 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_29 : OUT STD_LOGIC;
Dbg_TrValid_29 : IN STD_LOGIC;
Dbg_Disable_29 : OUT STD_LOGIC;
Dbg_AWADDR_29 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_29 : OUT STD_LOGIC;
Dbg_AWREADY_29 : IN STD_LOGIC;
Dbg_WDATA_29 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_29 : OUT STD_LOGIC;
Dbg_WREADY_29 : IN STD_LOGIC;
Dbg_BRESP_29 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_29 : IN STD_LOGIC;
Dbg_BREADY_29 : OUT STD_LOGIC;
Dbg_ARADDR_29 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_29 : OUT STD_LOGIC;
Dbg_ARREADY_29 : IN STD_LOGIC;
Dbg_RDATA_29 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_29 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_29 : IN STD_LOGIC;
Dbg_RREADY_29 : OUT STD_LOGIC;
Dbg_Clk_30 : OUT STD_LOGIC;
Dbg_TDI_30 : OUT STD_LOGIC;
Dbg_TDO_30 : IN STD_LOGIC;
Dbg_Reg_En_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_30 : OUT STD_LOGIC;
Dbg_Shift_30 : OUT STD_LOGIC;
Dbg_Update_30 : OUT STD_LOGIC;
Dbg_Rst_30 : OUT STD_LOGIC;
Dbg_Trig_In_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_30 : OUT STD_LOGIC;
Dbg_TrData_30 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_30 : OUT STD_LOGIC;
Dbg_TrValid_30 : IN STD_LOGIC;
Dbg_Disable_30 : OUT STD_LOGIC;
Dbg_AWADDR_30 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_30 : OUT STD_LOGIC;
Dbg_AWREADY_30 : IN STD_LOGIC;
Dbg_WDATA_30 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_30 : OUT STD_LOGIC;
Dbg_WREADY_30 : IN STD_LOGIC;
Dbg_BRESP_30 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_30 : IN STD_LOGIC;
Dbg_BREADY_30 : OUT STD_LOGIC;
Dbg_ARADDR_30 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_30 : OUT STD_LOGIC;
Dbg_ARREADY_30 : IN STD_LOGIC;
Dbg_RDATA_30 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_30 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_30 : IN STD_LOGIC;
Dbg_RREADY_30 : OUT STD_LOGIC;
Dbg_Clk_31 : OUT STD_LOGIC;
Dbg_TDI_31 : OUT STD_LOGIC;
Dbg_TDO_31 : IN STD_LOGIC;
Dbg_Reg_En_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_31 : OUT STD_LOGIC;
Dbg_Shift_31 : OUT STD_LOGIC;
Dbg_Update_31 : OUT STD_LOGIC;
Dbg_Rst_31 : OUT STD_LOGIC;
Dbg_Trig_In_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_31 : OUT STD_LOGIC;
Dbg_TrData_31 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_31 : OUT STD_LOGIC;
Dbg_TrValid_31 : IN STD_LOGIC;
Dbg_Disable_31 : OUT STD_LOGIC;
Dbg_AWADDR_31 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID_31 : OUT STD_LOGIC;
Dbg_AWREADY_31 : IN STD_LOGIC;
Dbg_WDATA_31 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID_31 : OUT STD_LOGIC;
Dbg_WREADY_31 : IN STD_LOGIC;
Dbg_BRESP_31 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID_31 : IN STD_LOGIC;
Dbg_BREADY_31 : OUT STD_LOGIC;
Dbg_ARADDR_31 : OUT STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID_31 : OUT STD_LOGIC;
Dbg_ARREADY_31 : IN STD_LOGIC;
Dbg_RDATA_31 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP_31 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID_31 : IN STD_LOGIC;
Dbg_RREADY_31 : OUT STD_LOGIC;
bscan_ext_tdi : IN STD_LOGIC;
bscan_ext_reset : IN STD_LOGIC;
bscan_ext_shift : IN STD_LOGIC;
bscan_ext_update : IN STD_LOGIC;
bscan_ext_capture : IN STD_LOGIC;
bscan_ext_sel : IN STD_LOGIC;
bscan_ext_drck : IN STD_LOGIC;
bscan_ext_tdo : OUT STD_LOGIC;
Ext_JTAG_DRCK : OUT STD_LOGIC;
Ext_JTAG_RESET : OUT STD_LOGIC;
Ext_JTAG_SEL : OUT STD_LOGIC;
Ext_JTAG_CAPTURE : OUT STD_LOGIC;
Ext_JTAG_SHIFT : OUT STD_LOGIC;
Ext_JTAG_UPDATE : OUT STD_LOGIC;
Ext_JTAG_TDI : OUT STD_LOGIC;
Ext_JTAG_TDO : IN STD_LOGIC
);
END COMPONENT MDM;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_mdm_1_0_arch: ARCHITECTURE IS "MDM,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_mdm_1_0_arch : ARCHITECTURE IS "system_mdm_1_0,MDM,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_mdm_1_0_arch: ARCHITECTURE IS "system_mdm_1_0,MDM,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mdm,x_ipVersion=3.2,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_JTAG_CHAIN=2,C_USE_BSCAN=0,C_DEBUG_INTERFACE=0,C_USE_CONFIG_RESET=0,C_INTERCONNECT=2,C_MB_DBG_PORTS=1,C_USE_UART=0,C_DBG_REG_ACCESS=0,C_DBG_MEM_ACCESS=0,C_USE_CROSS_TRIGGER=0,C_TRACE_OUTPUT=0,C_TRACE_DATA_WIDTH=32,C_TRACE_CLK_FREQ_HZ=200000000,C_TRACE_CLK_OUT_PHASE=90,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32" &
",C_S_AXI_ACLK_FREQ_HZ=100000000,C_M_AXI_ADDR_WIDTH=32,C_M_AXI_DATA_WIDTH=32,C_M_AXI_THREAD_ID_WIDTH=1,C_DATA_SIZE=32,C_M_AXIS_DATA_WIDTH=32,C_M_AXIS_ID_WIDTH=7}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Debug_SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Rst_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Disable_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 DISABLE";
BEGIN
U0 : MDM
GENERIC MAP (
C_FAMILY => "artix7",
C_JTAG_CHAIN => 2,
C_USE_BSCAN => 0,
C_DEBUG_INTERFACE => 0,
C_USE_CONFIG_RESET => 0,
C_INTERCONNECT => 2,
C_MB_DBG_PORTS => 1,
C_USE_UART => 0,
C_DBG_REG_ACCESS => 0,
C_DBG_MEM_ACCESS => 0,
C_USE_CROSS_TRIGGER => 0,
C_TRACE_OUTPUT => 0,
C_TRACE_DATA_WIDTH => 32,
C_TRACE_CLK_FREQ_HZ => 200000000,
C_TRACE_CLK_OUT_PHASE => 90,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_THREAD_ID_WIDTH => 1,
C_DATA_SIZE => 32,
C_M_AXIS_DATA_WIDTH => 32,
C_M_AXIS_ID_WIDTH => 7
)
PORT MAP (
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
M_AXI_ACLK => '0',
M_AXI_ARESETN => '0',
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
Debug_SYS_Rst => Debug_SYS_Rst,
Trig_In_0 => '0',
Trig_Ack_Out_0 => '0',
Trig_In_1 => '0',
Trig_Ack_Out_1 => '0',
Trig_In_2 => '0',
Trig_Ack_Out_2 => '0',
Trig_In_3 => '0',
Trig_Ack_Out_3 => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
M_AXI_AWREADY => '0',
M_AXI_WREADY => '0',
M_AXI_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_BVALID => '0',
M_AXI_ARREADY => '0',
M_AXI_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_RLAST => '0',
M_AXI_RVALID => '0',
LMB_Ready_0 => '0',
LMB_Data_Read_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_0 => '0',
LMB_UE_0 => '0',
LMB_Wait_0 => '0',
LMB_Ready_1 => '0',
LMB_Data_Read_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_1 => '0',
LMB_UE_1 => '0',
LMB_Wait_1 => '0',
LMB_Ready_2 => '0',
LMB_Data_Read_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_2 => '0',
LMB_UE_2 => '0',
LMB_Wait_2 => '0',
LMB_Ready_3 => '0',
LMB_Data_Read_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_3 => '0',
LMB_UE_3 => '0',
LMB_Wait_3 => '0',
LMB_Ready_4 => '0',
LMB_Data_Read_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_4 => '0',
LMB_UE_4 => '0',
LMB_Wait_4 => '0',
LMB_Ready_5 => '0',
LMB_Data_Read_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_5 => '0',
LMB_UE_5 => '0',
LMB_Wait_5 => '0',
LMB_Ready_6 => '0',
LMB_Data_Read_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_6 => '0',
LMB_UE_6 => '0',
LMB_Wait_6 => '0',
LMB_Ready_7 => '0',
LMB_Data_Read_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_7 => '0',
LMB_UE_7 => '0',
LMB_Wait_7 => '0',
LMB_Ready_8 => '0',
LMB_Data_Read_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_8 => '0',
LMB_UE_8 => '0',
LMB_Wait_8 => '0',
LMB_Ready_9 => '0',
LMB_Data_Read_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_9 => '0',
LMB_UE_9 => '0',
LMB_Wait_9 => '0',
LMB_Ready_10 => '0',
LMB_Data_Read_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_10 => '0',
LMB_UE_10 => '0',
LMB_Wait_10 => '0',
LMB_Ready_11 => '0',
LMB_Data_Read_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_11 => '0',
LMB_UE_11 => '0',
LMB_Wait_11 => '0',
LMB_Ready_12 => '0',
LMB_Data_Read_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_12 => '0',
LMB_UE_12 => '0',
LMB_Wait_12 => '0',
LMB_Ready_13 => '0',
LMB_Data_Read_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_13 => '0',
LMB_UE_13 => '0',
LMB_Wait_13 => '0',
LMB_Ready_14 => '0',
LMB_Data_Read_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_14 => '0',
LMB_UE_14 => '0',
LMB_Wait_14 => '0',
LMB_Ready_15 => '0',
LMB_Data_Read_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_15 => '0',
LMB_UE_15 => '0',
LMB_Wait_15 => '0',
LMB_Ready_16 => '0',
LMB_Data_Read_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_16 => '0',
LMB_UE_16 => '0',
LMB_Wait_16 => '0',
LMB_Ready_17 => '0',
LMB_Data_Read_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_17 => '0',
LMB_UE_17 => '0',
LMB_Wait_17 => '0',
LMB_Ready_18 => '0',
LMB_Data_Read_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_18 => '0',
LMB_UE_18 => '0',
LMB_Wait_18 => '0',
LMB_Ready_19 => '0',
LMB_Data_Read_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_19 => '0',
LMB_UE_19 => '0',
LMB_Wait_19 => '0',
LMB_Ready_20 => '0',
LMB_Data_Read_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_20 => '0',
LMB_UE_20 => '0',
LMB_Wait_20 => '0',
LMB_Ready_21 => '0',
LMB_Data_Read_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_21 => '0',
LMB_UE_21 => '0',
LMB_Wait_21 => '0',
LMB_Ready_22 => '0',
LMB_Data_Read_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_22 => '0',
LMB_UE_22 => '0',
LMB_Wait_22 => '0',
LMB_Ready_23 => '0',
LMB_Data_Read_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_23 => '0',
LMB_UE_23 => '0',
LMB_Wait_23 => '0',
LMB_Ready_24 => '0',
LMB_Data_Read_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_24 => '0',
LMB_UE_24 => '0',
LMB_Wait_24 => '0',
LMB_Ready_25 => '0',
LMB_Data_Read_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_25 => '0',
LMB_UE_25 => '0',
LMB_Wait_25 => '0',
LMB_Ready_26 => '0',
LMB_Data_Read_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_26 => '0',
LMB_UE_26 => '0',
LMB_Wait_26 => '0',
LMB_Ready_27 => '0',
LMB_Data_Read_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_27 => '0',
LMB_UE_27 => '0',
LMB_Wait_27 => '0',
LMB_Ready_28 => '0',
LMB_Data_Read_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_28 => '0',
LMB_UE_28 => '0',
LMB_Wait_28 => '0',
LMB_Ready_29 => '0',
LMB_Data_Read_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_29 => '0',
LMB_UE_29 => '0',
LMB_Wait_29 => '0',
LMB_Ready_30 => '0',
LMB_Data_Read_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_30 => '0',
LMB_UE_30 => '0',
LMB_Wait_30 => '0',
LMB_Ready_31 => '0',
LMB_Data_Read_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_31 => '0',
LMB_UE_31 => '0',
LMB_Wait_31 => '0',
M_AXIS_TREADY => '1',
TRACE_CLK => '0',
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Trig_In_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_0 => '0',
Dbg_Disable_0 => Dbg_Disable_0,
Dbg_AWREADY_0 => '0',
Dbg_WREADY_0 => '0',
Dbg_BRESP_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_0 => '0',
Dbg_ARREADY_0 => '0',
Dbg_RDATA_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_0 => '0',
Dbg_TDO_1 => '0',
Dbg_Trig_In_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_1 => '0',
Dbg_AWREADY_1 => '0',
Dbg_WREADY_1 => '0',
Dbg_BRESP_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_1 => '0',
Dbg_ARREADY_1 => '0',
Dbg_RDATA_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_1 => '0',
Dbg_TDO_2 => '0',
Dbg_Trig_In_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_2 => '0',
Dbg_AWREADY_2 => '0',
Dbg_WREADY_2 => '0',
Dbg_BRESP_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_2 => '0',
Dbg_ARREADY_2 => '0',
Dbg_RDATA_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_2 => '0',
Dbg_TDO_3 => '0',
Dbg_Trig_In_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_3 => '0',
Dbg_AWREADY_3 => '0',
Dbg_WREADY_3 => '0',
Dbg_BRESP_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_3 => '0',
Dbg_ARREADY_3 => '0',
Dbg_RDATA_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_3 => '0',
Dbg_TDO_4 => '0',
Dbg_Trig_In_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_4 => '0',
Dbg_AWREADY_4 => '0',
Dbg_WREADY_4 => '0',
Dbg_BRESP_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_4 => '0',
Dbg_ARREADY_4 => '0',
Dbg_RDATA_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_4 => '0',
Dbg_TDO_5 => '0',
Dbg_Trig_In_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_5 => '0',
Dbg_AWREADY_5 => '0',
Dbg_WREADY_5 => '0',
Dbg_BRESP_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_5 => '0',
Dbg_ARREADY_5 => '0',
Dbg_RDATA_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_5 => '0',
Dbg_TDO_6 => '0',
Dbg_Trig_In_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_6 => '0',
Dbg_AWREADY_6 => '0',
Dbg_WREADY_6 => '0',
Dbg_BRESP_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_6 => '0',
Dbg_ARREADY_6 => '0',
Dbg_RDATA_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_6 => '0',
Dbg_TDO_7 => '0',
Dbg_Trig_In_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_7 => '0',
Dbg_AWREADY_7 => '0',
Dbg_WREADY_7 => '0',
Dbg_BRESP_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_7 => '0',
Dbg_ARREADY_7 => '0',
Dbg_RDATA_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_7 => '0',
Dbg_TDO_8 => '0',
Dbg_Trig_In_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_8 => '0',
Dbg_AWREADY_8 => '0',
Dbg_WREADY_8 => '0',
Dbg_BRESP_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_8 => '0',
Dbg_ARREADY_8 => '0',
Dbg_RDATA_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_8 => '0',
Dbg_TDO_9 => '0',
Dbg_Trig_In_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_9 => '0',
Dbg_AWREADY_9 => '0',
Dbg_WREADY_9 => '0',
Dbg_BRESP_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_9 => '0',
Dbg_ARREADY_9 => '0',
Dbg_RDATA_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_9 => '0',
Dbg_TDO_10 => '0',
Dbg_Trig_In_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_10 => '0',
Dbg_AWREADY_10 => '0',
Dbg_WREADY_10 => '0',
Dbg_BRESP_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_10 => '0',
Dbg_ARREADY_10 => '0',
Dbg_RDATA_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_10 => '0',
Dbg_TDO_11 => '0',
Dbg_Trig_In_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_11 => '0',
Dbg_AWREADY_11 => '0',
Dbg_WREADY_11 => '0',
Dbg_BRESP_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_11 => '0',
Dbg_ARREADY_11 => '0',
Dbg_RDATA_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_11 => '0',
Dbg_TDO_12 => '0',
Dbg_Trig_In_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_12 => '0',
Dbg_AWREADY_12 => '0',
Dbg_WREADY_12 => '0',
Dbg_BRESP_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_12 => '0',
Dbg_ARREADY_12 => '0',
Dbg_RDATA_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_12 => '0',
Dbg_TDO_13 => '0',
Dbg_Trig_In_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_13 => '0',
Dbg_AWREADY_13 => '0',
Dbg_WREADY_13 => '0',
Dbg_BRESP_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_13 => '0',
Dbg_ARREADY_13 => '0',
Dbg_RDATA_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_13 => '0',
Dbg_TDO_14 => '0',
Dbg_Trig_In_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_14 => '0',
Dbg_AWREADY_14 => '0',
Dbg_WREADY_14 => '0',
Dbg_BRESP_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_14 => '0',
Dbg_ARREADY_14 => '0',
Dbg_RDATA_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_14 => '0',
Dbg_TDO_15 => '0',
Dbg_Trig_In_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_15 => '0',
Dbg_AWREADY_15 => '0',
Dbg_WREADY_15 => '0',
Dbg_BRESP_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_15 => '0',
Dbg_ARREADY_15 => '0',
Dbg_RDATA_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_15 => '0',
Dbg_TDO_16 => '0',
Dbg_Trig_In_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_16 => '0',
Dbg_AWREADY_16 => '0',
Dbg_WREADY_16 => '0',
Dbg_BRESP_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_16 => '0',
Dbg_ARREADY_16 => '0',
Dbg_RDATA_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_16 => '0',
Dbg_TDO_17 => '0',
Dbg_Trig_In_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_17 => '0',
Dbg_AWREADY_17 => '0',
Dbg_WREADY_17 => '0',
Dbg_BRESP_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_17 => '0',
Dbg_ARREADY_17 => '0',
Dbg_RDATA_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_17 => '0',
Dbg_TDO_18 => '0',
Dbg_Trig_In_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_18 => '0',
Dbg_AWREADY_18 => '0',
Dbg_WREADY_18 => '0',
Dbg_BRESP_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_18 => '0',
Dbg_ARREADY_18 => '0',
Dbg_RDATA_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_18 => '0',
Dbg_TDO_19 => '0',
Dbg_Trig_In_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_19 => '0',
Dbg_AWREADY_19 => '0',
Dbg_WREADY_19 => '0',
Dbg_BRESP_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_19 => '0',
Dbg_ARREADY_19 => '0',
Dbg_RDATA_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_19 => '0',
Dbg_TDO_20 => '0',
Dbg_Trig_In_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_20 => '0',
Dbg_AWREADY_20 => '0',
Dbg_WREADY_20 => '0',
Dbg_BRESP_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_20 => '0',
Dbg_ARREADY_20 => '0',
Dbg_RDATA_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_20 => '0',
Dbg_TDO_21 => '0',
Dbg_Trig_In_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_21 => '0',
Dbg_AWREADY_21 => '0',
Dbg_WREADY_21 => '0',
Dbg_BRESP_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_21 => '0',
Dbg_ARREADY_21 => '0',
Dbg_RDATA_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_21 => '0',
Dbg_TDO_22 => '0',
Dbg_Trig_In_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_22 => '0',
Dbg_AWREADY_22 => '0',
Dbg_WREADY_22 => '0',
Dbg_BRESP_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_22 => '0',
Dbg_ARREADY_22 => '0',
Dbg_RDATA_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_22 => '0',
Dbg_TDO_23 => '0',
Dbg_Trig_In_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_23 => '0',
Dbg_AWREADY_23 => '0',
Dbg_WREADY_23 => '0',
Dbg_BRESP_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_23 => '0',
Dbg_ARREADY_23 => '0',
Dbg_RDATA_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_23 => '0',
Dbg_TDO_24 => '0',
Dbg_Trig_In_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_24 => '0',
Dbg_AWREADY_24 => '0',
Dbg_WREADY_24 => '0',
Dbg_BRESP_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_24 => '0',
Dbg_ARREADY_24 => '0',
Dbg_RDATA_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_24 => '0',
Dbg_TDO_25 => '0',
Dbg_Trig_In_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_25 => '0',
Dbg_AWREADY_25 => '0',
Dbg_WREADY_25 => '0',
Dbg_BRESP_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_25 => '0',
Dbg_ARREADY_25 => '0',
Dbg_RDATA_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_25 => '0',
Dbg_TDO_26 => '0',
Dbg_Trig_In_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_26 => '0',
Dbg_AWREADY_26 => '0',
Dbg_WREADY_26 => '0',
Dbg_BRESP_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_26 => '0',
Dbg_ARREADY_26 => '0',
Dbg_RDATA_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_26 => '0',
Dbg_TDO_27 => '0',
Dbg_Trig_In_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_27 => '0',
Dbg_AWREADY_27 => '0',
Dbg_WREADY_27 => '0',
Dbg_BRESP_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_27 => '0',
Dbg_ARREADY_27 => '0',
Dbg_RDATA_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_27 => '0',
Dbg_TDO_28 => '0',
Dbg_Trig_In_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_28 => '0',
Dbg_AWREADY_28 => '0',
Dbg_WREADY_28 => '0',
Dbg_BRESP_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_28 => '0',
Dbg_ARREADY_28 => '0',
Dbg_RDATA_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_28 => '0',
Dbg_TDO_29 => '0',
Dbg_Trig_In_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_29 => '0',
Dbg_AWREADY_29 => '0',
Dbg_WREADY_29 => '0',
Dbg_BRESP_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_29 => '0',
Dbg_ARREADY_29 => '0',
Dbg_RDATA_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_29 => '0',
Dbg_TDO_30 => '0',
Dbg_Trig_In_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_30 => '0',
Dbg_AWREADY_30 => '0',
Dbg_WREADY_30 => '0',
Dbg_BRESP_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_30 => '0',
Dbg_ARREADY_30 => '0',
Dbg_RDATA_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_30 => '0',
Dbg_TDO_31 => '0',
Dbg_Trig_In_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_31 => '0',
Dbg_AWREADY_31 => '0',
Dbg_WREADY_31 => '0',
Dbg_BRESP_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_BVALID_31 => '0',
Dbg_ARREADY_31 => '0',
Dbg_RDATA_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_RRESP_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Dbg_RVALID_31 => '0',
bscan_ext_tdi => '0',
bscan_ext_reset => '0',
bscan_ext_shift => '0',
bscan_ext_update => '0',
bscan_ext_capture => '0',
bscan_ext_sel => '0',
bscan_ext_drck => '0',
Ext_JTAG_TDO => '0'
);
END system_mdm_1_0_arch;
|
apache-2.0
|
bd4362ba85ee72e01cd8115bb072d390
| 0.588325 | 2.877898 | false | false | false | false |
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