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FearlessJojo/COPproject
|
project/MEM_WB.vhd
| 1 | 1,684 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: MEM_WB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEM_WB is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
MEM_MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEM_Rd : in STD_LOGIC_VECTOR (3 downto 0);
MEM_regWE : in STD_LOGIC;
WB_MEMOUT : out STD_LOGIC_VECTOR (15 downto 0);
WB_Rd : out STD_LOGIC_VECTOR (3 downto 0);
WB_regWE : out STD_LOGIC);
end MEM_WB;
architecture Behavioral of MEM_WB is
begin
process(clk, rst)
begin
if (rst = '0') then
WB_regWE <= '0';
else
if (clk'event and clk = '1') then
if (enable = '1') then
WB_MEMOUT <= MEM_MEMOUT;
WB_Rd <= MEM_Rd;
WB_regWE <= MEM_regWE;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
6f6c19c252c4e15c53f98e781ad9eba4
| 0.55285 | 3.567797 | false | false | false | false |
FearlessJojo/COPproject
|
project/control.vhd
| 1 | 16,123 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:13:04 11/19/2016
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
Port ( Inst : in STD_LOGIC_VECTOR (15 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
Imm : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC;
NPC : in STD_LOGIC_VECTOR (15 downto 0);
OP : out STD_LOGIC_VECTOR (3 downto 0);
PCctrl : out STD_LOGIC_VECTOR (1 downto 0);
RFctrl : out STD_LOGIC_VECTOR (2 downto 0);
Immctrl : out STD_LOGIC_VECTOR (3 downto 0);
Rs : out STD_LOGIC_VECTOR (3 downto 0);
Rt : out STD_LOGIC_VECTOR (3 downto 0);
Rd : out STD_LOGIC_VECTOR (3 downto 0);
AccMEM : out STD_LOGIC;
memWE : out STD_LOGIC;
regWE : out STD_LOGIC;
DataIN : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0);
newT : out STD_LOGIC;
TE : out STD_LOGIC);
end control;
architecture Behavioral of control is
begin
process(Inst, A, B, Imm, T, NPC)
variable tmp : STD_LOGIC_VECTOR (15 downto 0);
begin
case Inst(15 downto 11) is
when "00001" => --NOP
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00010" => --B
OP <= "1111";
PCctrl <= "01";
RFctrl <= "000";
Immctrl <= "0011";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00100" => --BEQZ
OP <= "1111";
if (A="0000000000000000") then
PCctrl <= "01";
else
PCctrl <= "00";
end if;
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00101" => --BNEZ
OP <= "1111";
if (A="0000000000000000") then
PCctrl <= "00";
else
PCctrl <= "01";
end if;
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "00110" => --SLL|SRA
case Inst(1 downto 0) is
when "00" => --SLL
OP <= "0110";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0111";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11" => --SRA
OP <= "1000";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0111";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01000" => --ADDIU3
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0010";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(7 downto 5);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01001" => --ADDIU
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01010" => --SLTI
OP <= "1111";
tmp := A - Imm;
newT <= tmp(15);
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0001";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
TE <= '1';
when "01100" => --ADDSP|BTEQZ|MTSP
case Inst(10 downto 8) is
when "011" => --ADDSP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "100";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "1111";
Rd <= "1000";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "000" => --BTEQZ
OP <= "1111";
if (T='0') then
PCctrl <= "01";
else
PCctrl <= "00";
end if;
RFctrl <= "000";
Immctrl <= "0001";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "100" => --MTSP
OP <= "1010";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "1000";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01101" => --LI
OP <= "1011";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0100";
Rs <= "1111";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01111" => --MOVE
OP <= "1010";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "10010" => --LW_SP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "100";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '1';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "10011" => --LW
OP <= "0000";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0101";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "0" & Inst(7 downto 5);
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '1';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11010" => --SW_SP
OP <= "0000";
PCctrl <= "00";
RFctrl <= "111";
Immctrl <= "0001";
Rs <= "1000";
Rt <= "0" & Inst(10 downto 8);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '1';
regWE <= '0';
DataIN <= B;
newT <= '0';
TE <= '0';
when "11011" => --SW
OP <= "0000";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0101";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '1';
regWE <= '0';
DataIN <= B;
newT <= '0';
TE <= '0';
when "11100" => --ADDU|SUBU
case Inst(1 downto 0) is
when "01" => --ADDU
OP <= "0000";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(4 downto 2);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "11" => --SUBU
OP <= "0001";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(4 downto 2);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "11101" => --AND|CMP|JR|JALR|JRRA|MFPC|NOT|OR
case Inst(4 downto 0) is
when "01100" => --AND
OP <= "0010";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01010" => --CMP
OP <= "1111";
if (A=B) then
newT <= '0';
else
newT <= '1';
end if;
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
TE <= '1';
when "00000" => --JR|JALR|JRRA|MFPC
case Inst(7 downto 5) is
when "000" => --JR
OP <= "1111";
PCctrl <= "11";
RFctrl <= "001";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "110" => --JALR
OP <= "0000";
PCctrl <= "11";
RFctrl <= "001";
Immctrl <= "1000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1010";
ALUIN1 <= NPC;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "001" => --JRRA
OP <= "1111";
PCctrl <= "11";
RFctrl <= "101";
Immctrl <= "0000";
Rs <= "1010";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "010" => --MFPC
OP <= "1010";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "1000";
Rs <= "1111";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= NPC;
ALUIN2 <= Imm;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "01111" => --NOT
OP <= "0101";
PCctrl <= "00";
RFctrl <= "011";
Immctrl <= "0000";
Rs <= "0" & Inst(7 downto 5);
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when "01101" => --OR
OP <= "0011";
PCctrl <= "00";
RFctrl <= "010";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "0" & Inst(7 downto 5);
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when "11110" => --MFIH|MTIH
case Inst(0) is
when '0' => --MFIH
OP <= "1010";
PCctrl <= "00";
RFctrl <= "110";
Immctrl <= "0000";
Rs <= "1001";
Rt <= "1111";
Rd <= "0" & Inst(10 downto 8);
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when '1' => --MTIH
OP <= "1010";
PCctrl <= "00";
RFctrl <= "001";
Immctrl <= "0000";
Rs <= "0" & Inst(10 downto 8);
Rt <= "1111";
Rd <= "1001";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '1';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
when others =>
OP <= "1111";
PCctrl <= "00";
RFctrl <= "000";
Immctrl <= "0000";
Rs <= "1111";
Rt <= "1111";
Rd <= "1111";
ALUIN1 <= A;
ALUIN2 <= B;
AccMEM <= '0';
memWE <= '0';
regWE <= '0';
DataIN <= "0000000000000000";
newT <= '0';
TE <= '0';
end case;
end process;
end Behavioral;
|
mit
|
ca4e14c9e6395f34555d6760b48d49d5
| 0.414005 | 3.022685 | false | false | false | false |
FearlessJojo/COPproject
|
project/IF_ID.vhd
| 1 | 1,582 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: IF_ID - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IF_ID is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
IF_Inst : in STD_LOGIC_VECTOR (15 downto 0);
IF_NPC :in STD_LOGIC_VECTOR(15 DOWNTO 0);
ID_Inst : out STD_LOGIC_VECTOR (15 downto 0);
ID_NPC :out STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_RAM2 : in STD_LOGIC
);
end IF_ID;
architecture Behavioral of IF_ID is
begin
process(clk, rst)
begin
if (rst = '0') then
ID_Inst <= "0000100000000000";
ID_NPC <= "0000000000000000";
else
if (clk'event and clk = '1') then
if (enable = '1')and(MEM_RAM2 = '0')then
ID_Inst <= IF_Inst;
ID_NPC <= IF_NPC;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
ec837492cee2997cc68bf494f25dce3b
| 0.58976 | 3.337553 | false | false | false | false |
gustavowl/ProjetoOAC
|
Multiplicador64Bit_tb.vhd
| 1 | 488 |
library ieee;
use ieee.std_logic_1164.all;
entity mult64_tb is
end mult64_tb;
architecture mult64_tb of mult64_tb is
signal sclk, sstart, sdone: std_logic;
signal mtplcnd, res: std_logic_vector(63 downto 0);
signal mtplcdr: std_logic_vector(31 downto 0);
begin
vector: entity work.mult64
port map (
multiplicando => mtplcnd,
multiplicador => mtplcdr,
clk => sclk,
start => sstart,
produto => res,
done => sdone
);
process
begin
wait;
end process;
end mult64_tb;
|
gpl-2.0
|
77198b77b348664b762844c8eaca65ff
| 0.704918 | 2.820809 | false | false | false | false |
h397wang/Lab1
|
lab1-fans/lab1_code.vhd
| 1 | 2,149 |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- The above libaries lines must be included in every VHDL file, before EVERY ENTITY!
--
-- Main circuit Entity: connects all wires to the FPGA IO pins.
-- PORT mapping - declare all wire connections to INput or OUTput pins.
-- Note that all signal names here are fixed by the "DE2_pins.csv" file which you must use for every lab
--
entity Lab1 is port(
key : in std_logic_vector(2 downto 0); -- 3 push buttons on the board - HIGH when not pressed
sw : in std_logic_vector(1 downto 1); -- use 1 out of 18 switches on the board LOW when down towards edge of board
ledr : out std_logic_vector(0 downto 0); -- 1 red LED, if lit, indicates brake control is on
ledg : out std_logic_vector(0 downto 0) -- 1 green LED, if lit, indicates gas control is on
);
end Lab1;
architecture CarSimulator of Lab1 is
--
-- Create the temporary variables reprensting our input signals
--
-- Signals are either a vector or not. A vector is a group of two or more signals
--
-- Note that there are two basic types and we nearly always use std_logic:
-- UNSIGNED is a signal which can be used to perform math operations such as +, -, *
-- std_logic_vector is a signal which can be used for logic operations such as OR, AND, NOT, XOR
--
signal gas, clutch, brake, override: std_logic; -- four signals for inputs
signal gas_control, brake_control: std_logic; -- two signals for LED outputs (one green and one red)
-- The function of CarSimulator entity is defined here
begin
-- Associate the input signals with the corresponding engine function
gas <= not key(0);
clutch <= not key(1);
brake <= not key(2);
override <= not sw(1);
-- The outputs of gas_control and brake_control are defined with the following boolean functions
gas_control <= (not override) and (not brake) and (not clutch) and gas;
brake_control <= override or brake;
-- assign intermediate signals to output ports
ledg(0) <= gas_control;
ledr(0) <= brake_control;
end CarSimulator;
|
apache-2.0
|
f358f15c6d42920c803fd47e0d86e239
| 0.68497 | 3.730903 | false | false | false | false |
h397wang/Lab1
|
lab1-fans/lab1.vhd
| 1 | 2,182 |
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- The above libaries lines must be included in every VHDL file, before EVERY ENTITY!
--
-- Main circuit Entity: connects all wires to the FPGA IO pins.
-- PORT mapping - declare all wire connections to INput or OUTput pins.
-- Note that all signal names here are fixed by the "DE2_pins.csv" file which you must use for every lab
--
entity Lab1 is port(
key : in std_logic_vector(2 downto 0); -- 3 push buttons on the board - HIGH when not pressed
sw : in std_logic_vector(1 downto 1); -- use 1 out of 18 switches on the board LOW when down towards edge of board
ledr : out std_logic_vector(0 downto 0); -- 1 red LED, if lit, indicates brake control is on
ledg : out std_logic_vector(0 downto 0) -- 1 green LED, if lit, indicates gas control is on
);
end Lab1;
architecture CarSimulator of Lab1 is
--
-- Create the temporary variables reprensting our input signals
--
-- Signals are either a vector or not. A vector is a group of two or more signals
--
-- Note that there are two basic types and we nearly always use std_logic:
-- UNSIGNED is a signal which can be used to perform math operations such as +, -, *
-- std_logic_vector is a signal which can be used for logic operations such as OR, AND, NOT, XOR
--
signal gas, clutch, brake, override: std_logic; -- four signals for inputs
signal gas_control, brake_control: std_logic; -- two signals for LED outputs, green for gas, red for brake
-- The function of CarSimulator entity is defined here
begin
-- Associate the input signals with the corresponding engine function
-- The inputs are inverted to provide a conventionial user interface
gas <= not key(0);
clutch <= not key(1);
brake <= not key(2);
override <= not sw(1);
-- The outputs of gas_control and brake_control are defined with the following boolean functions
gas_control <= (not override) and (not brake) and (not clutch) and gas;
brake_control <= override or brake;
-- assign intermediate signals to output ports
ledg(0) <= gas_control;
ledr(0) <= brake_control;
end CarSimulator;
|
apache-2.0
|
d44138438cc6e02b0aad38bc4c94ee5b
| 0.702566 | 3.801394 | false | false | false | false |
corywalker/vhdl_fft
|
spi_mux.vhd
| 3 | 717 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity spi_mux is
port(
sck_a_o: out std_logic;
sck_b_o: out std_logic;
sck_i: in std_logic;
conv_a_o: out std_logic;
conv_b_o: out std_logic;
conv_i: in std_logic;
miso_a_i: in std_logic;
miso_b_i: in std_logic;
miso_o: out std_logic;
sel_i: in std_logic
);
end spi_mux;
architecture Behavioral of spi_mux is
begin
sck_a_o <= sck_i when sel_i = '0' else 'Z';
sck_b_o <= sck_i when sel_i = '1' else 'Z';
conv_a_o <= conv_i when sel_i = '0' else 'Z';
conv_b_o <= conv_i when sel_i = '1' else 'Z';
miso_o <= miso_a_i when sel_i = '0' else miso_b_i;
end Behavioral;
|
mit
|
58cbe8ff7bbfe4750f3c6e103f96245e
| 0.548117 | 2.597826 | false | false | false | false |
FearlessJojo/COPproject
|
project/main.vhd
| 1 | 15,307 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:24:26 11/18/2016
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port ( --FLASH_A : out STD_LOGIC_VECTOR (22 downto 0);
--FLASH_D : inout STD_LOGIC_VECTOR (15 downto 0);
--FPGA_KEY : in STD_LOGIC_VECTOR (3 downto 0);
CLK2 : in STD_LOGIC;
--CLK1 : in STD_LOGIC;
--LCD_CS1 : out STD_LOGIC;
--LCD_CS2 : out STD_LOGIC;
--LCD_DB : inout STD_LOGIC_VECTOR (7 downto 0);
--LCD_E : out STD_LOGIC;
--LCD_RESET : out STD_LOGIC;
--LCD_RS : out STD_LOGIC;
--LCD_RW : out STD_LOGIC;
--VGA_R : out STD_LOGIC_VECTOR (2 downto 0);
--VGA_G : out STD_LOGIC_VECTOR (2 downto 0);
--VGA_B : out STD_LOGIC_VECTOR (2 downto 0);
--VGA_HHYNC : out STD_LOGIC;
--VGA_VHYNC : out STD_LOGIC;
--PS2KB_CLOCK : out STD_LOGIC;
--PS2KB_DATA : in STD_LOGIC;
RAM1DATA : inout STD_LOGIC_VECTOR (15 downto 0);
--SW_DIP : in STD_LOGIC_VECTOR (15 downto 0);
--FLASH_BYTE : out STD_LOGIC;
--FLASH_CE : out STD_LOGIC;
--FLASH_CE1 : out STD_LOGIC;
--FLASH_CE2 : out STD_LOGIC;
--FLASH_OE : out STD_LOGIC;
--FLASH_RP : out STD_LOGIC;
--FLASH_STS : out STD_LOGIC;
--FLASH_VPEN : out STD_LOGIC;
--FLASH_WE : out STD_LOGIC;
--U_RXD : out STD_LOGIC;
--U_TXD : out STD_LOGIC;
RAM2DATA : inout STD_LOGIC_VECTOR (15 downto 0);
RAM1EN : out STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1WE : out STD_LOGIC;
L : out STD_LOGIC_VECTOR (15 downto 0);
RAM2EN : out STD_LOGIC;
RAM2OE : out STD_LOGIC;
RAM2WE : out STD_LOGIC;
RAM1ADDR : out STD_LOGIC_VECTOR (17 downto 0);
RAM2ADDR : out STD_LOGIC_VECTOR (17 downto 0);
--DYP0 : out STD_LOGIC_VECTOR (6 downto 0);
--DYP1 : out STD_LOGIC_VECTOR (6 downto 0);
--CLK_FROM_KEY : in STD_LOGIC;
RESET : in STD_LOGIC;
rdn: out STD_LOGIC;
wrn: out STD_LOGIC;
data_ready: in STD_LOGIC;
tbre: in STD_LOGIC;
tsre: in STD_LOGIC
);
end main;
architecture Behavioral of main is
component ALU is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ALUIN1 : in STD_LOGIC_VECTOR (15 downto 0);
ALUIN2 : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component ALUMUX1 is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
ALUctrl1 : in STD_LOGIC_VECTOR (1 downto 0);
ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component ALUMUX2 is
Port ( B : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
ALUctrl2 : in STD_LOGIC_VECTOR (1 downto 0);
ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component control is
Port ( Inst : in STD_LOGIC_VECTOR (15 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
Imm : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC;
NPC : in STD_LOGIC_VECTOR (15 downto 0);
OP : out STD_LOGIC_VECTOR (3 downto 0);
PCctrl : out STD_LOGIC_VECTOR (1 downto 0);
RFctrl : out STD_LOGIC_VECTOR (2 downto 0);
Immctrl : out STD_LOGIC_VECTOR (3 downto 0);
Rs : out STD_LOGIC_VECTOR (3 downto 0);
Rt : out STD_LOGIC_VECTOR (3 downto 0);
Rd : out STD_LOGIC_VECTOR (3 downto 0);
AccMEM : out STD_LOGIC;
memWE : out STD_LOGIC;
regWE : out STD_LOGIC;
DataIN : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0);
ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0);
newT : out STD_LOGIC;
TE : out STD_LOGIC);
end component;
component EXE_MEM is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
EXE_ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
EXE_Rd : in STD_LOGIC_VECTOR (3 downto 0);
EXE_AccMEM : in STD_LOGIC;
EXE_memWE : in STD_LOGIC;
EXE_regWE : in STD_LOGIC;
EXE_DataIN : in STD_LOGIC_VECTOR (15 downto 0);
MEM_ALUOUT : out STD_LOGIC_VECTOR (15 downto 0);
MEM_Rd : out STD_LOGIC_VECTOR (3 downto 0);
MEM_AccMEM : out STD_LOGIC;
MEM_memWE : out STD_LOGIC;
MEM_regWE : out STD_LOGIC;
MEM_DataIN : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC
);
end component;
component Forwarding is
Port ( ID_Rs : in STD_LOGIC_VECTOR (3 downto 0);
ID_Rt : in STD_LOGIC_VECTOR (3 downto 0);
ID_EXE_Rd : in STD_LOGIC_VECTOR (3 downto 0);
ID_EXE_regWE : in STD_LOGIC;
ID_EXE_AccMEM : in STD_LOGIC;
EXE_MEM_Rd : in STD_LOGIC_VECTOR (3 downto 0);
EXE_MEM_regWE : in STD_LOGIC;
PCReg_enable : out STD_LOGIC;
IF_ID_enable : out STD_LOGIC;
ID_EXE_enable : out STD_LOGIC;
ID_EXE_bubble : out STD_LOGIC;
ALUctrl1 : out STD_LOGIC_VECTOR (1 downto 0);
ALUctrl2 : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
component ID_EXE is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
bubble : in STD_LOGIC;
ID_ALUIN1 : in STD_LOGIC_VECTOR (15 downto 0);
ID_ALUIN2 : in STD_LOGIC_VECTOR (15 downto 0);
ID_OP : in STD_LOGIC_VECTOR (3 downto 0);
ID_Rd : in STD_LOGIC_VECTOR (3 downto 0);
ID_AccMEM : in STD_LOGIC;
ID_memWE : in STD_LOGIC;
ID_regWE : in STD_LOGIC;
ID_DataIN : in STD_LOGIC_VECTOR (15 downto 0);
EXE_ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0);
EXE_ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0);
EXE_OP : out STD_LOGIC_VECTOR (3 downto 0);
EXE_Rd : out STD_LOGIC_VECTOR (3 downto 0);
EXE_AccMEM : out STD_LOGIC;
EXE_memWE : out STD_LOGIC;
EXE_regWE : out STD_LOGIC;
EXE_DataIN : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2 : in STD_LOGIC
);
end component;
component IF_ID is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
IF_Inst : in STD_LOGIC_VECTOR (15 downto 0);
IF_NPC : in STD_LOGIC_VECTOR(15 DOWNTO 0);
ID_Inst : out STD_LOGIC_VECTOR (15 downto 0);
ID_NPC : out STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_RAM2 : in STD_LOGIC
);
end component;
component IM is
Port ( PC : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
--stateclk : in STD_LOGIC;
rst : in STD_LOGIC;
Ram2OE : out STD_LOGIC;
Ram2WE : out STD_LOGIC;
Ram2EN : out STD_LOGIC;
Ram2Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram2Data : inout STD_LOGIC_VECTOR (15 downto 0);
Inst : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC;
MEM_ACCMEM: in STD_LOGIC;
MEM_ALUOUT:in STD_LOGIC_VECTOR (15 downto 0);
MEM_DATAIN: in STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component Imm is
Port ( Immctrl : in STD_LOGIC_VECTOR (3 downto 0);
Inst : in STD_LOGIC_VECTOR (10 downto 0);
Imm : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component MEM_WB is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
MEM_MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEM_Rd : in STD_LOGIC_VECTOR (3 downto 0);
MEM_regWE : in STD_LOGIC;
WB_MEMOUT : out STD_LOGIC_VECTOR (15 downto 0);
WB_Rd : out STD_LOGIC_VECTOR (3 downto 0);
WB_regWE : out STD_LOGIC
);
end component;
component MEMMUX is
Port ( ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
DataOUT : in STD_LOGIC_VECTOR (15 downto 0);
ACCMEM : in STD_LOGIC;
MEMOUT : out STD_LOGIC_VECTOR (15 downto 0);
IMOUT: in STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2:in STD_LOGIC);
end component;
component PCMUX is
Port ( NPC : in STD_LOGIC_VECTOR (15 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
adderOUT : in STD_LOGIC_VECTOR (15 downto 0);
PCctrl : in STD_LOGIC_VECTOR (1 downto 0);
PCIN : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component PCReg is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
NPC : in STD_LOGIC_VECTOR (15 downto 0);
PC : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC;
L:out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component RAM_UART is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ACCMEM : in STD_LOGIC;
MEM_WE : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (15 downto 0);
data : in STD_LOGIC_VECTOR (15 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0);
Ram1Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram1Data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1OE : out STD_LOGIC;
Ram1WE : out STD_LOGIC;
Ram1EN : out STD_LOGIC;
wrn : out STD_LOGIC;
rdn : out STD_LOGIC;
data_ready : in STD_LOGIC;
tbre : in STD_LOGIC;
tsre : in STD_LOGIC;
MEM_RAM2: in STD_LOGIC);
end component;
component RF is
Port ( regWE : in STD_LOGIC;
RFctrl : in STD_LOGIC_VECTOR (2 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
Rd : in STD_LOGIC_VECTOR (3 downto 0);
Inst : in STD_LOGIC_VECTOR (5 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (15 downto 0);
B : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component T is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
T_in : in STD_LOGIC;
T_reg : out STD_LOGIC);
end component;
component Adder is
Port (
NPC : in STD_LOGIC_VECTOR(15 downto 0);
Imm : in STD_LOGIC_VECTOR(15 downto 0);
RPC : out STD_LOGIC_VECTOR(15 downto 0));
end component;
component PC_Adder is
Port (
PC : in STD_LOGIC_VECTOR(15 downto 0);
NPC : out STD_LOGIC_VECTOR(15 downto 0));
end component;
signal MEM_RAM2,ID_T,ID_AccMEM,ID_memWE,ID_regWE,ID_newT,ID_TE,EXE_AccMEM,EXE_memWE,EXE_regWE,MEM_AccMEM,MEM_memWE,MEM_regWE,PCReg_enable,IF_ID_enable,ID_EXE_enable,ID_EXE_bubble,WB_regWE : STD_LOGIC:='0';
signal ALUctrl1,ALUctrl2,PCctrl :STD_LOGIC_VECTOR(1 DOWNTO 0);
signal RFctrl :STD_LOGIC_VECTOR(2 DOWNTO 0);
signal ID_OP,EXE_OP,Immctrl,ID_Rs,ID_Rt,ID_Rd,EXE_Rd,MEM_Rd,WB_Rd :STD_LOGIC_VECTOR(3 DOWNTO 0);
signal EXE_ALUOUT,EXE_ALUIN1,EXE_ALUIN2,ID_A0,ID_B0,MEM_MEMOUT,ID_A,ID_B,ID_Inst,ID_DataIN,ID_ALUIN1,ID_ALUIN2,EXE_DataIN,MEM_ALUOUT,MEM_DataIN,IF_Inst,IF_NPC,ID_NPC,ID_Imm,WB_MEMOUT,DataOUT,adderOUT,PCIN,PC :STD_LOGIC_VECTOR(15 downto 0):="1111111111111111";
signal state0, state1, CLK0, CLK1 : STD_LOGIC := '0';
begin
ALU_module:ALU PORT MAP(EXE_OP,EXE_ALUIN1,EXE_ALUIN2,EXE_ALUOUT);
ALUMUX1_module:ALUMUX1 PORT MAP(ID_A0,EXE_ALUOUT,MEM_MEMOUT,ALUctrl1,ID_A);
ALUMUX2_module:ALUMUX2 PORT MAP(ID_B0,EXE_ALUOUT,MEM_MEMOUT,ALUctrl2,ID_B);
control_module:control PORT MAP(ID_Inst,ID_A,ID_B,ID_Imm,ID_T,ID_NPC,ID_OP,PCctrl,RFctrl,Immctrl,ID_Rs,ID_Rt,ID_Rd,ID_AccMEM,ID_memWE,ID_regWE,ID_DataIN,ID_ALUIN1,ID_ALUIN2,ID_newT,ID_TE);
EXE_MEM_module:EXE_MEM PORT MAP(CLK0,RESET,'1',EXE_ALUOUT,EXE_Rd,EXE_AccMEM,EXE_memWE,EXE_regWE,EXE_DataIN,MEM_ALUOUT,MEM_Rd,MEM_AccMEM,MEM_memWE,MEM_regWE,MEM_DataIN,MEM_RAM2);
Forwarding_module:Forwarding PORT MAP(ID_Rs ,ID_Rt ,EXE_Rd ,EXE_regWE ,EXE_AccMEM ,MEM_Rd ,MEM_regWE ,PCReg_enable ,IF_ID_enable ,ID_EXE_enable ,ID_EXE_bubble ,ALUctrl1 ,ALUctrl2);
ID_EXE_module:ID_EXE PORT MAP(CLK0 ,RESET ,ID_EXE_enable ,ID_EXE_bubble ,ID_ALUIN1 ,ID_ALUIN2 ,ID_OP ,ID_Rd ,ID_AccMEM ,ID_memWE ,ID_regWE ,ID_DataIN ,EXE_ALUIN1 ,EXE_ALUIN2 ,EXE_OP ,EXE_Rd ,EXE_AccMEM ,EXE_memWE ,EXE_regWE ,EXE_DataIN,MEM_RAM2);
IF_ID_module:IF_ID PORT MAP(CLK0 ,RESET ,IF_ID_enable ,IF_Inst ,IF_NPC ,ID_Inst ,ID_NPC,MEM_RAM2);
IM_module:IM PORT MAP(PC ,CLK1 , RESET ,RAM2OE ,RAM2WE ,RAM2EN ,RAM2ADDR ,RAM2DATA ,IF_Inst,MEM_RAM2,MEM_AccMEM,MEM_ALUOUT,MEM_DataIN);
Imm_module:Imm PORT MAP(Immctrl,ID_Inst(10 downto 0),ID_Imm);
MEM_WB_module:MEM_WB PORT MAP(CLK0 ,RESET ,'1' ,MEM_MEMOUT ,MEM_Rd ,MEM_regWE ,WB_MEMOUT ,WB_Rd ,WB_regWE);
MEMMUX_module:MEMMUX PORT MAP(MEM_ALUOUT ,DataOUT ,MEM_AccMEM ,MEM_MEMOUT,IF_Inst,MEM_RAM2);
PCMUX_module:PCMUX PORT MAP(IF_NPC ,ID_A ,adderOUT ,PCctrl ,PCIN);
PCReg_module:PCReg PORT MAP(CLK0 ,RESET ,PCReg_enable ,PCIN ,PC,MEM_RAM2,L);
RAM_UART_module:RAM_UART PORT MAP(CLK1 ,RESET,MEM_AccMEM ,MEM_memWE ,MEM_ALUOUT ,MEM_DataIN ,DataOUT,RAM1ADDR ,RAM1DATA ,RAM1OE ,RAM1WE ,RAM1EN ,wrn ,rdn,data_ready,tbre,tsre,MEM_RAM2);
RF_module:RF PORT MAP(WB_regWE ,RFctrl ,WB_MEMOUT ,WB_Rd ,ID_Inst(10 downto 5) ,CLK0 ,RESET ,ID_A0 ,ID_B0);
T_module:T PORT MAP(CLK0,RESET, ID_TE, ID_newT,ID_T);
Adder_module:Adder PORT MAP(ID_NPC, ID_Imm,adderOUT);
PC_Adder_module:PC_Adder PORT MAP(PC,IF_NPC);
process(MEM_ALUOUT,MEM_ACCMEM,MEM_MEMWE)
begin
if (MEM_ALUOUT(15) = '0')and(MEM_ALUOUT(14) = '1')and((MEM_ACCMEM = '1')or(MEM_MEMWE = '1')) then
MEM_RAM2 <= '1';
else
MEM_RAM2 <= '0';
end if;
end process;
process(CLK1)
begin
if (CLK1'event and CLK1 = '1') then
if (state0 = '0') then
CLK0 <= '1';
else
CLK0 <= '0';
end if;
state0 <= not state0;
end if;
end process;
--process(CLK2)
--begin
-- if (CLK2'event and CLK2 = '1') then
-- if (state1 = '0') then
-- CLK1 <= '1';
-- else
-- CLK1 <= '0';
-- end if;
-- state1 <= not state1;
-- end if;
--end process;
CLK1 <= CLK2;
end Behavioral;
|
mit
|
9c52bcc362f42362db8612355d74d60e
| 0.577971 | 3.113077 | false | false | false | false |
gustavowl/ProjetoOAC
|
ULA32bit/ula_tb.vhd
| 1 | 1,041 |
library ieee;
use ieee.std_logic_1164.all;
entity ula_tb is
end ula_tb;
architecture ula_tb of ula_tb is
signal ma, mb, ms: std_logic_vector(31 downto 0);
signal mw, mx, my, mz, mcout, mclk, mdo_op, mdone, mst: std_logic;
begin
vector: entity work.ula
port map (
a => ma,
b => mb,
s => ms,
x => mx,
y => my,
z => mz,
clk => mclk,
do_op => mdo_op,
done => mdone,
state => mst,
couterro => mcout
);
process
begin
ma <= "00111111111111100000000000001010";
mb <= "00111111111111100000000000000010";
mw <= '0';
mx <= '0';
my <= '0';
mz <= '0';
wait for 50 ns;
mx <= '0';
my <= '0';
mz <= '1';
wait for 50 ns;
mx <= '0';
my <= '1';
mz <= '0';
wait for 50 ns;
mx <= '0';
my <= '1';
mz <= '1';
wait for 50 ns;
mx <= '1';
my <= '0';
mz <= '0';
wait for 50 ns;
mx <= '1';
my <= '0';
mz <= '1';
wait for 50 ns;
mx <= '1';
my <= '1';
mz <= '0';
wait for 50 ns;
mx <= '1';
my <= '1';
mz <= '1';
wait for 50 ns;
wait;
end process;
end ula_tb;
|
gpl-2.0
|
6ceaf994a0fedc0449171831674c4e19
| 0.498559 | 2.323661 | false | false | false | false |
krabo0om/pauloBlaze
|
sources/io_module.vhd
| 2 | 3,068 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.op_codes.all;
entity io_module is
Port (
clk : in STD_LOGIC;
clk2 : in STD_LOGIC;
reset : in std_logic;
reg_value : out unsigned (7 downto 0);
reg_we : out std_logic;
reg_reg0 : in unsigned (7 downto 0);
reg_reg1 : in unsigned (7 downto 0);
out_data : in unsigned (7 downto 0);
io_op_in : in std_logic;
io_op_out : in std_logic;
io_op_out_pp : in std_logic;
io_kk_en : in std_logic;
io_kk_port : in unsigned (3 downto 0);
io_kk_data : in unsigned (7 downto 0);
-- actual i/o module ports
in_port : in unsigned (7 downto 0);
port_id : out unsigned (7 downto 0);
out_port : out unsigned (7 downto 0);
read_strobe : out STD_LOGIC;
write_strobe : out STD_LOGIC;
k_write_strobe : out STD_LOGIC
);
end io_module;
architecture Behavioral of io_module is
signal strobe_o : std_logic;
begin
reg_value <= in_port;
read_strobe <= io_op_in and not clk2;
write_strobe <= io_op_out and strobe_o and clk2;
k_write_strobe <= io_kk_en and strobe_o and clk2;
reg_we <= io_op_in and clk2;
out_proc : process (reset, out_data, reg_reg0, reg_reg1, io_kk_en, io_kk_port, io_kk_data, io_op_out_pp) begin
if (reset = '1') then
port_id <= (others => '0');
out_port <= (others => '0');
else
if (io_kk_en = '1') then
port_id <= x"0" & io_kk_port;
out_port <= io_kk_data;
else
out_port <= reg_reg0;
if (io_op_out_pp = '1') then -- intermediate value pp
port_id <= out_data;
else
port_id <= reg_reg1;
end if;
end if;
end if;
end process out_proc;
process (clk) begin
if (rising_edge(clk)) then
if (reset = '1') then
strobe_o <= '0';
else
if ((io_op_in or io_op_out or io_kk_en) = '1') then
strobe_o <= '1';
else
strobe_o <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
apache-2.0
|
f4956141d443d708a92959eed1029396
| 0.574316 | 2.96999 | false | false | false | false |
FearlessJojo/COPproject
|
project/IM.vhd
| 1 | 3,235 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: IM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IM is
Port ( PC : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Ram2OE : out STD_LOGIC;
Ram2WE : out STD_LOGIC;
Ram2EN : out STD_LOGIC;
Ram2Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram2Data : inout STD_LOGIC_VECTOR (15 downto 0);
Inst : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC;
MEM_ACCMEM: in STD_LOGIC;
MEM_ALUOUT:in STD_LOGIC_VECTOR (15 downto 0);
MEM_DATAIN: in STD_LOGIC_VECTOR (15 downto 0));
end IM;
architecture Behavioral of IM is
signal savedPC : std_logic_vector (15 downto 0) := "1111111111111111";
signal state : std_logic := '0';
begin
Ram2Addr(17 downto 16) <= "00";
process(clk, rst)
begin
if (clk'event and clk = '0') then
if (MEM_RAM2 = '0') then
if (state='0') then
if (PC /= savedPC) then
savedPC <= PC;
Ram2OE <= '0';
Ram2WE <= '1';
Ram2EN <= '0';
Ram2Addr(15 downto 0) <= PC;
Ram2Data <= "ZZZZZZZZZZZZZZZZ";
state <= '1';
else
Ram2OE <= '1';
Ram2EN <= '1';
Ram2WE <= '1';
Ram2Addr(15 downto 0) <= PC;
Ram2Data <= "ZZZZZZZZZZZZZZZZ";
end if;
else
state <= '0';
end if;
end if;
if (MEM_RAM2 = '1')and(MEM_ACCMEM='1') then
case state is
when '0' =>
Ram2EN <= '0';
Ram2WE <= '1';
Ram2OE <= '0';
RAM2Data <= "ZZZZZZZZZZZZZZZZ";
RAM2Addr(15 downto 0) <= MEM_ALUOUT;
state <= '1';
when '1' =>
state <= '0';
when others => null;
end case;
end if;
if (MEM_RAM2 = '1')and(MEM_ACCMEM='0') then
case state is
when '0'=>
Ram2EN <= '0';
Ram2OE <= '1';
Ram2WE <= '1';
RAM2Addr(15 downto 0) <= MEM_ALUOUT;
RAM2Data <= MEM_DATAIN;
state <= '1';
when '1' => Ram2WE <= '0';
state <= '0';
when others => null;
end case;
end if;
end if;--edge
if (rst = '0') then
state <= '0';
savedPC <= "1111111111111111";
Ram2EN <= '1';
Ram2OE <= '1';
Ram2WE <= '1';
end if;
end process;
process (Ram2data)
begin
Inst <= Ram2Data;
end process;
end Behavioral;
|
mit
|
fde020dc24e7a6ee371eb7ac646c8ad0
| 0.515301 | 3.165362 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/wb.vhd
| 1 | 847 |
library ieee;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb is
port (ctrl_memtoreg_in: in std_logic;
ctrl_regwrite_in: in std_logic;
ctrl_regwrite_out: out std_logic;
alu_in : in std_logic_vector (31 downto 0);
mem_in: in std_logic_vector (31 downto 0);
mux_out : out std_logic_vector (31 downto 0);
write_addr_in: in std_logic_vector (4 downto 0);
write_addr_out: out std_logic_vector (4 downto 0)
);
end wb;
architecture behavioral of wb is
begin
process(alu_in, mem_in, ctrl_memtoreg_in, ctrl_regwrite_in)
begin
write_addr_out <= write_addr_in;
ctrl_regwrite_out <= ctrl_regwrite_in;
case ctrl_memtoreg_in is
--ALU
when '0' =>
mux_out <= alu_in;
--MEM
when '1' =>
mux_out <= mem_in;
when others =>
mux_out <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
end behavioral;
|
gpl-3.0
|
e05f59c5a33f5630f3516c89b1350519
| 0.68595 | 2.758958 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/cpuPipeline_tb.vhd
| 1 | 1,146 |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cpuPipeline_tb is
end cpuPipeline_tb;
architecture cpuPipeline_tb_arch of cpuPipeline_tb is
component cpuPipeline is
port
(
clk : in std_logic;
reset : in std_logic;
four : INTEGER;
writeToRegisterFile : in std_logic;
writeToMemoryFile : in std_logic
);
end component;
constant clk_period : time := 1 ns;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal fourInt : INTEGER := 4;
signal writeToRegisterFile : std_logic := '0';
signal writeToMemoryFile : std_logic := '0';
begin
pipeline : cpuPipeline
port map(
clk => clk,
reset => rst,
four => fourInt,
writeToMemoryFile => writeToRegisterFile,
writeToRegisterFile => writeToMemoryFile
);
clk_process : process
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
BEGIN
wait for clk_period;
report "STARTING SIMULATION \n";
wait for 10000* clk_period;
writeToRegisterFile <= '1';
writeToMemoryFile <= '1';
wait;
end process;
end cpuPipeline_tb_arch;
|
gpl-3.0
|
aa48f76598f62e4c008842bd9c77f87f
| 0.676265 | 3.431138 | false | false | false | false |
LarbiBekka34/miniproject-vhdl
|
Kogge_Stone_Adder/KSA_64.vhd
| 1 | 4,970 |
-------------------------------------------------------
--Copyright 2014 Larbi Bekka, Walid Belhadj, Oussama Hemchi
-------------------------------------------------------
-------------------------------------------------------
--This file is part of 64-bit Kogge-Stone adder.
--64-bit Kogge-Stone adder is free hardware design: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--64-bit Kogge-Stone adder is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with 64-bit Kogge-Stone adder. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------
-------------------------------------------------------
-- Project : Computer arithmetic, fast adders (3rd year mini project)
-- Author : Larbi Bekka, Walid Belhadj, Oussama Hemchi
-- Date : 10-05-2014
-- File : KSA_64.vhd
-- Design : 64-bit Kogge-Stone adder
------------------------------------------------------
-- Description : a 64-bit Kogge-Stone adder
-------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.KSA_pkg.all;
ENTITY KSA_64 IS
PORT(
x : IN std_logic_vector(63 downto 0);
y : IN std_logic_vector(63 downto 0);
c_in : IN std_logic;
sum : OUT std_logic_vector(63 downto 0);
c_out : OUT std_logic
);
END KSA_64;
ARCHITECTURE arch OF KSA_64 IS
--internal individual g,p signals--
SIGNAL g_in : std_logic_vector(63 downto 0);
SIGNAL p_in : std_logic_vector(63 downto 0);
--output g,p signals of each KS stage--
--stage 01
SIGNAL g_1 : std_logic_vector(63 downto 0);
SIGNAL p_1 : std_logic_vector(63 downto 0);
--stage 02
SIGNAL g_2 : std_logic_vector(63 downto 0);
SIGNAL p_2 : std_logic_vector(63 downto 0);
--stage 03
SIGNAL g_3 : std_logic_vector(63 downto 0);
SIGNAL p_3 : std_logic_vector(63 downto 0);
--stage 04
SIGNAL g_4 : std_logic_vector(63 downto 0);
SIGNAL p_4 : std_logic_vector(63 downto 0);
--stage 05
SIGNAL g_5 : std_logic_vector(63 downto 0);
SIGNAL p_5 : std_logic_vector(63 downto 0);
--stage 06
SIGNAL g_6 : std_logic_vector(63 downto 0);
SIGNAL p_6 : std_logic_vector(63 downto 0);
--internal carries--
SIGNAL c : std_logic_vector(63 downto 0);
--SIGNAL p_block : std_logic_vector(63 downto 0);
BEGIN
--generating stage00 g,p signals--
stg00:
FOR i IN 0 TO 63 GENERATE
pm: gp_gen PORT MAP (x => x(i) , y => y(i) , g => g_in(i) , p => p_in(i) );
END GENERATE;
--stage01 carry operations--
g_1(0) <= g_in(0);
p_1(0) <= p_in(0);
stg01:
FOR i IN 0 TO 62 GENERATE
pm: carry_op PORT MAP (g1 => g_in(i) , p1 => p_in(i) , g2 => g_in(i+1) , p2 => p_in(i+1) , go => g_1(i+1) , po => p_1(i+1) );
END GENERATE;
--stage02 carry operations--
buffa1:
FOR i IN 0 TO 1 GENERATE
g_2(i) <= g_1(i);
p_2(i) <= p_1(i);
END GENERATE;
stg02:
FOR i IN 0 TO 61 GENERATE
pm: carry_op PORT MAP (g1 => g_1(i) , p1 => p_1(i) , g2 => g_1(i+2) , p2 => p_1(i+2) , go => g_2(i+2) , po => p_2(i+2) );
END GENERATE;
--stage03 carry operations--
buffa2:
FOR i IN 0 TO 3 GENERATE
g_3(i) <= g_2(i);
p_3(i) <= p_2(i);
END GENERATE;
stg03:
FOR i IN 0 TO 59 GENERATE
pm: carry_op PORT MAP (g1 => g_2(i) , p1 => p_2(i) , g2 => g_2(i+4) , p2 => p_2(i+4) , go => g_3(i+4) , po => p_3(i+4) );
END GENERATE;
--stage04 carry operations--
buffa3:
FOR i IN 0 TO 7 GENERATE
g_4(i) <= g_3(i);
p_4(i) <= p_3(i);
END GENERATE;
stg04:
FOR i IN 0 TO 55 GENERATE
pm: carry_op PORT MAP (g1 => g_3(i) , p1 => p_3(i) , g2 => g_3(i+8) , p2 => p_3(i+8) , go => g_4(i+8) , po => p_4(i+8) );
END GENERATE;
--stage05 carry operations--
buffa4:
FOR i IN 0 TO 15 GENERATE
g_5(i) <= g_4(i);
p_5(i) <= p_4(i);
END GENERATE;
stg05:
FOR i IN 0 TO 47 GENERATE
pm: carry_op PORT MAP (g1 => g_4(i) , p1 => p_4(i) , g2 => g_4(i+16) , p2 => p_4(i+16) , go => g_5(i+16) , po => p_5(i+16) );
END GENERATE;
--stage06 carry operations--
buffa5:
FOR i IN 0 TO 31 GENERATE
g_6(i) <= g_5(i);
p_6(i) <= p_5(i);
END GENERATE;
stg06:
FOR i IN 0 TO 31 GENERATE
pm: carry_op PORT MAP (g1 => g_5(i) , p1 => p_5(i) , g2 => g_5(i+32) , p2 => p_5(i+32) , go => g_6(i+32) , po => p_6(i+32) );
END GENERATE;
c_gen:
FOR i IN 0 TO 63 GENERATE
c(i) <= g_6(i) OR (c_in AND p_6(i));
END GENERATE;
c_out <= c(63);
sum(0) <= c_in XOR p_in(0);
addin:
FOR i IN 1 TO 63 GENERATE
sum(i) <= c(i-1) XOR p_in(i);
END GENERATE;
END arch;
|
gpl-3.0
|
b3e0a46065fd00139b20ea11d1dcc3a6
| 0.548893 | 2.726275 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/PC.vhd
| 1 | 505 |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pc is
port(clk : in std_logic;
reset : in std_logic;
counterOutput : out std_logic_vector(31 downto 0);
counterInput : in std_logic_vector(31 downto 0) := x"00000000"
);
end pc;
architecture pc_arch of pc is
begin
process (clk,reset)
begin
if (reset = '1') then
counterOutput <= x"00000000";
elsif (clk'event and clk = '1') then
counterOutput <= counterInput;
end if;
end process;
end pc_arch;
|
gpl-3.0
|
0e9589a8b83ca330d588e7c9b00c74a3
| 0.675248 | 2.970588 | false | false | false | false |
kumasento/zedboard-thesis
|
examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_gpio_0_1/sim/system_axi_gpio_0_1.vhd
| 1 | 9,104 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY system_axi_gpio_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_axi_gpio_0_1;
ARCHITECTURE system_axi_gpio_0_1_arch OF system_axi_gpio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 32,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_1_arch;
|
apache-2.0
|
c929b16225ee53ca898773558c4c4db8
| 0.679482 | 3.231807 | false | false | false | false |
gustavowl/ProjetoOAC
|
ULA64bit/ula_tb.vhd
| 1 | 1,105 |
library ieee;
use ieee.std_logic_1164.all;
entity ula_tb is
end ula_tb;
architecture ula_tb of ula_tb is
signal ma, mb, ms: std_logic_vector(63 downto 0);
signal mw, mx, my, mz, mcout, mclk, mdo_op, mdone, mst: std_logic;
begin
vector: entity work.ula
port map (
a => ma,
b => mb,
s => ms,
x => mx,
y => my,
z => mz,
clk => mclk,
do_op => mdo_op,
done => mdone,
state => mst,
couterro => mcout
);
process
begin
ma <= "0011111111111110000000000000101000111111111111100000000000001010";
mb <= "0011111101010110101010010011101000111111111111100000000000000010";
mw <= '0';
mx <= '0';
my <= '0';
mz <= '0';
wait for 50 ns;
mx <= '0';
my <= '0';
mz <= '1';
wait for 50 ns;
mx <= '0';
my <= '1';
mz <= '0';
wait for 50 ns;
mx <= '0';
my <= '1';
mz <= '1';
wait for 50 ns;
mx <= '1';
my <= '0';
mz <= '0';
wait for 50 ns;
mx <= '1';
my <= '0';
mz <= '1';
wait for 50 ns;
mx <= '1';
my <= '1';
mz <= '0';
wait for 50 ns;
mx <= '1';
my <= '1';
mz <= '1';
wait for 50 ns;
wait;
end process;
end ula_tb;
|
gpl-2.0
|
18f8ef30509cf8e8f8099ca0c2be9077
| 0.527602 | 2.428571 | false | false | false | false |
GHackAnonymous/SimonGameVHDL
|
LFSR.srcs/sources_1/new/Main.vhd
| 1 | 17,325 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Main is
Port (
Led: out STD_LOGIC_VECTOR(3 downto 0);
Display: out STD_LOGIC_VECTOR(6 downto 0);
Botones: in STD_LOGIC_VECTOR(3 downto 0);
switch: in STD_LOGIC;
clock: in STD_LOGIC);
end Main;
architecture Behavioral of Main is
component LFSR is
Port ( clk : in std_logic ;
value32 : out std_logic_vector ( 31 downto 0 );
value16 : out std_logic_vector ( 15 downto 0 );
value8 : out std_logic_vector ( 7 downto 0 );
value4 : out std_logic_vector ( 3 downto 0 );
value2 : out std_logic_vector ( 1 downto 0 );
value2_2 : out std_logic_vector ( 1 downto 0 );
value2_3 : out std_logic_vector ( 1 downto 0 );
value2_4 : out std_logic_vector ( 1 downto 0 ));
end component ;
signal sig1, sig2, sig3, sig4: STD_LOGIC_VECTOR(1 downto 0);
signal sigvalue2, sigvalue2_2, sigvalue2_3, sigvalue2_4: STD_LOGIC_VECTOR (1 downto 0);
signal contador_comienzo: INTEGER:= 0;
signal contador_tiempo: INTEGER:= 0;
signal contador_tiempo2: INTEGER:= 0;
signal contador_tiempo3: INTEGER:= 0;
signal contador_tiempo4: INTEGER:= 0;
signal contador_tiempo5: INTEGER:= 0;
signal contador_tiempo6: INTEGER:= 0;
signal contador_tiempo7: INTEGER:= 0;
signal contador_tiempo8: INTEGER:= 0;
signal contador_tiempo9: INTEGER:= 0;
signal contador_tiempo10: INTEGER:= 0;
signal contador_tiempo11: INTEGER:= 0;
signal contador_tiempo12: INTEGER:= 0;
signal contador_tiempo13: INTEGER:= 0;
signal contador_tiempo14: INTEGER:= 0;
signal contador_tiempo15: INTEGER:= 0;
signal contador_tiempo16: INTEGER:= 0;
signal contador_tiempo17: INTEGER:= 0;
signal contador_tiempo18: INTEGER:= 0;
signal contador_tiempo19: INTEGER:= 0;
signal contador_tiempo20: INTEGER:= 0;
signal contador_espera: INTEGER:= 0;
signal contador_espera2: INTEGER:= 0;
signal contador_espera3: INTEGER:= 0;
signal contador_espera4: INTEGER:= 0;
signal contador_espera5: INTEGER:= 0;
signal contador_espera6: INTEGER:= 0;
signal contador_espera7: INTEGER:= 0;
signal contador_espera8: INTEGER:= 0;
signal contador_espera9: INTEGER:= 0;
signal contador_espera10: INTEGER:= 0;
signal contador_espera11: INTEGER:= 0;
signal contador_espera12: INTEGER:= 0;
CONSTANT MAX : INTEGER := 10000000;
CONSTANT TIEMPO : INTEGER := 10000;
signal arsig1 : STD_LOGIC_VECTOR (3 downto 0);
signal arsig2 : STD_LOGIC_VECTOR (3 downto 0);
signal arsig3 : STD_LOGIC_VECTOR (3 downto 0);
signal arsig4 : STD_LOGIC_VECTOR (3 downto 0);
TYPE STATE_TYPE IS(s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, perder, ganar);
SIGNAL STATE: STATE_TYPE;
type boolean is (false,true);
signal valores: boolean := false;
begin
U0: LFSR port map (clk => clock, value2 => sigvalue2, value2_2 => sigvalue2_2, value2_3 => sigvalue2_3, value2_4 => sigvalue2_4);
meter_valores: process(clock)
begin
if(switch = '1')then
if(valores = false)then
sig1 <= sigvalue2;
sig2 <= sigvalue2_2;
sig3 <= sigvalue2_3;
sig4 <= sigvalue2_4;
valores <= true;
end if;
end if;
end process;
simon: process (clock)
begin
if(contador_comienzo < MAX) then
contador_comienzo <= contador_comienzo + 1;
end if;
if(contador_comienzo >= MAX) then
case STATE is
-- primer turno FALTA PONER BIEN LOS CONTADORES CORRESPONDIENTES
when s0 => --Se enciende primer led
Led <= arsig1;
if(contador_tiempo >= TIEMPO)then
Led <= "0000";
STATE <= s1;
end if;
contador_tiempo <= contador_tiempo +1;
when s1 => --Interacción usuario primer led
if(contador_tiempo2 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig1)then
STATE <= s2; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig1)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo2 <= contador_tiempo2 + 1;
if(contador_tiempo2 > MAX) then
STATE <= perder;
end if;
end if;
-- segundo turno
when s2 => --Se enciende primer led
Led <= arsig1;
if(contador_tiempo3 >= TIEMPO)then
Led <= "0000";
STATE <= s3;
end if;
contador_tiempo3 <= contador_tiempo3 +1;
when s3 => --Se enciende el segundo led
if(contador_espera < TIEMPO)then
contador_espera <= contador_espera + 1;
STATE <= s3;
end if;
if (contador_espera >= TIEMPO) then
Led <= arsig2;
if(contador_tiempo4 >= TIEMPO)then
Led <= "0000";
STATE <= s4;
end if;
contador_tiempo4 <= contador_tiempo4 +1;
end if;
when s4 => --Interacción usuario primer led
if(contador_tiempo5 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig1)then
STATE <= s5; --Si acierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig1)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo5 <= contador_tiempo5 + 1;
if(contador_tiempo5 > MAX) then
STATE <= perder;
end if;
end if;
when s5 => --Interacción usuario segundo led
if(contador_espera2 < TIEMPO)then
contador_espera2 <= contador_espera2 + 1;
end if;
if(contador_espera2 >= TIEMPO)then
if(contador_tiempo6 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig2)then
STATE <= s6; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig2)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo6 <= contador_tiempo6 + 1;
if(contador_tiempo6 > MAX) then
STATE <= perder;
end if;
end if;
end if;
-- tercer turno FALTA POR PONER LOS CONTADORES CORRESPONDIENTES
when s6 => --Se enciende primer led
Led <= arsig1;
if(contador_tiempo7 >= TIEMPO)then
Led <= "0000";
STATE <= s7;
end if;
contador_tiempo7 <= contador_tiempo7 +1;
when s7 => --Se enciende el segundo led
if(contador_espera3 < TIEMPO)then
contador_espera3 <= contador_espera3 + 1;
STATE <= s7;
end if;
if (contador_espera3 >= TIEMPO) then
Led <= arsig2;
if(contador_tiempo8 >= TIEMPO)then
Led <= "0000";
STATE <= s8;
end if;
contador_tiempo8 <= contador_tiempo8 +1;
end if;
when s8 => --Se enciende el tercer led
if(contador_espera4 < TIEMPO)then
contador_espera4 <= contador_espera4 + 1;
STATE <= s8;
end if;
if (contador_espera4 >= TIEMPO) then
Led <= arsig3;
if(contador_tiempo9 >= TIEMPO)then
Led <= "0000";
STATE <= s9;
end if;
contador_tiempo9 <= contador_tiempo9 +1;
end if;
when s9 => --Interacción usuario primer led
if(contador_tiempo10 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig1)then
STATE <= s10; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig1)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo10 <= contador_tiempo10 + 1;
if(contador_tiempo10 > MAX) then
STATE <= perder;
end if;
end if;
when s10 => --Interacción usuario segundo led
if(contador_espera5 < TIEMPO)then
contador_espera5 <= contador_espera5 + 1;
end if;
if(contador_espera5 >= TIEMPO)then
if(contador_tiempo11 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig2)then
STATE <= s11; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig2)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo11 <= contador_tiempo11 + 1;
if(contador_tiempo11 > MAX) then
STATE <= perder;
end if;
end if;
end if;
when s11 => --Interacción usuario tercer led
if(contador_espera6 < TIEMPO)then
contador_espera6 <= contador_espera6 + 1;
end if;
if(contador_espera6 >= TIEMPO)then
if(contador_tiempo12 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig3)then
STATE <= s12; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig3)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo12 <= contador_tiempo12 + 1;
if(contador_tiempo12 > MAX) then
STATE <= perder;
end if;
end if;
end if;
-- Cuarto turno Funcional
when s12 => --Se enciende primer led
Led <= arsig1;
if(contador_tiempo13 >= TIEMPO)then
Led <= "0000";
contador_tiempo13 <= 0;
contador_espera7 <= 0;
STATE <= s13;
end if;
contador_tiempo13 <= contador_tiempo13 +1;
when s13 => --Se enciende el segundo led
if(contador_espera7 < TIEMPO)then
contador_espera7 <= contador_espera7 + 1;
STATE <= s13;
end if;
if (contador_espera7 >= TIEMPO) then
Led <= arsig2;
if(contador_tiempo14 >= TIEMPO)then
Led <= "0000";
STATE <= s14;
end if;
contador_tiempo14 <= contador_tiempo14 +1;
end if;
when s14 => --Se enciende el tercer led
if(contador_espera8 < TIEMPO)then
contador_espera8 <= contador_espera8 + 1;
STATE <= s14;
end if;
if (contador_espera8 >= TIEMPO) then
Led <= arsig3;
if(contador_tiempo15 >= TIEMPO)then
Led <= "0000";
STATE <= s15;
end if;
contador_tiempo15 <= contador_tiempo15 +1;
end if;
when s15 => --Se enciende el cuarto led
if(contador_espera9 < TIEMPO)then
contador_espera9 <= contador_espera9 + 1;
STATE <= s15;
end if;
if (contador_espera9 >= TIEMPO) then
Led <= arsig4;
if(contador_tiempo16 >= TIEMPO)then
Led <= "0000";
STATE <= s16;
end if;
contador_tiempo16 <= contador_tiempo16 +1;
end if;
when s16 => --Interacción usuario primer led
if(contador_tiempo17 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig1)then
STATE <= s17; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig1)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo17 <= contador_tiempo17 + 1;
if(contador_tiempo17 > MAX) then
STATE <= perder;
end if;
end if;
when s17 => --Interacción usuario segundo led
if(contador_espera10 < TIEMPO)then
contador_espera10 <= contador_espera10 + 1;
end if;
if(contador_espera10 >= TIEMPO)then
if(contador_tiempo18 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig2)then
STATE <= s18; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig2)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo18 <= contador_tiempo18 + 1;
if(contador_tiempo18 > MAX) then
STATE <= perder;
end if;
end if;
end if;
when s18 => --Interacción usuario tercer led
if(contador_espera11 < TIEMPO)then
contador_espera11 <= contador_espera11 + 1;
end if;
if(contador_espera11 >= TIEMPO)then
if(contador_tiempo19 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig3)then
STATE <= s19; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig3)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo19 <= contador_tiempo19 + 1;
if(contador_tiempo19 > MAX) then
STATE <= perder;
end if;
end if;
end if;
when s19 => --Interacción usuario cuarto led
if(contador_espera12 < TIEMPO)then
contador_espera12 <= contador_espera12 + 1;
end if;
if(contador_espera12 >= TIEMPO)then
if(contador_tiempo20 <= MAX)then --Si estamos dentro del tiempo de pulsar boton
if(Botones /= "0000")then
if(Botones = arsig4)then
STATE <= ganar; --Si hacierta el boton dentro del tiempo pasa
end if;
if(Botones /= arsig4)then
STATE <= perder; --Si falla el boton despues del tiempo pierde
end if;
end if;
contador_tiempo20 <= contador_tiempo20 + 1;
if(contador_tiempo20 > MAX) then
STATE <= perder;
end if;
end if;
end if;
when ganar => Display <= "1111110";
when perder => Display <= "0111111";
when others => STATE <= s12;
end case;
end if;
end process;
with sig1 select arsig1 <=
"1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when others;
with sig2 select arsig2 <=
"1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when others;
with sig3 select arsig3 <=
"1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when others;
with sig4 select arsig4 <=
"1000" when "00",
"0100" when "01",
"0010" when "10",
"0001" when others;
end Behavioral;
|
gpl-3.0
|
7b476801e46b6d14bad0fe0971224a5f
| 0.492814 | 4.445727 | false | false | false | false |
FearlessJojo/COPproject
|
project/RAM.vhd
| 1 | 2,599 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:59:33 11/03/2016
-- Design Name:
-- Module Name: RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM is
Port (
CLK : in STD_LOGIC;
ACCMEM : in STD_LOGIC;
MEM_WE : in STD_LOGIC;
addr : inout STD_LOGIC_VECTOR (15 downto 0);
data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram1Data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1OE : out STD_LOGIC;
Ram1WE : out STD_LOGIC;
Ram1EN : out STD_LOGIC;
wrn : out STD_LOGIC;
rdn : out STD_LOGIC);
end RAM;
architecture Behavioral of RAM is
signal state1 : integer range 0 to 3 := 0;
signal state2 : integer range 0 to 10 := 0;
begin
wrn <= '1';
rdn <= '1';
Ram1Addr(17 downto 16) <= "00";
process(CLK)
begin
if (MEM_WE = '0') and (ACCMEM = '1') then
if (CLK'EVENT) and (CLK = '1') then
case state1 is
when 0 =>
state1 <= 1;
Ram1EN <= '1';
when 1 =>
state1 <= 2;
Ram1EN <= '0';
Ram1OE <= '1';
Ram1WE <= '1';
when 2 =>
state1 <= 3;
RAM1Addr(15 downto 0) <= addr;
RAM1Data <= data;
Ram1WE <= '1';
when 3 =>
Ram1WE <= '0';
state1 <= 0;
when others =>
null;
end case;
end if;
end if;
end process;
process(CLK)
begin
if (MEM_WE = '1') and (ACCMEM = '0') then
if (CLK'EVENT) and (CLK = '1') then
case state2 is
when 0 =>
state2 <= 1;
Ram1EN <= '0';
Ram1OE <= '0';
Ram1WE <= '1';
when 1 =>
state2 <= 2;
RAM1Data <= "ZZZZZZZZZZZZZZZZ";
when 2 =>
state2 <= 3;
RAM1Addr(15 downto 0) <= addr;
when 3 =>
data <= Ram1Data;
state2 <= 0;
when others =>
null;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
053d5fd9d8bd85be750eab81ec85d9fe
| 0.528665 | 3.07574 | false | false | false | false |
FearlessJojo/COPproject
|
project/maintester.vhd
| 1 | 3,919 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:53:20 11/25/2016
-- Design Name:
-- Module Name: Z:/Documents/COP/COPproject/project/maintester.vhd
-- Project Name: project
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: main
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY maintester IS
END maintester;
ARCHITECTURE behavior OF maintester IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT main
PORT(
CLK0 : IN std_logic;
CLK1 : IN std_logic;
RAM1DATA : INOUT std_logic_vector(15 downto 0);
RAM2DATA : INOUT std_logic_vector(15 downto 0);
RAM1EN : OUT std_logic;
RAM1OE : OUT std_logic;
RAM1WE : OUT std_logic;
RAM2EN : OUT std_logic;
RAM2OE : OUT std_logic;
RAM2WE : OUT std_logic;
RAM1ADDR : OUT std_logic_vector(17 downto 0);
RAM2ADDR : OUT std_logic_vector(17 downto 0);
RESET : IN std_logic;
rdn : OUT std_logic;
wrn : OUT std_logic;
data_ready : IN std_logic;
tbre : IN std_logic;
tsre : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK0 : std_logic := '0';
signal CLK1 : std_logic := '0';
signal RESET : std_logic := '1';
signal data_ready : std_logic := '0';
signal tbre : std_logic := '0';
signal tsre : std_logic := '0';
--BiDirs
signal RAM1DATA : std_logic_vector(15 downto 0);
signal RAM2DATA : std_logic_vector(15 downto 0);
--Outputs
signal RAM1EN : std_logic;
signal RAM1OE : std_logic;
signal RAM1WE : std_logic;
signal RAM2EN : std_logic;
signal RAM2OE : std_logic;
signal RAM2WE : std_logic;
signal RAM1ADDR : std_logic_vector(17 downto 0);
signal RAM2ADDR : std_logic_vector(17 downto 0);
signal rdn : std_logic;
signal wrn : std_logic;
-- Clock period definitions
constant CLK0_period : time := 1 sec;
constant CLK1_period : time := 1 sec;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: main PORT MAP (
CLK0 => CLK0,
CLK1 => CLK1,
RAM1DATA => RAM1DATA,
RAM2DATA => RAM2DATA,
RAM1EN => RAM1EN,
RAM1OE => RAM1OE,
RAM1WE => RAM1WE,
RAM2EN => RAM2EN,
RAM2OE => RAM2OE,
RAM2WE => RAM2WE,
RAM1ADDR => RAM1ADDR,
RAM2ADDR => RAM2ADDR,
RESET => RESET,
rdn => rdn,
wrn => wrn,
data_ready => data_ready,
tbre => tbre,
tsre => tsre
);
-- Clock process definitions
CLK0_process :process
begin
CLK0 <= '0';
wait for CLK0_period/2;
CLK0 <= '1';
wait for CLK0_period/2;
end process;
CLK1 <= '1';
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK0_period*10;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
f7552eec3fb24f0282d7fc5cb0ebf125
| 0.551671 | 3.69717 | false | true | false | false |
kumasento/zedboard-thesis
|
examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/bd/system/ip/system_rst_processing_system7_0_100M_0/synth/system_rst_processing_system7_0_100M_0.vhd
| 1 | 6,811 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY system_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_processing_system7_0_100M_0;
ARCHITECTURE system_rst_processing_system7_0_100M_0_arch OF system_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "system_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "system_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_processing_system7_0_100M_0_arch;
|
apache-2.0
|
f50070ca2546c6024708b0bdb16d3da9
| 0.71825 | 3.466158 | false | false | false | false |
daniw/add
|
rot_enc/gpio.vhd
| 1 | 11,495 |
-------------------------------------------------------------------------------
-- Entity: gpio
-- Author: Waj
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- GPIO block for simple von-Neumann MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity gpio is
port(rst : in std_logic;
clk : in std_logic;
-- GPIO bus signals
bus_in : in t_bus2rws;
bus_out : out t_rws2bus;
-- GPIO pin signals
gpio_in : in std_logic_vector(DW-1 downto 0);
gpio_out : out std_logic_vector(DW-1 downto 0);
gpio_out_enb : out std_logic_vector(DW-1 downto 0);
-- Encoder pin signals
enc_a : in std_logic;
enc_b : in std_logic
);
end gpio;
architecture rtl of gpio is
-- address select signal
signal addr_sel : t_gpio_addr_sel;
-- peripheral registers - gpio
signal data_in_reg : std_logic_vector(DW-1 downto 0);
signal data_out_reg : std_logic_vector(DW-1 downto 0);
signal out_enb_reg : std_logic_vector(DW-1 downto 0);
-- gpio input synchronisation
signal sync_gpio_in : std_logic_vector(DW-1 downto 0);
-- peripheral registers - encoder
signal enc_capture : std_logic;
signal enc_capt_reg : std_logic;
signal enc_capt_prev: std_logic;
signal enc_buf_dist : std_logic_vector(DW-1 downto 0);
signal enc_buf_pos : std_logic_vector(DW-1 downto 0);
signal enc_buf_neg : std_logic_vector(DW-1 downto 0);
-- encoder counter registers
signal enc_cnt_dist : std_logic_vector(DW-1 downto 0);
signal enc_cnt_pos : std_logic_vector(DW-1 downto 0);
signal enc_cnt_neg : std_logic_vector(DW-1 downto 0);
-- encoder count enable
signal enc_cnt_enb_pos : std_logic;
signal enc_cnt_enb_neg : std_logic;
-- encoder fsm
type t_enc_state is (st_active, st_idle_pos, st_idle_neg);
signal c_st : t_enc_state;
signal n_st : t_enc_state;
begin
-- output ssignment
gpio_out <= data_out_reg;
gpio_out_enb <= out_enb_reg;
-----------------------------------------------------------------------------
-- Input register
-----------------------------------------------------------------------------
P_in: process(clk)
begin
if rst = '1' then
sync_gpio_in <= (others=>'0');
elsif rising_edge(clk) then
sync_gpio_in <= gpio_in;
data_in_reg <= sync_gpio_in;
end if;
end process;
-----------------------------------------------------------------------------
-- Encoder fsm
-----------------------------------------------------------------------------
-- Memorizing process
p_enc_fsm_seq: process(rst, clk)
begin
if rst = '1' then
c_st <= st_active;
elsif rising_edge(clk) then
c_st <= n_st;
end if;
end process;
-- Combinatoric process
p_enc_fsm_comb: process(enc_a, enc_b, c_st)
begin
-- default assignments
n_st <= c_st;
enc_cnt_enb_pos <= '0';
enc_cnt_enb_neg <= '0';
-- states
case c_st is
when st_active =>
if enc_a = '0' and enc_b = '0' then
n_st <= st_idle_pos;
end if;
when st_idle_pos =>
if enc_a = '1' and enc_b = '0' then
n_st <= st_idle_neg;
elsif enc_a = '1' and enc_b = '1' then
enc_cnt_enb_pos <= '1';
n_st <= st_active;
end if;
when st_idle_neg =>
if enc_a = '0' and enc_b = '1' then
n_st <= st_idle_pos;
elsif enc_a = '1' and enc_b = '1' then
enc_cnt_enb_neg <= '1';
n_st <= st_active;
end if;
when others =>
n_st <= st_active;
end case;
end process;
-----------------------------------------------------------------------------
-- Encoder counter
-----------------------------------------------------------------------------
p_enc_cnt: process(rst, clk)
begin
if rst = '1' then
-- clear counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- clear buffer registers
enc_buf_dist <= (others => '0');
enc_buf_pos <= (others => '0');
enc_buf_neg <= (others => '0');
elsif rising_edge(clk) then
if enc_capture = '1' then
-- capture occured -> copy counter to buffer and reset counter
if enc_cnt_enb_pos = '0' and enc_cnt_enb_neg = '0' then -- no count
-- counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- buffer registers
enc_buf_dist <= enc_cnt_dist;
enc_buf_pos <= enc_cnt_pos;
enc_buf_neg <= enc_cnt_neg;
elsif enc_cnt_enb_pos = '0' and enc_cnt_enb_neg = '1' then -- neg count
-- counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- buffer registers
enc_buf_dist <= std_logic_vector(unsigned(enc_cnt_dist) - 1);
enc_buf_pos <= enc_cnt_pos;
enc_buf_neg <= std_logic_vector(unsigned(enc_cnt_neg) + 1);
elsif enc_cnt_enb_pos = '1' and enc_cnt_enb_neg = '0' then -- pos count
-- counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- buffer registers
enc_buf_dist <= std_logic_vector(unsigned(enc_cnt_dist) + 1);
enc_buf_pos <= std_logic_vector(unsigned(enc_cnt_pos) + 1);
enc_buf_neg <= enc_cnt_neg;
else -- pos and neg count (currently impossible)
-- counter registers
enc_cnt_dist <= (others => '0');
enc_cnt_pos <= (others => '0');
enc_cnt_neg <= (others => '0');
-- buffer registers
enc_buf_dist <= enc_cnt_dist;
enc_buf_pos <= std_logic_vector(unsigned(enc_cnt_pos) + 1);
enc_buf_neg <= std_logic_vector(unsigned(enc_cnt_neg) + 1);
end if;
else -- no capture occured
if enc_cnt_enb_pos = '0' and enc_cnt_enb_neg = '0' then -- no count
-- counter registers
enc_cnt_dist <= enc_cnt_dist;
enc_cnt_pos <= enc_cnt_pos;
enc_cnt_neg <= enc_cnt_neg;
-- buffer registers
enc_buf_dist <= enc_buf_dist;
enc_buf_pos <= enc_buf_pos;
enc_buf_neg <= enc_buf_neg;
elsif enc_cnt_enb_pos = '0' and enc_cnt_enb_neg = '1' then -- neg count
-- counter registers
enc_cnt_dist <= std_logic_vector(unsigned(enc_cnt_dist) - 1);
enc_cnt_pos <= enc_cnt_pos;
enc_cnt_neg <= std_logic_vector(unsigned(enc_cnt_neg) + 1);
-- buffer registers
enc_buf_dist <= enc_buf_dist;
enc_buf_pos <= enc_buf_pos;
enc_buf_neg <= enc_buf_neg;
elsif enc_cnt_enb_pos = '1' and enc_cnt_enb_neg = '0' then -- pos count
-- counter registers
enc_cnt_dist <= std_logic_vector(unsigned(enc_cnt_dist) + 1);
enc_cnt_pos <= std_logic_vector(unsigned(enc_cnt_pos) + 1);
enc_cnt_neg <= enc_cnt_neg;
-- buffer registers
enc_buf_dist <= enc_buf_dist;
enc_buf_pos <= enc_buf_pos;
enc_buf_neg <= enc_buf_neg;
else -- pos and neg count (with current state machine impossible)
-- counter registers
enc_cnt_dist <= enc_cnt_dist;
enc_cnt_pos <= std_logic_vector(unsigned(enc_cnt_pos) + 1);
enc_cnt_neg <= std_logic_vector(unsigned(enc_cnt_neg) + 1);
-- buffer registers
enc_buf_dist <= enc_buf_dist;
enc_buf_pos <= enc_buf_pos;
enc_buf_neg <= enc_buf_neg;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Encoder - Capture signal
-----------------------------------------------------------------------------
p_enc_capture: process(clk, rst)
begin
if rst = '1' then
enc_capture <= '0';
enc_capt_prev <= '0';
else
if rising_edge(clk) then
if enc_capt_prev = '0' and enc_capt_reg = '1' then
-- rising edge on capture
enc_capture <= '1';
else
enc_capture <= '0';
end if;
enc_capt_prev <= enc_capt_reg;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Address Decoding (combinationally)
-----------------------------------------------------------------------------
process(bus_in.addr)
begin
case bus_in.addr is
-- Port 1 addresses -----------------------------------------------------
when c_addr_gpio_data_in => addr_sel <= gpio_data_in;
when c_addr_gpio_data_out => addr_sel <= gpio_data_out;
when c_addr_gpio_out_enb => addr_sel <= gpio_enb;
-- Encoder adresses -----------------------------------------------------
when c_addr_enc_ctrl => addr_sel <= enc_ctrl;
when c_addr_enc_dist => addr_sel <= enc_dist;
when c_addr_enc_pos => addr_sel <= enc_pos;
when c_addr_enc_neg => addr_sel <= enc_neg;
-- unused addresses -----------------------------------------------------
when others => addr_sel <= none;
end case;
end process;
-----------------------------------------------------------------------------
-- Read Access (R and R/W registers)
-----------------------------------------------------------------------------
P_read: process(clk)
begin
if rising_edge(clk) then
-- default assignment
bus_out.data <= (others => '0');
-- use address select signal
case addr_sel is
when gpio_data_in => bus_out.data <= data_in_reg;
when gpio_data_out => bus_out.data <= data_out_reg;
when gpio_enb => bus_out.data <= out_enb_reg;
when enc_ctrl => bus_out.data <= "101010100101010" & enc_capture;
when enc_dist => bus_out.data <= enc_buf_dist;
when enc_pos => bus_out.data <= enc_buf_pos;
when enc_neg => bus_out.data <= enc_buf_neg;
when others => null;
end case;
end if;
end process;
-----------------------------------------------------------------------------
-- Write Access (R/W registers only)
-----------------------------------------------------------------------------
P_write: process(clk, rst)
begin
if rst = '1' then
data_out_reg <= (others => '0');
out_enb_reg <= (others => '0'); -- output disabled per default
enc_capt_reg <= '0';
elsif rising_edge(clk) then
if bus_in.wr_enb = '1' then
-- use address select signal
case addr_sel is
when gpio_data_out => data_out_reg <= bus_in.data;
when gpio_enb => out_enb_reg <= bus_in.data;
when enc_ctrl => enc_capt_reg <= bus_in.data(0);
when others => null;
end case;
else
enc_capt_reg <= '0';
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
ec5507665b1321b19c3c54f7b7617738
| 0.463506 | 3.679577 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/WindowsManager.vhd
| 1 | 1,810 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity WindowsManager is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
CWP : in STD_LOGIC;
nRs1 : out STD_LOGIC_VECTOR (5 downto 0);
nRs2 : out STD_LOGIC_VECTOR (5 downto 0);
nRd : out STD_LOGIC_VECTOR (5 downto 0);
nCWP : out STD_LOGIC);
end WindowsManager;
architecture Behavioral of WindowsManager is
begin
process(rs1,rs2,rd,op,op3,CWP)
begin
if(CWP='0') then
nRs1<='0'&rs1;
nRs2<='0'&rs2;
nRd<='0'&rd;
else
------------------rs1------------------
if(rs1>=24 and rs1<=31) then
nRs1<=rs1-"010000";
elsif((rs1>=16 and rs1<=23) or (rs1>=8 and rs1<=15)) then
nRs1<=rs1+"010000";
else
nRs1<='0'&rs1;
end if;
-----------------rs2----------------------
if(rs2>=24 and rs2<=31) then
nRs2<=rs2-"010000";
elsif((rs2>=16 and rs2<=23) or (rs2>=8 and rs2<=15)) then
nRs2<=rs2+"010000";
else
nRs2<='0'&rs2;
end if;
-----------------rd-------------------------
if(rd>=24 and rd<=31) then
nRd<=rd-"010000";
elsif((rd>=16 and rd<=23)or(rd>=8 and rd<=15)) then
nRd<=rd+"010000";
else
nRd<='0'&rd;
end if;
end if;
if((op="10") and (op3="111100" or op3="111101")) then --SAVE or Restore
nCWP<=not(CWP);
if (CWP='1') then
nRd<='0'&rd;
else
if(rd>=24 and rd<=31) then
nRd<=rd-"010000";
elsif((rd>=16 and rd<=23) or (rd>=8 and rd<=15)) then
nRd<=rd+"010000";
else
nRd<='0'&rd;
end if;
end if;
else
nCWP<=CWP;
end if;
end process;
end Behavioral;
|
mit
|
0cdef075221e9fd5617d3da6d8fe9354
| 0.529834 | 2.746586 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/RCR8Bit.vhd
| 1 | 1,411 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 03:58:32 PM
-- Design Name:
-- Module Name: RCR8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RCR8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end RCR8Bit;
architecture Behavioral of RCR8Bit is
begin
Cout <= Input(0);
Output(0) <= Input(1);
Output(1) <= Input(2);
Output(2) <= Input(3);
Output(3) <= Input(4);
Output(4) <= Input(5);
Output(5) <= Input(6);
Output(6) <= Input(7);
Output(7) <= Cin;
end Behavioral;
|
mit
|
5f22a2234cdafe35aa94f3611571a5f7
| 0.537208 | 3.813514 | false | false | false | false |
jeffmagina/ECE368
|
Project1/OPERAND_ACCESS/OP_ACCESS_tbd.vhd
| 1 | 4,232 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:44:10 03/31/2015
-- Design Name:
-- Module Name: C:/Users/Jeff Magina/Documents/GitHub/ECE368/Project1/OPERAND_ACCESS/OP_ACCESS_tbd.vhd
-- Project Name: OP_ACCESS
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: op_access
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY OP_ACCESS_tbd IS
END OP_ACCESS_tbd;
ARCHITECTURE behavior OF OP_ACCESS_tbd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT op_access
PORT(
CLK : IN std_logic;
OPCODE_IN : IN std_logic_vector(3 downto 0);
REG_A : IN std_logic_vector(3 downto 0);
IMMEDIATE : IN std_logic_vector(7 downto 0);
W_ADDR : IN std_logic_vector(3 downto 0);
OP2_MUX_SEL : IN STD_LOGIC;
BANK_R_W : IN std_logic;
BANK_ENB : IN std_logic;
BANK_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
DATA_IN : IN std_logic_vector(15 downto 0);
OPCODE_OUT : OUT std_logic_vector(3 downto 0);
OP1_OUT : OUT std_logic_vector(15 downto 0);
OP2_OUT : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal OPCODE_IN : std_logic_vector(3 downto 0) := (others => '0');
signal REG_A : std_logic_vector(3 downto 0) := (others => '0');
signal IMMEDIATE : std_logic_vector(7 downto 0) := (others => '0');
signal W_ADDR : std_logic_vector(3 downto 0) := (others => '0');
signal OP2_MUX_SEL : std_logic := '0';
signal BANK_R_W : std_logic := '0';
signal BANK_ENB : std_logic := '0';
signal BANK_DATA : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal DATA_IN : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal OPCODE_OUT : std_logic_vector(3 downto 0);
signal OP1_OUT : std_logic_vector(15 downto 0);
signal OP2_OUT : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: op_access PORT MAP (
CLK => CLK,
OPCODE_IN => OPCODE_IN,
REG_A => REG_A,
IMMEDIATE => IMMEDIATE,
W_ADDR => W_ADDR,
OP2_MUX_SEL => OP2_MUX_SEL,
BANK_R_W => BANK_R_W,
BANK_ENB => BANK_ENB,
BANK_DATA => BANK_DATA,
DATA_IN => DATA_IN,
OPCODE_OUT => OPCODE_OUT,
OP1_OUT => OP1_OUT,
OP2_OUT => OP2_OUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
tb: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
BANK_ENB <= '1';
W_ADDR <= x"0";
BANK_R_W <= '1';
BANK_DATA <= x"1111";
wait for CLK_period;
W_ADDR <= x"1";
BANK_R_W <= '1';
BANK_DATA <= x"1234";
wait for CLK_period;
W_ADDR <= x"2";
BANK_R_W <= '1';
BANK_DATA <= x"5678";
wait for CLK_period;
W_ADDR <= x"3";
BANK_R_W <= '1';
BANK_DATA <= x"8888";
wait for CLK_period;
OPCODE_IN <= "0011";
REG_A <= "0001";
IMMEDIATE <= "00100000";
OP2_MUX_SEL <= '0';
BANK_R_W <= '0';
wait for CLK_period;
OPCODE_IN <= "1001";
REG_A <= "0011";
IMMEDIATE <= "00011111";
OP2_MUX_SEL <= '1';
BANK_R_W <= '0';
wait;
end process;
END;
|
mit
|
562f00d2773fe6defa8726280774f7d2
| 0.567108 | 3.293385 | false | false | false | false |
daniw/add
|
floppy/mcu/bus.vhd
| 2 | 4,921 |
-------------------------------------------------------------------------------
-- Entity: ram
-- Author: Waj
-- Date : 12-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Data/address/control bus for simple von-Neumann MCU.
-- The bus master (CPU) can read/write in every cycle. The bus slaves are
-- assumed to have registerd read data output with an address-in to data-out
-- latency of 1 cc. The read data muxing from bus slaves to the bus master is
-- done combinationally. Thus, at the bus master interface, there results a
-- read data latency of 1 cc.
-------------------------------------------------------------------------------
-- Note on code portability:
-------------------------------------------------------------------------------
-- The address decoding logic as implemented in process P_dec below, shows how
-- to write portable code by means of a user-defined enumaration type which is
-- used as the index range for a constant array, see mcu_pkg. This allows to
-- leave the local code (in process P_dec) unchanged when the number and/or
-- base addresses of the bus slaves in the system change. Such changes then
-- need only to be made in the global definition package.
-- To generate such portable code for the rest of the functionality (e.g. for
-- the read data mux) would require to organize all data input vectors in a
-- signal array first. This would destroy the portability of the code, since it
-- requires manual code adaption when design parameter change.
-------------------------------------------------------------------------------
-- Total # of FFs: 2
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity buss is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
cpu_in : in t_cpu2bus;
cpu_out : out t_bus2cpu;
-- ROM bus signals
rom_in : in t_ros2bus;
rom_out : out t_bus2ros;
-- RAM bus signals
ram_in : in t_rws2bus;
ram_out : out t_bus2rws;
-- GPIO bus signals
gpio_in : in t_rws2bus;
gpio_out : out t_bus2rws;
-- LCD bus signals
lcd_in : in t_rws2bus;
lcd_out : out t_bus2rws
);
end buss;
architecture rtl of buss is
-- currently addressed bus slave
signal bus_slave, bus_slave_reg : t_bus_slave;
begin
-----------------------------------------------------------------------------
-- address decoding
-----------------------------------------------------------------------------
-- convey lower address bist from CPU to all bus slaves
rom_out.addr <= cpu_in.addr(AWL-1 downto 0);
ram_out.addr <= cpu_in.addr(AWL-1 downto 0);
gpio_out.addr <= cpu_in.addr(AWL-1 downto 0);
lcd_out.addr <= cpu_in.addr(AWL-1 downto 0);
-- combinational process:
-- determine addressed slave by decoding higher address bits
-----------------------------------------------------------------------------
P_dec: process(cpu_in)
begin
bus_slave <= ROM; -- default assignment
for k in t_bus_slave loop
if cpu_in.addr(AW-1 downto AW-AWH) = HBA(k) then
bus_slave <= k;
end if;
end loop;
end process;
-----------------------------------------------------------------------------
-- write transfer logic
-----------------------------------------------------------------------------
-- convey write data from CPU to all bus slaves
-- rom is read-only slave
ram_out.data <= cpu_in.data;
gpio_out.data <= cpu_in.data;
lcd_out.data <= cpu_in.data;
-- convey write enable from CPU to addressed slave only, others set to "read"
ram_out.we <= not cpu_in.r_wb when bus_slave = RAM else '0';
gpio_out.we <= not cpu_in.r_wb when bus_slave = GPIO else '0';
lcd_out.we <= not cpu_in.r_wb when bus_slave = LCD else '0';
-----------------------------------------------------------------------------
-- read transfer logic
-----------------------------------------------------------------------------
-- read data mux
with bus_slave_reg select cpu_out.data <= rom_in.data when ROM,
ram_in.data when RAM,
gpio_in.data when GPIO,
lcd_in.data when LCD,
(others => '-') when others;
-- sequential process:
-- register decode information to compensate read-latency of slaves
-----------------------------------------------------------------------------
P_reg: process(rst, clk)
begin
if rst = '1' then
bus_slave_reg <= ROM;
elsif rising_edge(clk) then
bus_slave_reg <= bus_slave;
end if;
end process;
end rtl;
|
gpl-2.0
|
8715ab29c2ca360815bf86561dfea84b
| 0.48608 | 4.485871 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALU/load_store_unit.vhd
| 1 | 1,317 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Load/Store Unit
-- Operations - Load/Store to a register
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Load_Store_Unit is
Port ( CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (7 downto 0);
IMMED : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Load_Store_Unit;
architecture Behavioral of Load_Store_Unit is
signal reg : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal w_en : std_logic := '0';-- '1' = write, '0' = read
begin
w_en <= '1' when OP="1010" else '0';
process(CLK)
begin
if (CLK'event and CLK='1') then
if (w_en = '1') then
reg <= A;
end if;
end if;
end process;
RESULT <= reg;
end Behavioral;
|
mit
|
9cec1e8769827357052cf574b649078e
| 0.551253 | 3.658333 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 2/MODULOPRINCIPAL.vhd
| 1 | 5,947 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MODULOPRINCIPAL is
Port ( rst : in STD_LOGIC;
CLK : in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end MODULOPRINCIPAL;
architecture Behavioral of MODULOPRINCIPAL is
COMPONENT PC
PORT(
rst : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
DataOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT Sumador32bits
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT InstructionMemory
PORT(
Address : IN std_logic_vector(5 downto 0);
rst : IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT OMUXT
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm : IN std_logic_vector(31 downto 0);
i : IN std_logic;
oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
imm13 : IN std_logic_vector(12 downto 0);
SEUimm : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT CU
PORT(
OP : IN std_logic_vector(1 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
COMPONENT PSRModifier
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Oper1 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
NZVC : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT PSR
PORT(
NZVC : IN std_logic_vector(3 downto 0);
nCWP: IN std_logic;
CLK: IN std_logic;
rst: IN std_logic;
CWP: OUT std_logic;
C : OUT std_logic
);
END COMPONENT;
COMPONENT WindowsManager
PORT(
rs1 : IN std_logic_vector(4 downto 0);
rs2 : IN std_logic_vector(4 downto 0);
rd : IN std_logic_vector(4 downto 0);
op : IN std_logic_vector(1 downto 0);
op3 : IN std_logic_vector(5 downto 0);
CWP : IN std_logic;
nRs1 : OUT std_logic_vector(5 downto 0);
nRs2 : OUT std_logic_vector(5 downto 0);
nRd : OUT std_logic_vector(5 downto 0);
nCWP : OUT std_logic
);
END COMPONENT;
signal B0:std_logic_vector(31 downto 0);--Result: conecta al sumador con el DataIn de nPC
signal B1:std_logic_vector(31 downto 0);--DataOut(nPC): conecta al nPC con el DataIn de PC
signal B2:std_logic_vector(31 downto 0);--DataOut(PC): conecta al PC con el address del IM
signal B3:std_logic_vector(31 downto 0);--OutWindowsManager: conecta al IM con el CU((31-30),(24-19)),WindowManager((18-14),(4-0),(29-25)),
--SEU(12-0) y OMUXT(13)
signal B4:std_logic_vector(5 downto 0); --ALUOP: conecta a CU y a la ALU
signal B5:std_logic_vector(31 downto 0);--ALURESULT: conecta a la ALU con el rd del RF, es la salida del Modulo Principal
signal B6:std_logic_vector(31 downto 0);--Crs1: conecta al RF con Oper1 de la ALU
signal B7:std_logic_vector(31 downto 0);--Crs2: conecta al RF con OMUXT
signal B8:std_logic_vector(31 downto 0);--SEUimm: conecta a SEU con OMUXT
signal B9:std_logic_vector(31 downto 0);--Oper2: conecta a OMUXT con el Oper2 de la ALU
signal B10: std_logic; --Carry: conecta al PSR y a la ALU
signal B11: std_logic_vector(3 downto 0);--NZVC: conecta al PSRModifier con el PSR
signal B12: std_logic_vector(17 downto 0);--Instruction: conecta al IM con el Windows Manager
signal B13: std_logic;--CWP: conecta al PSR con el WindowsManager
signal B14: std_logic;--nCWP_ conecta al WindowsManager con el PSR
begin
Inst_PC: PC PORT MAP(
rst => rst,
dataIn => B1,
CLK => CLK,
DataOut => B2
);
Inst_Sumador32bits: Sumador32bits PORT MAP(
Oper1 => "00000000000000000000000000000001",
Oper2 => B2,
Result => B0
);
Inst_nPC: PC PORT MAP(
rst => rst,
CLK => CLK,
DataIn => B0,
DataOut => B1
);
Inst_InstructionMemory: InstructionMemory PORT MAP(
Address => B2(5 downto 0),
rst => rst,
Instruction =>B3
);
Inst_OMUXT: OMUXT PORT MAP(
Crs2 => B7,
SEUimm => B8,
i => B3(13),
oper2 => B9
);
Inst_RF: RF PORT MAP(
rs1 => B12(17 downto 12),
rs2 => B12(11 downto 6),
rd => B12(5 downto 0),
DWR => B5,
rst => rst,
Crs1 => B6,
Crs2 => B7
);
Inst_SEU: SEU PORT MAP(
imm13 => B3(12 downto 0),
SEUimm => B8
);
Inst_ALU: ALU PORT MAP(
Oper1 => B6,
Oper2 => B9,
ALUOP => B4,
C => B10,
ALURESULT => B5
);
Inst_CU: CU PORT MAP(
OP => B3(31 downto 30),
OP3 =>B3(24 downto 19) ,
ALUOP => B4
);
Inst_PSRModifier: PSRModifier PORT MAP(
ALUOP => B4,
Oper2 => B9,
Oper1 => B6,
ALURESULT => B5,
NZVC => B11
);
Inst_PSR: PSR PORT MAP(
NZVC => B11,
nCWP=> B14,
CLK=> CLK,
rst=> rst,
CWP=> B13,
C => B10
);
Inst_WindowsManager: WindowsManager PORT MAP(
rs1 => B3(18 downto 14),
rs2 => B3(4 downto 0),
rd => B3(29 downto 25),
op => B3(31 downto 30),
op3 =>B3(24 downto 19) ,
CWP => B13,
nRs1 => B12(17 downto 12),
nRs2 => B12(11 downto 6),
nRd => B12(5 downto 0),
nCWP => B14
);
ALURESULT<=B5;
end Behavioral;
|
mit
|
c38fa87358df168c25b4e6cbe66b8281
| 0.619472 | 2.954297 | false | false | false | false |
eaglewyng/FPGA2048
|
Box.vhd
| 1 | 2,514 |
----------------------------------------------------------------------------------
-- Engineer: Parker Ridd and Travis Chambers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Box is
generic(
XPOS : in NATURAL;
YPOS : in NATURAL
);
port(
pixel_x : in STD_LOGIC_VECTOR(9 downto 0);
pixel_y : in STD_LOGIC_VECTOR(9 downto 0);
posXPixOut : out UNSIGNED(9 downto 0);
posYPixOut : out UNSIGNED(9 downto 0);
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox : out STD_LOGIC := '0'
);
end Box;
architecture game_arch of Box is
--============================================================================
------------------Signal Declarations-----------------------------------------
--============================================================================
signal pixel_ux, pixel_uy : UNSIGNED(9 downto 0);
signal posXPix, posYPix, posYPixInverted : UNSIGNED(9 downto 0);
--============================================================================
------------------Constant Declarations---------------------------------------
--============================================================================
constant DIMENSIONS : UNSIGNED(9 downto 0) := TO_UNSIGNED(90, 10);
constant MAX_X : UNSIGNED(9 downto 0) := XPOS + DIMENSIONS - 1;
constant MAX_Y : UNSIGNED(9 downto 0) := YPOS + DIMENSIONS - 1;
begin
posXPixOut <= posXPix;
posYPixOut <= posYPix;
--============================================================================
------------------Display Logic-----------------------------------------------
--============================================================================
drawBox <= '1' when pixel_ux >= XPOS and pixel_ux <= MAX_X and pixel_uy >= YPOS and pixel_uy <= MAX_Y else
'0';
--============================================================================
------------------Other Signal Assignments------------------------------------
--============================================================================
pixel_ux <= UNSIGNED(pixel_x);
pixel_uy <= UNSIGNED(pixel_y);
posXPix <= pixel_ux - XPOS;
posYPixInverted <= pixel_uy - YPOS;
posYPix <= 90 - posYPixInverted;
end game_arch;
|
mit
|
89f87b6045f8c2ba318504b0b697f73e
| 0.409706 | 5.068548 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_0/synth/system_microblaze_0_0.vhd
| 1 | 66,735 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:10.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v10_0_1;
USE microblaze_v10_0_1.MicroBlaze;
ENTITY system_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END system_microblaze_0_0;
ARCHITECTURE system_microblaze_0_0_arch OF system_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_LOCKSTEP_MASTER : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTR_SIZE : INTEGER;
C_IADDR_SIZE : INTEGER;
C_DADDR_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_NON_SECURE : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_ASYNC_WAKEUP : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR;
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR;
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR;
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR;
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
RAM_Static : IN STD_LOGIC_VECTOR(1023 DOWNTO 0);
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Hibernate : OUT STD_LOGIC;
Suspend : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Dbg_Continue : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
Pause : IN STD_LOGIC;
Pause_Ack : OUT STD_LOGIC;
Non_Secure : IN STD_LOGIC_VECTOR(0 TO 3);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Dbg_AWADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_AWVALID : IN STD_LOGIC;
Dbg_AWREADY : OUT STD_LOGIC;
Dbg_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_WVALID : IN STD_LOGIC;
Dbg_WREADY : OUT STD_LOGIC;
Dbg_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_BVALID : OUT STD_LOGIC;
Dbg_BREADY : IN STD_LOGIC;
Dbg_ARADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 2);
Dbg_ARVALID : IN STD_LOGIC;
Dbg_ARREADY : OUT STD_LOGIC;
Dbg_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
Dbg_RVALID : OUT STD_LOGIC;
Dbg_RREADY : IN STD_LOGIC;
DEBUG_ACLK : IN STD_LOGIC;
DEBUG_ARESETN : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_microblaze_0_0_arch: ARCHITECTURE IS "MicroBlaze,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_microblaze_0_0_arch : ARCHITECTURE IS "system_microblaze_0_0,MicroBlaze,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_microblaze_0_0_arch: ARCHITECTURE IS "system_microblaze_0_0,MicroBlaze,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze,x_ipVersion=10.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_SCO=0,C_FREQ=100000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_LOCKSTEP_MASTER=0,C_ENDIANNESS=1,C_FAMILY=artix7,C_DATA_SIZE=32,C_INSTR_SIZE=32,C_IADDR_SIZE=32,C_DADD" &
"R_SIZE=32,C_INSTANCE=system_microblaze_0_0,C_AVOID_PRIMITIVES=0,C_AREA_OPTIMIZED=0,C_OPTIMIZATION=0,C_INTERCONNECT=2,C_BASE_VECTORS=0x0000000000000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_M_AXI_D_BUS_EXCEPTION=0,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=0,C_D_LMB=1,C_D_AXI=1,C_I_LMB=1,C_I_AXI=0,C_USE_MSR_INSTR=0,C_USE_PCMP_INSTR=0,C_USE_BARREL=0,C_USE_DIV=0,C_USE" &
"_HW_MUL=0,C_USE_FPU=0,C_USE_REORDER_INSTR=1,C_UNALIGNED_EXCEPTIONS=0,C_ILL_OPCODE_EXCEPTION=0,C_DIV_ZERO_EXCEPTION=0,C_FPU_EXCEPTION=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=0,C_FSL_EXCEPTION=0,C_USE_STACK_PROTECTION=0,C_IMPRECISE_EXCEPTIONS=0,C_USE_INTERRUPT=2,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_USE_NON_SECURE=0,C_USE_MMU=0,C_MMU_DTLB_SIZE=4,C_MMU_ITLB_SIZE=2,C_MMU_TLB_ACCESS=3,C_MMU_ZONES=16,C_MMU_PRIVILEGED_INSTR=0,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=32,C_PVR=" &
"0,C_PVR_USER1=0x00,C_PVR_USER2=0x00000000,C_DYNAMIC_BUS_SIZING=0,C_RESET_MSR=0x00000000,C_OPCODE_0x0_ILLEGAL=0,C_DEBUG_ENABLED=1,C_DEBUG_INTERFACE=0,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=5,C_DEBUG_LATENCY_COUNTERS=1,C_DEBUG_COUNTER_WIDTH=32,C_DEBUG_TRACE_SIZE=8192,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_ASYNC_WAKEUP=3,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C" &
"_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WID" &
"TH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x0000000080000000,C_ICACHE_HIGHADDR=0x000000008FFFFFFF,C_USE_ICACHE=1,C_ALLOW_ICACHE_WR=1,C_ADDR_TAG_BITS=14,C_CACHE_BYTE_SIZE=16384,C_ICACHE_LINE_LEN=4,C_ICACHE_ALWAYS_USED=1,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE" &
"_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x0000000080000000,C_DCACHE_HIGHADDR=0x000000008fffffff,C_USE_DCACHE=1,C_ALLOW_DCACHE_WR=1,C_DCACHE_ADDR_TAG=14,C_DCACHE_BYTE_SIZE=16384,C_DCACHE_LINE_LEN=4,C_DCACHE_ALWAYS_USED=1,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORC" &
"E_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Disable: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG DISABLE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_LOCKSTEP_MASTER => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTR_SIZE => 32,
C_IADDR_SIZE => 32,
C_DADDR_SIZE => 32,
C_INSTANCE => "system_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"0000000000000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_NON_SECURE => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_DEBUG_INTERFACE => 0,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_ASYNC_WAKEUP => 3,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"0000000080000000",
C_ICACHE_HIGHADDR => X"000000008FFFFFFF",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 14,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"0000000080000000",
C_DCACHE_HIGHADDR => X"000000008fffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 14,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
RAM_Static => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1024)),
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Pause => '0',
Non_Secure => X"0",
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
Dbg_Disable => Dbg_Disable,
Dbg_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
Dbg_AWVALID => '0',
Dbg_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
Dbg_WVALID => '0',
Dbg_BREADY => '0',
Dbg_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
Dbg_ARVALID => '0',
Dbg_RREADY => '0',
DEBUG_ACLK => '0',
DEBUG_ARESETN => '0',
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END system_microblaze_0_0_arch;
|
apache-2.0
|
733235af57927928eb68ed41d285d4a7
| 0.642197 | 2.860725 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/CU_tb.vhd
| 1 | 4,171 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CU_tb IS
END CU_tb;
ARCHITECTURE behavior OF CU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CU
PORT(
OP : IN std_logic_vector(1 downto 0);
OP2 : IN std_logic_vector(2 downto 0);
Cond : IN std_logic_vector(3 downto 0);
icc : IN std_logic_vector(3 downto 0);
OP3 : IN std_logic_vector(5 downto 0);
WE : OUT std_logic;
RFDEST : OUT std_logic;
RFSOURCE : OUT std_logic_vector(1 downto 0);
WRENMEM : OUT std_logic;
PCSOURCE : OUT std_logic_vector(1 downto 0);
ALUOP : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal OP : std_logic_vector(1 downto 0) := (others => '0');
signal OP2 : std_logic_vector(2 downto 0) := (others => '0');
signal Cond : std_logic_vector(3 downto 0) := (others => '0');
signal icc : std_logic_vector(3 downto 0) := (others => '0');
signal OP3 : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal WE : std_logic;
signal RFDEST : std_logic;
signal RFSOURCE : std_logic_vector(1 downto 0);
signal WRENMEM : std_logic;
signal PCSOURCE : std_logic_vector(1 downto 0);
signal ALUOP : std_logic_vector(5 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CU PORT MAP (
OP => OP,
OP2 => OP2,
Cond => Cond,
icc => icc,
OP3 => OP3,
WE => WE,
RFDEST => RFDEST,
RFSOURCE => RFSOURCE,
WRENMEM => WRENMEM,
PCSOURCE => PCSOURCE,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
---------------Instrucciones Aritmetico Logicas---------------
OP<="10";
OP2<="000"; --No interesa este valor en este tipo de instrucciones de formato 3
Cond<="0000";--No interesa este valor en este tipo de instrucciones de formato 3
OP3<="000001";--0. AND
wait for 20 ns;
OP3<="000101";--1. ANDN
wait for 20 ns;
OP3<="000010";--2. OR
wait for 20 ns;
OP3<="000110";--3. ORN
wait for 20 ns;
OP3<="000011";--4. XOR
wait for 20 ns;
OP3<="000111";--5. XNOR
wait for 20 ns;
OP3<="000000";--6. ADD
wait for 20 ns;
OP3<="000100";--7. SUB
wait for 20 ns;
OP3<="100101";--8. SLL
wait for 20 ns;
OP3<="100110";--9. SRL
wait for 20 ns;
OP3<="100111";--10.SRA
wait for 20 ns;
OP3<="010001";--11. ANDcc
wait for 20 ns;
OP3<="010101";--12. ANDNcc
wait for 20 ns;
OP3<="010010";--13. ORcc
wait for 20 ns;
OP3<="010110";--14. ORNcc
wait for 20 ns;
OP3<="010011";--15. XORcc
wait for 20 ns;
OP3<="010111";--16. XNORcc
wait for 20 ns;
OP3<="010000";--17. ADDcc
wait for 20 ns;
OP3<="001000";--18. ADDX
wait for 20 ns;
OP3<="011000";--19. ADDXcc
wait for 20 ns;
OP3<="010100";--20. SUBcc
wait for 20 ns;
OP3<="001100";--21. SUBX
wait for 20 ns;
OP3<="011100";--22. SUBXcc
wait for 20 ns;
OP3<="111100";--23. SAVE
wait for 20 ns;
OP3<="111101";--24. RESTORE
wait for 20 ns;
OP3<="111000";--25-JUMP AND LINK
wait for 20 ns;
--Escribir y leer en Memoria
OP<="11";
OP3<="000100";--Store Word
wait for 20 ns;
OP3<="000000";--Load Word
wait;
--Branch
OP<="00";
OP3<="000000";--En instrucciones de formato 2 no se utiliza OP3
OP2<="010";
Cond<="1000";
wait for 20 ns;
Cond<="0000";
wait for 20 ns;
Cond<="1001";
wait for 20 ns;
Cond<="0001";
wait for 20 ns;
Cond<="1010";
wait for 20 ns;
Cond<="0010";
wait for 20 ns;
Cond<="1011";
wait for 20 ns;
Cond<="0011";
wait for 20 ns;
Cond<="1100";
wait for 20 ns;
Cond<="0100";
wait for 20 ns;
Cond<="1101";
wait for 20 ns;
Cond<="0101";
wait for 20 ns;
Cond<="1110";
wait for 20 ns;
Cond<="0110";
wait for 20 ns;
Cond<="1111";
wait for 20 ns;
Cond<="0111";
wait for 20 ns;
-------CALL AND LINK-----
OP<="01";
wait;
end process;
END;
|
mit
|
a6daa889a4473e6fc8f8f918d0bfa990
| 0.54855 | 3.196169 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/CounterTest/clk2Hz.vhd
| 1 | 1,419 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK2Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Clock Divider
-- Lower the Clock frequency from
-- 50 Mhz to 2 hz
-- 50Mhz = 50,000,000/25,000,000 = 2 Hz
-- 2Hz ~= 1 second
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk2Hz is
Port ( CLK_IN : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk2Hz;
architecture Behavioral of clk2Hz is
signal clkdv: STD_LOGIC:='0';
signal counter : integer range 0 to 25000000 := 0;
begin
frequency_divider: process (RST, CLK_IN) begin
if (RST = '1') then
clkdv <= '0';
counter <= 0;
elsif rising_edge(CLK_IN) then
if (counter = 25000000) then
if(clkdv='0') then
clkdv <= '1';
else
clkdv <= '0';
end if;
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
CLK_OUT <= clkdv;
end Behavioral;
|
mit
|
c7e3227f34345341db4cd0a9793dc08a
| 0.498238 | 4.16129 | false | false | false | false |
kaott/16-bit-risc
|
vhdl/dat_mem.vhd
| 4 | 866 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.lib.all;
entity dat_mem is
port (DIN, ADD : in std_logic_vector(15 downto 0);
WE, RE, CLK : in std_logic;
DOUT : out std_logic_vector(15 downto 0)
);
end dat_mem;
architecture Logic of dat_mem is
type memT is array (512 downto 0) of std_logic_vector(15 downto 0);
signal mem : memT := (256 => x"0100", 258 => x"0102", others => x"0000");
signal read_address : std_logic_vector(15 downto 0);
begin
process(CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
mem(to_integer(unsigned(ADD))) <= DIN;
end if;
read_address <= ADD;
end if;
end process;
process(RE)
begin
if RE = '1' then
DOUT <= mem(to_integer(unsigned(read_address)));
else
DOUT <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
end Logic;
|
mit
|
fb411d7f3e07cad134c185afb01e51bc
| 0.624711 | 2.848684 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/alu_logic_unit.vhd
| 3 | 1,513 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
x"00" when "100", -- CMP REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
mit
|
efe68ea7907f35350701d5b87f60369b
| 0.543291 | 3.681265 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/VGA Part 1/clk40MHz.vhd
| 1 | 2,162 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Pixel Clock
-- Output a 40Mhz clock for a vga controller
-- 100 Mhz to 40 Mhz
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity CLK_40MHZ is
port(CLK_IN: in std_logic;
CLK_OUT: inout std_logic);
end CLK_40MHZ;
architecture Behavioral of CLK_40MHZ is
component CLKDLL
generic (CLKDV_DIVIDE : real := 2.5;--2.0; -- (1.5, 2.0, 2.5,
-- 3.0, 4.0, 5.0, 8.0, 16.0)
DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE)
port(CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
attribute CLKDV_DIVIDE : real;
attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
signal CLK_D: std_logic;
begin
CLKDLL_inst : CLKDLL
port map (
CLK0 => open, -- 0 degree DLL CLK ouptput
CLK180 => open, -- 180 degree DLL CLK output
CLK270 => open, -- 270 degree DLL CLK output
CLK2X => CLK_D, -- 2X DLL CLK output
CLK90 => open, -- 90 degree DLL CLK output
CLKDV => CLK_OUT, -- Divided DLL CLK out (CLKDV_DIVIDE)
LOCKED => open, -- DLL LOCK status output
CLKFB => CLK_D, -- DLL clock feedback
CLKIN => CLK_IN, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
end Behavioral;
|
mit
|
c4432709ef77eae74ed6a6d6c04783de
| 0.574468 | 3.695726 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALUwithInput/ALUwithINPUT_toplevel.vhd
| 1 | 2,719 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: ALUwithINPUT
-- Project Name: ALUwithINPUT
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU for Lab 1 Part 5
-- eight switches control whats input
-- gets stored in register A when button 4
-- is clicked and stored in register B when
-- button 3 is clicked. Button 2
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity ALUwithINPUT is
Port ( CLK : in STD_LOGIC;
SW : in STD_LOGIC_VECTOR (7 downto 0);
BTN : in STD_LOGIC_VECTOR (3 downto 0);
SEG : out STD_LOGIC_VECTOR (6 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0));
end ALUwithINPUT;
architecture Structural of ALUwithINPUT is
signal cen : STD_LOGIC := '0';
signal enl : STD_LOGIC := '1';
signal dpc, BC_OUTPUT : STD_LOGIC_VECTOR (3 downto 0) := "1111";
signal TO_SEG, F1_OUT, F2_OUT, F3_OUT : STD_LOGIC_VECTOR (7 downto 0);
begin
----- Structural Components: -----
--Button Debounce Controller
BUTTON_CONTROLLER: entity work.buttoncontrol
port map( CLK => CLK,
BTN => BTN,
OUTPUT => BC_OUTPUT);
-- Create three flipflops
-- Send data from switches after button click
FlipFlop1: entity work.flip_flop
port map( CLK => BC_OUTPUT(3),
D_IN => SW(7 downto 0),
D_OUT => F1_OUT);
FlipFlop2: entity work.flip_flop
port map( CLK => BC_OUTPUT(2),
D_IN => SW(7 downto 0),
D_OUT => F2_OUT);
FlipFlop3: entity work.flip_flop
port map( CLK => BC_OUTPUT(1),
D_IN => SW(7 downto 0),
D_OUT => F3_OUT);
--Map ALU values using Flip flop values
--and LED display
ALU: entity work.ALU
port map( CLK => CLK,
RA => F1_OUT,
RB => F2_OUT,
OPCODE => F3_OUT(3 downto 0),
ALU_OUT => TO_SEG,
CCR => LED(3 downto 0));
-- Control Seven Segment display
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => '0',
EN => enl,
SEG_0 => "0000",
SEG_1 => "0000",
SEG_2 => TO_SEG(7 downto 4),
SEG_3 => TO_SEG(3 downto 0),
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
----- End Structural Components -----
end Structural;
|
mit
|
ecdf4a6c50c47dac0e4b1572d420ee09
| 0.548363 | 3.390274 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xbar_0/system_xbar_0_sim_netlist.vhdl
| 1 | 513,445 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:43:39 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xbar_0/system_xbar_0_sim_netlist.vhdl
-- Design : system_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : out STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
\gen_axi.s_axi_rid_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_single_thread.active_target_hot_reg[0]\ : out STD_LOGIC;
\s_axi_arready[0]\ : out STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]\ : out STD_LOGIC;
\gen_single_thread.active_target_hot_reg[0]_0\ : out STD_LOGIC;
\s_axi_arready[1]\ : out STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
sel_4 : out STD_LOGIC;
sel_4_0 : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[1]_0\ : out STD_LOGIC;
aclk : in STD_LOGIC;
mi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_11_in : in STD_LOGIC;
p_16_in : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
active_target_hot_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_2 : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_axi.read_cnt_reg[5]\ : in STD_LOGIC;
\gen_single_thread.active_target_hot_reg[0]_1\ : in STD_LOGIC;
st_mr_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[130]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]_1\ : in STD_LOGIC;
\gen_single_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]_0\ : in STD_LOGIC;
\gen_single_thread.accept_cnt_reg[0]_0\ : in STD_LOGIC;
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter : entity is "axi_crossbar_v2_1_12_addr_arbiter";
end system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter is
signal \^q\ : STD_LOGIC_VECTOR ( 57 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \gen_arbiter.any_grant_i_1__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.any_grant_reg_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_3_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[1]_i_4_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.grant_hot_reg_n_0_[1]\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_arbiter.m_grant_enc_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.s_ready_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.s_axi_rid_i_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal grant_hot : STD_LOGIC;
signal m_mesg_mux : STD_LOGIC_VECTOR ( 62 downto 1 );
signal m_target_hot_mux : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal qual_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arready[0]\ : STD_LOGIC;
signal \^s_axi_arready[1]\ : STD_LOGIC;
signal \^sel_4\ : STD_LOGIC;
signal \^sel_4_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[1]_i_2\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \gen_arbiter.m_grant_enc_i[0]_i_7\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[10]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[11]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[12]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[13]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[14]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[15]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[16]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[17]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[18]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[19]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[20]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[21]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[22]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[23]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[24]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[27]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[28]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[29]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[30]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[31]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[32]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[33]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[34]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[35]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[36]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[37]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[38]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[39]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[40]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[41]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[42]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[43]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[44]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[46]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[47]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[48]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[53]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[54]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[55]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[56]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[57]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[58]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[59]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[60]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[61]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[62]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[8]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gen_arbiter.m_mesg_i[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gen_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_arbiter.s_ready_i[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[8]_i_2\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair3";
begin
Q(57 downto 0) <= \^q\(57 downto 0);
SR(0) <= \^sr\(0);
aa_mi_arvalid <= \^aa_mi_arvalid\;
\gen_axi.s_axi_rid_i_reg[0]_0\(0) <= \^gen_axi.s_axi_rid_i_reg[0]_0\(0);
\s_axi_arready[0]\ <= \^s_axi_arready[0]\;
\s_axi_arready[1]\ <= \^s_axi_arready[1]\;
sel_4 <= \^sel_4\;
sel_4_0 <= \^sel_4_0\;
\gen_arbiter.any_grant_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DDDDDCCC"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \gen_arbiter.any_grant_reg_n_0\,
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\,
I3 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\,
I4 => \gen_arbiter.grant_hot[1]_i_3_n_0\,
I5 => \gen_arbiter.grant_hot[1]_i_4_n_0\,
O => \gen_arbiter.any_grant_i_1__0_n_0\
);
\gen_arbiter.any_grant_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.any_grant_i_1__0_n_0\,
Q => \gen_arbiter.any_grant_reg_n_0\,
R => '0'
);
\gen_arbiter.grant_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BBBA8A8A"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\,
I1 => \gen_arbiter.grant_hot[1]_i_2_n_0\,
I2 => \gen_arbiter.grant_hot[0]_i_2_n_0\,
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]_1\,
I4 => \gen_arbiter.last_rr_hot[0]_i_1__0_n_0\,
I5 => \gen_arbiter.grant_hot[1]_i_4_n_0\,
O => \gen_arbiter.grant_hot[0]_i_1_n_0\
);
\gen_arbiter.grant_hot[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800888"
)
port map (
I0 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\,
I1 => \gen_single_thread.accept_cnt_reg[0]\,
I2 => \^sel_4\,
I3 => m_valid_i_reg,
I4 => \gen_master_slots[1].r_issuing_cnt_reg[8]_0\,
O => \gen_arbiter.grant_hot[0]_i_2_n_0\
);
\gen_arbiter.grant_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BB88BAAA"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[1]\,
I1 => \gen_arbiter.grant_hot[1]_i_2_n_0\,
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\,
I3 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\,
I4 => \gen_arbiter.grant_hot[1]_i_3_n_0\,
I5 => \gen_arbiter.grant_hot[1]_i_4_n_0\,
O => \gen_arbiter.grant_hot[1]_i_1_n_0\
);
\gen_arbiter.grant_hot[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \gen_arbiter.any_grant_reg_n_0\,
O => \gen_arbiter.grant_hot[1]_i_2_n_0\
);
\gen_arbiter.grant_hot[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800888"
)
port map (
I0 => \gen_arbiter.last_rr_hot[0]_i_1__0_n_0\,
I1 => \gen_single_thread.accept_cnt_reg[0]_0\,
I2 => \^sel_4_0\,
I3 => m_valid_i_reg,
I4 => \gen_master_slots[1].r_issuing_cnt_reg[8]_0\,
O => \gen_arbiter.grant_hot[1]_i_3_n_0\
);
\gen_arbiter.grant_hot[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0808080FFFFFFFF"
)
port map (
I0 => m_axi_arready(0),
I1 => aa_mi_artarget_hot(0),
I2 => \^aa_mi_arvalid\,
I3 => \^gen_axi.s_axi_rid_i_reg[0]_0\(0),
I4 => mi_arready(0),
I5 => aresetn_d,
O => \gen_arbiter.grant_hot[1]_i_4_n_0\
);
\gen_arbiter.grant_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.grant_hot[0]_i_1_n_0\,
Q => \gen_arbiter.grant_hot_reg_n_0_[0]\,
R => '0'
);
\gen_arbiter.grant_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.grant_hot[1]_i_1_n_0\,
Q => \gen_arbiter.grant_hot_reg_n_0_[1]\,
R => '0'
);
\gen_arbiter.last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080800000800"
)
port map (
I0 => s_axi_arvalid(0),
I1 => qual_reg(0),
I2 => \^s_axi_arready[0]\,
I3 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
I4 => \gen_arbiter.last_rr_hot[0]_i_2_n_0\,
I5 => p_2_in,
O => \gen_arbiter.last_rr_hot[0]_i_1__0_n_0\
);
\gen_arbiter.last_rr_hot[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^s_axi_arready[1]\,
I1 => qual_reg(1),
I2 => s_axi_arvalid(1),
O => \gen_arbiter.last_rr_hot[0]_i_2_n_0\
);
\gen_arbiter.last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \gen_arbiter.last_rr_hot[0]_i_1__0_n_0\,
Q => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\gen_arbiter.last_rr_hot_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => grant_hot,
D => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\,
Q => p_2_in,
S => \^sr\(0)
);
\gen_arbiter.m_grant_enc_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000F888"
)
port map (
I0 => \gen_arbiter.last_rr_hot[0]_i_1__0_n_0\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]_1\,
I2 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\,
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\,
I4 => \gen_arbiter.any_grant_reg_n_0\,
I5 => \^aa_mi_arvalid\,
O => grant_hot
);
\gen_arbiter.m_grant_enc_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800080808000800"
)
port map (
I0 => s_axi_arvalid(1),
I1 => qual_reg(1),
I2 => \^s_axi_arready[1]\,
I3 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
I4 => \gen_arbiter.m_grant_enc_i[0]_i_5_n_0\,
I5 => p_2_in,
O => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\
);
\gen_arbiter.m_grant_enc_i[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^s_axi_arready[0]\,
I1 => qual_reg(0),
I2 => s_axi_arvalid(0),
O => \gen_arbiter.m_grant_enc_i[0]_i_5_n_0\
);
\gen_arbiter.m_grant_enc_i[0]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(0),
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(1),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(2),
O => \gen_arbiter.qual_reg_reg[1]_0\
);
\gen_arbiter.m_grant_enc_i[0]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => s_axi_araddr(60),
I1 => s_axi_araddr(63),
I2 => s_axi_araddr(61),
I3 => s_axi_araddr(62),
O => \^sel_4\
);
\gen_arbiter.m_grant_enc_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\,
Q => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => p_1_in
);
\gen_arbiter.m_mesg_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(41),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(9),
O => m_mesg_mux(10)
);
\gen_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(42),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(10),
O => m_mesg_mux(11)
);
\gen_arbiter.m_mesg_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(43),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(11),
O => m_mesg_mux(12)
);
\gen_arbiter.m_mesg_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(44),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(12),
O => m_mesg_mux(13)
);
\gen_arbiter.m_mesg_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(45),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(13),
O => m_mesg_mux(14)
);
\gen_arbiter.m_mesg_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(46),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(14),
O => m_mesg_mux(15)
);
\gen_arbiter.m_mesg_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(47),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(15),
O => m_mesg_mux(16)
);
\gen_arbiter.m_mesg_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(48),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(16),
O => m_mesg_mux(17)
);
\gen_arbiter.m_mesg_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(49),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(17),
O => m_mesg_mux(18)
);
\gen_arbiter.m_mesg_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(50),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(18),
O => m_mesg_mux(19)
);
\gen_arbiter.m_mesg_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(32),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(0),
O => m_mesg_mux(1)
);
\gen_arbiter.m_mesg_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(51),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(19),
O => m_mesg_mux(20)
);
\gen_arbiter.m_mesg_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(52),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(20),
O => m_mesg_mux(21)
);
\gen_arbiter.m_mesg_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(53),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(21),
O => m_mesg_mux(22)
);
\gen_arbiter.m_mesg_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(54),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(22),
O => m_mesg_mux(23)
);
\gen_arbiter.m_mesg_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(55),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(23),
O => m_mesg_mux(24)
);
\gen_arbiter.m_mesg_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(56),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(24),
O => m_mesg_mux(25)
);
\gen_arbiter.m_mesg_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(57),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(25),
O => m_mesg_mux(26)
);
\gen_arbiter.m_mesg_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(58),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(26),
O => m_mesg_mux(27)
);
\gen_arbiter.m_mesg_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(59),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(27),
O => m_mesg_mux(28)
);
\gen_arbiter.m_mesg_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(60),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(28),
O => m_mesg_mux(29)
);
\gen_arbiter.m_mesg_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(33),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(1),
O => m_mesg_mux(2)
);
\gen_arbiter.m_mesg_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(61),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(29),
O => m_mesg_mux(30)
);
\gen_arbiter.m_mesg_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(62),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(30),
O => m_mesg_mux(31)
);
\gen_arbiter.m_mesg_i[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_arbiter.m_mesg_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(63),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(31),
O => m_mesg_mux(32)
);
\gen_arbiter.m_mesg_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(8),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(0),
O => m_mesg_mux(33)
);
\gen_arbiter.m_mesg_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(9),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(1),
O => m_mesg_mux(34)
);
\gen_arbiter.m_mesg_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(10),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(2),
O => m_mesg_mux(35)
);
\gen_arbiter.m_mesg_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(11),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(3),
O => m_mesg_mux(36)
);
\gen_arbiter.m_mesg_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(12),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(4),
O => m_mesg_mux(37)
);
\gen_arbiter.m_mesg_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(13),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(5),
O => m_mesg_mux(38)
);
\gen_arbiter.m_mesg_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(14),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(6),
O => m_mesg_mux(39)
);
\gen_arbiter.m_mesg_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(34),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(2),
O => m_mesg_mux(3)
);
\gen_arbiter.m_mesg_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(15),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlen(7),
O => m_mesg_mux(40)
);
\gen_arbiter.m_mesg_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(3),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arsize(0),
O => m_mesg_mux(41)
);
\gen_arbiter.m_mesg_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(4),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arsize(1),
O => m_mesg_mux(42)
);
\gen_arbiter.m_mesg_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(5),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arsize(2),
O => m_mesg_mux(43)
);
\gen_arbiter.m_mesg_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlock(1),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arlock(0),
O => m_mesg_mux(44)
);
\gen_arbiter.m_mesg_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(3),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arprot(0),
O => m_mesg_mux(46)
);
\gen_arbiter.m_mesg_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(4),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arprot(1),
O => m_mesg_mux(47)
);
\gen_arbiter.m_mesg_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(5),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arprot(2),
O => m_mesg_mux(48)
);
\gen_arbiter.m_mesg_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(35),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(3),
O => m_mesg_mux(4)
);
\gen_arbiter.m_mesg_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(2),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arburst(0),
O => m_mesg_mux(53)
);
\gen_arbiter.m_mesg_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(3),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arburst(1),
O => m_mesg_mux(54)
);
\gen_arbiter.m_mesg_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arcache(4),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arcache(0),
O => m_mesg_mux(55)
);
\gen_arbiter.m_mesg_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arcache(5),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arcache(1),
O => m_mesg_mux(56)
);
\gen_arbiter.m_mesg_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arcache(6),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arcache(2),
O => m_mesg_mux(57)
);
\gen_arbiter.m_mesg_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arcache(7),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arcache(3),
O => m_mesg_mux(58)
);
\gen_arbiter.m_mesg_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arqos(4),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arqos(0),
O => m_mesg_mux(59)
);
\gen_arbiter.m_mesg_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(36),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(4),
O => m_mesg_mux(5)
);
\gen_arbiter.m_mesg_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arqos(5),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arqos(1),
O => m_mesg_mux(60)
);
\gen_arbiter.m_mesg_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arqos(6),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arqos(2),
O => m_mesg_mux(61)
);
\gen_arbiter.m_mesg_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arqos(7),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_arqos(3),
O => m_mesg_mux(62)
);
\gen_arbiter.m_mesg_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(37),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(5),
O => m_mesg_mux(6)
);
\gen_arbiter.m_mesg_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(38),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(6),
O => m_mesg_mux(7)
);
\gen_arbiter.m_mesg_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(39),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(7),
O => m_mesg_mux(8)
);
\gen_arbiter.m_mesg_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(40),
I1 => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
I2 => s_axi_araddr(8),
O => m_mesg_mux(9)
);
\gen_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \gen_arbiter.m_grant_enc_i_reg_n_0_[0]\,
Q => \^q\(0),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(10),
Q => \^q\(10),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(11),
Q => \^q\(11),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(12),
Q => \^q\(12),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(13),
Q => \^q\(13),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(14),
Q => \^q\(14),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(15),
Q => \^q\(15),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(16),
Q => \^q\(16),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(17),
Q => \^q\(17),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(18),
Q => \^q\(18),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(19),
Q => \^q\(19),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(1),
Q => \^q\(1),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(20),
Q => \^q\(20),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(21),
Q => \^q\(21),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(22),
Q => \^q\(22),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(23),
Q => \^q\(23),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(24),
Q => \^q\(24),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(25),
Q => \^q\(25),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(26),
Q => \^q\(26),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(27),
Q => \^q\(27),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(28),
Q => \^q\(28),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(29),
Q => \^q\(29),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(2),
Q => \^q\(2),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(30),
Q => \^q\(30),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(31),
Q => \^q\(31),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(32),
Q => \^q\(32),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(33),
Q => \^q\(33),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(34),
Q => \^q\(34),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(35),
Q => \^q\(35),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(36),
Q => \^q\(36),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(37),
Q => \^q\(37),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(38),
Q => \^q\(38),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(39),
Q => \^q\(39),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(3),
Q => \^q\(3),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(40),
Q => \^q\(40),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(41),
Q => \^q\(41),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(42),
Q => \^q\(42),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(43),
Q => \^q\(43),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(44),
Q => \^q\(44),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(46),
Q => \^q\(45),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(47),
Q => \^q\(46),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(48),
Q => \^q\(47),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(4),
Q => \^q\(4),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(53),
Q => \^q\(48),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(54),
Q => \^q\(49),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(55),
Q => \^q\(50),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(56),
Q => \^q\(51),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(57),
Q => \^q\(52),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(58),
Q => \^q\(53),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(59),
Q => \^q\(54),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(5),
Q => \^q\(5),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(60),
Q => \^q\(55),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(61),
Q => \^q\(56),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(62),
Q => \^q\(57),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(6),
Q => \^q\(6),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(7),
Q => \^q\(7),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(8),
Q => \^q\(8),
R => \^sr\(0)
);
\gen_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => m_mesg_mux(9),
Q => \^q\(9),
R => \^sr\(0)
);
\gen_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => s_axi_araddr(60),
I1 => s_axi_araddr(63),
I2 => s_axi_araddr(61),
I3 => s_axi_araddr(62),
I4 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\,
I5 => \^sel_4_0\,
O => m_target_hot_mux(0)
);
\gen_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDDDD1DDDD"
)
port map (
I0 => \^sel_4_0\,
I1 => \gen_arbiter.m_grant_enc_i[0]_i_2_n_0\,
I2 => s_axi_araddr(62),
I3 => s_axi_araddr(61),
I4 => s_axi_araddr(63),
I5 => s_axi_araddr(60),
O => m_target_hot_mux(1)
);
\gen_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_araddr(31),
I2 => s_axi_araddr(29),
I3 => s_axi_araddr(30),
O => \^sel_4_0\
);
\gen_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => m_target_hot_mux(0),
Q => aa_mi_artarget_hot(0),
R => \^sr\(0)
);
\gen_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => m_target_hot_mux(1),
Q => \^gen_axi.s_axi_rid_i_reg[0]_0\(0),
R => \^sr\(0)
);
\gen_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0777FFFF07770000"
)
port map (
I0 => m_axi_arready(0),
I1 => aa_mi_artarget_hot(0),
I2 => \^gen_axi.s_axi_rid_i_reg[0]_0\(0),
I3 => mi_arready(0),
I4 => \^aa_mi_arvalid\,
I5 => \gen_arbiter.any_grant_reg_n_0\,
O => \gen_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_mi_arvalid\,
R => \^sr\(0)
);
\gen_arbiter.qual_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_master_slots[0].r_issuing_cnt_reg[3]_2\(0),
Q => qual_reg(0),
R => \^sr\(0)
);
\gen_arbiter.qual_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_master_slots[0].r_issuing_cnt_reg[3]_2\(1),
Q => qual_reg(1),
R => \^sr\(0)
);
\gen_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\,
I1 => \gen_arbiter.any_grant_reg_n_0\,
I2 => \^aa_mi_arvalid\,
I3 => aresetn_d,
O => \gen_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_arbiter.s_ready_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[1]\,
I1 => \gen_arbiter.any_grant_reg_n_0\,
I2 => \^aa_mi_arvalid\,
I3 => aresetn_d,
O => \gen_arbiter.s_ready_i[1]_i_1_n_0\
);
\gen_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i[0]_i_1_n_0\,
Q => \^s_axi_arready[0]\,
R => '0'
);
\gen_arbiter.s_ready_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i[1]_i_1_n_0\,
Q => \^s_axi_arready[1]\,
R => '0'
);
\gen_axi.s_axi_rid_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^q\(0),
I1 => mi_arready(0),
I2 => \^gen_axi.s_axi_rid_i_reg[0]_0\(0),
I3 => \^aa_mi_arvalid\,
I4 => p_11_in,
I5 => p_16_in,
O => \gen_axi.s_axi_rid_i_reg[0]\
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55550003"
)
port map (
I0 => \gen_axi.read_cnt_reg[5]\,
I1 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
I2 => \^q\(34),
I3 => \^q\(33),
I4 => p_11_in,
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^q\(36),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(35),
I4 => \^q\(38),
I5 => \^q\(37),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(0),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(1),
O => D(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(0),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(1),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(2),
O => D(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(3),
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(2),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(1),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]_0\(0),
I4 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
O => D(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => aa_mi_artarget_hot(0),
I2 => \^aa_mi_arvalid\,
O => \gen_master_slots[0].r_issuing_cnt_reg[0]\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080808080808080"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => aa_mi_artarget_hot(0),
I2 => m_axi_arready(0),
I3 => \gen_single_thread.active_target_hot_reg[0]_1\,
I4 => st_mr_rvalid(0),
I5 => \m_payload_i_reg[130]\(0),
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^aa_mi_arvalid\,
I1 => \^gen_axi.s_axi_rid_i_reg[0]_0\(0),
I2 => mi_arready(0),
O => \gen_master_slots[1].r_issuing_cnt_reg[8]\
);
\gen_single_thread.active_target_enc[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFFFFEF0000"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_araddr(29),
I2 => s_axi_araddr(31),
I3 => s_axi_araddr(28),
I4 => \^s_axi_arready[0]\,
I5 => active_target_enc,
O => \gen_single_thread.active_target_enc_reg[0]\
);
\gen_single_thread.active_target_enc[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFFFFEF0000"
)
port map (
I0 => s_axi_araddr(62),
I1 => s_axi_araddr(61),
I2 => s_axi_araddr(63),
I3 => s_axi_araddr(60),
I4 => \^s_axi_arready[1]\,
I5 => active_target_enc_2,
O => \gen_single_thread.active_target_enc_reg[0]_0\
);
\gen_single_thread.active_target_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_araddr(31),
I2 => s_axi_araddr(29),
I3 => s_axi_araddr(30),
I4 => \^s_axi_arready[0]\,
I5 => active_target_hot(0),
O => \gen_single_thread.active_target_hot_reg[0]\
);
\gen_single_thread.active_target_hot[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => s_axi_araddr(60),
I1 => s_axi_araddr(63),
I2 => s_axi_araddr(61),
I3 => s_axi_araddr(62),
I4 => \^s_axi_arready[1]\,
I5 => active_target_hot_1(0),
O => \gen_single_thread.active_target_hot_reg[0]_0\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0 is
port (
aa_sa_awvalid : out STD_LOGIC;
ss_aa_awready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\storage_data1_reg[0]\ : out STD_LOGIC;
\storage_data1_reg[0]_0\ : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
sel_4 : out STD_LOGIC;
p_0_out : out STD_LOGIC;
push : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[2]\ : out STD_LOGIC;
push_0 : out STD_LOGIC;
\storage_data1_reg[0]_1\ : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
\storage_data1_reg[0]_2\ : out STD_LOGIC;
\gen_rep[0].fifoaddr_reg[0]_0\ : out STD_LOGIC;
\m_axi_awqos[3]\ : out STD_LOGIC_VECTOR ( 56 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_ready_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
grant_hot1 : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\gen_axi.s_axi_awready_i_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i_reg_0 : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 56 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[0]_3\ : in STD_LOGIC;
\s_axi_awaddr[28]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0 : entity is "axi_crossbar_v2_1_12_addr_arbiter";
end system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_arbiter.any_grant_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.any_grant_reg_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot[0]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_arbiter.grant_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_arbiter.s_ready_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal grant_hot : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal qual_reg : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_4\ : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_state[2]_i_2__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \FSM_onehot_state[3]_i_3__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \FSM_onehot_state[3]_i_4__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \gen_arbiter.any_grant_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[0]_i_2__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_5\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_valid_i_i_2__2\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \storage_data1[0]_i_3\ : label is "soft_lutpair35";
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
sel_4 <= \^sel_4\;
ss_aa_awready <= \^ss_aa_awready\;
\FSM_onehot_state[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => m_ready_d(0),
I1 => \^aa_sa_awvalid\,
I2 => \^q\(0),
O => \gen_rep[0].fifoaddr_reg[0]\
);
\FSM_onehot_state[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => m_ready_d(0),
I1 => \^aa_sa_awvalid\,
I2 => \^q\(1),
O => \gen_rep[0].fifoaddr_reg[0]_0\
);
\FSM_onehot_state[3]_i_4__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \out\(0),
I1 => \^q\(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(0),
O => \storage_data1_reg[0]\
);
\gen_arbiter.any_grant_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A0E0E0"
)
port map (
I0 => \gen_arbiter.any_grant_reg_n_0\,
I1 => grant_hot1(0),
I2 => aresetn_d,
I3 => \gen_axi.s_axi_awready_i_reg\,
I4 => \^aa_sa_awvalid\,
O => \gen_arbiter.any_grant_i_1_n_0\
);
\gen_arbiter.any_grant_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.any_grant_i_1_n_0\,
Q => \gen_arbiter.any_grant_reg_n_0\,
R => '0'
);
\gen_arbiter.grant_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000ABAAA8AA"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\,
I1 => \^aa_sa_awvalid\,
I2 => \gen_arbiter.any_grant_reg_n_0\,
I3 => grant_hot1(0),
I4 => \^d\(0),
I5 => \gen_arbiter.grant_hot[0]_i_2__0_n_0\,
O => \gen_arbiter.grant_hot[0]_i_1__0_n_0\
);
\gen_arbiter.grant_hot[0]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => \gen_axi.s_axi_awready_i_reg\,
I2 => aresetn_d,
O => \gen_arbiter.grant_hot[0]_i_2__0_n_0\
);
\gen_arbiter.grant_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.grant_hot[0]_i_1__0_n_0\,
Q => \gen_arbiter.grant_hot_reg_n_0_[0]\,
R => '0'
);
\gen_arbiter.last_rr_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => s_axi_awvalid(0),
I1 => qual_reg(0),
I2 => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
I3 => p_2_in,
I4 => \^ss_aa_awready\,
I5 => m_ready_d_1(0),
O => \^d\(0)
);
\gen_arbiter.last_rr_hot[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => grant_hot1(0),
I1 => \gen_arbiter.any_grant_reg_n_0\,
I2 => \^aa_sa_awvalid\,
O => grant_hot
);
\gen_arbiter.last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \^d\(0),
Q => \gen_arbiter.last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\gen_arbiter.last_rr_hot_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => grant_hot,
D => '0',
Q => p_2_in,
S => SR(0)
);
\gen_arbiter.m_mesg_i[32]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => p_1_in
);
\gen_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(9),
Q => \m_axi_awqos[3]\(9),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(10),
Q => \m_axi_awqos[3]\(10),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(11),
Q => \m_axi_awqos[3]\(11),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(12),
Q => \m_axi_awqos[3]\(12),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(13),
Q => \m_axi_awqos[3]\(13),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(14),
Q => \m_axi_awqos[3]\(14),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(15),
Q => \m_axi_awqos[3]\(15),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(16),
Q => \m_axi_awqos[3]\(16),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(17),
Q => \m_axi_awqos[3]\(17),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(18),
Q => \m_axi_awqos[3]\(18),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(0),
Q => \m_axi_awqos[3]\(0),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(19),
Q => \m_axi_awqos[3]\(19),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(20),
Q => \m_axi_awqos[3]\(20),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(21),
Q => \m_axi_awqos[3]\(21),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(22),
Q => \m_axi_awqos[3]\(22),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(23),
Q => \m_axi_awqos[3]\(23),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(24),
Q => \m_axi_awqos[3]\(24),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(25),
Q => \m_axi_awqos[3]\(25),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(26),
Q => \m_axi_awqos[3]\(26),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(27),
Q => \m_axi_awqos[3]\(27),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(28),
Q => \m_axi_awqos[3]\(28),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(1),
Q => \m_axi_awqos[3]\(1),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(29),
Q => \m_axi_awqos[3]\(29),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(30),
Q => \m_axi_awqos[3]\(30),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(31),
Q => \m_axi_awqos[3]\(31),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(32),
Q => \m_axi_awqos[3]\(32),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(33),
Q => \m_axi_awqos[3]\(33),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(34),
Q => \m_axi_awqos[3]\(34),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(35),
Q => \m_axi_awqos[3]\(35),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(36),
Q => \m_axi_awqos[3]\(36),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(37),
Q => \m_axi_awqos[3]\(37),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(38),
Q => \m_axi_awqos[3]\(38),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(2),
Q => \m_axi_awqos[3]\(2),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(39),
Q => \m_axi_awqos[3]\(39),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(40),
Q => \m_axi_awqos[3]\(40),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(41),
Q => \m_axi_awqos[3]\(41),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(42),
Q => \m_axi_awqos[3]\(42),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(43),
Q => \m_axi_awqos[3]\(43),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(44),
Q => \m_axi_awqos[3]\(44),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(45),
Q => \m_axi_awqos[3]\(45),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(46),
Q => \m_axi_awqos[3]\(46),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(3),
Q => \m_axi_awqos[3]\(3),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(47),
Q => \m_axi_awqos[3]\(47),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(48),
Q => \m_axi_awqos[3]\(48),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(49),
Q => \m_axi_awqos[3]\(49),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(50),
Q => \m_axi_awqos[3]\(50),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(51),
Q => \m_axi_awqos[3]\(51),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(52),
Q => \m_axi_awqos[3]\(52),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(53),
Q => \m_axi_awqos[3]\(53),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(4),
Q => \m_axi_awqos[3]\(4),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(54),
Q => \m_axi_awqos[3]\(54),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(55),
Q => \m_axi_awqos[3]\(55),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(56),
Q => \m_axi_awqos[3]\(56),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(5),
Q => \m_axi_awqos[3]\(5),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(6),
Q => \m_axi_awqos[3]\(6),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(7),
Q => \m_axi_awqos[3]\(7),
R => SR(0)
);
\gen_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \s_axi_awqos[3]\(8),
Q => \m_axi_awqos[3]\(8),
R => SR(0)
);
\gen_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \s_axi_awqos[3]\(28),
I1 => \s_axi_awqos[3]\(31),
I2 => \s_axi_awqos[3]\(29),
I3 => \s_axi_awqos[3]\(30),
O => \^sel_4\
);
\gen_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \^sel_4\,
Q => \^q\(0),
R => SR(0)
);
\gen_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => grant_hot,
D => \s_axi_awaddr[28]\(0),
Q => \^q\(1),
R => SR(0)
);
\gen_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.s_axi_awready_i_reg\,
I1 => \^aa_sa_awvalid\,
I2 => \gen_arbiter.any_grant_reg_n_0\,
O => \gen_arbiter.m_valid_i_i_1_n_0\
);
\gen_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_arbiter.qual_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d_reg[0]\,
Q => qual_reg(0),
R => SR(0)
);
\gen_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \gen_arbiter.grant_hot_reg_n_0_[0]\,
I1 => \gen_arbiter.any_grant_reg_n_0\,
I2 => \^aa_sa_awvalid\,
I3 => aresetn_d,
O => \gen_arbiter.s_ready_i[0]_i_1__0_n_0\
);
\gen_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i[0]_i_1__0_n_0\,
Q => \^ss_aa_awready\,
R => '0'
);
\gen_axi.write_cs[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(1),
I1 => mi_awready(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => \gen_master_slots[1].w_issuing_cnt_reg[8]\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DB24"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(1),
I3 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(3),
I1 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(0),
I2 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I3 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(1),
I4 => \gen_master_slots[0].w_issuing_cnt_reg[3]_0\(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \^aa_sa_awvalid\,
I1 => m_ready_d(1),
I2 => \^q\(0),
I3 => m_axi_awready(0),
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFBFFFFF"
)
port map (
I0 => m_valid_i_reg_1,
I1 => m_axi_awready(0),
I2 => \^q\(0),
I3 => m_ready_d(1),
I4 => \^aa_sa_awvalid\,
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"3000300000002000"
)
port map (
I0 => \out\(1),
I1 => m_ready_d(0),
I2 => \^aa_sa_awvalid\,
I3 => \^q\(0),
I4 => m_valid_i_reg_0,
I5 => \out\(2),
O => push
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B0000000A000"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2),
I1 => \storage_data1_reg[0]_3\,
I2 => \^q\(1),
I3 => \^aa_sa_awvalid\,
I4 => m_ready_d(0),
I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1),
O => push_0
);
\gen_rep[0].fifoaddr[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4FFFFFFF5FFF"
)
port map (
I0 => \out\(2),
I1 => m_valid_i_reg_0,
I2 => \^q\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_ready_d(0),
I5 => \out\(1),
O => \gen_rep[0].fifoaddr_reg[2]\
);
\gen_rep[0].fifoaddr[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888588888884888"
)
port map (
I0 => m_valid_i_reg_0,
I1 => \out\(2),
I2 => \^q\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_ready_d(0),
I5 => \out\(1),
O => p_0_out
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(0)
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0777"
)
port map (
I0 => \^q\(0),
I1 => m_axi_awready(0),
I2 => \^q\(1),
I3 => mi_awready(0),
O => \m_ready_d_reg[1]\
);
\m_valid_i_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00002000"
)
port map (
I0 => \out\(1),
I1 => m_ready_d(0),
I2 => \^aa_sa_awvalid\,
I3 => \^q\(0),
I4 => m_valid_i_reg_0,
O => m_valid_i_reg
);
\storage_data1[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000DFFF"
)
port map (
I0 => \out\(1),
I1 => m_ready_d(0),
I2 => \^aa_sa_awvalid\,
I3 => \^q\(0),
I4 => \out\(2),
O => \storage_data1_reg[0]_1\
);
\storage_data1[0]_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0),
I1 => \^q\(1),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(0),
O => \storage_data1_reg[0]_0\
);
\storage_data1[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000DFFF"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1),
I1 => m_ready_d(0),
I2 => \^aa_sa_awvalid\,
I3 => \^q\(1),
I4 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2),
O => \storage_data1_reg[0]_2\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_decerr_slave is
port (
mi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_10_in : out STD_LOGIC;
p_17_in : out STD_LOGIC;
p_11_in : out STD_LOGIC;
p_16_in : out STD_LOGIC;
p_13_in : out STD_LOGIC;
write_cs : out STD_LOGIC_VECTOR ( 1 downto 0 );
mi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_arready_i_reg_0\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
\gen_arbiter.m_mesg_i_reg[0]\ : in STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC;
mi_bready_1 : in STD_LOGIC;
\gen_axi.write_cs_reg[1]_0\ : in STD_LOGIC;
\storage_data1_reg[0]\ : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_1 : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
active_target_enc : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_decerr_slave : entity is "axi_crossbar_v2_1_12_decerr_slave";
end system_xbar_0_axi_crossbar_v2_1_12_decerr_slave;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__0__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \^gen_axi.s_axi_arready_i_reg_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^mi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^mi_awready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_10_in\ : STD_LOGIC;
signal \^p_11_in\ : STD_LOGIC;
signal \^p_13_in\ : STD_LOGIC;
signal \^p_17_in\ : STD_LOGIC;
signal s_axi_rid_i : STD_LOGIC;
signal \^write_cs\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[7]_i_3\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_2\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_4\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair39";
begin
\gen_axi.s_axi_arready_i_reg_0\ <= \^gen_axi.s_axi_arready_i_reg_0\;
mi_arready(0) <= \^mi_arready\(0);
mi_awready(0) <= \^mi_awready\(0);
p_10_in <= \^p_10_in\;
p_11_in <= \^p_11_in\;
p_13_in <= \^p_13_in\;
p_17_in <= \^p_17_in\;
write_cs(1 downto 0) <= \^write_cs\(1 downto 0);
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => Q(0),
I1 => \gen_axi.read_cnt_reg__0__0\(0),
I2 => \^p_11_in\,
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg__0__0\(0),
I2 => \^p_11_in\,
I3 => Q(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A9FFA900"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \gen_axi.read_cnt_reg__0__0\(0),
I3 => \^p_11_in\,
I4 => Q(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE01FFFFFE010000"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(2),
I1 => \gen_axi.read_cnt_reg__0\(1),
I2 => \gen_axi.read_cnt_reg__0__0\(0),
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \^p_11_in\,
I5 => Q(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0C3AAAAAAAA"
)
port map (
I0 => Q(4),
I1 => \gen_axi.read_cnt_reg__0\(2),
I2 => \gen_axi.read_cnt_reg__0\(4),
I3 => \gen_axi.read_cnt_reg__0\(3),
I4 => \gen_axi.read_cnt[4]_i_2_n_0\,
I5 => \^p_11_in\,
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_axi.read_cnt_reg__0__0\(0),
I1 => \gen_axi.read_cnt_reg__0\(1),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3CAA"
)
port map (
I0 => Q(5),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \^p_11_in\,
O => p_0_in(5)
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EE2E22E2"
)
port map (
I0 => Q(6),
I1 => \^p_11_in\,
I2 => \gen_axi.read_cnt[7]_i_3_n_0\,
I3 => \gen_axi.read_cnt_reg__0\(5),
I4 => \gen_axi.read_cnt_reg__0\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => aa_mi_arvalid,
I1 => \gen_arbiter.m_target_hot_i_reg[1]_0\(0),
I2 => \^mi_arready\(0),
I3 => \^p_11_in\,
I4 => mi_rready_1,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF7333BCCC40008"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \^p_11_in\,
I2 => \gen_axi.read_cnt_reg__0\(5),
I3 => \gen_axi.read_cnt_reg__0\(6),
I4 => \gen_axi.read_cnt_reg__0\(7),
I5 => Q(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(1),
I1 => \gen_axi.read_cnt_reg__0__0\(0),
I2 => \gen_axi.read_cnt_reg__0\(3),
I3 => \gen_axi.read_cnt_reg__0\(4),
I4 => \gen_axi.read_cnt_reg__0\(2),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__0__0\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg__0\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg__0\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg__0\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg__0\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg__0\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg__0\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg__0\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080FF80FF80FF80"
)
port map (
I0 => aa_mi_arvalid,
I1 => \gen_arbiter.m_target_hot_i_reg[1]_0\(0),
I2 => \^mi_arready\(0),
I3 => \^p_11_in\,
I4 => mi_rready_1,
I5 => \^gen_axi.s_axi_arready_i_reg_0\,
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_11_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready\(0),
I1 => \^p_11_in\,
I2 => mi_rready_1,
I3 => \^gen_axi.s_axi_arready_i_reg_0\,
I4 => aresetn_d,
I5 => s_axi_rid_i,
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \gen_axi.read_cnt[7]_i_3_n_0\,
I1 => \gen_axi.read_cnt_reg__0\(5),
I2 => \gen_axi.read_cnt_reg__0\(6),
I3 => \gen_axi.read_cnt_reg__0\(7),
O => \^gen_axi.s_axi_arready_i_reg_0\
);
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^mi_arready\(0),
I1 => \gen_arbiter.m_target_hot_i_reg[1]_0\(0),
I2 => aa_mi_arvalid,
I3 => \^p_11_in\,
O => s_axi_rid_i
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready\(0),
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFDD3011"
)
port map (
I0 => \gen_arbiter.m_target_hot_i_reg[1]\,
I1 => \^write_cs\(0),
I2 => mi_bready_1,
I3 => \^write_cs\(1),
I4 => \^mi_awready\(0),
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready\(0),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF7F800"
)
port map (
I0 => \^write_cs\(1),
I1 => mi_bready_1,
I2 => \^write_cs\(0),
I3 => \storage_data1_reg[0]\,
I4 => \^p_17_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_17_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.m_mesg_i_reg[0]\,
Q => p_16_in,
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BABB8A88"
)
port map (
I0 => s_axi_rlast_i0,
I1 => s_axi_rid_i,
I2 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => \^p_13_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFFFFFF"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(3),
I1 => \gen_axi.read_cnt_reg__0\(4),
I2 => \gen_axi.read_cnt_reg__0\(2),
I3 => \^p_11_in\,
I4 => mi_rready_1,
I5 => \gen_axi.read_cnt_reg__0\(1),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(7),
I1 => \gen_axi.read_cnt_reg__0\(6),
I2 => \gen_axi.read_cnt_reg__0\(5),
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_13_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0AFF0A02"
)
port map (
I0 => \gen_arbiter.m_target_hot_i_reg[1]\,
I1 => \^write_cs\(1),
I2 => \^write_cs\(0),
I3 => \gen_axi.write_cs_reg[1]_0\,
I4 => \^p_10_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_10_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4746"
)
port map (
I0 => \gen_axi.write_cs_reg[1]_0\,
I1 => \^write_cs\(0),
I2 => \^write_cs\(1),
I3 => \gen_arbiter.m_target_hot_i_reg[1]\,
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F1C0"
)
port map (
I0 => mi_bready_1,
I1 => \gen_axi.write_cs_reg[1]_0\,
I2 => \^write_cs\(0),
I3 => \^write_cs\(1),
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => \^write_cs\(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => \^write_cs\(1),
R => SR(0)
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BBB"
)
port map (
I0 => \^p_17_in\,
I1 => mi_bready_1,
I2 => active_target_enc,
I3 => s_axi_bready(0),
O => m_valid_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_si_transactor is
port (
active_target_enc : out STD_LOGIC;
active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
active_target_hot_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc_1 : in STD_LOGIC;
st_mr_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[130]\ : in STD_LOGIC;
\gen_arbiter.s_ready_i_reg[0]_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_si_transactor : entity is "axi_crossbar_v2_1_12_si_transactor";
end system_xbar_0_axi_crossbar_v2_1_12_si_transactor;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_si_transactor is
signal accept_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^active_target_enc\ : STD_LOGIC;
signal \^active_target_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_arbiter.m_grant_enc_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair318";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair318";
attribute SOFT_HLUTNM of \s_axi_rresp[0]_INST_0\ : label is "soft_lutpair319";
attribute SOFT_HLUTNM of \s_axi_rresp[1]_INST_0\ : label is "soft_lutpair319";
begin
active_target_enc <= \^active_target_enc\;
active_target_hot(0) <= \^active_target_hot\(0);
\gen_arbiter.m_grant_enc_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAA9AA"
)
port map (
I0 => \^active_target_enc\,
I1 => s_axi_araddr(2),
I2 => s_axi_araddr(1),
I3 => s_axi_araddr(3),
I4 => s_axi_araddr(0),
O => \gen_arbiter.m_grant_enc_i[0]_i_11_n_0\
);
\gen_arbiter.m_grant_enc_i[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF008000FF00FFFF"
)
port map (
I0 => s_axi_rvalid(0),
I1 => s_axi_rlast(0),
I2 => s_axi_rready(0),
I3 => \gen_arbiter.m_grant_enc_i[0]_i_11_n_0\,
I4 => accept_cnt(0),
I5 => accept_cnt(1),
O => \gen_arbiter.qual_reg_reg[0]\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0880088"
)
port map (
I0 => \^active_target_hot\(0),
I1 => s_axi_rready(0),
I2 => active_target_hot_0(0),
I3 => Q(2),
I4 => s_axi_rready(1),
O => \gen_master_slots[0].r_issuing_cnt_reg[0]\
);
\gen_master_slots[1].r_issuing_cnt[8]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0880088"
)
port map (
I0 => \^active_target_enc\,
I1 => s_axi_rready(0),
I2 => active_target_enc_1,
I3 => st_mr_rid(0),
I4 => s_axi_rready(1),
O => \gen_master_slots[1].r_issuing_cnt_reg[8]\
);
\gen_single_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9962"
)
port map (
I0 => \gen_arbiter.s_ready_i_reg[0]_1\,
I1 => \m_payload_i_reg[130]\,
I2 => accept_cnt(1),
I3 => accept_cnt(0),
O => \gen_single_thread.accept_cnt[0]_i_1_n_0\
);
\gen_single_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"C68C"
)
port map (
I0 => accept_cnt(0),
I1 => accept_cnt(1),
I2 => \m_payload_i_reg[130]\,
I3 => \gen_arbiter.s_ready_i_reg[0]_1\,
O => \gen_single_thread.accept_cnt[1]_i_1_n_0\
);
\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[0]_i_1_n_0\,
Q => accept_cnt(0),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[1]_i_1_n_0\,
Q => accept_cnt(1),
R => SR(0)
);
\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i_reg[0]\,
Q => \^active_target_enc\,
R => SR(0)
);
\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i_reg[0]_0\,
Q => \^active_target_hot\(0),
R => SR(0)
);
\s_axi_rresp[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => Q(0),
O => s_axi_rresp(0)
);
\s_axi_rresp[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => Q(1),
O => s_axi_rresp(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\ is
port (
active_target_enc : out STD_LOGIC;
active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : out STD_LOGIC;
grant_hot1 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_single_thread.active_target_enc_reg[0]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_single_thread.active_target_hot_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_34_out : in STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[1]\ : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
ss_wr_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
p_58_out : in STD_LOGIC;
st_mr_bmesg : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_12_si_transactor";
end \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\;
architecture STRUCTURE of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\ is
signal \^active_target_enc\ : STD_LOGIC;
signal \^active_target_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_arbiter.last_rr_hot[1]_i_3_n_0\ : STD_LOGIC;
signal \gen_arbiter.qual_reg[0]_i_5_n_0\ : STD_LOGIC;
signal \^gen_arbiter.qual_reg_reg[0]\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[1]_i_1__1_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.last_rr_hot[1]_i_3\ : label is "soft_lutpair322";
attribute SOFT_HLUTNM of \gen_arbiter.qual_reg[0]_i_5\ : label is "soft_lutpair323";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[8]_i_1\ : label is "soft_lutpair322";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1__1\ : label is "soft_lutpair323";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair321";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[3]_i_2\ : label is "soft_lutpair321";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[3]_i_3\ : label is "soft_lutpair320";
attribute SOFT_HLUTNM of \s_axi_bresp[0]_INST_0\ : label is "soft_lutpair324";
attribute SOFT_HLUTNM of \s_axi_bresp[1]_INST_0\ : label is "soft_lutpair324";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0\ : label is "soft_lutpair320";
begin
active_target_enc <= \^active_target_enc\;
active_target_hot(0) <= \^active_target_hot\(0);
\gen_arbiter.qual_reg_reg[0]\ <= \^gen_arbiter.qual_reg_reg[0]\;
\gen_arbiter.last_rr_hot[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A22AA00000000"
)
port map (
I0 => D(0),
I1 => \gen_master_slots[0].w_issuing_cnt_reg[0]\,
I2 => w_issuing_cnt(0),
I3 => sel_4,
I4 => \gen_arbiter.last_rr_hot[1]_i_3_n_0\,
I5 => \^gen_arbiter.qual_reg_reg[0]\,
O => grant_hot1(0)
);
\gen_arbiter.last_rr_hot[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_bready(0),
I1 => \^active_target_enc\,
I2 => p_34_out,
O => \gen_arbiter.last_rr_hot[1]_i_3_n_0\
);
\gen_arbiter.qual_reg[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"3C7D3C55"
)
port map (
I0 => \gen_single_thread.accept_cnt_reg\(3),
I1 => \^active_target_enc\,
I2 => sel_4,
I3 => \gen_arbiter.qual_reg[0]_i_5_n_0\,
I4 => \gen_single_thread.accept_cnt[3]_i_3_n_0\,
O => \^gen_arbiter.qual_reg_reg[0]\
);
\gen_arbiter.qual_reg[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_single_thread.accept_cnt_reg\(0),
I1 => \gen_single_thread.accept_cnt_reg\(1),
I2 => \gen_single_thread.accept_cnt_reg\(2),
O => \gen_arbiter.qual_reg[0]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F7F00"
)
port map (
I0 => s_axi_bready(0),
I1 => \^active_target_enc\,
I2 => p_34_out,
I3 => \gen_arbiter.m_target_hot_i_reg[1]\,
I4 => w_issuing_cnt(0),
O => \gen_master_slots[1].w_issuing_cnt_reg[8]\
);
\gen_single_thread.accept_cnt[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_single_thread.accept_cnt_reg\(0),
O => \gen_single_thread.accept_cnt[0]_i_1__1_n_0\
);
\gen_single_thread.accept_cnt[1]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"565656AAA9A9A955"
)
port map (
I0 => \gen_single_thread.accept_cnt_reg\(0),
I1 => ss_aa_awready,
I2 => m_ready_d(0),
I3 => m_ready_d(1),
I4 => ss_wr_awready(0),
I5 => \gen_single_thread.accept_cnt_reg\(1),
O => \gen_single_thread.accept_cnt[1]_i_1__1_n_0\
);
\gen_single_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_arbiter.s_ready_i_reg[0]\,
I1 => \gen_single_thread.accept_cnt_reg\(0),
I2 => \gen_single_thread.accept_cnt_reg\(1),
I3 => \gen_single_thread.accept_cnt_reg\(2),
O => \gen_single_thread.accept_cnt[2]_i_1_n_0\
);
\gen_single_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6666666666666662"
)
port map (
I0 => \gen_arbiter.s_ready_i_reg[0]\,
I1 => \gen_single_thread.accept_cnt[3]_i_3_n_0\,
I2 => \gen_single_thread.accept_cnt_reg\(0),
I3 => \gen_single_thread.accept_cnt_reg\(1),
I4 => \gen_single_thread.accept_cnt_reg\(2),
I5 => \gen_single_thread.accept_cnt_reg\(3),
O => \gen_single_thread.accept_cnt[3]_i_1_n_0\
);
\gen_single_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAA9"
)
port map (
I0 => \gen_single_thread.accept_cnt_reg\(3),
I1 => \gen_single_thread.accept_cnt_reg\(2),
I2 => \gen_single_thread.accept_cnt_reg\(1),
I3 => \gen_single_thread.accept_cnt_reg\(0),
I4 => \gen_arbiter.s_ready_i_reg[0]\,
O => \gen_single_thread.accept_cnt[3]_i_2_n_0\
);
\gen_single_thread.accept_cnt[3]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA808080"
)
port map (
I0 => s_axi_bready(0),
I1 => p_34_out,
I2 => \^active_target_enc\,
I3 => p_58_out,
I4 => \^active_target_hot\(0),
O => \gen_single_thread.accept_cnt[3]_i_3_n_0\
);
\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_single_thread.accept_cnt[3]_i_1_n_0\,
D => \gen_single_thread.accept_cnt[0]_i_1__1_n_0\,
Q => \gen_single_thread.accept_cnt_reg\(0),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_single_thread.accept_cnt[3]_i_1_n_0\,
D => \gen_single_thread.accept_cnt[1]_i_1__1_n_0\,
Q => \gen_single_thread.accept_cnt_reg\(1),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_single_thread.accept_cnt[3]_i_1_n_0\,
D => \gen_single_thread.accept_cnt[2]_i_1_n_0\,
Q => \gen_single_thread.accept_cnt_reg\(2),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_single_thread.accept_cnt[3]_i_1_n_0\,
D => \gen_single_thread.accept_cnt[3]_i_2_n_0\,
Q => \gen_single_thread.accept_cnt_reg\(3),
R => SR(0)
);
\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.active_target_enc_reg[0]_0\,
Q => \^active_target_enc\,
R => SR(0)
);
\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.active_target_hot_reg[0]_0\,
Q => \^active_target_hot\(0),
R => SR(0)
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => st_mr_bmesg(0),
O => s_axi_bresp(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => st_mr_bmesg(1),
O => s_axi_bresp(1)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_34_out,
I1 => \^active_target_enc\,
I2 => p_58_out,
I3 => \^active_target_hot\(0),
O => s_axi_bvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\ is
port (
active_target_enc : out STD_LOGIC;
active_target_hot : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.qual_reg_reg[1]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.s_ready_i_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_arbiter.s_ready_i_reg[1]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_arbiter.s_ready_i_reg[1]_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\ : entity is "axi_crossbar_v2_1_12_si_transactor";
end \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\;
architecture STRUCTURE of \system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\ is
signal accept_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^active_target_enc\ : STD_LOGIC;
signal \^active_target_hot\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_arbiter.m_grant_enc_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_single_thread.accept_cnt[1]_i_2_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair327";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair327";
attribute SOFT_HLUTNM of \s_axi_rresp[2]_INST_0\ : label is "soft_lutpair328";
attribute SOFT_HLUTNM of \s_axi_rresp[3]_INST_0\ : label is "soft_lutpair328";
begin
active_target_enc <= \^active_target_enc\;
active_target_hot(0) <= \^active_target_hot\(0);
s_axi_rvalid(0) <= \^s_axi_rvalid\(0);
\gen_arbiter.m_grant_enc_i[0]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF008000FF00FFFF"
)
port map (
I0 => \^s_axi_rvalid\(0),
I1 => s_axi_rlast(0),
I2 => s_axi_rready(0),
I3 => \gen_arbiter.m_grant_enc_i[0]_i_12_n_0\,
I4 => accept_cnt(0),
I5 => accept_cnt(1),
O => \gen_arbiter.qual_reg_reg[1]\
);
\gen_arbiter.m_grant_enc_i[0]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAA9AA"
)
port map (
I0 => \^active_target_enc\,
I1 => s_axi_araddr(2),
I2 => s_axi_araddr(1),
I3 => s_axi_araddr(3),
I4 => s_axi_araddr(0),
O => \gen_arbiter.m_grant_enc_i[0]_i_12_n_0\
);
\gen_single_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9962"
)
port map (
I0 => \gen_arbiter.s_ready_i_reg[1]_1\,
I1 => \gen_single_thread.accept_cnt[1]_i_2_n_0\,
I2 => accept_cnt(1),
I3 => accept_cnt(0),
O => \gen_single_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_single_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C68C"
)
port map (
I0 => accept_cnt(0),
I1 => accept_cnt(1),
I2 => \gen_single_thread.accept_cnt[1]_i_2_n_0\,
I3 => \gen_arbiter.s_ready_i_reg[1]_1\,
O => \gen_single_thread.accept_cnt[1]_i_1__0_n_0\
);
\gen_single_thread.accept_cnt[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A800000"
)
port map (
I0 => \^s_axi_rvalid\(0),
I1 => st_mr_rlast(0),
I2 => \^active_target_enc\,
I3 => Q(2),
I4 => s_axi_rready(0),
O => \gen_single_thread.accept_cnt[1]_i_2_n_0\
);
\gen_single_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[0]_i_1__0_n_0\,
Q => accept_cnt(0),
R => SR(0)
);
\gen_single_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_single_thread.accept_cnt[1]_i_1__0_n_0\,
Q => accept_cnt(1),
R => SR(0)
);
\gen_single_thread.active_target_enc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i_reg[1]\,
Q => \^active_target_enc\,
R => SR(0)
);
\gen_single_thread.active_target_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_arbiter.s_ready_i_reg[1]_0\,
Q => \^active_target_hot\(0),
R => SR(0)
);
\s_axi_rresp[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => Q(0),
O => s_axi_rresp(0)
);
\s_axi_rresp[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^active_target_enc\,
I1 => Q(1),
O => s_axi_rresp(1)
);
\s_axi_rvalid[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \^active_target_enc\,
I1 => st_mr_rid(0),
I2 => st_mr_rvalid(1),
I3 => \^active_target_hot\(0),
I4 => Q(3),
I5 => st_mr_rvalid(0),
O => \^s_axi_rvalid\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_splitter is
port (
\gen_single_thread.active_target_hot_reg[0]\ : out STD_LOGIC;
\s_axi_awready[0]\ : out STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_rep[0].fifoaddr_reg[0]\ : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].w_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_single_thread.accept_cnt_reg[3]\ : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
ss_wr_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_splitter : entity is "axi_crossbar_v2_1_12_splitter";
end system_xbar_0_axi_crossbar_v2_1_12_splitter;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.qual_reg[0]_i_1\ : label is "soft_lutpair325";
attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_4\ : label is "soft_lutpair325";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
\gen_arbiter.qual_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFDD"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(0),
I2 => \gen_master_slots[1].w_issuing_cnt_reg[8]\,
I3 => \gen_single_thread.accept_cnt_reg[3]\,
O => \gen_arbiter.qual_reg_reg[0]\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => s_axi_awvalid(0),
O => \gen_rep[0].fifoaddr_reg[0]\
);
\gen_single_thread.active_target_enc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFFFFEF0000"
)
port map (
I0 => s_axi_awaddr(2),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(3),
I3 => s_axi_awaddr(0),
I4 => \^s_axi_awready[0]\,
I5 => active_target_enc,
O => \gen_single_thread.active_target_enc_reg[0]\
);
\gen_single_thread.active_target_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040000"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awaddr(3),
I2 => s_axi_awaddr(1),
I3 => s_axi_awaddr(2),
I4 => \^s_axi_awready[0]\,
I5 => active_target_hot(0),
O => \gen_single_thread.active_target_hot_reg[0]\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000CC80"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => ss_aa_awready,
I3 => \^m_ready_d\(0),
I4 => \^m_ready_d\(1),
I5 => ss_wr_awready(0),
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => ss_aa_awready,
I3 => \^m_ready_d\(0),
I4 => \^m_ready_d\(1),
I5 => ss_wr_awready(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => ss_aa_awready,
I1 => \^m_ready_d\(0),
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready(0),
O => \^s_axi_awready[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_splitter_2 is
port (
\m_ready_d_reg[1]_0\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_sa_awvalid : in STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[0]\ : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_splitter_2 : entity is "axi_crossbar_v2_1_12_splitter";
end system_xbar_0_axi_crossbar_v2_1_12_splitter_2;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_splitter_2 is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \^m_ready_d_reg[1]_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d_reg[1]_0\ <= \^m_ready_d_reg[1]_0\;
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEAA0000"
)
port map (
I0 => \^m_ready_d\(0),
I1 => Q(0),
I2 => Q(1),
I3 => aa_sa_awvalid,
I4 => aresetn_d,
I5 => \^m_ready_d_reg[1]_0\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F200"
)
port map (
I0 => aa_sa_awvalid,
I1 => \gen_arbiter.m_target_hot_i_reg[0]\,
I2 => \^m_ready_d\(1),
I3 => aresetn_d,
I4 => \^m_ready_d_reg[1]_0\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFAFCF0FEFAFC00"
)
port map (
I0 => m_axi_awready(0),
I1 => mi_awready(0),
I2 => \^m_ready_d\(1),
I3 => Q(1),
I4 => Q(0),
I5 => \^m_ready_d\(0),
O => \^m_ready_d_reg[1]_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
\storage_data1_reg[0]_0\ : out STD_LOGIC;
push : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC;
\storage_data1_reg[0]_1\ : in STD_LOGIC;
p_10_in : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
m_avalid : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl;
architecture STRUCTURE of system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl is
signal \^storage_data1_reg[0]_0\ : STD_LOGIC;
signal storage_data2 : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => A(0),
A1 => A(1),
A2 => '0',
A3 => '0',
CE => push,
CLK => aclk,
D => '0',
Q => storage_data2
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \storage_data1_reg[0]_1\,
I1 => p_10_in,
I2 => m_select_enc_0,
I3 => m_avalid,
I4 => m_valid_i_reg,
O => \^storage_data1_reg[0]_0\
);
\storage_data1[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F888F8F80888080"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0),
I1 => storage_data2,
I2 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\,
I4 => \^storage_data1_reg[0]_0\,
I5 => \storage_data1_reg[0]_1\,
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized17\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
\storage_data1_reg[0]_0\ : out STD_LOGIC;
push : in STD_LOGIC;
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC;
\storage_data1_reg[0]_1\ : in STD_LOGIC;
m_avalid : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized17\ : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized17\;
architecture STRUCTURE of \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized17\ is
signal \^storage_data1_reg[0]_0\ : STD_LOGIC;
signal storage_data2 : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => fifoaddr(0),
A1 => fifoaddr(1),
A2 => fifoaddr(2),
A3 => '0',
CE => push,
CLK => aclk,
D => '0',
Q => storage_data2
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => m_avalid,
I1 => m_select_enc_0,
I2 => m_axi_wready(0),
I3 => \storage_data1_reg[0]_1\,
I4 => s_axi_wlast(0),
I5 => m_valid_i_reg,
O => \^storage_data1_reg[0]_0\
);
\storage_data1[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F888F8F80888080"
)
port map (
I0 => \out\(0),
I1 => storage_data2,
I2 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
I3 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\,
I4 => \^storage_data1_reg[0]_0\,
I5 => \storage_data1_reg[0]_1\,
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ is
port (
push : out STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\storage_data1_reg[0]\ : out STD_LOGIC;
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
sel_4 : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
\storage_data1_reg[0]_0\ : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_ready_i_reg : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
m_valid_i_reg_1 : in STD_LOGIC;
\m_ready_d_reg[1]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ : entity is "axi_data_fifo_v2_1_10_ndeep_srl";
end \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\;
architecture STRUCTURE of \system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\ is
signal \^gen_arbiter.m_target_hot_i_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^push\ : STD_LOGIC;
signal storage_data2 : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "SRLC32E";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_arbiter.m_target_hot_i_reg[1]\(0) <= \^gen_arbiter.m_target_hot_i_reg[1]\(0);
push <= \^push\;
\gen_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => s_axi_awaddr(2),
I1 => s_axi_awaddr(1),
I2 => s_axi_awaddr(3),
I3 => s_axi_awaddr(0),
O => \^gen_arbiter.m_target_hot_i_reg[1]\(0)
);
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => fifoaddr(0),
A1 => fifoaddr(1),
A2 => fifoaddr(2),
A3 => '0',
CE => \^push\,
CLK => aclk,
D => \^gen_arbiter.m_target_hot_i_reg[1]\(0),
Q => storage_data2
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F8F8F888"
)
port map (
I0 => s_ready_i_reg,
I1 => out0(0),
I2 => out0(1),
I3 => m_valid_i_reg_0,
I4 => m_valid_i_reg_1,
I5 => \m_ready_d_reg[1]_0\,
O => \^push\
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA33AFFFAA33A000"
)
port map (
I0 => storage_data2,
I1 => sel_4,
I2 => m_valid_i_reg,
I3 => out0(0),
I4 => \m_ready_d_reg[1]\,
I5 => \storage_data1_reg[0]_0\,
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ is
port (
p_34_out : out STD_LOGIC;
mi_bready_1 : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
\gen_axi.s_axi_bvalid_i_reg\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_17_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\;
architecture STRUCTURE of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\ is
signal \^p_34_out\ : STD_LOGIC;
signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC;
begin
p_34_out <= \^p_34_out\;
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_reg\,
Q => \^p_34_out\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^p_34_out\,
I1 => p_17_in,
I2 => s_axi_bready(0),
I3 => active_target_enc,
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__3_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__3_n_0\,
Q => mi_bready_1,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_3\ is
port (
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
s_ready_i_reg_1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[0]_0\ : out STD_LOGIC;
st_mr_bmesg : out STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
p_34_out : in STD_LOGIC;
active_target_enc_1 : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_3\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_3\;
architecture STRUCTURE of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_3\ is
signal \aresetn_d[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_arbiter.qual_reg_reg[0]_0\ : STD_LOGIC;
signal \^gen_master_slots[0].w_issuing_cnt_reg[0]\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \m_payload_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1_n_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal \s_ready_i_i_2__1_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \^s_ready_i_reg_1\ : STD_LOGIC;
signal \^st_mr_bmesg\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \s_ready_i_i_2__1\ : label is "soft_lutpair117";
begin
\gen_arbiter.qual_reg_reg[0]_0\ <= \^gen_arbiter.qual_reg_reg[0]_0\;
\gen_master_slots[0].w_issuing_cnt_reg[0]\ <= \^gen_master_slots[0].w_issuing_cnt_reg[0]\;
m_axi_bready(0) <= \^m_axi_bready\(0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
p_1_in <= \^p_1_in\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
s_ready_i_reg_1 <= \^s_ready_i_reg_1\;
st_mr_bmesg(1 downto 0) <= \^st_mr_bmesg\(1 downto 0);
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d[1]_i_1_n_0\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d[1]_i_1_n_0\,
Q => \^s_ready_i_reg_1\,
R => '0'
);
\gen_arbiter.qual_reg[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0ACACACACACACAC"
)
port map (
I0 => \^gen_arbiter.qual_reg_reg[0]_0\,
I1 => w_issuing_cnt(4),
I2 => sel_4,
I3 => p_34_out,
I4 => active_target_enc_1,
I5 => s_axi_bready(0),
O => \gen_arbiter.qual_reg_reg[0]\
);
\gen_arbiter.qual_reg[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => w_issuing_cnt(0),
I1 => w_issuing_cnt(3),
I2 => w_issuing_cnt(2),
I3 => w_issuing_cnt(1),
I4 => \^gen_master_slots[0].w_issuing_cnt_reg[0]\,
O => \^gen_arbiter.qual_reg_reg[0]_0\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA855555555"
)
port map (
I0 => \^gen_master_slots[0].w_issuing_cnt_reg[0]\,
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(3),
I4 => w_issuing_cnt(0),
I5 => \gen_arbiter.m_valid_i_reg\,
O => E(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => s_axi_bready(0),
I2 => active_target_hot(0),
O => \^gen_master_slots[0].w_issuing_cnt_reg[0]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => m_axi_bresp(0),
I1 => \^s_ready_i_reg_0\,
I2 => \^st_mr_bmesg\(0),
O => \m_payload_i[0]_i_1_n_0\
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E2"
)
port map (
I0 => m_axi_bresp(1),
I1 => \^s_ready_i_reg_0\,
I2 => \^st_mr_bmesg\(1),
O => \m_payload_i[1]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[0]_i_1_n_0\,
Q => \^st_mr_bmesg\(0),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[1]_i_1_n_0\,
Q => \^st_mr_bmesg\(1),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_1\,
O => \^m_valid_i_reg_0\
);
m_valid_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"8BBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => active_target_hot(0),
I3 => s_axi_bready(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
\s_ready_i_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => active_target_hot(0),
I4 => \^s_ready_i_reg_1\,
O => \s_ready_i_i_2__1_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_2__1_n_0\,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
port (
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
\skid_buffer_reg[130]_0\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]_0\ : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]_1\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[1]_0\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[1]_1\ : out STD_LOGIC;
\gen_single_thread.accept_cnt_reg[1]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[131]_0\ : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]\ : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[130]_0\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
\gen_single_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
sel_4_0 : in STD_LOGIC;
\gen_single_thread.accept_cnt_reg[0]_0\ : in STD_LOGIC;
active_target_enc_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
p_11_in : in STD_LOGIC;
active_target_enc_2 : in STD_LOGIC;
p_16_in : in STD_LOGIC;
p_13_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\;
architecture STRUCTURE of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\ is
signal \^gen_arbiter.qual_reg_reg[0]\ : STD_LOGIC;
signal \^gen_arbiter.qual_reg_reg[1]_0\ : STD_LOGIC;
signal \^gen_arbiter.qual_reg_reg[1]_1\ : STD_LOGIC;
signal \^gen_master_slots[1].r_issuing_cnt_reg[8]\ : STD_LOGIC;
signal \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\ : STD_LOGIC;
signal \m_payload_i[130]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[131]_i_1_n_0\ : STD_LOGIC;
signal \^m_payload_i_reg[131]_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \m_valid_i_i_2__0_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 131 downto 130 );
signal \^skid_buffer_reg[130]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[130]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[131]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.m_grant_enc_i[0]_i_6\ : label is "soft_lutpair317";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[8]_i_1\ : label is "soft_lutpair317";
attribute SOFT_HLUTNM of \gen_single_thread.accept_cnt[1]_i_2__0\ : label is "soft_lutpair314";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_1\ : label is "soft_lutpair316";
attribute SOFT_HLUTNM of \m_payload_i[131]_i_1\ : label is "soft_lutpair315";
attribute SOFT_HLUTNM of \s_axi_rlast[0]_INST_0\ : label is "soft_lutpair314";
attribute SOFT_HLUTNM of \skid_buffer[130]_i_1\ : label is "soft_lutpair316";
attribute SOFT_HLUTNM of \skid_buffer[131]_i_1\ : label is "soft_lutpair315";
begin
\gen_arbiter.qual_reg_reg[0]\ <= \^gen_arbiter.qual_reg_reg[0]\;
\gen_arbiter.qual_reg_reg[1]_0\ <= \^gen_arbiter.qual_reg_reg[1]_0\;
\gen_arbiter.qual_reg_reg[1]_1\ <= \^gen_arbiter.qual_reg_reg[1]_1\;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ <= \^gen_master_slots[1].r_issuing_cnt_reg[8]\;
\gen_master_slots[1].r_issuing_cnt_reg[8]_1\ <= \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\;
\m_payload_i_reg[131]_0\ <= \^m_payload_i_reg[131]_0\;
s_axi_rvalid(0) <= \^s_axi_rvalid\(0);
\skid_buffer_reg[130]_0\ <= \^skid_buffer_reg[130]_0\;
\gen_arbiter.m_grant_enc_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFF555500000000"
)
port map (
I0 => \^gen_arbiter.qual_reg_reg[1]_0\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
I2 => r_issuing_cnt(0),
I3 => \m_payload_i_reg[130]_0\,
I4 => sel_4,
I5 => \gen_single_thread.accept_cnt_reg[0]\,
O => \^gen_arbiter.qual_reg_reg[0]\
);
\gen_arbiter.m_grant_enc_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFF555500000000"
)
port map (
I0 => \^gen_arbiter.qual_reg_reg[1]_0\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
I2 => r_issuing_cnt(0),
I3 => \m_payload_i_reg[130]_0\,
I4 => sel_4_0,
I5 => \gen_single_thread.accept_cnt_reg[0]_0\,
O => \^gen_arbiter.qual_reg_reg[1]_1\
);
\gen_arbiter.m_grant_enc_i[0]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => r_issuing_cnt(1),
I1 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\,
I3 => \gen_single_thread.active_target_enc_reg[0]\,
O => \^gen_arbiter.qual_reg_reg[1]_0\
);
\gen_arbiter.qual_reg[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^gen_arbiter.qual_reg_reg[0]\,
I1 => s_axi_arvalid(0),
O => \gen_arbiter.qual_reg_reg[1]\(0)
);
\gen_arbiter.qual_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^gen_arbiter.qual_reg_reg[1]_1\,
I1 => s_axi_arvalid(1),
O => \gen_arbiter.qual_reg_reg[1]\(1)
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"95552AAA"
)
port map (
I0 => \gen_arbiter.m_valid_i_reg\,
I1 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\,
I3 => \gen_single_thread.active_target_enc_reg[0]\,
I4 => r_issuing_cnt(1),
O => \gen_master_slots[1].r_issuing_cnt_reg[8]_0\
);
\gen_single_thread.accept_cnt[1]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A800000"
)
port map (
I0 => \^s_axi_rvalid\(0),
I1 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\,
I2 => active_target_enc_1,
I3 => Q(0),
I4 => s_axi_rready(0),
O => \gen_single_thread.accept_cnt_reg[1]\
);
\m_payload_i[130]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFB800B8"
)
port map (
I0 => p_13_in,
I1 => \^skid_buffer_reg[130]_0\,
I2 => \skid_buffer_reg_n_0_[130]\,
I3 => \m_valid_i_i_2__0_n_0\,
I4 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\,
O => \m_payload_i[130]_i_1_n_0\
);
\m_payload_i[131]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFB800B8"
)
port map (
I0 => p_16_in,
I1 => \^skid_buffer_reg[130]_0\,
I2 => \skid_buffer_reg_n_0_[131]\,
I3 => \m_valid_i_i_2__0_n_0\,
I4 => \^m_payload_i_reg[131]_0\,
O => \m_payload_i[131]_i_1_n_0\
);
\m_payload_i_reg[130]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[130]_i_1_n_0\,
Q => \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\,
R => '0'
);
\m_payload_i_reg[131]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[131]_i_1_n_0\,
Q => \^m_payload_i_reg[131]_0\,
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \m_valid_i_i_2__0_n_0\,
I1 => p_11_in,
I2 => \^skid_buffer_reg[130]_0\,
O => m_valid_i0
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"20A02AAA2AAA2AAA"
)
port map (
I0 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
I1 => s_axi_rready(1),
I2 => \^m_payload_i_reg[131]_0\,
I3 => active_target_enc_2,
I4 => s_axi_rready(0),
I5 => active_target_enc_1,
O => \m_valid_i_i_2__0_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
R => \aresetn_d_reg[1]\
);
\s_axi_rlast[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\,
I1 => active_target_enc_1,
I2 => Q(0),
O => s_axi_rlast(0)
);
\s_axi_rlast[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^gen_master_slots[1].r_issuing_cnt_reg[8]_1\,
I1 => active_target_enc_2,
I2 => Q(0),
O => s_axi_rlast(1)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"40FF404040404040"
)
port map (
I0 => \^m_payload_i_reg[131]_0\,
I1 => active_target_enc_1,
I2 => \^gen_master_slots[1].r_issuing_cnt_reg[8]\,
I3 => Q(1),
I4 => active_target_hot(0),
I5 => m_valid_i_reg_0(0),
O => \^s_axi_rvalid\(0)
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => p_11_in,
I1 => \^skid_buffer_reg[130]_0\,
I2 => \m_valid_i_i_2__0_n_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[130]_0\,
R => p_1_in
);
\skid_buffer[130]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_13_in,
I1 => \^skid_buffer_reg[130]_0\,
I2 => \skid_buffer_reg_n_0_[130]\,
O => skid_buffer(130)
);
\skid_buffer[131]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_16_in,
I1 => \^skid_buffer_reg[130]_0\,
I2 => \skid_buffer_reg_n_0_[131]\,
O => skid_buffer(131)
);
\skid_buffer_reg[130]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(130),
Q => \skid_buffer_reg_n_0_[130]\,
R => '0'
);
\skid_buffer_reg[131]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(131),
Q => \skid_buffer_reg_n_0_[131]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_4\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
active_target_enc : in STD_LOGIC;
active_target_enc_0 : in STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[0]\ : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_single_thread.active_target_hot_reg[0]\ : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]_1\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_hot_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
active_target_hot_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_4\ : entity is "axi_register_slice_v2_1_11_axic_register_slice";
end \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_4\;
architecture STRUCTURE of \system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_4\ is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gen_master_slots[0].r_issuing_cnt_reg[0]_0\ : STD_LOGIC;
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in_0 : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 131 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[100]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[101]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[102]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[103]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[104]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[105]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[106]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[107]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[108]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[109]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[110]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[111]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[112]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[113]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[114]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[115]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[116]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[117]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[118]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[119]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[120]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[121]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[122]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[123]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[124]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[125]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[126]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[127]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[128]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[129]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[130]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[131]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[65]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[66]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[67]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[68]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[69]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[70]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[71]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[72]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[73]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[74]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[75]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[76]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[77]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[78]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[79]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[80]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[81]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[82]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[83]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[84]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[85]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[86]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[87]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[88]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[89]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[90]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[91]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[92]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[93]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[94]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[95]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[96]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[97]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[98]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[99]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 130 downto 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_arbiter.grant_hot[1]_i_5\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \m_payload_i[100]_i_1\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \m_payload_i[101]_i_1\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \m_payload_i[102]_i_1\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \m_payload_i[103]_i_1\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \m_payload_i[104]_i_1\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \m_payload_i[105]_i_1\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \m_payload_i[106]_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \m_payload_i[107]_i_1\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \m_payload_i[108]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \m_payload_i[109]_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \m_payload_i[110]_i_1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \m_payload_i[111]_i_1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \m_payload_i[112]_i_1\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \m_payload_i[113]_i_1\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \m_payload_i[114]_i_1\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \m_payload_i[115]_i_1\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \m_payload_i[116]_i_1\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \m_payload_i[117]_i_1\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \m_payload_i[118]_i_1\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[119]_i_1\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \m_payload_i[120]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \m_payload_i[121]_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \m_payload_i[122]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_payload_i[123]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_payload_i[124]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[125]_i_1\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[126]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \m_payload_i[127]_i_1\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \m_payload_i[128]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \m_payload_i[129]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \m_payload_i[130]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \m_payload_i[131]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \m_payload_i[65]_i_1\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \m_payload_i[66]_i_1\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \m_payload_i[67]_i_1\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \m_payload_i[68]_i_1\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \m_payload_i[69]_i_1\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \m_payload_i[70]_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \m_payload_i[71]_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \m_payload_i[72]_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \m_payload_i[73]_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \m_payload_i[74]_i_1\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \m_payload_i[75]_i_1\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \m_payload_i[76]_i_1\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \m_payload_i[77]_i_1\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \m_payload_i[78]_i_1\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \m_payload_i[79]_i_1\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \m_payload_i[80]_i_1\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \m_payload_i[81]_i_1\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \m_payload_i[82]_i_1\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \m_payload_i[83]_i_1\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \m_payload_i[84]_i_1\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \m_payload_i[85]_i_1\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \m_payload_i[86]_i_1\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \m_payload_i[87]_i_1\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \m_payload_i[88]_i_1\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \m_payload_i[89]_i_1\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \m_payload_i[90]_i_1\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \m_payload_i[91]_i_1\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \m_payload_i[92]_i_1\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \m_payload_i[93]_i_1\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \m_payload_i[94]_i_1\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \m_payload_i[95]_i_1\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \m_payload_i[96]_i_1\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \m_payload_i[97]_i_1\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \m_payload_i[98]_i_1\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \m_payload_i[99]_i_1\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \s_axi_rdata[0]_INST_0\ : label is "soft_lutpair313";
attribute SOFT_HLUTNM of \s_axi_rdata[100]_INST_0\ : label is "soft_lutpair213";
attribute SOFT_HLUTNM of \s_axi_rdata[101]_INST_0\ : label is "soft_lutpair212";
attribute SOFT_HLUTNM of \s_axi_rdata[102]_INST_0\ : label is "soft_lutpair211";
attribute SOFT_HLUTNM of \s_axi_rdata[103]_INST_0\ : label is "soft_lutpair210";
attribute SOFT_HLUTNM of \s_axi_rdata[104]_INST_0\ : label is "soft_lutpair209";
attribute SOFT_HLUTNM of \s_axi_rdata[105]_INST_0\ : label is "soft_lutpair208";
attribute SOFT_HLUTNM of \s_axi_rdata[106]_INST_0\ : label is "soft_lutpair207";
attribute SOFT_HLUTNM of \s_axi_rdata[107]_INST_0\ : label is "soft_lutpair206";
attribute SOFT_HLUTNM of \s_axi_rdata[108]_INST_0\ : label is "soft_lutpair205";
attribute SOFT_HLUTNM of \s_axi_rdata[109]_INST_0\ : label is "soft_lutpair204";
attribute SOFT_HLUTNM of \s_axi_rdata[10]_INST_0\ : label is "soft_lutpair303";
attribute SOFT_HLUTNM of \s_axi_rdata[110]_INST_0\ : label is "soft_lutpair203";
attribute SOFT_HLUTNM of \s_axi_rdata[111]_INST_0\ : label is "soft_lutpair202";
attribute SOFT_HLUTNM of \s_axi_rdata[112]_INST_0\ : label is "soft_lutpair201";
attribute SOFT_HLUTNM of \s_axi_rdata[113]_INST_0\ : label is "soft_lutpair200";
attribute SOFT_HLUTNM of \s_axi_rdata[114]_INST_0\ : label is "soft_lutpair199";
attribute SOFT_HLUTNM of \s_axi_rdata[115]_INST_0\ : label is "soft_lutpair198";
attribute SOFT_HLUTNM of \s_axi_rdata[116]_INST_0\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \s_axi_rdata[117]_INST_0\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \s_axi_rdata[118]_INST_0\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \s_axi_rdata[119]_INST_0\ : label is "soft_lutpair194";
attribute SOFT_HLUTNM of \s_axi_rdata[11]_INST_0\ : label is "soft_lutpair302";
attribute SOFT_HLUTNM of \s_axi_rdata[120]_INST_0\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \s_axi_rdata[121]_INST_0\ : label is "soft_lutpair192";
attribute SOFT_HLUTNM of \s_axi_rdata[122]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \s_axi_rdata[123]_INST_0\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \s_axi_rdata[124]_INST_0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \s_axi_rdata[125]_INST_0\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \s_axi_rdata[126]_INST_0\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \s_axi_rdata[127]_INST_0\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \s_axi_rdata[128]_INST_0\ : label is "soft_lutpair313";
attribute SOFT_HLUTNM of \s_axi_rdata[129]_INST_0\ : label is "soft_lutpair312";
attribute SOFT_HLUTNM of \s_axi_rdata[12]_INST_0\ : label is "soft_lutpair301";
attribute SOFT_HLUTNM of \s_axi_rdata[130]_INST_0\ : label is "soft_lutpair311";
attribute SOFT_HLUTNM of \s_axi_rdata[131]_INST_0\ : label is "soft_lutpair310";
attribute SOFT_HLUTNM of \s_axi_rdata[132]_INST_0\ : label is "soft_lutpair309";
attribute SOFT_HLUTNM of \s_axi_rdata[133]_INST_0\ : label is "soft_lutpair308";
attribute SOFT_HLUTNM of \s_axi_rdata[134]_INST_0\ : label is "soft_lutpair307";
attribute SOFT_HLUTNM of \s_axi_rdata[135]_INST_0\ : label is "soft_lutpair306";
attribute SOFT_HLUTNM of \s_axi_rdata[136]_INST_0\ : label is "soft_lutpair305";
attribute SOFT_HLUTNM of \s_axi_rdata[137]_INST_0\ : label is "soft_lutpair304";
attribute SOFT_HLUTNM of \s_axi_rdata[138]_INST_0\ : label is "soft_lutpair303";
attribute SOFT_HLUTNM of \s_axi_rdata[139]_INST_0\ : label is "soft_lutpair302";
attribute SOFT_HLUTNM of \s_axi_rdata[13]_INST_0\ : label is "soft_lutpair300";
attribute SOFT_HLUTNM of \s_axi_rdata[140]_INST_0\ : label is "soft_lutpair301";
attribute SOFT_HLUTNM of \s_axi_rdata[141]_INST_0\ : label is "soft_lutpair300";
attribute SOFT_HLUTNM of \s_axi_rdata[142]_INST_0\ : label is "soft_lutpair299";
attribute SOFT_HLUTNM of \s_axi_rdata[143]_INST_0\ : label is "soft_lutpair298";
attribute SOFT_HLUTNM of \s_axi_rdata[144]_INST_0\ : label is "soft_lutpair297";
attribute SOFT_HLUTNM of \s_axi_rdata[145]_INST_0\ : label is "soft_lutpair296";
attribute SOFT_HLUTNM of \s_axi_rdata[146]_INST_0\ : label is "soft_lutpair295";
attribute SOFT_HLUTNM of \s_axi_rdata[147]_INST_0\ : label is "soft_lutpair294";
attribute SOFT_HLUTNM of \s_axi_rdata[148]_INST_0\ : label is "soft_lutpair293";
attribute SOFT_HLUTNM of \s_axi_rdata[149]_INST_0\ : label is "soft_lutpair292";
attribute SOFT_HLUTNM of \s_axi_rdata[14]_INST_0\ : label is "soft_lutpair299";
attribute SOFT_HLUTNM of \s_axi_rdata[150]_INST_0\ : label is "soft_lutpair291";
attribute SOFT_HLUTNM of \s_axi_rdata[151]_INST_0\ : label is "soft_lutpair290";
attribute SOFT_HLUTNM of \s_axi_rdata[152]_INST_0\ : label is "soft_lutpair289";
attribute SOFT_HLUTNM of \s_axi_rdata[153]_INST_0\ : label is "soft_lutpair288";
attribute SOFT_HLUTNM of \s_axi_rdata[154]_INST_0\ : label is "soft_lutpair287";
attribute SOFT_HLUTNM of \s_axi_rdata[155]_INST_0\ : label is "soft_lutpair286";
attribute SOFT_HLUTNM of \s_axi_rdata[156]_INST_0\ : label is "soft_lutpair285";
attribute SOFT_HLUTNM of \s_axi_rdata[157]_INST_0\ : label is "soft_lutpair284";
attribute SOFT_HLUTNM of \s_axi_rdata[158]_INST_0\ : label is "soft_lutpair283";
attribute SOFT_HLUTNM of \s_axi_rdata[159]_INST_0\ : label is "soft_lutpair282";
attribute SOFT_HLUTNM of \s_axi_rdata[15]_INST_0\ : label is "soft_lutpair298";
attribute SOFT_HLUTNM of \s_axi_rdata[160]_INST_0\ : label is "soft_lutpair281";
attribute SOFT_HLUTNM of \s_axi_rdata[161]_INST_0\ : label is "soft_lutpair280";
attribute SOFT_HLUTNM of \s_axi_rdata[162]_INST_0\ : label is "soft_lutpair279";
attribute SOFT_HLUTNM of \s_axi_rdata[163]_INST_0\ : label is "soft_lutpair278";
attribute SOFT_HLUTNM of \s_axi_rdata[164]_INST_0\ : label is "soft_lutpair277";
attribute SOFT_HLUTNM of \s_axi_rdata[165]_INST_0\ : label is "soft_lutpair276";
attribute SOFT_HLUTNM of \s_axi_rdata[166]_INST_0\ : label is "soft_lutpair275";
attribute SOFT_HLUTNM of \s_axi_rdata[167]_INST_0\ : label is "soft_lutpair274";
attribute SOFT_HLUTNM of \s_axi_rdata[168]_INST_0\ : label is "soft_lutpair273";
attribute SOFT_HLUTNM of \s_axi_rdata[169]_INST_0\ : label is "soft_lutpair272";
attribute SOFT_HLUTNM of \s_axi_rdata[16]_INST_0\ : label is "soft_lutpair297";
attribute SOFT_HLUTNM of \s_axi_rdata[170]_INST_0\ : label is "soft_lutpair271";
attribute SOFT_HLUTNM of \s_axi_rdata[171]_INST_0\ : label is "soft_lutpair270";
attribute SOFT_HLUTNM of \s_axi_rdata[172]_INST_0\ : label is "soft_lutpair269";
attribute SOFT_HLUTNM of \s_axi_rdata[173]_INST_0\ : label is "soft_lutpair268";
attribute SOFT_HLUTNM of \s_axi_rdata[174]_INST_0\ : label is "soft_lutpair267";
attribute SOFT_HLUTNM of \s_axi_rdata[175]_INST_0\ : label is "soft_lutpair266";
attribute SOFT_HLUTNM of \s_axi_rdata[176]_INST_0\ : label is "soft_lutpair265";
attribute SOFT_HLUTNM of \s_axi_rdata[177]_INST_0\ : label is "soft_lutpair264";
attribute SOFT_HLUTNM of \s_axi_rdata[178]_INST_0\ : label is "soft_lutpair263";
attribute SOFT_HLUTNM of \s_axi_rdata[179]_INST_0\ : label is "soft_lutpair262";
attribute SOFT_HLUTNM of \s_axi_rdata[17]_INST_0\ : label is "soft_lutpair296";
attribute SOFT_HLUTNM of \s_axi_rdata[180]_INST_0\ : label is "soft_lutpair261";
attribute SOFT_HLUTNM of \s_axi_rdata[181]_INST_0\ : label is "soft_lutpair260";
attribute SOFT_HLUTNM of \s_axi_rdata[182]_INST_0\ : label is "soft_lutpair259";
attribute SOFT_HLUTNM of \s_axi_rdata[183]_INST_0\ : label is "soft_lutpair258";
attribute SOFT_HLUTNM of \s_axi_rdata[184]_INST_0\ : label is "soft_lutpair257";
attribute SOFT_HLUTNM of \s_axi_rdata[185]_INST_0\ : label is "soft_lutpair256";
attribute SOFT_HLUTNM of \s_axi_rdata[186]_INST_0\ : label is "soft_lutpair255";
attribute SOFT_HLUTNM of \s_axi_rdata[187]_INST_0\ : label is "soft_lutpair254";
attribute SOFT_HLUTNM of \s_axi_rdata[188]_INST_0\ : label is "soft_lutpair253";
attribute SOFT_HLUTNM of \s_axi_rdata[189]_INST_0\ : label is "soft_lutpair252";
attribute SOFT_HLUTNM of \s_axi_rdata[18]_INST_0\ : label is "soft_lutpair295";
attribute SOFT_HLUTNM of \s_axi_rdata[190]_INST_0\ : label is "soft_lutpair251";
attribute SOFT_HLUTNM of \s_axi_rdata[191]_INST_0\ : label is "soft_lutpair250";
attribute SOFT_HLUTNM of \s_axi_rdata[192]_INST_0\ : label is "soft_lutpair249";
attribute SOFT_HLUTNM of \s_axi_rdata[193]_INST_0\ : label is "soft_lutpair248";
attribute SOFT_HLUTNM of \s_axi_rdata[194]_INST_0\ : label is "soft_lutpair247";
attribute SOFT_HLUTNM of \s_axi_rdata[195]_INST_0\ : label is "soft_lutpair246";
attribute SOFT_HLUTNM of \s_axi_rdata[196]_INST_0\ : label is "soft_lutpair245";
attribute SOFT_HLUTNM of \s_axi_rdata[197]_INST_0\ : label is "soft_lutpair244";
attribute SOFT_HLUTNM of \s_axi_rdata[198]_INST_0\ : label is "soft_lutpair243";
attribute SOFT_HLUTNM of \s_axi_rdata[199]_INST_0\ : label is "soft_lutpair242";
attribute SOFT_HLUTNM of \s_axi_rdata[19]_INST_0\ : label is "soft_lutpair294";
attribute SOFT_HLUTNM of \s_axi_rdata[1]_INST_0\ : label is "soft_lutpair312";
attribute SOFT_HLUTNM of \s_axi_rdata[200]_INST_0\ : label is "soft_lutpair241";
attribute SOFT_HLUTNM of \s_axi_rdata[201]_INST_0\ : label is "soft_lutpair240";
attribute SOFT_HLUTNM of \s_axi_rdata[202]_INST_0\ : label is "soft_lutpair239";
attribute SOFT_HLUTNM of \s_axi_rdata[203]_INST_0\ : label is "soft_lutpair238";
attribute SOFT_HLUTNM of \s_axi_rdata[204]_INST_0\ : label is "soft_lutpair237";
attribute SOFT_HLUTNM of \s_axi_rdata[205]_INST_0\ : label is "soft_lutpair236";
attribute SOFT_HLUTNM of \s_axi_rdata[206]_INST_0\ : label is "soft_lutpair235";
attribute SOFT_HLUTNM of \s_axi_rdata[207]_INST_0\ : label is "soft_lutpair234";
attribute SOFT_HLUTNM of \s_axi_rdata[208]_INST_0\ : label is "soft_lutpair233";
attribute SOFT_HLUTNM of \s_axi_rdata[209]_INST_0\ : label is "soft_lutpair232";
attribute SOFT_HLUTNM of \s_axi_rdata[20]_INST_0\ : label is "soft_lutpair293";
attribute SOFT_HLUTNM of \s_axi_rdata[210]_INST_0\ : label is "soft_lutpair231";
attribute SOFT_HLUTNM of \s_axi_rdata[211]_INST_0\ : label is "soft_lutpair230";
attribute SOFT_HLUTNM of \s_axi_rdata[212]_INST_0\ : label is "soft_lutpair229";
attribute SOFT_HLUTNM of \s_axi_rdata[213]_INST_0\ : label is "soft_lutpair228";
attribute SOFT_HLUTNM of \s_axi_rdata[214]_INST_0\ : label is "soft_lutpair227";
attribute SOFT_HLUTNM of \s_axi_rdata[215]_INST_0\ : label is "soft_lutpair226";
attribute SOFT_HLUTNM of \s_axi_rdata[216]_INST_0\ : label is "soft_lutpair225";
attribute SOFT_HLUTNM of \s_axi_rdata[217]_INST_0\ : label is "soft_lutpair224";
attribute SOFT_HLUTNM of \s_axi_rdata[218]_INST_0\ : label is "soft_lutpair223";
attribute SOFT_HLUTNM of \s_axi_rdata[219]_INST_0\ : label is "soft_lutpair222";
attribute SOFT_HLUTNM of \s_axi_rdata[21]_INST_0\ : label is "soft_lutpair292";
attribute SOFT_HLUTNM of \s_axi_rdata[220]_INST_0\ : label is "soft_lutpair221";
attribute SOFT_HLUTNM of \s_axi_rdata[221]_INST_0\ : label is "soft_lutpair220";
attribute SOFT_HLUTNM of \s_axi_rdata[222]_INST_0\ : label is "soft_lutpair219";
attribute SOFT_HLUTNM of \s_axi_rdata[223]_INST_0\ : label is "soft_lutpair218";
attribute SOFT_HLUTNM of \s_axi_rdata[224]_INST_0\ : label is "soft_lutpair217";
attribute SOFT_HLUTNM of \s_axi_rdata[225]_INST_0\ : label is "soft_lutpair216";
attribute SOFT_HLUTNM of \s_axi_rdata[226]_INST_0\ : label is "soft_lutpair215";
attribute SOFT_HLUTNM of \s_axi_rdata[227]_INST_0\ : label is "soft_lutpair214";
attribute SOFT_HLUTNM of \s_axi_rdata[228]_INST_0\ : label is "soft_lutpair213";
attribute SOFT_HLUTNM of \s_axi_rdata[229]_INST_0\ : label is "soft_lutpair212";
attribute SOFT_HLUTNM of \s_axi_rdata[22]_INST_0\ : label is "soft_lutpair291";
attribute SOFT_HLUTNM of \s_axi_rdata[230]_INST_0\ : label is "soft_lutpair211";
attribute SOFT_HLUTNM of \s_axi_rdata[231]_INST_0\ : label is "soft_lutpair210";
attribute SOFT_HLUTNM of \s_axi_rdata[232]_INST_0\ : label is "soft_lutpair209";
attribute SOFT_HLUTNM of \s_axi_rdata[233]_INST_0\ : label is "soft_lutpair208";
attribute SOFT_HLUTNM of \s_axi_rdata[234]_INST_0\ : label is "soft_lutpair207";
attribute SOFT_HLUTNM of \s_axi_rdata[235]_INST_0\ : label is "soft_lutpair206";
attribute SOFT_HLUTNM of \s_axi_rdata[236]_INST_0\ : label is "soft_lutpair205";
attribute SOFT_HLUTNM of \s_axi_rdata[237]_INST_0\ : label is "soft_lutpair204";
attribute SOFT_HLUTNM of \s_axi_rdata[238]_INST_0\ : label is "soft_lutpair203";
attribute SOFT_HLUTNM of \s_axi_rdata[239]_INST_0\ : label is "soft_lutpair202";
attribute SOFT_HLUTNM of \s_axi_rdata[23]_INST_0\ : label is "soft_lutpair290";
attribute SOFT_HLUTNM of \s_axi_rdata[240]_INST_0\ : label is "soft_lutpair201";
attribute SOFT_HLUTNM of \s_axi_rdata[241]_INST_0\ : label is "soft_lutpair200";
attribute SOFT_HLUTNM of \s_axi_rdata[242]_INST_0\ : label is "soft_lutpair199";
attribute SOFT_HLUTNM of \s_axi_rdata[243]_INST_0\ : label is "soft_lutpair198";
attribute SOFT_HLUTNM of \s_axi_rdata[244]_INST_0\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \s_axi_rdata[245]_INST_0\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \s_axi_rdata[246]_INST_0\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \s_axi_rdata[247]_INST_0\ : label is "soft_lutpair194";
attribute SOFT_HLUTNM of \s_axi_rdata[248]_INST_0\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \s_axi_rdata[249]_INST_0\ : label is "soft_lutpair192";
attribute SOFT_HLUTNM of \s_axi_rdata[24]_INST_0\ : label is "soft_lutpair289";
attribute SOFT_HLUTNM of \s_axi_rdata[250]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \s_axi_rdata[251]_INST_0\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \s_axi_rdata[252]_INST_0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \s_axi_rdata[253]_INST_0\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \s_axi_rdata[254]_INST_0\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \s_axi_rdata[255]_INST_0\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \s_axi_rdata[25]_INST_0\ : label is "soft_lutpair288";
attribute SOFT_HLUTNM of \s_axi_rdata[26]_INST_0\ : label is "soft_lutpair287";
attribute SOFT_HLUTNM of \s_axi_rdata[27]_INST_0\ : label is "soft_lutpair286";
attribute SOFT_HLUTNM of \s_axi_rdata[28]_INST_0\ : label is "soft_lutpair285";
attribute SOFT_HLUTNM of \s_axi_rdata[29]_INST_0\ : label is "soft_lutpair284";
attribute SOFT_HLUTNM of \s_axi_rdata[2]_INST_0\ : label is "soft_lutpair311";
attribute SOFT_HLUTNM of \s_axi_rdata[30]_INST_0\ : label is "soft_lutpair283";
attribute SOFT_HLUTNM of \s_axi_rdata[31]_INST_0\ : label is "soft_lutpair282";
attribute SOFT_HLUTNM of \s_axi_rdata[32]_INST_0\ : label is "soft_lutpair281";
attribute SOFT_HLUTNM of \s_axi_rdata[33]_INST_0\ : label is "soft_lutpair280";
attribute SOFT_HLUTNM of \s_axi_rdata[34]_INST_0\ : label is "soft_lutpair279";
attribute SOFT_HLUTNM of \s_axi_rdata[35]_INST_0\ : label is "soft_lutpair278";
attribute SOFT_HLUTNM of \s_axi_rdata[36]_INST_0\ : label is "soft_lutpair277";
attribute SOFT_HLUTNM of \s_axi_rdata[37]_INST_0\ : label is "soft_lutpair276";
attribute SOFT_HLUTNM of \s_axi_rdata[38]_INST_0\ : label is "soft_lutpair275";
attribute SOFT_HLUTNM of \s_axi_rdata[39]_INST_0\ : label is "soft_lutpair274";
attribute SOFT_HLUTNM of \s_axi_rdata[3]_INST_0\ : label is "soft_lutpair310";
attribute SOFT_HLUTNM of \s_axi_rdata[40]_INST_0\ : label is "soft_lutpair273";
attribute SOFT_HLUTNM of \s_axi_rdata[41]_INST_0\ : label is "soft_lutpair272";
attribute SOFT_HLUTNM of \s_axi_rdata[42]_INST_0\ : label is "soft_lutpair271";
attribute SOFT_HLUTNM of \s_axi_rdata[43]_INST_0\ : label is "soft_lutpair270";
attribute SOFT_HLUTNM of \s_axi_rdata[44]_INST_0\ : label is "soft_lutpair269";
attribute SOFT_HLUTNM of \s_axi_rdata[45]_INST_0\ : label is "soft_lutpair268";
attribute SOFT_HLUTNM of \s_axi_rdata[46]_INST_0\ : label is "soft_lutpair267";
attribute SOFT_HLUTNM of \s_axi_rdata[47]_INST_0\ : label is "soft_lutpair266";
attribute SOFT_HLUTNM of \s_axi_rdata[48]_INST_0\ : label is "soft_lutpair265";
attribute SOFT_HLUTNM of \s_axi_rdata[49]_INST_0\ : label is "soft_lutpair264";
attribute SOFT_HLUTNM of \s_axi_rdata[4]_INST_0\ : label is "soft_lutpair309";
attribute SOFT_HLUTNM of \s_axi_rdata[50]_INST_0\ : label is "soft_lutpair263";
attribute SOFT_HLUTNM of \s_axi_rdata[51]_INST_0\ : label is "soft_lutpair262";
attribute SOFT_HLUTNM of \s_axi_rdata[52]_INST_0\ : label is "soft_lutpair261";
attribute SOFT_HLUTNM of \s_axi_rdata[53]_INST_0\ : label is "soft_lutpair260";
attribute SOFT_HLUTNM of \s_axi_rdata[54]_INST_0\ : label is "soft_lutpair259";
attribute SOFT_HLUTNM of \s_axi_rdata[55]_INST_0\ : label is "soft_lutpair258";
attribute SOFT_HLUTNM of \s_axi_rdata[56]_INST_0\ : label is "soft_lutpair257";
attribute SOFT_HLUTNM of \s_axi_rdata[57]_INST_0\ : label is "soft_lutpair256";
attribute SOFT_HLUTNM of \s_axi_rdata[58]_INST_0\ : label is "soft_lutpair255";
attribute SOFT_HLUTNM of \s_axi_rdata[59]_INST_0\ : label is "soft_lutpair254";
attribute SOFT_HLUTNM of \s_axi_rdata[5]_INST_0\ : label is "soft_lutpair308";
attribute SOFT_HLUTNM of \s_axi_rdata[60]_INST_0\ : label is "soft_lutpair253";
attribute SOFT_HLUTNM of \s_axi_rdata[61]_INST_0\ : label is "soft_lutpair252";
attribute SOFT_HLUTNM of \s_axi_rdata[62]_INST_0\ : label is "soft_lutpair251";
attribute SOFT_HLUTNM of \s_axi_rdata[63]_INST_0\ : label is "soft_lutpair250";
attribute SOFT_HLUTNM of \s_axi_rdata[64]_INST_0\ : label is "soft_lutpair249";
attribute SOFT_HLUTNM of \s_axi_rdata[65]_INST_0\ : label is "soft_lutpair248";
attribute SOFT_HLUTNM of \s_axi_rdata[66]_INST_0\ : label is "soft_lutpair247";
attribute SOFT_HLUTNM of \s_axi_rdata[67]_INST_0\ : label is "soft_lutpair246";
attribute SOFT_HLUTNM of \s_axi_rdata[68]_INST_0\ : label is "soft_lutpair245";
attribute SOFT_HLUTNM of \s_axi_rdata[69]_INST_0\ : label is "soft_lutpair244";
attribute SOFT_HLUTNM of \s_axi_rdata[6]_INST_0\ : label is "soft_lutpair307";
attribute SOFT_HLUTNM of \s_axi_rdata[70]_INST_0\ : label is "soft_lutpair243";
attribute SOFT_HLUTNM of \s_axi_rdata[71]_INST_0\ : label is "soft_lutpair242";
attribute SOFT_HLUTNM of \s_axi_rdata[72]_INST_0\ : label is "soft_lutpair241";
attribute SOFT_HLUTNM of \s_axi_rdata[73]_INST_0\ : label is "soft_lutpair240";
attribute SOFT_HLUTNM of \s_axi_rdata[74]_INST_0\ : label is "soft_lutpair239";
attribute SOFT_HLUTNM of \s_axi_rdata[75]_INST_0\ : label is "soft_lutpair238";
attribute SOFT_HLUTNM of \s_axi_rdata[76]_INST_0\ : label is "soft_lutpair237";
attribute SOFT_HLUTNM of \s_axi_rdata[77]_INST_0\ : label is "soft_lutpair236";
attribute SOFT_HLUTNM of \s_axi_rdata[78]_INST_0\ : label is "soft_lutpair235";
attribute SOFT_HLUTNM of \s_axi_rdata[79]_INST_0\ : label is "soft_lutpair234";
attribute SOFT_HLUTNM of \s_axi_rdata[7]_INST_0\ : label is "soft_lutpair306";
attribute SOFT_HLUTNM of \s_axi_rdata[80]_INST_0\ : label is "soft_lutpair233";
attribute SOFT_HLUTNM of \s_axi_rdata[81]_INST_0\ : label is "soft_lutpair232";
attribute SOFT_HLUTNM of \s_axi_rdata[82]_INST_0\ : label is "soft_lutpair231";
attribute SOFT_HLUTNM of \s_axi_rdata[83]_INST_0\ : label is "soft_lutpair230";
attribute SOFT_HLUTNM of \s_axi_rdata[84]_INST_0\ : label is "soft_lutpair229";
attribute SOFT_HLUTNM of \s_axi_rdata[85]_INST_0\ : label is "soft_lutpair228";
attribute SOFT_HLUTNM of \s_axi_rdata[86]_INST_0\ : label is "soft_lutpair227";
attribute SOFT_HLUTNM of \s_axi_rdata[87]_INST_0\ : label is "soft_lutpair226";
attribute SOFT_HLUTNM of \s_axi_rdata[88]_INST_0\ : label is "soft_lutpair225";
attribute SOFT_HLUTNM of \s_axi_rdata[89]_INST_0\ : label is "soft_lutpair224";
attribute SOFT_HLUTNM of \s_axi_rdata[8]_INST_0\ : label is "soft_lutpair305";
attribute SOFT_HLUTNM of \s_axi_rdata[90]_INST_0\ : label is "soft_lutpair223";
attribute SOFT_HLUTNM of \s_axi_rdata[91]_INST_0\ : label is "soft_lutpair222";
attribute SOFT_HLUTNM of \s_axi_rdata[92]_INST_0\ : label is "soft_lutpair221";
attribute SOFT_HLUTNM of \s_axi_rdata[93]_INST_0\ : label is "soft_lutpair220";
attribute SOFT_HLUTNM of \s_axi_rdata[94]_INST_0\ : label is "soft_lutpair219";
attribute SOFT_HLUTNM of \s_axi_rdata[95]_INST_0\ : label is "soft_lutpair218";
attribute SOFT_HLUTNM of \s_axi_rdata[96]_INST_0\ : label is "soft_lutpair217";
attribute SOFT_HLUTNM of \s_axi_rdata[97]_INST_0\ : label is "soft_lutpair216";
attribute SOFT_HLUTNM of \s_axi_rdata[98]_INST_0\ : label is "soft_lutpair215";
attribute SOFT_HLUTNM of \s_axi_rdata[99]_INST_0\ : label is "soft_lutpair214";
attribute SOFT_HLUTNM of \s_axi_rdata[9]_INST_0\ : label is "soft_lutpair304";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ <= \^gen_master_slots[0].r_issuing_cnt_reg[0]_0\;
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\gen_arbiter.grant_hot[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007F00"
)
port map (
I0 => \gen_single_thread.active_target_hot_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => \^q\(2),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I4 => \gen_master_slots[0].r_issuing_cnt_reg[0]_1\,
O => \gen_arbiter.grant_hot_reg[0]\
);
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9999999999999998"
)
port map (
I0 => \^gen_master_slots[0].r_issuing_cnt_reg[0]_0\,
I1 => \gen_arbiter.m_target_hot_i_reg[0]\,
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I4 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
I5 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
O => \gen_master_slots[0].r_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^q\(2),
I1 => \^m_payload_i_reg[0]_0\,
I2 => \gen_single_thread.active_target_hot_reg[0]\,
O => \^gen_master_slots[0].r_issuing_cnt_reg[0]_0\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[100]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(100),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[100]\,
O => skid_buffer(100)
);
\m_payload_i[101]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(101),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[101]\,
O => skid_buffer(101)
);
\m_payload_i[102]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(102),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[102]\,
O => skid_buffer(102)
);
\m_payload_i[103]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(103),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[103]\,
O => skid_buffer(103)
);
\m_payload_i[104]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(104),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[104]\,
O => skid_buffer(104)
);
\m_payload_i[105]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(105),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[105]\,
O => skid_buffer(105)
);
\m_payload_i[106]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(106),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[106]\,
O => skid_buffer(106)
);
\m_payload_i[107]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(107),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[107]\,
O => skid_buffer(107)
);
\m_payload_i[108]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(108),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[108]\,
O => skid_buffer(108)
);
\m_payload_i[109]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(109),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[109]\,
O => skid_buffer(109)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[110]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(110),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[110]\,
O => skid_buffer(110)
);
\m_payload_i[111]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(111),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[111]\,
O => skid_buffer(111)
);
\m_payload_i[112]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(112),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[112]\,
O => skid_buffer(112)
);
\m_payload_i[113]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(113),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[113]\,
O => skid_buffer(113)
);
\m_payload_i[114]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(114),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[114]\,
O => skid_buffer(114)
);
\m_payload_i[115]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(115),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[115]\,
O => skid_buffer(115)
);
\m_payload_i[116]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(116),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[116]\,
O => skid_buffer(116)
);
\m_payload_i[117]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(117),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[117]\,
O => skid_buffer(117)
);
\m_payload_i[118]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(118),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[118]\,
O => skid_buffer(118)
);
\m_payload_i[119]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(119),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[119]\,
O => skid_buffer(119)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[120]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(120),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[120]\,
O => skid_buffer(120)
);
\m_payload_i[121]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(121),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[121]\,
O => skid_buffer(121)
);
\m_payload_i[122]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(122),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[122]\,
O => skid_buffer(122)
);
\m_payload_i[123]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(123),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[123]\,
O => skid_buffer(123)
);
\m_payload_i[124]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(124),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[124]\,
O => skid_buffer(124)
);
\m_payload_i[125]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(125),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[125]\,
O => skid_buffer(125)
);
\m_payload_i[126]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(126),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[126]\,
O => skid_buffer(126)
);
\m_payload_i[127]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(127),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[127]\,
O => skid_buffer(127)
);
\m_payload_i[128]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[128]\,
O => skid_buffer(128)
);
\m_payload_i[129]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[129]\,
O => skid_buffer(129)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[130]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[130]\,
O => skid_buffer(130)
);
\m_payload_i[131]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0880088FFFFFFFF"
)
port map (
I0 => active_target_hot_2(0),
I1 => s_axi_rready(0),
I2 => active_target_hot_3(0),
I3 => \^q\(3),
I4 => s_axi_rready(1),
I5 => \^m_payload_i_reg[0]_0\,
O => p_1_in_0
);
\m_payload_i[131]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[131]\,
O => skid_buffer(131)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(32),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(33),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(34),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(35),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(36),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(37),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(38),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(39),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(40),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(41),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(42),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(43),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(44),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(45),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(46),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(47),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(48),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(49),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(50),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(51),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[52]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(52),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[52]\,
O => skid_buffer(52)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(53),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(54),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(55),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(56),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(57),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(58),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(59),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(60),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(61),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(62),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(63),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(64),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[65]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(65),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[65]\,
O => skid_buffer(65)
);
\m_payload_i[66]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(66),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[66]\,
O => skid_buffer(66)
);
\m_payload_i[67]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(67),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[67]\,
O => skid_buffer(67)
);
\m_payload_i[68]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(68),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[68]\,
O => skid_buffer(68)
);
\m_payload_i[69]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(69),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[69]\,
O => skid_buffer(69)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[70]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(70),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[70]\,
O => skid_buffer(70)
);
\m_payload_i[71]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(71),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[71]\,
O => skid_buffer(71)
);
\m_payload_i[72]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(72),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[72]\,
O => skid_buffer(72)
);
\m_payload_i[73]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(73),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[73]\,
O => skid_buffer(73)
);
\m_payload_i[74]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(74),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[74]\,
O => skid_buffer(74)
);
\m_payload_i[75]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(75),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[75]\,
O => skid_buffer(75)
);
\m_payload_i[76]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(76),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[76]\,
O => skid_buffer(76)
);
\m_payload_i[77]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(77),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[77]\,
O => skid_buffer(77)
);
\m_payload_i[78]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(78),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[78]\,
O => skid_buffer(78)
);
\m_payload_i[79]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(79),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[79]\,
O => skid_buffer(79)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[80]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(80),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[80]\,
O => skid_buffer(80)
);
\m_payload_i[81]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(81),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[81]\,
O => skid_buffer(81)
);
\m_payload_i[82]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(82),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[82]\,
O => skid_buffer(82)
);
\m_payload_i[83]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(83),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[83]\,
O => skid_buffer(83)
);
\m_payload_i[84]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(84),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[84]\,
O => skid_buffer(84)
);
\m_payload_i[85]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(85),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[85]\,
O => skid_buffer(85)
);
\m_payload_i[86]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(86),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[86]\,
O => skid_buffer(86)
);
\m_payload_i[87]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(87),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[87]\,
O => skid_buffer(87)
);
\m_payload_i[88]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(88),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[88]\,
O => skid_buffer(88)
);
\m_payload_i[89]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(89),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[89]\,
O => skid_buffer(89)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[90]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(90),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[90]\,
O => skid_buffer(90)
);
\m_payload_i[91]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(91),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[91]\,
O => skid_buffer(91)
);
\m_payload_i[92]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(92),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[92]\,
O => skid_buffer(92)
);
\m_payload_i[93]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(93),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[93]\,
O => skid_buffer(93)
);
\m_payload_i[94]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(94),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[94]\,
O => skid_buffer(94)
);
\m_payload_i[95]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(95),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[95]\,
O => skid_buffer(95)
);
\m_payload_i[96]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(96),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[96]\,
O => skid_buffer(96)
);
\m_payload_i[97]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(97),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[97]\,
O => skid_buffer(97)
);
\m_payload_i[98]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(98),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[98]\,
O => skid_buffer(98)
);
\m_payload_i[99]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(99),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[99]\,
O => skid_buffer(99)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(0),
Q => st_mr_rmesg(3),
R => '0'
);
\m_payload_i_reg[100]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(100),
Q => st_mr_rmesg(103),
R => '0'
);
\m_payload_i_reg[101]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(101),
Q => st_mr_rmesg(104),
R => '0'
);
\m_payload_i_reg[102]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(102),
Q => st_mr_rmesg(105),
R => '0'
);
\m_payload_i_reg[103]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(103),
Q => st_mr_rmesg(106),
R => '0'
);
\m_payload_i_reg[104]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(104),
Q => st_mr_rmesg(107),
R => '0'
);
\m_payload_i_reg[105]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(105),
Q => st_mr_rmesg(108),
R => '0'
);
\m_payload_i_reg[106]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(106),
Q => st_mr_rmesg(109),
R => '0'
);
\m_payload_i_reg[107]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(107),
Q => st_mr_rmesg(110),
R => '0'
);
\m_payload_i_reg[108]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(108),
Q => st_mr_rmesg(111),
R => '0'
);
\m_payload_i_reg[109]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(109),
Q => st_mr_rmesg(112),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(10),
Q => st_mr_rmesg(13),
R => '0'
);
\m_payload_i_reg[110]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(110),
Q => st_mr_rmesg(113),
R => '0'
);
\m_payload_i_reg[111]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(111),
Q => st_mr_rmesg(114),
R => '0'
);
\m_payload_i_reg[112]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(112),
Q => st_mr_rmesg(115),
R => '0'
);
\m_payload_i_reg[113]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(113),
Q => st_mr_rmesg(116),
R => '0'
);
\m_payload_i_reg[114]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(114),
Q => st_mr_rmesg(117),
R => '0'
);
\m_payload_i_reg[115]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(115),
Q => st_mr_rmesg(118),
R => '0'
);
\m_payload_i_reg[116]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(116),
Q => st_mr_rmesg(119),
R => '0'
);
\m_payload_i_reg[117]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(117),
Q => st_mr_rmesg(120),
R => '0'
);
\m_payload_i_reg[118]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(118),
Q => st_mr_rmesg(121),
R => '0'
);
\m_payload_i_reg[119]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(119),
Q => st_mr_rmesg(122),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(11),
Q => st_mr_rmesg(14),
R => '0'
);
\m_payload_i_reg[120]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(120),
Q => st_mr_rmesg(123),
R => '0'
);
\m_payload_i_reg[121]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(121),
Q => st_mr_rmesg(124),
R => '0'
);
\m_payload_i_reg[122]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(122),
Q => st_mr_rmesg(125),
R => '0'
);
\m_payload_i_reg[123]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(123),
Q => st_mr_rmesg(126),
R => '0'
);
\m_payload_i_reg[124]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(124),
Q => st_mr_rmesg(127),
R => '0'
);
\m_payload_i_reg[125]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(125),
Q => st_mr_rmesg(128),
R => '0'
);
\m_payload_i_reg[126]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(126),
Q => st_mr_rmesg(129),
R => '0'
);
\m_payload_i_reg[127]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(127),
Q => st_mr_rmesg(130),
R => '0'
);
\m_payload_i_reg[128]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(128),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[129]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(129),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(12),
Q => st_mr_rmesg(15),
R => '0'
);
\m_payload_i_reg[130]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(130),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[131]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(131),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(13),
Q => st_mr_rmesg(16),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(14),
Q => st_mr_rmesg(17),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(15),
Q => st_mr_rmesg(18),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(16),
Q => st_mr_rmesg(19),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(17),
Q => st_mr_rmesg(20),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(18),
Q => st_mr_rmesg(21),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(19),
Q => st_mr_rmesg(22),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(1),
Q => st_mr_rmesg(4),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(20),
Q => st_mr_rmesg(23),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(21),
Q => st_mr_rmesg(24),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(22),
Q => st_mr_rmesg(25),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(23),
Q => st_mr_rmesg(26),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(24),
Q => st_mr_rmesg(27),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(25),
Q => st_mr_rmesg(28),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(26),
Q => st_mr_rmesg(29),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(27),
Q => st_mr_rmesg(30),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(28),
Q => st_mr_rmesg(31),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(29),
Q => st_mr_rmesg(32),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(2),
Q => st_mr_rmesg(5),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(30),
Q => st_mr_rmesg(33),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(31),
Q => st_mr_rmesg(34),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(32),
Q => st_mr_rmesg(35),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(33),
Q => st_mr_rmesg(36),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(34),
Q => st_mr_rmesg(37),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(35),
Q => st_mr_rmesg(38),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(36),
Q => st_mr_rmesg(39),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(37),
Q => st_mr_rmesg(40),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(38),
Q => st_mr_rmesg(41),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(39),
Q => st_mr_rmesg(42),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(3),
Q => st_mr_rmesg(6),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(40),
Q => st_mr_rmesg(43),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(41),
Q => st_mr_rmesg(44),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(42),
Q => st_mr_rmesg(45),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(43),
Q => st_mr_rmesg(46),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(44),
Q => st_mr_rmesg(47),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(45),
Q => st_mr_rmesg(48),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(46),
Q => st_mr_rmesg(49),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(47),
Q => st_mr_rmesg(50),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(48),
Q => st_mr_rmesg(51),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(49),
Q => st_mr_rmesg(52),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(4),
Q => st_mr_rmesg(7),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(50),
Q => st_mr_rmesg(53),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(51),
Q => st_mr_rmesg(54),
R => '0'
);
\m_payload_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(52),
Q => st_mr_rmesg(55),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(53),
Q => st_mr_rmesg(56),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(54),
Q => st_mr_rmesg(57),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(55),
Q => st_mr_rmesg(58),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(56),
Q => st_mr_rmesg(59),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(57),
Q => st_mr_rmesg(60),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(58),
Q => st_mr_rmesg(61),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(59),
Q => st_mr_rmesg(62),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(5),
Q => st_mr_rmesg(8),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(60),
Q => st_mr_rmesg(63),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(61),
Q => st_mr_rmesg(64),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(62),
Q => st_mr_rmesg(65),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(63),
Q => st_mr_rmesg(66),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(64),
Q => st_mr_rmesg(67),
R => '0'
);
\m_payload_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(65),
Q => st_mr_rmesg(68),
R => '0'
);
\m_payload_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(66),
Q => st_mr_rmesg(69),
R => '0'
);
\m_payload_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(67),
Q => st_mr_rmesg(70),
R => '0'
);
\m_payload_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(68),
Q => st_mr_rmesg(71),
R => '0'
);
\m_payload_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(69),
Q => st_mr_rmesg(72),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(6),
Q => st_mr_rmesg(9),
R => '0'
);
\m_payload_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(70),
Q => st_mr_rmesg(73),
R => '0'
);
\m_payload_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(71),
Q => st_mr_rmesg(74),
R => '0'
);
\m_payload_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(72),
Q => st_mr_rmesg(75),
R => '0'
);
\m_payload_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(73),
Q => st_mr_rmesg(76),
R => '0'
);
\m_payload_i_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(74),
Q => st_mr_rmesg(77),
R => '0'
);
\m_payload_i_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(75),
Q => st_mr_rmesg(78),
R => '0'
);
\m_payload_i_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(76),
Q => st_mr_rmesg(79),
R => '0'
);
\m_payload_i_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(77),
Q => st_mr_rmesg(80),
R => '0'
);
\m_payload_i_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(78),
Q => st_mr_rmesg(81),
R => '0'
);
\m_payload_i_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(79),
Q => st_mr_rmesg(82),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(7),
Q => st_mr_rmesg(10),
R => '0'
);
\m_payload_i_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(80),
Q => st_mr_rmesg(83),
R => '0'
);
\m_payload_i_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(81),
Q => st_mr_rmesg(84),
R => '0'
);
\m_payload_i_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(82),
Q => st_mr_rmesg(85),
R => '0'
);
\m_payload_i_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(83),
Q => st_mr_rmesg(86),
R => '0'
);
\m_payload_i_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(84),
Q => st_mr_rmesg(87),
R => '0'
);
\m_payload_i_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(85),
Q => st_mr_rmesg(88),
R => '0'
);
\m_payload_i_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(86),
Q => st_mr_rmesg(89),
R => '0'
);
\m_payload_i_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(87),
Q => st_mr_rmesg(90),
R => '0'
);
\m_payload_i_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(88),
Q => st_mr_rmesg(91),
R => '0'
);
\m_payload_i_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(89),
Q => st_mr_rmesg(92),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(8),
Q => st_mr_rmesg(11),
R => '0'
);
\m_payload_i_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(90),
Q => st_mr_rmesg(93),
R => '0'
);
\m_payload_i_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(91),
Q => st_mr_rmesg(94),
R => '0'
);
\m_payload_i_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(92),
Q => st_mr_rmesg(95),
R => '0'
);
\m_payload_i_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(93),
Q => st_mr_rmesg(96),
R => '0'
);
\m_payload_i_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(94),
Q => st_mr_rmesg(97),
R => '0'
);
\m_payload_i_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(95),
Q => st_mr_rmesg(98),
R => '0'
);
\m_payload_i_reg[96]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(96),
Q => st_mr_rmesg(99),
R => '0'
);
\m_payload_i_reg[97]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(97),
Q => st_mr_rmesg(100),
R => '0'
);
\m_payload_i_reg[98]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(98),
Q => st_mr_rmesg(101),
R => '0'
);
\m_payload_i_reg[99]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(99),
Q => st_mr_rmesg(102),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in_0,
D => skid_buffer(9),
Q => st_mr_rmesg(12),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => s_ready_i_i_2_n_0,
I1 => m_axi_rvalid(0),
I2 => \^m_axi_rready[0]\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_axi_rdata[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(3),
I1 => active_target_enc_0,
O => s_axi_rdata(0)
);
\s_axi_rdata[100]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(103),
I1 => active_target_enc_0,
O => s_axi_rdata(100)
);
\s_axi_rdata[101]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(104),
I1 => active_target_enc_0,
O => s_axi_rdata(101)
);
\s_axi_rdata[102]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(105),
I1 => active_target_enc_0,
O => s_axi_rdata(102)
);
\s_axi_rdata[103]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(106),
I1 => active_target_enc_0,
O => s_axi_rdata(103)
);
\s_axi_rdata[104]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(107),
I1 => active_target_enc_0,
O => s_axi_rdata(104)
);
\s_axi_rdata[105]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(108),
I1 => active_target_enc_0,
O => s_axi_rdata(105)
);
\s_axi_rdata[106]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(109),
I1 => active_target_enc_0,
O => s_axi_rdata(106)
);
\s_axi_rdata[107]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(110),
I1 => active_target_enc_0,
O => s_axi_rdata(107)
);
\s_axi_rdata[108]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(111),
I1 => active_target_enc_0,
O => s_axi_rdata(108)
);
\s_axi_rdata[109]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(112),
I1 => active_target_enc_0,
O => s_axi_rdata(109)
);
\s_axi_rdata[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(13),
I1 => active_target_enc_0,
O => s_axi_rdata(10)
);
\s_axi_rdata[110]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(113),
I1 => active_target_enc_0,
O => s_axi_rdata(110)
);
\s_axi_rdata[111]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(114),
I1 => active_target_enc_0,
O => s_axi_rdata(111)
);
\s_axi_rdata[112]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(115),
I1 => active_target_enc_0,
O => s_axi_rdata(112)
);
\s_axi_rdata[113]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(116),
I1 => active_target_enc_0,
O => s_axi_rdata(113)
);
\s_axi_rdata[114]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(117),
I1 => active_target_enc_0,
O => s_axi_rdata(114)
);
\s_axi_rdata[115]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(118),
I1 => active_target_enc_0,
O => s_axi_rdata(115)
);
\s_axi_rdata[116]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(119),
I1 => active_target_enc_0,
O => s_axi_rdata(116)
);
\s_axi_rdata[117]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(120),
I1 => active_target_enc_0,
O => s_axi_rdata(117)
);
\s_axi_rdata[118]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(121),
I1 => active_target_enc_0,
O => s_axi_rdata(118)
);
\s_axi_rdata[119]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(122),
I1 => active_target_enc_0,
O => s_axi_rdata(119)
);
\s_axi_rdata[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(14),
I1 => active_target_enc_0,
O => s_axi_rdata(11)
);
\s_axi_rdata[120]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(123),
I1 => active_target_enc_0,
O => s_axi_rdata(120)
);
\s_axi_rdata[121]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(124),
I1 => active_target_enc_0,
O => s_axi_rdata(121)
);
\s_axi_rdata[122]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(125),
I1 => active_target_enc_0,
O => s_axi_rdata(122)
);
\s_axi_rdata[123]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(126),
I1 => active_target_enc_0,
O => s_axi_rdata(123)
);
\s_axi_rdata[124]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(127),
I1 => active_target_enc_0,
O => s_axi_rdata(124)
);
\s_axi_rdata[125]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(128),
I1 => active_target_enc_0,
O => s_axi_rdata(125)
);
\s_axi_rdata[126]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(129),
I1 => active_target_enc_0,
O => s_axi_rdata(126)
);
\s_axi_rdata[127]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(130),
I1 => active_target_enc_0,
O => s_axi_rdata(127)
);
\s_axi_rdata[128]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(3),
I1 => active_target_enc,
O => s_axi_rdata(128)
);
\s_axi_rdata[129]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(4),
I1 => active_target_enc,
O => s_axi_rdata(129)
);
\s_axi_rdata[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(15),
I1 => active_target_enc_0,
O => s_axi_rdata(12)
);
\s_axi_rdata[130]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(5),
I1 => active_target_enc,
O => s_axi_rdata(130)
);
\s_axi_rdata[131]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(6),
I1 => active_target_enc,
O => s_axi_rdata(131)
);
\s_axi_rdata[132]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(7),
I1 => active_target_enc,
O => s_axi_rdata(132)
);
\s_axi_rdata[133]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(8),
I1 => active_target_enc,
O => s_axi_rdata(133)
);
\s_axi_rdata[134]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(9),
I1 => active_target_enc,
O => s_axi_rdata(134)
);
\s_axi_rdata[135]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(10),
I1 => active_target_enc,
O => s_axi_rdata(135)
);
\s_axi_rdata[136]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(11),
I1 => active_target_enc,
O => s_axi_rdata(136)
);
\s_axi_rdata[137]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(12),
I1 => active_target_enc,
O => s_axi_rdata(137)
);
\s_axi_rdata[138]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(13),
I1 => active_target_enc,
O => s_axi_rdata(138)
);
\s_axi_rdata[139]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(14),
I1 => active_target_enc,
O => s_axi_rdata(139)
);
\s_axi_rdata[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(16),
I1 => active_target_enc_0,
O => s_axi_rdata(13)
);
\s_axi_rdata[140]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(15),
I1 => active_target_enc,
O => s_axi_rdata(140)
);
\s_axi_rdata[141]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(16),
I1 => active_target_enc,
O => s_axi_rdata(141)
);
\s_axi_rdata[142]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(17),
I1 => active_target_enc,
O => s_axi_rdata(142)
);
\s_axi_rdata[143]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(18),
I1 => active_target_enc,
O => s_axi_rdata(143)
);
\s_axi_rdata[144]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(19),
I1 => active_target_enc,
O => s_axi_rdata(144)
);
\s_axi_rdata[145]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(20),
I1 => active_target_enc,
O => s_axi_rdata(145)
);
\s_axi_rdata[146]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(21),
I1 => active_target_enc,
O => s_axi_rdata(146)
);
\s_axi_rdata[147]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(22),
I1 => active_target_enc,
O => s_axi_rdata(147)
);
\s_axi_rdata[148]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(23),
I1 => active_target_enc,
O => s_axi_rdata(148)
);
\s_axi_rdata[149]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(24),
I1 => active_target_enc,
O => s_axi_rdata(149)
);
\s_axi_rdata[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(17),
I1 => active_target_enc_0,
O => s_axi_rdata(14)
);
\s_axi_rdata[150]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(25),
I1 => active_target_enc,
O => s_axi_rdata(150)
);
\s_axi_rdata[151]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(26),
I1 => active_target_enc,
O => s_axi_rdata(151)
);
\s_axi_rdata[152]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(27),
I1 => active_target_enc,
O => s_axi_rdata(152)
);
\s_axi_rdata[153]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(28),
I1 => active_target_enc,
O => s_axi_rdata(153)
);
\s_axi_rdata[154]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(29),
I1 => active_target_enc,
O => s_axi_rdata(154)
);
\s_axi_rdata[155]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(30),
I1 => active_target_enc,
O => s_axi_rdata(155)
);
\s_axi_rdata[156]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(31),
I1 => active_target_enc,
O => s_axi_rdata(156)
);
\s_axi_rdata[157]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(32),
I1 => active_target_enc,
O => s_axi_rdata(157)
);
\s_axi_rdata[158]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(33),
I1 => active_target_enc,
O => s_axi_rdata(158)
);
\s_axi_rdata[159]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(34),
I1 => active_target_enc,
O => s_axi_rdata(159)
);
\s_axi_rdata[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(18),
I1 => active_target_enc_0,
O => s_axi_rdata(15)
);
\s_axi_rdata[160]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(35),
I1 => active_target_enc,
O => s_axi_rdata(160)
);
\s_axi_rdata[161]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(36),
I1 => active_target_enc,
O => s_axi_rdata(161)
);
\s_axi_rdata[162]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(37),
I1 => active_target_enc,
O => s_axi_rdata(162)
);
\s_axi_rdata[163]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(38),
I1 => active_target_enc,
O => s_axi_rdata(163)
);
\s_axi_rdata[164]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(39),
I1 => active_target_enc,
O => s_axi_rdata(164)
);
\s_axi_rdata[165]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(40),
I1 => active_target_enc,
O => s_axi_rdata(165)
);
\s_axi_rdata[166]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(41),
I1 => active_target_enc,
O => s_axi_rdata(166)
);
\s_axi_rdata[167]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(42),
I1 => active_target_enc,
O => s_axi_rdata(167)
);
\s_axi_rdata[168]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(43),
I1 => active_target_enc,
O => s_axi_rdata(168)
);
\s_axi_rdata[169]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(44),
I1 => active_target_enc,
O => s_axi_rdata(169)
);
\s_axi_rdata[16]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(19),
I1 => active_target_enc_0,
O => s_axi_rdata(16)
);
\s_axi_rdata[170]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(45),
I1 => active_target_enc,
O => s_axi_rdata(170)
);
\s_axi_rdata[171]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(46),
I1 => active_target_enc,
O => s_axi_rdata(171)
);
\s_axi_rdata[172]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(47),
I1 => active_target_enc,
O => s_axi_rdata(172)
);
\s_axi_rdata[173]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(48),
I1 => active_target_enc,
O => s_axi_rdata(173)
);
\s_axi_rdata[174]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(49),
I1 => active_target_enc,
O => s_axi_rdata(174)
);
\s_axi_rdata[175]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(50),
I1 => active_target_enc,
O => s_axi_rdata(175)
);
\s_axi_rdata[176]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(51),
I1 => active_target_enc,
O => s_axi_rdata(176)
);
\s_axi_rdata[177]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(52),
I1 => active_target_enc,
O => s_axi_rdata(177)
);
\s_axi_rdata[178]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(53),
I1 => active_target_enc,
O => s_axi_rdata(178)
);
\s_axi_rdata[179]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(54),
I1 => active_target_enc,
O => s_axi_rdata(179)
);
\s_axi_rdata[17]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(20),
I1 => active_target_enc_0,
O => s_axi_rdata(17)
);
\s_axi_rdata[180]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(55),
I1 => active_target_enc,
O => s_axi_rdata(180)
);
\s_axi_rdata[181]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(56),
I1 => active_target_enc,
O => s_axi_rdata(181)
);
\s_axi_rdata[182]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(57),
I1 => active_target_enc,
O => s_axi_rdata(182)
);
\s_axi_rdata[183]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(58),
I1 => active_target_enc,
O => s_axi_rdata(183)
);
\s_axi_rdata[184]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(59),
I1 => active_target_enc,
O => s_axi_rdata(184)
);
\s_axi_rdata[185]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(60),
I1 => active_target_enc,
O => s_axi_rdata(185)
);
\s_axi_rdata[186]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(61),
I1 => active_target_enc,
O => s_axi_rdata(186)
);
\s_axi_rdata[187]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(62),
I1 => active_target_enc,
O => s_axi_rdata(187)
);
\s_axi_rdata[188]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(63),
I1 => active_target_enc,
O => s_axi_rdata(188)
);
\s_axi_rdata[189]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(64),
I1 => active_target_enc,
O => s_axi_rdata(189)
);
\s_axi_rdata[18]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(21),
I1 => active_target_enc_0,
O => s_axi_rdata(18)
);
\s_axi_rdata[190]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(65),
I1 => active_target_enc,
O => s_axi_rdata(190)
);
\s_axi_rdata[191]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(66),
I1 => active_target_enc,
O => s_axi_rdata(191)
);
\s_axi_rdata[192]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(67),
I1 => active_target_enc,
O => s_axi_rdata(192)
);
\s_axi_rdata[193]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(68),
I1 => active_target_enc,
O => s_axi_rdata(193)
);
\s_axi_rdata[194]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(69),
I1 => active_target_enc,
O => s_axi_rdata(194)
);
\s_axi_rdata[195]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(70),
I1 => active_target_enc,
O => s_axi_rdata(195)
);
\s_axi_rdata[196]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(71),
I1 => active_target_enc,
O => s_axi_rdata(196)
);
\s_axi_rdata[197]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(72),
I1 => active_target_enc,
O => s_axi_rdata(197)
);
\s_axi_rdata[198]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(73),
I1 => active_target_enc,
O => s_axi_rdata(198)
);
\s_axi_rdata[199]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(74),
I1 => active_target_enc,
O => s_axi_rdata(199)
);
\s_axi_rdata[19]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(22),
I1 => active_target_enc_0,
O => s_axi_rdata(19)
);
\s_axi_rdata[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(4),
I1 => active_target_enc_0,
O => s_axi_rdata(1)
);
\s_axi_rdata[200]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(75),
I1 => active_target_enc,
O => s_axi_rdata(200)
);
\s_axi_rdata[201]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(76),
I1 => active_target_enc,
O => s_axi_rdata(201)
);
\s_axi_rdata[202]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(77),
I1 => active_target_enc,
O => s_axi_rdata(202)
);
\s_axi_rdata[203]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(78),
I1 => active_target_enc,
O => s_axi_rdata(203)
);
\s_axi_rdata[204]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(79),
I1 => active_target_enc,
O => s_axi_rdata(204)
);
\s_axi_rdata[205]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(80),
I1 => active_target_enc,
O => s_axi_rdata(205)
);
\s_axi_rdata[206]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(81),
I1 => active_target_enc,
O => s_axi_rdata(206)
);
\s_axi_rdata[207]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(82),
I1 => active_target_enc,
O => s_axi_rdata(207)
);
\s_axi_rdata[208]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(83),
I1 => active_target_enc,
O => s_axi_rdata(208)
);
\s_axi_rdata[209]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(84),
I1 => active_target_enc,
O => s_axi_rdata(209)
);
\s_axi_rdata[20]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(23),
I1 => active_target_enc_0,
O => s_axi_rdata(20)
);
\s_axi_rdata[210]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(85),
I1 => active_target_enc,
O => s_axi_rdata(210)
);
\s_axi_rdata[211]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(86),
I1 => active_target_enc,
O => s_axi_rdata(211)
);
\s_axi_rdata[212]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(87),
I1 => active_target_enc,
O => s_axi_rdata(212)
);
\s_axi_rdata[213]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(88),
I1 => active_target_enc,
O => s_axi_rdata(213)
);
\s_axi_rdata[214]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(89),
I1 => active_target_enc,
O => s_axi_rdata(214)
);
\s_axi_rdata[215]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(90),
I1 => active_target_enc,
O => s_axi_rdata(215)
);
\s_axi_rdata[216]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(91),
I1 => active_target_enc,
O => s_axi_rdata(216)
);
\s_axi_rdata[217]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(92),
I1 => active_target_enc,
O => s_axi_rdata(217)
);
\s_axi_rdata[218]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(93),
I1 => active_target_enc,
O => s_axi_rdata(218)
);
\s_axi_rdata[219]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(94),
I1 => active_target_enc,
O => s_axi_rdata(219)
);
\s_axi_rdata[21]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(24),
I1 => active_target_enc_0,
O => s_axi_rdata(21)
);
\s_axi_rdata[220]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(95),
I1 => active_target_enc,
O => s_axi_rdata(220)
);
\s_axi_rdata[221]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(96),
I1 => active_target_enc,
O => s_axi_rdata(221)
);
\s_axi_rdata[222]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(97),
I1 => active_target_enc,
O => s_axi_rdata(222)
);
\s_axi_rdata[223]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(98),
I1 => active_target_enc,
O => s_axi_rdata(223)
);
\s_axi_rdata[224]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(99),
I1 => active_target_enc,
O => s_axi_rdata(224)
);
\s_axi_rdata[225]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(100),
I1 => active_target_enc,
O => s_axi_rdata(225)
);
\s_axi_rdata[226]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(101),
I1 => active_target_enc,
O => s_axi_rdata(226)
);
\s_axi_rdata[227]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(102),
I1 => active_target_enc,
O => s_axi_rdata(227)
);
\s_axi_rdata[228]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(103),
I1 => active_target_enc,
O => s_axi_rdata(228)
);
\s_axi_rdata[229]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(104),
I1 => active_target_enc,
O => s_axi_rdata(229)
);
\s_axi_rdata[22]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(25),
I1 => active_target_enc_0,
O => s_axi_rdata(22)
);
\s_axi_rdata[230]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(105),
I1 => active_target_enc,
O => s_axi_rdata(230)
);
\s_axi_rdata[231]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(106),
I1 => active_target_enc,
O => s_axi_rdata(231)
);
\s_axi_rdata[232]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(107),
I1 => active_target_enc,
O => s_axi_rdata(232)
);
\s_axi_rdata[233]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(108),
I1 => active_target_enc,
O => s_axi_rdata(233)
);
\s_axi_rdata[234]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(109),
I1 => active_target_enc,
O => s_axi_rdata(234)
);
\s_axi_rdata[235]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(110),
I1 => active_target_enc,
O => s_axi_rdata(235)
);
\s_axi_rdata[236]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(111),
I1 => active_target_enc,
O => s_axi_rdata(236)
);
\s_axi_rdata[237]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(112),
I1 => active_target_enc,
O => s_axi_rdata(237)
);
\s_axi_rdata[238]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(113),
I1 => active_target_enc,
O => s_axi_rdata(238)
);
\s_axi_rdata[239]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(114),
I1 => active_target_enc,
O => s_axi_rdata(239)
);
\s_axi_rdata[23]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(26),
I1 => active_target_enc_0,
O => s_axi_rdata(23)
);
\s_axi_rdata[240]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(115),
I1 => active_target_enc,
O => s_axi_rdata(240)
);
\s_axi_rdata[241]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(116),
I1 => active_target_enc,
O => s_axi_rdata(241)
);
\s_axi_rdata[242]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(117),
I1 => active_target_enc,
O => s_axi_rdata(242)
);
\s_axi_rdata[243]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(118),
I1 => active_target_enc,
O => s_axi_rdata(243)
);
\s_axi_rdata[244]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(119),
I1 => active_target_enc,
O => s_axi_rdata(244)
);
\s_axi_rdata[245]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(120),
I1 => active_target_enc,
O => s_axi_rdata(245)
);
\s_axi_rdata[246]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(121),
I1 => active_target_enc,
O => s_axi_rdata(246)
);
\s_axi_rdata[247]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(122),
I1 => active_target_enc,
O => s_axi_rdata(247)
);
\s_axi_rdata[248]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(123),
I1 => active_target_enc,
O => s_axi_rdata(248)
);
\s_axi_rdata[249]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(124),
I1 => active_target_enc,
O => s_axi_rdata(249)
);
\s_axi_rdata[24]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(27),
I1 => active_target_enc_0,
O => s_axi_rdata(24)
);
\s_axi_rdata[250]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(125),
I1 => active_target_enc,
O => s_axi_rdata(250)
);
\s_axi_rdata[251]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(126),
I1 => active_target_enc,
O => s_axi_rdata(251)
);
\s_axi_rdata[252]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(127),
I1 => active_target_enc,
O => s_axi_rdata(252)
);
\s_axi_rdata[253]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(128),
I1 => active_target_enc,
O => s_axi_rdata(253)
);
\s_axi_rdata[254]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(129),
I1 => active_target_enc,
O => s_axi_rdata(254)
);
\s_axi_rdata[255]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(130),
I1 => active_target_enc,
O => s_axi_rdata(255)
);
\s_axi_rdata[25]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(28),
I1 => active_target_enc_0,
O => s_axi_rdata(25)
);
\s_axi_rdata[26]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(29),
I1 => active_target_enc_0,
O => s_axi_rdata(26)
);
\s_axi_rdata[27]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(30),
I1 => active_target_enc_0,
O => s_axi_rdata(27)
);
\s_axi_rdata[28]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(31),
I1 => active_target_enc_0,
O => s_axi_rdata(28)
);
\s_axi_rdata[29]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(32),
I1 => active_target_enc_0,
O => s_axi_rdata(29)
);
\s_axi_rdata[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(5),
I1 => active_target_enc_0,
O => s_axi_rdata(2)
);
\s_axi_rdata[30]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(33),
I1 => active_target_enc_0,
O => s_axi_rdata(30)
);
\s_axi_rdata[31]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(34),
I1 => active_target_enc_0,
O => s_axi_rdata(31)
);
\s_axi_rdata[32]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(35),
I1 => active_target_enc_0,
O => s_axi_rdata(32)
);
\s_axi_rdata[33]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(36),
I1 => active_target_enc_0,
O => s_axi_rdata(33)
);
\s_axi_rdata[34]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(37),
I1 => active_target_enc_0,
O => s_axi_rdata(34)
);
\s_axi_rdata[35]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(38),
I1 => active_target_enc_0,
O => s_axi_rdata(35)
);
\s_axi_rdata[36]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(39),
I1 => active_target_enc_0,
O => s_axi_rdata(36)
);
\s_axi_rdata[37]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(40),
I1 => active_target_enc_0,
O => s_axi_rdata(37)
);
\s_axi_rdata[38]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(41),
I1 => active_target_enc_0,
O => s_axi_rdata(38)
);
\s_axi_rdata[39]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(42),
I1 => active_target_enc_0,
O => s_axi_rdata(39)
);
\s_axi_rdata[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(6),
I1 => active_target_enc_0,
O => s_axi_rdata(3)
);
\s_axi_rdata[40]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(43),
I1 => active_target_enc_0,
O => s_axi_rdata(40)
);
\s_axi_rdata[41]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(44),
I1 => active_target_enc_0,
O => s_axi_rdata(41)
);
\s_axi_rdata[42]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(45),
I1 => active_target_enc_0,
O => s_axi_rdata(42)
);
\s_axi_rdata[43]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(46),
I1 => active_target_enc_0,
O => s_axi_rdata(43)
);
\s_axi_rdata[44]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(47),
I1 => active_target_enc_0,
O => s_axi_rdata(44)
);
\s_axi_rdata[45]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(48),
I1 => active_target_enc_0,
O => s_axi_rdata(45)
);
\s_axi_rdata[46]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(49),
I1 => active_target_enc_0,
O => s_axi_rdata(46)
);
\s_axi_rdata[47]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(50),
I1 => active_target_enc_0,
O => s_axi_rdata(47)
);
\s_axi_rdata[48]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(51),
I1 => active_target_enc_0,
O => s_axi_rdata(48)
);
\s_axi_rdata[49]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(52),
I1 => active_target_enc_0,
O => s_axi_rdata(49)
);
\s_axi_rdata[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(7),
I1 => active_target_enc_0,
O => s_axi_rdata(4)
);
\s_axi_rdata[50]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(53),
I1 => active_target_enc_0,
O => s_axi_rdata(50)
);
\s_axi_rdata[51]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(54),
I1 => active_target_enc_0,
O => s_axi_rdata(51)
);
\s_axi_rdata[52]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(55),
I1 => active_target_enc_0,
O => s_axi_rdata(52)
);
\s_axi_rdata[53]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(56),
I1 => active_target_enc_0,
O => s_axi_rdata(53)
);
\s_axi_rdata[54]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(57),
I1 => active_target_enc_0,
O => s_axi_rdata(54)
);
\s_axi_rdata[55]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(58),
I1 => active_target_enc_0,
O => s_axi_rdata(55)
);
\s_axi_rdata[56]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(59),
I1 => active_target_enc_0,
O => s_axi_rdata(56)
);
\s_axi_rdata[57]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(60),
I1 => active_target_enc_0,
O => s_axi_rdata(57)
);
\s_axi_rdata[58]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(61),
I1 => active_target_enc_0,
O => s_axi_rdata(58)
);
\s_axi_rdata[59]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(62),
I1 => active_target_enc_0,
O => s_axi_rdata(59)
);
\s_axi_rdata[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(8),
I1 => active_target_enc_0,
O => s_axi_rdata(5)
);
\s_axi_rdata[60]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(63),
I1 => active_target_enc_0,
O => s_axi_rdata(60)
);
\s_axi_rdata[61]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(64),
I1 => active_target_enc_0,
O => s_axi_rdata(61)
);
\s_axi_rdata[62]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(65),
I1 => active_target_enc_0,
O => s_axi_rdata(62)
);
\s_axi_rdata[63]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(66),
I1 => active_target_enc_0,
O => s_axi_rdata(63)
);
\s_axi_rdata[64]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(67),
I1 => active_target_enc_0,
O => s_axi_rdata(64)
);
\s_axi_rdata[65]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(68),
I1 => active_target_enc_0,
O => s_axi_rdata(65)
);
\s_axi_rdata[66]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(69),
I1 => active_target_enc_0,
O => s_axi_rdata(66)
);
\s_axi_rdata[67]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(70),
I1 => active_target_enc_0,
O => s_axi_rdata(67)
);
\s_axi_rdata[68]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(71),
I1 => active_target_enc_0,
O => s_axi_rdata(68)
);
\s_axi_rdata[69]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(72),
I1 => active_target_enc_0,
O => s_axi_rdata(69)
);
\s_axi_rdata[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(9),
I1 => active_target_enc_0,
O => s_axi_rdata(6)
);
\s_axi_rdata[70]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(73),
I1 => active_target_enc_0,
O => s_axi_rdata(70)
);
\s_axi_rdata[71]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(74),
I1 => active_target_enc_0,
O => s_axi_rdata(71)
);
\s_axi_rdata[72]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(75),
I1 => active_target_enc_0,
O => s_axi_rdata(72)
);
\s_axi_rdata[73]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(76),
I1 => active_target_enc_0,
O => s_axi_rdata(73)
);
\s_axi_rdata[74]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(77),
I1 => active_target_enc_0,
O => s_axi_rdata(74)
);
\s_axi_rdata[75]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(78),
I1 => active_target_enc_0,
O => s_axi_rdata(75)
);
\s_axi_rdata[76]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(79),
I1 => active_target_enc_0,
O => s_axi_rdata(76)
);
\s_axi_rdata[77]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(80),
I1 => active_target_enc_0,
O => s_axi_rdata(77)
);
\s_axi_rdata[78]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(81),
I1 => active_target_enc_0,
O => s_axi_rdata(78)
);
\s_axi_rdata[79]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(82),
I1 => active_target_enc_0,
O => s_axi_rdata(79)
);
\s_axi_rdata[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(10),
I1 => active_target_enc_0,
O => s_axi_rdata(7)
);
\s_axi_rdata[80]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(83),
I1 => active_target_enc_0,
O => s_axi_rdata(80)
);
\s_axi_rdata[81]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(84),
I1 => active_target_enc_0,
O => s_axi_rdata(81)
);
\s_axi_rdata[82]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(85),
I1 => active_target_enc_0,
O => s_axi_rdata(82)
);
\s_axi_rdata[83]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(86),
I1 => active_target_enc_0,
O => s_axi_rdata(83)
);
\s_axi_rdata[84]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(87),
I1 => active_target_enc_0,
O => s_axi_rdata(84)
);
\s_axi_rdata[85]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(88),
I1 => active_target_enc_0,
O => s_axi_rdata(85)
);
\s_axi_rdata[86]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(89),
I1 => active_target_enc_0,
O => s_axi_rdata(86)
);
\s_axi_rdata[87]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(90),
I1 => active_target_enc_0,
O => s_axi_rdata(87)
);
\s_axi_rdata[88]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(91),
I1 => active_target_enc_0,
O => s_axi_rdata(88)
);
\s_axi_rdata[89]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(92),
I1 => active_target_enc_0,
O => s_axi_rdata(89)
);
\s_axi_rdata[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(11),
I1 => active_target_enc_0,
O => s_axi_rdata(8)
);
\s_axi_rdata[90]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(93),
I1 => active_target_enc_0,
O => s_axi_rdata(90)
);
\s_axi_rdata[91]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(94),
I1 => active_target_enc_0,
O => s_axi_rdata(91)
);
\s_axi_rdata[92]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(95),
I1 => active_target_enc_0,
O => s_axi_rdata(92)
);
\s_axi_rdata[93]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(96),
I1 => active_target_enc_0,
O => s_axi_rdata(93)
);
\s_axi_rdata[94]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(97),
I1 => active_target_enc_0,
O => s_axi_rdata(94)
);
\s_axi_rdata[95]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(98),
I1 => active_target_enc_0,
O => s_axi_rdata(95)
);
\s_axi_rdata[96]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(99),
I1 => active_target_enc_0,
O => s_axi_rdata(96)
);
\s_axi_rdata[97]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(100),
I1 => active_target_enc_0,
O => s_axi_rdata(97)
);
\s_axi_rdata[98]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(101),
I1 => active_target_enc_0,
O => s_axi_rdata(98)
);
\s_axi_rdata[99]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(102),
I1 => active_target_enc_0,
O => s_axi_rdata(99)
);
\s_axi_rdata[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => st_mr_rmesg(12),
I1 => active_target_enc_0,
O => s_axi_rdata(9)
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => m_axi_rvalid(0),
I1 => \^m_axi_rready[0]\,
I2 => s_ready_i_i_2_n_0,
O => s_ready_i0
);
s_ready_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"20A02AAA2AAA2AAA"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => s_axi_rready(1),
I2 => \^q\(3),
I3 => active_target_hot_3(0),
I4 => s_axi_rready(0),
I5 => active_target_hot_2(0),
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[100]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(100),
Q => \skid_buffer_reg_n_0_[100]\,
R => '0'
);
\skid_buffer_reg[101]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(101),
Q => \skid_buffer_reg_n_0_[101]\,
R => '0'
);
\skid_buffer_reg[102]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(102),
Q => \skid_buffer_reg_n_0_[102]\,
R => '0'
);
\skid_buffer_reg[103]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(103),
Q => \skid_buffer_reg_n_0_[103]\,
R => '0'
);
\skid_buffer_reg[104]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(104),
Q => \skid_buffer_reg_n_0_[104]\,
R => '0'
);
\skid_buffer_reg[105]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(105),
Q => \skid_buffer_reg_n_0_[105]\,
R => '0'
);
\skid_buffer_reg[106]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(106),
Q => \skid_buffer_reg_n_0_[106]\,
R => '0'
);
\skid_buffer_reg[107]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(107),
Q => \skid_buffer_reg_n_0_[107]\,
R => '0'
);
\skid_buffer_reg[108]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(108),
Q => \skid_buffer_reg_n_0_[108]\,
R => '0'
);
\skid_buffer_reg[109]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(109),
Q => \skid_buffer_reg_n_0_[109]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[110]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(110),
Q => \skid_buffer_reg_n_0_[110]\,
R => '0'
);
\skid_buffer_reg[111]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(111),
Q => \skid_buffer_reg_n_0_[111]\,
R => '0'
);
\skid_buffer_reg[112]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(112),
Q => \skid_buffer_reg_n_0_[112]\,
R => '0'
);
\skid_buffer_reg[113]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(113),
Q => \skid_buffer_reg_n_0_[113]\,
R => '0'
);
\skid_buffer_reg[114]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(114),
Q => \skid_buffer_reg_n_0_[114]\,
R => '0'
);
\skid_buffer_reg[115]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(115),
Q => \skid_buffer_reg_n_0_[115]\,
R => '0'
);
\skid_buffer_reg[116]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(116),
Q => \skid_buffer_reg_n_0_[116]\,
R => '0'
);
\skid_buffer_reg[117]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(117),
Q => \skid_buffer_reg_n_0_[117]\,
R => '0'
);
\skid_buffer_reg[118]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(118),
Q => \skid_buffer_reg_n_0_[118]\,
R => '0'
);
\skid_buffer_reg[119]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(119),
Q => \skid_buffer_reg_n_0_[119]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[120]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(120),
Q => \skid_buffer_reg_n_0_[120]\,
R => '0'
);
\skid_buffer_reg[121]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(121),
Q => \skid_buffer_reg_n_0_[121]\,
R => '0'
);
\skid_buffer_reg[122]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(122),
Q => \skid_buffer_reg_n_0_[122]\,
R => '0'
);
\skid_buffer_reg[123]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(123),
Q => \skid_buffer_reg_n_0_[123]\,
R => '0'
);
\skid_buffer_reg[124]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(124),
Q => \skid_buffer_reg_n_0_[124]\,
R => '0'
);
\skid_buffer_reg[125]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(125),
Q => \skid_buffer_reg_n_0_[125]\,
R => '0'
);
\skid_buffer_reg[126]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(126),
Q => \skid_buffer_reg_n_0_[126]\,
R => '0'
);
\skid_buffer_reg[127]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(127),
Q => \skid_buffer_reg_n_0_[127]\,
R => '0'
);
\skid_buffer_reg[128]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[128]\,
R => '0'
);
\skid_buffer_reg[129]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[129]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[130]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[130]\,
R => '0'
);
\skid_buffer_reg[131]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[131]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(34),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(35),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(36),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(37),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(38),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(39),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(40),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(41),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(42),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(43),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(44),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(45),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(46),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(47),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(48),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(49),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(50),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(51),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(52),
Q => \skid_buffer_reg_n_0_[52]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(53),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(54),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(55),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(56),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(57),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(58),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(59),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(60),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(61),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(62),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(63),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(64),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(65),
Q => \skid_buffer_reg_n_0_[65]\,
R => '0'
);
\skid_buffer_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(66),
Q => \skid_buffer_reg_n_0_[66]\,
R => '0'
);
\skid_buffer_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(67),
Q => \skid_buffer_reg_n_0_[67]\,
R => '0'
);
\skid_buffer_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(68),
Q => \skid_buffer_reg_n_0_[68]\,
R => '0'
);
\skid_buffer_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(69),
Q => \skid_buffer_reg_n_0_[69]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(70),
Q => \skid_buffer_reg_n_0_[70]\,
R => '0'
);
\skid_buffer_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(71),
Q => \skid_buffer_reg_n_0_[71]\,
R => '0'
);
\skid_buffer_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(72),
Q => \skid_buffer_reg_n_0_[72]\,
R => '0'
);
\skid_buffer_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(73),
Q => \skid_buffer_reg_n_0_[73]\,
R => '0'
);
\skid_buffer_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(74),
Q => \skid_buffer_reg_n_0_[74]\,
R => '0'
);
\skid_buffer_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(75),
Q => \skid_buffer_reg_n_0_[75]\,
R => '0'
);
\skid_buffer_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(76),
Q => \skid_buffer_reg_n_0_[76]\,
R => '0'
);
\skid_buffer_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(77),
Q => \skid_buffer_reg_n_0_[77]\,
R => '0'
);
\skid_buffer_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(78),
Q => \skid_buffer_reg_n_0_[78]\,
R => '0'
);
\skid_buffer_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(79),
Q => \skid_buffer_reg_n_0_[79]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(80),
Q => \skid_buffer_reg_n_0_[80]\,
R => '0'
);
\skid_buffer_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(81),
Q => \skid_buffer_reg_n_0_[81]\,
R => '0'
);
\skid_buffer_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(82),
Q => \skid_buffer_reg_n_0_[82]\,
R => '0'
);
\skid_buffer_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(83),
Q => \skid_buffer_reg_n_0_[83]\,
R => '0'
);
\skid_buffer_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(84),
Q => \skid_buffer_reg_n_0_[84]\,
R => '0'
);
\skid_buffer_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(85),
Q => \skid_buffer_reg_n_0_[85]\,
R => '0'
);
\skid_buffer_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(86),
Q => \skid_buffer_reg_n_0_[86]\,
R => '0'
);
\skid_buffer_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(87),
Q => \skid_buffer_reg_n_0_[87]\,
R => '0'
);
\skid_buffer_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(88),
Q => \skid_buffer_reg_n_0_[88]\,
R => '0'
);
\skid_buffer_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(89),
Q => \skid_buffer_reg_n_0_[89]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(90),
Q => \skid_buffer_reg_n_0_[90]\,
R => '0'
);
\skid_buffer_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(91),
Q => \skid_buffer_reg_n_0_[91]\,
R => '0'
);
\skid_buffer_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(92),
Q => \skid_buffer_reg_n_0_[92]\,
R => '0'
);
\skid_buffer_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(93),
Q => \skid_buffer_reg_n_0_[93]\,
R => '0'
);
\skid_buffer_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(94),
Q => \skid_buffer_reg_n_0_[94]\,
R => '0'
);
\skid_buffer_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(95),
Q => \skid_buffer_reg_n_0_[95]\,
R => '0'
);
\skid_buffer_reg[96]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(96),
Q => \skid_buffer_reg_n_0_[96]\,
R => '0'
);
\skid_buffer_reg[97]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(97),
Q => \skid_buffer_reg_n_0_[97]\,
R => '0'
);
\skid_buffer_reg[98]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(98),
Q => \skid_buffer_reg_n_0_[98]\,
R => '0'
);
\skid_buffer_reg[99]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(99),
Q => \skid_buffer_reg_n_0_[99]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo is
port (
\gen_arbiter.m_target_hot_i_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_onehot_state_reg[2]_0\ : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
\storage_data1_reg[0]_0\ : out STD_LOGIC;
s_ready_i_reg_1 : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_bvalid_i_reg\ : out STD_LOGIC;
\storage_data1_reg[0]_1\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
aresetn_d_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
sel_4 : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_1 : in STD_LOGIC;
write_cs : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_avalid_0 : in STD_LOGIC;
m_select_enc_1 : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid_2 : in STD_LOGIC;
m_select_enc_3 : in STD_LOGIC;
m_valid_i_reg_2 : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo";
end system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo;
architecture STRUCTURE of system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo is
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_4__0_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_6_n_0\ : STD_LOGIC;
signal \^fsm_onehot_state_reg[2]_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_2\ : STD_LOGIC;
signal m_valid_i : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \m_valid_i_i_2__1_n_0\ : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i_i_1__1_n_0\ : STD_LOGIC;
signal \s_ready_i_i_2__0_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \^s_ready_i_reg_1\ : STD_LOGIC;
signal \storage_data1[0]_i_2__0_n_0\ : STD_LOGIC;
signal \^storage_data1_reg[0]_0\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_primitive_shifter.gen_srls[0].srl_inst_i_3\ : label is "soft_lutpair326";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair326";
begin
\FSM_onehot_state_reg[2]_0\ <= \^fsm_onehot_state_reg[2]_0\;
SR(0) <= \^sr\(0);
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
s_ready_i_reg_1 <= \^s_ready_i_reg_1\;
\storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"44040000"
)
port map (
I0 => p_9_in,
I1 => m_valid_i_reg_0,
I2 => s_axi_awvalid(0),
I3 => m_ready_d(0),
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444744"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => p_9_in,
I2 => push,
I3 => \FSM_onehot_state[2]_i_2_n_0\,
I4 => \FSM_onehot_state[3]_i_6_n_0\,
I5 => p_0_in8_in,
O => \FSM_onehot_state[1]_i_1_n_0\
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888BBBBB8BB"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => p_9_in,
I2 => push,
I3 => \FSM_onehot_state[2]_i_2_n_0\,
I4 => \FSM_onehot_state[3]_i_6_n_0\,
I5 => p_0_in8_in,
O => \FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => \^fsm_onehot_state_reg[2]_0\,
I2 => s_axi_wvalid(0),
I3 => s_axi_wlast(0),
I4 => m_valid_i_reg_1,
O => \FSM_onehot_state[2]_i_2_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEFEEEEEE"
)
port map (
I0 => \FSM_onehot_state[3]_i_3_n_0\,
I1 => \FSM_onehot_state[3]_i_4__0_n_0\,
I2 => push,
I3 => m_valid_i_reg_0,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => \FSM_onehot_state[3]_i_6_n_0\,
O => m_valid_i
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000022A2"
)
port map (
I0 => p_0_in8_in,
I1 => m_valid_i_reg_0,
I2 => s_axi_awvalid(0),
I3 => m_ready_d(0),
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"2822222222222222"
)
port map (
I0 => p_0_in8_in,
I1 => \m_ready_d_reg[1]\,
I2 => m_valid_i_reg_1,
I3 => s_axi_wlast(0),
I4 => s_axi_wvalid(0),
I5 => \^fsm_onehot_state_reg[2]_0\,
O => \FSM_onehot_state[3]_i_3_n_0\
);
\FSM_onehot_state[3]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => p_9_in,
I1 => s_axi_awvalid(0),
I2 => m_ready_d(0),
O => \FSM_onehot_state[3]_i_4__0_n_0\
);
\FSM_onehot_state[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => fifoaddr(1),
I1 => fifoaddr(2),
I2 => fifoaddr(0),
O => \FSM_onehot_state[3]_i_6_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => \^sr\(0)
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => \^sr\(0)
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => \^sr\(0)
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => m_valid_i,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => \^sr\(0)
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => aresetn_d_reg(0),
Q => \^sr\(0),
R => '0'
);
\gen_axi.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \^storage_data1_reg[0]_0\,
I1 => m_select_enc_1,
I2 => m_avalid_0,
I3 => write_cs(1),
I4 => \^s_ready_i_reg_1\,
O => \gen_axi.s_axi_bvalid_i_reg\
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \^s_ready_i_reg_1\,
I1 => write_cs(1),
I2 => m_avalid_0,
I3 => m_select_enc_1,
I4 => \^storage_data1_reg[0]_0\,
I5 => write_cs(0),
O => \gen_axi.s_axi_wready_i_reg\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^fsm_onehot_state_reg[2]_0\,
I1 => s_axi_wvalid(0),
I2 => s_axi_wlast(0),
O => \^s_ready_i_reg_1\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \^fsm_onehot_state_reg[2]_0\,
O => \storage_data1_reg[0]_1\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33FFBB07CC0044F8"
)
port map (
I0 => \^s_ready_i_reg_0\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => p_0_in8_in,
I3 => m_valid_i_reg_0,
I4 => \m_ready_d_reg[1]\,
I5 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5BF2A40"
)
port map (
I0 => fifoaddr(0),
I1 => m_valid_i_reg_0,
I2 => \FSM_onehot_state_reg_n_0_[3]\,
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F777EFFF08881000"
)
port map (
I0 => fifoaddr(0),
I1 => fifoaddr(1),
I2 => m_valid_i_reg_0,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => push,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => aresetn_d_reg(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => aresetn_d_reg(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => aresetn_d_reg(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized8\
port map (
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
\gen_arbiter.m_target_hot_i_reg[1]\(0) => \gen_arbiter.m_target_hot_i_reg[1]\(0),
\m_ready_d_reg[1]\ => \storage_data1[0]_i_2__0_n_0\,
\m_ready_d_reg[1]_0\ => \m_ready_d_reg[1]\,
m_valid_i_reg => m_valid_i_reg_0,
m_valid_i_reg_0 => \^s_ready_i_reg_1\,
m_valid_i_reg_1 => m_valid_i_reg_1,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
s_axi_awaddr(3 downto 0) => s_axi_awaddr(3 downto 0),
s_ready_i_reg => \^s_ready_i_reg_0\,
sel_4 => sel_4,
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_2\,
\storage_data1_reg[0]_0\ => \^storage_data1_reg[0]_0\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04000000"
)
port map (
I0 => \^storage_data1_reg[0]_0\,
I1 => m_avalid_2,
I2 => m_select_enc_3,
I3 => \^fsm_onehot_state_reg[2]_0\,
I4 => s_axi_wvalid(0),
O => m_axi_wvalid(0)
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDDFDDDDDD"
)
port map (
I0 => \m_valid_i_i_2__1_n_0\,
I1 => \FSM_onehot_state[3]_i_4__0_n_0\,
I2 => push,
I3 => m_valid_i_reg_0,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => \FSM_onehot_state[3]_i_6_n_0\,
O => m_valid_i_i_1_n_0
);
\m_valid_i_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAAAAAFFFFFFFF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => m_valid_i_reg_1,
I2 => s_axi_wlast(0),
I3 => s_axi_wvalid(0),
I4 => \^fsm_onehot_state_reg[2]_0\,
I5 => p_0_in8_in,
O => \m_valid_i_i_2__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i,
D => m_valid_i_i_1_n_0,
Q => \^fsm_onehot_state_reg[2]_0\,
R => \^sr\(0)
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888A888888888"
)
port map (
I0 => \^fsm_onehot_state_reg[2]_0\,
I1 => m_valid_i_reg_2,
I2 => m_axi_wready(0),
I3 => \^storage_data1_reg[0]_0\,
I4 => m_select_enc_3,
I5 => m_avalid_2,
O => s_axi_wready(0)
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFFAAAAAAAA"
)
port map (
I0 => \s_ready_i_i_2__0_n_0\,
I1 => fifoaddr(2),
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => push,
I5 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__1_n_0\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAAAAAAAAAAAAA"
)
port map (
I0 => \^sr\(0),
I1 => m_valid_i_reg_1,
I2 => s_axi_wlast(0),
I3 => s_axi_wvalid(0),
I4 => \^fsm_onehot_state_reg[2]_0\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => \s_ready_i_i_2__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__1_n_0\,
Q => \^s_ready_i_reg_0\,
R => aresetn_d_reg(0)
);
\storage_data1[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020202020202220"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in8_in,
I4 => \^s_ready_i_reg_1\,
I5 => m_valid_i_reg_1,
O => \storage_data1[0]_i_2__0_n_0\
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_2\,
Q => \^storage_data1_reg[0]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ is
port (
\storage_data1_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : out STD_LOGIC;
\storage_data1_reg[0]_1\ : out STD_LOGIC;
\storage_data1_reg[0]_2\ : out STD_LOGIC;
\storage_data1_reg[0]_3\ : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
push : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC;
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
in1 : in STD_LOGIC;
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]_0\ : in STD_LOGIC;
\m_ready_d_reg[0]\ : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_0 : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid_1 : in STD_LOGIC;
m_valid_i_reg_1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ : in STD_LOGIC;
p_0_out : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo";
end \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\;
architecture STRUCTURE of \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\ is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_onehot_state[2]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_3_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_5_n_0\ : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \^m_avalid\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \^storage_data1_reg[0]_0\ : STD_LOGIC;
signal \^storage_data1_reg[0]_1\ : STD_LOGIC;
signal \^storage_data1_reg[0]_3\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_state[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \FSM_onehot_state[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \FSM_onehot_state[3]_i_5__0\ : label is "soft_lutpair44";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM of \m_axi_wdata[0]_INST_0\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_axi_wdata[100]_INST_0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_axi_wdata[101]_INST_0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_axi_wdata[102]_INST_0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_axi_wdata[103]_INST_0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_axi_wdata[104]_INST_0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_axi_wdata[105]_INST_0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_axi_wdata[106]_INST_0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_axi_wdata[107]_INST_0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_axi_wdata[108]_INST_0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_axi_wdata[109]_INST_0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_axi_wdata[10]_INST_0\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_axi_wdata[110]_INST_0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_axi_wdata[111]_INST_0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_axi_wdata[112]_INST_0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_wdata[113]_INST_0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_axi_wdata[114]_INST_0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_axi_wdata[115]_INST_0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_axi_wdata[116]_INST_0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_axi_wdata[117]_INST_0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_axi_wdata[118]_INST_0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_axi_wdata[119]_INST_0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_axi_wdata[11]_INST_0\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_axi_wdata[120]_INST_0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_axi_wdata[121]_INST_0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_axi_wdata[122]_INST_0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_axi_wdata[123]_INST_0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_axi_wdata[124]_INST_0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_axi_wdata[125]_INST_0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_axi_wdata[126]_INST_0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_axi_wdata[127]_INST_0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_axi_wdata[12]_INST_0\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_axi_wdata[13]_INST_0\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_axi_wdata[14]_INST_0\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_axi_wdata[15]_INST_0\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_axi_wdata[16]_INST_0\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_axi_wdata[17]_INST_0\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_axi_wdata[18]_INST_0\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_axi_wdata[19]_INST_0\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_axi_wdata[1]_INST_0\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_axi_wdata[20]_INST_0\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_axi_wdata[21]_INST_0\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_axi_wdata[22]_INST_0\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_axi_wdata[23]_INST_0\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_axi_wdata[24]_INST_0\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_axi_wdata[25]_INST_0\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_axi_wdata[26]_INST_0\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_axi_wdata[27]_INST_0\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_axi_wdata[28]_INST_0\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_axi_wdata[29]_INST_0\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_axi_wdata[2]_INST_0\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_axi_wdata[30]_INST_0\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_axi_wdata[31]_INST_0\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_axi_wdata[32]_INST_0\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_axi_wdata[33]_INST_0\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_axi_wdata[34]_INST_0\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_axi_wdata[35]_INST_0\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_axi_wdata[36]_INST_0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_axi_wdata[37]_INST_0\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_axi_wdata[38]_INST_0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_axi_wdata[39]_INST_0\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_axi_wdata[3]_INST_0\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_axi_wdata[40]_INST_0\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_axi_wdata[41]_INST_0\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_axi_wdata[42]_INST_0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_axi_wdata[43]_INST_0\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_axi_wdata[44]_INST_0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_axi_wdata[45]_INST_0\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_axi_wdata[46]_INST_0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_axi_wdata[47]_INST_0\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_axi_wdata[48]_INST_0\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_axi_wdata[49]_INST_0\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_axi_wdata[4]_INST_0\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_axi_wdata[50]_INST_0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_axi_wdata[51]_INST_0\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_axi_wdata[52]_INST_0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_axi_wdata[53]_INST_0\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_axi_wdata[54]_INST_0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_axi_wdata[55]_INST_0\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_axi_wdata[56]_INST_0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_wdata[57]_INST_0\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_axi_wdata[58]_INST_0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_axi_wdata[59]_INST_0\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_axi_wdata[5]_INST_0\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_axi_wdata[60]_INST_0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_axi_wdata[61]_INST_0\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_axi_wdata[62]_INST_0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_axi_wdata[63]_INST_0\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_axi_wdata[64]_INST_0\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_axi_wdata[65]_INST_0\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_axi_wdata[66]_INST_0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_axi_wdata[67]_INST_0\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_axi_wdata[68]_INST_0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_axi_wdata[69]_INST_0\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_axi_wdata[6]_INST_0\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_axi_wdata[70]_INST_0\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_axi_wdata[71]_INST_0\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_axi_wdata[72]_INST_0\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_axi_wdata[73]_INST_0\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_axi_wdata[74]_INST_0\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_axi_wdata[75]_INST_0\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_axi_wdata[76]_INST_0\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_axi_wdata[77]_INST_0\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_axi_wdata[78]_INST_0\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_axi_wdata[79]_INST_0\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_axi_wdata[7]_INST_0\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_axi_wdata[80]_INST_0\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_axi_wdata[81]_INST_0\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_axi_wdata[82]_INST_0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_axi_wdata[83]_INST_0\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_axi_wdata[84]_INST_0\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_axi_wdata[85]_INST_0\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_axi_wdata[86]_INST_0\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_axi_wdata[87]_INST_0\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_axi_wdata[88]_INST_0\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_axi_wdata[89]_INST_0\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_axi_wdata[8]_INST_0\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_axi_wdata[90]_INST_0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_axi_wdata[91]_INST_0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_axi_wdata[92]_INST_0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_axi_wdata[93]_INST_0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_axi_wdata[94]_INST_0\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_axi_wdata[95]_INST_0\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_axi_wdata[96]_INST_0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_axi_wdata[97]_INST_0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_axi_wdata[98]_INST_0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_axi_wdata[99]_INST_0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_axi_wdata[9]_INST_0\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_axi_wlast[0]_INST_0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_axi_wstrb[0]_INST_0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_axi_wstrb[10]_INST_0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_axi_wstrb[11]_INST_0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_axi_wstrb[12]_INST_0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_axi_wstrb[13]_INST_0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_axi_wstrb[14]_INST_0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_axi_wstrb[15]_INST_0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_axi_wstrb[1]_INST_0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_axi_wstrb[2]_INST_0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_axi_wstrb[3]_INST_0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_axi_wstrb[4]_INST_0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_axi_wstrb[5]_INST_0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_axi_wstrb[6]_INST_0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_axi_wstrb[7]_INST_0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_axi_wstrb[8]_INST_0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_axi_wstrb[9]_INST_0\ : label is "soft_lutpair48";
begin
E(0) <= \^e\(0);
m_avalid <= \^m_avalid\;
\storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\;
\storage_data1_reg[0]_1\ <= \^storage_data1_reg[0]_1\;
\storage_data1_reg[0]_3\ <= \^storage_data1_reg[0]_3\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444044400000000"
)
port map (
I0 => \out\(0),
I1 => \^storage_data1_reg[0]_0\,
I2 => Q(0),
I3 => aa_sa_awvalid,
I4 => m_ready_d(0),
I5 => \out\(1),
O => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0)
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"44444744"
)
port map (
I0 => \m_ready_d_reg[0]\,
I1 => \out\(0),
I2 => \FSM_onehot_state[2]_i_3_n_0\,
I3 => \FSM_onehot_state[3]_i_5_n_0\,
I4 => \out\(1),
O => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1)
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8888B8BB"
)
port map (
I0 => \m_ready_d_reg[0]\,
I1 => \out\(0),
I2 => \FSM_onehot_state[2]_i_3_n_0\,
I3 => \FSM_onehot_state[3]_i_5_n_0\,
I4 => \out\(1),
O => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2)
);
\FSM_onehot_state[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \out\(2),
I1 => fifoaddr(2),
I2 => \^storage_data1_reg[0]_0\,
O => \FSM_onehot_state[2]_i_3_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFEEEEEEEEEEEEE"
)
port map (
I0 => \FSM_onehot_state[3]_i_3_n_0\,
I1 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
I2 => \out\(2),
I3 => fifoaddr(2),
I4 => \^storage_data1_reg[0]_0\,
I5 => \FSM_onehot_state[3]_i_5_n_0\,
O => \^e\(0)
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002222A222"
)
port map (
I0 => \out\(1),
I1 => \^storage_data1_reg[0]_0\,
I2 => Q(0),
I3 => aa_sa_awvalid,
I4 => m_ready_d(0),
I5 => \out\(0),
O => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3)
);
\FSM_onehot_state[3]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAA2000"
)
port map (
I0 => \out\(1),
I1 => m_ready_d(0),
I2 => aa_sa_awvalid,
I3 => Q(0),
I4 => \^storage_data1_reg[0]_0\,
O => \FSM_onehot_state[3]_i_3_n_0\
);
\FSM_onehot_state[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000CCFD"
)
port map (
I0 => \out\(1),
I1 => \m_ready_d_reg[0]\,
I2 => \^storage_data1_reg[0]_0\,
I3 => \out\(2),
I4 => fifoaddr(0),
I5 => fifoaddr(1),
O => \FSM_onehot_state[3]_i_5_n_0\
);
\FSM_onehot_state[3]_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^storage_data1_reg[0]_3\,
I1 => s_axi_wlast(0),
I2 => s_axi_wvalid(0),
I3 => m_avalid_1,
O => \storage_data1_reg[0]_2\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FDFF"
)
port map (
I0 => \^m_avalid\,
I1 => \^storage_data1_reg[0]_1\,
I2 => m_select_enc_0,
I3 => m_axi_wready(0),
I4 => m_valid_i_reg_1,
O => \^storage_data1_reg[0]_3\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3FCDC032"
)
port map (
I0 => \out\(1),
I1 => \m_ready_d_reg[0]\,
I2 => \out\(2),
I3 => \^storage_data1_reg[0]_0\,
I4 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFDDBFDF40224020"
)
port map (
I0 => fifoaddr(0),
I1 => \^storage_data1_reg[0]_0\,
I2 => \out\(2),
I3 => \m_ready_d_reg[0]\,
I4 => \out\(1),
I5 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BDFF4200"
)
port map (
I0 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\,
I1 => fifoaddr(0),
I2 => fifoaddr(1),
I3 => p_0_out,
I4 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl__parameterized17\
port map (
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]_0\,
m_avalid => \^m_avalid\,
m_axi_wready(0) => m_axi_wready(0),
m_select_enc_0 => m_select_enc_0,
m_valid_i_reg => m_valid_i_reg_0,
\out\(0) => \out\(2),
push => push,
s_axi_wlast(0) => s_axi_wlast(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
\storage_data1_reg[0]_0\ => \^storage_data1_reg[0]_0\,
\storage_data1_reg[0]_1\ => \^storage_data1_reg[0]_1\
);
\m_axi_wdata[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(0)
);
\m_axi_wdata[100]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(100),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(100)
);
\m_axi_wdata[101]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(101),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(101)
);
\m_axi_wdata[102]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(102),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(102)
);
\m_axi_wdata[103]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(103),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(103)
);
\m_axi_wdata[104]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(104),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(104)
);
\m_axi_wdata[105]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(105),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(105)
);
\m_axi_wdata[106]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(106),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(106)
);
\m_axi_wdata[107]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(107),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(107)
);
\m_axi_wdata[108]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(108),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(108)
);
\m_axi_wdata[109]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(109),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(109)
);
\m_axi_wdata[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(10),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(10)
);
\m_axi_wdata[110]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(110),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(110)
);
\m_axi_wdata[111]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(111),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(111)
);
\m_axi_wdata[112]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(112),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(112)
);
\m_axi_wdata[113]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(113),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(113)
);
\m_axi_wdata[114]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(114),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(114)
);
\m_axi_wdata[115]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(115),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(115)
);
\m_axi_wdata[116]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(116),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(116)
);
\m_axi_wdata[117]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(117),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(117)
);
\m_axi_wdata[118]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(118),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(118)
);
\m_axi_wdata[119]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(119),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(119)
);
\m_axi_wdata[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(11),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(11)
);
\m_axi_wdata[120]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(120),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(120)
);
\m_axi_wdata[121]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(121),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(121)
);
\m_axi_wdata[122]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(122),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(122)
);
\m_axi_wdata[123]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(123),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(123)
);
\m_axi_wdata[124]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(124),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(124)
);
\m_axi_wdata[125]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(125),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(125)
);
\m_axi_wdata[126]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(126),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(126)
);
\m_axi_wdata[127]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(127),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(127)
);
\m_axi_wdata[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(12),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(12)
);
\m_axi_wdata[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(13),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(13)
);
\m_axi_wdata[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(14),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(14)
);
\m_axi_wdata[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(15),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(15)
);
\m_axi_wdata[16]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(16),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(16)
);
\m_axi_wdata[17]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(17),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(17)
);
\m_axi_wdata[18]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(18),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(18)
);
\m_axi_wdata[19]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(19),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(19)
);
\m_axi_wdata[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(1)
);
\m_axi_wdata[20]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(20),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(20)
);
\m_axi_wdata[21]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(21),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(21)
);
\m_axi_wdata[22]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(22),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(22)
);
\m_axi_wdata[23]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(23),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(23)
);
\m_axi_wdata[24]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(24),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(24)
);
\m_axi_wdata[25]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(25),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(25)
);
\m_axi_wdata[26]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(26),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(26)
);
\m_axi_wdata[27]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(27),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(27)
);
\m_axi_wdata[28]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(28),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(28)
);
\m_axi_wdata[29]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(29),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(29)
);
\m_axi_wdata[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(2)
);
\m_axi_wdata[30]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(30),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(30)
);
\m_axi_wdata[31]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(31),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(31)
);
\m_axi_wdata[32]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(32),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(32)
);
\m_axi_wdata[33]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(33),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(33)
);
\m_axi_wdata[34]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(34),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(34)
);
\m_axi_wdata[35]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(35),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(35)
);
\m_axi_wdata[36]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(36),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(36)
);
\m_axi_wdata[37]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(37),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(37)
);
\m_axi_wdata[38]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(38),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(38)
);
\m_axi_wdata[39]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(39),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(39)
);
\m_axi_wdata[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(3)
);
\m_axi_wdata[40]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(40),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(40)
);
\m_axi_wdata[41]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(41),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(41)
);
\m_axi_wdata[42]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(42),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(42)
);
\m_axi_wdata[43]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(43),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(43)
);
\m_axi_wdata[44]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(44),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(44)
);
\m_axi_wdata[45]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(45),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(45)
);
\m_axi_wdata[46]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(46),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(46)
);
\m_axi_wdata[47]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(47),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(47)
);
\m_axi_wdata[48]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(48),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(48)
);
\m_axi_wdata[49]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(49),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(49)
);
\m_axi_wdata[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(4)
);
\m_axi_wdata[50]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(50),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(50)
);
\m_axi_wdata[51]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(51),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(51)
);
\m_axi_wdata[52]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(52),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(52)
);
\m_axi_wdata[53]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(53),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(53)
);
\m_axi_wdata[54]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(54),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(54)
);
\m_axi_wdata[55]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(55),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(55)
);
\m_axi_wdata[56]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(56),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(56)
);
\m_axi_wdata[57]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(57),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(57)
);
\m_axi_wdata[58]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(58),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(58)
);
\m_axi_wdata[59]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(59),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(59)
);
\m_axi_wdata[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(5)
);
\m_axi_wdata[60]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(60),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(60)
);
\m_axi_wdata[61]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(61),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(61)
);
\m_axi_wdata[62]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(62),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(62)
);
\m_axi_wdata[63]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(63),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(63)
);
\m_axi_wdata[64]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(64),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(64)
);
\m_axi_wdata[65]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(65),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(65)
);
\m_axi_wdata[66]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(66),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(66)
);
\m_axi_wdata[67]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(67),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(67)
);
\m_axi_wdata[68]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(68),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(68)
);
\m_axi_wdata[69]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(69),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(69)
);
\m_axi_wdata[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(6)
);
\m_axi_wdata[70]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(70),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(70)
);
\m_axi_wdata[71]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(71),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(71)
);
\m_axi_wdata[72]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(72),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(72)
);
\m_axi_wdata[73]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(73),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(73)
);
\m_axi_wdata[74]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(74),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(74)
);
\m_axi_wdata[75]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(75),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(75)
);
\m_axi_wdata[76]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(76),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(76)
);
\m_axi_wdata[77]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(77),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(77)
);
\m_axi_wdata[78]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(78),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(78)
);
\m_axi_wdata[79]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(79),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(79)
);
\m_axi_wdata[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(7)
);
\m_axi_wdata[80]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(80),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(80)
);
\m_axi_wdata[81]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(81),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(81)
);
\m_axi_wdata[82]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(82),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(82)
);
\m_axi_wdata[83]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(83),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(83)
);
\m_axi_wdata[84]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(84),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(84)
);
\m_axi_wdata[85]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(85),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(85)
);
\m_axi_wdata[86]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(86),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(86)
);
\m_axi_wdata[87]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(87),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(87)
);
\m_axi_wdata[88]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(88),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(88)
);
\m_axi_wdata[89]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(89),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(89)
);
\m_axi_wdata[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(8),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(8)
);
\m_axi_wdata[90]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(90),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(90)
);
\m_axi_wdata[91]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(91),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(91)
);
\m_axi_wdata[92]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(92),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(92)
);
\m_axi_wdata[93]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(93),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(93)
);
\m_axi_wdata[94]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(94),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(94)
);
\m_axi_wdata[95]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(95),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(95)
);
\m_axi_wdata[96]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(96),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(96)
);
\m_axi_wdata[97]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(97),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(97)
);
\m_axi_wdata[98]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(98),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(98)
);
\m_axi_wdata[99]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(99),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(99)
);
\m_axi_wdata[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wdata(9),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wdata(9)
);
\m_axi_wlast[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wlast(0),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wlast(0)
);
\m_axi_wstrb[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(0),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(0)
);
\m_axi_wstrb[10]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(10),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(10)
);
\m_axi_wstrb[11]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(11),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(11)
);
\m_axi_wstrb[12]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(12),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(12)
);
\m_axi_wstrb[13]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(13),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(13)
);
\m_axi_wstrb[14]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(14),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(14)
);
\m_axi_wstrb[15]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(15),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(15)
);
\m_axi_wstrb[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(1),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(1)
);
\m_axi_wstrb[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(2),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(2)
);
\m_axi_wstrb[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(3),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(3)
);
\m_axi_wstrb[4]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(4),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(4)
);
\m_axi_wstrb[5]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(5),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(5)
);
\m_axi_wstrb[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(6),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(6)
);
\m_axi_wstrb[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(7),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(7)
);
\m_axi_wstrb[8]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(8),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(8)
);
\m_axi_wstrb[9]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wstrb(9),
I1 => \^storage_data1_reg[0]_1\,
O => m_axi_wstrb(9)
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFEEEEEEEEEEEEE"
)
port map (
I0 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\,
I1 => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
I2 => \out\(2),
I3 => fifoaddr(2),
I4 => \^storage_data1_reg[0]_0\,
I5 => \FSM_onehot_state[3]_i_5_n_0\,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^e\(0),
D => m_valid_i_i_1_n_0,
Q => \^m_avalid\,
R => in1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
Q => \^storage_data1_reg[0]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ is
port (
\storage_data1_reg[0]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : out STD_LOGIC;
\storage_data1_reg[0]_1\ : out STD_LOGIC;
\storage_data1_reg[0]_2\ : out STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
push : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]\ : in STD_LOGIC;
in1 : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC;
p_10_in : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
m_valid_i_reg_1 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ : entity is "axi_data_fifo_v2_1_10_axic_reg_srl_fifo";
end \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\;
architecture STRUCTURE of \system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\ is
signal fifoaddr : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \^m_avalid\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_in3_out : STD_LOGIC;
signal \^storage_data1_reg[0]_0\ : STD_LOGIC;
signal \^storage_data1_reg[0]_1\ : STD_LOGIC;
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
begin
m_avalid <= \^m_avalid\;
m_valid_i_reg_0(0) <= \^m_valid_i_reg_0\(0);
\storage_data1_reg[0]_0\ <= \^storage_data1_reg[0]_0\;
\storage_data1_reg[0]_1\ <= \^storage_data1_reg[0]_1\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444044400000000"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0),
I1 => \^storage_data1_reg[0]_0\,
I2 => Q(0),
I3 => aa_sa_awvalid,
I4 => m_ready_d(0),
I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1),
O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0)
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800080008FF0800"
)
port map (
I0 => Q(0),
I1 => aa_sa_awvalid,
I2 => m_ready_d(0),
I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0),
I4 => p_0_in3_out,
I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1),
O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1)
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00BFFF"
)
port map (
I0 => m_ready_d(0),
I1 => aa_sa_awvalid,
I2 => Q(0),
I3 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0),
I4 => p_0_in3_out,
I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1),
O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2)
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF88F488F488F4"
)
port map (
I0 => \^storage_data1_reg[0]_0\,
I1 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1),
I2 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0),
I3 => \m_ready_d_reg[0]\,
I4 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2),
I5 => p_0_in3_out,
O => \^m_valid_i_reg_0\(0)
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002222A222"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1),
I1 => \^storage_data1_reg[0]_0\,
I2 => Q(0),
I3 => aa_sa_awvalid,
I4 => m_ready_d(0),
I5 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0),
O => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3)
);
\FSM_onehot_state[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_ready_d_reg[0]\,
I1 => fifoaddr(1),
I2 => \^storage_data1_reg[0]_0\,
I3 => fifoaddr(0),
I4 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2),
O => p_0_in3_out
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3FCDC032"
)
port map (
I0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1),
I1 => \m_ready_d_reg[0]\,
I2 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2),
I3 => \^storage_data1_reg[0]_0\,
I4 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFDDBFDF40224020"
)
port map (
I0 => fifoaddr(0),
I1 => \^storage_data1_reg[0]_0\,
I2 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2),
I3 => \m_ready_d_reg[0]\,
I4 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1),
I5 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.system_xbar_0_axi_data_fifo_v2_1_10_ndeep_srl
port map (
A(1 downto 0) => fifoaddr(1 downto 0),
aclk => aclk,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2),
m_avalid => \^m_avalid\,
m_select_enc_0 => m_select_enc_0,
m_valid_i_reg => m_valid_i_reg_1,
p_10_in => p_10_in,
push => push,
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
\storage_data1_reg[0]_0\ => \^storage_data1_reg[0]_0\,
\storage_data1_reg[0]_1\ => \^storage_data1_reg[0]_1\
);
m_valid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00F400F400F4"
)
port map (
I0 => \^storage_data1_reg[0]_0\,
I1 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1),
I2 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0),
I3 => \m_ready_d_reg[0]\,
I4 => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2),
I5 => p_0_in3_out,
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_valid_i_reg_0\(0),
D => m_valid_i_i_1_n_0,
Q => \^m_avalid\,
R => in1
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^m_avalid\,
I1 => m_select_enc_0,
I2 => p_10_in,
I3 => \^storage_data1_reg[0]_1\,
O => \storage_data1_reg[0]_2\
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
Q => \^storage_data1_reg[0]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice is
port (
p_58_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
st_mr_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_axi_rready[0]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[0]_0\ : out STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ : out STD_LOGIC;
\gen_arbiter.grant_hot_reg[0]\ : out STD_LOGIC;
st_mr_bmesg : out STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
active_target_enc_0 : in STD_LOGIC;
w_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
p_34_out : in STD_LOGIC;
active_target_enc_1 : in STD_LOGIC;
\gen_arbiter.m_target_hot_i_reg[0]\ : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_single_thread.active_target_hot_reg[0]\ : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]_1\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_hot_2 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
active_target_hot_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice;
architecture STRUCTURE of system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
p_1_in <= \^p_1_in\;
b_pipe: entity work.\system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1_3\
port map (
E(0) => E(0),
aclk => aclk,
active_target_enc_1 => active_target_enc_1,
active_target_hot(0) => active_target_hot(0),
aresetn => aresetn,
\gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\,
\gen_arbiter.qual_reg_reg[0]\ => \gen_arbiter.qual_reg_reg[0]\,
\gen_arbiter.qual_reg_reg[0]_0\ => \gen_arbiter.qual_reg_reg[0]_0\,
\gen_master_slots[0].w_issuing_cnt_reg[0]\ => \gen_master_slots[0].w_issuing_cnt_reg[0]\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_valid_i_reg_0 => \^m_valid_i_reg\,
p_1_in => \^p_1_in\,
p_34_out => p_34_out,
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => p_58_out,
s_ready_i_reg_1 => s_ready_i_reg,
sel_4 => sel_4,
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
w_issuing_cnt(4 downto 0) => w_issuing_cnt(4 downto 0)
);
r_pipe: entity work.\system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2_4\
port map (
Q(3 downto 0) => Q(3 downto 0),
aclk => aclk,
active_target_enc => active_target_enc,
active_target_enc_0 => active_target_enc_0,
active_target_hot_2(0) => active_target_hot_2(0),
active_target_hot_3(0) => active_target_hot_3(0),
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
\gen_arbiter.grant_hot_reg[0]\ => \gen_arbiter.grant_hot_reg[0]\,
\gen_arbiter.m_target_hot_i_reg[0]\ => \gen_arbiter.m_target_hot_i_reg[0]\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\(0) => \gen_master_slots[0].r_issuing_cnt_reg[0]\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ => \gen_master_slots[0].r_issuing_cnt_reg[0]_0\,
\gen_master_slots[0].r_issuing_cnt_reg[0]_1\ => \gen_master_slots[0].r_issuing_cnt_reg[0]_1\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0),
\gen_single_thread.active_target_hot_reg[0]\ => \gen_single_thread.active_target_hot_reg[0]\,
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(0) => m_axi_rid(0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
\m_payload_i_reg[0]_0\ => st_mr_rvalid(0),
p_1_in => \^p_1_in\,
s_axi_rdata(255 downto 0) => s_axi_rdata(255 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1 is
port (
p_34_out : out STD_LOGIC;
mi_bready_1 : out STD_LOGIC;
st_mr_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_1 : out STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : out STD_LOGIC;
st_mr_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_arbiter.qual_reg_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_arbiter.qual_reg_reg[0]\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[1]_0\ : out STD_LOGIC;
\gen_arbiter.qual_reg_reg[1]_1\ : out STD_LOGIC;
\gen_single_thread.accept_cnt_reg[1]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
\gen_axi.s_axi_bvalid_i_reg\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\gen_arbiter.m_valid_i_reg\ : in STD_LOGIC;
\gen_single_thread.active_target_enc_reg[0]\ : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_17_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
active_target_enc : in STD_LOGIC;
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[130]\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
\gen_single_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
sel_4_0 : in STD_LOGIC;
\gen_single_thread.accept_cnt_reg[0]_0\ : in STD_LOGIC;
active_target_enc_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
active_target_hot : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
p_11_in : in STD_LOGIC;
active_target_enc_2 : in STD_LOGIC;
p_16_in : in STD_LOGIC;
p_13_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1 : entity is "axi_register_slice_v2_1_11_axi_register_slice";
end system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1;
architecture STRUCTURE of system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1 is
begin
b_pipe: entity work.\system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized1\
port map (
aclk => aclk,
active_target_enc => active_target_enc,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_axi.s_axi_bvalid_i_reg\ => \gen_axi.s_axi_bvalid_i_reg\,
mi_bready_1 => mi_bready_1,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_34_out => p_34_out,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\system_xbar_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2\
port map (
Q(1 downto 0) => Q(1 downto 0),
aclk => aclk,
active_target_enc_1 => active_target_enc_1,
active_target_enc_2 => active_target_enc_2,
active_target_hot(0) => active_target_hot(0),
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\gen_arbiter.m_valid_i_reg\ => \gen_arbiter.m_valid_i_reg\,
\gen_arbiter.qual_reg_reg[0]\ => \gen_arbiter.qual_reg_reg[0]\,
\gen_arbiter.qual_reg_reg[1]\(1 downto 0) => \gen_arbiter.qual_reg_reg[1]\(1 downto 0),
\gen_arbiter.qual_reg_reg[1]_0\ => \gen_arbiter.qual_reg_reg[1]_0\,
\gen_arbiter.qual_reg_reg[1]_1\ => \gen_arbiter.qual_reg_reg[1]_1\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => st_mr_rvalid(0),
\gen_master_slots[1].r_issuing_cnt_reg[8]_0\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[1].r_issuing_cnt_reg[8]_1\ => st_mr_rlast(0),
\gen_single_thread.accept_cnt_reg[0]\ => \gen_single_thread.accept_cnt_reg[0]\,
\gen_single_thread.accept_cnt_reg[0]_0\ => \gen_single_thread.accept_cnt_reg[0]_0\,
\gen_single_thread.accept_cnt_reg[1]\ => \gen_single_thread.accept_cnt_reg[1]\,
\gen_single_thread.active_target_enc_reg[0]\ => \gen_single_thread.active_target_enc_reg[0]\,
\m_payload_i_reg[130]_0\ => \m_payload_i_reg[130]\,
\m_payload_i_reg[131]_0\ => st_mr_rid(0),
m_valid_i_reg_0(0) => m_valid_i_reg(0),
p_11_in => p_11_in,
p_13_in => p_13_in,
p_16_in => p_16_in,
p_1_in => p_1_in,
r_issuing_cnt(1 downto 0) => r_issuing_cnt(1 downto 0),
s_axi_arvalid(1 downto 0) => s_axi_arvalid(1 downto 0),
s_axi_rlast(1 downto 0) => s_axi_rlast(1 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rvalid(0) => s_axi_rvalid(0),
sel_4 => sel_4,
sel_4_0 => sel_4_0,
\skid_buffer_reg[130]_0\ => mi_rready_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_wdata_mux is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : out STD_LOGIC;
m_select_enc : out STD_LOGIC;
\storage_data1_reg[0]_0\ : out STD_LOGIC;
\storage_data1_reg[0]_1\ : out STD_LOGIC;
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
push : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC;
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
in1 : in STD_LOGIC;
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]_0\ : in STD_LOGIC;
\m_ready_d_reg[0]\ : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid_1 : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ : in STD_LOGIC;
p_0_out : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_wdata_mux : entity is "axi_crossbar_v2_1_12_wdata_mux";
end system_xbar_0_axi_crossbar_v2_1_12_wdata_mux;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_wdata_mux is
begin
\gen_wmux.wmux_aw_fifo\: entity work.\system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized0\
port map (
E(0) => E(0),
Q(0) => Q(0),
SR(0) => SR(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]_0\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]_0\,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0),
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\,
in1 => in1,
m_avalid => m_avalid,
m_avalid_1 => m_avalid_1,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wlast(0) => m_axi_wlast(0),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => \m_ready_d_reg[0]\,
m_select_enc_0 => m_select_enc_0,
m_valid_i_reg_0 => m_valid_i_reg,
m_valid_i_reg_1 => m_valid_i_reg_0,
\out\(2 downto 0) => \out\(2 downto 0),
p_0_out => p_0_out,
push => push,
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_axi_wvalid(0) => s_axi_wvalid(0),
\storage_data1_reg[0]_0\ => \storage_data1_reg[0]\,
\storage_data1_reg[0]_1\ => m_select_enc,
\storage_data1_reg[0]_2\ => \storage_data1_reg[0]_0\,
\storage_data1_reg[0]_3\ => \storage_data1_reg[0]_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : out STD_LOGIC;
m_select_enc : out STD_LOGIC;
\storage_data1_reg[0]_0\ : out STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
push : in STD_LOGIC;
aclk : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[0]\ : in STD_LOGIC;
in1 : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : in STD_LOGIC;
p_10_in : in STD_LOGIC;
m_select_enc_0 : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ : entity is "axi_crossbar_v2_1_12_wdata_mux";
end \system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\;
architecture STRUCTURE of \system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\ is
begin
\gen_wmux.wmux_aw_fifo\: entity work.\system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo__parameterized1\
port map (
Q(0) => Q(0),
SR(0) => SR(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0),
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0),
in1 => in1,
m_avalid => m_avalid,
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => \m_ready_d_reg[0]\,
m_select_enc_0 => m_select_enc_0,
m_valid_i_reg_0(0) => m_valid_i_reg(0),
m_valid_i_reg_1 => m_valid_i_reg_0,
p_10_in => p_10_in,
push => push,
\storage_data1_reg[0]_0\ => \storage_data1_reg[0]\,
\storage_data1_reg[0]_1\ => m_select_enc,
\storage_data1_reg[0]_2\ => \storage_data1_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_wdata_router is
port (
\gen_arbiter.m_target_hot_i_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : out STD_LOGIC;
ss_wr_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_select_enc : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\gen_axi.s_axi_wready_i_reg\ : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axi.s_axi_bvalid_i_reg\ : out STD_LOGIC;
\storage_data1_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
sel_4 : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_0 : in STD_LOGIC;
write_cs : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_avalid_0 : in STD_LOGIC;
m_select_enc_1 : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid_2 : in STD_LOGIC;
m_select_enc_3 : in STD_LOGIC;
m_valid_i_reg_1 : in STD_LOGIC;
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_wdata_router : entity is "axi_crossbar_v2_1_12_wdata_router";
end system_xbar_0_axi_crossbar_v2_1_12_wdata_router;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_wdata_router is
begin
wrouter_aw_fifo: entity work.system_xbar_0_axi_data_fifo_v2_1_10_axic_reg_srl_fifo
port map (
\FSM_onehot_state_reg[2]_0\ => m_avalid,
SR(0) => SS(0),
aclk => aclk,
aresetn_d_reg(0) => SR(0),
\gen_arbiter.m_target_hot_i_reg[1]\(0) => \gen_arbiter.m_target_hot_i_reg[1]\(0),
\gen_axi.s_axi_bvalid_i_reg\ => \gen_axi.s_axi_bvalid_i_reg\,
\gen_axi.s_axi_wready_i_reg\ => \gen_axi.s_axi_wready_i_reg\,
m_avalid_0 => m_avalid_0,
m_avalid_2 => m_avalid_2,
m_axi_wready(0) => m_axi_wready(0),
m_axi_wvalid(0) => m_axi_wvalid(0),
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_select_enc_1 => m_select_enc_1,
m_select_enc_3 => m_select_enc_3,
m_valid_i_reg_0 => m_valid_i_reg,
m_valid_i_reg_1 => m_valid_i_reg_0,
m_valid_i_reg_2 => m_valid_i_reg_1,
s_axi_awaddr(3 downto 0) => s_axi_awaddr(3 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg_0 => ss_wr_awready(0),
s_ready_i_reg_1 => s_ready_i_reg,
sel_4 => sel_4,
\storage_data1_reg[0]_0\ => m_select_enc,
\storage_data1_reg[0]_1\ => \storage_data1_reg[0]\,
write_cs(1 downto 0) => write_cs(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_crossbar is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_axi_rready[0]\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
areset_d1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 57 downto 0 );
\s_axi_awready[0]\ : out STD_LOGIC;
\s_axi_arready[0]\ : out STD_LOGIC;
\s_axi_arready[1]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
\m_axi_awqos[3]\ : out STD_LOGIC_VECTOR ( 56 downto 0 );
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 24 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_crossbar : entity is "axi_crossbar_v2_1_12_crossbar";
end system_xbar_0_axi_crossbar_v2_1_12_crossbar;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 57 downto 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 1 to 1 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal active_target_enc : STD_LOGIC;
signal active_target_enc_10 : STD_LOGIC;
signal active_target_enc_6 : STD_LOGIC;
signal active_target_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_target_hot_5 : STD_LOGIC_VECTOR ( 0 to 0 );
signal active_target_hot_9 : STD_LOGIC_VECTOR ( 0 to 0 );
signal addr_arbiter_ar_n_2 : STD_LOGIC;
signal addr_arbiter_ar_n_62 : STD_LOGIC;
signal addr_arbiter_ar_n_64 : STD_LOGIC;
signal addr_arbiter_ar_n_65 : STD_LOGIC;
signal addr_arbiter_ar_n_67 : STD_LOGIC;
signal addr_arbiter_ar_n_68 : STD_LOGIC;
signal addr_arbiter_ar_n_69 : STD_LOGIC;
signal addr_arbiter_ar_n_70 : STD_LOGIC;
signal addr_arbiter_ar_n_72 : STD_LOGIC;
signal addr_arbiter_ar_n_74 : STD_LOGIC;
signal addr_arbiter_ar_n_77 : STD_LOGIC;
signal addr_arbiter_aw_n_10 : STD_LOGIC;
signal addr_arbiter_aw_n_11 : STD_LOGIC;
signal addr_arbiter_aw_n_12 : STD_LOGIC;
signal addr_arbiter_aw_n_13 : STD_LOGIC;
signal addr_arbiter_aw_n_14 : STD_LOGIC;
signal addr_arbiter_aw_n_18 : STD_LOGIC;
signal addr_arbiter_aw_n_2 : STD_LOGIC;
signal addr_arbiter_aw_n_20 : STD_LOGIC;
signal addr_arbiter_aw_n_21 : STD_LOGIC;
signal addr_arbiter_aw_n_22 : STD_LOGIC;
signal addr_arbiter_aw_n_23 : STD_LOGIC;
signal addr_arbiter_aw_n_3 : STD_LOGIC;
signal addr_arbiter_aw_n_6 : STD_LOGIC;
signal addr_arbiter_aw_n_7 : STD_LOGIC;
signal addr_arbiter_aw_n_9 : STD_LOGIC;
signal \^areset_d1\ : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\ : STD_LOGIC;
signal \gen_decerr_slave.decerr_slave_inst_n_10\ : STD_LOGIC;
signal \gen_decerr_slave.decerr_slave_inst_n_9\ : STD_LOGIC;
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_267\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_268\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_269\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_270\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_271\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_272\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_273\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_4\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_10\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_11\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_7\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_8\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_9\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_4\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_4\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_2\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_5\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_6\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_8\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w_n_9\ : STD_LOGIC;
signal \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_4\ : STD_LOGIC;
signal \gen_wmux.wmux_aw_fifo/p_0_out\ : STD_LOGIC;
signal \gen_wmux.wmux_aw_fifo/push\ : STD_LOGIC;
signal \gen_wmux.wmux_aw_fifo/push_1\ : STD_LOGIC;
signal grant_hot1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m_avalid : STD_LOGIC;
signal m_avalid_4 : STD_LOGIC;
signal m_avalid_8 : STD_LOGIC;
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_11 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_select_enc : STD_LOGIC;
signal m_select_enc_3 : STD_LOGIC;
signal m_select_enc_7 : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 1 to 1 );
signal mi_awready : STD_LOGIC_VECTOR ( 1 to 1 );
signal mi_bready_1 : STD_LOGIC;
signal mi_rready_1 : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_34_out : STD_LOGIC;
signal p_58_out : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 8 downto 0 );
signal reset : STD_LOGIC;
signal \^s_axi_arready[0]\ : STD_LOGIC;
signal \^s_axi_arready[1]\ : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s_axi_rlast_i0 : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal splitter_aw_mi_n_0 : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC_VECTOR ( 0 to 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rlast : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_rvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 8 downto 0 );
signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
Q(57 downto 0) <= \^q\(57 downto 0);
areset_d1 <= \^areset_d1\;
\s_axi_arready[0]\ <= \^s_axi_arready[0]\;
\s_axi_arready[1]\ <= \^s_axi_arready[1]\;
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
s_axi_rlast(1 downto 0) <= \^s_axi_rlast\(1 downto 0);
s_axi_rvalid(1 downto 0) <= \^s_axi_rvalid\(1 downto 0);
addr_arbiter_ar: entity work.system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter
port map (
D(2) => addr_arbiter_ar_n_68,
D(1) => addr_arbiter_ar_n_69,
D(0) => addr_arbiter_ar_n_70,
Q(57 downto 0) => \^q\(57 downto 0),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
active_target_enc => active_target_enc,
active_target_enc_2 => active_target_enc_10,
active_target_hot(0) => active_target_hot(0),
active_target_hot_1(0) => active_target_hot_9(0),
aresetn_d => aresetn_d,
\gen_arbiter.qual_reg_reg[1]_0\ => addr_arbiter_ar_n_77,
\gen_axi.read_cnt_reg[5]\ => \gen_decerr_slave.decerr_slave_inst_n_9\,
\gen_axi.s_axi_rid_i_reg[0]\ => addr_arbiter_ar_n_2,
\gen_axi.s_axi_rid_i_reg[0]_0\(0) => aa_mi_artarget_hot(1),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => addr_arbiter_ar_n_74,
\gen_master_slots[0].r_issuing_cnt_reg[3]\ => \gen_master_slots[1].reg_slice_mi_n_10\,
\gen_master_slots[0].r_issuing_cnt_reg[3]_0\(3 downto 0) => r_issuing_cnt(3 downto 0),
\gen_master_slots[0].r_issuing_cnt_reg[3]_1\ => \gen_master_slots[1].reg_slice_mi_n_8\,
\gen_master_slots[0].r_issuing_cnt_reg[3]_2\(1) => \gen_master_slots[1].reg_slice_mi_n_6\,
\gen_master_slots[0].r_issuing_cnt_reg[3]_2\(0) => \gen_master_slots[1].reg_slice_mi_n_7\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => addr_arbiter_ar_n_72,
\gen_master_slots[1].r_issuing_cnt_reg[8]_0\ => \gen_master_slots[1].reg_slice_mi_n_9\,
\gen_single_thread.accept_cnt_reg[0]\ => \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_4\,
\gen_single_thread.accept_cnt_reg[0]_0\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_4\,
\gen_single_thread.active_target_enc_reg[0]\ => addr_arbiter_ar_n_64,
\gen_single_thread.active_target_enc_reg[0]_0\ => addr_arbiter_ar_n_67,
\gen_single_thread.active_target_hot_reg[0]\ => addr_arbiter_ar_n_62,
\gen_single_thread.active_target_hot_reg[0]_0\ => addr_arbiter_ar_n_65,
\gen_single_thread.active_target_hot_reg[0]_1\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
m_axi_arready(0) => m_axi_arready(0),
m_axi_arvalid(0) => m_axi_arvalid(0),
\m_payload_i_reg[130]\(0) => st_mr_rlast(0),
m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_273\,
mi_arready(0) => mi_arready(1),
p_11_in => p_11_in,
p_16_in => p_16_in,
s_axi_araddr(63 downto 0) => s_axi_araddr(63 downto 0),
s_axi_arburst(3 downto 0) => s_axi_arburst(3 downto 0),
s_axi_arcache(7 downto 0) => s_axi_arcache(7 downto 0),
s_axi_arlen(15 downto 0) => s_axi_arlen(15 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(5 downto 0) => s_axi_arprot(5 downto 0),
s_axi_arqos(7 downto 0) => s_axi_arqos(7 downto 0),
\s_axi_arready[0]\ => \^s_axi_arready[0]\,
\s_axi_arready[1]\ => \^s_axi_arready[1]\,
s_axi_arsize(5 downto 0) => s_axi_arsize(5 downto 0),
s_axi_arvalid(1 downto 0) => s_axi_arvalid(1 downto 0),
s_axi_rlast_i0 => s_axi_rlast_i0,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\,
sel_4_0 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
st_mr_rvalid(0) => st_mr_rvalid(0)
);
addr_arbiter_aw: entity work.system_xbar_0_axi_crossbar_v2_1_12_addr_arbiter_0
port map (
D(0) => addr_arbiter_aw_n_2,
Q(1 downto 0) => aa_mi_awtarget_hot(1 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axi.s_axi_awready_i_reg\ => splitter_aw_mi_n_0,
\gen_master_slots[0].w_issuing_cnt_reg[0]\ => addr_arbiter_aw_n_12,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => addr_arbiter_aw_n_9,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => addr_arbiter_aw_n_10,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => addr_arbiter_aw_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]_0\(3 downto 0) => w_issuing_cnt(3 downto 0),
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0),
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => addr_arbiter_aw_n_13,
\gen_rep[0].fifoaddr_reg[0]\ => addr_arbiter_aw_n_21,
\gen_rep[0].fifoaddr_reg[0]_0\ => addr_arbiter_aw_n_23,
\gen_rep[0].fifoaddr_reg[2]\ => addr_arbiter_aw_n_18,
grant_hot1(0) => grant_hot1(0),
\m_axi_awqos[3]\(56 downto 0) => \m_axi_awqos[3]\(56 downto 0),
m_axi_awready(0) => m_axi_awready(0),
m_axi_awvalid(0) => m_axi_awvalid(0),
m_ready_d(1 downto 0) => m_ready_d_11(1 downto 0),
m_ready_d_1(0) => m_ready_d(0),
\m_ready_d_reg[0]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
\m_ready_d_reg[1]\ => addr_arbiter_aw_n_14,
m_valid_i_reg => addr_arbiter_aw_n_3,
m_valid_i_reg_0 => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_0\,
m_valid_i_reg_1 => \gen_master_slots[0].reg_slice_mi_n_268\,
mi_awready(0) => mi_awready(1),
\out\(2 downto 0) => \out\(2 downto 0),
p_0_out => \gen_wmux.wmux_aw_fifo/p_0_out\,
push => \gen_wmux.wmux_aw_fifo/push_1\,
push_0 => \gen_wmux.wmux_aw_fifo/push\,
\s_axi_awaddr[28]\(0) => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_0\,
\s_axi_awqos[3]\(56 downto 32) => D(24 downto 0),
\s_axi_awqos[3]\(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\,
ss_aa_awready => ss_aa_awready,
\storage_data1_reg[0]\ => addr_arbiter_aw_n_6,
\storage_data1_reg[0]_0\ => addr_arbiter_aw_n_7,
\storage_data1_reg[0]_1\ => addr_arbiter_aw_n_20,
\storage_data1_reg[0]_2\ => addr_arbiter_aw_n_22,
\storage_data1_reg[0]_3\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_0\
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.system_xbar_0_axi_crossbar_v2_1_12_decerr_slave
port map (
Q(7 downto 0) => \^q\(40 downto 33),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
active_target_enc => active_target_enc_6,
aresetn_d => aresetn_d,
\gen_arbiter.m_mesg_i_reg[0]\ => addr_arbiter_ar_n_2,
\gen_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_13,
\gen_arbiter.m_target_hot_i_reg[1]_0\(0) => aa_mi_artarget_hot(1),
\gen_axi.s_axi_arready_i_reg_0\ => \gen_decerr_slave.decerr_slave_inst_n_9\,
\gen_axi.write_cs_reg[1]_0\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_6\,
m_valid_i_reg => \gen_decerr_slave.decerr_slave_inst_n_10\,
mi_arready(0) => mi_arready(1),
mi_awready(0) => mi_awready(1),
mi_bready_1 => mi_bready_1,
mi_rready_1 => mi_rready_1,
p_10_in => p_10_in,
p_11_in => p_11_in,
p_13_in => p_13_in,
p_16_in => p_16_in,
p_17_in => p_17_in,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rlast_i0 => s_axi_rlast_i0,
\storage_data1_reg[0]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_8\,
write_cs(1 downto 0) => write_cs(1 downto 0)
);
\gen_master_slots[0].gen_mi_write.wdata_mux_w\: entity work.system_xbar_0_axi_crossbar_v2_1_12_wdata_mux
port map (
E(0) => E(0),
Q(0) => aa_mi_awtarget_hot(0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => addr_arbiter_aw_n_6,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => addr_arbiter_aw_n_3,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]_0\ => addr_arbiter_aw_n_20,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0),
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\ => addr_arbiter_aw_n_18,
in1 => \^areset_d1\,
m_avalid => m_avalid,
m_avalid_1 => m_avalid_8,
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wlast(0) => m_axi_wlast(0),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_ready_d(0) => m_ready_d_11(0),
\m_ready_d_reg[0]\ => addr_arbiter_aw_n_21,
m_select_enc => m_select_enc,
m_select_enc_0 => m_select_enc_7,
m_valid_i_reg => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_9\,
m_valid_i_reg_0 => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_4\,
\out\(2 downto 0) => \out\(2 downto 0),
p_0_out => \gen_wmux.wmux_aw_fifo/p_0_out\,
push => \gen_wmux.wmux_aw_fifo/push_1\,
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_axi_wvalid(0) => s_axi_wvalid(0),
\storage_data1_reg[0]\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_0\,
\storage_data1_reg[0]_0\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_4\,
\storage_data1_reg[0]_1\ => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_271\,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_271\,
D => addr_arbiter_ar_n_70,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_271\,
D => addr_arbiter_ar_n_69,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_271\,
D => addr_arbiter_ar_n_68,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice
port map (
E(0) => \gen_master_slots[0].reg_slice_mi_n_267\,
Q(3) => st_mr_rid(0),
Q(2) => st_mr_rlast(0),
Q(1 downto 0) => st_mr_rmesg(1 downto 0),
aclk => aclk,
active_target_enc => active_target_enc_10,
active_target_enc_0 => active_target_enc,
active_target_enc_1 => active_target_enc_6,
active_target_hot(0) => active_target_hot_5(0),
active_target_hot_2(0) => active_target_hot(0),
active_target_hot_3(0) => active_target_hot_9(0),
aresetn => aresetn,
\gen_arbiter.grant_hot_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_273\,
\gen_arbiter.m_target_hot_i_reg[0]\ => addr_arbiter_ar_n_74,
\gen_arbiter.m_valid_i_reg\ => addr_arbiter_aw_n_12,
\gen_arbiter.qual_reg_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_269\,
\gen_arbiter.qual_reg_reg[0]_0\ => \gen_master_slots[0].reg_slice_mi_n_270\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\(0) => \gen_master_slots[0].reg_slice_mi_n_271\,
\gen_master_slots[0].r_issuing_cnt_reg[0]_0\ => \gen_master_slots[0].reg_slice_mi_n_272\,
\gen_master_slots[0].r_issuing_cnt_reg[0]_1\ => addr_arbiter_ar_n_77,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => r_issuing_cnt(3 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_268\,
\gen_single_thread.active_target_hot_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(0) => m_axi_rid(0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg => \gen_master_slots[0].reg_slice_mi_n_1\,
p_1_in => p_1_in,
p_34_out => p_34_out,
p_58_out => p_58_out,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rdata(255 downto 0) => s_axi_rdata(255 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_ready_i_reg => \gen_master_slots[0].reg_slice_mi_n_6\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\,
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
st_mr_rvalid(0) => st_mr_rvalid(0),
w_issuing_cnt(4) => w_issuing_cnt(8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_267\,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_267\,
D => addr_arbiter_aw_n_11,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_267\,
D => addr_arbiter_aw_n_10,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_267\,
D => addr_arbiter_aw_n_9,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w\: entity work.\system_xbar_0_axi_crossbar_v2_1_12_wdata_mux__parameterized0\
port map (
Q(0) => aa_mi_awtarget_hot(1),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ => addr_arbiter_aw_n_7,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ => addr_arbiter_aw_n_22,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3 downto 0),
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2 downto 0),
in1 => \^areset_d1\,
m_avalid => m_avalid_4,
m_ready_d(0) => m_ready_d_11(0),
\m_ready_d_reg[0]\ => addr_arbiter_aw_n_23,
m_select_enc => m_select_enc_3,
m_select_enc_0 => m_select_enc_7,
m_valid_i_reg(0) => m_valid_i_reg(0),
m_valid_i_reg_0 => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_5\,
p_10_in => p_10_in,
push => \gen_wmux.wmux_aw_fifo/push\,
\storage_data1_reg[0]\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_0\,
\storage_data1_reg[0]_0\ => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_4\
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_master_slots[1].reg_slice_mi_n_4\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.system_xbar_0_axi_register_slice_v2_1_11_axi_register_slice_1
port map (
Q(1) => st_mr_rid(0),
Q(0) => st_mr_rlast(0),
aclk => aclk,
active_target_enc => active_target_enc_6,
active_target_enc_1 => active_target_enc,
active_target_enc_2 => active_target_enc_10,
active_target_hot(0) => active_target_hot(0),
\aresetn_d_reg[1]\ => \gen_master_slots[0].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[0].reg_slice_mi_n_6\,
\gen_arbiter.m_valid_i_reg\ => addr_arbiter_ar_n_72,
\gen_arbiter.qual_reg_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_8\,
\gen_arbiter.qual_reg_reg[1]\(1) => \gen_master_slots[1].reg_slice_mi_n_6\,
\gen_arbiter.qual_reg_reg[1]\(0) => \gen_master_slots[1].reg_slice_mi_n_7\,
\gen_arbiter.qual_reg_reg[1]_0\ => \gen_master_slots[1].reg_slice_mi_n_9\,
\gen_arbiter.qual_reg_reg[1]_1\ => \gen_master_slots[1].reg_slice_mi_n_10\,
\gen_axi.s_axi_bvalid_i_reg\ => \gen_decerr_slave.decerr_slave_inst_n_10\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => addr_arbiter_ar_n_77,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_4\,
\gen_single_thread.accept_cnt_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_4\,
\gen_single_thread.accept_cnt_reg[0]_0\ => \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_4\,
\gen_single_thread.accept_cnt_reg[1]\ => \gen_master_slots[1].reg_slice_mi_n_11\,
\gen_single_thread.active_target_enc_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\m_payload_i_reg[130]\ => \gen_master_slots[0].reg_slice_mi_n_272\,
m_valid_i_reg(0) => st_mr_rvalid(0),
mi_bready_1 => mi_bready_1,
mi_rready_1 => mi_rready_1,
p_11_in => p_11_in,
p_13_in => p_13_in,
p_16_in => p_16_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_34_out => p_34_out,
r_issuing_cnt(1) => r_issuing_cnt(8),
r_issuing_cnt(0) => r_issuing_cnt(3),
s_axi_arvalid(1 downto 0) => s_axi_arvalid(1 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_rlast(1 downto 0) => \^s_axi_rlast\(1 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rvalid(0) => \^s_axi_rvalid\(0),
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
sel_4_0 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_0\,
st_mr_rid(0) => st_mr_rid(1),
st_mr_rlast(0) => st_mr_rlast(1),
st_mr_rvalid(0) => st_mr_rvalid(1)
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.system_xbar_0_axi_crossbar_v2_1_12_si_transactor
port map (
Q(2) => st_mr_rid(0),
Q(1 downto 0) => st_mr_rmesg(1 downto 0),
SR(0) => reset,
aclk => aclk,
active_target_enc => active_target_enc,
active_target_enc_1 => active_target_enc_10,
active_target_hot(0) => active_target_hot(0),
active_target_hot_0(0) => active_target_hot_9(0),
\gen_arbiter.qual_reg_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_4\,
\gen_arbiter.s_ready_i_reg[0]\ => addr_arbiter_ar_n_64,
\gen_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_62,
\gen_arbiter.s_ready_i_reg[0]_1\ => \^s_axi_arready[0]\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5\,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6\,
\m_payload_i_reg[130]\ => \gen_master_slots[1].reg_slice_mi_n_11\,
s_axi_araddr(3 downto 0) => s_axi_araddr(31 downto 28),
s_axi_rlast(0) => \^s_axi_rlast\(0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid(0) => \^s_axi_rvalid\(0),
st_mr_rid(0) => st_mr_rid(1)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized0\
port map (
D(0) => addr_arbiter_aw_n_2,
SR(0) => reset,
aclk => aclk,
active_target_enc => active_target_enc_6,
active_target_hot(0) => active_target_hot_5(0),
\gen_arbiter.m_target_hot_i_reg[1]\ => addr_arbiter_aw_n_13,
\gen_arbiter.qual_reg_reg[0]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_4\,
\gen_arbiter.s_ready_i_reg[0]\ => \^s_axi_awready[0]\,
\gen_master_slots[0].w_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_270\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2\,
\gen_single_thread.active_target_enc_reg[0]_0\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_2\,
\gen_single_thread.active_target_hot_reg[0]_0\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_0\,
grant_hot1(0) => grant_hot1(0),
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
p_34_out => p_34_out,
p_58_out => p_58_out,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\,
ss_aa_awready => ss_aa_awready,
ss_wr_awready(0) => ss_wr_awready(0),
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
w_issuing_cnt(0) => w_issuing_cnt(8)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.system_xbar_0_axi_crossbar_v2_1_12_splitter
port map (
aclk => aclk,
active_target_enc => active_target_enc_6,
active_target_hot(0) => active_target_hot_5(0),
aresetn_d => aresetn_d,
\gen_arbiter.qual_reg_reg[0]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3\,
\gen_master_slots[1].w_issuing_cnt_reg[8]\ => \gen_master_slots[0].reg_slice_mi_n_269\,
\gen_rep[0].fifoaddr_reg[0]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_6\,
\gen_single_thread.accept_cnt_reg[3]\ => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_4\,
\gen_single_thread.active_target_enc_reg[0]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_2\,
\gen_single_thread.active_target_hot_reg[0]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_0\,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
s_axi_awaddr(3 downto 0) => s_axi_awaddr(31 downto 28),
\s_axi_awready[0]\ => \^s_axi_awready[0]\,
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready(0) => ss_wr_awready(0)
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.system_xbar_0_axi_crossbar_v2_1_12_wdata_router
port map (
SR(0) => reset,
SS(0) => \^areset_d1\,
aclk => aclk,
\gen_arbiter.m_target_hot_i_reg[1]\(0) => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_0\,
\gen_axi.s_axi_bvalid_i_reg\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_8\,
\gen_axi.s_axi_wready_i_reg\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_6\,
m_avalid => m_avalid_8,
m_avalid_0 => m_avalid_4,
m_avalid_2 => m_avalid,
m_axi_wready(0) => m_axi_wready(0),
m_axi_wvalid(0) => m_axi_wvalid(0),
m_ready_d(0) => m_ready_d(1),
\m_ready_d_reg[1]\ => \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_6\,
m_select_enc => m_select_enc_7,
m_select_enc_1 => m_select_enc_3,
m_select_enc_3 => m_select_enc,
m_valid_i_reg => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_4\,
m_valid_i_reg_0 => \gen_master_slots[0].gen_mi_write.wdata_mux_w_n_5\,
m_valid_i_reg_1 => \gen_master_slots[1].gen_mi_write.wdata_mux_w_n_4\,
s_axi_awaddr(3 downto 0) => s_axi_awaddr(31 downto 28),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_5\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[0].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_2\,
ss_wr_awready(0) => ss_wr_awready(0),
\storage_data1_reg[0]\ => \gen_slave_slots[0].gen_si_write.wdata_router_w_n_9\,
write_cs(1 downto 0) => write_cs(1 downto 0)
);
\gen_slave_slots[1].gen_si_read.si_transactor_ar\: entity work.\system_xbar_0_axi_crossbar_v2_1_12_si_transactor__parameterized1\
port map (
Q(3) => st_mr_rid(0),
Q(2) => st_mr_rlast(0),
Q(1 downto 0) => st_mr_rmesg(1 downto 0),
SR(0) => reset,
aclk => aclk,
active_target_enc => active_target_enc_10,
active_target_hot(0) => active_target_hot_9(0),
\gen_arbiter.qual_reg_reg[1]\ => \gen_slave_slots[1].gen_si_read.si_transactor_ar_n_4\,
\gen_arbiter.s_ready_i_reg[1]\ => addr_arbiter_ar_n_67,
\gen_arbiter.s_ready_i_reg[1]_0\ => addr_arbiter_ar_n_65,
\gen_arbiter.s_ready_i_reg[1]_1\ => \^s_axi_arready[1]\,
s_axi_araddr(3 downto 0) => s_axi_araddr(63 downto 60),
s_axi_rlast(0) => \^s_axi_rlast\(1),
s_axi_rready(0) => s_axi_rready(1),
s_axi_rresp(1 downto 0) => s_axi_rresp(3 downto 2),
s_axi_rvalid(0) => \^s_axi_rvalid\(1),
st_mr_rid(0) => st_mr_rid(1),
st_mr_rlast(0) => st_mr_rlast(1),
st_mr_rvalid(1 downto 0) => st_mr_rvalid(1 downto 0)
);
splitter_aw_mi: entity work.system_xbar_0_axi_crossbar_v2_1_12_splitter_2
port map (
Q(1 downto 0) => aa_mi_awtarget_hot(1 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_arbiter.m_target_hot_i_reg[0]\ => addr_arbiter_aw_n_14,
m_axi_awready(0) => m_axi_awready(0),
m_ready_d(1 downto 0) => m_ready_d_11(1 downto 0),
\m_ready_d_reg[1]_0\ => splitter_aw_mi_n_0,
mi_awready(0) => mi_awready(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 128;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "artix7";
attribute C_M_AXI_ADDR_WIDTH : integer;
attribute C_M_AXI_ADDR_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 28;
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000010000000000000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : integer;
attribute C_M_AXI_READ_CONNECTIVITY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 3;
attribute C_M_AXI_READ_ISSUING : integer;
attribute C_M_AXI_READ_ISSUING of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 8;
attribute C_M_AXI_SECURE : integer;
attribute C_M_AXI_SECURE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_M_AXI_WRITE_CONNECTIVITY : integer;
attribute C_M_AXI_WRITE_CONNECTIVITY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_M_AXI_WRITE_ISSUING : integer;
attribute C_M_AXI_WRITE_ISSUING of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 8;
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 2;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : string;
attribute C_S_AXI_ARB_PRIORITY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_BASE_ID : string;
attribute C_S_AXI_BASE_ID of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000100000000000000000000000000000000";
attribute C_S_AXI_READ_ACCEPTANCE : string;
attribute C_S_AXI_READ_ACCEPTANCE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000001000000000000000000000000000000010";
attribute C_S_AXI_SINGLE_THREAD : string;
attribute C_S_AXI_SINGLE_THREAD of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_THREAD_ID_WIDTH : string;
attribute C_S_AXI_THREAD_ID_WIDTH of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_WRITE_ACCEPTANCE : string;
attribute C_S_AXI_WRITE_ACCEPTANCE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "64'b0000000000000000000000000000001000000000000000000000000000001000";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "axi_crossbar_v2_1_12_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "artix7";
attribute P_INCR : string;
attribute P_INCR of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "32'b00000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "1'b1";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "1'b1";
attribute P_ONES : string;
attribute P_ONES of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "2'b11";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar : entity is "2'b01";
end system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar;
architecture STRUCTURE of system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\ : STD_LOGIC;
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : signal is "yes";
signal \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : signal is "yes";
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\ : STD_LOGIC;
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\ : signal is "yes";
signal \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : STD_LOGIC;
attribute RTL_KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\ : signal is "yes";
signal \gen_samd.crossbar_samd_n_383\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_384\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_385\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_386\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_387\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_388\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_389\ : STD_LOGIC;
signal \gen_samd.crossbar_samd_n_390\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute KEEP : string;
attribute KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : label is "yes";
attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\ : label is "yes";
begin
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_awready(1) <= \<const0>\;
s_axi_awready(0) <= \^s_axi_awready\(0);
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(3) <= \<const0>\;
s_axi_bresp(2) <= \<const0>\;
s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0);
s_axi_buser(1) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid(1) <= \<const0>\;
s_axi_bvalid(0) <= \^s_axi_bvalid\(0);
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_ruser(1) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready(1) <= \<const0>\;
s_axi_wready(0) <= \^s_axi_wready\(0);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_386\,
Q => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\,
S => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_385\,
Q => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\,
R => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_384\,
Q => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\,
R => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_383\,
Q => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\,
R => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_390\,
Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\,
S => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_389\,
Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\,
R => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_388\,
Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[2]\,
R => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
D => \gen_samd.crossbar_samd_n_387\,
Q => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\,
R => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\
);
\gen_samd.crossbar_samd\: entity work.system_xbar_0_axi_crossbar_v2_1_12_crossbar
port map (
D(24 downto 21) => s_axi_awqos(3 downto 0),
D(20 downto 17) => s_axi_awcache(3 downto 0),
D(16 downto 15) => s_axi_awburst(1 downto 0),
D(14 downto 12) => s_axi_awprot(2 downto 0),
D(11) => s_axi_awlock(0),
D(10 downto 8) => s_axi_awsize(2 downto 0),
D(7 downto 0) => s_axi_awlen(7 downto 0),
E(0) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
Q(57 downto 54) => m_axi_arqos(3 downto 0),
Q(53 downto 50) => m_axi_arcache(3 downto 0),
Q(49 downto 48) => m_axi_arburst(1 downto 0),
Q(47 downto 45) => m_axi_arprot(2 downto 0),
Q(44) => m_axi_arlock(0),
Q(43 downto 41) => m_axi_arsize(2 downto 0),
Q(40 downto 33) => m_axi_arlen(7 downto 0),
Q(32 downto 1) => m_axi_araddr(31 downto 0),
Q(0) => m_axi_arid(0),
aclk => aclk,
areset_d1 => \gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/areset_d1\,
aresetn => aresetn,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3) => \gen_samd.crossbar_samd_n_383\,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2) => \gen_samd.crossbar_samd_n_384\,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1) => \gen_samd.crossbar_samd_n_385\,
\gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0) => \gen_samd.crossbar_samd_n_386\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(3) => \gen_samd.crossbar_samd_n_387\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(2) => \gen_samd.crossbar_samd_n_388\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(1) => \gen_samd.crossbar_samd_n_389\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]\(0) => \gen_samd.crossbar_samd_n_390\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(2) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(1) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\,
\gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg[3]_0\(0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\,
m_axi_arready(0) => m_axi_arready(0),
m_axi_arvalid(0) => m_axi_arvalid(0),
\m_axi_awqos[3]\(56 downto 53) => m_axi_awqos(3 downto 0),
\m_axi_awqos[3]\(52 downto 49) => m_axi_awcache(3 downto 0),
\m_axi_awqos[3]\(48 downto 47) => m_axi_awburst(1 downto 0),
\m_axi_awqos[3]\(46 downto 44) => m_axi_awprot(2 downto 0),
\m_axi_awqos[3]\(43) => m_axi_awlock(0),
\m_axi_awqos[3]\(42 downto 40) => m_axi_awsize(2 downto 0),
\m_axi_awqos[3]\(39 downto 32) => m_axi_awlen(7 downto 0),
\m_axi_awqos[3]\(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awready(0) => m_axi_awready(0),
m_axi_awvalid(0) => m_axi_awvalid(0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(0) => m_axi_rid(0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => m_axi_rready(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wlast(0) => m_axi_wlast(0),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wvalid(0) => m_axi_wvalid(0),
m_valid_i_reg(0) => \gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/m_valid_i\,
\out\(2) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/FSM_onehot_state_reg_n_0_[3]\,
\out\(1) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_0_in6_in\,
\out\(0) => \gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/p_7_in\,
s_axi_araddr(63 downto 0) => s_axi_araddr(63 downto 0),
s_axi_arburst(3 downto 0) => s_axi_arburst(3 downto 0),
s_axi_arcache(7 downto 0) => s_axi_arcache(7 downto 0),
s_axi_arlen(15 downto 0) => s_axi_arlen(15 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(5 downto 0) => s_axi_arprot(5 downto 0),
s_axi_arqos(7 downto 0) => s_axi_arqos(7 downto 0),
\s_axi_arready[0]\ => s_axi_arready(0),
\s_axi_arready[1]\ => s_axi_arready(1),
s_axi_arsize(5 downto 0) => s_axi_arsize(5 downto 0),
s_axi_arvalid(1 downto 0) => s_axi_arvalid(1 downto 0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
\s_axi_awready[0]\ => \^s_axi_awready\(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => \^s_axi_bresp\(1 downto 0),
s_axi_bvalid(0) => \^s_axi_bvalid\(0),
s_axi_rdata(255 downto 0) => s_axi_rdata(255 downto 0),
s_axi_rlast(1 downto 0) => s_axi_rlast(1 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rresp(3 downto 0) => s_axi_rresp(3 downto 0),
s_axi_rvalid(1 downto 0) => s_axi_rvalid(1 downto 0),
s_axi_wdata(127 downto 0) => s_axi_wdata(127 downto 0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => \^s_axi_wready\(0),
s_axi_wstrb(15 downto 0) => s_axi_wstrb(15 downto 0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_xbar_0 : entity is "system_xbar_0,axi_crossbar_v2_1_12_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_xbar_0 : entity is "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4";
end system_xbar_0;
architecture STRUCTURE of system_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 128;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_M_AXI_ADDR_WIDTH : integer;
attribute C_M_AXI_ADDR_WIDTH of inst : label is 28;
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "64'b0000000000000000000000000000000010000000000000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : integer;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is 3;
attribute C_M_AXI_READ_ISSUING : integer;
attribute C_M_AXI_READ_ISSUING of inst : label is 8;
attribute C_M_AXI_SECURE : integer;
attribute C_M_AXI_SECURE of inst : label is 0;
attribute C_M_AXI_WRITE_CONNECTIVITY : integer;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is 1;
attribute C_M_AXI_WRITE_ISSUING : integer;
attribute C_M_AXI_WRITE_ISSUING of inst : label is 8;
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 1;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 2;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : string;
attribute C_S_AXI_ARB_PRIORITY of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_BASE_ID : string;
attribute C_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000100000000000000000000000000000000";
attribute C_S_AXI_READ_ACCEPTANCE : string;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is "64'b0000000000000000000000000000001000000000000000000000000000000010";
attribute C_S_AXI_SINGLE_THREAD : string;
attribute C_S_AXI_SINGLE_THREAD of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_THREAD_ID_WIDTH : string;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_S_AXI_WRITE_ACCEPTANCE : string;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is "64'b0000000000000000000000000000001000000000000000000000000000001000";
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "artix7";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "32'b00000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "2'b11";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "2'b01";
begin
inst: entity work.system_xbar_0_axi_crossbar_v2_1_12_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(0) => m_axi_arid(0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready(0) => m_axi_arready(0),
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid(0) => m_axi_arvalid(0),
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(0) => m_axi_awid(0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready(0) => m_axi_awready(0),
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid(0) => m_axi_awvalid(0),
m_axi_bid(0) => m_axi_bid(0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(0) => m_axi_rid(0),
m_axi_rlast(0) => m_axi_rlast(0),
m_axi_rready(0) => m_axi_rready(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid(0) => m_axi_rvalid(0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0),
m_axi_wlast(0) => m_axi_wlast(0),
m_axi_wready(0) => m_axi_wready(0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid(0) => m_axi_wvalid(0),
s_axi_araddr(63 downto 0) => s_axi_araddr(63 downto 0),
s_axi_arburst(3 downto 0) => s_axi_arburst(3 downto 0),
s_axi_arcache(7 downto 0) => s_axi_arcache(7 downto 0),
s_axi_arid(1 downto 0) => s_axi_arid(1 downto 0),
s_axi_arlen(15 downto 0) => s_axi_arlen(15 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(5 downto 0) => s_axi_arprot(5 downto 0),
s_axi_arqos(7 downto 0) => s_axi_arqos(7 downto 0),
s_axi_arready(1 downto 0) => s_axi_arready(1 downto 0),
s_axi_arsize(5 downto 0) => s_axi_arsize(5 downto 0),
s_axi_aruser(1 downto 0) => B"00",
s_axi_arvalid(1 downto 0) => s_axi_arvalid(1 downto 0),
s_axi_awaddr(63 downto 0) => s_axi_awaddr(63 downto 0),
s_axi_awburst(3 downto 0) => s_axi_awburst(3 downto 0),
s_axi_awcache(7 downto 0) => s_axi_awcache(7 downto 0),
s_axi_awid(1 downto 0) => s_axi_awid(1 downto 0),
s_axi_awlen(15 downto 0) => s_axi_awlen(15 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(5 downto 0) => s_axi_awprot(5 downto 0),
s_axi_awqos(7 downto 0) => s_axi_awqos(7 downto 0),
s_axi_awready(1 downto 0) => s_axi_awready(1 downto 0),
s_axi_awsize(5 downto 0) => s_axi_awsize(5 downto 0),
s_axi_awuser(1 downto 0) => B"00",
s_axi_awvalid(1 downto 0) => s_axi_awvalid(1 downto 0),
s_axi_bid(1 downto 0) => s_axi_bid(1 downto 0),
s_axi_bready(1 downto 0) => s_axi_bready(1 downto 0),
s_axi_bresp(3 downto 0) => s_axi_bresp(3 downto 0),
s_axi_buser(1 downto 0) => NLW_inst_s_axi_buser_UNCONNECTED(1 downto 0),
s_axi_bvalid(1 downto 0) => s_axi_bvalid(1 downto 0),
s_axi_rdata(255 downto 0) => s_axi_rdata(255 downto 0),
s_axi_rid(1 downto 0) => s_axi_rid(1 downto 0),
s_axi_rlast(1 downto 0) => s_axi_rlast(1 downto 0),
s_axi_rready(1 downto 0) => s_axi_rready(1 downto 0),
s_axi_rresp(3 downto 0) => s_axi_rresp(3 downto 0),
s_axi_ruser(1 downto 0) => NLW_inst_s_axi_ruser_UNCONNECTED(1 downto 0),
s_axi_rvalid(1 downto 0) => s_axi_rvalid(1 downto 0),
s_axi_wdata(255 downto 0) => s_axi_wdata(255 downto 0),
s_axi_wid(1 downto 0) => B"00",
s_axi_wlast(1 downto 0) => s_axi_wlast(1 downto 0),
s_axi_wready(1 downto 0) => s_axi_wready(1 downto 0),
s_axi_wstrb(31 downto 0) => s_axi_wstrb(31 downto 0),
s_axi_wuser(1 downto 0) => B"00",
s_axi_wvalid(1 downto 0) => s_axi_wvalid(1 downto 0)
);
end STRUCTURE;
|
apache-2.0
|
19b9d85e5a681a0a2d62da2515b4a038
| 0.556541 | 2.688546 | false | false | false | false |
daniw/add
|
floppy/mcu/floppy.vhd
| 1 | 35,666 |
-------------------------------------------------------------------------------
-- Entity: floppy
-- Author: daniw
-------------------------------------------------------------------------------
-- Description: floppy
-- Floppy Controller
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity floppy is
port(
rst : in std_logic;
clk : in std_logic;
-- input signals from cpu
enable : in std_logic;
mode : in std_logic;
pitch_fix : in std_logic_vector(15 downto 0);
-- output signals to cpu
status_init : out std_logic;
status_melody : out std_logic;
-- output signals to floppy
floppy_step : out std_logic;
floppy_dir : out std_logic
floppy_en : out std_logic;
);
end floppy;
architecture rtl of floppy is
-- constants to specify module properties
-- pitch width
constant PITCH_WIDTH : integer := 7; -- 127
-- melody duration width
constant MEL_DUR_WIDTH : integer := 10; -- 1023
-- melody duration counter width
constant MEL_DUR_CNT_WIDTH : integer := 27; -- 51150000 (1023 * 50000)
-- melody address width
constant MEL_ADDR_WIDTH : integer := 10; -- 1023
-- converted pitch width
constant PITCH_CONV_WIDTH : integer := 23; -- 5772367
-- step counter width
constant STEP_CNT_WIDTH : integer := 7; -- 80
-- constant to define number of clock cycles per duration tick
constant NOF_CLK_DUR : integer := 50000;
-- constant for init pitch
constant PITCH_INIT : unsigned(PITCH_WIDTH-1 downto 0) := to_unsigned(69, PITCH_WIDTH); -- 440 [Hz]
-- melody rom
type t_mel_rom is array (0 to 2**MEL_ADDR_WIDTH-1) of std_logic_vector(MEL_DUR_WIDTH+PITCH_WIDTH-1 downto 0); -- new type instead of std_logic_vector for easier separation of duration and pitch
constant mel_rom : t_mel_rom := (
---------------------------------
-- Harold Faltermeyer - Axel F --
---------------------------------
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 238, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 357, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 119, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 56, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 417, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 59, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 179, MEL_DUR_WIDTH)),
--......................................................................
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 59, MEL_DUR_WIDTH)),
-- probably rest here to separate tones
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 90, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 29, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 58, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 179, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 59, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 179, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 59, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 51, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 179, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 59, MEL_DUR_WIDTH)),
--......................................................................
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 357, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 119, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 60, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 238, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 119, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 119, MEL_DUR_WIDTH)),
--......................................................................
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 59, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
-- probably rest here to separate tones
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 89, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 30, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 61, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 178, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 60, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 178, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 56, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 178, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
--......................................................................
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 178, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 60, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 178, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 65, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 178, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 89, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 30, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 51, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 119, MEL_DUR_WIDTH)),
--......................................................................
std_logic_vector(to_unsigned( 51, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 59, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
-- probably rest here to separate tones
std_logic_vector(to_unsigned( 51, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 89, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 30, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 48, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 178, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 55, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 178, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 60, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 238, MEL_DUR_WIDTH)),
--......................................................................
std_logic_vector(to_unsigned( 53, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 356, MEL_DUR_WIDTH)),
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 120, MEL_DUR_WIDTH)),
--......................................................................
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 952, MEL_DUR_WIDTH)),
--......................................................................
--======================================================================
--......................................................................
-- End of melody -> do not change!
std_logic_vector(to_unsigned( 0, PITCH_WIDTH)) & std_logic_vector(to_unsigned( 0, MEL_DUR_WIDTH)),
-- Filling rest of rom with zeros
others => (others => '0')
);
-- signal to cut pitch_fix
signal pitch_fix_reg : std_logic_vector(PITCH_WIDTH-1 downto 0);
-- signals for buffering outputs
signal status_init_reg : std_logic;
signal status_melody_reg : std_logic;
signal step_reg : std_logic;
signal dir_reg : std_logic;
signal en_reg : std_logic;
-- signal to indicate end of actual tone
signal tone_end : std_logic;
-- signal that contains duration of actual tone
signal duration_melody : std_logic_vector(MEL_DUR_WIDTH-1 downto 0); -- in milliseconds
-- signal that contains pitch of actual tone
signal pitch_melody : std_logic_vector(PITCH_WIDTH-1 downto 0);
-- pitch after pitch selector
signal pitch_sel : unsigned(PITCH_WIDTH-1 downto 0);
-- pitch after converted to number of clocks
signal pitch_conv : std_logic_vector(PITCH_CONV_WIDTH-1 downto 0);
-- step after divider
signal step_int : std_logic;
-- edge detection of step_reg
signal step_edge : std_logic;
signal step_edge_prev : std_logic;
-- signal to indicate step_cnt end
signal step_cnt_end : std_logic;
-- counters
-- mel_dur_cnt
signal mel_dur_cnt : unsigned(MEL_DUR_CNT_WIDTH-1 downto 0);
-- mel_tone_cnt
signal mel_tone_cnt : unsigned(MEL_ADDR_WIDTH-1 downto 0);
-- step_divider
signal step_divider : unsigned(PITCH_CONV_WIDTH-1 downto 0);
-- step_cnt
signal step_cnt : unsigned(STEP_CNT_WIDTH-1 downto 0);
begin
-----------------------------------------------------------------------------
-- combinatorial process to cut pitch_fix to PITCH_WIDTH
-- in:
-- pitch_fix
-- out:
-- pitch_fix_reg
-----------------------------------------------------------------------------
pitch_fix_cut: process(pitch_fix)
begin
pitch_fix_reg <= pitch_fix(PITCH_WIDTH-1 downto 0);
end process;
-----------------------------------------------------------------------------
-- combinatorial process to connect buffered outputs to the outputs
-- in:
-- status_init_reg
-- status_melody_reg
-- step_reg
-- dir_reg
-- en_reg
-- out:
-- status_init
-- status_melody
-- floppy_step
-- floppy_dir
-- floppy_en
-----------------------------------------------------------------------------
reg_out: process(status_init_reg, status_melody_reg, step_reg, dir_reg)
begin
status_init <= status_init_reg;
status_melody <= status_melody_reg;
floppy_step <= step_reg;
floppy_dir <= dir_reg;
floppy_en <= en_reg;
end process;
-----------------------------------------------------------------------------
-- sequential process to count the tone duration
-- in:
-- rst
-- clk
-- mode
-- enable
-- status_melody_reg
-- duration_melody
-- mel_dur_cnt
-- out:
-- mel_dur_cnt
-- tone_end
-----------------------------------------------------------------------------
dur_cnt: process(rst, clk)
begin
if rst = '1' then
mel_dur_cnt <= to_unsigned(0, MEL_DUR_CNT_WIDTH);
tone_end <= '0';
elsif rising_edge(clk) then
if ((enable = '1') and (mode = '1') and (status_melody_reg = '1')) then
if mel_dur_cnt = 2 then
mel_dur_cnt <= mel_dur_cnt - 1;
tone_end <= '1';
elsif mel_dur_cnt = 0 then
mel_dur_cnt <= to_unsigned(to_integer(unsigned(duration_melody)) * NOF_CLK_DUR, MEL_DUR_CNT_WIDTH) + 1;
tone_end <= '0';
else
mel_dur_cnt <= mel_dur_cnt - 1;
tone_end <= '0';
end if;
else
mel_dur_cnt <= to_unsigned(to_integer(unsigned(duration_melody)) * NOF_CLK_DUR, MEL_DUR_CNT_WIDTH);
tone_end <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- sequential process to count the number of tones played
-- in:
-- rst
-- clk
-- mode
-- enable
-- status_melody_reg
-- duration_melody
-- tone_end
-- mel_tone_cnt
-- out:
-- mel_tone_cnt
-----------------------------------------------------------------------------
tone_cnt: process(rst, clk)
begin
if rst = '1' then
mel_tone_cnt <= to_unsigned(0, MEL_ADDR_WIDTH);
elsif rising_edge(clk) then
if ((enable = '1') and (mode = '1') and (status_melody_reg = '1')) then
if tone_end = '1' then
mel_tone_cnt <= mel_tone_cnt + 1;
else
mel_tone_cnt <= mel_tone_cnt;
end if;
else
mel_tone_cnt <= to_unsigned(0, MEL_ADDR_WIDTH);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- combinatorial process for melody rom
-- in:
-- mel_tone_cnt
-- out:
-- duration_melody
-- pitch_melody
-----------------------------------------------------------------------------
melody_rom: process(mel_tone_cnt)
begin
pitch_melody <= mel_rom(to_integer(mel_tone_cnt))(MEL_DUR_WIDTH+PITCH_WIDTH-1 downto MEL_DUR_WIDTH);
duration_melody <= mel_rom(to_integer(mel_tone_cnt))(MEL_DUR_WIDTH-1 downto 0);
end process;
-----------------------------------------------------------------------------
-- combinatorial process to detect end of melody
-- in:
-- pitch_melody
-- duration_melody
-- out:
-- status_melody_reg
-----------------------------------------------------------------------------
mel_end_det: process(pitch_melody, duration_melody)
begin
if ((unsigned(duration_melody) = 0) and (unsigned(duration_melody)) = 0) then
status_melody_reg <= '0';
else
status_melody_reg <= '1';
end if;
end process;
-----------------------------------------------------------------------------
-- combinatorial process for pitch selector
-- in:
-- status_init_reg
-- mode
-- pitch_fix_reg
-- pitch_melody
-- out:
-- pitch_sel
-----------------------------------------------------------------------------
--pitch_sel: process(status_init_reg, mode, pitch_fix_reg, pitch_melody)
--begin
pitch_sel <= PITCH_INIT when (status_init_reg = '1') else
unsigned(pitch_melody) when (mode = '1') else
unsigned(pitch_fix_reg);
--end process;
-----------------------------------------------------------------------------
-- combinatorial process for converting pitch to number of cycles
-- in:
-- pitch_sel
-- out:
-- pitch_conv
-----------------------------------------------------------------------------
--pitch_conv: process(pitch_sel)
--begin
with to_integer(pitch_sel) select
-- # clk MIDI Frequency
pitch_conv <= std_logic_vector(to_unsigned( 0, PITCH_CONV_WIDTH)) when 0, -- rest
std_logic_vector(to_unsigned(5772367, PITCH_CONV_WIDTH)) when 1, -- 8.661 [Hz]
std_logic_vector(to_unsigned(5448389, PITCH_CONV_WIDTH)) when 2, -- 9.177 [Hz]
std_logic_vector(to_unsigned(5142594, PITCH_CONV_WIDTH)) when 3, -- 9.722 [Hz]
std_logic_vector(to_unsigned(4853963, PITCH_CONV_WIDTH)) when 4, -- 10.30 [Hz]
std_logic_vector(to_unsigned(4581531, PITCH_CONV_WIDTH)) when 5, -- 10.91 [Hz]
std_logic_vector(to_unsigned(4324389, PITCH_CONV_WIDTH)) when 6, -- 11.56 [Hz]
std_logic_vector(to_unsigned(4081680, PITCH_CONV_WIDTH)) when 7, -- 12.24 [Hz]
std_logic_vector(to_unsigned(3852593, PITCH_CONV_WIDTH)) when 8, -- 12.97 [Hz]
std_logic_vector(to_unsigned(3636363, PITCH_CONV_WIDTH)) when 9, -- 13.75 [Hz]
std_logic_vector(to_unsigned(3432270, PITCH_CONV_WIDTH)) when 10, -- 14.56 [Hz]
std_logic_vector(to_unsigned(3239631, PITCH_CONV_WIDTH)) when 11, -- 15.43 [Hz]
std_logic_vector(to_unsigned(3057805, PITCH_CONV_WIDTH)) when 12, -- 16.35 [Hz]
std_logic_vector(to_unsigned(2886183, PITCH_CONV_WIDTH)) when 13, -- 17.32 [Hz]
std_logic_vector(to_unsigned(2724194, PITCH_CONV_WIDTH)) when 14, -- 18.35 [Hz]
std_logic_vector(to_unsigned(2571297, PITCH_CONV_WIDTH)) when 15, -- 19.44 [Hz]
std_logic_vector(to_unsigned(2426981, PITCH_CONV_WIDTH)) when 16, -- 20.60 [Hz]
std_logic_vector(to_unsigned(2290765, PITCH_CONV_WIDTH)) when 17, -- 21.82 [Hz]
std_logic_vector(to_unsigned(2162194, PITCH_CONV_WIDTH)) when 18, -- 23.12 [Hz]
std_logic_vector(to_unsigned(2040840, PITCH_CONV_WIDTH)) when 19, -- 24.49 [Hz]
std_logic_vector(to_unsigned(1926296, PITCH_CONV_WIDTH)) when 20, -- 25.95 [Hz]
std_logic_vector(to_unsigned(1818181, PITCH_CONV_WIDTH)) when 21, -- 27.5 [Hz]
std_logic_vector(to_unsigned(1716135, PITCH_CONV_WIDTH)) when 22, -- 29.13 [Hz]
std_logic_vector(to_unsigned(1619815, PITCH_CONV_WIDTH)) when 23, -- 30.86 [Hz]
std_logic_vector(to_unsigned(1528902, PITCH_CONV_WIDTH)) when 24, -- 32.70 [Hz]
std_logic_vector(to_unsigned(1443091, PITCH_CONV_WIDTH)) when 25, -- 34.64 [Hz]
std_logic_vector(to_unsigned(1362097, PITCH_CONV_WIDTH)) when 26, -- 36.70 [Hz]
std_logic_vector(to_unsigned(1285648, PITCH_CONV_WIDTH)) when 27, -- 38.89 [Hz]
std_logic_vector(to_unsigned(1213490, PITCH_CONV_WIDTH)) when 28, -- 41.20 [Hz]
std_logic_vector(to_unsigned(1145382, PITCH_CONV_WIDTH)) when 29, -- 43.65 [Hz]
std_logic_vector(to_unsigned(1081097, PITCH_CONV_WIDTH)) when 30, -- 46.24 [Hz]
std_logic_vector(to_unsigned(1020420, PITCH_CONV_WIDTH)) when 31, -- 48.99 [Hz]
std_logic_vector(to_unsigned( 963148, PITCH_CONV_WIDTH)) when 32, -- 51.91 [Hz]
std_logic_vector(to_unsigned( 909090, PITCH_CONV_WIDTH)) when 33, -- 55 [Hz]
std_logic_vector(to_unsigned( 858067, PITCH_CONV_WIDTH)) when 34, -- 58.27 [Hz]
std_logic_vector(to_unsigned( 809907, PITCH_CONV_WIDTH)) when 35, -- 61.73 [Hz]
std_logic_vector(to_unsigned( 764451, PITCH_CONV_WIDTH)) when 36, -- 65.40 [Hz]
std_logic_vector(to_unsigned( 721545, PITCH_CONV_WIDTH)) when 37, -- 69.29 [Hz]
std_logic_vector(to_unsigned( 681048, PITCH_CONV_WIDTH)) when 38, -- 73.41 [Hz]
std_logic_vector(to_unsigned( 642824, PITCH_CONV_WIDTH)) when 39, -- 77.78 [Hz]
std_logic_vector(to_unsigned( 606745, PITCH_CONV_WIDTH)) when 40, -- 82.40 [Hz]
std_logic_vector(to_unsigned( 572691, PITCH_CONV_WIDTH)) when 41, -- 87.30 [Hz]
std_logic_vector(to_unsigned( 540548, PITCH_CONV_WIDTH)) when 42, -- 92.49 [Hz]
std_logic_vector(to_unsigned( 510210, PITCH_CONV_WIDTH)) when 43, -- 97.99 [Hz]
std_logic_vector(to_unsigned( 481574, PITCH_CONV_WIDTH)) when 44, -- 103.8 [Hz]
std_logic_vector(to_unsigned( 454545, PITCH_CONV_WIDTH)) when 45, -- 110 [Hz]
std_logic_vector(to_unsigned( 429033, PITCH_CONV_WIDTH)) when 46, -- 116.5 [Hz]
std_logic_vector(to_unsigned( 404953, PITCH_CONV_WIDTH)) when 47, -- 123.4 [Hz]
std_logic_vector(to_unsigned( 382225, PITCH_CONV_WIDTH)) when 48, -- 130.8 [Hz]
std_logic_vector(to_unsigned( 360772, PITCH_CONV_WIDTH)) when 49, -- 138.5 [Hz]
std_logic_vector(to_unsigned( 340524, PITCH_CONV_WIDTH)) when 50, -- 146.8 [Hz]
std_logic_vector(to_unsigned( 321412, PITCH_CONV_WIDTH)) when 51, -- 155.5 [Hz]
std_logic_vector(to_unsigned( 303372, PITCH_CONV_WIDTH)) when 52, -- 164.8 [Hz]
std_logic_vector(to_unsigned( 286345, PITCH_CONV_WIDTH)) when 53, -- 174.6 [Hz]
std_logic_vector(to_unsigned( 270274, PITCH_CONV_WIDTH)) when 54, -- 184.9 [Hz]
std_logic_vector(to_unsigned( 255105, PITCH_CONV_WIDTH)) when 55, -- 195.9 [Hz]
std_logic_vector(to_unsigned( 240787, PITCH_CONV_WIDTH)) when 56, -- 207.6 [Hz]
std_logic_vector(to_unsigned( 227272, PITCH_CONV_WIDTH)) when 57, -- 220 [Hz]
std_logic_vector(to_unsigned( 214516, PITCH_CONV_WIDTH)) when 58, -- 233.0 [Hz]
std_logic_vector(to_unsigned( 202476, PITCH_CONV_WIDTH)) when 59, -- 246.9 [Hz]
std_logic_vector(to_unsigned( 191112, PITCH_CONV_WIDTH)) when 60, -- 261.6 [Hz]
std_logic_vector(to_unsigned( 180386, PITCH_CONV_WIDTH)) when 61, -- 277.1 [Hz]
std_logic_vector(to_unsigned( 170262, PITCH_CONV_WIDTH)) when 62, -- 293.6 [Hz]
std_logic_vector(to_unsigned( 160706, PITCH_CONV_WIDTH)) when 63, -- 311.1 [Hz]
std_logic_vector(to_unsigned( 151686, PITCH_CONV_WIDTH)) when 64, -- 329.6 [Hz]
std_logic_vector(to_unsigned( 143172, PITCH_CONV_WIDTH)) when 65, -- 349.2 [Hz]
std_logic_vector(to_unsigned( 135137, PITCH_CONV_WIDTH)) when 66, -- 369.9 [Hz]
std_logic_vector(to_unsigned( 127552, PITCH_CONV_WIDTH)) when 67, -- 391.9 [Hz]
std_logic_vector(to_unsigned( 120393, PITCH_CONV_WIDTH)) when 68, -- 415.3 [Hz]
std_logic_vector(to_unsigned( 113636, PITCH_CONV_WIDTH)) when 69, -- 440 [Hz]
std_logic_vector(to_unsigned( 107258, PITCH_CONV_WIDTH)) when 70, -- 466.1 [Hz]
std_logic_vector(to_unsigned( 101238, PITCH_CONV_WIDTH)) when 71, -- 493.8 [Hz]
std_logic_vector(to_unsigned( 95556, PITCH_CONV_WIDTH)) when 72, -- 523.2 [Hz]
std_logic_vector(to_unsigned( 90193, PITCH_CONV_WIDTH)) when 73, -- 554.3 [Hz]
std_logic_vector(to_unsigned( 85131, PITCH_CONV_WIDTH)) when 74, -- 587.3 [Hz]
std_logic_vector(to_unsigned( 80353, PITCH_CONV_WIDTH)) when 75, -- 622.2 [Hz]
std_logic_vector(to_unsigned( 75843, PITCH_CONV_WIDTH)) when 76, -- 659.2 [Hz]
std_logic_vector(to_unsigned( 71586, PITCH_CONV_WIDTH)) when 77, -- 698.4 [Hz]
std_logic_vector(to_unsigned( 67568, PITCH_CONV_WIDTH)) when 78, -- 739.9 [Hz]
std_logic_vector(to_unsigned( 63776, PITCH_CONV_WIDTH)) when 79, -- 783.9 [Hz]
std_logic_vector(to_unsigned( 60196, PITCH_CONV_WIDTH)) when 80, -- 830.6 [Hz]
std_logic_vector(to_unsigned( 56818, PITCH_CONV_WIDTH)) when 81, -- 880 [Hz]
std_logic_vector(to_unsigned( 53629, PITCH_CONV_WIDTH)) when 82, -- 932.3 [Hz]
std_logic_vector(to_unsigned( 50619, PITCH_CONV_WIDTH)) when 83, -- 987.7 [Hz]
std_logic_vector(to_unsigned( 47778, PITCH_CONV_WIDTH)) when 84, -- 1046 [Hz]
std_logic_vector(to_unsigned( 45096, PITCH_CONV_WIDTH)) when 85, -- 1108 [Hz]
std_logic_vector(to_unsigned( 42565, PITCH_CONV_WIDTH)) when 86, -- 1174 [Hz]
std_logic_vector(to_unsigned( 40176, PITCH_CONV_WIDTH)) when 87, -- 1244 [Hz]
std_logic_vector(to_unsigned( 37921, PITCH_CONV_WIDTH)) when 88, -- 1318 [Hz]
std_logic_vector(to_unsigned( 35793, PITCH_CONV_WIDTH)) when 89, -- 1396 [Hz]
std_logic_vector(to_unsigned( 33784, PITCH_CONV_WIDTH)) when 90, -- 1479 [Hz]
std_logic_vector(to_unsigned( 31888, PITCH_CONV_WIDTH)) when 91, -- 1567 [Hz]
std_logic_vector(to_unsigned( 30098, PITCH_CONV_WIDTH)) when 92, -- 1661 [Hz]
std_logic_vector(to_unsigned( 28409, PITCH_CONV_WIDTH)) when 93, -- 1760 [Hz]
std_logic_vector(to_unsigned( 26814, PITCH_CONV_WIDTH)) when 94, -- 1864 [Hz]
std_logic_vector(to_unsigned( 25309, PITCH_CONV_WIDTH)) when 95, -- 1975 [Hz]
std_logic_vector(to_unsigned( 23889, PITCH_CONV_WIDTH)) when 96, -- 2093 [Hz]
std_logic_vector(to_unsigned( 22548, PITCH_CONV_WIDTH)) when 97, -- 2217 [Hz]
std_logic_vector(to_unsigned( 21282, PITCH_CONV_WIDTH)) when 98, -- 2349 [Hz]
std_logic_vector(to_unsigned( 20088, PITCH_CONV_WIDTH)) when 99, -- 2489 [Hz]
std_logic_vector(to_unsigned( 18960, PITCH_CONV_WIDTH)) when 100, -- 2637 [Hz]
std_logic_vector(to_unsigned( 17896, PITCH_CONV_WIDTH)) when 101, -- 2793 [Hz]
std_logic_vector(to_unsigned( 16892, PITCH_CONV_WIDTH)) when 102, -- 2959 [Hz]
std_logic_vector(to_unsigned( 15944, PITCH_CONV_WIDTH)) when 103, -- 3135 [Hz]
std_logic_vector(to_unsigned( 15049, PITCH_CONV_WIDTH)) when 104, -- 3322 [Hz]
std_logic_vector(to_unsigned( 14204, PITCH_CONV_WIDTH)) when 105, -- 3520 [Hz]
std_logic_vector(to_unsigned( 13407, PITCH_CONV_WIDTH)) when 106, -- 3729 [Hz]
std_logic_vector(to_unsigned( 12654, PITCH_CONV_WIDTH)) when 107, -- 3951 [Hz]
std_logic_vector(to_unsigned( 11944, PITCH_CONV_WIDTH)) when 108, -- 4186 [Hz]
std_logic_vector(to_unsigned( 11274, PITCH_CONV_WIDTH)) when 109, -- 4434 [Hz]
std_logic_vector(to_unsigned( 10641, PITCH_CONV_WIDTH)) when 110, -- 4698 [Hz]
std_logic_vector(to_unsigned( 10044, PITCH_CONV_WIDTH)) when 111, -- 4978 [Hz]
std_logic_vector(to_unsigned( 9480, PITCH_CONV_WIDTH)) when 112, -- 5274 [Hz]
std_logic_vector(to_unsigned( 8948, PITCH_CONV_WIDTH)) when 113, -- 5587 [Hz]
std_logic_vector(to_unsigned( 8446, PITCH_CONV_WIDTH)) when 114, -- 5919 [Hz]
std_logic_vector(to_unsigned( 7972, PITCH_CONV_WIDTH)) when 115, -- 6271 [Hz]
std_logic_vector(to_unsigned( 7524, PITCH_CONV_WIDTH)) when 116, -- 6644 [Hz]
std_logic_vector(to_unsigned( 7102, PITCH_CONV_WIDTH)) when 117, -- 7040 [Hz]
std_logic_vector(to_unsigned( 6703, PITCH_CONV_WIDTH)) when 118, -- 7458 [Hz]
std_logic_vector(to_unsigned( 6327, PITCH_CONV_WIDTH)) when 119, -- 7902 [Hz]
std_logic_vector(to_unsigned( 5972, PITCH_CONV_WIDTH)) when 120, -- 8372 [Hz]
std_logic_vector(to_unsigned( 5637, PITCH_CONV_WIDTH)) when 121, -- 8869 [Hz]
std_logic_vector(to_unsigned( 5320, PITCH_CONV_WIDTH)) when 122, -- 9397 [Hz]
std_logic_vector(to_unsigned( 5022, PITCH_CONV_WIDTH)) when 123, -- 9956 [Hz]
std_logic_vector(to_unsigned( 4740, PITCH_CONV_WIDTH)) when 124, -- 10548 [Hz]
--std_logic_vector(to_unsigned( 4474, PITCH_CONV_WIDTH)) when 125, -- 11175 [Hz]
--std_logic_vector(to_unsigned( 4223, PITCH_CONV_WIDTH)) when 126, -- 11839 [Hz]
--std_logic_vector(to_unsigned( 3986, PITCH_CONV_WIDTH)) when 127, -- 12543 [Hz]
--std_logic_vector(to_unsigned( 3762, PITCH_CONV_WIDTH)) when 128, -- 13289 [Hz]
--std_logic_vector(to_unsigned( 3551, PITCH_CONV_WIDTH)) when 129, -- 14080 [Hz]
--std_logic_vector(to_unsigned( 3351, PITCH_CONV_WIDTH)) when 130, -- 14917 [Hz]
--std_logic_vector(to_unsigned( 3163, PITCH_CONV_WIDTH)) when 131, -- 15804 [Hz]
--std_logic_vector(to_unsigned( 2986, PITCH_CONV_WIDTH)) when 132, -- 16744 [Hz]
--std_logic_vector(to_unsigned( 2818, PITCH_CONV_WIDTH)) when 133, -- 17739 [Hz]
--std_logic_vector(to_unsigned( 2660, PITCH_CONV_WIDTH)) when 134, -- 18794 [Hz]
--std_logic_vector(to_unsigned( 2511, PITCH_CONV_WIDTH)) when 135, -- 19912 [Hz]
--std_logic_vector(to_unsigned( 2370, PITCH_CONV_WIDTH)) when 136, -- 21096 [Hz]
std_logic_vector(to_unsigned( 113636, PITCH_CONV_WIDTH)) when others; -- 440 [Hz]
--end process;
-----------------------------------------------------------------------------
-- sequential process for divider to create internal step signal
-- in:
-- rst
-- clk
-- pitch_conv
-- step_divider
-- out:
-- step_int
-- step_divider
-----------------------------------------------------------------------------
divider: process(rst, clk)
begin
if rst = '1' then
step_int <= '1';
step_divider <= (others => '0');
elsif rising_edge(clk) then
if (step_divider = 0) then
step_divider <= unsigned(pitch_conv);
if (to_integer(unsigned(pitch_conv)) = 0) then
step_int <= step_int;
else
step_int <= not step_int;
end if;
else
step_divider <= step_divider - 1;
step_int <= step_int;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- combinatorial process to enable step
-- in:
-- enable
-- status_init_reg
-- step_int
-- out:
-- step_reg
-- en_reg
-----------------------------------------------------------------------------
--step_enable: process(enable, status_init_reg, step_int)
--begin
step_reg <= step_int when ((status_init_reg = '1') or (enable = '1')) else
'0';
en_reg <= 0 when ((status_init_reg = '1') or (enable = '1')) else
'1';
--end process;
-----------------------------------------------------------------------------
-- sequential process for edge detection on step_reg
-- in:
-- rst
-- clk
-- step_reg
-- out:
-- step_edge
-----------------------------------------------------------------------------
step_edge_proc: process(rst, clk)
begin
if rst = '1' then
step_edge <= '0';
step_edge_prev <= '0';
elsif rising_edge(clk) then
step_edge_prev <= step_reg;
if ((step_reg = '1') and (step_edge_prev = '0')) then
step_edge <= '1';
else
step_edge <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- sequential process for counting the number of steps
-- in:
-- rst
-- clk
-- step_cnt_end
-- step_edge
-- step_cnt
-- out:
-- step_cnt_end
-- step_cnt
-----------------------------------------------------------------------------
step_cnt_proc: process(rst, clk)
begin
if rst = '1' then
step_cnt <= to_unsigned(80, STEP_CNT_WIDTH);
step_cnt_end <= '0';
elsif rising_edge(clk) then
if step_edge = '1' then
if step_cnt = 0 then
step_cnt <= to_unsigned(79, STEP_CNT_WIDTH);
step_cnt_end <= '1';
else
step_cnt <= step_cnt - 1;
step_cnt_end <= '0';
end if;
else
step_cnt <= step_cnt;
step_cnt_end <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- sequential process to generate dir_reg signal
-- in:
-- rst
-- clk
-- step_cnt_end
-- out:
-- dir_reg
-----------------------------------------------------------------------------
dir_gen: process(rst, clk)
begin
if rst = '1' then
dir_reg <= '1';
elsif rising_edge(clk) then
if step_cnt_end = '1' then
dir_reg <= not dir_reg;
else
dir_reg <= dir_reg;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- sequential process to generate status_init_reg
-- in:
-- rst
-- clk
-- step_cnt_end
-- out:
-- status_init_reg
-----------------------------------------------------------------------------
init_ff: process(rst, clk)
begin
if rst = '1' then
status_init_reg <= '1';
elsif rising_edge(clk) then
if step_cnt_end = '1' then
status_init_reg <= '0';
else
status_init_reg <= status_init_reg;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
4a7bef4056cd01a7d00cf41cb2266254
| 0.495514 | 3.744069 | false | false | false | false |
daniw/add
|
floppy/mcu/mcu_pkg.vhd
| 2 | 8,581 |
-------------------------------------------------------------------------------
-- Entity: mcu_pkg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- VHDL package for definition of design parameters and types used throughout
-- the MCU.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mcu_pkg is
-----------------------------------------------------------------------------
-- tool chain selection (because no suppoprt of 'val attritube in ISE XST)
-----------------------------------------------------------------------------
constant ISE_TOOL : boolean := true; -- true = ISE XST
-- false = other synthesizer (e.g. Vivado)
-----------------------------------------------------------------------------
-- design parameters
-----------------------------------------------------------------------------
-- system clock frequency in Hz
constant CF : natural := 50_000_000; -- 50 MHz
-- bus architecture parameters
constant DW : natural range 4 to 64 := 16; -- data word width
constant AW : natural range 2 to 64 := 8; -- total address width
constant AWH : natural range 1 to 64 := 2; -- high address width
constant AWL : natural range 1 to 64 := AW-AWH; -- low address width
-- memory map
type t_bus_slave is (ROM, RAM, GPIO, LCD); -- list of bus slaves
type t_ba is array (t_bus_slave) of std_logic_vector(AW-1 downto 0);
constant BA : t_ba := ( -- full base addresses
ROM => X"00",
RAM => X"40",
GPIO => X"80",
LCD => X"C0"
);
type t_hba is array (t_bus_slave) of std_logic_vector(AWH-1 downto 0);
constant HBA : t_hba := ( -- high base address for decoding
ROM => BA(ROM)(AW-1 downto AW-AWH),
RAM => BA(RAM)(AW-1 downto AW-AWH),
GPIO => BA(GPIO)(AW-1 downto AW-AWH),
LCD => BA(LCD)(AW-1 downto AW-AWH)
);
-- CPU instruction set
-- Note: Defining the OPcode in the way shown below, allows assembler-style
-- programming with mnemonics rather than machine coding (see rom.vhd).
constant OPCW : natural range 1 to DW := 5; -- Opcode word width
constant OPAW : natural range 1 to DW := 4; -- ALU operation word width
constant IOWW : natural range 1 to DW := 8; -- immediate operand word width
type t_instr is (add, sub, andi, ori, xori, slai, srai, mov,
ld, st,
addil, addih, setil, setih,
jmp, bne, bge, blt, bca, bov,
nop);
-- Instructions targeted at the ALU are defined by means of a sub-type.
-- This allows changing the opcode of instructions without having to
-- modify the source code of the ALU.
subtype t_alu_instr is t_instr range add to mov;
type t_opcode is array (t_instr) of std_logic_vector(OPCW-1 downto 0);
constant OPC : t_opcode := ( -- OPcode
-- ALU operations -------------------------------
add => "00000", -- 0: addition
sub => "00001", -- 1: subtraction
andi => "00010", -- 2: bit-wise AND
ori => "00011", -- 3: bit-wise OR
xori => "00100", -- 4: bit-wise XOR
slai => "00101", -- 5: shift-left arithmetically
srai => "00110", -- 6: shift-right arithmetically
mov => "00111", -- 7: move between register
-- Immediate Operands ---------------------------
addil => "01100", -- 12: add imm. constant low
addih => "01101", -- 13: add imm. constant high
setil => "01110", -- 14: set imm. constant low
setih => "01111", -- 15: set imm. constant high
-- Memory load/store ----------------------------
ld => "10000", -- 16: load from memory
st => "10001", -- 17: store to memory
-- Jump/Branch ----------------------------------
jmp => "11000", -- 24: absolute jump
bne => "11001", -- 25: branch if not equal (not Z)
bge => "11010", -- 26: branch if greater/equal (not N or Z)
blt => "11011", -- 27: branch if less than (N)
bca => "11100", -- 28: branch if carry set (C)
bov => "11101", -- 29: branch if overflow set (O)
-- Others ---------------------------------------
nop => "11111" -- 31: no operation
);
type t_flags is (Z, N, C, O); -- ALU flags (zero, negative, carry, overflow)
type t_flag_arr is array (t_flags) of std_logic;
-- register block
constant RIDW : natural range 1 to DW := 3; -- register ID word width
type t_regid is array(0 to 7) of std_logic_vector(RIDW-1 downto 0);
constant reg : t_regid := ("000","001","010","011","100","101","110","111");
type t_regblk is array(0 to 7) of std_logic_vector(DW-1 downto 0);
-- CPU address generation
type t_pc_mode is (linear, abs_jump, rel_offset); -- addr calcultion modi
type t_addr_exc is (no_err, lin_err, rel_err); -- address exceptions
-- LCD peripheral
constant LCD_PW : natural := 7; -- # of LCD control + data signal
-----------------------------------------------------------------------------
-- global types
-----------------------------------------------------------------------------
-- Master bus interface -----------------------------------------------------
type t_bus2cpu is record
data : std_logic_vector(DW-1 downto 0);
end record;
type t_cpu2bus is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
r_wb : std_logic;
end record;
-- Read-only slave bus interface -------------------------------------------
type t_bus2ros is record
addr : std_logic_vector(AWL-1 downto 0);
end record;
type t_ros2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- read/write slave bus interface -------------------------------------------
type t_bus2rws is record
addr : std_logic_vector(AWL-1 downto 0);
data : std_logic_vector(DW-1 downto 0);
we : std_logic;
end record;
type t_rws2bus is record
data : std_logic_vector(DW-1 downto 0);
end record;
-- GPIO ---------------------------------------------------------------------
type t_gpio_pin_in is record
in_0 : std_logic_vector(DW-1 downto 0);
in_1 : std_logic_vector(DW-1 downto 0);
in_2 : std_logic_vector(DW-1 downto 0);
in_3 : std_logic_vector(DW-1 downto 0);
end record;
type t_gpio_pin_out is record
out_0 : std_logic_vector(DW-1 downto 0);
out_1 : std_logic_vector(DW-1 downto 0);
out_2 : std_logic_vector(DW-1 downto 0);
out_3 : std_logic_vector(DW-1 downto 0);
enb_0 : std_logic_vector(DW-1 downto 0);
enb_1 : std_logic_vector(DW-1 downto 0);
enb_2 : std_logic_vector(DW-1 downto 0);
enb_3 : std_logic_vector(DW-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- CPU internal types
-----------------------------------------------------------------------------
-- Control Unit / Register Block interface ----------------------------------
type t_ctr2reg is record
src1 : std_logic_vector(RIDW-1 downto 0);
src2 : std_logic_vector(RIDW-1 downto 0);
dest : std_logic_vector(RIDW-1 downto 0);
enb_res : std_logic;
data : std_logic_vector(DW-1 downto 0);
enb_data_low : std_logic;
enb_data_high : std_logic;
end record;
type t_reg2ctr is record
data : std_logic_vector(DW-1 downto 0);
addr : std_logic_vector(AW-1 downto 0);
end record;
-- Control Unit / Program Counter interface --------------------------------
type t_ctr2prc is record
enb : std_logic;
mode : t_pc_mode;
addr : std_logic_vector(AW-1 downto 0);
end record;
type t_prc2ctr is record
pc : std_logic_vector(AW-1 downto 0);
exc : t_addr_exc;
end record;
-- Control Unit / ALU interface ---------------------------------------------
type t_ctr2alu is record
op : std_logic_vector(OPAW-1 downto 0); -- operation
imm : std_logic_vector(IOWW-1 downto 0); -- immediate operand
enb : std_logic; -- enable flag update
end record;
type t_alu2ctr is record
flag : t_flag_arr;
end record;
end mcu_pkg;
|
gpl-2.0
|
f424d5081f48cfc6fb552dcbc56a5562
| 0.491201 | 4.024859 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_xadc_core_drp.vhd
| 1 | 50,323 |
-------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_xadc_core_drp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010, 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : system_xadc_wiz_0_0_xadc_core_drp.vhd
-- Version : v1.00.a
-- Description : XADC for AXI bus on new FPGA devices.
-- This file containts actual interface between the core
-- and XADC hard macro.
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_xadc.vhd
-- -system_xadc_wiz_0_0_xadc_core_drp.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.unsigned;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.or_reduce;
use IEEE.numeric_std.all;
library work;
use work.system_xadc_wiz_0_0_ipif_pkg.all;
use work.system_xadc_wiz_0_0_proc_common_pkg.all;
Library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- un-comment below line if testing locally with BLH or UNISIM model
--use unisim.XADC;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- AXI4 Slave Single block generics
-------------------------------------------------------------------------------
-- C_S_AXI_ADDR_WIDTH -- AXI4 address bus width
-- C_S_AXI_DATA_WIDTH -- AXI4 Slave bus width
--
-------------------------------------------------------------------------------
-- XADC Specific Generics
-------------------------------------------------------------------------------
-- C_SIM_MONITOR_FILE -- stimuli file
-- CE_NUMBERS -- read/write chip enble no.
-- IP_INTR_NUM -- interrupt signals no.
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- AXI Slave Interface -- INPUT/OUTPUT Signals
-------------------------------------------------------------------------------
-- Bus2IP_Clk -- bus clock
-- Bus2IP_Rst -- bus reset
-- -- Bus 2 IP IPIC interface
-- Bus2IP_RdCE -- bus read chip enable signals
-- Bus2IP_WrCE -- bus write chip enable signals
-- Bus2IP_Addr -- bus address bits
-- Bus2IP_Data -- bus to ip data
-- -- IP 2 Bus IPIC interface
-- Sysmon_IP2Bus_Data -- data from sysmon
-- Sysmon_IP2Bus_WrAck -- write ack from sysmon
-- Sysmon_IP2Bus_RdAck -- read ack from sysmon
-------------------------------------------------------------------------------
-- XADC EXTERNAL INTERFACE -- INPUT Signals
-------------------------------------------------------------------------------
-- VAUXN -- user selectable differential inputs
-- VAUXP -- user selectable differential inputs
-- CONVST -- Conversion start signal for event-driven
-- sampling mode
-------------------------------------------------------------------------------
-- XADC Interrupt -- OUTPUT Signal to Interrupt Module
-------------------------------------------------------------------------------
-- Interrupt_status -- interrupt from the sysmon core
-- ALARM -- XADC alarm output signals of the hard macro
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_xadc_core_drp is
generic
(
----------------
C_S_AXI_ADDR_WIDTH : integer;
C_S_AXI_DATA_WIDTH : integer;
C_FAMILY : string;
----------------
CE_NUMBERS : integer;
IP_INTR_NUM : integer;
C_SIM_MONITOR_FILE : string ;
----------------
MUX_ADDR_NO : integer
);
port
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
-- Bus 2 IP IPIC interface
Bus2IP_RdCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_WrCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_Addr : in std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- IP 2 Bus IPIC interface
Sysmon_IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Sysmon_IP2Bus_WrAck : out std_logic;
Sysmon_IP2Bus_RdAck : out std_logic;
---------------- interrupt interface with the system -----------
Interrupt_status : out std_logic_vector(0 to IP_INTR_NUM-1);
---------------- sysmon macro interface -------------------
vauxp0 : in STD_LOGIC; -- Auxiliary Channel 0
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC; -- Auxiliary Channel 1
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC; -- Auxiliary Channel 2
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC; -- Auxiliary Channel 4
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC; -- Auxiliary Channel 5
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC; -- Auxiliary Channel 9
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC; -- Auxiliary Channel 10
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC; -- Auxiliary Channel 12
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC; -- Auxiliary Channel 13
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
alarm_out : out STD_LOGIC_VECTOR (7 downto 0);
temp_out : out std_logic_vector(11 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end entity system_xadc_wiz_0_0_xadc_core_drp;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of system_xadc_wiz_0_0_xadc_core_drp is
component temperature_update
port (
reset : in std_logic;
clk : in std_logic;
temp_bus_update : in std_logic;
wait_cycle : in std_logic_vector(15 downto 0);
temp_out : out std_logic_vector(11 downto 0);
-- DRP signals for Arbiter
daddr_o : out std_logic_vector(7 downto 0);
den_o : out std_logic;
di_o : out std_logic_vector(15 downto 0);
dwe_o : out std_logic;
do_i : in std_logic_vector(15 downto 0);
drdy_i : in std_logic;
busy_o : out std_logic
);
end component;
component drp_arbiter
port (
reset : in std_logic;
clk : in std_logic; -- input clock
jtaglocked: in std_logic; -- input clock
bgrant_A : out std_logic; -- bus grant
bgrant_B : out std_logic; -- bus grant
bbusy_A : in std_logic; -- bus busy
bbusy_B : in std_logic := '0'; -- bus busy
daddr_A : in std_logic_vector(7 downto 0);
den_A : in std_logic;
di_A : in std_logic_vector(15 downto 0);
dwe_A : in std_logic;
do_A : out std_logic_vector(15 downto 0);
drdy_A : out std_logic;
daddr_B : in std_logic_vector(7 downto 0);
den_B : in std_logic;
di_B : in std_logic_vector(15 downto 0);
dwe_B : in std_logic;
do_B : out std_logic_vector(15 downto 0);
drdy_B : out std_logic;
daddr_C : out std_logic_vector(7 downto 0);
den_C : out std_logic;
di_C : out std_logic_vector(15 downto 0);
dwe_C : out std_logic;
do_C : in std_logic_vector(15 downto 0);
drdy_C : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant DATA_SIZE_DRP : integer := 16;
constant ADDR_SIZE_DRP : integer := 7;
constant CHANNEL_NO : integer := 5;
constant ALARM_NO : integer := 8; -- updated from 3 to 8 for XADC
constant ALARM_REG_LENGTH : integer := 9;-- internal constant-- updated from 4 to 9 for XADC
constant STATUS_REG_LENGTH : integer := 11;--internal constant
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal daddr_i : std_logic_vector(ADDR_SIZE_DRP-1 downto 0);
signal alm_i : std_logic_vector(ALARM_NO-1 downto 0);
signal channel_i : std_logic_vector(CHANNEL_NO-1 downto 0);
signal mux_addr_no_i : std_logic_vector(MUX_ADDR_NO-1 downto 0);-- added for XADC
signal do_i : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal di_i : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal den_i : std_logic;
signal dwe_i : std_logic;
signal busy_i : std_logic;
signal drdy_i : std_logic;
signal eoc_i : std_logic;
signal eos_i : std_logic;
signal ot_i : std_logic;
signal daddr_C : std_logic_vector(7 downto 0);
signal den_C : std_logic;
signal di_C : std_logic_vector(15 downto 0);
signal dwe_C : std_logic;
signal do_C : std_logic_vector(15 downto 0);
signal drdy_C : std_logic;
signal bgrant_B : std_logic;
signal daddr_i_int : std_logic_vector(ADDR_SIZE_DRP downto 0);
signal temp_bus_update: std_logic := '0';
signal temp_rd_wait_cycle_reg : std_logic_vector(15 downto 0) := X"03E8";
-- JTAG related signals
signal jtaglocked_i : std_logic;
signal jtagbusy_i : std_logic;
signal jtagmodified_i : std_logic;
signal jtagmodified_d1 : std_logic;
signal jtag_modified_info: std_logic;
-------------------------------------------------------------------------------
-- Following signals are used as internal signals
signal do_reg : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal alarm_reg : std_logic_vector(ALARM_REG_LENGTH-1 downto 0);
signal status_reg : std_logic_vector(STATUS_REG_LENGTH-1 downto 0);
-------------------------------------------------------------------------------
signal convst_rst_wrce_or_reduce : std_logic;
signal local_rdce_or_reduce : std_logic;
signal register_rdce_select : std_logic_vector(0 to 2);
signal convst_reset_wrce_select : std_logic_vector(0 to 1);
-------------------------------------------------------------------------------
signal eoc_d1 : std_logic;
signal eos_d1 : std_logic;
signal eoc_info : std_logic;
signal eos_info : std_logic;
-------------------------------------------------------------------------------
signal convst_reg : std_logic := '0';
signal hard_macro_rst_reg : std_logic;
signal sysmon_hard_block_reset : std_logic;
-------------------------------------------------------------------------------
signal local_reg_rdack_final : std_logic;
signal status_reg_rdack : std_logic;
signal status_reg_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
signal local_reg_wrack : std_logic;
signal local_reg_wrack_d1 : std_logic;
signal local_reg_rdack : std_logic;
signal local_reg_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
signal sysmon_IP2Bus_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
signal drdy_rd_ack_i : std_logic;
signal drdy_wr_ack_i : std_logic;
signal drdy_rd_ack_i_d1 : std_logic;
signal drdy_rd_ack_i_d2 : std_logic;
signal drdy_wr_ack_i_d1 : std_logic;
signal drdy_wr_ack_i_d2 : std_logic;
signal convst_d1 : std_logic;
-------------------------------------------------------------------------------
signal convst_reg_input : std_logic;
signal den_d1 : std_logic;
signal den_actual : std_logic;
signal dwe_d1 : std_logic;
signal dwe_actual : std_logic;
-------------------------------------------------------------------------------
-- The following signals are locally declared signals and will not be connected
-- to any where from XADC hard macro. EDK has dedicated VN/VP ports and these
-- are connected to the board like power supply pins, so it is not required
-- that these ports to be listed in the port list of the core.
-- in simulation these signals will show as un-initialised.
-------------------------------------------------------------------------------
--following signals are added for providing the falling edge interrupt detection
signal ot_d1 : std_logic;
signal ot_falling_edge : std_logic;
--
signal alarm_0_d1 : std_logic;
signal alarm_0_falling_edge : std_logic;
--
signal alarm_3_d1 : std_logic;
signal vbram_alarm_3_falling_edge : std_logic;
--
signal alarm_4_d1 : std_logic;
signal vccpint_alarm_4_falling_edge : std_logic;
--
signal aux_channel_p : std_logic_vector (15 downto 0);
signal aux_channel_n : std_logic_vector (15 downto 0);
signal daddr_A : std_logic_vector(7 downto 0);
signal den_A : std_logic;
signal di_A : std_logic_vector(15 downto 0);
signal dwe_A : std_logic;
signal do_A : std_logic_vector(15 downto 0);
signal drdy_A : std_logic;
signal bbusy_A : std_logic;
signal drp_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Assign temporary internal signal to separate out Addr bit 23 to Addr bit 29
-- from PLB address lines
-- As the addresses for XADC are word aligned, it is required to trim the
-- address bit 30 and 31. The incoming address from PLB is word aligned.
-- The internal register file interface are at sequential address like
-- 0x00h, 0x01h...etc
-------------------------------------------------------------------------------
-- daddr_i <= Bus2IP_Addr(23 to 29);
daddr_i <= Bus2IP_Addr(2 to 8);
-------------------------------------------------------------------------------
-- Data from PLB will be assigned to the DI port of DRP
-- Assign the last half word (bit 16 to 31)data from PLB DATA Bus to the
-- internal signal
-------------------------------------------------------------------------------
di_i <= Bus2IP_Data((C_S_AXI_DATA_WIDTH/2) to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
-- If jtaglocked_i output from XADC goes high, it prevents read/write access
-- to DRP port
-------------------------------------------------------------------------------
-- JTAGLOCKED_RD_PROCESS
------------------------
-- generate enable signal for DRP. the enable signal is logical AND of
-- chip enable for the address range of REG_FILE_BASEADDR
-------------------------------------------------------------------------------
JTAGLOCKED_RD_PROCESS: process(jtaglocked_i,
Bus2IP_RdCE(CE_NUMBERS-1),
Bus2IP_WrCE(CE_NUMBERS-1)
) is
begin
if (jtaglocked_i ='1') then
den_i <= '0';
else
den_i <= (
Bus2IP_RdCE(CE_NUMBERS-1)
or
Bus2IP_WrCE(CE_NUMBERS-1)
);
end if;
end process JTAGLOCKED_RD_PROCESS;
-------------------------------------------------------------------------------
-- DEN_REG_PROCESS
------------------------
-- generate enable signal for DRP for "Single Clock Cycle" only.
-------------------------------------------------------------------------------
DEN_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
den_d1 <= den_i;
end if;
end process DEN_REG_PROCESS;
den_actual <= den_i and (not den_d1);
-------------------------------------------------------------------------------
-- JTAGLOCKED_WR_PROCESS
------------------------
-- This signal will be interfaced with DWE port of XADC
-------------------------------------------------------------------------------
JTAGLOCKED_WR_PROCESS: process(jtaglocked_i,
Bus2IP_WrCE(CE_NUMBERS-1)
) is
begin
if (jtaglocked_i ='1') then
dwe_i <= '0';
else
dwe_i <= Bus2IP_WrCE(CE_NUMBERS-1);
end if;
end process JTAGLOCKED_WR_PROCESS;
DWE_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
dwe_d1 <= dwe_i;
end if;
end process DWE_REG_PROCESS;
dwe_actual <= dwe_i and (not dwe_d1);
-------------------------------------------------------------------------------
-- JTAGLOCKED_WR_ACK_PROCESS
----------------------------
-- Generate the internal register write_ack, when the DRDY from XADC is high
-- as well as the WrCE(5) signal from PLB is high.
-- This Write Ack is only when PLB accesses DRP port.
-- _____|--------|____ WrCE
-- ___________|--|__ DRDY is active for 1 clock cycle = one clock width ack
-- DRDY will go high after the 4th clock cycle when the data, address, control
-- signals are present on the interface.
-- Delayed the ACK generated when jtaglock='1'.
-------------------------------------------------------------------------------
JTAGLOCKED_WR_ACK_PROCESS:process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if(Bus2IP_Rst = RESET_ACTIVE) then
drdy_wr_ack_i <= '0';
drdy_wr_ack_i_d1 <= '0';
drdy_wr_ack_i_d2 <= '0';
elsif (jtaglocked_i ='1') then
drdy_wr_ack_i_d1 <= Bus2IP_WrCE(CE_NUMBERS-1);
drdy_wr_ack_i_d2 <= drdy_wr_ack_i_d1;
drdy_wr_ack_i <= drdy_wr_ack_i_d1 and (not drdy_wr_ack_i_d2);
else
drdy_wr_ack_i <= drdy_i and Bus2IP_WrCE(CE_NUMBERS-1);
end if;
end if;
end process JTAGLOCKED_WR_ACK_PROCESS;
-------------------------------------------------------------------------------
-- JTAGLOCKED_RD_ACK_PROCESS
----------------------------
-- Generate the internal read_ack, when the DRDY from XADC is high as well as
-- the RdCE(5) signal from PLB is high
-- This Read Ack is only when PLB accesses DRP port.
-- Delayed the ACK generated when jtaglock='1'.
-------------------------------------------------------------------------------
JTAGLOCKED_RD_ACK_PROCESS:process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if(Bus2IP_Rst = RESET_ACTIVE) then
drdy_rd_ack_i <= '0';
drdy_rd_ack_i_d1 <= '0';
drdy_rd_ack_i_d2 <= '0';
elsif (jtaglocked_i ='1') then
drdy_rd_ack_i_d1 <= Bus2IP_RdCE(CE_NUMBERS-1);
drdy_rd_ack_i_d2 <= drdy_rd_ack_i_d1;
drdy_rd_ack_i <= drdy_rd_ack_i_d1 and (not drdy_rd_ack_i_d2);
else
drdy_rd_ack_i <= drdy_i and Bus2IP_RdCE(CE_NUMBERS-1);
end if;
end if;
end process JTAGLOCKED_RD_ACK_PROCESS;
-------------------------------------------------------------------------------
-- It is required to register the DRDY as well as DO ports of the XADC .
-- This will delay the ACK generation by one clock cycle.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- DO_REG_PROCESS
-----------------
-- This process is used to register the DO port of DRP in the
-- local register. If JTAG access is going on, then core need to wait till the
-- JTAG access ends. Once the JTAG access is over the Bus2IP_Addr, DEN are
-- presented to the DRP, then DO of DRP put the data as per the DADDR by making
-- the DRDY high for 1 clock cycle.
-------------------------------------------------------------------------------
DO_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(Bus2IP_Rst = RESET_ACTIVE) then
do_reg <= (others => '0');
elsif (jtaglocked_i ='1') then
do_reg <= (others => '0');
else
do_reg <= do_i;
end if;
end if;
end process DO_REG_PROCESS;
-------------------------------------------------------------------------------
-- combine for CONVST and reset macro write chip enable signals
-------------------------------------------------------------------------------
convst_reset_wrce_select <= Bus2IP_WrCE(3) & Bus2IP_WrCE(4);
-------------------------------------------------------------------------------
-- CONVST_RST_PROCESS:
----------------------
-- This process is used to register the CONVST and XADC RST signals
-- The bit 31st Bus2IP_Data is used along with the Bus2IP_WrCE(3 to 4)
-- to start the conversion or to reset the sysmon through software.
-------------------------------------------------------------------------------
CONVST_RST_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
convst_reg_input <= '0';
hard_macro_rst_reg <= '0';
temp_bus_update <= '0';
temp_rd_wait_cycle_reg <= X"03E8";
else
case convst_reset_wrce_select is
when "10" => convst_reg_input <= Bus2IP_Data(31);
temp_bus_update <= '1';
temp_rd_wait_cycle_reg <= Bus2IP_Data(14 to 29);
when "01" => hard_macro_rst_reg <= Bus2IP_Data(31);
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process CONVST_RST_PROCESS;
-- Generate the WRITE ACK back to PLB
Sysmon_IP2Bus_WrAck <= (drdy_wr_ack_i or local_reg_wrack) ;
-- Generate the READ ACK back to PLB
Sysmon_IP2Bus_RdAck <= (drdy_rd_ack_i or local_reg_rdack_final);
-------------------------------------------------------------------------------
-- Bus reset as well as the hard macro register reset
-------------------------------------------------------------------------------
-- XADC Reset Register (SYSMONRR)
-------------------------------------------------------------------------------
sysmon_hard_block_reset<= Bus2IP_Rst or hard_macro_rst_reg;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- EOC_REG_EXTEND_PROCESS
-------------------------
-- Extend the EOC signal which is active high for 1 clock cycle till the
-- PLB reads the status register.
-- _____|--|__________ one clock width EOC
-- _____|--------|____ extended EOC
-------------------------------------------------------------------------------
EOC_REG_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
eoc_d1 <= '0';
elsif(eoc_i = '1') then
eoc_d1 <= '1';
elsif(status_reg_rdack = '1')then
eoc_d1 <= '0';
end if;
end if;
end process EOC_REG_EXTEND_PROCESS;
eoc_info <= eoc_d1 or eoc_i;
-------------------------------------------------------------------------------
-- EOS_REG_EXTEND_PROCESS
-------------------------
-- Extend the EOS signal which is active high for 1 clock cycle till the
-- PLB reads the status register.
-- _____|--|__________ one clock width EOS
-- _____|--------|____ extended EOS
-------------------------------------------------------------------------------
EOS_REG_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
eos_d1 <= '0';
elsif(eos_i = '1') then
eos_d1 <= '1';
elsif(status_reg_rdack = '1')then
eos_d1 <= '0';
end if;
end if;
end process EOS_REG_EXTEND_PROCESS;
eos_info <= eos_d1 or eos_i;
-------------------------------------------------------------------------------
-- JTAGMODIFIED_EXTEND_PROCESS
-------------------------
-- Extend the JTAGMODIFIED signal which is active high till the DRP read is
-- performed
-- __________|------ RDCE to DRP
-- _____|----|_____ JTAGMODIFIED
-- _______|------|____ extended JTAGMODIFIED
-- _____|--------|____ jtag_modified_info
-------------------------------------------------------------------------------
JTAGMODIFIED_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE or drdy_rd_ack_i = '1') then
jtagmodified_d1 <= '0';
elsif(jtagmodified_i = '1') then
jtagmodified_d1 <= '1';
end if;
end if;
end process JTAGMODIFIED_EXTEND_PROCESS;
jtag_modified_info <= jtagmodified_i or jtagmodified_d1;
-------------------------------------------------------------------------------
-- STATUS_REG_PROCESS
---------------------
-- This process is used to register the JTAG, BUSY, EOC, EOS,
-- & Channel bits in internal register
-------------------------------------------------------------------------------
STATUS_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
status_reg <= (others => '0');
else
status_reg(10) <= jtagbusy_i;
status_reg(9) <= jtag_modified_info;
status_reg(8) <= jtaglocked_i;
status_reg(7) <= busy_i;
status_reg(6) <= eos_info;
status_reg(5) <= eoc_info;
status_reg(4) <= channel_i(4);
status_reg(3) <= channel_i(3);
status_reg(2) <= channel_i(2);
status_reg(1) <= channel_i(1);
status_reg(0) <= channel_i(0);
end if;
end if;
end process STATUS_REG_PROCESS;
busy_out <= busy_i;
channel_out <= channel_i;
eoc_out <= eoc_i;
eos_out <= eos_i;
-------------------------------------------------------------------------------
-- ALARM_REG_PROCESS (ALARM OUTPUT STATUS REGISTER - AOSR)
-----------------------------------------------------------
-- This process is used to register the ALARM, OT bits in internal register
-------------------------------------------------------------------------------
ALARM_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
alarm_reg <= (others => '0');
else
alarm_reg(8) <= alm_i(7);-- added for XADC
alarm_reg(7) <= alm_i(6);
alarm_reg(6) <= alm_i(5);
alarm_reg(5) <= alm_i(4);
alarm_reg(4) <= alm_i(3);-- added for XADC
alarm_reg(3) <= alm_i(2);
alarm_reg(2) <= alm_i(1);
alarm_reg(1) <= alm_i(0);
alarm_reg(0) <= ot_i;
end if;
end if;
end process ALARM_REG_PROCESS;
--------------------------
-- OT_FALLING_EDGE_DETECT: this process is used to register the OT.
--------------------------
-- ____|-------|________ ot_i
-- ______|-------|______ ot_d1
-- ____________|-|______ ot_falling_edge
----------------------------------------
OT_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
ot_d1 <= ot_i;
end if;
end process OT_FALLING_EDGE_DETECT;
ot_falling_edge <= ot_d1 and (not ot_i);
------------------------------
-- ALARM_0_FALLING_EDGE_DETECT: User temperature settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(0)
-- ______|-------|______ alm_i(0)_d1
-- ____________|-|______ alarm_0_falling_edge
---------------------------------------------
ALARM_0_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
alarm_0_d1 <= alm_i(0);
end if;
end process ALARM_0_FALLING_EDGE_DETECT;
alarm_0_falling_edge <= alarm_0_d1 and (not alm_i(0));
------------------------------
-- ALARM_3_FALLING_EDGE_DETECT: VBRM settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(3)
-- ______|-------|______ alm_i(3)_d1
-- ____________|-|______ vbram_alarm_3_falling_edge
---------------------------------------------
--ALARM_3_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
--begin
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- alarm_3_d1 <= alm_i(3);
-- end if;
--end process ALARM_3_FALLING_EDGE_DETECT;
--vbram_alarm_3_falling_edge <= alarm_3_d1 and (not alm_i(3));
------------------------------
-- ALARM_4_FALLING_EDGE_DETECT: VCCPINT settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(4)
-- ______|-------|______ alm_i(4)_d1
-- ____________|-|______ vccpint_alarm_4_falling_edge
---------------------------------------------
--ALARM_4_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
--begin
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- alarm_4_d1 <= alm_i(4);
-- end if;
--end process ALARM_4_FALLING_EDGE_DETECT;
--vccpint_alarm_4_falling_edge <= alarm_4_d1 and (not alm_i(4));
-------------------------------------------------------------------------------
-- dont register any interrupt signal and just pass
-- it on to the interrupt controller
-------------------------------------------------------------------------------
Interrupt_status(0) <= ot_i;
Interrupt_status(1) <= alm_i(0);
Interrupt_status(2) <= alm_i(1);
Interrupt_status(3) <= alm_i(2);
Interrupt_status(4) <= eos_i;
Interrupt_status(5) <= eoc_i;
Interrupt_status(6) <= jtaglocked_i;
Interrupt_status(7) <= jtagmodified_i;
Interrupt_status(8) <= ot_falling_edge;
Interrupt_status(9) <= alarm_0_falling_edge;
Interrupt_status(10) <= alm_i(3);-- Added for XADC VccBram sensor o/p
Interrupt_status(11) <= alm_i(4); -- XADC VCCPint sensor o/p for Zynq
Interrupt_status(12) <= alm_i(5); -- XADC VCCPaux sensor o/p for Zynq
Interrupt_status(13) <= alm_i(6); -- XADC VCCddro sensor o/p for Zynq
Interrupt_status(14) <= '0';
Interrupt_status(15) <= '0';
Interrupt_status(16) <= '0';
-------------------------------------------------------------------------------
-- Status Register, Alarm Reg and DRP Register File Interface (RFI) can be READ
-------------------------------------------------------------------------------
register_rdce_select <= Bus2IP_RdCE(1) & -- Status Register
Bus2IP_RdCE(2) & -- AOSR
Bus2IP_RdCE(CE_NUMBERS-1);-- DPR
-------------------------------------------------------------------------------
-- The upper bits are always '0'.
-------------------------------------------------------------------------------
sysmon_IP2Bus_Data_i(0 to 13)<=(others => '0');
-------------------------------------------------------------------------------
-- LOCAL_REG_READ_PROCESS
-------------------------
LOCAL_REG_READ_PROCESS: process (register_rdce_select,
status_reg,
alarm_reg,
do_reg,
jtag_modified_info,
jtaglocked_i) is
begin
case register_rdce_select is
-- bus2ip_rdce(1,2,8)
when "100" =>
sysmon_IP2Bus_Data_i(14 to 31) <= "0000000" & status_reg;
when "010" =>
sysmon_IP2Bus_Data_i(14 to 31) <= "000000000" & alarm_reg;
when "001" =>
sysmon_IP2Bus_Data_i(14 to 31) <= jtag_modified_info &
jtaglocked_i &
do_reg;
-- coverage off
when others =>
sysmon_IP2Bus_Data_i(14 to 31) <= (others => '0');
-- coverage on
end case;
end process LOCAL_REG_READ_PROCESS;
-------------------------------------------------------------------------------
-- STATUS_REG_READ_ACK_GEN_PROCESS
----------------------------------
-- To generate the RdAck for status registers, use RdCE
-------------------------------------------------------------------------------
-- _____|-----|_______ rdce
-- ________|--|__________ rd_ack from local registers i.e. status register
-------------------------------------------------------------------------------
STATUS_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
status_reg_rdack_d1 <= '0';
status_reg_rdack <= '0';
else
status_reg_rdack_d1 <= Bus2IP_RdCE(1);
status_reg_rdack <= Bus2IP_RdCE(1) and (not status_reg_rdack_d1);
end if;
end if;
end process STATUS_REG_READ_ACK_GEN_PROCESS;
-------------------------------------------------------------------------------
-- For register which are just write-only a read ack is required for completing
-- the transaction.
-------------------------------------------------------------------------------
local_rdce_or_reduce <= or_reduce(Bus2IP_RdCE(2 to 4));
-------------------------------------------------------------------------------
-- LOCAL_REG_READ_ACK_GEN_PROCESS
---------------------------------
-- To generate the RdAck for alarm,CONVST,XADC Hard Macro registers,
-- use RdCE
-------------------------------------------------------------------------------
-- _____|-----|_______ rdce
-- ________|--|__________ rd_ack from local registers
-------------------------------------------------------------------------------
LOCAL_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
local_reg_rdack_d1 <= '0';
local_reg_rdack <= '0';
else
local_reg_rdack_d1 <= local_rdce_or_reduce;
local_reg_rdack <= local_rdce_or_reduce and (not local_reg_rdack_d1);
end if;
end if;
end process LOCAL_REG_READ_ACK_GEN_PROCESS;
local_reg_rdack_final <= status_reg_rdack or local_reg_rdack;
-------------------------------------------------------------------------------
-- For register which are just read-only a write ack is required for completing
-- the transaction.
-------------------------------------------------------------------------------
convst_rst_wrce_or_reduce <= or_reduce(Bus2IP_WrCE(1 to 4));
-------------------------------------------------------------------------------
-- LOCAL_REG_WRITE_ACK_GEN_PROCESS
----------------------------------
-- To generate the WrAck for local registers, use WrCE
-------------------------------------------------------------------------------
-- _____|-----|_______ wrce
-- ________|--|__________ wr_ack from local registers
-- i.e. convst,reset register
-------------------------------------------------------------------------------
LOCAL_REG_WRITE_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
local_reg_wrack_d1 <= '0';
local_reg_wrack <= '0';
else
local_reg_wrack_d1 <= convst_rst_wrce_or_reduce;
local_reg_wrack <= convst_rst_wrce_or_reduce and
(not local_reg_wrack_d1);
end if;
end if;
end process LOCAL_REG_WRITE_ACK_GEN_PROCESS;
-------------------------------------------------------------------------------
-- All the signals listed here are FROM IP to PLB IPIF INTERFACE
-------------------------------------------------------------------------------
-- Present the DRP data to Sysmon_IP2Bus_Data
Sysmon_IP2Bus_Data <= sysmon_IP2Bus_Data_i;
-------------------------------------------------------------------------------
-- Added interface to ALARM signals from the XADC macro to core ports.
------------------------------------------------------------------------
alarm_out <= alarm_reg(8 downto 1);-- updated from 2 downto 1 to 8 downto 1 for XADC
------------------------------------------------------------------------
daddr_i_int <= '0' & daddr_i;
-- Instantiate the temperature_update and arbiter
temperature_update_inst: temperature_update port map (
reset => sysmon_hard_block_reset,
clk => Bus2IP_Clk,
wait_cycle => temp_rd_wait_cycle_reg,
temp_out => temp_out,
temp_bus_update => temp_bus_update,
daddr_o => daddr_A,
den_o => den_A,
di_o => di_A,
dwe_o => dwe_A,
do_i => do_A,
drdy_i => drdy_A,
busy_o => bbusy_A
);
Inst_drp_arbiter: drp_arbiter port map (
reset => sysmon_hard_block_reset,
clk => Bus2IP_Clk ,
jtaglocked => jtaglocked_i,
bgrant_A => open ,
bgrant_B => bgrant_B,
bbusy_A => bbusy_A,
bbusy_B => '0',
daddr_A => daddr_A,
den_A => den_A,
di_A => di_A,
dwe_A => dwe_A,
do_A => do_A,
drdy_A => drdy_A,
daddr_B => daddr_i_int,
den_B => den_actual,
di_B => di_i,
dwe_B => dwe_actual,
do_B => do_i,
drdy_B => drdy_i,
daddr_C => daddr_C,
den_C => den_C,
di_C => di_C,
dwe_C => dwe_C,
do_C => do_C,
drdy_C => drdy_C
);
-- Added interface to MUX ADDRESS for external address multiplexer from the
-- XADC macro to core ports.
-------------------------------------------------------------------------------
-- == XADC INTERFACE -- OUTPUT Signals ==
-------------------------------------------------------------------------------
-- BUSY -- ADC busy signal
-- DRDY -- Data ready signal for Dynamic Reconfigurable Port
-- EOC -- End of conversion for ADC
-- EOS -- End of sequence used in auto sequence mode
-- JTAGBUSY -- Used to indicate that the JTAG DRP is doing transaction
-- JTAGLOCKED -- Used to indicate the DRP port lock is requested
-- JTAGMODIFIED -- Used to indicate that the JTAG write to JTAG is happened
-- OT -- Signal for Over Temperature alarm
-- ALM -- Sysmon Alarm outputs
-- CHANNEL -- Channel selection outputs
-- DO -- Output data bus for Dynamic Reconfigurable Port
-------------------------------------------------------------------------------
-- == XADC INTERFACE -- INPUT Signals ==
-------------------------------------------------------------------------------
-- VN -- High Bandwidth Dedicated analog input pair
-- VP which provides differential analog input. These pins are
-- just like dedicated suply pins and user dont have control
-- over these pins.
-- CONVST -- Conversion start input used in event driven sampling
-- CONVSTCLK -- Conversion start clock input
-- DCLK -- Clock input for Dynamic Reconfigurable Port
-- DEN -- Enable signal for Dynamic Reconfigurable Port
-- DWE -- Write Enable signal for Dynamic Reconfigurable Port
-- RESET -- External hard Reset input
-- DADDR -- Address bus for Dynamic Reconfigurable Port
-- DI -- Input data bus for Dynamic Reconfigurable Port
-- VAUXN -- Low Bandwidth, Sixteen auxiliary analog input pairs
-- VAUXP which provides differential analog inputs
-- MUXADDR -- External address multiplexer driven by Channel selection
-- Registers
aux_channel_p(0) <= vauxp0;
aux_channel_n(0) <= vauxn0;
aux_channel_p(1) <= vauxp1;
aux_channel_n(1) <= vauxn1;
aux_channel_p(2) <= vauxp2;
aux_channel_n(2) <= vauxn2;
aux_channel_p(3) <= '0';
aux_channel_n(3) <= '0';
aux_channel_p(4) <= vauxp4;
aux_channel_n(4) <= vauxn4;
aux_channel_p(5) <= vauxp5;
aux_channel_n(5) <= vauxn5;
aux_channel_p(6) <= vauxp6;
aux_channel_n(6) <= vauxn6;
aux_channel_p(7) <= vauxp7;
aux_channel_n(7) <= vauxn7;
aux_channel_p(8) <= '0';
aux_channel_n(8) <= '0';
aux_channel_p(9) <= vauxp9;
aux_channel_n(9) <= vauxn9;
aux_channel_p(10) <= vauxp10;
aux_channel_n(10) <= vauxn10;
aux_channel_p(11) <= '0';
aux_channel_n(11) <= '0';
aux_channel_p(12) <= vauxp12;
aux_channel_n(12) <= vauxn12;
aux_channel_p(13) <= vauxp13;
aux_channel_n(13) <= vauxn13;
aux_channel_p(14) <= vauxp14;
aux_channel_n(14) <= vauxn14;
aux_channel_p(15) <= vauxp15;
aux_channel_n(15) <= vauxn15;
XADC_INST : XADC
generic map(
INIT_40 => X"0000", -- config reg 0
INIT_41 => X"21A1", -- config reg 1
INIT_42 => X"0400", -- config reg 2
INIT_48 => X"0900", -- Sequencer channel selection
INIT_49 => X"F6F7", -- Sequencer channel selection
INIT_4A => X"0000", -- Sequencer Average selection
INIT_4B => X"0000", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"B5ED", -- Temp alarm trigger
INIT_51 => X"53A0", -- Vccint upper alarm limit
INIT_52 => X"A147", -- Vccaux upper alarm limit
INIT_53 => X"CA33", -- Temp alarm OT upper
INIT_54 => X"A93A", -- Temp alarm reset
INIT_55 => X"5111", -- Vccint lower alarm limit
INIT_56 => X"9555", -- Vccaux lower alarm limit
INIT_57 => X"AE4E", -- Temp alarm OT reset
INIT_58 => X"5999", -- Vccbram upper alarm limit
INIT_5C => X"5111", -- Vccbram lower alarm limit
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "design.txt"
)
port map (
CONVST => '0',
CONVSTCLK => '0',
DADDR => daddr_C(6 downto 0), --: in (6 downto 0)
DCLK => Bus2IP_Clk, --: in
DEN => den_C, --: in
DI => di_C, --: in (15 downto 0)
DWE => dwe_C, --: in
RESET => sysmon_hard_block_reset, --: in
VAUXN(15 downto 0) => aux_channel_n(15 downto 0),
VAUXP(15 downto 0) => aux_channel_p(15 downto 0),
ALM => alm_i,
BUSY => busy_i, --: out
CHANNEL => channel_i, --: out (4 downto 0)
DO => do_C, --: out (15 downto 0)
DRDY => drdy_C, --: out
EOC => eoc_i, --: out
EOS => eos_i, --: out
JTAGLOCKED => jtaglocked_i, --: out
JTAGBUSY => jtagbusy_i, --: out
JTAGMODIFIED => jtagmodified_i, --: out
OT => ot_i, --: out
VN => vn_in,
VP => vp_in
);
end architecture imp;
--------------------------------------------------------------------------------
|
apache-2.0
|
28c50f92bf47997b7f1f9d269cf9344f
| 0.440932 | 4.32291 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALU/alu_toplevel.vhd
| 1 | 2,607 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
mit
|
4f0f338d0053afae8d51cdf0035a211d
| 0.489068 | 3.891045 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/CounterTest/debounce.vhd
| 2 | 2,029 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debouncer
-- Debounce Input Signal
-- Input is fed through two flip flops
-- If both flip flops(2 cycles) have a high then
-- the counter will increment till it goes to
-- the necessary wait time.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
entity debounce is
Generic ( wait_time : INTEGER := 20);
-- Wait_time is a fixed time to wait to validate a debounce signal
-- Wait time is based on the Nexys 50 MHZ Clock
-- XX : (2^xx + 2)/CLK
-- 21 : 41.9ms | (2^21 + 2)/50E6
-- 20 : 21.0ms | (2^20 + 2)/50E6
-- 19 : 10.5ms | (2^19 + 2)/50E6
-- 18 : 5.2ms | (2^18 + 2)/50E6
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
INPUT : in STD_LOGIC;
OUTPUT : out STD_LOGIC);
end debounce;
architecture Logic of debounce is
signal D_STATE : STD_LOGIC_VECTOR (1 downto 0);
signal D_SET : STD_LOGIC;
signal Count : STD_LOGIC_VECTOR( wait_time downto 0) := (others => '0');
begin
D_SET <= D_STATE(0) xor D_STATE(1);
--Check what the deboune states are
-- *if their is a change in state then D_SET will be set to a high
input_monitor: process (EN, CLK)
begin
if (CLK'event and CLK = '1' and EN = '1') then
D_STATE(0) <= INPUT;
D_STATE(1) <= D_STATE(0);
if(D_SET = '1') then
Count <= (others => '0');
elsif(Count(wait_time) = '0') then
Count <= Count + 1;
else
OUTPUT <= D_STATE(1);
end if;
end if;
end process;
end Logic;
|
mit
|
cb7fe9b337d14007a3a376434a19f76f
| 0.546575 | 3.584806 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_quad_spi_flash_0/system_axi_quad_spi_flash_0_sim_netlist.vhdl
| 1 | 669,579 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:39 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_quad_spi_flash_0/system_axi_quad_spi_flash_0_sim_netlist.vhdl
-- Design : system_axi_quad_spi_flash_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\ is
port (
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => Q(4),
I1 => start2,
I2 => Q(2),
I3 => Q(1),
I4 => Q(3),
I5 => Q(0),
O => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\ is
port (
p_14_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => Q(4),
I3 => start2,
I4 => Q(3),
I5 => Q(1),
O => p_14_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\ is
port (
p_5_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(4),
I3 => start2,
I4 => Q(0),
I5 => Q(3),
O => p_5_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\ is
port (
p_4_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000400000000000"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
I3 => Q(3),
I4 => Q(4),
I5 => start2,
O => p_4_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\ is
port (
p_3_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(4),
I3 => start2,
I4 => Q(0),
I5 => Q(3),
O => p_3_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\ is
port (
p_2_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => Q(1),
I1 => Q(4),
I2 => start2,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => p_2_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\ is
port (
p_1_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => Q(4),
I3 => start2,
I4 => Q(3),
I5 => Q(2),
O => p_1_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\ is
port (
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => Q(1),
I3 => Q(3),
I4 => start2,
I5 => Q(4),
O => \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\ is
port (
p_13_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(4),
I3 => start2,
I4 => Q(3),
I5 => Q(0),
O => p_13_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\ is
port (
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0200000000000000"
)
port map (
I0 => Q(2),
I1 => Q(0),
I2 => Q(3),
I3 => start2,
I4 => Q(4),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\ is
port (
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => Q(1),
I3 => Q(4),
I4 => Q(3),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\ is
port (
p_12_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => Q(3),
I1 => Q(1),
I2 => Q(0),
I3 => Q(2),
I4 => Q(4),
I5 => start2,
O => p_12_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\ is
port (
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => Q(2),
I1 => Q(0),
I2 => Q(4),
I3 => Q(3),
I4 => start2,
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\ is
port (
p_11_out_1 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => Q(2),
I1 => Q(0),
I2 => Q(4),
I3 => start2,
I4 => Q(3),
I5 => Q(1),
O => p_11_out_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\ is
port (
p_10_out_2 : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(0),
I3 => Q(1),
I4 => Q(4),
I5 => start2,
O => p_10_out_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\ is
port (
p_9_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => Q(3),
I1 => Q(1),
I2 => Q(2),
I3 => Q(0),
I4 => Q(4),
I5 => start2,
O => p_9_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\ is
port (
p_8_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => Q(3),
I1 => Q(1),
I2 => Q(0),
I3 => Q(4),
I4 => start2,
I5 => Q(2),
O => p_8_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\ is
port (
p_7_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => Q(4),
I1 => start2,
I2 => Q(2),
I3 => Q(3),
I4 => Q(1),
I5 => Q(0),
O => p_7_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\ is
port (
p_6_out : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
start2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\ : entity is "axi_lite_ipif_v3_0_4_pselect_f";
end \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\ is
begin
CS: unisim.vcomponents.LUT6
generic map(
INIT => X"0000100000000000"
)
port map (
I0 => Q(2),
I1 => Q(4),
I2 => start2,
I3 => Q(0),
I4 => Q(1),
I5 => Q(3),
O => p_6_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_cdc_sync is
port (
scndry_out : out STD_LOGIC;
prmry_in : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_cdc_sync : entity is "cdc_sync";
end system_axi_quad_spi_flash_0_cdc_sync;
architecture STRUCTURE of system_axi_quad_spi_flash_0_cdc_sync is
signal s_level_out_d1_cdc_to : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_cdc_sync_0 is
port (
D : out STD_LOGIC_VECTOR ( 0 to 0 );
scndry_out : out STD_LOGIC;
\updown_cnt_en_rx__4\ : out STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_synced_i : out STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\icount_out_reg[1]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[1]\ : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_sig : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_flag : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
spiXfer_done_to_axi_1 : in STD_LOGIC;
Rx_FIFO_Full_int : in STD_LOGIC;
\out\ : in STD_LOGIC;
prmry_in : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_cdc_sync_0 : entity is "cdc_sync";
end system_axi_quad_spi_flash_0_cdc_sync_0;
architecture STRUCTURE of system_axi_quad_spi_flash_0_cdc_sync_0 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => \^scndry_out\,
R => '0'
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF888"
)
port map (
I0 => \^scndry_out\,
I1 => bus2ip_rdce_int(0),
I2 => Q(0),
I3 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
I4 => \icount_out_reg[1]\,
I5 => \goreg_dm.dout_i_reg[1]\,
O => D(0)
);
\icount_out[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000450000454500"
)
port map (
I0 => Rx_FIFO_Full_Fifo_d1_sig,
I1 => Rx_FIFO_Full_Fifo_d1_flag,
I2 => \^scndry_out\,
I3 => \IP2Bus_RdAck_receive_enable__1\,
I4 => spiXfer_done_to_axi_1,
I5 => Rx_FIFO_Full_int,
O => \updown_cnt_en_rx__4\
);
rc_FIFO_Full_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^scndry_out\,
I1 => \out\,
O => Rx_FIFO_Full_Fifo_d1_synced_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_counter_f is
port (
rx_fifo_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ : out STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_reg\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : in STD_LOGIC;
spiXfer_done_to_axi_1 : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
p_2_in : in STD_LOGIC;
\out\ : in STD_LOGIC;
p_4_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
Rx_FIFO_Full_int : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_counter_f : entity is "counter_f";
end system_axi_quad_spi_flash_0_counter_f;
architecture STRUCTURE of system_axi_quad_spi_flash_0_counter_f is
signal \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_i_2_n_0\ : STD_LOGIC;
signal \icount_out[1]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[2]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[3]_i_2_n_0\ : STD_LOGIC;
signal \icount_out[3]_i_4_n_0\ : STD_LOGIC;
signal \^rx_fifo_count\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
rx_fifo_count(3 downto 0) <= \^rx_fifo_count\(3 downto 0);
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200030002"
)
port map (
I0 => \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_i_2_n_0\,
I1 => \RESET_FLOPS[15].RST_FLOPS\,
I2 => bus2ip_reset_ipif_inverted,
I3 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
I4 => Rx_FIFO_Full_int,
I5 => \IP2Bus_RdAck_receive_enable__1\,
O => \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_reg\
);
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \^rx_fifo_count\(0),
I1 => \^rx_fifo_count\(1),
I2 => spiXfer_done_to_axi_1,
I3 => \^rx_fifo_count\(2),
I4 => \^rx_fifo_count\(3),
I5 => \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\,
O => \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF08000008080000"
)
port map (
I0 => \^rx_fifo_count\(0),
I1 => p_2_in,
I2 => \out\,
I3 => p_4_in,
I4 => Bus_RNW_reg,
I5 => SPISSR_frm_axi_clk,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\
);
\icount_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFEFFFEFEFF"
)
port map (
I0 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
I3 => \^rx_fifo_count\(1),
I4 => \^rx_fifo_count\(0),
I5 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\,
O => \icount_out[1]_i_1_n_0\
);
\icount_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFEFFFEFEFF"
)
port map (
I0 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
I3 => \^rx_fifo_count\(2),
I4 => \^rx_fifo_count\(1),
I5 => \icount_out[3]_i_4_n_0\,
O => \icount_out[2]_i_1_n_0\
);
\icount_out[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFEFEFEFEFEFEEF"
)
port map (
I0 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
I1 => reset2ip_reset_int,
I2 => \^rx_fifo_count\(3),
I3 => \^rx_fifo_count\(2),
I4 => \^rx_fifo_count\(1),
I5 => \icount_out[3]_i_4_n_0\,
O => \icount_out[3]_i_2_n_0\
);
\icount_out[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"8E"
)
port map (
I0 => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\,
I1 => \^rx_fifo_count\(0),
I2 => \^rx_fifo_count\(1),
O => \icount_out[3]_i_4_n_0\
);
\icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\,
D => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_1\,
Q => \^rx_fifo_count\(0),
R => '0'
);
\icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\,
D => \icount_out[1]_i_1_n_0\,
Q => \^rx_fifo_count\(1),
R => '0'
);
\icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\,
D => \icount_out[2]_i_1_n_0\,
Q => \^rx_fifo_count\(2),
R => '0'
);
\icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\,
D => \icount_out[3]_i_2_n_0\,
Q => \^rx_fifo_count\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_counter_f_1 is
port (
\FIFO_EXISTS.tx_occ_msb_2_reg\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ : out STD_LOGIC;
Tx_FIFO_Empty_intr : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[2]\ : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
\p_39_out__0\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ : in STD_LOGIC;
tx_FIFO_Empty_d1 : in STD_LOGIC;
spiXfer_done_to_axi_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_3_in : in STD_LOGIC;
rx_fifo_count : in STD_LOGIC_VECTOR ( 1 downto 0 );
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_counter_f_1 : entity is "counter_f";
end system_axi_quad_spi_flash_0_counter_f_1;
architecture STRUCTURE of system_axi_quad_spi_flash_0_counter_f_1 is
signal \^fifo_exists.tx_occ_msb_2_reg\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_2_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_3_n_0\ : STD_LOGIC;
signal \icount_out[1]_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out[2]_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out[3]_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out[3]_i_4__0_n_0\ : STD_LOGIC;
signal tx_fifo_count : STD_LOGIC_VECTOR ( 2 downto 1 );
begin
\FIFO_EXISTS.tx_occ_msb_2_reg\(1 downto 0) <= \^fifo_exists.tx_occ_msb_2_reg\(1 downto 0);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BEEE"
)
port map (
I0 => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_2_n_0\,
I1 => p_1_in32_in,
I2 => s_axi_wdata(0),
I3 => \p_39_out__0\,
O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000002000"
)
port map (
I0 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\,
I1 => tx_FIFO_Empty_d1,
I2 => spiXfer_done_to_axi_1,
I3 => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_3_n_0\,
I4 => \^fifo_exists.tx_occ_msb_2_reg\(0),
I5 => tx_fifo_count(1),
O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_2_n_0\
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => tx_fifo_count(2),
I1 => \^fifo_exists.tx_occ_msb_2_reg\(1),
O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_3_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF008000800080"
)
port map (
I0 => \^fifo_exists.tx_occ_msb_2_reg\(1),
I1 => Bus_RNW_reg,
I2 => p_3_in,
I3 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\,
I4 => rx_fifo_count(1),
I5 => Bus_RNW_reg_reg_0,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF888"
)
port map (
I0 => tx_fifo_count(2),
I1 => Bus_RNW_reg_reg,
I2 => Q(0),
I3 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
I4 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\,
I5 => \goreg_dm.dout_i_reg[2]\,
O => D(0)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF008000800080"
)
port map (
I0 => tx_fifo_count(1),
I1 => Bus_RNW_reg,
I2 => p_3_in,
I3 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\,
I4 => rx_fifo_count(0),
I5 => Bus_RNW_reg_reg_0,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\
);
\icount_out[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFEFFFEFEFF"
)
port map (
I0 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
I3 => tx_fifo_count(1),
I4 => \^fifo_exists.tx_occ_msb_2_reg\(0),
I5 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
O => \icount_out[1]_i_1__0_n_0\
);
\icount_out[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFEFEFEFEFEFEEF"
)
port map (
I0 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
I1 => reset2ip_reset_int,
I2 => tx_fifo_count(2),
I3 => tx_fifo_count(1),
I4 => \^fifo_exists.tx_occ_msb_2_reg\(0),
I5 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
O => \icount_out[2]_i_1__0_n_0\
);
\icount_out[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFEFEFEFEFEFEEF"
)
port map (
I0 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
I1 => reset2ip_reset_int,
I2 => \^fifo_exists.tx_occ_msb_2_reg\(1),
I3 => tx_fifo_count(2),
I4 => tx_fifo_count(1),
I5 => \icount_out[3]_i_4__0_n_0\,
O => \icount_out[3]_i_2__0_n_0\
);
\icount_out[3]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8E"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
I1 => \^fifo_exists.tx_occ_msb_2_reg\(0),
I2 => tx_fifo_count(1),
O => \icount_out[3]_i_4__0_n_0\
);
\icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus_RNW_reg_reg_1,
D => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\,
Q => \^fifo_exists.tx_occ_msb_2_reg\(0),
R => '0'
);
\icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus_RNW_reg_reg_1,
D => \icount_out[1]_i_1__0_n_0\,
Q => tx_fifo_count(1),
R => '0'
);
\icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus_RNW_reg_reg_1,
D => \icount_out[2]_i_1__0_n_0\,
Q => tx_fifo_count(2),
R => '0'
);
\icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Bus_RNW_reg_reg_1,
D => \icount_out[3]_i_2__0_n_0\,
Q => \^fifo_exists.tx_occ_msb_2_reg\(1),
R => '0'
);
tx_FIFO_Empty_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\,
I1 => \^fifo_exists.tx_occ_msb_2_reg\(1),
I2 => spiXfer_done_to_axi_1,
I3 => \^fifo_exists.tx_occ_msb_2_reg\(0),
I4 => tx_fifo_count(1),
I5 => tx_fifo_count(2),
O => Tx_FIFO_Empty_intr
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_cross_clk_sync_fifo_1 is
port (
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC_0\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC_0\ : out STD_LOGIC;
tx_FIFO_Occpncy_MSB_d1_reg : out STD_LOGIC;
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC_0\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC_0\ : out STD_LOGIC;
SPICR_2_MST_N_SLV_to_spi_clk : out STD_LOGIC;
spicr_3_cpol_to_spi_clk : out STD_LOGIC;
spicr_4_cpha_to_spi_clk : out STD_LOGIC;
spicr_8_tr_inhibit_to_spi_clk : out STD_LOGIC;
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC_0\ : out STD_LOGIC;
register_Data_slvsel_int : out STD_LOGIC;
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_0_CMD_Error_d1_reg\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[8]\ : out STD_LOGIC;
transfer_start_reg : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg_reg[13]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
\icount_out_reg[2]\ : out STD_LOGIC;
spiXfer_done_to_axi_1 : out STD_LOGIC;
tx_occ_msb : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
\icount_out_reg[1]\ : out STD_LOGIC;
R : out STD_LOGIC;
modf_reg : out STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\ : out STD_LOGIC;
rx_fifo_reset : out STD_LOGIC;
R_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D_1 : out STD_LOGIC;
\master_tri_state_en_control1__1\ : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
SPISR_0_CMD_Error_int : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
spisel_d1_reg : in STD_LOGIC;
\out\ : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\ : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
sr_3_MODF_int : in STD_LOGIC;
spicr_bits_7_8_frm_axi_clk : in STD_LOGIC_VECTOR ( 1 downto 0 );
SPISSR_frm_axi_clk : in STD_LOGIC;
SPICR_RX_FIFO_Rst_en : in STD_LOGIC;
QSPI_SPISEL : in STD_LOGIC;
p_5_out : in STD_LOGIC;
p_2_out : in STD_LOGIC;
p_0_out : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2_0\ : in STD_LOGIC;
stop_clock : in STD_LOGIC;
SPISR_0_CMD_Error_d1 : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 5 downto 0 );
\p_39_out__0\ : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_1_in35_in : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
ram_full_i_reg : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
tx_occ_msb_4 : in STD_LOGIC;
p_7_in : in STD_LOGIC;
rx_fifo_count : in STD_LOGIC_VECTOR ( 0 to 0 );
p_2_in : in STD_LOGIC;
prmry_in : in STD_LOGIC;
scndry_out : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_flag : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_sig : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg_0\ : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_d2 : in STD_LOGIC;
modf_strobe_int : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_cross_clk_sync_fifo_1 : entity is "cross_clk_sync_fifo_1";
end system_axi_quad_spi_flash_0_cross_clk_sync_fifo_1;
architecture STRUCTURE of system_axi_quad_spi_flash_0_cross_clk_sync_fifo_1 is
signal \^logic_generation_fdr.drr_overrun_s2ax_1_cdc_0\ : STD_LOGIC;
signal \^logic_generation_fdr.modf_strobe_s2ax_1_cdc_0\ : STD_LOGIC;
signal \^logic_generation_fdr.rx_fifo_rst_ax2s_1_cdc_0\ : STD_LOGIC;
signal \^logic_generation_fdr.spisel_pulse_s2ax_1_cdc_0\ : STD_LOGIC;
signal \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC_n_0\ : STD_LOGIC;
signal \^logic_generation_fdr.sync_spixfer_done_s2ax_1_cdc_0\ : STD_LOGIC;
signal Mst_N_Slv_mode_cdc_from_spi_d1 : STD_LOGIC;
signal Mst_N_Slv_mode_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of Mst_N_Slv_mode_cdc_from_spi_d2 : signal is "true";
signal SPICR_1_SPE_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : STD_LOGIC;
signal \^spicr_2_mst_n_slv_to_spi_clk\ : STD_LOGIC;
signal SPICR_3_CPOL_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_4_CPHA_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_5_TXFIFO_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_bits_7_8_cdc_from_axi_d1_0 : STD_LOGIC;
signal SPICR_bits_7_8_cdc_from_axi_d1_1 : STD_LOGIC;
signal SPISR_0_CMD_Error_cdc_from_spi_d1 : STD_LOGIC;
signal SPISR_0_CMD_Error_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of SPISR_0_CMD_Error_cdc_from_spi_d2 : signal is "true";
signal SR_3_modf_cdc_from_axi_d1 : STD_LOGIC;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d1 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d2 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d3 : STD_LOGIC;
signal modf_strobe_cdc_from_spi_d1 : STD_LOGIC;
attribute RTL_KEEP of modf_strobe_cdc_from_spi_d1 : signal is "true";
signal modf_strobe_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of modf_strobe_cdc_from_spi_d2 : signal is "true";
signal modf_strobe_cdc_from_spi_d3 : STD_LOGIC;
signal reset_RcFIFO_ptr_cdc_from_axi_d1 : STD_LOGIC;
signal reset_RcFIFO_ptr_cdc_from_axi_d2 : STD_LOGIC;
signal slave_MODF_strobe_cdc_from_spi_d1 : STD_LOGIC;
attribute RTL_KEEP of slave_MODF_strobe_cdc_from_spi_d1 : signal is "true";
signal slave_MODF_strobe_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of slave_MODF_strobe_cdc_from_spi_d2 : signal is "true";
signal slave_MODF_strobe_cdc_from_spi_d3 : STD_LOGIC;
signal spiXfer_done_d1 : STD_LOGIC;
signal spiXfer_done_d2 : STD_LOGIC;
signal spiXfer_done_d3 : STD_LOGIC;
signal \^spixfer_done_to_axi_1\ : STD_LOGIC;
signal spicr_1_spe_to_spi_clk : STD_LOGIC;
signal \^spicr_3_cpol_to_spi_clk\ : STD_LOGIC;
signal \^spicr_4_cpha_to_spi_clk\ : STD_LOGIC;
signal spicr_5_txfifo_to_spi_clk : STD_LOGIC;
signal spicr_bits_7_8_to_spi_clk : STD_LOGIC_VECTOR ( 0 to 1 );
signal spisel_d1_reg_cdc_from_spi_d1 : STD_LOGIC;
signal spisel_d1_reg_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of spisel_d1_reg_cdc_from_spi_d2 : signal is "true";
signal spisel_pulse_cdc_from_spi_d1 : STD_LOGIC;
attribute RTL_KEEP of spisel_pulse_cdc_from_spi_d1 : signal is "true";
signal spisel_pulse_cdc_from_spi_d2 : STD_LOGIC;
attribute RTL_KEEP of spisel_pulse_cdc_from_spi_d2 : signal is "true";
signal spisel_pulse_cdc_from_spi_d3 : STD_LOGIC;
signal sr_3_modf_to_spi_clk : STD_LOGIC;
signal \^tx_fifo_occpncy_msb_d1_reg\ : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_1_CDC\ : label is "FDR";
attribute box_type : string;
attribute box_type of \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\ : label is "PRIMITIVE";
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : label is "FDR";
attribute box_type of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of QSPI_IO0_T_i_3 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of QSPI_SCK_T_i_1 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1__0\ : label is "soft_lutpair20";
begin
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_0_CMD_Error_d1_reg\ <= SPISR_0_CMD_Error_cdc_from_spi_d2;
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC_0\ <= \^logic_generation_fdr.drr_overrun_s2ax_1_cdc_0\;
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC_0\ <= \^logic_generation_fdr.modf_strobe_s2ax_1_cdc_0\;
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC_0\ <= \^logic_generation_fdr.rx_fifo_rst_ax2s_1_cdc_0\;
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC_0\ <= \^logic_generation_fdr.spisel_pulse_s2ax_1_cdc_0\;
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC_0\ <= \^logic_generation_fdr.sync_spixfer_done_s2ax_1_cdc_0\;
SPICR_2_MST_N_SLV_to_spi_clk <= \^spicr_2_mst_n_slv_to_spi_clk\;
\ip_irpt_enable_reg_reg[8]\ <= spisel_d1_reg_cdc_from_spi_d2;
spiXfer_done_to_axi_1 <= \^spixfer_done_to_axi_1\;
spicr_3_cpol_to_spi_clk <= \^spicr_3_cpol_to_spi_clk\;
spicr_4_cpha_to_spi_clk <= \^spicr_4_cpha_to_spi_clk\;
tx_FIFO_Occpncy_MSB_d1_reg <= \^tx_fifo_occpncy_msb_d1_reg\;
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF90"
)
port map (
I0 => spiXfer_done_d2,
I1 => spiXfer_done_d3,
I2 => \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg_0\,
I3 => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
I4 => bus2ip_reset_ipif_inverted,
I5 => \RESET_FLOPS[15].RST_FLOPS\,
O => \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFFFF6A"
)
port map (
I0 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
I1 => \p_39_out__0\,
I2 => s_axi_wdata(0),
I3 => modf_strobe_cdc_from_spi_d2,
I4 => modf_strobe_cdc_from_spi_d3,
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\
);
\GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4FF4F4F4"
)
port map (
I0 => SPISR_0_CMD_Error_d1,
I1 => SPISR_0_CMD_Error_cdc_from_spi_d2,
I2 => p_1_in,
I3 => s_axi_wdata(5),
I4 => \p_39_out__0\,
O => \GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg_reg[13]\
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFFFF6A"
)
port map (
I0 => p_1_in35_in,
I1 => s_axi_wdata(1),
I2 => \p_39_out__0\,
I3 => slave_MODF_strobe_cdc_from_spi_d2,
I4 => slave_MODF_strobe_cdc_from_spi_d3,
O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFFFF6A"
)
port map (
I0 => p_1_in23_in,
I1 => s_axi_wdata(2),
I2 => \p_39_out__0\,
I3 => drr_Overrun_int_cdc_from_spi_d2,
I4 => drr_Overrun_int_cdc_from_spi_d3,
O => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFFFF6A"
)
port map (
I0 => p_1_in17_in,
I1 => s_axi_wdata(3),
I2 => \p_39_out__0\,
I3 => spisel_pulse_cdc_from_spi_d2,
I4 => spisel_pulse_cdc_from_spi_d3,
O => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => spisel_d1_reg_cdc_from_spi_d2,
I1 => \CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\,
O => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008800F8008800"
)
port map (
I0 => \^tx_fifo_occpncy_msb_d1_reg\,
I1 => p_7_in,
I2 => rx_fifo_count(0),
I3 => Bus_RNW_reg,
I4 => p_2_in,
I5 => prmry_in,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\
);
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => SPISR_0_CMD_Error_int,
Q => SPISR_0_CMD_Error_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => SPISR_0_CMD_Error_cdc_from_spi_d1,
Q => SPISR_0_CMD_Error_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^logic_generation_fdr.drr_overrun_s2ax_1_cdc_0\,
Q => drr_Overrun_int_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => drr_Overrun_int_cdc_from_spi_d1,
Q => drr_Overrun_int_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => drr_Overrun_int_cdc_from_spi_d2,
Q => drr_Overrun_int_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^logic_generation_fdr.modf_strobe_s2ax_1_cdc_0\,
Q => modf_strobe_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => modf_strobe_cdc_from_spi_d1,
Q => modf_strobe_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => modf_strobe_cdc_from_spi_d2,
Q => modf_strobe_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
Q => Mst_N_Slv_mode_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Mst_N_Slv_mode_cdc_from_spi_d1,
Q => Mst_N_Slv_mode_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \^logic_generation_fdr.rx_fifo_rst_ax2s_1_cdc_0\,
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => slave_MODF_strobe_cdc_from_spi_d1,
Q => slave_MODF_strobe_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => slave_MODF_strobe_cdc_from_spi_d2,
Q => slave_MODF_strobe_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_1_spe_frm_axi_clk,
Q => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_1_SPE_cdc_from_axi_d1,
Q => spicr_1_spe_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\,
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
Q => \^spicr_2_mst_n_slv_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_3_cpol_frm_axi_clk,
Q => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_3_CPOL_cdc_from_axi_d1,
Q => \^spicr_3_cpol_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_4_cpha_frm_axi_clk,
Q => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_4_CPHA_cdc_from_axi_d1,
Q => \^spicr_4_cpha_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
Q => SPICR_5_TXFIFO_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_5_TXFIFO_cdc_from_axi_d1,
Q => spicr_5_txfifo_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_8_tr_inhibit_frm_axi_clk,
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
Q => spicr_8_tr_inhibit_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_bits_7_8_frm_axi_clk(0),
Q => SPICR_bits_7_8_cdc_from_axi_d1_0,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_bits_7_8_cdc_from_axi_d1_0,
Q => spicr_bits_7_8_to_spi_clk(1),
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_bits_7_8_frm_axi_clk(1),
Q => SPICR_bits_7_8_cdc_from_axi_d1_1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_bits_7_8_cdc_from_axi_d1_1,
Q => spicr_bits_7_8_to_spi_clk(0),
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => SPICR_RX_FIFO_Rst_en,
Q => \^logic_generation_fdr.rx_fifo_rst_ax2s_1_cdc_0\,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spisel_d1_reg,
Q => spisel_d1_reg_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spisel_d1_reg_cdc_from_spi_d1,
Q => spisel_d1_reg_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^logic_generation_fdr.spisel_pulse_s2ax_1_cdc_0\,
Q => spisel_pulse_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spisel_pulse_cdc_from_spi_d1,
Q => spisel_pulse_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spisel_pulse_cdc_from_spi_d2,
Q => spisel_pulse_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPISSR_frm_axi_clk,
Q => \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC_n_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC_n_0\,
Q => register_Data_slvsel_int,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => sr_3_MODF_int,
Q => SR_3_modf_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SR_3_modf_cdc_from_axi_d1,
Q => sr_3_modf_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^logic_generation_fdr.sync_spixfer_done_s2ax_1_cdc_0\,
Q => spiXfer_done_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spiXfer_done_d1,
Q => spiXfer_done_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => spiXfer_done_d2,
Q => spiXfer_done_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
Q => \^tx_fifo_occpncy_msb_d1_reg\,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_0_out,
Q => \^logic_generation_fdr.drr_overrun_s2ax_1_cdc_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_5_out,
Q => \^logic_generation_fdr.modf_strobe_s2ax_1_cdc_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_2_out,
Q => \^logic_generation_fdr.sync_spixfer_done_s2ax_1_cdc_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => QSPI_SPISEL,
Q => \^logic_generation_fdr.spisel_pulse_s2ax_1_cdc_0\,
R => Rst_to_spi
);
QSPI_IO0_T_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => sr_3_modf_to_spi_clk,
I1 => modf_strobe_int,
I2 => spicr_bits_7_8_to_spi_clk(1),
I3 => spicr_bits_7_8_to_spi_clk(0),
O => \master_tri_state_en_control1__1\
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => spicr_5_txfifo_to_spi_clk,
I1 => Rst_to_spi,
O => R_0
);
QSPI_SCK_T_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => spicr_bits_7_8_to_spi_clk(0),
I1 => spicr_bits_7_8_to_spi_clk(1),
I2 => modf_strobe_int,
I3 => sr_3_modf_to_spi_clk,
O => D_1
);
\RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^spicr_2_mst_n_slv_to_spi_clk\,
O => R
);
\RATIO_OF_2_GENERATE.Count[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F07"
)
port map (
I0 => \^spicr_3_cpol_to_spi_clk\,
I1 => \^spicr_4_cpha_to_spi_clk\,
I2 => Q(0),
I3 => transfer_start_d2,
O => E(0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => slave_MODF_strobe_cdc_from_spi_d1
);
\icount_out[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFAEFFFF"
)
port map (
I0 => \^spixfer_done_to_axi_1\,
I1 => scndry_out,
I2 => Rx_FIFO_Full_Fifo_d1_flag,
I3 => Rx_FIFO_Full_Fifo_d1_sig,
I4 => \IP2Bus_RdAck_receive_enable__1\,
O => \icount_out_reg[1]\
);
\icount_out[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00200020FFFF"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
I1 => ram_full_i_reg,
I2 => p_6_in,
I3 => Bus_RNW_reg,
I4 => spiXfer_done_d3,
I5 => spiXfer_done_d2,
O => \icount_out_reg[2]\
);
\icount_out[3]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => spiXfer_done_d2,
I1 => spiXfer_done_d3,
O => \^spixfer_done_to_axi_1\
);
\ip_irpt_enable_reg[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => s_axi_wdata(4),
I1 => spisel_d1_reg_cdc_from_spi_d2,
I2 => \CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\,
O => D(0)
);
modf_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000BE00BE00BE"
)
port map (
I0 => sr_3_MODF_int,
I1 => modf_strobe_cdc_from_spi_d3,
I2 => modf_strobe_cdc_from_spi_d2,
I3 => reset2ip_reset_int,
I4 => bus2ip_rdce_int(0),
I5 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
O => modf_reg
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => Rst_to_spi,
I1 => reset_RcFIFO_ptr_cdc_from_axi_d2,
I2 => reset_RcFIFO_ptr_cdc_from_axi_d1,
O => rx_fifo_reset
);
transfer_start_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => spicr_1_spe_to_spi_clk,
I1 => Rst_to_spi,
I2 => \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2_0\,
I3 => sr_3_modf_to_spi_clk,
I4 => stop_clock,
O => transfer_start_reg
);
tx_FIFO_Occpncy_MSB_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => tx_occ_msb_4,
I1 => \^tx_fifo_occpncy_msb_d1_reg\,
O => tx_occ_msb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : out STD_LOGIC;
p_1_in35_in : out STD_LOGIC;
p_1_in32_in : out STD_LOGIC;
p_1_in29_in : out STD_LOGIC;
p_1_in26_in : out STD_LOGIC;
p_1_in23_in : out STD_LOGIC;
p_1_in20_in : out STD_LOGIC;
p_1_in17_in : out STD_LOGIC;
p_1_in14_in : out STD_LOGIC;
p_1_in11_in : out STD_LOGIC;
p_1_in8_in : out STD_LOGIC;
p_1_in5_in : out STD_LOGIC;
p_1_in2_in : out STD_LOGIC;
p_1_in : out STD_LOGIC;
p_2_in_0 : out STD_LOGIC;
irpt_rdack_d1 : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
ip2intc_irpt : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
IP2Bus_RdAck_1 : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0\ : in STD_LOGIC;
rc_FIFO_Full_d1_reg : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg_reg[9]_0\ : in STD_LOGIC;
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\ : in STD_LOGIC;
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_2_MSB_Error_d1_reg\ : in STD_LOGIC;
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_1_LOOP_Back_Error_d1_reg\ : in STD_LOGIC;
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_0_CMD_Error_d1_reg\ : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
SPISR_1_LOOP_Back_Error_int : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_15_in : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\icount_out_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
\icount_out_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : in STD_LOGIC;
p_3_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : in STD_LOGIC;
data_Exists_RcFIFO_int_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 13 downto 0 );
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : in STD_LOGIC;
\p_39_out__0\ : in STD_LOGIC;
tx_FIFO_Occpncy_MSB_d1 : in STD_LOGIC;
tx_occ_msb_4 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_interrupt_control : entity is "interrupt_control";
end system_axi_quad_spi_flash_0_interrupt_control;
architecture STRUCTURE of system_axi_quad_spi_flash_0_interrupt_control is
signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_5_n_0\ : STD_LOGIC;
signal \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal ip2intc_irpt_INST_0_i_1_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_2_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_3_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_4_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_5_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_6_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_7_n_0 : STD_LOGIC;
signal \ip_irpt_enable_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \^ipif_glbl_irpt_enable_reg_reg_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_0_in28_in : STD_LOGIC;
signal p_0_in31_in : STD_LOGIC;
signal p_0_in34_in : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
signal \^p_1_in11_in\ : STD_LOGIC;
signal \^p_1_in14_in\ : STD_LOGIC;
signal \^p_1_in17_in\ : STD_LOGIC;
signal \^p_1_in20_in\ : STD_LOGIC;
signal \^p_1_in23_in\ : STD_LOGIC;
signal \^p_1_in26_in\ : STD_LOGIC;
signal \^p_1_in29_in\ : STD_LOGIC;
signal \^p_1_in2_in\ : STD_LOGIC;
signal \^p_1_in32_in\ : STD_LOGIC;
signal \^p_1_in35_in\ : STD_LOGIC;
signal \^p_1_in5_in\ : STD_LOGIC;
signal \^p_1_in8_in\ : STD_LOGIC;
begin
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\(9 downto 0) <= \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(9 downto 0);
ipif_glbl_irpt_enable_reg_reg_0 <= \^ipif_glbl_irpt_enable_reg_reg_0\;
p_1_in <= \^p_1_in\;
p_1_in11_in <= \^p_1_in11_in\;
p_1_in14_in <= \^p_1_in14_in\;
p_1_in17_in <= \^p_1_in17_in\;
p_1_in20_in <= \^p_1_in20_in\;
p_1_in23_in <= \^p_1_in23_in\;
p_1_in26_in <= \^p_1_in26_in\;
p_1_in29_in <= \^p_1_in29_in\;
p_1_in2_in <= \^p_1_in2_in\;
p_1_in32_in <= \^p_1_in32_in\;
p_1_in35_in <= \^p_1_in35_in\;
p_1_in5_in <= \^p_1_in5_in\;
p_1_in8_in <= \^p_1_in8_in\;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1\,
Q => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\,
Q => \^p_1_in8_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_2_MSB_Error_d1_reg\,
Q => \^p_1_in5_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_1_LOOP_Back_Error_d1_reg\,
Q => \^p_1_in2_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_0_CMD_Error_d1_reg\,
Q => \^p_1_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0\,
Q => \^p_1_in35_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]_0\,
Q => \^p_1_in32_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0\,
Q => \^p_1_in29_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rc_FIFO_Full_d1_reg,
Q => \^p_1_in26_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0\,
Q => \^p_1_in23_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF6A6A6AFF6AFF6A"
)
port map (
I0 => \^p_1_in20_in\,
I1 => s_axi_wdata(6),
I2 => \p_39_out__0\,
I3 => tx_FIFO_Occpncy_MSB_d1,
I4 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\,
I5 => tx_occ_msb_4,
O => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\,
Q => \^p_1_in20_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0\,
Q => \^p_1_in17_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1FF1F0F0F1F1F0F0"
)
port map (
I0 => data_Exists_RcFIFO_int_d1,
I1 => \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\,
I2 => \^p_1_in14_in\,
I3 => s_axi_wdata(8),
I4 => \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\,
I5 => \p_39_out__0\,
O => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1_n_0\,
Q => \^p_1_in14_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg_reg[9]_0\,
Q => \^p_1_in11_in\,
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^p_1_in\,
I1 => irpt_rdack144_out,
I2 => p_0_in34_in,
I3 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
O => D(3)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^p_1_in2_in\,
I1 => irpt_rdack144_out,
I2 => p_0_in31_in,
I3 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
O => D(2)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^p_1_in5_in\,
I1 => irpt_rdack144_out,
I2 => p_0_in28_in,
I3 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
O => D(1)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_2_n_0\,
I1 => SPISR_1_LOOP_Back_Error_int,
I2 => bus2ip_rdce_int(1),
I3 => p_15_in,
I4 => Q(0),
I5 => \icount_out_reg[0]\,
O => D(0)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAFFEAFFEAEAEA"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_5_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
I2 => \ip_irpt_enable_reg_reg_n_0_[0]\,
I3 => bus2ip_rdce_int(0),
I4 => \FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\,
I5 => \out\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888F8888888"
)
port map (
I0 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
I1 => irpt_rdack144_out,
I2 => \icount_out_reg[0]_0\(0),
I3 => Bus_RNW_reg,
I4 => p_3_in,
I5 => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_5_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_RdAck_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => p_0_in,
I1 => ip2Bus_RdAck_intr_reg_hole,
I2 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
O => IP2Bus_RdAck_1
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => p_0_in,
R => reset2ip_reset_int
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => p_2_in_0,
R => reset2ip_reset_int
);
ip2intc_irpt_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAAAAA"
)
port map (
I0 => ip2intc_irpt_INST_0_i_1_n_0,
I1 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(6),
I2 => \^p_1_in17_in\,
I3 => ip2intc_irpt_INST_0_i_2_n_0,
I4 => \^ipif_glbl_irpt_enable_reg_reg_0\,
I5 => ip2intc_irpt_INST_0_i_3_n_0,
O => ip2intc_irpt
);
ip2intc_irpt_INST_0_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF80"
)
port map (
I0 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
I1 => \ip_irpt_enable_reg_reg_n_0_[0]\,
I2 => \^ipif_glbl_irpt_enable_reg_reg_0\,
I3 => ip2intc_irpt_INST_0_i_4_n_0,
I4 => ip2intc_irpt_INST_0_i_5_n_0,
O => ip2intc_irpt_INST_0_i_1_n_0
);
ip2intc_irpt_INST_0_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => ip2intc_irpt_INST_0_i_6_n_0,
I1 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(3),
I2 => \^p_1_in26_in\,
I3 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(2),
I4 => \^p_1_in29_in\,
I5 => ip2intc_irpt_INST_0_i_7_n_0,
O => ip2intc_irpt_INST_0_i_2_n_0
);
ip2intc_irpt_INST_0_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => p_0_in28_in,
I1 => \^p_1_in5_in\,
I2 => \^ipif_glbl_irpt_enable_reg_reg_0\,
I3 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(9),
I4 => \^p_1_in8_in\,
O => ip2intc_irpt_INST_0_i_3_n_0
);
ip2intc_irpt_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(8),
I1 => \^p_1_in11_in\,
I2 => \^ipif_glbl_irpt_enable_reg_reg_0\,
I3 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(7),
I4 => \^p_1_in14_in\,
O => ip2intc_irpt_INST_0_i_4_n_0
);
ip2intc_irpt_INST_0_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => p_0_in34_in,
I1 => \^p_1_in\,
I2 => \^ipif_glbl_irpt_enable_reg_reg_0\,
I3 => p_0_in31_in,
I4 => \^p_1_in2_in\,
O => ip2intc_irpt_INST_0_i_5_n_0
);
ip2intc_irpt_INST_0_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(0),
I1 => \^p_1_in35_in\,
I2 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(1),
I3 => \^p_1_in32_in\,
O => ip2intc_irpt_INST_0_i_6_n_0
);
ip2intc_irpt_INST_0_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(5),
I1 => \^p_1_in20_in\,
I2 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(4),
I3 => \^p_1_in23_in\,
O => ip2intc_irpt_INST_0_i_7_n_0
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => \ip_irpt_enable_reg_reg_n_0_[0]\,
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(10),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(9),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(11),
Q => p_0_in28_in,
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(12),
Q => p_0_in31_in,
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(13),
Q => p_0_in34_in,
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(0),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(1),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(2),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(3),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(4),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(5),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(6),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2_0\(0),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(7),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(9),
Q => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\(8),
R => reset2ip_reset_int
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg,
Q => \^ipif_glbl_irpt_enable_reg_reg_0\,
R => reset2ip_reset_int
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => reset2ip_reset_int
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irpt_wrack,
Q => irpt_wrack_d1,
R => reset2ip_reset_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_qspi_cntrl_reg is
port (
spicr_bits_7_8_frm_axi_clk : out STD_LOGIC_VECTOR ( 1 downto 0 );
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_1_LOOP_Back_Error_d1_reg\ : out STD_LOGIC;
spicr_1_spe_frm_axi_clk : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : out STD_LOGIC;
spicr_3_cpol_frm_axi_clk : out STD_LOGIC;
spicr_4_cpha_frm_axi_clk : out STD_LOGIC;
spicr_7_ss_frm_axi_clk : out STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : out STD_LOGIC;
SPISR_2_MSB_Error_int : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_1_CDC\ : out STD_LOGIC;
\icount_out_reg[0]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg_reg[9]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
SPISR_4_CPOL_CPHA_Error_int : out STD_LOGIC;
SPICR_RX_FIFO_Rst_en : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
\icount_out_reg[0]_0\ : out STD_LOGIC;
\icount_out_reg[0]_1\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg_reg[12]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg_reg[11]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg_reg[10]\ : out STD_LOGIC;
SPISR_3_Slave_Mode_Error_int : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
bus2ip_wrce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aclk : in STD_LOGIC;
SPICR_data_int_reg0 : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\ : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
\p_39_out__0\ : in STD_LOGIC;
SPISR_4_CPOL_CPHA_Error_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_15_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
p_1_in20_in : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 1 downto 0 );
\ip_irpt_enable_reg_reg[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg\ : in STD_LOGIC;
\updown_cnt_en_rx__4\ : in STD_LOGIC;
rx_fifo_count : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_fifo_count : in STD_LOGIC_VECTOR ( 0 to 0 );
SPISR_1_LOOP_Back_Error_d1 : in STD_LOGIC;
p_1_in2_in : in STD_LOGIC;
SPISR_2_MSB_Error_d1 : in STD_LOGIC;
p_1_in5_in : in STD_LOGIC;
SPISR_3_Slave_Mode_Error_d1 : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_qspi_cntrl_reg : entity is "qspi_cntrl_reg";
end system_axi_quad_spi_flash_0_qspi_cntrl_reg;
architecture STRUCTURE of system_axi_quad_spi_flash_0_qspi_cntrl_reg is
signal \^fifo_exists.dual_md_intr_gen.spisr_1_loop_back_error_d1_reg\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_2_n_0\ : STD_LOGIC;
signal \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\ : STD_LOGIC;
signal \^logic_generation_fdr.spicr_5_txfifo_ax2s_1_cdc\ : STD_LOGIC;
signal \^spisr_2_msb_error_int\ : STD_LOGIC;
signal \^spisr_4_cpol_cpha_error_int\ : STD_LOGIC;
signal \^icount_out_reg[0]\ : STD_LOGIC;
signal \^spicr_3_cpol_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_4_cpha_frm_axi_clk\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_3_Slave_Mode_Error_d1_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg[10]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1\ : label is "soft_lutpair18";
attribute box_type : string;
attribute box_type of \SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I\ : label is "PRIMITIVE";
attribute box_type of \SPICR_REG_78_GENERATE[8].SPI_TRISTATE_CONTROL_I\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \icount_out[3]_i_1\ : label is "soft_lutpair18";
begin
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_1_LOOP_Back_Error_d1_reg\ <= \^fifo_exists.dual_md_intr_gen.spisr_1_loop_back_error_d1_reg\;
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ <= \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\;
\LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_1_CDC\ <= \^logic_generation_fdr.spicr_5_txfifo_ax2s_1_cdc\;
SPISR_2_MSB_Error_int <= \^spisr_2_msb_error_int\;
SPISR_4_CPOL_CPHA_Error_int <= \^spisr_4_cpol_cpha_error_int\;
\icount_out_reg[0]\ <= \^icount_out_reg[0]\;
spicr_3_cpol_frm_axi_clk <= \^spicr_3_cpol_frm_axi_clk\;
spicr_4_cpha_frm_axi_clk <= \^spicr_4_cpha_frm_axi_clk\;
\CONTROL_REG_1_2_GENERATE[1].SPICR_data_int_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(6),
Q => spicr_8_tr_inhibit_frm_axi_clk,
S => reset2ip_reset_int
);
\CONTROL_REG_1_2_GENERATE[2].SPICR_data_int_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(5),
Q => spicr_7_ss_frm_axi_clk,
S => reset2ip_reset_int
);
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\,
Q => \^icount_out_reg[0]\,
R => '0'
);
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\,
Q => \^logic_generation_fdr.spicr_5_txfifo_ax2s_1_cdc\,
R => '0'
);
\CONTROL_REG_5_9_GENERATE[5].SPICR_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(4),
Q => \^spicr_4_cpha_frm_axi_clk\,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[6].SPICR_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(3),
Q => \^spicr_3_cpol_frm_axi_clk\,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(2),
Q => \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[8].SPICR_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(1),
Q => spicr_1_spe_frm_axi_clk,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(0),
Q => \^fifo_exists.dual_md_intr_gen.spisr_1_loop_back_error_d1_reg\,
R => reset2ip_reset_int
);
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_3_Slave_Mode_Error_d1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\,
O => SPISR_3_Slave_Mode_Error_int
);
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_4_CPOL_CPHA_Error_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^spicr_4_cpha_frm_axi_clk\,
I1 => \^spicr_3_cpol_frm_axi_clk\,
O => \^spisr_4_cpol_cpha_error_int\
);
\GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"1FF1F1F1"
)
port map (
I0 => \^logic_generation_fdr.spicr_2_mst_n_slv_ax2s_1_cdc\,
I1 => SPISR_3_Slave_Mode_Error_d1,
I2 => p_1_in8_in,
I3 => s_axi_wdata(8),
I4 => \p_39_out__0\,
O => \GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg_reg[10]\
);
\GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4FF4F4F4"
)
port map (
I0 => SPISR_2_MSB_Error_d1,
I1 => \^spisr_2_msb_error_int\,
I2 => p_1_in5_in,
I3 => s_axi_wdata(9),
I4 => \p_39_out__0\,
O => \GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg_reg[11]\
);
\GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4FF4F4F4"
)
port map (
I0 => SPISR_1_LOOP_Back_Error_d1,
I1 => \^fifo_exists.dual_md_intr_gen.spisr_1_loop_back_error_d1_reg\,
I2 => p_1_in2_in,
I3 => s_axi_wdata(10),
I4 => \p_39_out__0\,
O => \GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg_reg[12]\
);
\GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A6A6AFF6AFF6A6A"
)
port map (
I0 => p_1_in11_in,
I1 => s_axi_wdata(7),
I2 => \p_39_out__0\,
I3 => SPISR_4_CPOL_CPHA_Error_d1,
I4 => \^spicr_4_cpha_frm_axi_clk\,
I5 => \^spicr_3_cpol_frm_axi_clk\,
O => \GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg_reg[9]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_2_n_0\,
I1 => Q(0),
I2 => p_15_in,
I3 => irpt_rdack144_out,
I4 => p_1_in20_in,
O => D(0)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^spisr_4_cpol_cpha_error_int\,
I1 => bus2ip_rdce_int(0),
I2 => bus2ip_rdce_int(1),
I3 => \^icount_out_reg[0]\,
I4 => \ip_irpt_enable_reg_reg[6]\(0),
I5 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[25]_i_2_n_0\
);
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FE"
)
port map (
I0 => \^icount_out_reg[0]\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
I3 => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg\,
O => SPICR_RX_FIFO_Rst_en
);
\SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce_int(0),
D => s_axi_wdata(2),
Q => spicr_bits_7_8_frm_axi_clk(1),
R => reset2ip_reset_int
);
\SPICR_REG_78_GENERATE[8].SPI_TRISTATE_CONTROL_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce_int(0),
D => s_axi_wdata(1),
Q => spicr_bits_7_8_frm_axi_clk(0),
R => reset2ip_reset_int
);
\SPICR_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => SPICR_data_int_reg0,
D => s_axi_wdata(7),
Q => \^spisr_2_msb_error_int\,
R => reset2ip_reset_int
);
\icount_out[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => \^icount_out_reg[0]\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
I3 => rx_fifo_count(0),
O => \icount_out_reg[0]_0\
);
\icount_out[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => \^logic_generation_fdr.spicr_5_txfifo_ax2s_1_cdc\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
I3 => tx_fifo_count(0),
O => \icount_out_reg[0]_1\
);
\icount_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^icount_out_reg[0]\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \RESET_FLOPS[15].RST_FLOPS\,
I3 => \updown_cnt_en_rx__4\,
O => \icount_out_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_qspi_fifo_ifmodule is
port (
tx_FIFO_Empty_d1 : out STD_LOGIC;
p_11_out : out STD_LOGIC;
p_10_out : out STD_LOGIC;
tx_FIFO_Occpncy_MSB_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_synced_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Tx_FIFO_Empty_intr : in STD_LOGIC;
Receive_ip2bus_error0 : in STD_LOGIC;
Transmit_ip2bus_error0 : in STD_LOGIC;
tx_occ_msb : in STD_LOGIC;
scndry_out : in STD_LOGIC;
prmry_in : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
\p_39_out__0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_qspi_fifo_ifmodule : entity is "qspi_fifo_ifmodule";
end system_axi_quad_spi_flash_0_qspi_fifo_ifmodule;
architecture STRUCTURE of system_axi_quad_spi_flash_0_qspi_fifo_ifmodule is
signal rc_FIFO_Full_d1 : STD_LOGIC;
begin
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"04FFFF04FF04FF04"
)
port map (
I0 => rc_FIFO_Full_d1,
I1 => scndry_out,
I2 => prmry_in,
I3 => p_1_in26_in,
I4 => s_axi_wdata(0),
I5 => \p_39_out__0\,
O => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\
);
Receive_ip2bus_error_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Receive_ip2bus_error0,
Q => p_11_out,
R => reset2ip_reset_int
);
Transmit_ip2bus_error_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Transmit_ip2bus_error0,
Q => p_10_out,
R => reset2ip_reset_int
);
rc_FIFO_Full_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Rx_FIFO_Full_Fifo_d1_synced_i,
Q => rc_FIFO_Full_d1,
R => reset2ip_reset_int
);
tx_FIFO_Empty_d1_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => Tx_FIFO_Empty_intr,
Q => tx_FIFO_Empty_d1,
S => reset2ip_reset_int
);
tx_FIFO_Occpncy_MSB_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_occ_msb,
Q => tx_FIFO_Occpncy_MSB_d1,
R => reset2ip_reset_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_qspi_mode_control_logic is
port (
ss_t : out STD_LOGIC;
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_t : out STD_LOGIC;
sck_o : out STD_LOGIC;
stop_clock : out STD_LOGIC;
transfer_start_d1 : out STD_LOGIC;
transfer_start : out STD_LOGIC;
transfer_start_d2 : out STD_LOGIC;
SPIXfer_done_int : out STD_LOGIC;
SPIXfer_done_int_pulse_d1_reg_0 : out STD_LOGIC;
SPIXfer_done_int_pulse_d2 : out STD_LOGIC;
\^spixfer_done_int\ : out STD_LOGIC;
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
spisel_d1_reg : out STD_LOGIC;
modf_strobe_int : out STD_LOGIC;
io0_o : out STD_LOGIC;
io1_o : out STD_LOGIC;
io2_o : out STD_LOGIC;
io3_o : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\mode_0__0\ : out STD_LOGIC;
\mode_1__0\ : out STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ : out STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.DTR_FIFO_Data_Exists_d1_reg\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
p_5_out : out STD_LOGIC;
p_2_out : out STD_LOGIC;
p_0_out : out STD_LOGIC;
\goreg_dm.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc1.count_d1_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
empty_fwft_fb_o_i0 : out STD_LOGIC;
empty_fwft_i0 : out STD_LOGIC;
SPIXfer_done_rd_tx_en : out STD_LOGIC;
\RATIO_OF_2_GENERATE.Count_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\qspi_cntrl_ps_reg[1]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
D_0 : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
spisel : in STD_LOGIC;
spicr_8_tr_inhibit_to_spi_clk : in STD_LOGIC;
\qspo_int_reg[9]\ : in STD_LOGIC;
R : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
register_Data_slvsel_int : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ : in STD_LOGIC;
\qspo_int_reg[10]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\master_tri_state_en_control1__1\ : in STD_LOGIC;
\qspi_cntrl_ps_reg[0]_0\ : in STD_LOGIC;
\qspo_int_reg[5]\ : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
DTR_FIFO_Data_Exists_d1 : in STD_LOGIC;
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
\goreg_dm.dout_i_reg[7]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[7]_0\ : in STD_LOGIC;
SPICR_2_MST_N_SLV_to_spi_clk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\ : in STD_LOGIC;
\qspo_int_reg[3]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\out\ : in STD_LOGIC;
empty_fwft_fb_o_i_reg : in STD_LOGIC;
empty_fwft_fb_i_reg : in STD_LOGIC;
\goreg_dm.dout_i_reg[7]_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
io1_i_sync : in STD_LOGIC;
io0_i_sync : in STD_LOGIC;
spicr_3_cpol_to_spi_clk : in STD_LOGIC;
io3_i_sync : in STD_LOGIC;
io2_i_sync : in STD_LOGIC;
\qspo_int_reg[6]\ : in STD_LOGIC;
empty_fwft_i_reg_0 : in STD_LOGIC;
\qspo_int_reg[5]_0\ : in STD_LOGIC;
ram_full_i_reg : in STD_LOGIC;
scndry_out : in STD_LOGIC;
spicr_4_cpha_to_spi_clk : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_qspi_mode_control_logic : entity is "qspi_mode_control_logic";
end system_axi_quad_spi_flash_0_qspi_mode_control_logic;
architecture STRUCTURE of system_axi_quad_spi_flash_0_qspi_mode_control_logic is
signal Allow_MODF_Strobe : STD_LOGIC;
signal Allow_MODF_Strobe_i_1_n_0 : STD_LOGIC;
signal DRR_Overrun_reg_int0 : STD_LOGIC;
signal MODF_strobe_i_1_n_0 : STD_LOGIC;
signal Mst_Trans_inhibit_d1 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal QSPI_IO0_T_i_1_n_0 : STD_LOGIC;
signal QSPI_IO1_T_i_1_n_0 : STD_LOGIC;
signal QSPI_IO1_T_i_2_n_0 : STD_LOGIC;
signal \QSPI_MODE_2_T_CONTROL.QSPI_IO3_T_i_1_n_0\ : STD_LOGIC;
signal \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_2_n_0\ : STD_LOGIC;
signal \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2_n_0\ : STD_LOGIC;
signal \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_3_n_0\ : STD_LOGIC;
signal \^ratio_of_2_generate.count_reg[4]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_4_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_3_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_2_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_3_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_6_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_i_2_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_2_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_3_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_2_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_2_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[3]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[3]_i_2_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[4]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[4]_i_2_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_2_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[6]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[7]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[0]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[1]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[2]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[3]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_3_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[1]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[2]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[3]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[4]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[5]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[6]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[7]\ : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.sck_o_int_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_2_n_0\ : STD_LOGIC;
signal SPISEL_sync : STD_LOGIC;
signal \^spixfer_done_int_1\ : STD_LOGIC;
signal SPIXfer_done_int_d1 : STD_LOGIC;
signal SPIXfer_done_int_pulse_d1 : STD_LOGIC;
signal \^spixfer_done_int_pulse_d1_reg_0\ : STD_LOGIC;
signal \^spixfer_done_int_pulse_d2\ : STD_LOGIC;
signal Serial_Dout_018_out : STD_LOGIC;
signal Serial_Dout_113_out : STD_LOGIC;
signal Shift_Reg : STD_LOGIC_VECTOR ( 4 to 7 );
signal drr_Overrun_int : STD_LOGIC;
signal \^io0_o\ : STD_LOGIC;
signal \^io1_o\ : STD_LOGIC;
signal \^io2_o\ : STD_LOGIC;
signal \^io3_o\ : STD_LOGIC;
signal \^mode_0__0\ : STD_LOGIC;
signal \^mode_1__0\ : STD_LOGIC;
signal \^modf_strobe_int\ : STD_LOGIC;
signal \p_0_out__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_2_in44_in : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal p_41_in : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal \p_6_out__2\ : STD_LOGIC;
signal \plusOp__4\ : STD_LOGIC_VECTOR ( 4 downto 1 );
signal qspi_cntrl_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \qspi_cntrl_ps[0]_i_2_n_0\ : STD_LOGIC;
signal \qspi_cntrl_ps[1]_i_2_n_0\ : STD_LOGIC;
signal \qspi_cntrl_ps[1]_i_3_n_0\ : STD_LOGIC;
signal \qspi_cntrl_ps[2]_i_2_n_0\ : STD_LOGIC;
signal \^qspi_cntrl_ps_reg[1]_0\ : STD_LOGIC;
signal receive_Data_int : STD_LOGIC;
signal rx_shft_reg_mode_0011 : STD_LOGIC_VECTOR ( 0 to 7 );
signal sck_d1 : STD_LOGIC;
signal sck_d2 : STD_LOGIC;
signal sck_d3 : STD_LOGIC;
signal sck_o_int : STD_LOGIC;
signal \^spixfer_done_int_2\ : STD_LOGIC;
signal \^stop_clock\ : STD_LOGIC;
signal stop_clock_reg : STD_LOGIC;
signal stop_clock_reg_i_2_n_0 : STD_LOGIC;
signal stop_clock_reg_i_3_n_0 : STD_LOGIC;
signal \^transfer_start\ : STD_LOGIC;
signal \^transfer_start_d1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Allow_MODF_Strobe_i_1 : label is "soft_lutpair48";
attribute SOFT_HLUTNM of DRR_Overrun_reg_int_i_1 : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of MODF_strobe_i_1 : label is "soft_lutpair48";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of MST_TRANS_INHIBIT_D1_I : label is "FD";
attribute box_type : string;
attribute box_type of MST_TRANS_INHIBIT_D1_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of QSPI_IO0_T : label is "FD";
attribute box_type of QSPI_IO0_T : label is "PRIMITIVE";
attribute SOFT_HLUTNM of QSPI_IO0_T_i_1 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of QSPI_IO0_T_i_4 : label is "soft_lutpair42";
attribute XILINX_LEGACY_PRIM of QSPI_IO1_T : label is "FD";
attribute box_type of QSPI_IO1_T : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \QSPI_LOOK_UP_MODE_2_MEMORY_1.DTR_FIFO_Data_Exists_d1_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I_i_2\ : label is "soft_lutpair39";
attribute XILINX_LEGACY_PRIM of \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ : label is "FD";
attribute box_type of \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \QSPI_MODE_2_T_CONTROL.QSPI_IO3_T\ : label is "FD";
attribute box_type of \QSPI_MODE_2_T_CONTROL.QSPI_IO3_T\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_2\ : label is "soft_lutpair43";
attribute XILINX_LEGACY_PRIM of QSPI_SCK_T : label is "FD";
attribute box_type of QSPI_SCK_T : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of QSPI_SPISEL : label is "FD";
attribute box_type of QSPI_SPISEL : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of QSPI_SS_T : label is "FD";
attribute box_type of QSPI_SS_T : label is "PRIMITIVE";
attribute IOB : string;
attribute IOB of \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST\ : label is "TRUE";
attribute box_type of \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.Count[0]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.Count[1]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.Count[2]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.Count[3]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.Count[4]_i_3\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_3\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_3\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_6\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_3\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_2\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_2\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_3\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \RATIO_OF_2_GENERATE.sck_o_int_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_2\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_3\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of SPIXfer_done_int_pulse_d1_i_1 : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[7]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \qspi_cntrl_ps[1]_i_3\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of stop_clock_reg_i_3 : label is "soft_lutpair47";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\RATIO_OF_2_GENERATE.Count_reg[4]_0\(0) <= \^ratio_of_2_generate.count_reg[4]_0\(0);
SPIXfer_done_int <= \^spixfer_done_int_1\;
SPIXfer_done_int_pulse_d1_reg_0 <= \^spixfer_done_int_pulse_d1_reg_0\;
SPIXfer_done_int_pulse_d2 <= \^spixfer_done_int_pulse_d2\;
\^spixfer_done_int\ <= \^spixfer_done_int_2\;
io0_o <= \^io0_o\;
io1_o <= \^io1_o\;
io2_o <= \^io2_o\;
io3_o <= \^io3_o\;
\mode_0__0\ <= \^mode_0__0\;
\mode_1__0\ <= \^mode_1__0\;
modf_strobe_int <= \^modf_strobe_int\;
\qspi_cntrl_ps_reg[1]_0\ <= \^qspi_cntrl_ps_reg[1]_0\;
stop_clock <= \^stop_clock\;
transfer_start <= \^transfer_start\;
transfer_start_d1 <= \^transfer_start_d1\;
Allow_MODF_Strobe_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF4"
)
port map (
I0 => SPICR_2_MST_N_SLV_to_spi_clk,
I1 => Allow_MODF_Strobe,
I2 => SPISEL_sync,
I3 => Rst_to_spi,
O => Allow_MODF_Strobe_i_1_n_0
);
Allow_MODF_Strobe_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => Allow_MODF_Strobe_i_1_n_0,
Q => Allow_MODF_Strobe,
R => '0'
);
DRR_Overrun_reg_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => drr_Overrun_int,
I1 => ram_full_i_reg,
I2 => scndry_out,
I3 => \^spixfer_done_int_2\,
O => DRR_Overrun_reg_int0
);
DRR_Overrun_reg_int_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => DRR_Overrun_reg_int0,
Q => drr_Overrun_int,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => drr_Overrun_int,
I1 => \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\,
O => p_0_out
);
\LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^modf_strobe_int\,
I1 => \LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg\,
O => p_5_out
);
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^spixfer_done_int_2\,
I1 => \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\,
O => p_2_out
);
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => SPISEL_sync,
I1 => \LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\,
O => \LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg\
);
MODF_strobe_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => Allow_MODF_Strobe,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
I2 => SPISEL_sync,
I3 => Rst_to_spi,
O => MODF_strobe_i_1_n_0
);
MODF_strobe_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => MODF_strobe_i_1_n_0,
Q => \^modf_strobe_int\,
R => '0'
);
MST_TRANS_INHIBIT_D1_I: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_8_tr_inhibit_to_spi_clk,
Q => Mst_Trans_inhibit_d1,
R => '0'
);
QSPI_IO0_T: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => QSPI_IO0_T_i_1_n_0,
Q => io0_t,
R => '0'
);
QSPI_IO0_T_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"A8ADFFFF"
)
port map (
I0 => \^q\(1),
I1 => \qspo_int_reg[5]\,
I2 => \^q\(2),
I3 => \^q\(0),
I4 => \master_tri_state_en_control1__1\,
O => QSPI_IO0_T_i_1_n_0
);
QSPI_IO0_T_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(1),
I1 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(2),
I2 => \qspo_int_reg[10]\(3),
I3 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(0),
O => \^qspi_cntrl_ps_reg[1]_0\
);
QSPI_IO1_T: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => QSPI_IO1_T_i_1_n_0,
Q => io1_t,
R => '0'
);
QSPI_IO1_T_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEAAEFFFFFFFF"
)
port map (
I0 => QSPI_IO1_T_i_2_n_0,
I1 => \^q\(2),
I2 => \qspo_int_reg[10]\(5),
I3 => \qspo_int_reg[10]\(4),
I4 => \^q\(1),
I5 => \master_tri_state_en_control1__1\,
O => QSPI_IO1_T_i_1_n_0
);
QSPI_IO1_T_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00200F2F0020FFEF"
)
port map (
I0 => \qspo_int_reg[6]\,
I1 => empty_fwft_i_reg_0,
I2 => \^q\(1),
I3 => \^qspi_cntrl_ps_reg[1]_0\,
I4 => \^q\(2),
I5 => \qspo_int_reg[5]_0\,
O => QSPI_IO1_T_i_2_n_0
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.DTR_FIFO_Data_Exists_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => empty_fwft_i_reg,
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \QSPI_LOOK_UP_MODE_2_MEMORY_1.DTR_FIFO_Data_Exists_d1_reg\
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => empty_fwft_i_reg,
I4 => DTR_FIFO_Data_Exists_d1,
O => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\
);
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int_reg[9]\,
Q => io2_t,
R => '0'
);
\QSPI_MODE_2_T_CONTROL.QSPI_IO3_T\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \QSPI_MODE_2_T_CONTROL.QSPI_IO3_T_i_1_n_0\,
Q => io3_t,
R => '0'
);
\QSPI_MODE_2_T_CONTROL.QSPI_IO3_T_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ADFDFFFF"
)
port map (
I0 => \^q\(1),
I1 => \qspi_cntrl_ps_reg[0]_0\,
I2 => \^q\(2),
I3 => \qspo_int_reg[10]\(5),
I4 => \master_tri_state_en_control1__1\,
O => \QSPI_MODE_2_T_CONTROL.QSPI_IO3_T_i_1_n_0\
);
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000D200"
)
port map (
I0 => \^spixfer_done_int_1\,
I1 => SPIXfer_done_int_d1,
I2 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(0),
I3 => \^q\(1),
I4 => \^q\(2),
I5 => \^q\(0),
O => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[0]_i_1_n_0\
);
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000006A00"
)
port map (
I0 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(1),
I1 => \^spixfer_done_int_pulse_d1_reg_0\,
I2 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(0),
I3 => \^q\(1),
I4 => \^q\(2),
I5 => \^q\(0),
O => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[1]_i_1_n_0\
);
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAA6AAA"
)
port map (
I0 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(2),
I1 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(1),
I2 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(0),
I3 => \^spixfer_done_int_1\,
I4 => SPIXfer_done_int_d1,
I5 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_2_n_0\,
O => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_1_n_0\
);
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^q\(0),
I1 => \^q\(2),
I2 => \^q\(1),
O => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_2_n_0\
);
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[0]_i_1_n_0\,
Q => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(0),
R => '0'
);
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[1]_i_1_n_0\,
Q => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(1),
R => '0'
);
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt[2]_i_1_n_0\,
Q => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(2),
R => '0'
);
QSPI_SCK_T: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => D_0,
Q => sck_t,
R => '0'
);
QSPI_SPISEL: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spisel,
Q => SPISEL_sync,
R => '0'
);
QSPI_SS_T: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => D_0,
Q => ss_t,
R => '0'
);
\RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2_n_0\,
Q => sck_o,
R => R
);
\RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFF8000"
)
port map (
I0 => sck_o_int,
I1 => \^transfer_start_d1\,
I2 => \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_3_n_0\,
I3 => \^transfer_start\,
I4 => spicr_3_cpol_to_spi_clk,
O => \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_2_n_0\
);
\RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST_i_3_n_0\
);
\RATIO_OF_2_GENERATE.Count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
O => p_2_in
);
\RATIO_OF_2_GENERATE.Count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
I1 => p_41_in,
O => \plusOp__4\(1)
);
\RATIO_OF_2_GENERATE.Count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
I1 => p_41_in,
I2 => p_1_in,
O => \plusOp__4\(2)
);
\RATIO_OF_2_GENERATE.Count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_41_in,
I1 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
I2 => p_1_in,
I3 => p_2_in44_in,
O => \plusOp__4\(3)
);
\RATIO_OF_2_GENERATE.Count[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \^transfer_start\,
I1 => Rst_to_spi,
I2 => \^spixfer_done_int_1\,
O => p_3_out
);
\RATIO_OF_2_GENERATE.Count[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_1_in,
I1 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
I2 => p_41_in,
I3 => p_2_in44_in,
I4 => \^ratio_of_2_generate.count_reg[4]_0\(0),
O => \plusOp__4\(4)
);
\RATIO_OF_2_GENERATE.Count_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\(0),
D => p_2_in,
Q => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
R => p_3_out
);
\RATIO_OF_2_GENERATE.Count_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\(0),
D => \plusOp__4\(1),
Q => p_41_in,
R => p_3_out
);
\RATIO_OF_2_GENERATE.Count_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\(0),
D => \plusOp__4\(2),
Q => p_1_in,
R => p_3_out
);
\RATIO_OF_2_GENERATE.Count_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\(0),
D => \plusOp__4\(3),
Q => p_2_in44_in,
R => p_3_out
);
\RATIO_OF_2_GENERATE.Count_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\(0),
D => \plusOp__4\(4),
Q => \^ratio_of_2_generate.count_reg[4]_0\(0),
R => p_3_out
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]\,
I1 => \p_0_out__0\,
I2 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_4_n_0\,
I3 => Serial_Dout_018_out,
I4 => \^io0_o\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => \^transfer_start_d1\,
I1 => \^transfer_start\,
I2 => SPIXfer_done_int_d1,
O => \p_0_out__0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEF20E02"
)
port map (
I0 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[0]\,
I1 => \^mode_0__0\,
I2 => \^mode_1__0\,
I3 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[1]\,
I4 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[3]\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_4_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"7077777700000000"
)
port map (
I0 => \^mode_1__0\,
I1 => \^mode_0__0\,
I2 => SPIXfer_done_int_d1,
I3 => \^transfer_start_d1\,
I4 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
I5 => \^transfer_start\,
O => Serial_Dout_018_out
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_1_n_0\,
Q => \^io0_o\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_0\,
I1 => \p_0_out__0\,
I2 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_3_n_0\,
I3 => Serial_Dout_113_out,
I4 => \^io1_o\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[0]\,
I1 => \^mode_0__0\,
I2 => \^mode_1__0\,
I3 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[2]\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_3_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00BFBF0000000000"
)
port map (
I0 => SPIXfer_done_int_d1,
I1 => \^transfer_start_d1\,
I2 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
I3 => \^mode_1__0\,
I4 => \^mode_0__0\,
I5 => \^transfer_start\,
O => Serial_Dout_113_out
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_1_n_0\,
Q => \^io1_o\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFFFFF00800000"
)
port map (
I0 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_2_n_0\,
I1 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_3_n_0\,
I2 => \^mode_1__0\,
I3 => \^mode_0__0\,
I4 => \^transfer_start\,
I5 => \^io2_o\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAEFAA20"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(6),
I1 => \^transfer_start_d1\,
I2 => \^transfer_start\,
I3 => SPIXfer_done_int_d1,
I4 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[1]\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_2_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"AEFF"
)
port map (
I0 => SPIXfer_done_int_d1,
I1 => \^transfer_start\,
I2 => \^transfer_start_d1\,
I3 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_3_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E4E4A0A0E4E0A0E0"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \qspo_int_reg[10]\(5),
I3 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_6_n_0\,
I4 => \qspo_int_reg[10]\(2),
I5 => \^q\(0),
O => \^mode_1__0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"E4E4A0A0E4E0A0E0"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \qspo_int_reg[10]\(4),
I3 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_6_n_0\,
I4 => \qspo_int_reg[10]\(1),
I5 => \^q\(0),
O => \^mode_0__0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \qspo_int_reg[10]\(6),
I1 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(1),
I2 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(2),
I3 => \qspo_int_reg[10]\(3),
I4 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(0),
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_6_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_1_n_0\,
Q => \^io2_o\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBF3FFFF08000000"
)
port map (
I0 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_i_2_n_0\,
I1 => \^transfer_start\,
I2 => \^mode_0__0\,
I3 => \^mode_1__0\,
I4 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_2_i_3_n_0\,
I5 => \^io3_o\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAEFAA20"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(7),
I1 => \^transfer_start_d1\,
I2 => \^transfer_start\,
I3 => SPIXfer_done_int_d1,
I4 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[0]\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_i_2_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_3_i_1_n_0\,
Q => \^io3_o\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88888880"
)
port map (
I0 => \^transfer_start\,
I1 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_3_n_0\,
I3 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
I4 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I5 => \p_0_out__0\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACACC"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(7),
I1 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_3_n_0\,
I2 => \^transfer_start_d1\,
I3 => \^transfer_start\,
I4 => SPIXfer_done_int_d1,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_2_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEF20E02"
)
port map (
I0 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[1]\,
I1 => \^mode_0__0\,
I2 => \^mode_1__0\,
I3 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[2]\,
I4 => Shift_Reg(4),
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_3_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACACC"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(6),
I1 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_2_n_0\,
I2 => \^transfer_start_d1\,
I3 => \^transfer_start\,
I4 => SPIXfer_done_int_d1,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEF20E02"
)
port map (
I0 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[2]\,
I1 => \^mode_0__0\,
I2 => \^mode_1__0\,
I3 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[3]\,
I4 => Shift_Reg(5),
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_2_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACACC"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(5),
I1 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_2_n_0\,
I2 => \^transfer_start_d1\,
I3 => \^transfer_start\,
I4 => SPIXfer_done_int_d1,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEF20E02"
)
port map (
I0 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[3]\,
I1 => \^mode_0__0\,
I2 => \^mode_1__0\,
I3 => Shift_Reg(4),
I4 => Shift_Reg(6),
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_2_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACACC"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(4),
I1 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[3]_i_2_n_0\,
I2 => \^transfer_start_d1\,
I3 => \^transfer_start\,
I4 => SPIXfer_done_int_d1,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[3]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEF20E02"
)
port map (
I0 => Shift_Reg(4),
I1 => \^mode_0__0\,
I2 => \^mode_1__0\,
I3 => Shift_Reg(5),
I4 => Shift_Reg(7),
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[3]_i_2_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACACC"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(3),
I1 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[4]_i_2_n_0\,
I2 => \^transfer_start_d1\,
I3 => \^transfer_start\,
I4 => SPIXfer_done_int_d1,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[4]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEF20E02"
)
port map (
I0 => Shift_Reg(5),
I1 => \^mode_0__0\,
I2 => \^mode_1__0\,
I3 => Shift_Reg(6),
I4 => io3_i_sync,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[4]_i_2_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACACC"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(2),
I1 => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_2_n_0\,
I2 => \^transfer_start_d1\,
I3 => \^transfer_start\,
I4 => SPIXfer_done_int_d1,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEF20E02"
)
port map (
I0 => Shift_Reg(6),
I1 => \^mode_0__0\,
I2 => \^mode_1__0\,
I3 => Shift_Reg(7),
I4 => io2_i_sync,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_2_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACFC0"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(1),
I1 => Shift_Reg(7),
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
I3 => io1_i_sync,
I4 => \p_0_out__0\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[6]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACFC0"
)
port map (
I0 => \goreg_dm.dout_i_reg[7]_1\(0),
I1 => io1_i_sync,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
I3 => io0_i_sync,
I4 => \p_0_out__0\,
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[7]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\,
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_2_n_0\,
Q => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[0]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\,
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[1]_i_1_n_0\,
Q => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[1]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\,
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[2]_i_1_n_0\,
Q => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[2]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\,
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[3]_i_1_n_0\,
Q => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg_n_0_[3]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\,
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[4]_i_1_n_0\,
Q => Shift_Reg(4),
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\,
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[5]_i_1_n_0\,
Q => Shift_Reg(5),
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\,
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[6]_i_1_n_0\,
Q => Shift_Reg(6),
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[0]_i_1_n_0\,
D => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Shift_Reg[7]_i_1_n_0\,
Q => Shift_Reg(7),
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000FE"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_3_n_0\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I3 => \qspo_int_reg[10]\(6),
I4 => sck_d3,
O => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACFC0"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[2]\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[3]\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I3 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[5]\,
I4 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
O => rx_shft_reg_mode_0011(1)
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mode_1__0\,
I1 => \^mode_0__0\,
O => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_3_n_0\
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^mode_0__0\,
I1 => \^mode_1__0\,
O => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mode_0__0\,
I1 => \^mode_1__0\,
O => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACFC0"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[3]\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[4]\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I3 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[6]\,
I4 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
O => rx_shft_reg_mode_0011(2)
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACFC0"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[4]\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[5]\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I3 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[7]\,
I4 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
O => rx_shft_reg_mode_0011(3)
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACFC0"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[5]\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[6]\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I3 => io3_i_sync,
I4 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
O => rx_shft_reg_mode_0011(4)
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACFC0"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[6]\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[7]\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I3 => io2_i_sync,
I4 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
O => rx_shft_reg_mode_0011(5)
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[7]\,
I1 => io1_i_sync,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
O => rx_shft_reg_mode_0011(6)
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => io1_i_sync,
I1 => io0_i_sync,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
O => rx_shft_reg_mode_0011(7)
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\,
D => rx_shft_reg_mode_0011(1),
Q => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[1]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\,
D => rx_shft_reg_mode_0011(2),
Q => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[2]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\,
D => rx_shft_reg_mode_0011(3),
Q => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[3]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\,
D => rx_shft_reg_mode_0011(4),
Q => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[4]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\,
D => rx_shft_reg_mode_0011(5),
Q => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[5]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\,
D => rx_shft_reg_mode_0011(6),
Q => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[6]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_1_n_0\,
D => rx_shft_reg_mode_0011(7),
Q => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[7]\,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.sck_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => sck_o_int,
Q => sck_d1,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.sck_d2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => sck_d1,
Q => sck_d2,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.sck_d3_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => sck_d2,
Q => sck_d3,
R => Rst_to_spi
);
\RATIO_OF_2_GENERATE.sck_o_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000006F6F606"
)
port map (
I0 => sck_o_int,
I1 => \^transfer_start\,
I2 => \p_6_out__2\,
I3 => spicr_4_cpha_to_spi_clk,
I4 => spicr_3_cpol_to_spi_clk,
I5 => Rst_to_spi,
O => \RATIO_OF_2_GENERATE.sck_o_int_i_1_n_0\
);
\RATIO_OF_2_GENERATE.sck_o_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^spixfer_done_int_1\,
I1 => Mst_Trans_inhibit_d1,
I2 => spicr_8_tr_inhibit_to_spi_clk,
O => \p_6_out__2\
);
\RATIO_OF_2_GENERATE.sck_o_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \RATIO_OF_2_GENERATE.sck_o_int_i_1_n_0\,
Q => sck_o_int,
R => '0'
);
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEAA0000"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_3_n_0\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I2 => p_2_in44_in,
I3 => p_1_in,
I4 => \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_2_n_0\,
I5 => p_4_out,
O => \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_1_n_0\
);
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_41_in,
I1 => \RATIO_OF_2_GENERATE.Count_reg_n_0_[0]\,
O => \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_2_n_0\
);
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => Rst_to_spi,
I1 => \^transfer_start_d1\,
I2 => \^transfer_start\,
O => p_4_out
);
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_i_1_n_0\,
Q => \^spixfer_done_int_1\,
R => '0'
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => \^spixfer_done_int_pulse_d2\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_3_n_0\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
I3 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
O => receive_Data_int
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAACFC0"
)
port map (
I0 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[1]\,
I1 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[2]\,
I2 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_5_n_0\,
I3 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011_reg_n_0_[4]\,
I4 => \RATIO_OF_2_GENERATE.rx_shft_reg_mode_0011[1]_i_4_n_0\,
O => rx_shft_reg_mode_0011(0)
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => receive_Data_int,
D => rx_shft_reg_mode_0011(0),
Q => \gpr1.dout_i_reg[7]\(7),
R => Rst_to_spi
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => receive_Data_int,
D => rx_shft_reg_mode_0011(1),
Q => \gpr1.dout_i_reg[7]\(6),
R => Rst_to_spi
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => receive_Data_int,
D => rx_shft_reg_mode_0011(2),
Q => \gpr1.dout_i_reg[7]\(5),
R => Rst_to_spi
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => receive_Data_int,
D => rx_shft_reg_mode_0011(3),
Q => \gpr1.dout_i_reg[7]\(4),
R => Rst_to_spi
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => receive_Data_int,
D => rx_shft_reg_mode_0011(4),
Q => \gpr1.dout_i_reg[7]\(3),
R => Rst_to_spi
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => receive_Data_int,
D => rx_shft_reg_mode_0011(5),
Q => \gpr1.dout_i_reg[7]\(2),
R => Rst_to_spi
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => receive_Data_int,
D => rx_shft_reg_mode_0011(6),
Q => \gpr1.dout_i_reg[7]\(1),
R => Rst_to_spi
);
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => receive_Data_int,
D => rx_shft_reg_mode_0011(7),
Q => \gpr1.dout_i_reg[7]\(0),
R => Rst_to_spi
);
SPIXfer_done_int_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^spixfer_done_int_1\,
Q => SPIXfer_done_int_d1,
R => Rst_to_spi
);
SPIXfer_done_int_pulse_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^spixfer_done_int_1\,
I1 => SPIXfer_done_int_d1,
O => \^spixfer_done_int_pulse_d1_reg_0\
);
SPIXfer_done_int_pulse_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^spixfer_done_int_pulse_d1_reg_0\,
Q => SPIXfer_done_int_pulse_d1,
R => Rst_to_spi
);
SPIXfer_done_int_pulse_d2_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => SPIXfer_done_int_pulse_d1,
Q => \^spixfer_done_int_pulse_d2\,
R => Rst_to_spi
);
SPIXfer_done_int_pulse_d3_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^spixfer_done_int_pulse_d2\,
Q => \^spixfer_done_int_2\,
R => Rst_to_spi
);
\SS_O_reg[0]\: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => register_Data_slvsel_int,
Q => ss_o(0),
S => Rst_to_spi
);
aempty_fwft_fb_i_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => \^transfer_start_d1\,
I1 => \^transfer_start\,
I2 => \^spixfer_done_int_pulse_d2\,
O => SPIXfer_done_rd_tx_en
);
\empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00FF00AE0000"
)
port map (
I0 => \^spixfer_done_int_pulse_d2\,
I1 => \^transfer_start\,
I2 => \^transfer_start_d1\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I4 => \gpregsm1.curr_fwft_state_reg[1]\(0),
I5 => empty_fwft_fb_i_reg,
O => empty_fwft_i0
);
\empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00FF00AE0000"
)
port map (
I0 => \^spixfer_done_int_pulse_d2\,
I1 => \^transfer_start\,
I2 => \^transfer_start_d1\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I4 => \gpregsm1.curr_fwft_state_reg[1]\(0),
I5 => empty_fwft_fb_o_i_reg,
O => empty_fwft_fb_o_i0
);
\gc1.count_d1[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AEFFFFFF"
)
port map (
I0 => \^spixfer_done_int_pulse_d2\,
I1 => \^transfer_start\,
I2 => \^transfer_start_d1\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\(0),
I4 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I5 => \out\,
O => \gc1.count_d1_reg[3]\(0)
);
\gic0.gc1.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^spixfer_done_int_2\,
I1 => ram_full_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA2A22"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I1 => \gpregsm1.curr_fwft_state_reg[1]\(0),
I2 => \^transfer_start_d1\,
I3 => \^transfer_start\,
I4 => \^spixfer_done_int_pulse_d2\,
O => \goreg_dm.dout_i_reg[0]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAEFAAAA"
)
port map (
I0 => \gpregsm1.curr_fwft_state_reg[1]\(1),
I1 => \^transfer_start_d1\,
I2 => \^transfer_start\,
I3 => \^spixfer_done_int_pulse_d2\,
I4 => \gpregsm1.curr_fwft_state_reg[1]\(0),
O => D(0)
);
\qspi_cntrl_ps[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => empty_fwft_i_reg,
I1 => register_Data_slvsel_int,
I2 => \^q\(2),
I3 => \qspi_cntrl_ps[0]_i_2_n_0\,
I4 => \^q\(1),
I5 => \qspo_int_reg[3]\,
O => qspi_cntrl_ns(0)
);
\qspi_cntrl_ps[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00B0"
)
port map (
I0 => \^q\(0),
I1 => \qspo_int_reg[10]\(3),
I2 => empty_fwft_i_reg,
I3 => register_Data_slvsel_int,
O => \qspi_cntrl_ps[0]_i_2_n_0\
);
\qspi_cntrl_ps[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F700F0F7F700000"
)
port map (
I0 => empty_fwft_i_reg,
I1 => register_Data_slvsel_int,
I2 => \^q\(2),
I3 => \qspi_cntrl_ps[1]_i_2_n_0\,
I4 => \^q\(1),
I5 => \qspi_cntrl_ps[1]_i_3_n_0\,
O => qspi_cntrl_ns(1)
);
\qspi_cntrl_ps[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7277FAFF3333FAFF"
)
port map (
I0 => \^q\(0),
I1 => register_Data_slvsel_int,
I2 => \^qspi_cntrl_ps_reg[1]_0\,
I3 => \qspo_int_reg[10]\(6),
I4 => empty_fwft_i_reg,
I5 => \qspo_int_reg[10]\(3),
O => \qspi_cntrl_ps[1]_i_2_n_0\
);
\qspi_cntrl_ps[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^q\(0),
I1 => \^spixfer_done_int_1\,
I2 => SPIXfer_done_int_d1,
I3 => \qspo_int_reg[10]\(0),
O => \qspi_cntrl_ps[1]_i_3_n_0\
);
\qspi_cntrl_ps[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7070707070707F70"
)
port map (
I0 => register_Data_slvsel_int,
I1 => empty_fwft_i_reg,
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => \qspi_cntrl_ps[2]_i_2_n_0\,
O => qspi_cntrl_ns(2)
);
\qspi_cntrl_ps[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(0),
I1 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(2),
I2 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg__0\(1),
I3 => \qspo_int_reg[10]\(3),
O => \qspi_cntrl_ps[2]_i_2_n_0\
);
\qspi_cntrl_ps_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => qspi_cntrl_ns(0),
Q => \^q\(0),
R => Rst_to_spi
);
\qspi_cntrl_ps_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => qspi_cntrl_ns(1),
Q => \^q\(1),
R => Rst_to_spi
);
\qspi_cntrl_ps_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => qspi_cntrl_ns(2),
Q => \^q\(2),
R => Rst_to_spi
);
\spisel_d1_reg__0\: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => SPISEL_sync,
Q => spisel_d1_reg,
S => Rst_to_spi
);
stop_clock_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"ABABA8ABA8ABA8AB"
)
port map (
I0 => stop_clock_reg_i_2_n_0,
I1 => \^q\(1),
I2 => \^q\(2),
I3 => \^q\(0),
I4 => stop_clock_reg_i_3_n_0,
I5 => empty_fwft_i_reg,
O => \^stop_clock\
);
stop_clock_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"88888A8800000000"
)
port map (
I0 => \^q\(0),
I1 => stop_clock_reg,
I2 => register_Data_slvsel_int,
I3 => \^spixfer_done_int_1\,
I4 => SPIXfer_done_int_d1,
I5 => empty_fwft_i_reg,
O => stop_clock_reg_i_2_n_0
);
stop_clock_reg_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \qspo_int_reg[10]\(0),
I1 => SPIXfer_done_int_d1,
I2 => \^spixfer_done_int_1\,
O => stop_clock_reg_i_3_n_0
);
stop_clock_reg_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^stop_clock\,
Q => stop_clock_reg,
R => Rst_to_spi
);
transfer_start_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^transfer_start\,
Q => \^transfer_start_d1\,
R => Rst_to_spi
);
transfer_start_d2_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^transfer_start_d1\,
Q => transfer_start_d2,
R => Rst_to_spi
);
transfer_start_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\,
Q => \^transfer_start\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_qspi_status_slave_sel_reg is
port (
sr_3_MODF_int : out STD_LOGIC;
SPISSR_frm_axi_clk : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
modf_reg_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_15_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
p_1_in26_in : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 1 downto 0 );
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
\ip_irpt_enable_reg_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_qspi_status_slave_sel_reg : entity is "qspi_status_slave_sel_reg";
end system_axi_quad_spi_flash_0_qspi_status_slave_sel_reg;
architecture STRUCTURE of system_axi_quad_spi_flash_0_qspi_status_slave_sel_reg is
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_2_n_0\ : STD_LOGIC;
signal \^sr_3_modf_int\ : STD_LOGIC;
begin
sr_3_MODF_int <= \^sr_3_modf_int\;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_2_n_0\,
I1 => Q(0),
I2 => p_15_in,
I3 => irpt_rdack144_out,
I4 => p_1_in26_in,
O => D(0)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^sr_3_modf_int\,
I1 => bus2ip_rdce_int(0),
I2 => bus2ip_rdce_int(1),
I3 => spicr_4_cpha_frm_axi_clk,
I4 => \ip_irpt_enable_reg_reg[4]\(0),
I5 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[27]_i_2_n_0\
);
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg,
Q => SPISSR_frm_axi_clk,
S => reset2ip_reset_int
);
modf_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => modf_reg_0,
Q => \^sr_3_modf_int\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_reset_sync_module is
port (
Rst_to_spi : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_reset_sync_module : entity is "reset_sync_module";
end system_axi_quad_spi_flash_0_reset_sync_module;
architecture STRUCTURE of system_axi_quad_spi_flash_0_reset_sync_module is
signal Soft_Reset_frm_axi_d1 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of RESET_SYNC_AX2S_1 : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of RESET_SYNC_AX2S_1 : label is "FDR";
attribute box_type : string;
attribute box_type of RESET_SYNC_AX2S_1 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of RESET_SYNC_AX2S_2 : label is "FDR";
attribute box_type of RESET_SYNC_AX2S_2 : label is "PRIMITIVE";
begin
RESET_SYNC_AX2S_1: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => reset2ip_reset_int,
Q => Soft_Reset_frm_axi_d1,
R => '0'
);
RESET_SYNC_AX2S_2: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => Soft_Reset_frm_axi_d1,
Q => Rst_to_spi,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_soft_reset is
port (
sw_rst_cond_d1 : out STD_LOGIC;
FF_WRACK_0 : out STD_LOGIC;
\icount_out_reg[3]\ : out STD_LOGIC;
reset_TxFIFO_ptr_int : out STD_LOGIC;
IP2Bus_WrAck_1 : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\ : out STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
sw_rst_cond : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_trig0 : in STD_LOGIC;
spiXfer_done_to_axi_1 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_6_in : in STD_LOGIC;
ram_full_i_reg : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\ : in STD_LOGIC;
\data_is_non_reset_match__4\ : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
p_2_in_0 : in STD_LOGIC;
ip2Bus_WrAck_core_reg : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_flag : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_sig : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
scndry_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_soft_reset : entity is "soft_reset";
end system_axi_quad_spi_flash_0_soft_reset;
architecture STRUCTURE of system_axi_quad_spi_flash_0_soft_reset is
signal \^ff_wrack_0\ : STD_LOGIC;
signal FF_WRACK_i_1_n_0 : STD_LOGIC;
signal \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal S : STD_LOGIC;
signal flop_q_chain : STD_LOGIC_VECTOR ( 1 to 15 );
signal \^reset_txfifo_ptr_int\ : STD_LOGIC;
signal wrack : STD_LOGIC;
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of FF_WRACK : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of FF_WRACK : label is "1'b0";
attribute box_type : string;
attribute box_type of FF_WRACK : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of FF_WRACK_i_1 : label is "soft_lutpair52";
attribute IS_CE_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[0].RST_FLOPS\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \RESET_FLOPS[10].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[10].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[10].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[10].RST_FLOPS_i_1\ : label is "soft_lutpair57";
attribute IS_CE_INVERTED of \RESET_FLOPS[11].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[11].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[11].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[11].RST_FLOPS_i_1\ : label is "soft_lutpair58";
attribute IS_CE_INVERTED of \RESET_FLOPS[12].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[12].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[12].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[12].RST_FLOPS_i_1\ : label is "soft_lutpair58";
attribute IS_CE_INVERTED of \RESET_FLOPS[13].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[13].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[13].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[13].RST_FLOPS_i_1\ : label is "soft_lutpair59";
attribute IS_CE_INVERTED of \RESET_FLOPS[14].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[14].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[14].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[14].RST_FLOPS_i_1\ : label is "soft_lutpair59";
attribute IS_CE_INVERTED of \RESET_FLOPS[15].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[15].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[15].RST_FLOPS\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[1].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[1].RST_FLOPS_i_1\ : label is "soft_lutpair53";
attribute IS_CE_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[2].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[2].RST_FLOPS_i_1\ : label is "soft_lutpair53";
attribute IS_CE_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[3].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[3].RST_FLOPS_i_1\ : label is "soft_lutpair54";
attribute IS_CE_INVERTED of \RESET_FLOPS[4].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[4].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[4].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[4].RST_FLOPS_i_1\ : label is "soft_lutpair54";
attribute IS_CE_INVERTED of \RESET_FLOPS[5].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[5].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[5].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[5].RST_FLOPS_i_1\ : label is "soft_lutpair55";
attribute IS_CE_INVERTED of \RESET_FLOPS[6].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[6].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[6].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[6].RST_FLOPS_i_1\ : label is "soft_lutpair55";
attribute IS_CE_INVERTED of \RESET_FLOPS[7].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[7].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[7].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[7].RST_FLOPS_i_1\ : label is "soft_lutpair56";
attribute IS_CE_INVERTED of \RESET_FLOPS[8].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[8].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[8].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[8].RST_FLOPS_i_1\ : label is "soft_lutpair56";
attribute IS_CE_INVERTED of \RESET_FLOPS[9].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[9].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[9].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[9].RST_FLOPS_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\ : label is "soft_lutpair52";
begin
FF_WRACK_0 <= \^ff_wrack_0\;
reset_TxFIFO_ptr_int <= \^reset_txfifo_ptr_int\;
FF_WRACK: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => FF_WRACK_i_1_n_0,
Q => wrack,
R => bus2ip_reset_ipif_inverted
);
FF_WRACK_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^ff_wrack_0\,
I1 => flop_q_chain(15),
O => FF_WRACK_i_1_n_0
);
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D000C000C"
)
port map (
I0 => Rx_FIFO_Full_Fifo_d1_flag,
I1 => Rx_FIFO_Full_Fifo_d1_sig,
I2 => bus2ip_reset_ipif_inverted,
I3 => \^ff_wrack_0\,
I4 => \IP2Bus_RdAck_receive_enable__1\,
I5 => scndry_out,
O => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\,
I1 => \data_is_non_reset_match__4\,
I2 => ip2Bus_WrAck_intr_reg_hole,
I3 => wrack,
I4 => p_2_in_0,
I5 => ip2Bus_WrAck_core_reg,
O => IP2Bus_WrAck_1
);
\RESET_FLOPS[0].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => S,
Q => flop_q_chain(1),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[10].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(11),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[10].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(10),
O => \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[11].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(12),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[11].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(11),
O => \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[12].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(13),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[12].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(12),
O => \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[13].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(14),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[13].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(13),
O => \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[14].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(15),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[14].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(14),
O => \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[15].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\,
Q => \^ff_wrack_0\,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[15].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(15),
O => \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[1].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(2),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[1].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(1),
O => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[2].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(3),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[2].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(2),
O => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[3].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(4),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[3].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(3),
O => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[4].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(5),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[4].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(4),
O => \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[5].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(6),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[5].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(5),
O => \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[6].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(7),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[6].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(6),
O => \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[7].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(8),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[7].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(7),
O => \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[8].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(9),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[8].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(8),
O => \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[9].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain(10),
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[9].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain(9),
O => \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\
);
\icount_out[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEBEEEEEEEEEE"
)
port map (
I0 => \^reset_txfifo_ptr_int\,
I1 => spiXfer_done_to_axi_1,
I2 => Bus_RNW_reg,
I3 => p_6_in,
I4 => ram_full_i_reg,
I5 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
O => \icount_out_reg[3]\
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \^ff_wrack_0\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
O => \^reset_txfifo_ptr_int\
);
reset_trig_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => reset_trig0,
Q => S,
R => bus2ip_reset_ipif_inverted
);
sw_rst_cond_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => sw_rst_cond,
Q => sw_rst_cond_d1,
R => bus2ip_reset_ipif_inverted
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
I93 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
L : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_dmem : entity is "dmem";
end system_axi_quad_spi_flash_0_dmem;
architecture STRUCTURE of system_axi_quad_spi_flash_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_7_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_7_n_1 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_7 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => L(3 downto 0),
DIA(1 downto 0) => s_axi_wdata(1 downto 0),
DIB(1 downto 0) => s_axi_wdata(3 downto 2),
DIC(1 downto 0) => s_axi_wdata(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_axi_aclk,
WE => I93
);
RAM_reg_0_15_6_7: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => L(3 downto 0),
DIA(1 downto 0) => s_axi_wdata(7 downto 6),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_7_n_0,
DOA(0) => RAM_reg_0_15_6_7_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOD_UNCONNECTED(1 downto 0),
WCLK => s_axi_aclk,
WE => I93
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_6_7_n_1,
Q => Q(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => RAM_reg_0_15_6_7_n_0,
Q => Q(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_dmem_19 is
port (
\goreg_dm.dout_i_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
L : in STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_dmem_19 : entity is "dmem";
end system_axi_quad_spi_flash_0_dmem_19;
architecture STRUCTURE of system_axi_quad_spi_flash_0_dmem_19 is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_7_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_7_n_1 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_7_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_7 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => Q(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => Q(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => Q(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => L(3 downto 0),
DIA(1 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(1 downto 0),
DIB(1 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(3 downto 2),
DIC(1 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => ext_spi_clk,
WE => E(0)
);
RAM_reg_0_15_6_7: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => Q(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => Q(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => Q(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => L(3 downto 0),
DIA(1 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 6),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_7_n_0,
DOA(0) => RAM_reg_0_15_6_7_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_7_DOD_UNCONNECTED(1 downto 0),
WCLK => ext_spi_clk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_1,
Q => \goreg_dm.dout_i_reg[7]\(0)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_0,
Q => \goreg_dm.dout_i_reg[7]\(1)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_3,
Q => \goreg_dm.dout_i_reg[7]\(2)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_2,
Q => \goreg_dm.dout_i_reg[7]\(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_5,
Q => \goreg_dm.dout_i_reg[7]\(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_4,
Q => \goreg_dm.dout_i_reg[7]\(5)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_6_7_n_1,
Q => \goreg_dm.dout_i_reg[7]\(6)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_6_7_n_0,
Q => \goreg_dm.dout_i_reg[7]\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rd_bin_cntr is
port (
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc1.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
SPIXfer_done_int_pulse_d2_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rd_bin_cntr : entity is "rd_bin_cntr";
end system_axi_quad_spi_flash_0_rd_bin_cntr;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rd_bin_cntr is
signal \^gc1.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc1.count[2]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gc1.count[3]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__0\ : label is "soft_lutpair30";
begin
\gc1.count_d2_reg[3]_0\(3 downto 0) <= \^gc1.count_d2_reg[3]_0\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc1.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus2(0),
O => \plusOp__3\(0)
);
\gc1.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus2(0),
I1 => rd_pntr_plus2(1),
O => \plusOp__3\(1)
);
\gc1.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus2(0),
I1 => rd_pntr_plus2(1),
I2 => rd_pntr_plus2(2),
O => \plusOp__3\(2)
);
\gc1.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus2(1),
I1 => rd_pntr_plus2(0),
I2 => rd_pntr_plus2(2),
I3 => rd_pntr_plus2(3),
O => \plusOp__3\(3)
);
\gc1.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
D => rd_pntr_plus2(0),
PRE => AR(0),
Q => \^gc1.count_d2_reg[3]_0\(0)
);
\gc1.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => rd_pntr_plus2(1),
Q => \^gc1.count_d2_reg[3]_0\(1)
);
\gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => rd_pntr_plus2(2),
Q => \^gc1.count_d2_reg[3]_0\(2)
);
\gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => rd_pntr_plus2(3),
Q => \^gc1.count_d2_reg[3]_0\(3)
);
\gc1.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[3]_0\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[3]_0\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[3]_0\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[3]_0\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc1.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => \plusOp__3\(0),
Q => rd_pntr_plus2(0)
);
\gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
D => \plusOp__3\(1),
PRE => AR(0),
Q => rd_pntr_plus2(1)
);
\gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => \plusOp__3\(2),
Q => rd_pntr_plus2(2)
);
\gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d2_reg(0),
CLR => AR(0),
D => \plusOp__3\(3),
Q => rd_pntr_plus2(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rd_bin_cntr_24 is
port (
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc1.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rd_bin_cntr_24 : entity is "rd_bin_cntr";
end system_axi_quad_spi_flash_0_rd_bin_cntr_24;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rd_bin_cntr_24 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gc1.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc1.count[2]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gc1.count[3]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair24";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gc1.count_d2_reg[3]_0\(3 downto 0) <= \^gc1.count_d2_reg[3]_0\(3 downto 0);
\gc1.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gc1.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus2(0),
I1 => rd_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gc1.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus2(0),
I1 => rd_pntr_plus2(1),
I2 => rd_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gc1.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus2(2),
I1 => rd_pntr_plus2(1),
I2 => rd_pntr_plus2(0),
I3 => rd_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gc1.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => rd_pntr_plus2(0),
PRE => AR(0),
Q => \^gc1.count_d2_reg[3]_0\(0)
);
\gc1.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(1),
Q => \^gc1.count_d2_reg[3]_0\(1)
);
\gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(2),
Q => \^gc1.count_d2_reg[3]_0\(2)
);
\gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => rd_pntr_plus2(3),
Q => \^gc1.count_d2_reg[3]_0\(3)
);
\gc1.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[3]_0\(0),
Q => \^q\(0)
);
\gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[3]_0\(1),
Q => \^q\(1)
);
\gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[3]_0\(2),
Q => \^q\(2)
);
\gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^gc1.count_d2_reg[3]_0\(3),
Q => \^q\(3)
);
\gc1.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => rd_pntr_plus2(0)
);
\gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => rd_pntr_plus2(1)
);
\gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => rd_pntr_plus2(2)
);
\gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => rd_pntr_plus2(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rd_fwft is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty_fwft_fb_i_reg_0 : out STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : out STD_LOGIC;
empty_fwft_fb_o_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
QSPI_IO1_T : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
empty_fwft_i0 : in STD_LOGIC;
empty_fwft_fb_o_i0 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_d1 : in STD_LOGIC;
transfer_start : in STD_LOGIC;
SPIXfer_done_int_pulse_d2 : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
SPIXfer_done_rd_tx_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rd_fwft : entity is "rd_fwft";
end system_axi_quad_spi_flash_0_rd_fwft;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 to 1 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ <= empty_fwft_i;
empty_fwft_fb_i_reg_0 <= empty_fwft_fb_i;
empty_fwft_fb_o_i_reg_0 <= empty_fwft_fb_o_i;
\out\(1 downto 0) <= curr_fwft_state(1 downto 0);
QSPI_IO0_T_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => empty_fwft_i,
I1 => Q(0),
O => QSPI_IO1_T
);
\aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEFD8000"
)
port map (
I0 => curr_fwft_state(0),
I1 => ram_empty_fb_i_reg,
I2 => SPIXfer_done_rd_tx_en,
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gpr1.dout_i[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF7F77"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => transfer_start_d1,
I3 => transfer_start,
I4 => SPIXfer_done_int_pulse_d2,
I5 => ram_empty_fb_i_reg,
O => E(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"22020000FFFFFFFF"
)
port map (
I0 => curr_fwft_state(1),
I1 => SPIXfer_done_int_pulse_d2,
I2 => transfer_start,
I3 => transfer_start_d1,
I4 => curr_fwft_state(0),
I5 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => user_valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rd_fwft_22 is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc1.count_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rd_fwft_22 : entity is "rd_fwft";
end system_axi_quad_spi_flash_0_rd_fwft_22;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rd_fwft_22 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal \^gc1.count_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\gc1.count_reg[3]\(0) <= \^gc1.count_reg[3]\(0);
\out\ <= empty_fwft_i;
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F8E0C0F0"
)
port map (
I0 => \IP2Bus_RdAck_receive_enable__1\,
I1 => ram_empty_fb_i_reg,
I2 => aempty_fwft_fb_i,
I3 => curr_fwft_state(1),
I4 => curr_fwft_state(0),
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => AR(0),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"C0EC"
)
port map (
I0 => \IP2Bus_RdAck_receive_enable__1\,
I1 => empty_fwft_fb_i,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"C0EC"
)
port map (
I0 => \IP2Bus_RdAck_receive_enable__1\,
I1 => empty_fwft_fb_o_i,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => AR(0),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => AR(0),
Q => empty_fwft_i
);
\gc1.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => \IP2Bus_RdAck_receive_enable__1\,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => \^gc1.count_reg[3]\(0)
);
\goreg_dm.dout_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55D5555500000000"
)
port map (
I0 => curr_fwft_state(0),
I1 => Bus_RNW_reg,
I2 => p_5_in,
I3 => empty_fwft_i,
I4 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
I5 => curr_fwft_state(1),
O => E(0)
);
\gpr1.dout_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gc1.count_reg[3]\(0),
I1 => ram_empty_fb_i_reg,
O => \gpr1.dout_i_reg[0]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEAEEEEEEEEEEE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => Bus_RNW_reg,
I3 => p_5_in,
I4 => empty_fwft_i,
I5 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => \IP2Bus_RdAck_receive_enable__1\,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => next_fwft_state(0),
Q => user_valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
ram_empty_i0 : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rd_status_flags_as : entity is "rd_status_flags_as";
end system_axi_quad_spi_flash_0_rd_status_flags_as;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rd_status_flags_as_23 is
port (
\out\ : out STD_LOGIC;
ram_empty_i0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rd_status_flags_as_23 : entity is "rd_status_flags_as";
end system_axi_quad_spi_flash_0_rd_status_flags_as_23;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rd_status_flags_as_23 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ram_empty_i0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rom is
port (
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ : out STD_LOGIC;
\qspi_cntrl_ps_reg[0]\ : out STD_LOGIC;
SPISR_0_CMD_Error_int : out STD_LOGIC;
QSPI_IO0_T : out STD_LOGIC;
transfer_start_reg : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
QSPI_IO1_T_0 : out STD_LOGIC;
\qspi_cntrl_ps_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\master_tri_state_en_control1__1\ : in STD_LOGIC;
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\ : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
CMD_decoded_int : in STD_LOGIC;
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\ : in STD_LOGIC;
empty_fwft_i_reg_0 : in STD_LOGIC;
spicr_8_tr_inhibit_to_spi_clk : in STD_LOGIC;
SPIXfer_done_int : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rom : entity is "rom";
end system_axi_quad_spi_flash_0_rom;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rom is
signal Look_up_op : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^qspi_mode_2_t_control.qspi_io2_t_0\ : STD_LOGIC;
signal \qspo_int[0]_i_4_n_0\ : STD_LOGIC;
signal \qspo_int[0]_i_5_n_0\ : STD_LOGIC;
signal \qspo_int[0]_i_6_n_0\ : STD_LOGIC;
signal \qspo_int[0]_i_7_n_0\ : STD_LOGIC;
signal \qspo_int[10]_i_1_n_0\ : STD_LOGIC;
signal \qspo_int[10]_i_2_n_0\ : STD_LOGIC;
signal \qspo_int[3]_i_4_n_0\ : STD_LOGIC;
signal \qspo_int[3]_i_5_n_0\ : STD_LOGIC;
signal \qspo_int[3]_i_6_n_0\ : STD_LOGIC;
signal \qspo_int[3]_i_7_n_0\ : STD_LOGIC;
signal \qspo_int[5]_i_1_n_0\ : STD_LOGIC;
signal \qspo_int[5]_i_2_n_0\ : STD_LOGIC;
signal \qspo_int[6]_i_1_n_0\ : STD_LOGIC;
signal \qspo_int[7]_i_1_n_0\ : STD_LOGIC;
signal \qspo_int[7]_i_2_n_0\ : STD_LOGIC;
signal \qspo_int[8]_i_1_n_0\ : STD_LOGIC;
signal \qspo_int[8]_i_2_n_0\ : STD_LOGIC;
signal \qspo_int[9]_i_1_n_0\ : STD_LOGIC;
signal \qspo_int[9]_i_2_n_0\ : STD_LOGIC;
signal \qspo_int_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \qspo_int_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \qspo_int_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \qspo_int_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \qspo_int_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \qspo_int_reg[3]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \qspo_int[5]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \qspo_int[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \qspo_int[8]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \qspo_int[9]_i_1\ : label is "soft_lutpair33";
begin
Q(6 downto 0) <= \^q\(6 downto 0);
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ <= \^qspi_mode_2_t_control.qspi_io2_t_0\;
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_1_CDC_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => CMD_decoded_int,
I1 => Look_up_op(0),
O => SPISR_0_CMD_Error_int
);
QSPI_IO0_T_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"888888808888888F"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
I2 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\,
I3 => \qspi_cntrl_ps_reg[2]\(0),
I4 => empty_fwft_i_reg_0,
I5 => \^q\(6),
O => QSPI_IO0_T
);
QSPI_IO1_T_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9F9F909F909F9F9F"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \qspi_cntrl_ps_reg[2]\(0),
I3 => \^q\(6),
I4 => \^q\(4),
I5 => \^q\(5),
O => QSPI_IO1_T
);
QSPI_IO1_T_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => QSPI_IO1_T_0
);
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7C7FFFF"
)
port map (
I0 => \^q\(5),
I1 => \qspi_cntrl_ps_reg[2]\(2),
I2 => \qspi_cntrl_ps_reg[2]\(1),
I3 => \^qspi_mode_2_t_control.qspi_io2_t_0\,
I4 => \master_tri_state_en_control1__1\,
O => \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\
);
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3332333733373337"
)
port map (
I0 => \qspi_cntrl_ps_reg[2]\(0),
I1 => \^q\(2),
I2 => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\,
I3 => empty_fwft_i_reg_0,
I4 => \^q\(6),
I5 => \^q\(5),
O => \^qspi_mode_2_t_control.qspi_io2_t_0\
);
\qspi_cntrl_ps[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"D500D5FFD500D500"
)
port map (
I0 => \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\,
I1 => \^q\(0),
I2 => empty_fwft_i_reg,
I3 => \qspi_cntrl_ps_reg[2]\(0),
I4 => Look_up_op(0),
I5 => CMD_decoded_int,
O => \qspi_cntrl_ps_reg[0]\
);
\qspo_int[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF3FF9FFFEEEEEE3"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[0]_i_4_n_0\
);
\qspo_int[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFB7FFFFFF4FFFFF"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[0]_i_5_n_0\
);
\qspo_int[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEDF3FFFFF"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[0]_i_6_n_0\
);
\qspo_int[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFBFBDFFFF3FFF"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[0]_i_7_n_0\
);
\qspo_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \qspo_int[10]_i_2_n_0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[10]_i_1_n_0\
);
\qspo_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[10]_i_2_n_0\
);
\qspo_int[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040060001110104"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[3]_i_4_n_0\
);
\qspo_int[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000040000000B000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[3]_i_5_n_0\
);
\qspo_int[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000010000C000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[3]_i_6_n_0\
);
\qspo_int[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1040000200800000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[3]_i_7_n_0\
);
\qspo_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \qspo_int[5]_i_2_n_0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[5]_i_1_n_0\
);
\qspo_int[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[5]_i_2_n_0\
);
\qspo_int[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \qspo_int[8]_i_2_n_0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[6]_i_1_n_0\
);
\qspo_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0BBF088"
)
port map (
I0 => \qspo_int[9]_i_2_n_0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \qspo_int[7]_i_2_n_0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \qspo_int[10]_i_2_n_0\,
O => \qspo_int[7]_i_1_n_0\
);
\qspo_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0600000000000000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[7]_i_2_n_0\
);
\qspo_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \qspo_int[8]_i_2_n_0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[8]_i_1_n_0\
);
\qspo_int[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[8]_i_2_n_0\
);
\qspo_int[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \qspo_int[9]_i_2_n_0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \qspo_int[10]_i_2_n_0\,
O => \qspo_int[9]_i_1_n_0\
);
\qspo_int[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
I1 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
I2 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
I3 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
I4 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
I5 => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
O => \qspo_int[9]_i_2_n_0\
);
\qspo_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int_reg[0]_i_1_n_0\,
Q => Look_up_op(0),
R => Rst_to_spi
);
\qspo_int_reg[0]_i_1\: unisim.vcomponents.MUXF8
port map (
I0 => \qspo_int_reg[0]_i_2_n_0\,
I1 => \qspo_int_reg[0]_i_3_n_0\,
O => \qspo_int_reg[0]_i_1_n_0\,
S => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\
);
\qspo_int_reg[0]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \qspo_int[0]_i_4_n_0\,
I1 => \qspo_int[0]_i_5_n_0\,
O => \qspo_int_reg[0]_i_2_n_0\,
S => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\
);
\qspo_int_reg[0]_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \qspo_int[0]_i_6_n_0\,
I1 => \qspo_int[0]_i_7_n_0\,
O => \qspo_int_reg[0]_i_3_n_0\,
S => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\
);
\qspo_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int[10]_i_1_n_0\,
Q => \^q\(6),
R => Rst_to_spi
);
\qspo_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int_reg[3]_i_1_n_0\,
Q => \^q\(0),
R => Rst_to_spi
);
\qspo_int_reg[3]_i_1\: unisim.vcomponents.MUXF8
port map (
I0 => \qspo_int_reg[3]_i_2_n_0\,
I1 => \qspo_int_reg[3]_i_3_n_0\,
O => \qspo_int_reg[3]_i_1_n_0\,
S => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\
);
\qspo_int_reg[3]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \qspo_int[3]_i_4_n_0\,
I1 => \qspo_int[3]_i_5_n_0\,
O => \qspo_int_reg[3]_i_2_n_0\,
S => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\
);
\qspo_int_reg[3]_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \qspo_int[3]_i_6_n_0\,
I1 => \qspo_int[3]_i_7_n_0\,
O => \qspo_int_reg[3]_i_3_n_0\,
S => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\
);
\qspo_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int[5]_i_1_n_0\,
Q => \^q\(1),
R => Rst_to_spi
);
\qspo_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int[6]_i_1_n_0\,
Q => \^q\(2),
R => Rst_to_spi
);
\qspo_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int[7]_i_1_n_0\,
Q => \^q\(3),
R => Rst_to_spi
);
\qspo_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int[8]_i_1_n_0\,
Q => \^q\(4),
R => Rst_to_spi
);
\qspo_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \qspo_int[9]_i_1_n_0\,
Q => \^q\(5),
R => Rst_to_spi
);
transfer_start_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEAA"
)
port map (
I0 => spicr_8_tr_inhibit_to_spi_clk,
I1 => SPIXfer_done_int,
I2 => \^q\(3),
I3 => empty_fwft_i_reg,
I4 => \^q\(0),
O => transfer_start_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_synchronizer_ff : entity is "synchronizer_ff";
end system_axi_quad_spi_flash_0_synchronizer_ff;
architecture STRUCTURE of system_axi_quad_spi_flash_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_synchronizer_ff_15 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_synchronizer_ff_15 : entity is "synchronizer_ff";
end system_axi_quad_spi_flash_0_synchronizer_ff_15;
architecture STRUCTURE of system_axi_quad_spi_flash_0_synchronizer_ff_15 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_synchronizer_ff_16 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_synchronizer_ff_16 : entity is "synchronizer_ff";
end system_axi_quad_spi_flash_0_synchronizer_ff_16;
architecture STRUCTURE of system_axi_quad_spi_flash_0_synchronizer_ff_16 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_synchronizer_ff_17 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_synchronizer_ff_17 : entity is "synchronizer_ff";
end system_axi_quad_spi_flash_0_synchronizer_ff_17;
architecture STRUCTURE of system_axi_quad_spi_flash_0_synchronizer_ff_17 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_synchronizer_ff_18 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_synchronizer_ff_18 : entity is "synchronizer_ff";
end system_axi_quad_spi_flash_0_synchronizer_ff_18;
architecture STRUCTURE of system_axi_quad_spi_flash_0_synchronizer_ff_18 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_synchronizer_ff_3 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_synchronizer_ff_3 : entity is "synchronizer_ff";
end system_axi_quad_spi_flash_0_synchronizer_ff_3;
architecture STRUCTURE of system_axi_quad_spi_flash_0_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_synchronizer_ff_4 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_synchronizer_ff_4 : entity is "synchronizer_ff";
end system_axi_quad_spi_flash_0_synchronizer_ff_4;
architecture STRUCTURE of system_axi_quad_spi_flash_0_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_synchronizer_ff_5 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_synchronizer_ff_5 : entity is "synchronizer_ff";
end system_axi_quad_spi_flash_0_synchronizer_ff_5;
architecture STRUCTURE of system_axi_quad_spi_flash_0_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0_25\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0_25\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0_25\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0_25\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1_26\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1_26\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1_26\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1_26\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2_27\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2_27\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2_27\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2_27\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3_28\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3_28\ : entity is "synchronizer_ff";
end \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3_28\;
architecture STRUCTURE of \system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3_28\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_wr_bin_cntr is
port (
ram_full_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\IP2Bus_WrAck_transmit_enable__0\ : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_wr_bin_cntr : entity is "wr_bin_cntr";
end system_axi_quad_spi_flash_0_wr_bin_cntr;
architecture STRUCTURE of system_axi_quad_spi_flash_0_wr_bin_cntr is
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_3_n_0 : STD_LOGIC;
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_plus3 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc1.count[0]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \gic0.gc1.count[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \gic0.gc1.count[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \gic0.gc1.count[3]_i_1\ : label is "soft_lutpair31";
begin
\gic0.gc1.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus3(0),
O => \plusOp__1\(0)
);
\gic0.gc1.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
O => \plusOp__1\(1)
);
\gic0.gc1.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
I2 => wr_pntr_plus3(2),
O => \plusOp__1\(2)
);
\gic0.gc1.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus3(2),
I1 => wr_pntr_plus3(1),
I2 => wr_pntr_plus3(0),
I3 => wr_pntr_plus3(3),
O => \plusOp__1\(3)
);
\gic0.gc1.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc1.count_d1_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => wr_pntr_plus3(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc1.count_d2_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => p_13_out(0)
);
\gic0.gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => p_13_out(1)
);
\gic0.gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => p_13_out(2)
);
\gic0.gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => p_13_out(3)
);
\gic0.gc1.count_d3_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(0),
Q => Q(0)
);
\gic0.gc1.count_d3_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(1),
Q => Q(1)
);
\gic0.gc1.count_d3_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(2),
Q => Q(2)
);
\gic0.gc1.count_d3_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(3),
Q => Q(3)
);
\gic0.gc1.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \plusOp__1\(0),
PRE => AR(0),
Q => wr_pntr_plus3(0)
);
\gic0.gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => wr_pntr_plus3(1)
);
\gic0.gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => wr_pntr_plus3(2)
);
\gic0.gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => wr_pntr_plus3(3)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EBAAAAEBAAAAAAAA"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => p_13_out(3),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3),
I3 => p_13_out(2),
I4 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(2),
I5 => ram_full_i_i_3_n_0,
O => ram_full_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3),
I2 => wr_pntr_plus2(2),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(2),
I4 => \IP2Bus_WrAck_transmit_enable__0\,
I5 => ram_full_i_i_5_n_0,
O => ram_full_i_i_2_n_0
);
ram_full_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"41000041"
)
port map (
I0 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I1 => p_13_out(1),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(1),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
I4 => p_13_out(0),
O => ram_full_i_i_3_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0009000000000009"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(1),
I1 => wr_pntr_plus2(1),
I2 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I3 => \out\,
I4 => wr_pntr_plus2(0),
I5 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_wr_bin_cntr_21 is
port (
ram_full_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_0 : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_wr_bin_cntr_21 : entity is "wr_bin_cntr";
end system_axi_quad_spi_flash_0_wr_bin_cntr_21;
architecture STRUCTURE of system_axi_quad_spi_flash_0_wr_bin_cntr_21 is
signal \gwas.wsts/comp1\ : STD_LOGIC;
signal \gwas.wsts/comp2\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
signal \ram_full_i_i_5__0_n_0\ : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_plus3 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc1.count[0]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gic0.gc1.count[1]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gic0.gc1.count[2]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gic0.gc1.count[3]_i_1__0\ : label is "soft_lutpair25";
begin
\gic0.gc1.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus3(0),
O => \plusOp__2\(0)
);
\gic0.gc1.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
O => \plusOp__2\(1)
);
\gic0.gc1.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus3(0),
I1 => wr_pntr_plus3(1),
I2 => wr_pntr_plus3(2),
O => \plusOp__2\(2)
);
\gic0.gc1.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus3(1),
I1 => wr_pntr_plus3(0),
I2 => wr_pntr_plus3(2),
I3 => wr_pntr_plus3(3),
O => \plusOp__2\(3)
);
\gic0.gc1.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc1.count_d1_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => wr_pntr_plus3(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc1.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc1.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus3(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc1.count_d2_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => p_13_out(0)
);
\gic0.gc1.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => p_13_out(1)
);
\gic0.gc1.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => p_13_out(2)
);
\gic0.gc1.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => p_13_out(3)
);
\gic0.gc1.count_d3_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(0),
Q => Q(0)
);
\gic0.gc1.count_d3_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(1),
Q => Q(1)
);
\gic0.gc1.count_d3_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(2),
Q => Q(2)
);
\gic0.gc1.count_d3_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(3),
Q => Q(3)
);
\gic0.gc1.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => \plusOp__2\(0),
PRE => AR(0),
Q => wr_pntr_plus3(0)
);
\gic0.gc1.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => E(0),
D => \plusOp__2\(1),
PRE => AR(0),
Q => wr_pntr_plus3(1)
);
\gic0.gc1.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(2),
Q => wr_pntr_plus3(2)
);
\gic0.gc1.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(3),
Q => wr_pntr_plus3(3)
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF20"
)
port map (
I0 => \gwas.wsts/comp2\,
I1 => ram_full_fb_i_reg_0,
I2 => spiXfer_done_int,
I3 => \gwas.wsts/comp1\,
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3),
I1 => wr_pntr_plus2(3),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(2),
I3 => wr_pntr_plus2(2),
I4 => \ram_full_i_i_4__0_n_0\,
O => \gwas.wsts/comp2\
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3),
I1 => p_13_out(3),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(2),
I3 => p_13_out(2),
I4 => \ram_full_i_i_5__0_n_0\,
O => \gwas.wsts/comp1\
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(1),
I2 => wr_pntr_plus2(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => \ram_full_i_i_4__0_n_0\
);
\ram_full_i_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_13_out(1),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(1),
I2 => p_13_out(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => \ram_full_i_i_5__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_wr_status_flags_as is
port (
\gic0.gc1.count_reg[3]\ : out STD_LOGIC;
\out\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc1.count_d2_reg[3]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip_irpt_enable_reg_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\icount_out_reg[3]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[3]\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_wr_status_flags_as : entity is "wr_status_flags_as";
end system_axi_quad_spi_flash_0_wr_status_flags_as;
architecture STRUCTURE of system_axi_quad_spi_flash_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc1.count_reg[3]\ <= ram_full_i;
\out\ <= ram_full_fb_i;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFF888"
)
port map (
I0 => ram_full_i,
I1 => bus2ip_rdce_int(0),
I2 => \ip_irpt_enable_reg_reg[3]\(0),
I3 => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
I4 => \icount_out_reg[3]\,
I5 => \goreg_dm.dout_i_reg[3]\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0)
);
\gic0.gc1.count_d1[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
I1 => ram_full_i,
I2 => p_6_in,
I3 => Bus_RNW_reg,
I4 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gic0.gc1.count_d2_reg[3]\,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gic0.gc1.count_d2_reg[3]\,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_wr_status_flags_as_20 is
port (
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg_1 : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
scndry_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_wr_status_flags_as_20 : entity is "wr_status_flags_as";
end system_axi_quad_spi_flash_0_wr_status_flags_as_20;
architecture STRUCTURE of system_axi_quad_spi_flash_0_wr_status_flags_as_20 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ <= ram_full_i;
ram_full_fb_i_reg_0 <= ram_full_fb_i;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ram_full_i,
I1 => scndry_out,
O => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => ram_full_fb_i_reg_1,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => ram_full_fb_i_reg_1,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_address_decoder is
port (
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\ : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ : out STD_LOGIC;
p_4_in : out STD_LOGIC;
Receive_ip2bus_error_reg : out STD_LOGIC;
Transmit_ip2bus_error_reg : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_0\ : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_1\ : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
wr_ce_or_reduce_core_cmb : out STD_LOGIC;
bus2ip_wrce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
SPICR_data_int_reg0 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
p_15_in : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[26]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\ : out STD_LOGIC;
bus2ip_rdce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\p_39_out__0\ : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Receive_ip2bus_error0 : out STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : out STD_LOGIC;
Transmit_ip2bus_error0 : out STD_LOGIC;
IP2Bus_Error_1 : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ : out STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : out STD_LOGIC;
rd_ce_or_reduce_core_cmb : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
intr_controller_rd_ce_or_reduce : out STD_LOGIC;
intr_controller_wr_ce_or_reduce : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC;
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : out STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
ip2Bus_WrAck_core_reg_d1 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
is_read : in STD_LOGIC;
p_15_out : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
p_16_out : in STD_LOGIC;
\out\ : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
bus2ip_be_int : in STD_LOGIC_VECTOR ( 0 to 0 );
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_1_in23_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
\ip_irpt_enable_reg_reg[10]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_1_in14_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : in STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_1_in29_in : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
rx_fifo_empty_i : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
p_10_out : in STD_LOGIC;
p_11_out : in STD_LOGIC;
bus2ip_rnw_i_reg_0 : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
SPISR_2_MSB_Error_int : in STD_LOGIC;
SPISR_1_LOOP_Back_Error_int : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_address_decoder : entity is "address_decoder";
end system_axi_quad_spi_flash_0_address_decoder;
architecture STRUCTURE of system_axi_quad_spi_flash_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[22]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_2_n_0\ : STD_LOGIC;
signal \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\ : STD_LOGIC;
signal \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\ : STD_LOGIC;
signal \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[26]\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\ : STD_LOGIC;
signal \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_d1_reg\ : STD_LOGIC;
signal \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg\ : STD_LOGIC;
signal \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_i_2_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\ : STD_LOGIC;
signal \^receive_ip2bus_error_reg\ : STD_LOGIC;
signal \^transmit_ip2bus_error_reg\ : STD_LOGIC;
signal \^bus2ip_rdce_int\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal cs_ce_clr : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 : STD_LOGIC;
signal \^ipif_glbl_irpt_enable_reg_reg\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out_2 : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out_1 : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal \^p_15_in\ : STD_LOGIC;
signal p_15_in_0 : STD_LOGIC;
signal p_15_out_3 : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_18_in : STD_LOGIC;
signal p_19_in : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_20_in : STD_LOGIC;
signal p_21_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_24_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_26_in : STD_LOGIC;
signal p_27_in : STD_LOGIC;
signal p_28_in : STD_LOGIC;
signal p_29_in : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_30_in : STD_LOGIC;
signal p_31_in : STD_LOGIC;
signal p_32_in : STD_LOGIC;
signal \^p_39_out__0\ : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal \^p_4_in\ : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int[9]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[18]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[18]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[21]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[22]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_3\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of Receive_ip2bus_error_i_1 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of Transmit_ip2bus_error_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gc1.count_d1[3]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of ip2Bus_RdAck_intr_reg_hole_d1_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of ip2Bus_RdAck_intr_reg_hole_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of ip2Bus_WrAck_intr_reg_hole_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \ip_irpt_enable_reg[13]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of ram_full_i_i_4 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of reset_trig_i_1 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of sw_rst_cond_d1_i_1 : label is "soft_lutpair2";
begin
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\ <= \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\ <= \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[26]\ <= \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[26]\;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\ <= \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_d1_reg\;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ <= \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg\;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_0\ <= \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg_0\;
Receive_ip2bus_error_reg <= \^receive_ip2bus_error_reg\;
Transmit_ip2bus_error_reg <= \^transmit_ip2bus_error_reg\;
bus2ip_rdce_int(0) <= \^bus2ip_rdce_int\(0);
ipif_glbl_irpt_enable_reg_reg <= \^ipif_glbl_irpt_enable_reg_reg\;
p_15_in <= \^p_15_in\;
\p_39_out__0\ <= \^p_39_out__0\;
p_4_in <= \^p_4_in\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => start2,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^ipif_glbl_irpt_enable_reg_reg\,
R => '0'
);
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E200000000"
)
port map (
I0 => spicr_6_rxfifo_rst_frm_axi_clk,
I1 => ip2Bus_WrAck_core_reg_1,
I2 => s_axi_wdata(3),
I3 => reset2ip_reset_int,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
I5 => p_8_in,
O => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\
);
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E200000000"
)
port map (
I0 => spicr_5_txfifo_rst_frm_axi_clk,
I1 => ip2Bus_WrAck_core_reg_1,
I2 => s_axi_wdata(2),
I3 => reset2ip_reset_int,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
I5 => p_8_in,
O => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\
);
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => ip2Bus_WrAck_core_reg_1,
I1 => p_8_in,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
O => SPICR_data_int_reg0
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => p_32_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_5_out,
Q => p_22_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_4_out,
Q => p_21_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_3_out,
Q => p_20_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_2_out,
Q => p_19_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_1_out,
Q => p_18_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => Q(3),
I1 => Q(1),
I2 => Q(0),
I3 => Q(4),
I4 => start2,
I5 => Q(2),
O => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1_n_0\,
Q => p_17_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000000"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => Q(3),
I3 => start2,
I4 => Q(4),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0\,
Q => p_16_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => start2,
I5 => Q(4),
O => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0\,
Q => p_15_in_0,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => p_14_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => Q(3),
I1 => start2,
I2 => Q(4),
I3 => Q(2),
I4 => Q(0),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0\,
Q => p_13_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_14_out,
Q => p_31_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => Q(3),
I3 => start2,
I4 => Q(4),
I5 => Q(2),
O => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1_n_0\,
Q => p_12_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000000000"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
I3 => Q(3),
I4 => start2,
I5 => Q(4),
O => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1_n_0\,
Q => p_11_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => p_10_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => Q(3),
I1 => start2,
I2 => Q(4),
I3 => Q(2),
I4 => Q(0),
I5 => Q(1),
O => p_15_out_3
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_15_out_3,
Q => p_9_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => Q(4),
I3 => Q(3),
I4 => start2,
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1_n_0\,
Q => p_8_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(4),
I4 => Q(3),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1_n_0\,
Q => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => \^transmit_ip2bus_error_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000000000000"
)
port map (
I0 => Q(4),
I1 => Q(3),
I2 => start2,
I3 => Q(2),
I4 => Q(0),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1_n_0\,
Q => \^receive_ip2bus_error_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => Q(4),
I3 => Q(3),
I4 => start2,
I5 => Q(2),
O => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1_n_0\,
Q => \^p_4_in\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
I3 => Q(4),
I4 => Q(3),
I5 => start2,
O => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1_n_0\,
Q => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_13_out,
Q => p_30_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_d1_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => Q(4),
I1 => Q(3),
I2 => start2,
I3 => Q(2),
I4 => Q(0),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2_n_0\,
Q => \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_12_out,
Q => p_29_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_11_out_1,
Q => p_28_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_10_out_2,
Q => p_27_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_9_out,
Q => p_26_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_8_out,
Q => p_25_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_7_out,
Q => p_24_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2,
D => p_6_out,
Q => p_23_in,
R => cs_ce_clr
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => irpt_wrack_d1,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => bus2ip_be_int(0),
I3 => p_24_in,
O => \^p_39_out__0\
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^p_39_out__0\,
I1 => s_axi_wdata(1),
I2 => p_1_in29_in,
O => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => p_22_in,
I1 => p_24_in,
I2 => bus2ip_be_int(0),
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
I4 => p_25_in,
I5 => ipif_glbl_irpt_enable_reg,
O => D(5)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[18]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => p_24_in,
I2 => s_axi_wstrb(0),
I3 => bus2ip_rnw_i_reg,
O => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[26]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[18]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A80000"
)
port map (
I0 => p_22_in,
I1 => bus2ip_rnw_i_reg,
I2 => s_axi_wstrb(0),
I3 => p_24_in,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\,
I1 => \ip_irpt_enable_reg_reg[10]\(4),
I2 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\,
I3 => \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\,
I4 => p_1_in8_in,
I5 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[26]\,
O => D(4)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[21]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg_0\,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\,
I1 => \ip_irpt_enable_reg_reg[10]\(3),
I2 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[26]\,
I3 => p_1_in11_in,
I4 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[22]_i_2_n_0\,
O => D(3)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[22]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => SPISR_2_MSB_Error_int,
I1 => p_8_in,
I2 => SPISR_1_LOOP_Back_Error_int,
I3 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg_0\,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[22]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\,
I1 => \ip_irpt_enable_reg_reg[10]\(2),
I2 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[26]\,
I3 => p_1_in14_in,
I4 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\,
O => D(2)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8880000"
)
port map (
I0 => p_8_in,
I1 => spicr_8_tr_inhibit_frm_axi_clk,
I2 => SPISR_2_MSB_Error_int,
I3 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg_0\,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[23]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_2_n_0\,
I1 => \goreg_dm.dout_i_reg[7]\(1),
I2 => \^p_15_in\,
I3 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[26]\,
I4 => p_1_in17_in,
O => D(1)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF222F222F222"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\,
I1 => spicr_2_mst_n_slv_frm_axi_clk,
I2 => spicr_7_ss_frm_axi_clk,
I3 => \^bus2ip_rdce_int\(0),
I4 => \ip_irpt_enable_reg_reg[10]\(1),
I5 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[24]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => ip2Bus_RdAck_core_reg,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => \^receive_ip2bus_error_reg\,
O => \^p_15_in\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_2_n_0\,
I1 => \goreg_dm.dout_i_reg[7]\(0),
I2 => \^p_15_in\,
I3 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[26]\,
I4 => p_1_in23_in,
O => D(0)
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[21]\,
I1 => \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\,
I2 => \^bus2ip_rdce_int\(0),
I3 => spicr_5_txfifo_rst_frm_axi_clk,
I4 => \ip_irpt_enable_reg_reg[10]\(0),
I5 => \^legacy_md_ip2bus_data_gen.ip2bus_data_reg[23]\,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[26]_i_2_n_0\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_d1_reg\,
I2 => empty_fwft_i_reg,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg\,
I2 => Tx_FIFO_Empty_SPISR_to_axi_clk,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_8_in,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \^bus2ip_rdce_int\(0)
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEFEEE"
)
port map (
I0 => p_10_out,
I1 => p_11_out,
I2 => bus2ip_rnw_i_reg_0,
I3 => p_16_in,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
O => IP2Bus_Error_1
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_16_in,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
O => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AFAE"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
I3 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_d1_reg\,
O => wr_ce_or_reduce_core_cmb
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF00FF00FF00BA"
)
port map (
I0 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg_0\,
I1 => \out\,
I2 => \^transmit_ip2bus_error_reg\,
I3 => \^ipif_glbl_irpt_enable_reg_reg\,
I4 => p_8_in,
I5 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg\,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\,
I1 => p_12_in,
I2 => p_15_in_0,
I3 => p_9_in,
I4 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^p_4_in\,
I1 => \^receive_ip2bus_error_reg\,
I2 => p_13_in,
I3 => p_11_in,
I4 => p_10_in,
I5 => p_14_in,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AFAE"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
I3 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_d1_reg\,
I4 => ip2Bus_WrAck_core_reg_d1,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_1\
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FAEA"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_i_2_n_0\,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
I3 => \^transmit_ip2bus_error_reg\,
O => rd_ce_or_reduce_core_cmb
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF0000FFFE0000"
)
port map (
I0 => p_16_in,
I1 => p_8_in,
I2 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg_0\,
I3 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_reg\,
I4 => \^ipif_glbl_irpt_enable_reg_reg\,
I5 => \^legacy_md_wr_rd_ack_gen.ip2bus_wrack_core_reg_d1_reg\,
O => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_i_2_n_0\
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized0\
port map (
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q(4 downto 0) => Q(4 downto 0),
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[10].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized10\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_5_out => p_5_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[11].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized11\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_4_out => p_4_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[12].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized12\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_3_out => p_3_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[13].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized13\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_2_out => p_2_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[14].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized14\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_1_out => p_1_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[1].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized1\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_14_out => p_14_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized2\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_13_out => p_13_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[3].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized3\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_12_out => p_12_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized4\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_11_out_1 => p_11_out_1,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized5\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_10_out_2 => p_10_out_2,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized6\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_9_out => p_9_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized7\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_8_out => p_8_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[8].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized8\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_7_out => p_7_out,
start2 => start2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[9].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized9\
port map (
Q(4 downto 0) => Q(4 downto 0),
p_6_out => p_6_out,
start2 => start2
);
\MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized19\
port map (
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\ => \MEM_DECODE_GEN[1].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q(4 downto 0) => Q(4 downto 0),
start2 => start2
);
\MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized23\
port map (
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\ => \MEM_DECODE_GEN[1].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q(4 downto 0) => Q(4 downto 0),
start2 => start2
);
\MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized28\
port map (
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\ => \MEM_DECODE_GEN[2].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q(4 downto 0) => Q(4 downto 0),
start2 => start2
);
\MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\system_axi_quad_spi_flash_0_axi_lite_ipif_v3_0_4_pselect_f__parameterized32\
port map (
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\ => \MEM_DECODE_GEN[2].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I_n_0\,
Q(4 downto 0) => Q(4 downto 0),
start2 => start2
);
Receive_ip2bus_error_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => \^receive_ip2bus_error_reg\,
I2 => rx_fifo_empty_i,
I3 => empty_fwft_i_reg,
O => Receive_ip2bus_error0
);
\SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_8_in,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
O => bus2ip_wrce_int(0)
);
\SPISSR_WR_GEN[0].SPISSR_Data_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFF2000"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => ip2Bus_WrAck_core_reg_1,
I3 => \^p_4_in\,
I4 => SPISSR_frm_axi_clk,
O => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\
);
Transmit_ip2bus_error_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => \out\,
I2 => \^transmit_ip2bus_error_reg\,
O => Transmit_ip2bus_error0
);
\gc1.count_d1[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => \^receive_ip2bus_error_reg\,
I2 => empty_fwft_i_reg,
I3 => ip2Bus_RdAck_core_reg,
O => \IP2Bus_RdAck_receive_enable__1\
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A0A0A080"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => p_22_in,
I2 => bus2ip_be_int(0),
I3 => p_25_in,
I4 => p_24_in,
I5 => irpt_rdack_d1,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000044444440"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => bus2ip_be_int(0),
I2 => p_22_in,
I3 => p_25_in,
I4 => p_24_in,
I5 => irpt_wrack_d1,
O => interrupt_wrce_strb
);
ip2Bus_RdAck_intr_reg_hole_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
O => intr_controller_rd_ce_or_reduce
);
ip2Bus_RdAck_intr_reg_hole_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => ip2Bus_RdAck_intr_reg_hole_d1,
O => ip2Bus_RdAck_intr_reg_hole0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
O => intr_controller_wr_ce_or_reduce
);
ip2Bus_WrAck_intr_reg_hole_d1_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0,
I1 => p_20_in,
I2 => p_23_in,
I3 => p_18_in,
I4 => p_19_in,
I5 => ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_29_in,
I1 => p_21_in,
I2 => p_30_in,
I3 => p_32_in,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_31_in,
I1 => p_28_in,
I2 => p_17_in,
I3 => p_26_in,
I4 => p_27_in,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0
);
ip2Bus_WrAck_intr_reg_hole_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => ip2Bus_WrAck_intr_reg_hole_d1,
O => ip2Bus_WrAck_intr_reg_hole0
);
\ip_irpt_enable_reg[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5400"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => bus2ip_rnw_i_reg,
I2 => s_axi_wstrb(0),
I3 => p_22_in,
O => E(0)
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEFFFFF22200000"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^ipif_glbl_irpt_enable_reg_reg\,
I2 => bus2ip_rnw_i_reg,
I3 => s_axi_wstrb(0),
I4 => p_25_in,
I5 => ipif_glbl_irpt_enable_reg,
O => ipif_glbl_irpt_enable_reg_reg_0
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0EEE000000000"
)
port map (
I0 => p_24_in,
I1 => p_25_in,
I2 => bus2ip_rnw_i_reg,
I3 => s_axi_wstrb(0),
I4 => p_22_in,
I5 => \^ipif_glbl_irpt_enable_reg_reg\,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FEFEFE00"
)
port map (
I0 => p_24_in,
I1 => p_25_in,
I2 => p_22_in,
I3 => s_axi_wstrb(0),
I4 => bus2ip_rnw_i_reg,
I5 => \^ipif_glbl_irpt_enable_reg_reg\,
O => irpt_wrack
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => \^transmit_ip2bus_error_reg\,
I2 => \out\,
I3 => ip2Bus_WrAck_core_reg_1,
O => \IP2Bus_WrAck_transmit_enable__0\
);
reset_trig_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => sw_rst_cond_d1,
I1 => p_16_in,
I2 => \^ipif_glbl_irpt_enable_reg_reg\,
I3 => bus2ip_rnw_i_reg_0,
O => reset_trig0
);
s_axi_arready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I2 => is_read,
I3 => s_axi_wready_INST_0_i_1_n_0,
I4 => p_15_out,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I2 => is_write_reg,
I3 => s_axi_wready_INST_0_i_1_n_0,
I4 => p_16_out,
O => \^s_axi_wready\
);
s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2),
O => s_axi_wready_INST_0_i_1_n_0
);
sw_rst_cond_d1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^ipif_glbl_irpt_enable_reg_reg\,
I1 => p_16_in,
I2 => bus2ip_rnw_i_reg_0,
O => sw_rst_cond
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i0 : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc1.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc1.count_d3_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_clk_x_pntrs : entity is "clk_x_pntrs";
end system_axi_quad_spi_flash_0_clk_x_pntrs;
architecture STRUCTURE of system_axi_quad_spi_flash_0_clk_x_pntrs is
signal \_inferred__0/i__n_0\ : STD_LOGIC;
signal \_inferred__2/i__n_0\ : STD_LOGIC;
signal \_inferred__3/i__n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_4__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_inferred__2/i_\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \_inferred__3/i_\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair28";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
\_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \_inferred__0/i__n_0\
);
\_inferred__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(1),
I1 => p_6_out(0),
I2 => p_6_out(3),
I3 => p_6_out(2),
O => \_inferred__2/i__n_0\
);
\_inferred__3/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(1),
I2 => p_6_out(3),
O => \_inferred__3/i__n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
ext_spi_clk => ext_spi_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2\
port map (
D(0) => \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
ext_spi_clk => ext_spi_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
\out\(3 downto 0) => p_6_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \_inferred__2/i__n_0\,
Q => ram_full_i_reg(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \_inferred__3/i__n_0\,
Q => ram_full_i_reg(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => ram_full_i_reg(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => p_6_out(3),
Q => ram_full_i_reg(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \_inferred__0/i__n_0\,
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\,
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(0),
I1 => \gic0.gc1.count_d3_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(1),
I1 => \gic0.gc1.count_d3_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(2),
I1 => \gic0.gc1.count_d3_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc1.count_d3_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF41000041"
)
port map (
I0 => \ram_empty_i_i_2__0_n_0\,
I1 => p_22_out(2),
I2 => Q(2),
I3 => p_22_out(3),
I4 => Q(3),
I5 => \ram_empty_i_i_3__0_n_0\,
O => ram_empty_i0
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
I2 => p_22_out(0),
I3 => Q(0),
O => \ram_empty_i_i_2__0_n_0\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4100004100000000"
)
port map (
I0 => \ram_empty_i_i_4__0_n_0\,
I1 => p_22_out(2),
I2 => \gc1.count_d1_reg[3]\(2),
I3 => p_22_out(3),
I4 => \gc1.count_d1_reg[3]\(3),
I5 => E(0),
O => \ram_empty_i_i_3__0_n_0\
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(1),
I1 => \gc1.count_d1_reg[3]\(1),
I2 => p_22_out(0),
I3 => \gc1.count_d1_reg[3]\(0),
O => \ram_empty_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_clk_x_pntrs_10 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i0 : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc1.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc1.count_d3_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc1.count_d2_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_clk_x_pntrs_10 : entity is "clk_x_pntrs";
end system_axi_quad_spi_flash_0_clk_x_pntrs_10;
architecture STRUCTURE of system_axi_quad_spi_flash_0_clk_x_pntrs_10 is
signal \_inferred__2/i__n_0\ : STD_LOGIC;
signal \_inferred__3/i__n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_inferred__2/i_\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \_inferred__3/i_\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair22";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
\_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\_inferred__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(1),
I1 => p_6_out(0),
I2 => p_6_out(3),
I3 => p_6_out(2),
O => \_inferred__2/i__n_0\
);
\_inferred__3/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(1),
I2 => p_6_out(3),
O => \_inferred__3/i__n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_axi_quad_spi_flash_0_synchronizer_ff__parameterized0_25\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_axi_quad_spi_flash_0_synchronizer_ff__parameterized1_26\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0),
ext_spi_clk => ext_spi_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_axi_quad_spi_flash_0_synchronizer_ff__parameterized2_27\
port map (
D(0) => gray2bin(2),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_axi_quad_spi_flash_0_synchronizer_ff__parameterized3_28\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
ext_spi_clk => ext_spi_clk,
\out\(3 downto 0) => p_6_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \_inferred__2/i__n_0\,
Q => ram_full_fb_i_reg(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \_inferred__3/i__n_0\,
Q => ram_full_fb_i_reg(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => ram_full_fb_i_reg(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(3),
Q => ram_full_fb_i_reg(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc1.count_d2_reg[2]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc1.count_d2_reg[2]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc1.count_d2_reg[2]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(0),
I1 => \gic0.gc1.count_d3_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(1),
I1 => \gic0.gc1.count_d3_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc1.count_d3_reg[3]\(2),
I1 => \gic0.gc1.count_d3_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc1.count_d3_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BAABAAAAAAAABAAB"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => ram_empty_i_i_3_n_0,
I2 => Q(0),
I3 => p_22_out(0),
I4 => Q(1),
I5 => p_22_out(1),
O => ram_empty_i0
);
ram_empty_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"4100004100000000"
)
port map (
I0 => ram_empty_i_i_4_n_0,
I1 => p_22_out(0),
I2 => \gc1.count_d1_reg[3]\(0),
I3 => p_22_out(1),
I4 => \gc1.count_d1_reg[3]\(1),
I5 => E(0),
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
I2 => p_22_out(2),
I3 => Q(2),
O => ram_empty_i_i_3_n_0
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(3),
I1 => \gc1.count_d1_reg[3]\(3),
I2 => p_22_out(2),
I3 => \gc1.count_d1_reg[3]\(2),
O => ram_empty_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11_synth is
port (
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ : out STD_LOGIC;
\qspi_cntrl_ps_reg[0]\ : out STD_LOGIC;
SPISR_0_CMD_Error_int : out STD_LOGIC;
QSPI_IO0_T : out STD_LOGIC;
transfer_start_reg : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
QSPI_IO1_T_0 : out STD_LOGIC;
\qspi_cntrl_ps_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\master_tri_state_en_control1__1\ : in STD_LOGIC;
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\ : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
CMD_decoded_int : in STD_LOGIC;
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\ : in STD_LOGIC;
empty_fwft_i_reg_0 : in STD_LOGIC;
spicr_8_tr_inhibit_to_spi_clk : in STD_LOGIC;
SPIXfer_done_int : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11_synth : entity is "dist_mem_gen_v8_0_11_synth";
end system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11_synth;
architecture STRUCTURE of system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11_synth is
begin
\gen_rom.rom_inst\: entity work.system_axi_quad_spi_flash_0_rom
port map (
CMD_decoded_int => CMD_decoded_int,
Q(6 downto 0) => Q(6 downto 0),
QSPI_IO0_T => QSPI_IO0_T,
QSPI_IO1_T => QSPI_IO1_T,
QSPI_IO1_T_0 => QSPI_IO1_T_0,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ => \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\,
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ => \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\,
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\ => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\,
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\ => \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\,
Rst_to_spi => Rst_to_spi,
SPISR_0_CMD_Error_int => SPISR_0_CMD_Error_int,
SPIXfer_done_int => SPIXfer_done_int,
empty_fwft_i_reg => empty_fwft_i_reg,
empty_fwft_i_reg_0 => empty_fwft_i_reg_0,
ext_spi_clk => ext_spi_clk,
\master_tri_state_en_control1__1\ => \master_tri_state_en_control1__1\,
\qspi_cntrl_ps_reg[0]\ => \qspi_cntrl_ps_reg[0]\,
\qspi_cntrl_ps_reg[2]\(2 downto 0) => \qspi_cntrl_ps_reg[2]\(2 downto 0),
spicr_8_tr_inhibit_to_spi_clk => spicr_8_tr_inhibit_to_spi_clk,
transfer_start_reg => transfer_start_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_memory is
port (
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ : out STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ : out STD_LOGIC;
\mode_0__0\ : in STD_LOGIC;
\mode_1__0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
I93 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gc1.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
L : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_memory : entity is "memory";
end system_axi_quad_spi_flash_0_memory;
architecture STRUCTURE of system_axi_quad_spi_flash_0_memory is
signal \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
begin
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0) <= \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(7 downto 0);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEF20E02"
)
port map (
I0 => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(7),
I1 => \mode_0__0\,
I2 => \mode_1__0\,
I3 => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(6),
I4 => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(4),
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\
);
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(7),
I1 => \mode_0__0\,
I2 => \mode_1__0\,
I3 => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(5),
O => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\
);
\gdm.dm_gen.dm\: entity work.system_axi_quad_spi_flash_0_dmem
port map (
AR(0) => AR(0),
E(0) => E(0),
I93 => I93,
L(3 downto 0) => L(3 downto 0),
Q(7) => \gdm.dm_gen.dm_n_0\,
Q(6) => \gdm.dm_gen.dm_n_1\,
Q(5) => \gdm.dm_gen.dm_n_2\,
Q(4) => \gdm.dm_gen.dm_n_3\,
Q(3) => \gdm.dm_gen.dm_n_4\,
Q(2) => \gdm.dm_gen.dm_n_5\,
Q(1) => \gdm.dm_gen.dm_n_6\,
Q(0) => \gdm.dm_gen.dm_n_7\,
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(0)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(1)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(2)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(3)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(4)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(5)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(6)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \^qspi_look_up_mode_2_memory_1.txfifo_addr_bits_generate[0].txfifo_first_entry_reg_i\(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_memory_13 is
port (
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_15_in : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in35_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
L : in STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gpregsm1.curr_fwft_state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_memory_13 : entity is "memory";
end system_axi_quad_spi_flash_0_memory_13;
architecture STRUCTURE of system_axi_quad_spi_flash_0_memory_13 is
signal data_from_rx_fifo : STD_LOGIC_VECTOR ( 4 to 6 );
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
begin
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[28]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => data_from_rx_fifo(4),
I1 => p_15_in,
I2 => bus2ip_rdce_int(0),
I3 => spicr_3_cpol_frm_axi_clk,
I4 => p_1_in29_in,
I5 => irpt_rdack144_out,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[29]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => data_from_rx_fifo(5),
I1 => p_15_in,
I2 => bus2ip_rdce_int(0),
I3 => spicr_2_mst_n_slv_frm_axi_clk,
I4 => p_1_in32_in,
I5 => irpt_rdack144_out,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[30]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => data_from_rx_fifo(6),
I1 => p_15_in,
I2 => spicr_1_spe_frm_axi_clk,
I3 => bus2ip_rdce_int(0),
I4 => p_1_in35_in,
I5 => irpt_rdack144_out,
O => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\
);
\gdm.dm_gen.dm\: entity work.system_axi_quad_spi_flash_0_dmem_19
port map (
AR(0) => AR(0),
E(0) => E(0),
L(3 downto 0) => L(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0),
ext_spi_clk => ext_spi_clk,
\goreg_dm.dout_i_reg[7]\(7) => \gdm.dm_gen.dm_n_0\,
\goreg_dm.dout_i_reg[7]\(6) => \gdm.dm_gen.dm_n_1\,
\goreg_dm.dout_i_reg[7]\(5) => \gdm.dm_gen.dm_n_2\,
\goreg_dm.dout_i_reg[7]\(4) => \gdm.dm_gen.dm_n_3\,
\goreg_dm.dout_i_reg[7]\(3) => \gdm.dm_gen.dm_n_4\,
\goreg_dm.dout_i_reg[7]\(2) => \gdm.dm_gen.dm_n_5\,
\goreg_dm.dout_i_reg[7]\(1) => \gdm.dm_gen.dm_n_6\,
\goreg_dm.dout_i_reg[7]\(0) => \gdm.dm_gen.dm_n_7\,
ram_empty_fb_i_reg(0) => ram_empty_fb_i_reg(0),
s_axi_aclk => s_axi_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(0)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_6\,
Q => data_from_rx_fifo(6)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_5\,
Q => data_from_rx_fifo(5)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_4\,
Q => data_from_rx_fifo(4)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(1)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(2)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(3)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \gpregsm1.curr_fwft_state_reg[0]\(0),
CLR => AR(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rd_logic is
port (
\out\ : out STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty_fwft_fb_i_reg : out STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : out STD_LOGIC;
empty_fwft_fb_o_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
QSPI_IO1_T : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc1.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i0 : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
empty_fwft_i0 : in STD_LOGIC;
empty_fwft_fb_o_i0 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_d1 : in STD_LOGIC;
transfer_start : in STD_LOGIC;
SPIXfer_done_int_pulse_d2 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
SPIXfer_done_rd_tx_en : in STD_LOGIC;
SPIXfer_done_int_pulse_d2_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rd_logic : entity is "rd_logic";
end system_axi_quad_spi_flash_0_rd_logic;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rd_logic is
signal \^out\ : STD_LOGIC;
begin
\out\ <= \^out\;
\gr1.gr1_int.rfwft\: entity work.system_axi_quad_spi_flash_0_rd_fwft
port map (
AR(0) => AR(0),
D(0) => D(0),
E(0) => E(0),
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\,
Q(0) => Q(0),
QSPI_IO1_T => QSPI_IO1_T,
SPIXfer_done_int_pulse_d2 => SPIXfer_done_int_pulse_d2,
SPIXfer_done_rd_tx_en => SPIXfer_done_rd_tx_en,
empty_fwft_fb_i_reg_0 => empty_fwft_fb_i_reg,
empty_fwft_fb_o_i0 => empty_fwft_fb_o_i0,
empty_fwft_fb_o_i_reg_0 => empty_fwft_fb_o_i_reg,
empty_fwft_i0 => empty_fwft_i0,
ext_spi_clk => ext_spi_clk,
\out\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
ram_empty_fb_i_reg => \^out\,
transfer_start => transfer_start,
transfer_start_d1 => transfer_start_d1
);
\gras.rsts\: entity work.system_axi_quad_spi_flash_0_rd_status_flags_as
port map (
AR(0) => AR(0),
ext_spi_clk => ext_spi_clk,
\out\ => \^out\,
ram_empty_i0 => ram_empty_i0
);
rpntr: entity work.system_axi_quad_spi_flash_0_rd_bin_cntr
port map (
AR(0) => AR(0),
SPIXfer_done_int_pulse_d2_reg(0) => SPIXfer_done_int_pulse_d2_reg(0),
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]_0\(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_rd_logic_11 is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gpr1.dout_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc1.count_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gc1.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_rd_logic_11 : entity is "rd_logic";
end system_axi_quad_spi_flash_0_rd_logic_11;
architecture STRUCTURE of system_axi_quad_spi_flash_0_rd_logic_11 is
signal \^gc1.count_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_2_out : STD_LOGIC;
begin
\gc1.count_reg[3]\(0) <= \^gc1.count_reg[3]\(0);
\gr1.gr1_int.rfwft\: entity work.system_axi_quad_spi_flash_0_rd_fwft_22
port map (
AR(0) => AR(0),
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
\gc1.count_reg[3]\(0) => \^gc1.count_reg[3]\(0),
\gpr1.dout_i_reg[0]\(0) => \gpr1.dout_i_reg[0]\(0),
\out\ => \out\,
p_5_in => p_5_in,
ram_empty_fb_i_reg => p_2_out,
s_axi_aclk => s_axi_aclk
);
\gras.rsts\: entity work.system_axi_quad_spi_flash_0_rd_status_flags_as_23
port map (
AR(0) => AR(0),
\out\ => p_2_out,
ram_empty_i0 => ram_empty_i0,
s_axi_aclk => s_axi_aclk
);
rpntr: entity work.system_axi_quad_spi_flash_0_rd_bin_cntr_24
port map (
AR(0) => AR(0),
E(0) => \^gc1.count_reg[3]\(0),
Q(3 downto 0) => Q(3 downto 0),
\gc1.count_d2_reg[3]_0\(3 downto 0) => \gc1.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc1.count_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_i_reg : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end system_axi_quad_spi_flash_0_reset_blk_ramfifo;
architecture STRUCTURE of system_axi_quad_spi_flash_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc1.count_reg[0]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_axi_quad_spi_flash_0_synchronizer_ff
port map (
ext_spi_clk => ext_spi_clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_axi_quad_spi_flash_0_synchronizer_ff_3
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_axi_quad_spi_flash_0_synchronizer_ff_4
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
ext_spi_clk => ext_spi_clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_axi_quad_spi_flash_0_synchronizer_ff_5
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => reset_TxFIFO_ptr_int,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => rst_rd_reg1,
PRE => reset_TxFIFO_ptr_int,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => reset_TxFIFO_ptr_int,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => reset_TxFIFO_ptr_int,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_reset_blk_ramfifo_14 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc1.count_reg[0]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_reset_blk_ramfifo_14 : entity is "reset_blk_ramfifo";
end system_axi_quad_spi_flash_0_reset_blk_ramfifo_14;
architecture STRUCTURE of system_axi_quad_spi_flash_0_reset_blk_ramfifo_14 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc1.count_reg[0]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_axi_quad_spi_flash_0_synchronizer_ff_15
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_axi_quad_spi_flash_0_synchronizer_ff_16
port map (
ext_spi_clk => ext_spi_clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_axi_quad_spi_flash_0_synchronizer_ff_17
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_axi_quad_spi_flash_0_synchronizer_ff_18
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
ext_spi_clk => ext_spi_clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => rx_fifo_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => rx_fifo_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => rx_fifo_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rx_fifo_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_wr_logic is
port (
\gic0.gc1.count_reg[3]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip_irpt_enable_reg_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\icount_out_reg[3]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[3]\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\IP2Bus_WrAck_transmit_enable__0\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_wr_logic : entity is "wr_logic";
end system_axi_quad_spi_flash_0_wr_logic;
architecture STRUCTURE of system_axi_quad_spi_flash_0_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gwas.wsts_n_1\ : STD_LOGIC;
signal wpntr_n_0 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_axi_quad_spi_flash_0_wr_status_flags_as
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => \^e\(0),
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
\gic0.gc1.count_d2_reg[3]\ => wpntr_n_0,
\gic0.gc1.count_reg[3]\ => \gic0.gc1.count_reg[3]\,
\goreg_dm.dout_i_reg[3]\ => \goreg_dm.dout_i_reg[3]\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\ip_irpt_enable_reg_reg[3]\(0) => \ip_irpt_enable_reg_reg[3]\(0),
\out\ => \gwas.wsts_n_1\,
p_6_in => p_6_in,
s_axi_aclk => s_axi_aclk
);
wpntr: entity work.system_axi_quad_spi_flash_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
Q(3 downto 0) => Q(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \gwas.wsts_n_1\,
ram_full_i_reg => wpntr_n_0,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_wr_logic_12 is
port (
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ext_spi_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
scndry_out : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_wr_logic_12 : entity is "wr_logic";
end system_axi_quad_spi_flash_0_wr_logic_12;
architecture STRUCTURE of system_axi_quad_spi_flash_0_wr_logic_12 is
signal \^ram_full_fb_i_reg\ : STD_LOGIC;
signal wpntr_n_0 : STD_LOGIC;
begin
ram_full_fb_i_reg <= \^ram_full_fb_i_reg\;
\gwas.wsts\: entity work.system_axi_quad_spi_flash_0_wr_status_flags_as_20
port map (
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\,
ext_spi_clk => ext_spi_clk,
\out\ => \out\,
ram_full_fb_i_reg_0 => \^ram_full_fb_i_reg\,
ram_full_fb_i_reg_1 => wpntr_n_0,
scndry_out => scndry_out
);
wpntr: entity work.system_axi_quad_spi_flash_0_wr_bin_cntr_21
port map (
AR(0) => AR(0),
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
ext_spi_clk => ext_spi_clk,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
ram_full_fb_i_reg => wpntr_n_0,
ram_full_fb_i_reg_0 => \^ram_full_fb_i_reg\,
spiXfer_done_int => spiXfer_done_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_slave_attachment is
port (
bus2ip_rnw_i_reg_0 : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\ : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ : out STD_LOGIC;
p_4_in : out STD_LOGIC;
Receive_ip2bus_error_reg : out STD_LOGIC;
Transmit_ip2bus_error_reg : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_0\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_1\ : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
wr_ce_or_reduce_core_cmb : out STD_LOGIC;
bus2ip_wrce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
SPICR_data_int_reg0 : out STD_LOGIC;
reset2ip_reset_int : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
p_15_in : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[26]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\ : out STD_LOGIC;
bus2ip_rdce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\p_39_out__0\ : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Receive_ip2bus_error0 : out STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : out STD_LOGIC;
Transmit_ip2bus_error0 : out STD_LOGIC;
IP2Bus_Error_1 : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ : out STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : out STD_LOGIC;
rd_ce_or_reduce_core_cmb : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
intr_controller_rd_ce_or_reduce : out STD_LOGIC;
intr_controller_wr_ce_or_reduce : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg_0 : out STD_LOGIC;
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_aclk : in STD_LOGIC;
IP2Bus_Error : in STD_LOGIC;
ip2Bus_WrAck_core_reg_d1 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
p_15_out : in STD_LOGIC;
p_16_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\out\ : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_1_in23_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
\ip_irpt_enable_reg_reg[10]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_1_in14_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : in STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
p_1_in29_in : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
rx_fifo_empty_i : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
p_10_out : in STD_LOGIC;
p_11_out : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
SPISR_2_MSB_Error_int : in STD_LOGIC;
SPISR_1_LOOP_Back_Error_int : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\ : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_slave_attachment : entity is "slave_attachment";
end system_axi_quad_spi_flash_0_slave_attachment;
architecture STRUCTURE of system_axi_quad_spi_flash_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^legacy_md_wr_rd_ack_gen.ip2bus_error_reg\ : STD_LOGIC;
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[5]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[6]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[2]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[3]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[4]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[5]\ : STD_LOGIC;
signal \bus2ip_addr_i_reg_n_0_[6]\ : STD_LOGIC;
signal bus2ip_be_int : STD_LOGIC_VECTOR ( 3 to 3 );
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal \^bus2ip_rnw_i_reg_0\ : STD_LOGIC;
signal bus2ip_rnw_i_reg_n_0 : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^reset2ip_reset_int\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \s_axi_bresp_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair14";
begin
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg\ <= \^legacy_md_wr_rd_ack_gen.ip2bus_error_reg\;
bus2ip_rnw_i_reg_0 <= \^bus2ip_rnw_i_reg_0\;
reset2ip_reset_int <= \^reset2ip_reset_int\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bresp(0) <= \^s_axi_bresp\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
O => plusOp(4)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
O => plusOp(5)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(4),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(5),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
R => clear
);
I_DECODER: entity work.system_axi_quad_spi_flash_0_address_decoder
port map (
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
D(5 downto 0) => D(5 downto 0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0),
IP2Bus_Error_1 => IP2Bus_Error_1,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[26]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[26]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_0\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_0\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_1\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_1\,
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ => \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\,
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ => \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\,
Q(4) => \bus2ip_addr_i_reg_n_0_[6]\,
Q(3) => \bus2ip_addr_i_reg_n_0_[5]\,
Q(2) => \bus2ip_addr_i_reg_n_0_[4]\,
Q(1) => \bus2ip_addr_i_reg_n_0_[3]\,
Q(0) => \bus2ip_addr_i_reg_n_0_[2]\,
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Receive_ip2bus_error_reg => Receive_ip2bus_error_reg,
SPICR_data_int_reg0 => SPICR_data_int_reg0,
SPISR_1_LOOP_Back_Error_int => SPISR_1_LOOP_Back_Error_int,
SPISR_2_MSB_Error_int => SPISR_2_MSB_Error_int,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => Transmit_ip2bus_error0,
Transmit_ip2bus_error_reg => Transmit_ip2bus_error_reg,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
bus2ip_be_int(0) => bus2ip_be_int(3),
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
bus2ip_rnw_i_reg => bus2ip_rnw_i_reg_n_0,
bus2ip_rnw_i_reg_0 => \^legacy_md_wr_rd_ack_gen.ip2bus_error_reg\,
bus2ip_wrce_int(0) => bus2ip_wrce_int(0),
empty_fwft_i_reg => empty_fwft_i_reg,
\goreg_dm.dout_i_reg[7]\(1 downto 0) => Q(1 downto 0),
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
intr_controller_wr_ce_or_reduce => intr_controller_wr_ce_or_reduce,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
\ip_irpt_enable_reg_reg[10]\(4 downto 0) => \ip_irpt_enable_reg_reg[10]\(4 downto 0),
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => ipif_glbl_irpt_enable_reg_reg,
ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg_0,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
\out\ => \out\,
p_10_out => p_10_out,
p_11_out => p_11_out,
p_15_in => p_15_in,
p_15_out => p_15_out,
p_16_out => p_16_out,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in23_in => p_1_in23_in,
p_1_in29_in => p_1_in29_in,
p_1_in8_in => p_1_in8_in,
\p_39_out__0\ => \p_39_out__0\,
p_4_in => p_4_in,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
reset2ip_reset_int => \^reset2ip_reset_int\,
reset_trig0 => reset_trig0,
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(4 downto 1) => s_axi_wdata(6 downto 3),
s_axi_wdata(0) => s_axi_wdata(0),
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(0) => s_axi_wstrb(1),
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
start2 => start2,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bus2ip_rnw_i_reg_n_0,
I1 => s_axi_wstrb(1),
O => bus2ip_be_int(3)
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF1FFFFFF"
)
port map (
I0 => bus2ip_rnw_i_reg_n_0,
I1 => s_axi_wstrb(0),
I2 => s_axi_wdata(2),
I3 => s_axi_wdata(3),
I4 => s_axi_wdata(1),
I5 => s_axi_wdata(0),
O => \^legacy_md_wr_rd_ack_gen.ip2bus_error_reg\
);
RESET_SYNC_AX2S_1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bus2ip_rnw_i_reg_0\,
I1 => \RESET_FLOPS[15].RST_FLOPS\,
O => \^reset2ip_reset_int\
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(0),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(1),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(2),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(3),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(3),
O => \bus2ip_addr_i[5]_i_1_n_0\
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(4),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(4),
O => \bus2ip_addr_i[6]_i_1_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[2]\,
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[3]\,
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[4]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[4]\,
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[5]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[5]\,
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[6]_i_1_n_0\,
Q => \bus2ip_addr_i_reg_n_0_[6]\,
R => \^bus2ip_rnw_i_reg_0\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => bus2ip_rnw_i_reg_n_0,
R => \^bus2ip_rnw_i_reg_0\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^bus2ip_rnw_i_reg_0\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^bus2ip_rnw_i_reg_0\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_0_in1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in1_in,
Q => \^bus2ip_rnw_i_reg_0\,
R => '0'
);
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => IP2Bus_Error,
I1 => state(1),
I2 => state(0),
I3 => \^s_axi_bresp\(0),
O => \s_axi_bresp_i[1]_i_1_n_0\
);
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_bresp_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => \^bus2ip_rnw_i_reg_0\
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(0),
Q => s_axi_rdata(0),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(10),
Q => s_axi_rdata(10),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(11),
Q => s_axi_rdata(11),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(12),
Q => s_axi_rdata(12),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(13),
Q => s_axi_rdata(13),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(1),
Q => s_axi_rdata(1),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(2),
Q => s_axi_rdata(2),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(14),
Q => s_axi_rdata(14),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(3),
Q => s_axi_rdata(3),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(4),
Q => s_axi_rdata(4),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(5),
Q => s_axi_rdata(5),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(6),
Q => s_axi_rdata(6),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(7),
Q => s_axi_rdata(7),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(8),
Q => s_axi_rdata(8),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(9),
Q => s_axi_rdata(9),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Error,
Q => s_axi_rresp(0),
R => \^bus2ip_rnw_i_reg_0\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^bus2ip_rnw_i_reg_0\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^bus2ip_rnw_i_reg_0\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3AFF3AF0"
)
port map (
I0 => \^s_axi_wready\,
I1 => \state[1]_i_2_n_0\,
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3AF03AFF3AF03AF0"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => s_axi_arvalid,
I5 => \state[1]_i_3_n_0\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^bus2ip_rnw_i_reg_0\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^bus2ip_rnw_i_reg_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11 is
port (
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ : out STD_LOGIC;
\qspi_cntrl_ps_reg[0]\ : out STD_LOGIC;
SPISR_0_CMD_Error_int : out STD_LOGIC;
QSPI_IO0_T : out STD_LOGIC;
transfer_start_reg : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
QSPI_IO1_T_0 : out STD_LOGIC;
\qspi_cntrl_ps_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\master_tri_state_en_control1__1\ : in STD_LOGIC;
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\ : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
CMD_decoded_int : in STD_LOGIC;
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\ : in STD_LOGIC;
empty_fwft_i_reg_0 : in STD_LOGIC;
spicr_8_tr_inhibit_to_spi_clk : in STD_LOGIC;
SPIXfer_done_int : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\ : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11 : entity is "dist_mem_gen_v8_0_11";
end system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11;
architecture STRUCTURE of system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11 is
begin
\synth_options.dist_mem_inst\: entity work.system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11_synth
port map (
CMD_decoded_int => CMD_decoded_int,
Q(6 downto 0) => Q(6 downto 0),
QSPI_IO0_T => QSPI_IO0_T,
QSPI_IO1_T => QSPI_IO1_T,
QSPI_IO1_T_0 => QSPI_IO1_T_0,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ => \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\,
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ => \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\,
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\ => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\,
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\ => \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\,
Rst_to_spi => Rst_to_spi,
SPISR_0_CMD_Error_int => SPISR_0_CMD_Error_int,
SPIXfer_done_int => SPIXfer_done_int,
empty_fwft_i_reg => empty_fwft_i_reg,
empty_fwft_i_reg_0 => empty_fwft_i_reg_0,
ext_spi_clk => ext_spi_clk,
\master_tri_state_en_control1__1\ => \master_tri_state_en_control1__1\,
\qspi_cntrl_ps_reg[0]\ => \qspi_cntrl_ps_reg[0]\,
\qspi_cntrl_ps_reg[2]\(2 downto 0) => \qspi_cntrl_ps_reg[2]\(2 downto 0),
spicr_8_tr_inhibit_to_spi_clk => spicr_8_tr_inhibit_to_spi_clk,
transfer_start_reg => transfer_start_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_fifo_generator_ramfifo is
port (
\out\ : out STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty_fwft_fb_i_reg : out STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : out STD_LOGIC;
empty_fwft_fb_o_i_reg : out STD_LOGIC;
\gic0.gc1.count_reg[3]\ : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ : out STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
empty_fwft_i0 : in STD_LOGIC;
empty_fwft_fb_o_i0 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_d1 : in STD_LOGIC;
transfer_start : in STD_LOGIC;
SPIXfer_done_int_pulse_d2 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip_irpt_enable_reg_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\icount_out_reg[3]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[3]\ : in STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
SPIXfer_done_rd_tx_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\mode_0__0\ : in STD_LOGIC;
\mode_1__0\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end system_axi_quad_spi_flash_0_fifo_generator_ramfifo;
architecture STRUCTURE of system_axi_quad_spi_flash_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_10\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_8\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_9\ : STD_LOGIC;
signal \gras.rsts/ram_empty_i0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_23_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rstblk_n_6 : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_axi_quad_spi_flash_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_8\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_9\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_10\,
E(0) => E(0),
Q(3 downto 0) => p_0_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
ext_spi_clk => ext_spi_clk,
\gc1.count_d1_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gic0.gc1.count_d3_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_5_out(3 downto 0),
ram_empty_i0 => \gras.rsts/ram_empty_i0\,
ram_full_i_reg(3 downto 0) => p_23_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_5_out(1),
I1 => p_5_out(0),
I2 => p_5_out(3),
I3 => p_5_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_axi_quad_spi_flash_0_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(0) => D(0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\,
Q(0) => Q(0),
QSPI_IO1_T => QSPI_IO1_T,
SPIXfer_done_int_pulse_d2 => SPIXfer_done_int_pulse_d2,
SPIXfer_done_int_pulse_d2_reg(0) => E(0),
SPIXfer_done_rd_tx_en => SPIXfer_done_rd_tx_en,
empty_fwft_fb_i_reg => empty_fwft_fb_i_reg,
empty_fwft_fb_o_i0 => empty_fwft_fb_o_i0,
empty_fwft_fb_o_i_reg => empty_fwft_fb_o_i_reg,
empty_fwft_i0 => empty_fwft_i0,
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_8\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_9\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_10\,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
\out\ => \out\,
ram_empty_i0 => \gras.rsts/ram_empty_i0\,
transfer_start => transfer_start,
transfer_start_d1 => transfer_start_d1
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_axi_quad_spi_flash_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
Bus_RNW_reg => Bus_RNW_reg,
E(0) => p_18_out,
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
Q(3 downto 0) => p_12_out(3 downto 0),
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
\gic0.gc1.count_reg[3]\ => \gic0.gc1.count_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => p_23_out(3 downto 0),
\goreg_dm.dout_i_reg[3]\ => \goreg_dm.dout_i_reg[3]\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => rstblk_n_6,
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\ip_irpt_enable_reg_reg[3]\(0) => \ip_irpt_enable_reg_reg[3]\(0),
\out\ => rst_full_ff_i,
p_6_in => p_6_in,
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.mem\: entity work.system_axi_quad_spi_flash_0_memory
port map (
AR(0) => rd_rst_i(0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
I93 => p_18_out,
L(3 downto 0) => p_12_out(3 downto 0),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0) => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0),
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\,
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\,
ext_spi_clk => ext_spi_clk,
\gc1.count_d2_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
\mode_0__0\ => \mode_0__0\,
\mode_1__0\ => \mode_1__0\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
);
rstblk: entity work.system_axi_quad_spi_flash_0_reset_blk_ramfifo
port map (
ext_spi_clk => ext_spi_clk,
\gc1.count_reg[0]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_i_reg => rstblk_n_6,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_fifo_generator_ramfifo_9 is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
p_15_in : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in35_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_fifo_generator_ramfifo_9 : entity is "fifo_generator_ramfifo";
end system_axi_quad_spi_flash_0_fifo_generator_ramfifo_9;
architecture STRUCTURE of system_axi_quad_spi_flash_0_fifo_generator_ramfifo_9 is
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gras.rsts/ram_empty_i0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC;
signal p_5_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_7_out : STD_LOGIC;
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rstblk_n_6 : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_axi_quad_spi_flash_0_clk_x_pntrs_10
port map (
AR(0) => wr_rst_i(0),
D(0) => gray2bin(0),
E(0) => p_7_out,
Q(3 downto 0) => p_0_out(3 downto 0),
ext_spi_clk => ext_spi_clk,
\gc1.count_d1_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gc1.count_d2_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\gc1.count_d2_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gc1.count_d2_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gic0.gc1.count_d3_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_5_out_0(3 downto 0),
ram_empty_i0 => \gras.rsts/ram_empty_i0\,
ram_full_fb_i_reg(3 downto 0) => p_23_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_5_out_0(1),
I1 => p_5_out_0(0),
I2 => p_5_out_0(3),
I3 => p_5_out_0(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_axi_quad_spi_flash_0_rd_logic_11
port map (
AR(0) => rd_rst_i(2),
Bus_RNW_reg => Bus_RNW_reg,
E(0) => p_5_out,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(3 downto 0) => p_0_out(3 downto 0),
\gc1.count_d2_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gc1.count_reg[3]\(0) => p_7_out,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gpr1.dout_i_reg[0]\(0) => ram_rd_en_i,
\out\ => \out\,
p_5_in => p_5_in,
ram_empty_i0 => \gras.rsts/ram_empty_i0\,
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_axi_quad_spi_flash_0_wr_logic_12
port map (
AR(0) => wr_rst_i(1),
E(0) => E(0),
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\,
Q(3 downto 0) => p_12_out(3 downto 0),
ext_spi_clk => ext_spi_clk,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => p_23_out(3 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => rstblk_n_6,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => ram_full_fb_i_reg,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int
);
\gntv_or_sync_fifo.mem\: entity work.system_axi_quad_spi_flash_0_memory_13
port map (
AR(0) => rd_rst_i(0),
E(0) => E(0),
L(3 downto 0) => p_12_out(3 downto 0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\(4 downto 0) => Q(4 downto 0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\,
Q(3 downto 0) => p_0_out(3 downto 0),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0),
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
ext_spi_clk => ext_spi_clk,
\gpregsm1.curr_fwft_state_reg[0]\(0) => p_5_out,
irpt_rdack144_out => irpt_rdack144_out,
p_15_in => p_15_in,
p_1_in29_in => p_1_in29_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
ram_empty_fb_i_reg(0) => ram_rd_en_i,
s_axi_aclk => s_axi_aclk,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk
);
rstblk: entity work.system_axi_quad_spi_flash_0_reset_blk_ramfifo_14
port map (
ext_spi_clk => ext_spi_clk,
\gc1.count_reg[0]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => rstblk_n_6,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_axi_lite_ipif is
port (
bus2ip_reset_ipif_inverted : out STD_LOGIC;
p_2_in : out STD_LOGIC;
p_3_in : out STD_LOGIC;
p_4_in : out STD_LOGIC;
p_5_in : out STD_LOGIC;
p_6_in : out STD_LOGIC;
p_7_in : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
wr_ce_or_reduce_core_cmb : out STD_LOGIC;
bus2ip_wrce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
SPICR_data_int_reg0 : out STD_LOGIC;
reset2ip_reset_int : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
intr2bus_rdack0 : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
p_15_in : out STD_LOGIC;
irpt_rdack144_out : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\ : out STD_LOGIC;
bus2ip_rdce_int : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\p_39_out__0\ : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
irpt_wrack : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Receive_ip2bus_error0 : out STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : out STD_LOGIC;
Transmit_ip2bus_error0 : out STD_LOGIC;
IP2Bus_Error_1 : out STD_LOGIC;
\data_is_non_reset_match__4\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ : out STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : out STD_LOGIC;
rd_ce_or_reduce_core_cmb : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
intr_controller_rd_ce_or_reduce : out STD_LOGIC;
intr_controller_wr_ce_or_reduce : out STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : out STD_LOGIC;
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_aclk : in STD_LOGIC;
IP2Bus_Error : in STD_LOGIC;
ip2Bus_WrAck_core_reg_d1 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
p_15_out : in STD_LOGIC;
p_16_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\out\ : in STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : in STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : in STD_LOGIC;
ipif_glbl_irpt_enable_reg : in STD_LOGIC;
irpt_rdack_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
p_1_in23_in : in STD_LOGIC;
p_1_in17_in : in STD_LOGIC;
\ip_irpt_enable_reg_reg[10]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_1_in14_in : in STD_LOGIC;
p_1_in11_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ : in STD_LOGIC;
p_1_in8_in : in STD_LOGIC;
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : in STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
p_1_in29_in : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
rx_fifo_empty_i : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
p_10_out : in STD_LOGIC;
p_11_out : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
SPISR_2_MSB_Error_int : in STD_LOGIC;
SPISR_1_LOOP_Back_Error_int : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\ : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_quad_spi_flash_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_quad_spi_flash_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_quad_spi_flash_0_slave_attachment
port map (
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
D(5 downto 0) => D(5 downto 0),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Error_1 => IP2Bus_Error_1,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(14 downto 0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(14 downto 0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\ => bus2ip_rdce_int(0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[26]\ => irpt_rdack144_out,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg\ => \data_is_non_reset_match__4\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\ => p_2_in,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ => p_3_in,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_0\ => p_7_in,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg_1\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\,
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ => \LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\,
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ => \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\,
Q(1 downto 0) => Q(1 downto 0),
\RESET_FLOPS[15].RST_FLOPS\ => \RESET_FLOPS[15].RST_FLOPS\,
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Receive_ip2bus_error_reg => p_5_in,
SPICR_data_int_reg0 => SPICR_data_int_reg0,
SPISR_1_LOOP_Back_Error_int => SPISR_1_LOOP_Back_Error_int,
SPISR_2_MSB_Error_int => SPISR_2_MSB_Error_int,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => Transmit_ip2bus_error0,
Transmit_ip2bus_error_reg => p_6_in,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
bus2ip_rdce_int(0) => bus2ip_rdce_int(1),
bus2ip_rnw_i_reg_0 => bus2ip_reset_ipif_inverted,
bus2ip_wrce_int(0) => bus2ip_wrce_int(0),
empty_fwft_i_reg => empty_fwft_i_reg,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
intr_controller_wr_ce_or_reduce => intr_controller_wr_ce_or_reduce,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
\ip_irpt_enable_reg_reg[10]\(4 downto 0) => \ip_irpt_enable_reg_reg[10]\(4 downto 0),
ipif_glbl_irpt_enable_reg => ipif_glbl_irpt_enable_reg,
ipif_glbl_irpt_enable_reg_reg => Bus_RNW_reg,
ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
\out\ => \out\,
p_10_out => p_10_out,
p_11_out => p_11_out,
p_15_in => p_15_in,
p_15_out => p_15_out,
p_16_out => p_16_out,
p_1_in11_in => p_1_in11_in,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => p_1_in17_in,
p_1_in23_in => p_1_in23_in,
p_1_in29_in => p_1_in29_in,
p_1_in8_in => p_1_in8_in,
\p_39_out__0\ => \p_39_out__0\,
p_4_in => p_4_in,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
reset2ip_reset_int => reset2ip_reset_int,
reset_trig0 => reset_trig0,
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(14 downto 0) => s_axi_rdata(14 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(1 downto 0) => s_axi_wstrb(1 downto 0),
s_axi_wvalid => s_axi_wvalid,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_qspi_look_up_logic is
port (
DTR_FIFO_Data_Exists_d1 : out STD_LOGIC;
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 6 downto 0 );
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ : out STD_LOGIC;
\qspi_cntrl_ps_reg[0]\ : out STD_LOGIC;
SPISR_0_CMD_Error_int : out STD_LOGIC;
QSPI_IO0_T : out STD_LOGIC;
transfer_start_reg : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
QSPI_IO1_T_0 : out STD_LOGIC;
R : in STD_LOGIC;
\qspi_cntrl_ps_reg[1]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
empty_fwft_i_reg : in STD_LOGIC;
\qspi_cntrl_ps_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\master_tri_state_en_control1__1\ : in STD_LOGIC;
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\ : in STD_LOGIC;
empty_fwft_i_reg_0 : in STD_LOGIC;
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\ : in STD_LOGIC;
empty_fwft_i_reg_1 : in STD_LOGIC;
spicr_8_tr_inhibit_to_spi_clk : in STD_LOGIC;
SPIXfer_done_int : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_qspi_look_up_logic : entity is "qspi_look_up_logic";
end system_axi_quad_spi_flash_0_qspi_look_up_logic;
architecture STRUCTURE of system_axi_quad_spi_flash_0_qspi_look_up_logic is
signal CMD_decoded_int : STD_LOGIC;
signal CMD_decoded_int_d1 : STD_LOGIC;
signal \^dtr_fifo_data_exists_d1\ : STD_LOGIC;
signal \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\ : STD_LOGIC;
signal \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\ : STD_LOGIC;
signal \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\ : STD_LOGIC;
signal \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\ : STD_LOGIC;
signal \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\ : STD_LOGIC;
signal \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\ : STD_LOGIC;
signal \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\ : STD_LOGIC;
signal \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ : label is "PRIMITIVE";
attribute box_type of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I\ : label is "PRIMITIVE";
attribute box_type of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I\ : label is "PRIMITIVE";
attribute box_type of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I\ : label is "PRIMITIVE";
attribute box_type of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I\ : label is "PRIMITIVE";
attribute box_type of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I\ : label is "PRIMITIVE";
attribute box_type of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I\ : label is "PRIMITIVE";
attribute box_type of \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I\ : label is "PRIMITIVE";
begin
DTR_FIFO_Data_Exists_d1 <= \^dtr_fifo_data_exists_d1\;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.CMD_decoded_int_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^dtr_fifo_data_exists_d1\,
Q => CMD_decoded_int_d1,
R => Rst_to_spi
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.CMD_decoded_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => CMD_decoded_int_d1,
Q => CMD_decoded_int,
R => Rst_to_spi
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.DTR_FIFO_Data_Exists_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => empty_fwft_i_reg,
Q => \^dtr_fifo_data_exists_d1\,
R => Rst_to_spi
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => \qspi_cntrl_ps_reg[1]\,
D => \goreg_dm.dout_i_reg[7]\(7),
Q => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
R => R
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => \qspi_cntrl_ps_reg[1]\,
D => \goreg_dm.dout_i_reg[7]\(6),
Q => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
R => R
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => \qspi_cntrl_ps_reg[1]\,
D => \goreg_dm.dout_i_reg[7]\(5),
Q => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
R => R
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => \qspi_cntrl_ps_reg[1]\,
D => \goreg_dm.dout_i_reg[7]\(4),
Q => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
R => R
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => \qspi_cntrl_ps_reg[1]\,
D => \goreg_dm.dout_i_reg[7]\(3),
Q => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
R => R
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => \qspi_cntrl_ps_reg[1]\,
D => \goreg_dm.dout_i_reg[7]\(2),
Q => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
R => R
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => \qspi_cntrl_ps_reg[1]\,
D => \goreg_dm.dout_i_reg[7]\(1),
Q => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
R => R
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => \qspi_cntrl_ps_reg[1]\,
D => \goreg_dm.dout_i_reg[7]\(0),
Q => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
R => R
);
\QSPI_LOOK_UP_MODE_2_MEMORY_1.dist_mem_gen_QSPI_LOOK_UP_MODE_2_MEMORY_1.C_SPI_MODE_1_MIXED_ROM_I\: entity work.system_axi_quad_spi_flash_0_dist_mem_gen_v8_0_11
port map (
CMD_decoded_int => CMD_decoded_int,
Q(6 downto 0) => Q(6 downto 0),
QSPI_IO0_T => QSPI_IO0_T,
QSPI_IO1_T => QSPI_IO1_T,
QSPI_IO1_T_0 => QSPI_IO1_T_0,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[1].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[2].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[3].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[4].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[5].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[6].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\ => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[7].TXFIFO_FIRST_ENTRY_REG_I__0\,
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ => \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\,
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ => \QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\,
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\ => \QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\,
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\ => \RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\,
Rst_to_spi => Rst_to_spi,
SPISR_0_CMD_Error_int => SPISR_0_CMD_Error_int,
SPIXfer_done_int => SPIXfer_done_int,
empty_fwft_i_reg => empty_fwft_i_reg_0,
empty_fwft_i_reg_0 => empty_fwft_i_reg_1,
ext_spi_clk => ext_spi_clk,
\master_tri_state_en_control1__1\ => \master_tri_state_en_control1__1\,
\qspi_cntrl_ps_reg[0]\ => \qspi_cntrl_ps_reg[0]\,
\qspi_cntrl_ps_reg[2]\(2 downto 0) => \qspi_cntrl_ps_reg[2]\(2 downto 0),
spicr_8_tr_inhibit_to_spi_clk => spicr_8_tr_inhibit_to_spi_clk,
transfer_start_reg => transfer_start_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_fifo_generator_top is
port (
\out\ : out STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty_fwft_fb_i_reg : out STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : out STD_LOGIC;
empty_fwft_fb_o_i_reg : out STD_LOGIC;
\gic0.gc1.count_reg[3]\ : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ : out STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
empty_fwft_i0 : in STD_LOGIC;
empty_fwft_fb_o_i0 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_d1 : in STD_LOGIC;
transfer_start : in STD_LOGIC;
SPIXfer_done_int_pulse_d2 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip_irpt_enable_reg_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\icount_out_reg[3]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[3]\ : in STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
SPIXfer_done_rd_tx_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\mode_0__0\ : in STD_LOGIC;
\mode_1__0\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_fifo_generator_top : entity is "fifo_generator_top";
end system_axi_quad_spi_flash_0_fifo_generator_top;
architecture STRUCTURE of system_axi_quad_spi_flash_0_fifo_generator_top is
begin
\grf.rf\: entity work.system_axi_quad_spi_flash_0_fifo_generator_ramfifo
port map (
Bus_RNW_reg => Bus_RNW_reg,
D(0) => D(0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\,
Q(0) => Q(0),
QSPI_IO1_T => QSPI_IO1_T,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0) => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0),
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\,
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\,
SPIXfer_done_int_pulse_d2 => SPIXfer_done_int_pulse_d2,
SPIXfer_done_rd_tx_en => SPIXfer_done_rd_tx_en,
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
empty_fwft_fb_i_reg => empty_fwft_fb_i_reg,
empty_fwft_fb_o_i0 => empty_fwft_fb_o_i0,
empty_fwft_fb_o_i_reg => empty_fwft_fb_o_i_reg,
empty_fwft_i0 => empty_fwft_i0,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[3]\ => \gic0.gc1.count_reg[3]\,
\goreg_dm.dout_i_reg[3]\ => \goreg_dm.dout_i_reg[3]\,
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\ip_irpt_enable_reg_reg[3]\(0) => \ip_irpt_enable_reg_reg[3]\(0),
\mode_0__0\ => \mode_0__0\,
\mode_1__0\ => \mode_1__0\,
\out\ => \out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
transfer_start => transfer_start,
transfer_start_d1 => transfer_start_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_fifo_generator_top_8 is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
p_15_in : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in35_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_fifo_generator_top_8 : entity is "fifo_generator_top";
end system_axi_quad_spi_flash_0_fifo_generator_top_8;
architecture STRUCTURE of system_axi_quad_spi_flash_0_fifo_generator_top_8 is
begin
\grf.rf\: entity work.system_axi_quad_spi_flash_0_fifo_generator_ramfifo_9
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(4 downto 0) => Q(4 downto 0),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0),
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
ext_spi_clk => ext_spi_clk,
irpt_rdack144_out => irpt_rdack144_out,
\out\ => \out\,
p_15_in => p_15_in,
p_1_in29_in => p_1_in29_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_5_in => p_5_in,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth is
port (
\out\ : out STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty_fwft_fb_i_reg : out STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : out STD_LOGIC;
empty_fwft_fb_o_i_reg : out STD_LOGIC;
\gic0.gc1.count_reg[3]\ : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ : out STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
empty_fwft_i0 : in STD_LOGIC;
empty_fwft_fb_o_i0 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_d1 : in STD_LOGIC;
transfer_start : in STD_LOGIC;
SPIXfer_done_int_pulse_d2 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip_irpt_enable_reg_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\icount_out_reg[3]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[3]\ : in STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
SPIXfer_done_rd_tx_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\mode_0__0\ : in STD_LOGIC;
\mode_1__0\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.system_axi_quad_spi_flash_0_fifo_generator_top
port map (
Bus_RNW_reg => Bus_RNW_reg,
D(0) => D(0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\,
Q(0) => Q(0),
QSPI_IO1_T => QSPI_IO1_T,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0) => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0),
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\,
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\,
SPIXfer_done_int_pulse_d2 => SPIXfer_done_int_pulse_d2,
SPIXfer_done_rd_tx_en => SPIXfer_done_rd_tx_en,
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
empty_fwft_fb_i_reg => empty_fwft_fb_i_reg,
empty_fwft_fb_o_i0 => empty_fwft_fb_o_i0,
empty_fwft_fb_o_i_reg => empty_fwft_fb_o_i_reg,
empty_fwft_i0 => empty_fwft_i0,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[3]\ => \gic0.gc1.count_reg[3]\,
\goreg_dm.dout_i_reg[3]\ => \goreg_dm.dout_i_reg[3]\,
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\ip_irpt_enable_reg_reg[3]\(0) => \ip_irpt_enable_reg_reg[3]\(0),
\mode_0__0\ => \mode_0__0\,
\mode_1__0\ => \mode_1__0\,
\out\ => \out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
transfer_start => transfer_start,
transfer_start_d1 => transfer_start_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth_7 is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
p_15_in : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in35_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth_7 : entity is "fifo_generator_v13_1_3_synth";
end system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth_7;
architecture STRUCTURE of system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth_7 is
begin
\gconvfifo.rf\: entity work.system_axi_quad_spi_flash_0_fifo_generator_top_8
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(4 downto 0) => Q(4 downto 0),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0),
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
ext_spi_clk => ext_spi_clk,
irpt_rdack144_out => irpt_rdack144_out,
\out\ => \out\,
p_15_in => p_15_in,
p_1_in29_in => p_1_in29_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_5_in => p_5_in,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_fifo_generator_v13_1_3 is
port (
\out\ : out STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty_fwft_fb_i_reg : out STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : out STD_LOGIC;
empty_fwft_fb_o_i_reg : out STD_LOGIC;
\gic0.gc1.count_reg[3]\ : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ : out STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
empty_fwft_i0 : in STD_LOGIC;
empty_fwft_fb_o_i0 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_d1 : in STD_LOGIC;
transfer_start : in STD_LOGIC;
SPIXfer_done_int_pulse_d2 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip_irpt_enable_reg_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\icount_out_reg[3]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[3]\ : in STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
SPIXfer_done_rd_tx_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\mode_0__0\ : in STD_LOGIC;
\mode_1__0\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end system_axi_quad_spi_flash_0_fifo_generator_v13_1_3;
architecture STRUCTURE of system_axi_quad_spi_flash_0_fifo_generator_v13_1_3 is
begin
inst_fifo_gen: entity work.system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth
port map (
Bus_RNW_reg => Bus_RNW_reg,
D(0) => D(0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\,
Q(0) => Q(0),
QSPI_IO1_T => QSPI_IO1_T,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0) => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0),
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\,
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\,
SPIXfer_done_int_pulse_d2 => SPIXfer_done_int_pulse_d2,
SPIXfer_done_rd_tx_en => SPIXfer_done_rd_tx_en,
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
empty_fwft_fb_i_reg => empty_fwft_fb_i_reg,
empty_fwft_fb_o_i0 => empty_fwft_fb_o_i0,
empty_fwft_fb_o_i_reg => empty_fwft_fb_o_i_reg,
empty_fwft_i0 => empty_fwft_i0,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[3]\ => \gic0.gc1.count_reg[3]\,
\goreg_dm.dout_i_reg[3]\ => \goreg_dm.dout_i_reg[3]\,
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\ip_irpt_enable_reg_reg[3]\(0) => \ip_irpt_enable_reg_reg[3]\(0),
\mode_0__0\ => \mode_0__0\,
\mode_1__0\ => \mode_1__0\,
\out\ => \out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
transfer_start => transfer_start,
transfer_start_d1 => transfer_start_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_6 is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
p_15_in : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in35_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_6 : entity is "fifo_generator_v13_1_3";
end system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_6;
architecture STRUCTURE of system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_6 is
begin
inst_fifo_gen: entity work.system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_synth_7
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(4 downto 0) => Q(4 downto 0),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0),
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
ext_spi_clk => ext_spi_clk,
irpt_rdack144_out => irpt_rdack144_out,
\out\ => \out\,
p_15_in => p_15_in,
p_1_in29_in => p_1_in29_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_5_in => p_5_in,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_async_fifo_fg is
port (
\out\ : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rx_fifo_reset : in STD_LOGIC;
spiXfer_done_int : in STD_LOGIC;
scndry_out : in STD_LOGIC;
p_15_in : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in35_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
p_1_in32_in : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_async_fifo_fg : entity is "async_fifo_fg";
end system_axi_quad_spi_flash_0_async_fifo_fg;
architecture STRUCTURE of system_axi_quad_spi_flash_0_async_fifo_fg is
begin
\USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM\: entity work.system_axi_quad_spi_flash_0_fifo_generator_v13_1_3_6
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => E(0),
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ => \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\,
Q(4 downto 0) => Q(4 downto 0),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0) => \RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7 downto 0),
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
ext_spi_clk => ext_spi_clk,
irpt_rdack144_out => irpt_rdack144_out,
\out\ => \out\,
p_15_in => p_15_in,
p_1_in29_in => p_1_in29_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_5_in => p_5_in,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
spiXfer_done_int => spiXfer_done_int,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_async_fifo_fg_2 is
port (
\out\ : out STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
empty_fwft_fb_i_reg : out STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : out STD_LOGIC;
empty_fwft_fb_o_i_reg : out STD_LOGIC;
\gic0.gc1.count_reg[3]\ : out STD_LOGIC;
QSPI_IO1_T : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ : out STD_LOGIC;
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ : out STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
reset_TxFIFO_ptr_int : in STD_LOGIC;
empty_fwft_i0 : in STD_LOGIC;
empty_fwft_fb_o_i0 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_d1 : in STD_LOGIC;
transfer_start : in STD_LOGIC;
SPIXfer_done_int_pulse_d2 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
\ip_irpt_enable_reg_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
\icount_out_reg[3]\ : in STD_LOGIC;
\goreg_dm.dout_i_reg[3]\ : in STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : in STD_LOGIC;
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ : in STD_LOGIC;
p_6_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
SPIXfer_done_rd_tx_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\mode_0__0\ : in STD_LOGIC;
\mode_1__0\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_async_fifo_fg_2 : entity is "async_fifo_fg";
end system_axi_quad_spi_flash_0_async_fifo_fg_2;
architecture STRUCTURE of system_axi_quad_spi_flash_0_async_fifo_fg_2 is
begin
\USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM\: entity work.system_axi_quad_spi_flash_0_fifo_generator_v13_1_3
port map (
Bus_RNW_reg => Bus_RNW_reg,
D(0) => D(0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ => \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\,
Q(0) => Q(0),
QSPI_IO1_T => QSPI_IO1_T,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0) => \QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7 downto 0),
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\,
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ => \RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\,
SPIXfer_done_int_pulse_d2 => SPIXfer_done_int_pulse_d2,
SPIXfer_done_rd_tx_en => SPIXfer_done_rd_tx_en,
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
empty_fwft_fb_i_reg => empty_fwft_fb_i_reg,
empty_fwft_fb_o_i0 => empty_fwft_fb_o_i0,
empty_fwft_fb_o_i_reg => empty_fwft_fb_o_i_reg,
empty_fwft_i0 => empty_fwft_i0,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[3]\ => \gic0.gc1.count_reg[3]\,
\goreg_dm.dout_i_reg[3]\ => \goreg_dm.dout_i_reg[3]\,
\gpregsm1.curr_fwft_state_reg[1]\(1 downto 0) => \gpregsm1.curr_fwft_state_reg[1]\(1 downto 0),
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \gpregsm1.curr_fwft_state_reg[1]_0\(0),
\icount_out_reg[3]\ => \icount_out_reg[3]\,
\ip_irpt_enable_reg_reg[3]\(0) => \ip_irpt_enable_reg_reg[3]\(0),
\mode_0__0\ => \mode_0__0\,
\mode_1__0\ => \mode_1__0\,
\out\ => \out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
transfer_start => transfer_start,
transfer_start_d1 => transfer_start_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_qspi_core_interface is
port (
Tx_FIFO_Empty_SPISR_to_axi_clk : out STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : out STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : out STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : out STD_LOGIC;
SPISSR_frm_axi_clk : out STD_LOGIC;
\out\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[8]\ : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
\gic0.gc1.count_reg[3]\ : out STD_LOGIC;
ss_t : out STD_LOGIC;
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_t : out STD_LOGIC;
sck_o : out STD_LOGIC;
IP2Bus_Error : out STD_LOGIC;
SPISR_1_LOOP_Back_Error_int : out STD_LOGIC;
spicr_7_ss_frm_axi_clk : out STD_LOGIC;
SPISR_2_MSB_Error_int : out STD_LOGIC;
sw_rst_cond_d1 : out STD_LOGIC;
irpt_wrack_d1 : out STD_LOGIC;
p_1_in29_in : out STD_LOGIC;
p_1_in23_in : out STD_LOGIC;
p_1_in17_in : out STD_LOGIC;
p_1_in14_in : out STD_LOGIC;
p_1_in11_in : out STD_LOGIC;
p_1_in8_in : out STD_LOGIC;
irpt_rdack_d1 : out STD_LOGIC;
p_11_out : out STD_LOGIC;
p_10_out : out STD_LOGIC;
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2Bus_WrAck_intr_reg_hole_d1 : out STD_LOGIC;
ip2Bus_WrAck_core_reg_d1 : out STD_LOGIC;
p_16_out : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : out STD_LOGIC;
ip2Bus_RdAck_core_reg : out STD_LOGIC;
p_15_out : out STD_LOGIC;
ip2Bus_WrAck_core_reg_1 : out STD_LOGIC;
FF_WRACK : out STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : out STD_LOGIC;
ipif_glbl_irpt_enable_reg : out STD_LOGIC;
io0_o : out STD_LOGIC;
io1_o : out STD_LOGIC;
io2_o : out STD_LOGIC;
io3_o : out STD_LOGIC;
rx_fifo_empty_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
ip2intc_irpt : out STD_LOGIC;
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 14 downto 0 );
reset2ip_reset_int : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rd_ce_or_reduce_core_cmb : in STD_LOGIC;
bus2ip_wrce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 13 downto 0 );
ext_spi_clk : in STD_LOGIC;
spisel : in STD_LOGIC;
IP2Bus_Error_1 : in STD_LOGIC;
SPICR_data_int_reg0 : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
sw_rst_cond : in STD_LOGIC;
reset_trig0 : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
Receive_ip2bus_error0 : in STD_LOGIC;
Transmit_ip2bus_error0 : in STD_LOGIC;
intr_controller_wr_ce_or_reduce : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : in STD_LOGIC;
wr_ce_or_reduce_core_cmb : in STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
intr_controller_rd_ce_or_reduce : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
\p_39_out__0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 5 downto 0 );
p_15_in : in STD_LOGIC;
irpt_rdack144_out : in STD_LOGIC;
bus2ip_rdce_int : in STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_6_in : in STD_LOGIC;
p_3_in : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
\IP2Bus_RdAck_receive_enable__1\ : in STD_LOGIC;
p_5_in : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\ : in STD_LOGIC;
\data_is_non_reset_match__4\ : in STD_LOGIC;
\IP2Bus_WrAck_transmit_enable__0\ : in STD_LOGIC;
p_7_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
p_4_in : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
io1_i_sync : in STD_LOGIC;
io0_i_sync : in STD_LOGIC;
io3_i_sync : in STD_LOGIC;
io2_i_sync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_qspi_core_interface : entity is "qspi_core_interface";
end system_axi_quad_spi_flash_0_qspi_core_interface;
architecture STRUCTURE of system_axi_quad_spi_flash_0_qspi_core_interface is
signal Addr_Mode_0_int : STD_LOGIC;
signal Addr_Mode_1_int : STD_LOGIC;
signal Addr_Phase_int : STD_LOGIC;
signal CONTROL_REG_I_n_12 : STD_LOGIC;
signal CONTROL_REG_I_n_16 : STD_LOGIC;
signal CONTROL_REG_I_n_17 : STD_LOGIC;
signal CONTROL_REG_I_n_18 : STD_LOGIC;
signal CONTROL_REG_I_n_19 : STD_LOGIC;
signal CONTROL_REG_I_n_20 : STD_LOGIC;
signal CONTROL_REG_I_n_21 : STD_LOGIC;
signal DTR_FIFO_Data_Exists_d1 : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Dir_int : STD_LOGIC;
signal Data_Mode_0_int : STD_LOGIC;
signal Data_Mode_1_int : STD_LOGIC;
signal Data_Phase_int : STD_LOGIC;
signal \^ff_wrack\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_0\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_1\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_13\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_14\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_15\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_16\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_17\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_18\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_19\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_23\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_24\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_25\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_27\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_28\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_3\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_31\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_4\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_9\ : STD_LOGIC;
signal \FIFO_EXISTS.FIFO_IF_MODULE_I_n_4\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_4\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_5\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_II_n_10\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_II_n_11\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_II_n_2\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_II_n_3\ : STD_LOGIC;
signal \FIFO_EXISTS.RX_FIFO_II_n_4\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_II_n_1\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_II_n_18\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_II_n_5\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_II_n_7\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_II_n_9\ : STD_LOGIC;
signal \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\ : STD_LOGIC;
signal INTERRUPT_CONTROL_I_n_1 : STD_LOGIC;
signal IP2Bus_RdAck_1 : STD_LOGIC;
signal IP2Bus_WrAck_1 : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_gate_n_0\ : STD_LOGIC;
signal \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_1\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_10\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_12\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_13\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_14\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_15\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_9\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_12\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_27\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_28\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_29\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_30\ : STD_LOGIC;
signal \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_40\ : STD_LOGIC;
signal R : STD_LOGIC;
signal \RATIO_OF_2_GENERATE.Count_reg__0\ : STD_LOGIC_VECTOR ( 4 to 4 );
signal R_1 : STD_LOGIC;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1 : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_flag : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_sig : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_synced : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_synced_i : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_org : STD_LOGIC;
signal Rx_FIFO_Full_int : STD_LOGIC;
signal SOFT_RESET_I_n_2 : STD_LOGIC;
signal SOFT_RESET_I_n_5 : STD_LOGIC;
signal SPICR_2_MST_N_SLV_to_spi_clk : STD_LOGIC;
signal SPICR_RX_FIFO_Rst_en : STD_LOGIC;
signal SPISR_0_CMD_Error_d1 : STD_LOGIC;
signal SPISR_0_CMD_Error_int : STD_LOGIC;
signal SPISR_1_LOOP_Back_Error_d1 : STD_LOGIC;
signal \^spisr_1_loop_back_error_int\ : STD_LOGIC;
signal SPISR_2_MSB_Error_d1 : STD_LOGIC;
signal \^spisr_2_msb_error_int\ : STD_LOGIC;
signal SPISR_3_Slave_Mode_Error_d1 : STD_LOGIC;
signal SPISR_3_Slave_Mode_Error_int : STD_LOGIC;
signal SPISR_4_CPOL_CPHA_Error_d1 : STD_LOGIC;
signal SPISR_4_CPOL_CPHA_Error_int : STD_LOGIC;
signal \^spissr_frm_axi_clk\ : STD_LOGIC;
signal SPIXfer_done_int : STD_LOGIC;
signal SPIXfer_done_int_pulse_d2 : STD_LOGIC;
signal SPIXfer_done_rd_tx_en : STD_LOGIC;
signal \^tx_fifo_empty_spisr_to_axi_clk\ : STD_LOGIC;
signal Tx_FIFO_Empty_intr : STD_LOGIC;
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i0\ : STD_LOGIC;
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i0\ : STD_LOGIC;
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/next_fwft_state\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/p_0_in2_in\ : STD_LOGIC;
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\ : STD_LOGIC;
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_5_out\ : STD_LOGIC;
signal \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_7_out\ : STD_LOGIC;
signal bus2IP_Data_for_interrupt_core : STD_LOGIC_VECTOR ( 23 to 23 );
signal data_Exists_RcFIFO_int_d1 : STD_LOGIC;
signal data_Exists_RcFIFO_pulse036_in : STD_LOGIC;
signal data_from_rx_fifo : STD_LOGIC_VECTOR ( 1 to 7 );
signal data_from_txfifo : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^gic0.gc1.count_reg[3]\ : STD_LOGIC;
signal intr_ip2bus_data : STD_LOGIC_VECTOR ( 18 to 20 );
signal ip2Bus_Data_1 : STD_LOGIC_VECTOR ( 25 to 31 );
signal \^ip2bus_rdack_core_reg\ : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal ip2Bus_WrAck_core_reg : STD_LOGIC;
signal \^ip2bus_wrack_core_reg_1\ : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal \master_tri_state_en_control1__1\ : STD_LOGIC;
signal \mode_0__0\ : STD_LOGIC;
signal \mode_1__0\ : STD_LOGIC;
signal modf_strobe_int : STD_LOGIC;
signal \^out\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal p_0_in4_in : STD_LOGIC;
signal p_0_in7_in : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^p_1_in11_in\ : STD_LOGIC;
signal \^p_1_in17_in\ : STD_LOGIC;
signal p_1_in20_in : STD_LOGIC;
signal \^p_1_in23_in\ : STD_LOGIC;
signal p_1_in26_in : STD_LOGIC;
signal \^p_1_in29_in\ : STD_LOGIC;
signal p_1_in2_in : STD_LOGIC;
signal p_1_in32_in : STD_LOGIC;
signal p_1_in35_in : STD_LOGIC;
signal p_1_in5_in : STD_LOGIC;
signal \^p_1_in8_in\ : STD_LOGIC;
signal p_2_in_0 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal qspi_cntrl_ps : STD_LOGIC_VECTOR ( 2 downto 0 );
signal read_ack_delay_6 : STD_LOGIC;
signal read_ack_delay_7 : STD_LOGIC;
signal receive_Data_int : STD_LOGIC_VECTOR ( 0 to 7 );
signal register_Data_slvsel_int : STD_LOGIC;
signal reset_TxFIFO_ptr_int : STD_LOGIC;
signal rst_to_spi_int : STD_LOGIC;
signal rx_fifo_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^rx_fifo_empty_i\ : STD_LOGIC;
signal rx_fifo_reset : STD_LOGIC;
signal \^spixfer_done_int\ : STD_LOGIC;
signal spiXfer_done_to_axi_1 : STD_LOGIC;
signal spicr_1_spe_frm_axi_clk : STD_LOGIC;
signal \^spicr_2_mst_n_slv_frm_axi_clk\ : STD_LOGIC;
signal spicr_3_cpol_frm_axi_clk : STD_LOGIC;
signal spicr_3_cpol_to_spi_clk : STD_LOGIC;
signal spicr_4_cpha_frm_axi_clk : STD_LOGIC;
signal spicr_4_cpha_to_spi_clk : STD_LOGIC;
signal \^spicr_5_txfifo_rst_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_6_rxfifo_rst_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_8_tr_inhibit_frm_axi_clk\ : STD_LOGIC;
signal spicr_8_tr_inhibit_to_spi_clk : STD_LOGIC;
signal spicr_bits_7_8_frm_axi_clk : STD_LOGIC_VECTOR ( 1 downto 0 );
signal spisel_d1_reg : STD_LOGIC;
signal sr_3_MODF_int : STD_LOGIC;
signal stop_clock : STD_LOGIC;
signal transfer_start : STD_LOGIC;
signal transfer_start_d1 : STD_LOGIC;
signal transfer_start_d2 : STD_LOGIC;
signal tx_FIFO_Empty_d1 : STD_LOGIC;
signal tx_FIFO_Occpncy_MSB_d1 : STD_LOGIC;
signal tx_fifo_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal tx_fifo_empty : STD_LOGIC;
signal tx_occ_msb : STD_LOGIC;
signal tx_occ_msb_2 : STD_LOGIC;
signal tx_occ_msb_3 : STD_LOGIC;
signal tx_occ_msb_4 : STD_LOGIC;
signal \updown_cnt_en_rx__4\ : STD_LOGIC;
attribute srl_name : string;
attribute srl_name of \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r\ : label is "U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r ";
begin
FF_WRACK <= \^ff_wrack\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ <= \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\;
SPISR_1_LOOP_Back_Error_int <= \^spisr_1_loop_back_error_int\;
SPISR_2_MSB_Error_int <= \^spisr_2_msb_error_int\;
SPISSR_frm_axi_clk <= \^spissr_frm_axi_clk\;
Tx_FIFO_Empty_SPISR_to_axi_clk <= \^tx_fifo_empty_spisr_to_axi_clk\;
\gic0.gc1.count_reg[3]\ <= \^gic0.gc1.count_reg[3]\;
ip2Bus_RdAck_core_reg <= \^ip2bus_rdack_core_reg\;
ip2Bus_WrAck_core_reg_1 <= \^ip2bus_wrack_core_reg_1\;
\out\ <= \^out\;
p_1_in11_in <= \^p_1_in11_in\;
p_1_in17_in <= \^p_1_in17_in\;
p_1_in23_in <= \^p_1_in23_in\;
p_1_in29_in <= \^p_1_in29_in\;
p_1_in8_in <= \^p_1_in8_in\;
rx_fifo_empty_i <= \^rx_fifo_empty_i\;
spicr_2_mst_n_slv_frm_axi_clk <= \^spicr_2_mst_n_slv_frm_axi_clk\;
spicr_5_txfifo_rst_frm_axi_clk <= \^spicr_5_txfifo_rst_frm_axi_clk\;
spicr_6_rxfifo_rst_frm_axi_clk <= \^spicr_6_rxfifo_rst_frm_axi_clk\;
spicr_8_tr_inhibit_frm_axi_clk <= \^spicr_8_tr_inhibit_frm_axi_clk\;
CONTROL_REG_I: entity work.system_axi_quad_spi_flash_0_qspi_cntrl_reg
port map (
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\ => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
D(0) => ip2Bus_Data_1(25),
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_1_LOOP_Back_Error_d1_reg\ => \^spisr_1_loop_back_error_int\,
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\GEN_IP_IRPT_STATUS_REG[10].GEN_REG_STATUS.ip_irpt_status_reg_reg[10]\ => CONTROL_REG_I_n_21,
\GEN_IP_IRPT_STATUS_REG[11].GEN_REG_STATUS.ip_irpt_status_reg_reg[11]\ => CONTROL_REG_I_n_20,
\GEN_IP_IRPT_STATUS_REG[12].GEN_REG_STATUS.ip_irpt_status_reg_reg[12]\ => CONTROL_REG_I_n_19,
\GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg_reg[9]\ => CONTROL_REG_I_n_12,
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ => \^spicr_2_mst_n_slv_frm_axi_clk\,
\LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_1_CDC\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_3\,
Q(0) => data_from_rx_fifo(1),
\RESET_FLOPS[15].RST_FLOPS\ => \^ff_wrack\,
SPICR_RX_FIFO_Rst_en => SPICR_RX_FIFO_Rst_en,
SPICR_data_int_reg0 => SPICR_data_int_reg0,
SPISR_1_LOOP_Back_Error_d1 => SPISR_1_LOOP_Back_Error_d1,
SPISR_2_MSB_Error_d1 => SPISR_2_MSB_Error_d1,
SPISR_2_MSB_Error_int => \^spisr_2_msb_error_int\,
SPISR_3_Slave_Mode_Error_d1 => SPISR_3_Slave_Mode_Error_d1,
SPISR_3_Slave_Mode_Error_int => SPISR_3_Slave_Mode_Error_int,
SPISR_4_CPOL_CPHA_Error_d1 => SPISR_4_CPOL_CPHA_Error_d1,
SPISR_4_CPOL_CPHA_Error_int => SPISR_4_CPOL_CPHA_Error_int,
bus2ip_rdce_int(1 downto 0) => bus2ip_rdce_int(1 downto 0),
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
bus2ip_wrce_int(0) => bus2ip_wrce_int(0),
\icount_out_reg[0]\ => \^spicr_6_rxfifo_rst_frm_axi_clk\,
\icount_out_reg[0]_0\ => CONTROL_REG_I_n_17,
\icount_out_reg[0]_1\ => CONTROL_REG_I_n_18,
\icount_out_reg[3]\ => CONTROL_REG_I_n_16,
\ip_irpt_enable_reg_reg[6]\(0) => p_0_in13_in,
irpt_rdack144_out => irpt_rdack144_out,
p_15_in => p_15_in,
p_1_in11_in => \^p_1_in11_in\,
p_1_in20_in => p_1_in20_in,
p_1_in2_in => p_1_in2_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => \^p_1_in8_in\,
\p_39_out__0\ => \p_39_out__0\,
reset2ip_reset_int => reset2ip_reset_int,
rx_fifo_count(0) => rx_fifo_count(0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(10 downto 5) => s_axi_wdata(12 downto 7),
s_axi_wdata(4 downto 0) => s_axi_wdata(4 downto 0),
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => \^spicr_8_tr_inhibit_frm_axi_clk\,
spicr_bits_7_8_frm_axi_clk(1 downto 0) => spicr_bits_7_8_frm_axi_clk(1 downto 0),
tx_fifo_count(0) => tx_fifo_count(0),
\updown_cnt_en_rx__4\ => \updown_cnt_en_rx__4\
);
\FIFO_EXISTS.CLK_CROSS_I\: entity work.system_axi_quad_spi_flash_0_cross_clk_sync_fifo_1
port map (
Bus_RNW_reg => Bus_RNW_reg,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \^spicr_6_rxfifo_rst_frm_axi_clk\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\ => \^spicr_2_mst_n_slv_frm_axi_clk\,
D(0) => bus2IP_Data_for_interrupt_core(23),
D_1 => D_0,
E(0) => \FIFO_EXISTS.CLK_CROSS_I_n_31\,
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_0_CMD_Error_d1_reg\ => \^out\,
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_28\,
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg_0\ => \^rx_fifo_empty_i\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \FIFO_EXISTS.CLK_CROSS_I_n_18\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => INTERRUPT_CONTROL_I_n_1,
\GEN_IP_IRPT_STATUS_REG[13].GEN_REG_STATUS.ip_irpt_status_reg_reg[13]\ => \FIFO_EXISTS.CLK_CROSS_I_n_14\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \FIFO_EXISTS.CLK_CROSS_I_n_17\,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ => \FIFO_EXISTS.CLK_CROSS_I_n_16\,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\ => \FIFO_EXISTS.CLK_CROSS_I_n_15\,
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\ => \FIFO_EXISTS.CLK_CROSS_I_n_23\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \FIFO_EXISTS.CLK_CROSS_I_n_24\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \^ip2bus_rdack_core_reg\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \^ip2bus_wrack_core_reg_1\,
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_9\,
\LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_1\,
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_3\,
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2_0\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_13\,
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_0\,
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_4\,
Q(0) => \RATIO_OF_2_GENERATE.Count_reg__0\(4),
QSPI_SPISEL => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_29\,
R => R_1,
\RESET_FLOPS[15].RST_FLOPS\ => \^ff_wrack\,
R_0 => R,
Rst_to_spi => rst_to_spi_int,
Rx_FIFO_Full_Fifo_d1_flag => Rx_FIFO_Full_Fifo_d1_flag,
Rx_FIFO_Full_Fifo_d1_sig => Rx_FIFO_Full_Fifo_d1_sig,
SPICR_2_MST_N_SLV_to_spi_clk => SPICR_2_MST_N_SLV_to_spi_clk,
SPICR_RX_FIFO_Rst_en => SPICR_RX_FIFO_Rst_en,
SPISR_0_CMD_Error_d1 => SPISR_0_CMD_Error_d1,
SPISR_0_CMD_Error_int => SPISR_0_CMD_Error_int,
SPISSR_frm_axi_clk => \^spissr_frm_axi_clk\,
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
ext_spi_clk => ext_spi_clk,
\icount_out_reg[1]\ => \FIFO_EXISTS.CLK_CROSS_I_n_25\,
\icount_out_reg[2]\ => \FIFO_EXISTS.CLK_CROSS_I_n_19\,
\ip_irpt_enable_reg_reg[8]\ => \ip_irpt_enable_reg_reg[8]\,
\master_tri_state_en_control1__1\ => \master_tri_state_en_control1__1\,
modf_reg => \FIFO_EXISTS.CLK_CROSS_I_n_27\,
modf_strobe_int => modf_strobe_int,
\out\ => tx_fifo_empty,
p_0_out => p_0_out,
p_1_in => p_1_in,
p_1_in17_in => \^p_1_in17_in\,
p_1_in23_in => \^p_1_in23_in\,
p_1_in35_in => p_1_in35_in,
p_2_in => p_2_in,
p_2_out => p_2_out,
\p_39_out__0\ => \p_39_out__0\,
p_5_out => p_5_out,
p_6_in => p_6_in,
p_7_in => p_7_in,
prmry_in => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
ram_full_i_reg => \^gic0.gc1.count_reg[3]\,
register_Data_slvsel_int => register_Data_slvsel_int,
reset2ip_reset_int => reset2ip_reset_int,
rx_fifo_count(0) => rx_fifo_count(2),
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(5) => s_axi_wdata(13),
s_axi_wdata(4 downto 3) => s_axi_wdata(8 downto 7),
s_axi_wdata(2) => s_axi_wdata(5),
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0),
scndry_out => Rx_FIFO_Full_Fifo_d1_synced,
spiXfer_done_to_axi_1 => spiXfer_done_to_axi_1,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_3_cpol_to_spi_clk => spicr_3_cpol_to_spi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_4_cpha_to_spi_clk => spicr_4_cpha_to_spi_clk,
spicr_8_tr_inhibit_frm_axi_clk => \^spicr_8_tr_inhibit_frm_axi_clk\,
spicr_8_tr_inhibit_to_spi_clk => spicr_8_tr_inhibit_to_spi_clk,
spicr_bits_7_8_frm_axi_clk(1 downto 0) => spicr_bits_7_8_frm_axi_clk(1 downto 0),
spisel_d1_reg => spisel_d1_reg,
sr_3_MODF_int => sr_3_MODF_int,
stop_clock => stop_clock,
transfer_start_d2 => transfer_start_d2,
transfer_start_reg => \FIFO_EXISTS.CLK_CROSS_I_n_13\,
tx_FIFO_Occpncy_MSB_d1_reg => \^tx_fifo_empty_spisr_to_axi_clk\,
tx_occ_msb => tx_occ_msb,
tx_occ_msb_4 => tx_occ_msb_4
);
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_0_CMD_Error_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^out\,
Q => SPISR_0_CMD_Error_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_1_LOOP_Back_Error_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^spisr_1_loop_back_error_int\,
Q => SPISR_1_LOOP_Back_Error_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_2_MSB_Error_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^spisr_2_msb_error_int\,
Q => SPISR_2_MSB_Error_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_3_Slave_Mode_Error_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => SPISR_3_Slave_Mode_Error_int,
Q => SPISR_3_Slave_Mode_Error_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_4_CPOL_CPHA_Error_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => SPISR_4_CPOL_CPHA_Error_int,
Q => SPISR_4_CPOL_CPHA_Error_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.FIFO_IF_MODULE_I\: entity work.system_axi_quad_spi_flash_0_qspi_fifo_ifmodule
port map (
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\ => \FIFO_EXISTS.FIFO_IF_MODULE_I_n_4\,
Receive_ip2bus_error0 => Receive_ip2bus_error0,
Rx_FIFO_Full_Fifo_d1_synced_i => Rx_FIFO_Full_Fifo_d1_synced_i,
Transmit_ip2bus_error0 => Transmit_ip2bus_error0,
Tx_FIFO_Empty_intr => Tx_FIFO_Empty_intr,
p_10_out => p_10_out,
p_11_out => p_11_out,
p_1_in26_in => p_1_in26_in,
\p_39_out__0\ => \p_39_out__0\,
prmry_in => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
reset2ip_reset_int => reset2ip_reset_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(4),
scndry_out => Rx_FIFO_Full_Fifo_d1_synced,
tx_FIFO_Empty_d1 => tx_FIFO_Empty_d1,
tx_FIFO_Occpncy_MSB_d1 => tx_FIFO_Occpncy_MSB_d1,
tx_occ_msb => tx_occ_msb
);
\FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC\: entity work.system_axi_quad_spi_flash_0_cdc_sync
port map (
ext_spi_clk => ext_spi_clk,
prmry_in => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
\FIFO_EXISTS.RX_FIFO_FULL_CNTR_I\: entity work.system_axi_quad_spi_flash_0_counter_f
port map (
Bus_RNW_reg => Bus_RNW_reg,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \^spicr_6_rxfifo_rst_frm_axi_clk\,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ => CONTROL_REG_I_n_16,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_1\ => CONTROL_REG_I_n_17,
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_reg\ => \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_5\,
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\ => \^rx_fifo_empty_i\,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ => \FIFO_EXISTS.CLK_CROSS_I_n_25\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\ => \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_4\,
\RESET_FLOPS[15].RST_FLOPS\ => \^ff_wrack\,
Rx_FIFO_Full_int => Rx_FIFO_Full_int,
SPISSR_frm_axi_clk => \^spissr_frm_axi_clk\,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
\out\ => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
p_2_in => p_2_in,
p_4_in => p_4_in,
reset2ip_reset_int => reset2ip_reset_int,
rx_fifo_count(3 downto 0) => rx_fifo_count(3 downto 0),
s_axi_aclk => s_axi_aclk,
spiXfer_done_to_axi_1 => spiXfer_done_to_axi_1
);
\FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC\: entity work.system_axi_quad_spi_flash_0_cdc_sync_0
port map (
D(0) => ip2Bus_Data_1(30),
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
Q(0) => p_0_in,
Rx_FIFO_Full_Fifo_d1_flag => Rx_FIFO_Full_Fifo_d1_flag,
Rx_FIFO_Full_Fifo_d1_sig => Rx_FIFO_Full_Fifo_d1_sig,
Rx_FIFO_Full_Fifo_d1_synced_i => Rx_FIFO_Full_Fifo_d1_synced_i,
Rx_FIFO_Full_int => Rx_FIFO_Full_int,
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
\goreg_dm.dout_i_reg[1]\ => \FIFO_EXISTS.RX_FIFO_II_n_4\,
\icount_out_reg[1]\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5\,
\out\ => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
prmry_in => Rx_FIFO_Full_Fifo_d1,
s_axi_aclk => s_axi_aclk,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced,
spiXfer_done_to_axi_1 => spiXfer_done_to_axi_1,
\updown_cnt_en_rx__4\ => \updown_cnt_en_rx__4\
);
\FIFO_EXISTS.RX_FIFO_II\: entity work.system_axi_quad_spi_flash_0_async_fifo_fg
port map (
Bus_RNW_reg => Bus_RNW_reg,
E(0) => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_30\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\ => Rx_FIFO_Full_Fifo_org,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg_0\ => \FIFO_EXISTS.RX_FIFO_II_n_3\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \FIFO_EXISTS.RX_FIFO_II_n_11\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \FIFO_EXISTS.RX_FIFO_II_n_10\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ => \FIFO_EXISTS.RX_FIFO_II_n_4\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \^ip2bus_rdack_core_reg\,
Q(4) => Q(1),
Q(3) => data_from_rx_fifo(1),
Q(2) => Q(0),
Q(1) => data_from_rx_fifo(3),
Q(0) => data_from_rx_fifo(7),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(7) => receive_Data_int(0),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(6) => receive_Data_int(1),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(5) => receive_Data_int(2),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(4) => receive_Data_int(3),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(3) => receive_Data_int(4),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(2) => receive_Data_int(5),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(1) => receive_Data_int(6),
\RX_DATA_SCK_RATIO_2_GEN1.receive_Data_int_reg[0]\(0) => receive_Data_int(7),
bus2ip_rdce_int(0) => bus2ip_rdce_int(1),
ext_spi_clk => ext_spi_clk,
irpt_rdack144_out => irpt_rdack144_out,
\out\ => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
p_15_in => p_15_in,
p_1_in29_in => \^p_1_in29_in\,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_5_in => p_5_in,
ram_full_fb_i_reg => \FIFO_EXISTS.RX_FIFO_II_n_2\,
rx_fifo_reset => rx_fifo_reset,
s_axi_aclk => s_axi_aclk,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain,
spiXfer_done_int => \^spixfer_done_int\,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => \^spicr_2_mst_n_slv_frm_axi_clk\,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk
);
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.Rx_FIFO_Full_int_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_5\,
Q => Rx_FIFO_Full_int,
R => '0'
);
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FIFO_EXISTS.CLK_CROSS_I_n_28\,
Q => \^rx_fifo_empty_i\,
R => '0'
);
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_flag_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Rx_FIFO_Full_Fifo_d1_synced,
Q => Rx_FIFO_Full_Fifo_d1_flag,
R => reset2ip_reset_int
);
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \FIFO_EXISTS.RX_FIFO_II_n_3\,
Q => Rx_FIFO_Full_Fifo_d1,
R => rst_to_spi_int
);
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => SOFT_RESET_I_n_5,
Q => Rx_FIFO_Full_Fifo_d1_sig,
R => '0'
);
\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I\: entity work.system_axi_quad_spi_flash_0_counter_f_1
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_1 => SOFT_RESET_I_n_2,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\ => CONTROL_REG_I_n_18,
D(0) => ip2Bus_Data_1(29),
\FIFO_EXISTS.tx_occ_msb_2_reg\(1) => tx_fifo_count(3),
\FIFO_EXISTS.tx_occ_msb_2_reg\(0) => tx_fifo_count(0),
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_19\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_24\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ => \^tx_fifo_empty_spisr_to_axi_clk\,
Q(0) => p_0_in1_in,
\RESET_FLOPS[15].RST_FLOPS\ => \^ff_wrack\,
Tx_FIFO_Empty_intr => Tx_FIFO_Empty_intr,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
\goreg_dm.dout_i_reg[2]\ => \FIFO_EXISTS.RX_FIFO_II_n_10\,
p_1_in32_in => p_1_in32_in,
\p_39_out__0\ => \p_39_out__0\,
p_3_in => p_3_in,
reset2ip_reset_int => reset2ip_reset_int,
rx_fifo_count(1) => rx_fifo_count(3),
rx_fifo_count(0) => rx_fifo_count(1),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(0) => s_axi_wdata(2),
spiXfer_done_to_axi_1 => spiXfer_done_to_axi_1,
tx_FIFO_Empty_d1 => tx_FIFO_Empty_d1
);
\FIFO_EXISTS.TX_FIFO_II\: entity work.system_axi_quad_spi_flash_0_async_fifo_fg_2
port map (
Bus_RNW_reg => Bus_RNW_reg,
D(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/next_fwft_state\(0),
E(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_7_out\,
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\(0) => ip2Bus_Data_1(28),
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \^ip2bus_wrack_core_reg_1\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ => tx_fifo_empty,
Q(0) => Data_Phase_int,
QSPI_IO1_T => \FIFO_EXISTS.TX_FIFO_II_n_7\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(7) => data_from_txfifo(0),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(6) => data_from_txfifo(1),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(5) => data_from_txfifo(2),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(4) => data_from_txfifo(3),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(3) => data_from_txfifo(4),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(2) => data_from_txfifo(5),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(1) => data_from_txfifo(6),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\(0) => data_from_txfifo(7),
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_0_reg\ => \FIFO_EXISTS.TX_FIFO_II_n_9\,
\RATIO_OF_2_GENERATE.RATIO_2_CAP_QSPI_QUAD_MODE_OTHER_MEM_GEN.Serial_Dout_1_reg\ => \FIFO_EXISTS.TX_FIFO_II_n_18\,
SPIXfer_done_int_pulse_d2 => SPIXfer_done_int_pulse_d2,
SPIXfer_done_rd_tx_en => SPIXfer_done_rd_tx_en,
bus2ip_rdce_int(0) => bus2ip_rdce_int(0),
empty_fwft_fb_i_reg => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/p_0_in2_in\,
empty_fwft_fb_o_i0 => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i0\,
empty_fwft_fb_o_i_reg => \FIFO_EXISTS.TX_FIFO_II_n_5\,
empty_fwft_i0 => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i0\,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[3]\ => \^gic0.gc1.count_reg[3]\,
\goreg_dm.dout_i_reg[3]\ => \FIFO_EXISTS.RX_FIFO_II_n_11\,
\gpregsm1.curr_fwft_state_reg[1]\(1) => \FIFO_EXISTS.TX_FIFO_II_n_1\,
\gpregsm1.curr_fwft_state_reg[1]\(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/p_0_in\(0),
\gpregsm1.curr_fwft_state_reg[1]_0\(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_5_out\,
\icount_out_reg[3]\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6\,
\ip_irpt_enable_reg_reg[3]\(0) => p_0_in4_in,
\mode_0__0\ => \mode_0__0\,
\mode_1__0\ => \mode_1__0\,
\out\ => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\,
p_6_in => p_6_in,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
transfer_start => transfer_start,
transfer_start_d1 => transfer_start_d1
);
\FIFO_EXISTS.data_Exists_RcFIFO_int_d1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^rx_fifo_empty_i\,
O => data_Exists_RcFIFO_pulse036_in
);
\FIFO_EXISTS.data_Exists_RcFIFO_int_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => data_Exists_RcFIFO_pulse036_in,
Q => data_Exists_RcFIFO_int_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.tx_occ_msb_2_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_fifo_count(3),
Q => tx_occ_msb_2,
R => reset2ip_reset_int
);
\FIFO_EXISTS.tx_occ_msb_3_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_occ_msb_2,
Q => tx_occ_msb_3,
R => reset2ip_reset_int
);
\FIFO_EXISTS.tx_occ_msb_4_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_occ_msb_3,
Q => tx_occ_msb_4,
R => reset2ip_reset_int
);
INTERRUPT_CONTROL_I: entity work.system_axi_quad_spi_flash_0_interrupt_control
port map (
Bus_RNW_reg => Bus_RNW_reg,
Bus_RNW_reg_reg => Bus_RNW_reg_reg_0,
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\ => CONTROL_REG_I_n_21,
D(3) => intr_ip2bus_data(18),
D(2) => intr_ip2bus_data(19),
D(1) => intr_ip2bus_data(20),
D(0) => ip2Bus_Data_1(31),
E(0) => E(0),
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_0_CMD_Error_d1_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_14\,
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_1_LOOP_Back_Error_d1_reg\ => CONTROL_REG_I_n_19,
\FIFO_EXISTS.DUAL_MD_INTR_GEN.SPISR_2_MSB_Error_d1_reg\ => CONTROL_REG_I_n_20,
\FIFO_EXISTS.RX_FULL_EMP_MD_12_INTR_GEN.rx_fifo_empty_i_reg\ => \^rx_fifo_empty_i\,
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => INTERRUPT_CONTROL_I_n_1,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1\ => \FIFO_EXISTS.CLK_CROSS_I_n_18\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_17\,
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]_0\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0\ => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_16\,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_15\,
\GEN_IP_IRPT_STATUS_REG[9].GEN_REG_STATUS.ip_irpt_status_reg_reg[9]_0\ => CONTROL_REG_I_n_12,
IP2Bus_RdAck_1 => IP2Bus_RdAck_1,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\(9 downto 6) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]_0\(4 downto 1),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\(5) => p_0_in13_in,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\(4) => \LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]_0\(0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\(3) => p_0_in7_in,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\(2) => p_0_in4_in,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\(1) => p_0_in1_in,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\(0) => p_0_in,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\ => \^ip2bus_rdack_core_reg\,
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_23\,
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2_0\(0) => bus2IP_Data_for_interrupt_core(23),
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ => \^tx_fifo_empty_spisr_to_axi_clk\,
Q(0) => data_from_rx_fifo(7),
SPISR_1_LOOP_Back_Error_int => \^spisr_1_loop_back_error_int\,
bus2ip_rdce_int(1 downto 0) => bus2ip_rdce_int(1 downto 0),
data_Exists_RcFIFO_int_d1 => data_Exists_RcFIFO_int_d1,
\icount_out_reg[0]\ => \FIFO_EXISTS.RX_FIFO_FULL_CNTR_I_n_4\,
\icount_out_reg[0]_0\(0) => tx_fifo_count(0),
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2intc_irpt => ip2intc_irpt,
ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg,
irpt_rdack => irpt_rdack,
irpt_rdack144_out => irpt_rdack144_out,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
\out\ => \^generate_level_p_s_cdc.single_bit.cross_plevel_in2scndry_in_cdc_to\,
p_15_in => p_15_in,
p_1_in => p_1_in,
p_1_in11_in => \^p_1_in11_in\,
p_1_in14_in => p_1_in14_in,
p_1_in17_in => \^p_1_in17_in\,
p_1_in20_in => p_1_in20_in,
p_1_in23_in => \^p_1_in23_in\,
p_1_in26_in => p_1_in26_in,
p_1_in29_in => \^p_1_in29_in\,
p_1_in2_in => p_1_in2_in,
p_1_in32_in => p_1_in32_in,
p_1_in35_in => p_1_in35_in,
p_1_in5_in => p_1_in5_in,
p_1_in8_in => \^p_1_in8_in\,
p_2_in_0 => p_2_in_0,
\p_39_out__0\ => \p_39_out__0\,
p_3_in => p_3_in,
rc_FIFO_Full_d1_reg => \FIFO_EXISTS.FIFO_IF_MODULE_I_n_4\,
reset2ip_reset_int => reset2ip_reset_int,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(13 downto 0) => s_axi_wdata(13 downto 0),
tx_FIFO_Occpncy_MSB_d1 => tx_FIFO_Occpncy_MSB_d1,
tx_occ_msb_4 => tx_occ_msb_4
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(5),
Q => \s_axi_rdata_i_reg[31]\(14),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_ip2bus_data(18),
Q => \s_axi_rdata_i_reg[31]\(13),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_ip2bus_data(19),
Q => \s_axi_rdata_i_reg[31]\(12),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_ip2bus_data(20),
Q => \s_axi_rdata_i_reg[31]\(11),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(4),
Q => \s_axi_rdata_i_reg[31]\(10),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(3),
Q => \s_axi_rdata_i_reg[31]\(9),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(2),
Q => \s_axi_rdata_i_reg[31]\(8),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(1),
Q => \s_axi_rdata_i_reg[31]\(7),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_Data_1(25),
Q => \s_axi_rdata_i_reg[31]\(6),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => D(0),
Q => \s_axi_rdata_i_reg[31]\(5),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_Data_1(27),
Q => \s_axi_rdata_i_reg[31]\(4),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_Data_1(28),
Q => \s_axi_rdata_i_reg[31]\(3),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_Data_1(29),
Q => \s_axi_rdata_i_reg[31]\(2),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_Data_1(30),
Q => \s_axi_rdata_i_reg[31]\(1),
R => reset2ip_reset_int
);
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_Data_1(31),
Q => \s_axi_rdata_i_reg[31]\(0),
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_Error_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2Bus_Error_1,
Q => IP2Bus_Error,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_RdAck_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2Bus_RdAck_1,
Q => p_15_out,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => IP2Bus_WrAck_1,
Q => p_16_out,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => read_ack_delay_6,
I1 => read_ack_delay_7,
O => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1_n_0\,
Q => \^ip2bus_rdack_core_reg\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_WrAck_core_reg,
Q => \^ip2bus_wrack_core_reg_1\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => wr_ce_or_reduce_core_cmb,
Q => ip2Bus_WrAck_core_reg_d1,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg,
Q => ip2Bus_WrAck_core_reg,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => '1',
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r\: unisim.vcomponents.SRL16E
port map (
A0 => '1',
A1 => '1',
A2 => '0',
A3 => '0',
CE => '1',
CLK => s_axi_aclk,
D => rd_ce_or_reduce_core_cmb,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_srl4___NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\,
R => '0'
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_gate\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_NO_DUAL_QUAD_MODE.QSPI_NORMAL_QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\,
I1 => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\,
O => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_gate_n_0\
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg_r_n_0\,
Q => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_r_n_0\,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_6_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg_gate_n_0\,
Q => read_ack_delay_6,
R => reset2ip_reset_int
);
\LEGACY_MD_WR_RD_ACK_GEN.read_ack_delay_7_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => read_ack_delay_6,
Q => read_ack_delay_7,
R => reset2ip_reset_int
);
\LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I\: entity work.system_axi_quad_spi_flash_0_qspi_look_up_logic
port map (
DTR_FIFO_Data_Exists_d1 => DTR_FIFO_Data_Exists_d1,
Q(6) => Data_Dir_int,
Q(5) => Data_Mode_1_int,
Q(4) => Data_Mode_0_int,
Q(3) => Data_Phase_int,
Q(2) => Addr_Mode_1_int,
Q(1) => Addr_Mode_0_int,
Q(0) => Addr_Phase_int,
QSPI_IO0_T => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_12\,
QSPI_IO1_T => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_14\,
QSPI_IO1_T_0 => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_15\,
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_1\,
\QSPI_MODE_2_T_CONTROL.QSPI_IO2_T_0\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_9\,
\QSPI_QUAD_MODE_MIXED_WB_MEM_GEN.addr_cnt_reg[1]\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_40\,
R => R,
\RX_DATA_SCK_RATIO_2_GEN1.SPIXfer_done_int_reg\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_12\,
Rst_to_spi => rst_to_spi_int,
SPISR_0_CMD_Error_int => SPISR_0_CMD_Error_int,
SPIXfer_done_int => SPIXfer_done_int,
empty_fwft_i_reg => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_28\,
empty_fwft_i_reg_0 => tx_fifo_empty,
empty_fwft_i_reg_1 => \FIFO_EXISTS.TX_FIFO_II_n_7\,
ext_spi_clk => ext_spi_clk,
\goreg_dm.dout_i_reg[7]\(7) => data_from_txfifo(0),
\goreg_dm.dout_i_reg[7]\(6) => data_from_txfifo(1),
\goreg_dm.dout_i_reg[7]\(5) => data_from_txfifo(2),
\goreg_dm.dout_i_reg[7]\(4) => data_from_txfifo(3),
\goreg_dm.dout_i_reg[7]\(3) => data_from_txfifo(4),
\goreg_dm.dout_i_reg[7]\(2) => data_from_txfifo(5),
\goreg_dm.dout_i_reg[7]\(1) => data_from_txfifo(6),
\goreg_dm.dout_i_reg[7]\(0) => data_from_txfifo(7),
\master_tri_state_en_control1__1\ => \master_tri_state_en_control1__1\,
\qspi_cntrl_ps_reg[0]\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_10\,
\qspi_cntrl_ps_reg[1]\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_27\,
\qspi_cntrl_ps_reg[2]\(2 downto 0) => qspi_cntrl_ps(2 downto 0),
spicr_8_tr_inhibit_to_spi_clk => spicr_8_tr_inhibit_to_spi_clk,
transfer_start_reg => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_13\
);
\LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I\: entity work.system_axi_quad_spi_flash_0_qspi_mode_control_logic
port map (
D(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/next_fwft_state\(0),
DTR_FIFO_Data_Exists_d1 => DTR_FIFO_Data_Exists_d1,
D_0 => D_0,
E(0) => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_30\,
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_13\,
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\(0) => \FIFO_EXISTS.CLK_CROSS_I_n_31\,
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_9\,
\LOGIC_GENERATION_FDR.modf_strobe_cdc_from_spi_int_2_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_1\,
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_4\,
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_29\,
\LOGIC_GENERATION_FDR.spisel_pulse_cdc_from_spi_int_2_reg_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_0\,
Q(2 downto 0) => qspi_cntrl_ps(2 downto 0),
\QSPI_LOOK_UP_MODE_2_MEMORY_1.DTR_FIFO_Data_Exists_d1_reg\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_28\,
\QSPI_LOOK_UP_MODE_2_MEMORY_1.TXFIFO_ADDR_BITS_GENERATE[0].TXFIFO_FIRST_ENTRY_REG_I\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_27\,
R => R_1,
\RATIO_OF_2_GENERATE.Count_reg[4]_0\(0) => \RATIO_OF_2_GENERATE.Count_reg__0\(4),
Rst_to_spi => rst_to_spi_int,
SPICR_2_MST_N_SLV_to_spi_clk => SPICR_2_MST_N_SLV_to_spi_clk,
SPIXfer_done_int => SPIXfer_done_int,
SPIXfer_done_int_pulse_d1_reg_0 => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_12\,
SPIXfer_done_int_pulse_d2 => SPIXfer_done_int_pulse_d2,
SPIXfer_done_rd_tx_en => SPIXfer_done_rd_tx_en,
empty_fwft_fb_i_reg => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/p_0_in2_in\,
empty_fwft_fb_o_i0 => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i0\,
empty_fwft_fb_o_i_reg => \FIFO_EXISTS.TX_FIFO_II_n_5\,
empty_fwft_i0 => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i0\,
empty_fwft_i_reg => tx_fifo_empty,
empty_fwft_i_reg_0 => \FIFO_EXISTS.TX_FIFO_II_n_7\,
ext_spi_clk => ext_spi_clk,
\gc1.count_d1_reg[3]\(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_7_out\,
\goreg_dm.dout_i_reg[0]\(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_5_out\,
\goreg_dm.dout_i_reg[7]\ => \FIFO_EXISTS.TX_FIFO_II_n_9\,
\goreg_dm.dout_i_reg[7]_0\ => \FIFO_EXISTS.TX_FIFO_II_n_18\,
\goreg_dm.dout_i_reg[7]_1\(7) => data_from_txfifo(0),
\goreg_dm.dout_i_reg[7]_1\(6) => data_from_txfifo(1),
\goreg_dm.dout_i_reg[7]_1\(5) => data_from_txfifo(2),
\goreg_dm.dout_i_reg[7]_1\(4) => data_from_txfifo(3),
\goreg_dm.dout_i_reg[7]_1\(3) => data_from_txfifo(4),
\goreg_dm.dout_i_reg[7]_1\(2) => data_from_txfifo(5),
\goreg_dm.dout_i_reg[7]_1\(1) => data_from_txfifo(6),
\goreg_dm.dout_i_reg[7]_1\(0) => data_from_txfifo(7),
\gpr1.dout_i_reg[7]\(7) => receive_Data_int(0),
\gpr1.dout_i_reg[7]\(6) => receive_Data_int(1),
\gpr1.dout_i_reg[7]\(5) => receive_Data_int(2),
\gpr1.dout_i_reg[7]\(4) => receive_Data_int(3),
\gpr1.dout_i_reg[7]\(3) => receive_Data_int(4),
\gpr1.dout_i_reg[7]\(2) => receive_Data_int(5),
\gpr1.dout_i_reg[7]\(1) => receive_Data_int(6),
\gpr1.dout_i_reg[7]\(0) => receive_Data_int(7),
\gpregsm1.curr_fwft_state_reg[1]\(1) => \FIFO_EXISTS.TX_FIFO_II_n_1\,
\gpregsm1.curr_fwft_state_reg[1]\(0) => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/p_0_in\(0),
io0_i_sync => io0_i_sync,
io0_o => io0_o,
io0_t => io0_t,
io1_i_sync => io1_i_sync,
io1_o => io1_o,
io1_t => io1_t,
io2_i_sync => io2_i_sync,
io2_o => io2_o,
io2_t => io2_t,
io3_i_sync => io3_i_sync,
io3_o => io3_o,
io3_t => io3_t,
\master_tri_state_en_control1__1\ => \master_tri_state_en_control1__1\,
\mode_0__0\ => \mode_0__0\,
\mode_1__0\ => \mode_1__0\,
modf_strobe_int => modf_strobe_int,
\out\ => \USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\,
p_0_out => p_0_out,
p_2_out => p_2_out,
p_5_out => p_5_out,
\qspi_cntrl_ps_reg[0]_0\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_9\,
\qspi_cntrl_ps_reg[1]_0\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_CONTROL_LOGIC_I_n_40\,
\qspo_int_reg[10]\(6) => Data_Dir_int,
\qspo_int_reg[10]\(5) => Data_Mode_1_int,
\qspo_int_reg[10]\(4) => Data_Mode_0_int,
\qspo_int_reg[10]\(3) => Data_Phase_int,
\qspo_int_reg[10]\(2) => Addr_Mode_1_int,
\qspo_int_reg[10]\(1) => Addr_Mode_0_int,
\qspo_int_reg[10]\(0) => Addr_Phase_int,
\qspo_int_reg[3]\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_10\,
\qspo_int_reg[5]\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_12\,
\qspo_int_reg[5]_0\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_15\,
\qspo_int_reg[6]\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_14\,
\qspo_int_reg[9]\ => \LOGIC_FOR_MD_12_GEN.SPI_MODE_1_LUT_LOGIC_I_n_1\,
ram_full_fb_i_reg => \FIFO_EXISTS.RX_FIFO_II_n_2\,
ram_full_i_reg => Rx_FIFO_Full_Fifo_org,
register_Data_slvsel_int => register_Data_slvsel_int,
sck_o => sck_o,
sck_t => sck_t,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain,
\^spixfer_done_int\ => \^spixfer_done_int\,
spicr_3_cpol_to_spi_clk => spicr_3_cpol_to_spi_clk,
spicr_4_cpha_to_spi_clk => spicr_4_cpha_to_spi_clk,
spicr_8_tr_inhibit_to_spi_clk => spicr_8_tr_inhibit_to_spi_clk,
spisel => spisel,
spisel_d1_reg => spisel_d1_reg,
ss_o(0) => ss_o(0),
ss_t => ss_t,
stop_clock => stop_clock,
transfer_start => transfer_start,
transfer_start_d1 => transfer_start_d1,
transfer_start_d2 => transfer_start_d2
);
RESET_SYNC_AXI_SPI_CLK_INST: entity work.system_axi_quad_spi_flash_0_reset_sync_module
port map (
Rst_to_spi => rst_to_spi_int,
ext_spi_clk => ext_spi_clk,
reset2ip_reset_int => reset2ip_reset_int
);
SOFT_RESET_I: entity work.system_axi_quad_spi_flash_0_soft_reset
port map (
Bus_RNW_reg => Bus_RNW_reg,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
FF_WRACK_0 => \^ff_wrack\,
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_sig_reg\ => SOFT_RESET_I_n_5,
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\ => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
IP2Bus_WrAck_1 => IP2Bus_WrAck_1,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg\ => \^ip2bus_wrack_core_reg_1\,
Rx_FIFO_Full_Fifo_d1_flag => Rx_FIFO_Full_Fifo_d1_flag,
Rx_FIFO_Full_Fifo_d1_sig => Rx_FIFO_Full_Fifo_d1_sig,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
\data_is_non_reset_match__4\ => \data_is_non_reset_match__4\,
\icount_out_reg[3]\ => SOFT_RESET_I_n_2,
ip2Bus_WrAck_core_reg => ip2Bus_WrAck_core_reg,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
p_2_in_0 => p_2_in_0,
p_6_in => p_6_in,
ram_full_i_reg => \^gic0.gc1.count_reg[3]\,
reset_TxFIFO_ptr_int => reset_TxFIFO_ptr_int,
reset_trig0 => reset_trig0,
s_axi_aclk => s_axi_aclk,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced,
spiXfer_done_to_axi_1 => spiXfer_done_to_axi_1,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1
);
\STATUS_REG_MODE_12_GEN.STATUS_SLAVE_SEL_REG_I\: entity work.system_axi_quad_spi_flash_0_qspi_status_slave_sel_reg
port map (
Bus_RNW_reg_reg => Bus_RNW_reg_reg_1,
D(0) => ip2Bus_Data_1(27),
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\,
Q(0) => data_from_rx_fifo(3),
SPISSR_frm_axi_clk => \^spissr_frm_axi_clk\,
bus2ip_rdce_int(1 downto 0) => bus2ip_rdce_int(1 downto 0),
\ip_irpt_enable_reg_reg[4]\(0) => p_0_in7_in,
irpt_rdack144_out => irpt_rdack144_out,
modf_reg_0 => \FIFO_EXISTS.CLK_CROSS_I_n_27\,
p_15_in => p_15_in,
p_1_in26_in => p_1_in26_in,
reset2ip_reset_int => reset2ip_reset_int,
s_axi_aclk => s_axi_aclk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
sr_3_MODF_int => sr_3_MODF_int
);
ip2Bus_RdAck_intr_reg_hole_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_controller_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => reset2ip_reset_int
);
ip2Bus_RdAck_intr_reg_hole_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_RdAck_intr_reg_hole0,
Q => ip2Bus_RdAck_intr_reg_hole,
R => reset2ip_reset_int
);
ip2Bus_WrAck_intr_reg_hole_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_controller_wr_ce_or_reduce,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => reset2ip_reset_int
);
ip2Bus_WrAck_intr_reg_hole_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2Bus_WrAck_intr_reg_hole0,
Q => ip2Bus_WrAck_intr_reg_hole,
R => reset2ip_reset_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_axi_quad_spi_top is
port (
ss_t : out STD_LOGIC;
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_t : out STD_LOGIC;
sck_o : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
io0_o : out STD_LOGIC;
io1_o : out STD_LOGIC;
io2_o : out STD_LOGIC;
io3_o : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
io0_i : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
io1_i : in STD_LOGIC;
io2_i : in STD_LOGIC;
io3_i : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 14 downto 0 );
spisel : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_axi_quad_spi_top : entity is "axi_quad_spi_top";
end system_axi_quad_spi_flash_0_axi_quad_spi_top;
architecture STRUCTURE of system_axi_quad_spi_flash_0_axi_quad_spi_top is
signal \CONTROL_REG_I/SPICR_data_int_reg0\ : STD_LOGIC;
signal \FIFO_EXISTS.FIFO_IF_MODULE_I/Receive_ip2bus_error0\ : STD_LOGIC;
signal \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\ : STD_LOGIC;
signal \FIFO_EXISTS.FIFO_IF_MODULE_I/p_15_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/interrupt_wrce_strb\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/intr2bus_rdack0\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/ipif_glbl_irpt_enable_reg\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_rdack\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_rdack144_out\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_rdack_d1\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_wrack\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_wrack_d1\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_wrack_d11\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in10_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in16_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in19_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in22_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in25_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in11_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in14_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in17_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in23_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in29_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in8_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_39_out__0\ : STD_LOGIC;
signal IP2Bus_Data : STD_LOGIC_VECTOR ( 0 to 31 );
signal IP2Bus_Error : STD_LOGIC;
signal IP2Bus_Error_1 : STD_LOGIC;
signal \IP2Bus_RdAck_receive_enable__1\ : STD_LOGIC;
signal \IP2Bus_WrAck_transmit_enable__0\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_2_in\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_3_in\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_4_in\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_5_in\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_7_in\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_12\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_31\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_34\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_46\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_49\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_50\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_53\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_54\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_55\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_56\ : STD_LOGIC;
signal \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_39\ : STD_LOGIC;
signal Rx_FIFO_Empty : STD_LOGIC;
signal \SOFT_RESET_I/data_is_non_reset_match__4\ : STD_LOGIC;
signal \SOFT_RESET_I/reset_trig0\ : STD_LOGIC;
signal \SOFT_RESET_I/sw_rst_cond\ : STD_LOGIC;
signal \SOFT_RESET_I/sw_rst_cond_d1\ : STD_LOGIC;
signal SPISR_0_CMD_Error_to_axi_clk : STD_LOGIC;
signal SPISR_1_LOOP_Back_Error_int : STD_LOGIC;
signal SPISR_2_MSB_Error_int : STD_LOGIC;
signal SPISSR_frm_axi_clk : STD_LOGIC;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : STD_LOGIC;
signal bus2ip_rdce_int : STD_LOGIC_VECTOR ( 7 downto 6 );
signal bus2ip_reset_ipif_inverted : STD_LOGIC;
signal bus2ip_wrce_int : STD_LOGIC_VECTOR ( 7 to 7 );
signal data_from_rx_fifo : STD_LOGIC_VECTOR ( 0 to 2 );
signal intr_controller_rd_ce_or_reduce : STD_LOGIC;
signal intr_controller_wr_ce_or_reduce : STD_LOGIC;
signal intr_ip2bus_data : STD_LOGIC_VECTOR ( 0 to 0 );
signal io0_i_sync : STD_LOGIC;
signal io1_i_sync : STD_LOGIC;
signal io2_i_sync : STD_LOGIC;
signal io3_i_sync : STD_LOGIC;
signal ip2Bus_Data_1 : STD_LOGIC_VECTOR ( 21 to 26 );
signal ip2Bus_RdAck_core_reg : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole0 : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_core_reg_1 : STD_LOGIC;
signal ip2Bus_WrAck_core_reg_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_out : STD_LOGIC;
signal rd_ce_or_reduce_core_cmb : STD_LOGIC;
signal reset2ip_reset_int : STD_LOGIC;
signal rx_fifo_empty_i : STD_LOGIC;
signal spicr_2_mst_n_slv_frm_axi_clk : STD_LOGIC;
signal spicr_5_txfifo_rst_frm_axi_clk : STD_LOGIC;
signal spicr_6_rxfifo_rst_frm_axi_clk : STD_LOGIC;
signal spicr_7_ss_frm_axi_clk : STD_LOGIC;
signal spicr_8_tr_inhibit_frm_axi_clk : STD_LOGIC;
signal spisel_d1_reg_to_axi_clk : STD_LOGIC;
signal tx_fifo_full : STD_LOGIC;
signal wr_ce_or_reduce_core_cmb : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of IO0_I_REG : label is "FD";
attribute box_type : string;
attribute box_type of IO0_I_REG : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of IO1_I_REG : label is "FD";
attribute box_type of IO1_I_REG : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of IO2_I_REG : label is "FD";
attribute box_type of IO2_I_REG : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of IO3_I_REG : label is "FD";
attribute box_type of IO3_I_REG : label is "PRIMITIVE";
begin
IO0_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => io0_i,
Q => io0_i_sync,
R => '0'
);
IO1_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => io1_i,
Q => io1_i_sync,
R => '0'
);
IO2_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => io2_i,
Q => io2_i_sync,
R => '0'
);
IO3_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => io3_i,
Q => io3_i_sync,
R => '0'
);
\QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I\: entity work.system_axi_quad_spi_flash_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_55\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_56\,
D(5) => intr_ip2bus_data(0),
D(4) => ip2Bus_Data_1(21),
D(3) => ip2Bus_Data_1(22),
D(2) => ip2Bus_Data_1(23),
D(1) => ip2Bus_Data_1(24),
D(0) => ip2Bus_Data_1(26),
E(0) => \INTERRUPT_CONTROL_I/irpt_wrack_d11\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_34\,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Error_1 => IP2Bus_Error_1,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(14) => IP2Bus_Data(0),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(13) => IP2Bus_Data(18),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(12) => IP2Bus_Data(19),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(11) => IP2Bus_Data(20),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(10) => IP2Bus_Data(21),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(9) => IP2Bus_Data(22),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(8) => IP2Bus_Data(23),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(7) => IP2Bus_Data(24),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(6) => IP2Bus_Data(25),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(5) => IP2Bus_Data(26),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(4) => IP2Bus_Data(27),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(3) => IP2Bus_Data(28),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(2) => IP2Bus_Data(29),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(1) => IP2Bus_Data(30),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[0]\(0) => IP2Bus_Data(31),
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[23]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_31\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[28]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_49\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[29]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_50\,
\LEGACY_MD_WR_RD_ACK_GEN.IP2Bus_WrAck_reg\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_46\,
\LEGACY_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_12\,
\LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2\ => SPISR_0_CMD_Error_to_axi_clk,
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ => spisel_d1_reg_to_axi_clk,
Q(1) => data_from_rx_fifo(0),
Q(0) => data_from_rx_fifo(2),
\RESET_FLOPS[15].RST_FLOPS\ => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_39\,
Receive_ip2bus_error0 => \FIFO_EXISTS.FIFO_IF_MODULE_I/Receive_ip2bus_error0\,
SPICR_data_int_reg0 => \CONTROL_REG_I/SPICR_data_int_reg0\,
SPISR_1_LOOP_Back_Error_int => SPISR_1_LOOP_Back_Error_int,
SPISR_2_MSB_Error_int => SPISR_2_MSB_Error_int,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_54\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
bus2ip_rdce_int(1 downto 0) => bus2ip_rdce_int(7 downto 6),
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
bus2ip_wrce_int(0) => bus2ip_wrce_int(7),
\data_is_non_reset_match__4\ => \SOFT_RESET_I/data_is_non_reset_match__4\,
empty_fwft_i_reg => Rx_FIFO_Empty,
interrupt_wrce_strb => \INTERRUPT_CONTROL_I/interrupt_wrce_strb\,
intr2bus_rdack0 => \INTERRUPT_CONTROL_I/intr2bus_rdack0\,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
intr_controller_wr_ce_or_reduce => intr_controller_wr_ce_or_reduce,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
\ip_irpt_enable_reg_reg[10]\(4) => \INTERRUPT_CONTROL_I/p_0_in25_in\,
\ip_irpt_enable_reg_reg[10]\(3) => \INTERRUPT_CONTROL_I/p_0_in22_in\,
\ip_irpt_enable_reg_reg[10]\(2) => \INTERRUPT_CONTROL_I/p_0_in19_in\,
\ip_irpt_enable_reg_reg[10]\(1) => \INTERRUPT_CONTROL_I/p_0_in16_in\,
\ip_irpt_enable_reg_reg[10]\(0) => \INTERRUPT_CONTROL_I/p_0_in10_in\,
ipif_glbl_irpt_enable_reg => \INTERRUPT_CONTROL_I/ipif_glbl_irpt_enable_reg\,
ipif_glbl_irpt_enable_reg_reg => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_53\,
irpt_rdack => \INTERRUPT_CONTROL_I/irpt_rdack\,
irpt_rdack144_out => \INTERRUPT_CONTROL_I/irpt_rdack144_out\,
irpt_rdack_d1 => \INTERRUPT_CONTROL_I/irpt_rdack_d1\,
irpt_wrack => \INTERRUPT_CONTROL_I/irpt_wrack\,
irpt_wrack_d1 => \INTERRUPT_CONTROL_I/irpt_wrack_d1\,
\out\ => tx_fifo_full,
p_10_out => p_10_out,
p_11_out => p_11_out,
p_15_in => \FIFO_EXISTS.FIFO_IF_MODULE_I/p_15_in\,
p_15_out => p_15_out,
p_16_out => p_16_out,
p_1_in11_in => \INTERRUPT_CONTROL_I/p_1_in11_in\,
p_1_in14_in => \INTERRUPT_CONTROL_I/p_1_in14_in\,
p_1_in17_in => \INTERRUPT_CONTROL_I/p_1_in17_in\,
p_1_in23_in => \INTERRUPT_CONTROL_I/p_1_in23_in\,
p_1_in29_in => \INTERRUPT_CONTROL_I/p_1_in29_in\,
p_1_in8_in => \INTERRUPT_CONTROL_I/p_1_in8_in\,
p_2_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_2_in\,
\p_39_out__0\ => \INTERRUPT_CONTROL_I/p_39_out__0\,
p_3_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_3_in\,
p_4_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_4_in\,
p_5_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_5_in\,
p_6_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\,
p_7_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_7_in\,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
reset2ip_reset_int => reset2ip_reset_int,
reset_trig0 => \SOFT_RESET_I/reset_trig0\,
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(14 downto 0) => s_axi_rdata(14 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(6) => s_axi_wdata(14),
s_axi_wdata(5 downto 4) => s_axi_wdata(6 downto 5),
s_axi_wdata(3 downto 0) => s_axi_wdata(3 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(1 downto 0) => s_axi_wstrb(1 downto 0),
s_axi_wvalid => s_axi_wvalid,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
sw_rst_cond => \SOFT_RESET_I/sw_rst_cond\,
sw_rst_cond_d1 => \SOFT_RESET_I/sw_rst_cond_d1\,
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
\QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I\: entity work.system_axi_quad_spi_flash_0_qspi_core_interface
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_12\,
Bus_RNW_reg_reg_0 => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_53\,
Bus_RNW_reg_reg_1 => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_54\,
Bus_RNW_reg_reg_2 => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_50\,
Bus_RNW_reg_reg_3 => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_49\,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_55\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_56\,
D(5) => intr_ip2bus_data(0),
D(4) => ip2Bus_Data_1(21),
D(3) => ip2Bus_Data_1(22),
D(2) => ip2Bus_Data_1(23),
D(1) => ip2Bus_Data_1(24),
D(0) => ip2Bus_Data_1(26),
E(0) => \INTERRUPT_CONTROL_I/irpt_wrack_d11\,
FF_WRACK => \QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I_n_39\,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => Rx_FIFO_Empty,
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_31\,
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_46\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \QSPI_LEGACY_MD_GEN.AXI_LITE_IPIF_I_n_34\,
IP2Bus_Error => IP2Bus_Error,
IP2Bus_Error_1 => IP2Bus_Error_1,
\IP2Bus_RdAck_receive_enable__1\ => \IP2Bus_RdAck_receive_enable__1\,
\IP2Bus_WrAck_transmit_enable__0\ => \IP2Bus_WrAck_transmit_enable__0\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]_0\(4) => \INTERRUPT_CONTROL_I/p_0_in25_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]_0\(3) => \INTERRUPT_CONTROL_I/p_0_in22_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]_0\(2) => \INTERRUPT_CONTROL_I/p_0_in19_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]_0\(1) => \INTERRUPT_CONTROL_I/p_0_in16_in\,
\LEGACY_MD_IP2BUS_DATA_GEN.IP2Bus_Data_reg[21]_0\(0) => \INTERRUPT_CONTROL_I/p_0_in10_in\,
Q(1) => data_from_rx_fifo(0),
Q(0) => data_from_rx_fifo(2),
Receive_ip2bus_error0 => \FIFO_EXISTS.FIFO_IF_MODULE_I/Receive_ip2bus_error0\,
SPICR_data_int_reg0 => \CONTROL_REG_I/SPICR_data_int_reg0\,
SPISR_1_LOOP_Back_Error_int => SPISR_1_LOOP_Back_Error_int,
SPISR_2_MSB_Error_int => SPISR_2_MSB_Error_int,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
bus2ip_rdce_int(1 downto 0) => bus2ip_rdce_int(7 downto 6),
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
bus2ip_wrce_int(0) => bus2ip_wrce_int(7),
\data_is_non_reset_match__4\ => \SOFT_RESET_I/data_is_non_reset_match__4\,
ext_spi_clk => ext_spi_clk,
\gic0.gc1.count_reg[3]\ => tx_fifo_full,
interrupt_wrce_strb => \INTERRUPT_CONTROL_I/interrupt_wrce_strb\,
intr2bus_rdack0 => \INTERRUPT_CONTROL_I/intr2bus_rdack0\,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
intr_controller_wr_ce_or_reduce => intr_controller_wr_ce_or_reduce,
io0_i_sync => io0_i_sync,
io0_o => io0_o,
io0_t => io0_t,
io1_i_sync => io1_i_sync,
io1_o => io1_o,
io1_t => io1_t,
io2_i_sync => io2_i_sync,
io2_o => io2_o,
io2_t => io2_t,
io3_i_sync => io3_i_sync,
io3_o => io3_o,
io3_t => io3_t,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg_1 => ip2Bus_WrAck_core_reg_1,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2intc_irpt => ip2intc_irpt,
\ip_irpt_enable_reg_reg[8]\ => spisel_d1_reg_to_axi_clk,
ipif_glbl_irpt_enable_reg => \INTERRUPT_CONTROL_I/ipif_glbl_irpt_enable_reg\,
irpt_rdack => \INTERRUPT_CONTROL_I/irpt_rdack\,
irpt_rdack144_out => \INTERRUPT_CONTROL_I/irpt_rdack144_out\,
irpt_rdack_d1 => \INTERRUPT_CONTROL_I/irpt_rdack_d1\,
irpt_wrack => \INTERRUPT_CONTROL_I/irpt_wrack\,
irpt_wrack_d1 => \INTERRUPT_CONTROL_I/irpt_wrack_d1\,
\out\ => SPISR_0_CMD_Error_to_axi_clk,
p_10_out => p_10_out,
p_11_out => p_11_out,
p_15_in => \FIFO_EXISTS.FIFO_IF_MODULE_I/p_15_in\,
p_15_out => p_15_out,
p_16_out => p_16_out,
p_1_in11_in => \INTERRUPT_CONTROL_I/p_1_in11_in\,
p_1_in14_in => \INTERRUPT_CONTROL_I/p_1_in14_in\,
p_1_in17_in => \INTERRUPT_CONTROL_I/p_1_in17_in\,
p_1_in23_in => \INTERRUPT_CONTROL_I/p_1_in23_in\,
p_1_in29_in => \INTERRUPT_CONTROL_I/p_1_in29_in\,
p_1_in8_in => \INTERRUPT_CONTROL_I/p_1_in8_in\,
p_2_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_2_in\,
\p_39_out__0\ => \INTERRUPT_CONTROL_I/p_39_out__0\,
p_3_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_3_in\,
p_4_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_4_in\,
p_5_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_5_in\,
p_6_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_6_in\,
p_7_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_7_in\,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
reset2ip_reset_int => reset2ip_reset_int,
reset_trig0 => \SOFT_RESET_I/reset_trig0\,
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi_aclk => s_axi_aclk,
\s_axi_rdata_i_reg[31]\(14) => IP2Bus_Data(0),
\s_axi_rdata_i_reg[31]\(13) => IP2Bus_Data(18),
\s_axi_rdata_i_reg[31]\(12) => IP2Bus_Data(19),
\s_axi_rdata_i_reg[31]\(11) => IP2Bus_Data(20),
\s_axi_rdata_i_reg[31]\(10) => IP2Bus_Data(21),
\s_axi_rdata_i_reg[31]\(9) => IP2Bus_Data(22),
\s_axi_rdata_i_reg[31]\(8) => IP2Bus_Data(23),
\s_axi_rdata_i_reg[31]\(7) => IP2Bus_Data(24),
\s_axi_rdata_i_reg[31]\(6) => IP2Bus_Data(25),
\s_axi_rdata_i_reg[31]\(5) => IP2Bus_Data(26),
\s_axi_rdata_i_reg[31]\(4) => IP2Bus_Data(27),
\s_axi_rdata_i_reg[31]\(3) => IP2Bus_Data(28),
\s_axi_rdata_i_reg[31]\(2) => IP2Bus_Data(29),
\s_axi_rdata_i_reg[31]\(1) => IP2Bus_Data(30),
\s_axi_rdata_i_reg[31]\(0) => IP2Bus_Data(31),
s_axi_wdata(13 downto 0) => s_axi_wdata(13 downto 0),
sck_o => sck_o,
sck_t => sck_t,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
spisel => spisel,
ss_o(0) => ss_o(0),
ss_t => ss_t,
sw_rst_cond => \SOFT_RESET_I/sw_rst_cond\,
sw_rst_cond_d1 => \SOFT_RESET_I/sw_rst_cond_d1\,
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0_axi_quad_spi is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi4_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_awaddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_awlock : in STD_LOGIC;
s_axi4_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awvalid : in STD_LOGIC;
s_axi4_awready : out STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_wlast : in STD_LOGIC;
s_axi4_wvalid : in STD_LOGIC;
s_axi4_wready : out STD_LOGIC;
s_axi4_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_bvalid : out STD_LOGIC;
s_axi4_bready : in STD_LOGIC;
s_axi4_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_araddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_arlock : in STD_LOGIC;
s_axi4_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arvalid : in STD_LOGIC;
s_axi4_arready : out STD_LOGIC;
s_axi4_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_rlast : out STD_LOGIC;
s_axi4_rvalid : out STD_LOGIC;
s_axi4_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_i : in STD_LOGIC;
io2_o : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_i : in STD_LOGIC;
io3_o : out STD_LOGIC;
io3_t : out STD_LOGIC;
io0_1_i : in STD_LOGIC;
io0_1_o : out STD_LOGIC;
io0_1_t : out STD_LOGIC;
io1_1_i : in STD_LOGIC;
io1_1_o : out STD_LOGIC;
io1_1_t : out STD_LOGIC;
io2_1_i : in STD_LOGIC;
io2_1_o : out STD_LOGIC;
io2_1_t : out STD_LOGIC;
io3_1_i : in STD_LOGIC;
io3_1_o : out STD_LOGIC;
io3_1_t : out STD_LOGIC;
spisel : in STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ss_1_i : in STD_LOGIC;
ss_1_o : out STD_LOGIC;
ss_1_t : out STD_LOGIC;
cfgclk : out STD_LOGIC;
cfgmclk : out STD_LOGIC;
eos : out STD_LOGIC;
preq : out STD_LOGIC;
clk : in STD_LOGIC;
gsr : in STD_LOGIC;
gts : in STD_LOGIC;
keyclearb : in STD_LOGIC;
usrcclkts : in STD_LOGIC;
usrdoneo : in STD_LOGIC;
usrdonets : in STD_LOGIC;
pack : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
attribute Async_Clk : integer;
attribute Async_Clk of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_DUAL_QUAD_MODE : integer;
attribute C_DUAL_QUAD_MODE of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_quad_spi_flash_0_axi_quad_spi : entity is "artix7";
attribute C_FIFO_DEPTH : integer;
attribute C_FIFO_DEPTH of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 16;
attribute C_INSTANCE : string;
attribute C_INSTANCE of system_axi_quad_spi_flash_0_axi_quad_spi : entity is "axi_quad_spi_inst";
attribute C_LSB_STUP : integer;
attribute C_LSB_STUP of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_NUM_SS_BITS : integer;
attribute C_NUM_SS_BITS of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 1;
attribute C_NUM_TRANSFER_BITS : integer;
attribute C_NUM_TRANSFER_BITS of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 8;
attribute C_SCK_RATIO : integer;
attribute C_SCK_RATIO of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 2;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_SHARED_STARTUP : integer;
attribute C_SHARED_STARTUP of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_SPI_MEMORY : integer;
attribute C_SPI_MEMORY of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 1;
attribute C_SPI_MEM_ADDR_BITS : integer;
attribute C_SPI_MEM_ADDR_BITS of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 24;
attribute C_SPI_MODE : integer;
attribute C_SPI_MODE of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 2;
attribute C_SUB_FAMILY : string;
attribute C_SUB_FAMILY of system_axi_quad_spi_flash_0_axi_quad_spi : entity is "artix7";
attribute C_S_AXI4_ADDR_WIDTH : integer;
attribute C_S_AXI4_ADDR_WIDTH of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 24;
attribute C_S_AXI4_BASEADDR : integer;
attribute C_S_AXI4_BASEADDR of system_axi_quad_spi_flash_0_axi_quad_spi : entity is -1;
attribute C_S_AXI4_DATA_WIDTH : integer;
attribute C_S_AXI4_DATA_WIDTH of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 32;
attribute C_S_AXI4_HIGHADDR : integer;
attribute C_S_AXI4_HIGHADDR of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_S_AXI4_ID_WIDTH : integer;
attribute C_S_AXI4_ID_WIDTH of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 7;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 32;
attribute C_TYPE_OF_AXI4_INTERFACE : integer;
attribute C_TYPE_OF_AXI4_INTERFACE of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_UC_FAMILY : integer;
attribute C_UC_FAMILY of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_USE_STARTUP : integer;
attribute C_USE_STARTUP of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_USE_STARTUP_EXT : integer;
attribute C_USE_STARTUP_EXT of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute C_XIP_MODE : integer;
attribute C_XIP_MODE of system_axi_quad_spi_flash_0_axi_quad_spi : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_quad_spi_flash_0_axi_quad_spi : entity is "axi_quad_spi";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_quad_spi_flash_0_axi_quad_spi : entity is "yes";
end system_axi_quad_spi_flash_0_axi_quad_spi;
architecture STRUCTURE of system_axi_quad_spi_flash_0_axi_quad_spi is
signal \<const0>\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
cfgclk <= \<const0>\;
cfgmclk <= \<const0>\;
eos <= \<const0>\;
io0_1_o <= \<const0>\;
io0_1_t <= \<const0>\;
io1_1_o <= \<const0>\;
io1_1_t <= \<const0>\;
io2_1_o <= \<const0>\;
io2_1_t <= \<const0>\;
io3_1_o <= \<const0>\;
io3_1_t <= \<const0>\;
preq <= \<const0>\;
s_axi4_arready <= \<const0>\;
s_axi4_awready <= \<const0>\;
s_axi4_bid(0) <= \<const0>\;
s_axi4_bresp(1) <= \<const0>\;
s_axi4_bresp(0) <= \<const0>\;
s_axi4_bvalid <= \<const0>\;
s_axi4_rdata(31) <= \<const0>\;
s_axi4_rdata(30) <= \<const0>\;
s_axi4_rdata(29) <= \<const0>\;
s_axi4_rdata(28) <= \<const0>\;
s_axi4_rdata(27) <= \<const0>\;
s_axi4_rdata(26) <= \<const0>\;
s_axi4_rdata(25) <= \<const0>\;
s_axi4_rdata(24) <= \<const0>\;
s_axi4_rdata(23) <= \<const0>\;
s_axi4_rdata(22) <= \<const0>\;
s_axi4_rdata(21) <= \<const0>\;
s_axi4_rdata(20) <= \<const0>\;
s_axi4_rdata(19) <= \<const0>\;
s_axi4_rdata(18) <= \<const0>\;
s_axi4_rdata(17) <= \<const0>\;
s_axi4_rdata(16) <= \<const0>\;
s_axi4_rdata(15) <= \<const0>\;
s_axi4_rdata(14) <= \<const0>\;
s_axi4_rdata(13) <= \<const0>\;
s_axi4_rdata(12) <= \<const0>\;
s_axi4_rdata(11) <= \<const0>\;
s_axi4_rdata(10) <= \<const0>\;
s_axi4_rdata(9) <= \<const0>\;
s_axi4_rdata(8) <= \<const0>\;
s_axi4_rdata(7) <= \<const0>\;
s_axi4_rdata(6) <= \<const0>\;
s_axi4_rdata(5) <= \<const0>\;
s_axi4_rdata(4) <= \<const0>\;
s_axi4_rdata(3) <= \<const0>\;
s_axi4_rdata(2) <= \<const0>\;
s_axi4_rdata(1) <= \<const0>\;
s_axi4_rdata(0) <= \<const0>\;
s_axi4_rid(0) <= \<const0>\;
s_axi4_rlast <= \<const0>\;
s_axi4_rresp(1) <= \<const0>\;
s_axi4_rresp(0) <= \<const0>\;
s_axi4_rvalid <= \<const0>\;
s_axi4_wready <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \^s_axi_bresp\(1);
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(31);
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13 downto 0) <= \^s_axi_rdata\(13 downto 0);
s_axi_rresp(1) <= \^s_axi_rresp\(1);
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
ss_1_o <= \<const0>\;
ss_1_t <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\NO_DUAL_QUAD_MODE.QSPI_NORMAL\: entity work.system_axi_quad_spi_flash_0_axi_quad_spi_top
port map (
ext_spi_clk => ext_spi_clk,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => io2_i,
io2_o => io2_o,
io2_t => io2_t,
io3_i => io3_i,
io3_o => io3_o,
io3_t => io3_t,
ip2intc_irpt => ip2intc_irpt,
s_axi4_aclk => s_axi4_aclk,
s_axi4_aresetn => s_axi4_aresetn,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(6 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(6 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(1),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(14) => \^s_axi_rdata\(31),
s_axi_rdata(13 downto 0) => \^s_axi_rdata\(13 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => \^s_axi_rresp\(1),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(14) => s_axi_wdata(31),
s_axi_wdata(13 downto 0) => s_axi_wdata(13 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(1) => s_axi_wstrb(3),
s_axi_wstrb(0) => s_axi_wstrb(0),
s_axi_wvalid => s_axi_wvalid,
sck_o => sck_o,
sck_t => sck_t,
spisel => spisel,
ss_o(0) => ss_o(0),
ss_t => ss_t
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_quad_spi_flash_0 is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_i : in STD_LOGIC;
io2_o : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_i : in STD_LOGIC;
io3_o : out STD_LOGIC;
io3_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_quad_spi_flash_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_quad_spi_flash_0 : entity is "system_axi_quad_spi_flash_0,axi_quad_spi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_quad_spi_flash_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_quad_spi_flash_0 : entity is "axi_quad_spi,Vivado 2016.4";
end system_axi_quad_spi_flash_0;
architecture STRUCTURE of system_axi_quad_spi_flash_0 is
signal NLW_U0_cfgclk_UNCONNECTED : STD_LOGIC;
signal NLW_U0_cfgmclk_UNCONNECTED : STD_LOGIC;
signal NLW_U0_eos_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io0_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io0_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io1_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io1_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_preq_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ss_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ss_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi4_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi4_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi4_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi4_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute Async_Clk : integer;
attribute Async_Clk of U0 : label is 0;
attribute C_DUAL_QUAD_MODE : integer;
attribute C_DUAL_QUAD_MODE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FIFO_DEPTH : integer;
attribute C_FIFO_DEPTH of U0 : label is 16;
attribute C_INSTANCE : string;
attribute C_INSTANCE of U0 : label is "axi_quad_spi_inst";
attribute C_LSB_STUP : integer;
attribute C_LSB_STUP of U0 : label is 0;
attribute C_NUM_SS_BITS : integer;
attribute C_NUM_SS_BITS of U0 : label is 1;
attribute C_NUM_TRANSFER_BITS : integer;
attribute C_NUM_TRANSFER_BITS of U0 : label is 8;
attribute C_SCK_RATIO : integer;
attribute C_SCK_RATIO of U0 : label is 2;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SHARED_STARTUP : integer;
attribute C_SHARED_STARTUP of U0 : label is 0;
attribute C_SPI_MEMORY : integer;
attribute C_SPI_MEMORY of U0 : label is 1;
attribute C_SPI_MEM_ADDR_BITS : integer;
attribute C_SPI_MEM_ADDR_BITS of U0 : label is 24;
attribute C_SPI_MODE : integer;
attribute C_SPI_MODE of U0 : label is 2;
attribute C_SUB_FAMILY : string;
attribute C_SUB_FAMILY of U0 : label is "artix7";
attribute C_S_AXI4_ADDR_WIDTH : integer;
attribute C_S_AXI4_ADDR_WIDTH of U0 : label is 24;
attribute C_S_AXI4_BASEADDR : integer;
attribute C_S_AXI4_BASEADDR of U0 : label is -1;
attribute C_S_AXI4_DATA_WIDTH : integer;
attribute C_S_AXI4_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI4_HIGHADDR : integer;
attribute C_S_AXI4_HIGHADDR of U0 : label is 0;
attribute C_S_AXI4_ID_WIDTH : integer;
attribute C_S_AXI4_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 7;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TYPE_OF_AXI4_INTERFACE : integer;
attribute C_TYPE_OF_AXI4_INTERFACE of U0 : label is 0;
attribute C_UC_FAMILY : integer;
attribute C_UC_FAMILY of U0 : label is 0;
attribute C_USE_STARTUP : integer;
attribute C_USE_STARTUP of U0 : label is 0;
attribute C_USE_STARTUP_EXT : integer;
attribute C_USE_STARTUP_EXT of U0 : label is 0;
attribute C_XIP_MODE : integer;
attribute C_XIP_MODE of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_axi_quad_spi_flash_0_axi_quad_spi
port map (
cfgclk => NLW_U0_cfgclk_UNCONNECTED,
cfgmclk => NLW_U0_cfgmclk_UNCONNECTED,
clk => '0',
eos => NLW_U0_eos_UNCONNECTED,
ext_spi_clk => ext_spi_clk,
gsr => '0',
gts => '0',
io0_1_i => '0',
io0_1_o => NLW_U0_io0_1_o_UNCONNECTED,
io0_1_t => NLW_U0_io0_1_t_UNCONNECTED,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_1_i => '0',
io1_1_o => NLW_U0_io1_1_o_UNCONNECTED,
io1_1_t => NLW_U0_io1_1_t_UNCONNECTED,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_1_i => '0',
io2_1_o => NLW_U0_io2_1_o_UNCONNECTED,
io2_1_t => NLW_U0_io2_1_t_UNCONNECTED,
io2_i => io2_i,
io2_o => io2_o,
io2_t => io2_t,
io3_1_i => '0',
io3_1_o => NLW_U0_io3_1_o_UNCONNECTED,
io3_1_t => NLW_U0_io3_1_t_UNCONNECTED,
io3_i => io3_i,
io3_o => io3_o,
io3_t => io3_t,
ip2intc_irpt => ip2intc_irpt,
keyclearb => '0',
pack => '0',
preq => NLW_U0_preq_UNCONNECTED,
s_axi4_aclk => '0',
s_axi4_araddr(23 downto 0) => B"000000000000000000000000",
s_axi4_arburst(1 downto 0) => B"00",
s_axi4_arcache(3 downto 0) => B"0000",
s_axi4_aresetn => '0',
s_axi4_arid(0) => '0',
s_axi4_arlen(7 downto 0) => B"00000000",
s_axi4_arlock => '0',
s_axi4_arprot(2 downto 0) => B"000",
s_axi4_arready => NLW_U0_s_axi4_arready_UNCONNECTED,
s_axi4_arsize(2 downto 0) => B"000",
s_axi4_arvalid => '0',
s_axi4_awaddr(23 downto 0) => B"000000000000000000000000",
s_axi4_awburst(1 downto 0) => B"00",
s_axi4_awcache(3 downto 0) => B"0000",
s_axi4_awid(0) => '0',
s_axi4_awlen(7 downto 0) => B"00000000",
s_axi4_awlock => '0',
s_axi4_awprot(2 downto 0) => B"000",
s_axi4_awready => NLW_U0_s_axi4_awready_UNCONNECTED,
s_axi4_awsize(2 downto 0) => B"000",
s_axi4_awvalid => '0',
s_axi4_bid(0) => NLW_U0_s_axi4_bid_UNCONNECTED(0),
s_axi4_bready => '0',
s_axi4_bresp(1 downto 0) => NLW_U0_s_axi4_bresp_UNCONNECTED(1 downto 0),
s_axi4_bvalid => NLW_U0_s_axi4_bvalid_UNCONNECTED,
s_axi4_rdata(31 downto 0) => NLW_U0_s_axi4_rdata_UNCONNECTED(31 downto 0),
s_axi4_rid(0) => NLW_U0_s_axi4_rid_UNCONNECTED(0),
s_axi4_rlast => NLW_U0_s_axi4_rlast_UNCONNECTED,
s_axi4_rready => '0',
s_axi4_rresp(1 downto 0) => NLW_U0_s_axi4_rresp_UNCONNECTED(1 downto 0),
s_axi4_rvalid => NLW_U0_s_axi4_rvalid_UNCONNECTED,
s_axi4_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi4_wlast => '0',
s_axi4_wready => NLW_U0_s_axi4_wready_UNCONNECTED,
s_axi4_wstrb(3 downto 0) => B"0000",
s_axi4_wvalid => '0',
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
spisel => '1',
ss_1_i => '0',
ss_1_o => NLW_U0_ss_1_o_UNCONNECTED,
ss_1_t => NLW_U0_ss_1_t_UNCONNECTED,
ss_i(0) => ss_i(0),
ss_o(0) => ss_o(0),
ss_t => ss_t,
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0'
);
end STRUCTURE;
|
apache-2.0
|
680741df5a4ae19e87ddb9560769ed7e
| 0.595852 | 2.584948 | false | false | false | false |
daniw/add
|
rot_enc/cpu.vhd
| 3 | 2,610 |
-------------------------------------------------------------------------------
-- Entity: cpu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Top-level of CPU for simple von-Neumann MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
bus_in : in t_bus2cpu;
bus_out : out t_cpu2bus
);
end cpu;
architecture rtl of cpu is
signal ctr2prc : t_ctr2prc;
signal prc2ctr : t_prc2ctr;
signal ctr2alu : t_ctr2alu;
signal alu2ctr : t_alu2ctr;
signal ctr2reg : t_ctr2reg;
signal reg2ctr : t_reg2ctr;
signal alu_res, alu_op1, alu_op2 : std_logic_vector(DW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- Control Unit--------------------------------------------------------------
i_ctrl: entity work.cpu_ctrl
port map(
rst => rst,
clk => clk,
data_in => bus_in.data,
addr => bus_out.addr,
data_out => bus_out.data,
rd_enb => bus_out.rd_enb,
wr_enb => bus_out.wr_enb,
reg_in => reg2ctr,
reg_out => ctr2reg,
prc_in => prc2ctr,
prc_out => ctr2prc,
alu_in => alu2ctr,
alu_out => ctr2alu
);
-- Address Generation -------------------------------------------------------
i_prc: entity work.cpu_prc
port map(
rst => rst,
clk => clk,
ctr_in => ctr2prc,
ctr_out => prc2ctr
);
-- ALU ----------------------------------------------------------------------
i_alu: entity work.cpu_alu
port map(
rst => rst,
clk => clk,
alu_in => ctr2alu,
alu_out => alu2ctr,
oper1 => alu_op1,
oper2 => alu_op2,
result => alu_res
);
-- Register Block -----------------------------------------------------------
i_reg: entity work.cpu_reg
port map(
rst => rst,
clk => clk,
reg_in => ctr2reg,
reg_out => reg2ctr,
alu_res => alu_res,
alu_op1 => alu_op1,
alu_op2 => alu_op2
);
end rtl;
|
gpl-2.0
|
7d805f80debe4c033aa2bf8888f96be9
| 0.383142 | 3.990826 | false | false | false | false |
jeffmagina/ECE368
|
Project1/CONTROL_UNIT/control_unit.vhd
| 1 | 2,632 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Josh Tombs
--
-- Create Date: SPRING 2015
-- Module Name: ControlUnit
-- Project Name: UMD_RISC16
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Control unit for RISC16.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity control_unit is
Port( CLK : IN STD_LOGIC;
OPA_OPCODE : IN STD_LOGIC_VECTOR(3 downto 0);
OP1_MUX_SEL : OUT STD_LOGIC_VECTOR(1 downto 0);
OP2_MUX_SEL : OUT STD_LOGIC_VECTOR(1 downto 0);
REG_BANK_WE : OUT STD_LOGIC;
DATA_MEM_WE : OUT STD_LOGIC;
WB_OPCODE : IN STD_LOGIC_VECTOR(3 downto 0);
OPA_D_OUT_SEL : OUT STD_LOGIC
);
end control_unit;
architecture Behavioral of control_unit is
begin
OPA: PROCESS(CLK)
begin
if(CLK'EVENT and CLK = '1') then
OP1_MUX_SEL <= "00" ;
case OPA_OPCODE is
when "0000" => OP2_MUX_SEL <= "00";
when "0001" => OP2_MUX_SEL <= "00";
when "0010" => OP2_MUX_SEL <= "00";
when "0011" => OP2_MUX_SEL <= "00";
when "0100" => OP2_MUX_SEL <= "00";
when "0101" => OP2_MUX_SEL <= "01";
when "0110" => OP2_MUX_SEL <= "01";
when "0111" => OP2_MUX_SEL <= "10";
when "1000" => OP2_MUX_SEL <= "10";
when "1001" => OP2_MUX_SEL <= "01";
when "1010" => OP2_MUX_SEL <= "01";
when others => OP2_MUX_SEL <= "01";
end case;
end if;
end PROCESS;
WB: PROCESS(CLK)
begin
if(CLK'EVENT and CLK = '1') then
case WB_OPCODE is
when "0000"|"0001"|"0010"|"0011"|"0100"|"0101"|"0110"|"0111"|"1000" =>
OPA_D_OUT_SEL <= '1';
DATA_MEM_WE <= '0';
REG_BANK_WE <= '1';
when "1001" =>
OPA_D_OUT_SEL <= '0';
DATA_MEM_WE <= '0';
REG_BANK_WE <= '1';
when "1010" =>
OPA_D_OUT_SEL <= '0';
DATA_MEM_WE <= '1';
REG_BANK_WE <= '0';
when others =>
OPA_D_OUT_SEL <= '1';
DATA_MEM_WE <= '0';
REG_BANK_WE <= '0';
end case;
end if;
end PROCESS;
end Behavioral;
|
mit
|
7639f085cc9f5e1fef0c533c35a9bba9
| 0.43693 | 3.670851 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALU/alu_tb.vhd
| 1 | 7,475 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_TB
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY ALU_tb_vhd IS
END ALU_tb_vhd;
ARCHITECTURE behavior OF ALU_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR(7 downto 0);
RB : in STD_LOGIC_VECTOR(7 downto 0);
OPCODE : in STD_LOGIC_VECTOR(3 downto 0);
CCR : out STD_LOGIC_VECTOR(3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR(7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR(7 downto 0));
END COMPONENT;
--Inputs
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RA : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL RB : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
SIGNAL OPCODE : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
--Outputs
SIGNAL CCR : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL ALU_OUT : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL LDST_OUT : STD_LOGIC_VECTOR(7 downto 0);
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
--Condition Codes
SIGNAL N : STD_LOGIC := '0';
SIGNAL Z : STD_LOGIC := '0';
SIGNAL V : STD_LOGIC := '0';
SIGNAL C : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP( CLK => CLK,
RA => RA,
RB => RB,
OPCODE => OPCODE,
CCR => CCR,
ALU_OUT => ALU_OUT,
LDST_OUT => LDST_OUT);
-- Assign condition code bits
N <= CCR(3); -- N - Negative
Z <= CCR(2); -- Z - Zero
V <= CCR(1); -- V - Overflow
C <= CCR(0); -- C - Carry/Borrow
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Start ALU Test Bench" severity NOTE;
----- Register-Register Arithmetic Tests -----
RA <= "00000101"; -- 5
RB <= "00000011"; -- 3
OPCODE <= "0000"; wait for period;
assert (ALU_OUT = 8) report "Failed ADD 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed ADD 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0001"; wait for period;
assert (ALU_OUT = 2) report "Failed SUB 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed SUB 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0010"; wait for period;
assert (ALU_OUT = 1) report "Failed AND 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed AND 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0011"; wait for period;
assert (ALU_OUT = 7) report "Failed OR 1. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed OR 1 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "01100100"; -- 100
RB <= "00110010"; -- 50
OPCODE <= "0000"; wait for period;
assert (ALU_OUT = 150) report "Failed ADD 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "1010") report "Failed ADD 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0001"; wait for period;
assert (ALU_OUT = 50) report "Failed SUB 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed SUB 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0010"; wait for period;
assert (ALU_OUT = "0000000000100000") report "Failed AND 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed AND 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "0011"; wait for period;
assert (ALU_OUT = "0000000001110110") report "Failed OR 2. ALU_OUT=" & integer'image(to_integer(unsigned(ALU_OUT))) severity ERROR;
assert (CCR = "0000") report "Failed OR 2 - CCR. CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
----- END Arithmetic Tests -----
----- CCR Tests -----
RA <= "00000000";
RB <= "00000000";
OPCODE <= "0000"; wait for period;
assert (CCR(2) = '1') report "Failed CCR 1 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "00000001";
RB <= "11111111";
OPCODE <= "0000"; wait for period;
assert (Z = '1') report "Failed CCR 2 (Z). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
assert (C = '1') report "Failed CCR 3 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "00000000";
RB <= "00000001";
OPCODE <= "0001"; wait for period;
assert (N = '1') report "Failed CCR 4 (N). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "01111111";
RB <= "00000001";
OPCODE <= "0000"; wait for period;
assert (V = '1') report "Failed CCR 5 (V). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= "11111111";
RB <= "00000001";
OPCODE <= "0000"; wait for period;
assert (C = '1') report "Failed CCR 6 (C). CCR=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
----- END CCR Tests -----
-- Mem Test --
OPCODE <= "1001"; wait for period;
assert (ALU_OUT = 0) report "Failed MEMORY READ(1) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
RA <= X"16";
OPCODE <= "1010"; wait for period;
assert (ALU_OUT = 0) report "Failed MEMORY WRITE ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
OPCODE <= "1001"; wait for period;
assert (ALU_OUT = X"16") report "Failed MEMORY READ(2) ALU_OUT=" & integer'image(to_integer(unsigned(CCR))) severity ERROR;
-- END Mem Test --
report "Finish ALU Test Bench" severity NOTE;
wait; -- will wait forever
END PROCESS;
END;
|
mit
|
b590dd6b7bb58d59978f457b2cb047f0
| 0.550635 | 3.815722 | false | true | false | false |
jeffmagina/ECE368
|
Project1/EXECUTE/ALU/alu_toplevel.vhd
| 1 | 2,586 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (15 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(3 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
mit
|
2e63f88873fd5a4389a75e5f8bab8777
| 0.493813 | 3.894578 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_quad_spi_flash_0/sim/system_axi_quad_spi_flash_0.vhd
| 1 | 16,599 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_10;
USE axi_quad_spi_v3_2_10.axi_quad_spi;
ENTITY system_axi_quad_spi_flash_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_axi_quad_spi_flash_0;
ARCHITECTURE system_axi_quad_spi_flash_0_arch OF system_axi_quad_spi_flash_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_quad_spi_flash_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_DUAL_QUAD_MODE : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_USE_STARTUP_EXT : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
io0_1_i : IN STD_LOGIC;
io0_1_o : OUT STD_LOGIC;
io0_1_t : OUT STD_LOGIC;
io1_1_i : IN STD_LOGIC;
io1_1_o : OUT STD_LOGIC;
io1_1_t : OUT STD_LOGIC;
io2_1_i : IN STD_LOGIC;
io2_1_o : OUT STD_LOGIC;
io2_1_t : OUT STD_LOGIC;
io3_1_i : IN STD_LOGIC;
io3_1_o : OUT STD_LOGIC;
io3_1_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ss_1_i : IN STD_LOGIC;
ss_1_o : OUT STD_LOGIC;
ss_1_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF io2_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_I";
ATTRIBUTE X_INTERFACE_INFO OF io2_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_O";
ATTRIBUTE X_INTERFACE_INFO OF io2_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO2_T";
ATTRIBUTE X_INTERFACE_INFO OF io3_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_I";
ATTRIBUTE X_INTERFACE_INFO OF io3_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_O";
ATTRIBUTE X_INTERFACE_INFO OF io3_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO3_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 0,
C_FAMILY => "artix7",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "artix7",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 2,
C_DUAL_QUAD_MODE => 0,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 2,
C_USE_STARTUP => 0,
C_USE_STARTUP_EXT => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => io2_i,
io2_o => io2_o,
io2_t => io2_t,
io3_i => io3_i,
io3_o => io3_o,
io3_t => io3_t,
io0_1_i => '0',
io1_1_i => '0',
io2_1_i => '0',
io3_1_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ss_1_i => '0',
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END system_axi_quad_spi_flash_0_arch;
|
apache-2.0
|
c9893d9679ee64808f9821cf5e31ee8d
| 0.636544 | 2.979002 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/axi_pkg.vhd
| 1 | 9,142 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/19/2016
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This is the package for the AXI interfaces.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Changed indentation
-- Revision 0.3 - Updated package name
-- Added constants, subprograms and interface definition
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package axi is
------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------
constant cslv_axsize_1 : std_logic_vector(2 downto 0) := "000";
constant cslv_axsize_2 : std_logic_vector(2 downto 0) := "001";
constant cslv_axsize_4 : std_logic_vector(2 downto 0) := "010";
constant cslv_axsize_8 : std_logic_vector(2 downto 0) := "011";
constant cslv_axsize_16 : std_logic_vector(2 downto 0) := "100";
constant cslv_axsize_32 : std_logic_vector(2 downto 0) := "101";
constant cslv_axsize_64 : std_logic_vector(2 downto 0) := "110";
constant cslv_axsize_128 : std_logic_vector(2 downto 0) := "111";
constant cslv_axburst_fixed : std_logic_vector(1 downto 0) := "00";
constant cslv_axburst_incr : std_logic_vector(1 downto 0) := "01";
constant cslv_axburst_wrap : std_logic_vector(1 downto 0) := "10";
constant cslv_awlock_normal : std_logic_vector(1 downto 0) := "00";
constant cslv_awlock_exclusive : std_logic_vector(1 downto 0) := "01";
constant cslv_awlock_locked : std_logic_vector(1 downto 0) := "10";
constant cslv_axcache_dev_non_buf : std_logic_vector(3 downto 0) := "0000";
constant cslv_axcache_dev_buf : std_logic_vector(3 downto 0) := "0001";
constant cslv_axcache_norm_nc_nb : std_logic_vector(3 downto 0) := "0010";
constant cslv_axcache_norm_nc_b : std_logic_vector(3 downto 0) := "0010";
constant cslv_arcache_wt_no_alloc : std_logic_vector(3 downto 0) := "0011";
constant cslv_awcache_wt_no_alloc : std_logic_vector(3 downto 0) := "0110";
constant cslv_arcache_wt_r_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_awcache_wt_r_alloc : std_logic_vector(3 downto 0) := "0110";
constant cslv_arcache_wt_w_alloc : std_logic_vector(3 downto 0) := "1010";
constant cslv_awcache_wt_w_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_axcache_wtr_w_alloc : std_logic_vector(3 downto 0) := "1110";
constant cslv_arcache_wb_no_alloc : std_logic_vector(3 downto 0) := "1011";
constant cslv_awcache_wb_no_alloc : std_logic_vector(3 downto 0) := "0111";
constant cslv_arcache_wb_r_alloc : std_logic_vector(3 downto 0) := "1111";
constant cslv_awcache_wb_r_alloc : std_logic_vector(3 downto 0) := "0111";
constant cslv_axprot_u_access : std_logic_vector(2 downto 0) := "000";
constant cslv_axprot_p_access : std_logic_vector(2 downto 0) := "001";
constant cslv_axprot_s_access : std_logic_vector(2 downto 0) := "010";
constant cslv_axprot_ns_access : std_logic_vector(2 downto 0) := "011";
constant cslv_axprot_d_access : std_logic_vector(2 downto 0) := "100";
constant cslv_axprot_i_access : std_logic_vector(2 downto 0) := "100";
constant cslv_xresp_okay : std_logic_vector(1 downto 0) := "00";
constant cslv_xresp_exokay : std_logic_vector(1 downto 0) := "01";
constant cslv_xresp_slverr : std_logic_vector(1 downto 0) := "10";
constant cslv_xresp_decerr : std_logic_vector(1 downto 0) := "11";
------------------------------------------------------------------------------
-- AXI-4 Global Signals
------------------------------------------------------------------------------
type t_axi_wa_slv_in is record
slv_awid : std_logic_vector(3 downto 0);
slv_awaddr : std_logic_vector(31 downto 0);
slv_awlen : std_logic_vector(7 downto 0);
slv_awsize : std_logic_vector(2 downto 0);
slv_awburst : std_logic_vector(1 downto 0);
slv_awlock : std_logic_vector(1 downto 0);
slv_awcache : std_logic_Vector(3 downto 0);
slv_awprot : std_logic_vector(2 downto 0);
sl_awvalid : std_ulogic;
end record;
type t_axi_wa_slv_out is record
sl_awready : std_ulogic;
end record;
type t_axi_wd_slv_in is record
slv_wdata : std_logic_vector(31 downto 0);
slv_wstrb : std_logic_vector(3 downto 0);
sl_wlast : std_ulogic;
sl_wvalid : std_ulogic;
end record;
type t_axi_wd_slv_out is record
sl_wready : std_ulogic;
end record;
type t_axi_wr_slv_in is record
sl_bready : std_ulogic;
end record;
type t_axi_wr_slv_out is record
sl_bid : std_ulogic;
sl_bresp : std_ulogic;
sl_bvalid : std_ulogic;
end record;
type t_axi4_wd_slv_in is record
r_axi : t_axi_wd_slv_in;
sl_wuser : std_ulogic;
end record;
type t_axi_ra_slv_in is record
slv_arid : std_logic_vector(1 downto 0);
slv_araddr : std_logic_vector(31 downto 0);
slv_arlen : std_logic_vector(7 downto 0);
slv_arsize : std_logic_vector(2 downto 0);
slv_arburst : std_logic_vector(1 downto 0);
sl_arlock : std_logic;
slv_arcache : std_logic_vector(3 downto 0);
slv_arprot : std_logic_vector(2 downto 0);
slv_arqos : std_logic_vector(3 downto 0);
slv_arregion : std_logic_vector(3 downto 0);
sl_aruser : std_logic;
sl_arvalid : std_logic;
end record;
type t_axi_ra_slv_out is record
sl_arready : std_ulogic;
end record;
type t_axi_rd_slv_in is record
sl_rready : std_logic;
end record;
type t_axi_rd_slv_out is record
sl_rid : std_logic;
slv_rdata : std_logic_vector(31 downto 0);
slv_rresp : std_logic_vector(1 downto 0);
sl_rlast : std_logic;
sl_ruser : std_logic;
sl_rvalid : std_logic;
end record;
type t_axi_lpi_slv_in is record
sl_csysreq : std_ulogic;
end record;
type t_axi_lpi_slv_out is record
sl_csysack : std_ulogic;
sl_cactive : std_ulogic;
end record;
------------------------------------------------------------------------------
-- Sub-programs
------------------------------------------------------------------------------
--function axi_device_reg()
--return std_logic_vector;
function axireadword (
rdata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(4 downto 0))
return std_logic_vector;
procedure axireadword (
rdata : in std_logic_vector(31 downto 0);
raddr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(31 downto 0));
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
component axi3_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_aresetn : in std_ulogic;
-- write address channel
-- write data channel
-- write response channel
-- read data channel
-- low power interface
r_lpi_in : in t_axi_lpi_slv_in;
r_lpi_out : out t_axi_lpi_slv_out
);
end component;
component axi4_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_areset_n : in std_ulogic;
-- write address channel
r_wac_in : in t_axi_wa_slv_in;
awqos : in std_logic_vector(3 downto 0);
awregion : in std_logic_vector(3 downto 0);
awuser : in std_ulogic;
r_wac_out : out t_axi_wa_slv_out;
-- write data channel
r_wdc_in : in t_axi4_wd_slv_in;
r_wdc_out : out t_axi_wd_slv_out;
-- write response channel
r_wrc_in : in t_axi_wr_slv_in;
r_wrc_out : out t_axi_wr_slv_out;
-- read address channel
r_rac_in : in t_axi_ra_slv_in;
r_rac_out : out t_axi_ra_slv_out;
-- read data channel
r_rdc_in : in t_axi_rd_slv_in;
r_rdc_out : out t_axi_rd_slv_out;
-- low power interface
r_lpi_in : in t_axi_lpi_slv_in;
r_lpi_out : out t_axi_lpi_slv_out
);
end component;
component axi4_light_slave
port (
-- global signals
sl_aclk : in std_ulogic;
sl_areset_n : in std_ulogic
);
end component;
end axi;
package body axi is
function axireadword (
rdata : std_logic_vector(31 downto 0);
raddr : std_logic_vector(4 downto 0))
return std_logic_vector is
begin
end axireadword;
procedure axireadword (
rdata : in std_logic_vector(31 downto 0);
raddr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(31 downto 0)) is
begin
end axireadword;
end;
|
gpl-3.0
|
2e685d12c72e7fcf35bab89beba552a4
| 0.563443 | 3.43297 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/Debug Unit/ASCII_BUFFER.vhd
| 1 | 3,093 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: DEBUG UNIT
-- Project Name: DEBUG UNIT
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debug Unit for part 4 of Lab 1
-- Takes in a 0 - F on the ASCII_DATA line
-- and outputs it to the BUFFER concatenated
-- together to form the Instruction
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ASCII_BUFFER is
port(
ASCII_DATA : in STD_LOGIC_VECTOR(7 downto 0);
ASCII_RD: in STD_LOGIC;
ASCII_WE: in STD_LOGIC;
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
ASCII_BUFF: out STD_LOGIC_VECTOR(15 downto 0)
);
end ASCII_BUFFER;
architecture dataflow of ASCII_BUFFER is
type StateType is (init, idle, VALID_KEY, SPECIAL_KEY, BACKSPACE, FLUSH);
signal STATE : StateType := init;
type ram_type is array (0 to 3) of STD_LOGIC_VECTOR(3 downto 0);
signal ram_addr : integer range 0 to 3;
signal ram : ram_type;
signal KEY : STD_LOGIC_VECTOR(3 downto 0);
signal INST: STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
with ASCII_DATA select
KEY <=
x"f" when x"66",
x"e" when x"65",
x"d" when x"64",
x"c" when x"63",
x"b" when x"62",
x"a" when x"61",
x"F" when x"46",
x"E" when x"45",
x"D" when x"44",
x"C" when x"43",
x"B" when x"42",
x"A" when x"41",
x"9" when x"39",
x"8" when x"38",
x"7" when x"37",
x"6" when x"36",
x"5" when x"35",
x"4" when x"34",
x"3" when x"33",
x"2" when x"32",
x"1" when x"31",
x"0" when x"30",
x"0" when OTHERS; -- Null
PROCESS(CLK,RST)
BEGIN
if(RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '1' ) then
case STATE is
when init =>
ASCII_BUFF <= (OTHERS => '0');
ram(0) <= x"0";
ram(1) <= x"0";
ram(2) <= x"0";
ram(3) <= x"0";
ram_addr <= 0;
state <= idle;
when idle =>
ASCII_BUFF <= INST;
if ASCII_RD = '1' and ASCII_WE = '1' then
state <= VALID_KEY;
-- A Valid key was pressed
elsif ASCII_RD = '1' and ASCII_WE = '0' then
state <= SPECIAL_KEY;
--Special key was pressed
else
state <= idle;
end if;
when VALID_KEY =>
ram(ram_addr) <= key;
ram_addr <= ram_addr + 1;
state <= idle;
when SPECIAL_KEY =>
if ASCII_DATA = x"0D" then --0D = enterkey
state <= FLUSH;
elsif ASCII_DATA = x"08" then -- 08 = backspace
state <= BACKSPACE;
else
state <= idle;
end if;
when BACKSPACE =>
if ram_addr > 0 then
ram_addr <= ram_addr - 1;
end if;
ram(ram_addr) <= x"0";
state <= idle;
when FLUSH =>
INST <= ram(0) & ram(1) & ram(2) & ram(3);
state <= init;
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
|
mit
|
6f49ff82ddd4c89563f720173481030f
| 0.553831 | 2.901501 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/EnableCircuit.vhd
| 1 | 1,457 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 06:01:15 PM
-- Design Name:
-- Module Name: EnableCircuit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EnableCircuit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Enable : in BIT; -- Should be input value returned?
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end EnableCircuit;
architecture Behavioral of EnableCircuit is
begin
Output(0) <= Input(0) and Enable;
Output(1) <= Input(1) and Enable;
Output(2) <= Input(2) and Enable;
Output(3) <= Input(3) and Enable;
Output(4) <= Input(4) and Enable;
Output(5) <= Input(5) and Enable;
Output(6) <= Input(6) and Enable;
Output(7) <= Input(7) and Enable;
end Behavioral;
|
mit
|
6a187e38f625a394ded968de3c0d8352
| 0.578586 | 3.937838 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/CU.vhd
| 1 | 5,782 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CU is
Port ( OP : in STD_LOGIC_VECTOR (1 downto 0);
OP2 : in STD_LOGIC_VECTOR(2 downto 0);
Cond: in STD_LOGIC_VECTOR (3 downto 0);
icc: in STD_LOGIC_VECTOR (3 downto 0);
OP3 : in STD_LOGIC_VECTOR (5 downto 0);
WE : out STD_LOGIC;
RFDEST : out STD_LOGIC;
RFSOURCE: out STD_LOGIC_VECTOR(1 downto 0);
WRENMEM: out STD_LOGIC;
--RDENMEM: out STD_LOGIC;
PCSOURCE: out STD_LOGIC_VECTOR(1 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0));
end CU;
architecture Behavioral of CU is
begin
process(OP,OP3,Cond,icc,OP2)
begin
case OP is
when "10"=>
WE<='1';
WRENMEM<='0';
--RDENMEM<='0';
RFDEST<='0';
PCSOURCE<="10";
RFSOURCE<="01";
case OP3 is --Instrucciones aritmetico logicas
when "000001"=>ALUOP<="000000"; --0. AND
when "000101"=>ALUOP<="000001"; --1. ANDN
when "000010"=>ALUOP<="000010"; --2. OR
when "000110"=>ALUOP<="000011"; --3. ORN
when "000011"=>ALUOP<="000100"; --4. XOR
when "000111"=>ALUOP<="000101"; --5. XNOR
when "000000"=>ALUOP<="000110"; --6. ADD
when "000100"=>ALUOP<="000111"; --7. SUB
when "100101"=>ALUOP<="001000"; --8. SLL
when "100110"=>ALUOP<="001001"; --9. SRL
when "100111"=>ALUOP<="001010"; --10. SRA
when "010001"=>ALUOP<="001011"; --11. ANDcc
when "010101"=>ALUOP<="001100"; --12. ANDNcc
when "010010"=>ALUOP<="001101"; --13. ORcc
when "010110"=>ALUOP<="001110"; --14. ORNcc
when "010011"=>ALUOP<="001111"; --15. XORcc
when "010111"=>ALUOP<="010000"; --16. XNORcc
when "010000"=>ALUOP<="010001"; --17. ADDcc
when "001000"=>ALUOP<="010010"; --18. ADDX
when "011000"=>ALUOP<="010011"; --19. ADDXcc
when "010100"=>ALUOP<="010100"; --20. SUBcc
when "001100"=>ALUOP<="010101"; --21. SUBX
when "011100"=>ALUOP<="010110"; --22. SUBXcc
when "111100"=>ALUOP<="010111"; --23. SAVE
when "111101"=>ALUOP<="011000"; --24. RESTORE
when "111000"=>--JUMP AND LINK
ALUOP<="000110";--SUMA
PCSOURCE<="11";
RFSOURCE<="10";
when others=> ALUOP<="111111"; --Instrucciones artimetico logicas no definidas
WE<='0';
end case;
when "11"=>
RFDEST<='0';
PCSOURCE<="10";
ALUOP<="000110";--SUMA
RFSOURCE<="00";
case OP3 is --Instrucciones para escribir y leer en memoria
when "000100"=>--25. Store Word
WE<='0';
WRENMEM<='1';
--RDENMEM<='0';
when "000000"=>--26. Load word
WE<='1';
WRENMEM<='0';
--RDENMEM<='1';
when others=>ALUOP<="111111";
WE<='0';
WRENMEM<='0';
end case;
when "00"=> --Branch on Integer Condition Codes Instructions
case OP2 is
when "010"=>
WE<='0';
RFDEST<='0';
WRENMEM<='0';
--RDENMEM<='0';
RFSOURCE<="01";
ALUOP<="111111";
case Cond is
when "1000"=>--Branch Always BA
PCSOURCE<="01";
when "0000"=>--Branch Never BN
PCSOURCE<="10";
when "1001"=>--Branch on Not Equal BNE
if(icc(2)='0') then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "0001"=>--Branch on Equal BE
if(icc(2)='1') then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "1010"=>--Branch on Greater BG
if(icc(2) or(icc(3) xor icc(1)))='0' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "0010"=>--Branch on Less or Equal BLE
if (icc(2) or(icc(3) xor icc(1)))='1' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "1011"=>--Branch on Greater or Equal BGE
if (icc(3) xor icc(1))='0' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "0011"=>--Branch on Less BL
if(icc(3) xor icc(1))='1' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "1100"=>--Branch on Greater Unsigned BGU
if(icc(0) or icc(2))='0' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "0100"=>--Branch on Less or Equal Unsigned BLEU
if(icc(0) or icc(2))='1' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "1101"=>--Branch on Carry Clear(Greater than or Equal, Unsigned) BCC
if icc(0)='0' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "0101"=>--Branch on Carry Set(Less than Unsigned) BCS
if icc(0)='1' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "1110"=>--Branch on Positive BPOS
if icc(3)='0' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "0110"=>--Branch on Negative BNEG
if icc(3)='1' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "1111"=>--Branch on Overflow Clear BVC
if icc(1)='0' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when "0111"=>--Branch on Overflow Set BVS
if icc(1)='1' then
PCSOURCE<="01";
else
PCSOURCE<="10";
end if;
when others=>ALUOP<="111111";
end case;
when others=>
ALUOP<="111111";
WE<='0';
WRENMEM<='0';
RFDEST<='0';
PCSOURCE<="10";
RFSOURCE<="01";
end case;
when "01"=>--CALL AND LINK
RFDEST<='1';
WE<='1';
WRENMEM<='0';
--RDENMEM<='0';
PCSOURCE<="00";
RFSOURCE<="10";
ALUOP<="111111";
when others=>ALUOP<="111111"; --Otras instrucciones aun no definidas
RFDEST<='0';
WE<='0';
WRENMEM<='0';
PCSOURCE<="10";
RFSOURCE<="01";
end case;
end process;
end Behavioral;
|
mit
|
d0b975cd72b7335c371248a8057adbfb
| 0.528191 | 3.311569 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_gpio_pullup_0/synth/system_axi_gpio_pullup_0.vhd
| 1 | 10,051 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_pullup_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END system_axi_gpio_pullup_0;
ARCHITECTURE system_axi_gpio_pullup_0_arch OF system_axi_gpio_pullup_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_pullup_0_arch : ARCHITECTURE IS "system_axi_gpio_pullup_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "system_axi_gpio_pullup_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=2,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 2,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_pullup_0_arch;
|
apache-2.0
|
c88f705f16a0b3cf0bfef010e827f790
| 0.688887 | 3.183719 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_rst_clk_wiz_1_100M_0/synth/system_rst_clk_wiz_1_100M_0.vhd
| 1 | 6,620 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rst_clk_wiz_1_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_clk_wiz_1_100M_0;
ARCHITECTURE system_rst_clk_wiz_1_100M_0_arch OF system_rst_clk_wiz_1_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rst_clk_wiz_1_100M_0_arch : ARCHITECTURE IS "system_rst_clk_wiz_1_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "system_rst_clk_wiz_1_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_clk_wiz_1_100M_0_arch;
|
apache-2.0
|
c768fba823b935ec1d538cc37d0243a1
| 0.712991 | 3.442538 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/04b4/hdl/proc_sys_reset_v5_0_vh_rfs.vhd
| 8 | 69,537 |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
apache-2.0
|
3c64b249c692ef319ccc1c660efb422e
| 0.434618 | 4.331174 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-4-4bit-ALU/lib/add_sub/cla_4_bit_testBench.vhd
| 2 | 3,004 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cla_4_bit_testBench IS
END cla_4_bit_testBench;
ARCHITECTURE behavior OF cla_4_bit_testBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cla_4_bit
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
Sum : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';
--Outputs
signal Sum : std_logic_vector(3 downto 0);
signal Cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cla_4_bit PORT MAP (
A => A,
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);
-- Clock process definitions
--<clock>_process :process
--begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
--end process;
-- Stimulus process
stim_proc: process
variable count : integer :=0;
begin
A <= "0000";
B <= "0000";
-- TEST ADDER FUNCTIONALITY
Cin <= '0';
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(Sum = (A+B)) then
assert Sum = (A + B) report "Sum should have been " &
integer'image(to_integer(unsigned((A+B)))) & " with A=" &
integer'image(to_integer(unsigned(A))) & " and B=" &
integer'image(to_integer(unsigned(B))) & " but instead Sum was " &
integer'image(to_integer(unsigned(Sum))) severity ERROR;
count := count + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
-- TEST SUBTRACTOR FUNCTIONALITY
Cin <= '1';
wait for 1 ns;
for i in 0 to 15 loop
for j in 0 to 15 loop
wait for 1 ns;
if NOT(Sum = (A-B)) then
assert Sum = (A - B) report "Difference should have been " &
integer'image(to_integer(unsigned((A-B)))) & " with A=" &
integer'image(to_integer(unsigned(A))) & " and B=" &
integer'image(to_integer(unsigned(B))) & " but instead Sum was " &
integer'image(to_integer(unsigned(Sum))) severity ERROR;
count := count + 1;
else
--nada
end if;
B <= B + "0001";
end loop;
A <= A + "0001";
end loop;
--wait for <clock>_period*10;
-- insert stimulus here
report "TEST FINISHED.";
report "ERROR COUNT: " & integer'image(count);
wait;
end process;
END;
|
agpl-3.0
|
5809880eaf38643b824d9b72209b0b84
| 0.577563 | 3.272331 | false | true | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/efc9/hdl/axi_iic_v2_0_vh_rfs.vhd
| 1 | 300,637 |
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
-------------------------------------------------------------------------------
-- upcnt_n.vhd entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v1.01.b
--
-- Description:
-- This file contains a parameterizable N-bit up counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Data width of counter
--
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- Active low clear
-- Data -- Serial data in
-- Cnt_en -- Count enable
-- Load -- Load line enable
-- Qout -- Shift register shift enable
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : integer :=9
);
port(
Clr : in std_logic;
Clk : in std_logic;
Data : in std_logic_vector (0 to C_SIZE-1);
Cnt_en : in std_logic;
Load : in std_logic;
Qout : inout std_logic_vector (0 to C_SIZE-1)
);
end upcnt_n;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of upcnt_n is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal q_int : unsigned (0 to C_SIZE-1);
begin
----------------------------------------------------------------------------
-- PROCESS: UP_COUNT_GEN
-- purpose: Up counter
----------------------------------------------------------------------------
UP_COUNT_GEN : process(Clk)
begin
if (Clk'event) and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
q_int <= (others => '0');
elsif (Load = '1') then -- Load in start value
q_int <= unsigned(Data);
elsif Cnt_en = '1' then -- If count enable is high
q_int <= q_int + 1;
else
q_int <= q_int;
end if;
end if;
end process UP_COUNT_GEN;
Qout <= std_logic_vector(q_int);
end architecture RTL;
-------------------------------------------------------------------------------
-- shift8.vhd - Entity and Architecture
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: shift8.vhd
-- Version: v1.01.b
-- Description:
-- This file contains an 8 bit shift register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- System reset
-- Data_ld -- Shift register data load enable
-- Data_in -- Shift register data in
-- Shift_in -- Shift register serial data in
-- Shift_en -- Shift register shift enable
-- Shift_out -- Shift register serial data out
-- Data_out -- Shift register shift data out
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shift8 is
port(
Clk : in std_logic; -- Clock
Clr : in std_logic; -- Clear
Data_ld : in std_logic; -- Data load enable
Data_in : in std_logic_vector (7 downto 0);-- Data to load in
Shift_in : in std_logic; -- Serial data in
Shift_en : in std_logic; -- Shift enable
Shift_out : out std_logic; -- Shift serial data out
Data_out : out std_logic_vector (7 downto 0) -- Shifted data
);
end shift8;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of shift8 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal data_int : std_logic_vector (7 downto 0);
begin
----------------------------------------------------------------------------
-- PROCESS: SHIFT_REG_GEN
-- purpose: generate shift register
----------------------------------------------------------------------------
SHIFT_REG_GEN : process(Clk)
begin
if Clk'event and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
data_int <= (others => '0');
elsif (Data_ld = '1') then -- Load data
data_int <= Data_in;
elsif Shift_en = '1' then -- If shift enable is high
data_int <= data_int(6 downto 0) & Shift_in; -- Shift the data
end if;
end if;
end process SHIFT_REG_GEN;
Shift_out <= data_int(7);
Data_out <= data_int;
end architecture RTL;
-------------------------------------------------------------------------------
-- iic_pkg.vhd - Package
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic_pkg.vhd
-- Version: v1.01.b
-- Description: This file contains the constants used in the design of the
-- iic bus interface.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package iic_pkg is
----------------------------------------------------------------------------
-- Constant Declarations
----------------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1'; -- Reset Constant
constant NUM_IIC_REGS : integer := 11; -- should be same as C_NUM_IIC_REGS in axi_iic top
constant DATA_BITS : natural := 8; -- FIFO Width Generic
constant TX_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits
constant RC_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits
--IPIF Generics that must remain at these values for the IIC
constant INCLUDE_DEV_PENCODER : BOOLEAN := False;
constant IPIF_ABUS_WIDTH : INTEGER := 32;
constant INCLUDE_DEV_ISC : Boolean := false;
type STD_LOGIC_VECTOR_ARRAY is array (0 to NUM_IIC_REGS-1) of std_logic_vector(24 to 31);
type INTEGER_ARRAY is array (24 to 31) of integer;
----------------------------------------------------------------------------
-- Function and Procedure Declarations
----------------------------------------------------------------------------
function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer;
C_IIC_FREQ : integer) return integer;
function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector;
function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector;
function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY) return
INTEGER_ARRAY;
end package iic_pkg;
-------------------------------------------------------------------------------
-- Package body
-------------------------------------------------------------------------------
package body iic_pkg is
----------------------------------------------------------------------------
-- Function Definitions
----------------------------------------------------------------------------
-- Function num_ctr_bits
--
-- This function returns the number of bits required to count 1/2 the period
-- of the SCL clock.
--
----------------------------------------------------------------------------
function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer;
C_IIC_FREQ : integer) return integer is
variable num_bits : integer :=0;
variable i : integer :=0;
begin
-- for loop used because XST service pack 2 does not support While loops
if C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ > C_S_AXI_ACLK_FREQ_HZ/212766 then
for i in 0 to 30 loop -- 30 is a magic number needed for for loops
if 2**i < C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ then
num_bits := num_bits + 1;
end if;
end loop;
return (num_bits);
else
for i in 0 to 30 loop
if 2**i < C_S_AXI_ACLK_FREQ_HZ/212766 then
num_bits := num_bits + 1;
end if;
end loop;
return (num_bits);
end if;
end function num_ctr_bits;
----------------------------------------------------------------------------
-- Function ten_bit_addr_used
--
-- This function returns either b"00000000" for no ten bit addressing or
-- b"00000111" for ten bit addressing
--
----------------------------------------------------------------------------
function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector is
begin
if C_TEN_BIT_ADR = 0 then
return (b"00000000");
else
return (b"00000111");
end if;
end function ten_bit_addr_used;
----------------------------------------------------------------------------
-- Function gpo_bit_used
--
-- This function returns b"00000000" up to b"11111111" depending on
-- C_GPO_WIDTH
--
----------------------------------------------------------------------------
function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector is
begin
if C_GPO_WIDTH = 1 then
return (b"00000001");
elsif C_GPO_WIDTH = 2 then
return (b"00000011");
elsif C_GPO_WIDTH = 3 then
return (b"00000111");
elsif C_GPO_WIDTH = 4 then
return (b"00001111");
elsif C_GPO_WIDTH = 5 then
return (b"00011111");
elsif C_GPO_WIDTH = 6 then
return (b"00111111");
elsif C_GPO_WIDTH = 7 then
return (b"01111111");
elsif C_GPO_WIDTH = 8 then
return (b"11111111");
end if;
end function gpo_bit_used;
----------------------------------------------------------------------------
-- Function count_reg_bits_used
--
-- This function returns either b"00000000" for no ten bit addressing or
-- b"00000111" for ten bit addressing
--
----------------------------------------------------------------------------
function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY)
return INTEGER_ARRAY is
variable count : INTEGER_ARRAY;
begin
for i in 24 to 31 loop
count(i) := 0;
for m in 0 to NUM_IIC_REGS-1 loop --IP_REG_NUM - 1
if (REG_BITS_USED(m)(i) = '1') then
count(i) := count(i) + 1;
end if;
end loop;
end loop;
return count;
end function count_reg_bits_used;
end package body iic_pkg;
-------------------------------------------------------------------------------
-- debounce.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: debounce.vhd
-- Version: v1.01.b
-- Description:
-- This file implements a simple debounce (inertial delay)
-- filter to remove short glitches from a signal based upon
-- using user definable delay parameters. It accepts a "Stable"
-- signal which allows the filter to dynamically stretch its
-- delay based on whether another signal is Stable or not. If
-- the filter has detected a change on is "Noisy" input then it
-- will signal its output is "unstable". That can be cross
-- coupled into the "Stable" input of another filter if
-- necessary.
-- Notes:
-- 1) A default assignment based on the generic C_DEFAULT is made for the flip
-- flop output of the delay logic when C_INERTIAL_DELAY > 0. Otherwise, the
-- logic is free running and no reset is possible.
-- 2) A C_INERTIAL_DELAY value of 0 eliminates the debounce logic and connects
-- input to output directly.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- - Fixed the CR#613486
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_INERTIAL_DELAY -- Filtering delay
-- C_DEFAULT -- User logic high address
-- Definition of Ports:
-- Sysclk -- System clock
-- Stable -- IIC signal is Stable
-- Unstable_n -- IIC signal is unstable
-- Noisy -- IIC signal is Noisy
-- Clean -- IIC signal is Clean
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity debounce is
generic (
C_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_DEFAULT : std_logic := '1'
);
port (
Sysclk : in std_logic;
Rst : in std_logic;
Stable : in std_logic;
Unstable_n : out std_logic;
Noisy : in std_logic;
Clean : out std_logic);
end entity debounce;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of debounce is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- XST proceses default assignments for configuration purposes
signal clean_cs : std_logic := C_DEFAULT;
signal stable_cs : std_logic := '1';
signal debounce_ct : integer range 0 to 255;
signal Noisy_d1 : std_logic := '1';
signal Noisy_d2 : std_logic := '1';
begin
----------------------------------------------------------------------------
-- Input Registers Process
-- This process samples the incoming SDA and SCL with the system clock
----------------------------------------------------------------------------
-- INPUT_DOUBLE_REGS : process(Sysclk)
-- begin
-- if Sysclk'event and Sysclk = '1' then
-- Noisy_d1 <= Noisy;
-- Noisy_d2 <= Noisy_d1; -- double buffer async input
-- end if;
-- end process INPUT_DOUBLE_REGS;
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Noisy,
prmry_vect_in => (others => '0'),
scndry_aclk => Sysclk,
scndry_resetn => '0',
scndry_out => Noisy_d2,
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- GEN_INERTIAL : Generate when C_INERTIAL_DELAY > 0
----------------------------------------------------------------------------
GEN_INERTIAL : if (C_INERTIAL_DELAY > 0) generate
----------------------------------------------------------------------------
-- GEN_INERTIAL : C_INERTIAL_DELAY > 0
-- Inertial delay filters out pulses that are smaller in width then the
-- specified delay. If the C_INERTIAL_DELAY is 0 then the input is passed
-- directly to the "Clean" output signal.
----------------------------------------------------------------------------
INRTL_PROCESS : process (Sysclk) is
begin
if ((rising_edge(Sysclk))) then
if Rst = '1' then
clean_cs <= C_DEFAULT;
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
elsif (clean_cs = Noisy_d2) then
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
else
if (debounce_ct > 0) then
debounce_ct <= debounce_ct - 1;
Unstable_n <= '0';
else
if Stable = '1' then
clean_cs <= Noisy_d2;
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
end if;
end if;
end if;
end if;
end process INRTL_PROCESS;
s0 : Clean <= clean_cs;
end generate GEN_INERTIAL;
----------------------------------------------------------------------------
-- NO_INERTIAL : C_INERTIAL_DELAY = 0
-- No inertial delay means output is always Stable
----------------------------------------------------------------------------
NO_INERTIAL : if (C_INERTIAL_DELAY = 0) generate
s0 : Clean <= Noisy_d2;
s1 : Unstable_n <= '1';
end generate NO_INERTIAL;
end architecture RTL;
-------------------------------------------------------------------------------
-- reg_interface.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: reg_interface.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the interface between the IPIF
-- and the iic controller. All registers are generated
-- here and all interrupts are processed here.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_arith.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.iic_pkg.all;
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_TX_FIFO_EXIST -- IIC transmit FIFO exist
-- C_TX_FIFO_BITS -- Transmit FIFO bit size
-- C_RC_FIFO_EXIST -- IIC receive FIFO exist
-- C_RC_FIFO_BITS -- Receive FIFO bit size
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_S_AXI_DATA_WIDTH -- Slave bus data width
-- C_NUM_IIC_REGS -- Number of IIC Registers
--
-- Definition of Ports:
-- Clk -- System clock
-- Rst -- System reset
-- Bus2IIC_Addr -- Bus to IIC address bus
-- Bus2IIC_Data -- Bus to IIC data bus
-- Bus2IIC_WrCE -- Bus to IIC write chip enable
-- Bus2IIC_RdCE -- Bus to IIC read chip enable
-- IIC2Bus_Data -- IIC to Bus data bus
-- IIC2Bus_IntrEvent -- IIC Interrupt events
-- Gpo -- General purpose outputs
-- Cr -- Control register
-- Msms_rst -- MSMS reset signal
-- Rsta_rst -- Repeated start reset
-- Msms_set -- MSMS set
-- DynMsmsSet -- Dynamic MSMS set signal
-- DynRstaSet -- Dynamic repeated start set signal
-- Cr_txModeSelect_set -- Sets transmit mode select
-- Cr_txModeSelect_clr -- Clears transmit mode select
-- Aas -- Addressed as slave indicator
-- Bb -- Bus busy indicator
-- Srw -- Slave read/write indicator
-- Abgc -- Addressed by general call indicator
-- Dtr -- Data transmit register
-- Rdy_new_xmt -- New data loaded in shift reg indicator
-- Dtre -- Data transmit register empty
-- Drr -- Data receive register
-- Data_i2c -- IIC data for processor
-- New_rcv_dta -- New Receive Data ready
-- Ro_prev -- Receive over run prevent
-- Adr -- IIC slave address
-- Ten_adr -- IIC slave 10 bit address
-- Al -- Arbitration lost indicator
-- Txer -- Received acknowledge indicator
-- Tx_under_prev -- DTR or Tx FIFO empty IRQ indicator
-- Tx_fifo_data -- FIFO data to transmit
-- Tx_data_exists -- next FIFO data exists
-- Tx_fifo_wr -- Decode to enable writes to FIFO
-- Tx_fifo_rd -- Decode to enable read from FIFO
-- Tx_fifo_rst -- Reset Tx FIFO on IP Reset or CR(6)
-- Tx_fifo_Full -- Transmit FIFO full indicator
-- Tx_addr -- Transmit FIFO address
-- Rc_fifo_data -- Read Fifo data for AXI
-- Rc_fifo_wr -- Write IIC data to fifo
-- Rc_fifo_rd -- AXI read from fifo
-- Rc_fifo_Full -- Read Fifo is full prevent rcv overrun
-- Rc_data_Exists -- Next FIFO data exists
-- Rc_addr -- Receive FIFO address
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity reg_interface is
generic(
C_SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_TX_FIFO_EXIST : boolean := TRUE;
C_TX_FIFO_BITS : integer := 4;
C_RC_FIFO_EXIST : boolean := TRUE;
C_RC_FIFO_BITS : integer := 4;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 0;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_SIZE : integer := 32;
C_NUM_IIC_REGS : integer;
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port(
-- IPIF Interface Signals
Clk : in std_logic;
Rst : in std_logic;
Bus2IIC_Addr : in std_logic_vector (0 to C_S_AXI_ADDR_WIDTH-1);
Bus2IIC_Data : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH - 1);
Bus2IIC_WrCE : in std_logic_vector (0 to C_NUM_IIC_REGS - 1);
Bus2IIC_RdCE : in std_logic_vector (0 to C_NUM_IIC_REGS - 1);
IIC2Bus_Data : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH - 1);
IIC2Bus_IntrEvent : out std_logic_vector (0 to 7);
-- Internal iic Bus Registers
-- GPO Register Offset 124h
Gpo : out std_logic_vector(32 - C_GPO_WIDTH to
C_S_AXI_DATA_WIDTH - 1);
-- Control Register Offset 100h
Cr : out std_logic_vector(0 to 7);
Msms_rst : in std_logic;
Rsta_rst : in std_logic;
Msms_set : out std_logic;
DynMsmsSet : in std_logic;
DynRstaSet : in std_logic;
Cr_txModeSelect_set : in std_logic;
Cr_txModeSelect_clr : in std_logic;
-- Status Register Offest 04h
Aas : in std_logic;
Bb : in std_logic;
Srw : in std_logic;
Abgc : in std_logic;
-- Data Transmit Register Offset 108h
Dtr : out std_logic_vector(0 to 7);
Rdy_new_xmt : in std_logic;
Dtre : out std_logic;
-- Data Receive Register Offset 10Ch
Drr : out std_logic_vector(0 to 7);
Data_i2c : in std_logic_vector(0 to 7);
New_rcv_dta : in std_logic;
Ro_prev : out std_logic;
-- Address Register Offset 10h
Adr : out std_logic_vector(0 to 7);
-- Ten Bit Address Register Offset 1Ch
Ten_adr : out std_logic_vector(5 to 7) := (others => '0');
Al : in std_logic;
Txer : in std_logic;
Tx_under_prev : in std_logic;
-- Timing Parameters to iic_control
Timing_param_tsusta : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsusto : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thdsta : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsudat : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tbuf : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thigh : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tlow : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thddat : out std_logic_vector(C_SIZE-1 downto 0);
-- FIFO input (fifo write) and output (fifo read)
Tx_fifo_data : in std_logic_vector(0 to 7);
Tx_data_exists : in std_logic;
Tx_fifo_wr : out std_logic;
Tx_fifo_rd : out std_logic;
Tx_fifo_rst : out std_logic;
Tx_fifo_Full : in std_logic;
Tx_addr : in std_logic_vector(0 to C_TX_FIFO_BITS - 1);
Rc_fifo_data : in std_logic_vector(0 to 7);
Rc_fifo_wr : out std_logic;
Rc_fifo_rd : out std_logic;
Rc_fifo_Full : in std_logic;
Rc_data_Exists : in std_logic;
Rc_addr : in std_logic_vector(0 to C_RC_FIFO_BITS - 1);
reg_empty : in std_logic
);
end reg_interface;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of reg_interface is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
----------------------------------------------------------------------------
-- Constant Declarations
----------------------------------------------------------------------------
-- Calls the function from the iic_pkg.vhd
--constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
constant IIC_CNT : integer := (C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ - 14);
-- Calls the function from the iic_pkg.vhd
--constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
-- number of SYSCLK in iic SCL High time
constant HIGH_CNT : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/2 - C_SCL_INERTIAL_DELAY, C_SIZE);
-- number of SYSCLK in iic SCL Low time
constant LOW_CNT : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/2 - C_SCL_INERTIAL_DELAY, C_SIZE);
-- half of HIGH_CNT
constant HIGH_CNT_2 : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/4, C_SIZE);
----------------------------------------------------------------------------
-- Function calc_tsusta
--
-- This function returns Setup time integer value for repeated start for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsusta (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate setup time for repeated start condition depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.7 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/175438, C_SIZE);
-- Added to have 5.7 us (tr+tsu-sta)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tr+tsu-sta)
else
-- Fast Mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tr+tsu-sta)
end if;
end FUNCTION calc_tsusta;
----------------------------------------------------------------------------
-- Function calc_tsusto
--
-- This function returns Setup time integer value for stop condition for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsusto (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate setup time for stop condition depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.0 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/200000, C_SIZE);
-- Added to have 5 us (tr+tsu-sto)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tr+tsu-sto)
else
-- Fast-mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tr+tsu-sto)
end if;
end FUNCTION calc_tsusto;
----------------------------------------------------------------------------
-- Function calc_thdsta
--
-- This function returns Hold time integer value for reapeted start for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_thdsta (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate (repeated) START hold time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.0 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/232558, C_SIZE);
-- Added to have 4.3 us (tf+thd-sta)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tf+thd-sta)
else
-- Fast-mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tf+thd-sta)
end if;
end FUNCTION calc_thdsta;
----------------------------------------------------------------------------
-- Function calc_tsudat
--
-- This function returns Data Setup time integer value for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsudat (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data setup time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 250 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1818181, C_SIZE);
-- Added to have 550 ns (tf+tsu-dat)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 100 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2500000, C_SIZE);
-- Added to have 400 ns (tf+tsu-dat)
else
-- Fast-mode Plus timing is 50 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/5882353, C_SIZE);
-- Added to have 170 ns (tf+tsu-dat)
end if;
end FUNCTION calc_tsudat;
----------------------------------------------------------------------------
-- Function calc_tbuf
--
-- This function returns Bus free time between a STOP and START condition
-- integer value for Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tbuf (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data setup time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.7 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/200000, C_SIZE);
-- Added to have 5 us
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 1.3 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/625000, C_SIZE);
-- Added to have 1.6 us
else
-- Fast-mode Plus timing is 0.5 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1612904, C_SIZE);
-- Added to have 0.62 us
end if;
end FUNCTION calc_tbuf;
----------------------------------------------------------------------------
-- Function calc_thddat
--
-- This function returns the data hold time integer value for I2C and
-- SMBus/PMBus protocols.
----------------------------------------------------------------------------
FUNCTION calc_thddat (
constant C_SMBUS_PMBUS_HOST : integer;
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data hold time depending on SMBus/PMBus compatability
if (C_SMBUS_PMBUS_HOST = 1) then
-- hold time of 300 ns for SMBus/PMBus
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/3333334, C_SIZE);
else
-- hold time of 0 ns for normal I2C
RETURN conv_std_logic_vector(1, C_SIZE);
end if;
end FUNCTION calc_thddat;
-- Set-up time for a repeated start
constant TSUSTA : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsusta(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Set-up time for a stop
constant TSUSTO : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsusto(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Hold time (repeated) START condition. After this period, the first clock
-- pulse is generated.
constant THDSTA : std_logic_vector(C_SIZE-1 downto 0)
:= calc_thdsta(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Data setup time.
constant TSUDAT : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsudat(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Bus free time.
constant TBUF : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tbuf(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Data Hold time
constant THDDAT : std_logic_vector(C_SIZE-1 downto 0)
:= calc_thddat(C_SMBUS_PMBUS_HOST, C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
----------------------------------------------------------------------------
-- Signal and Type Declarations
----------------------------------------------------------------------------
signal cr_i : std_logic_vector(0 to 7); -- intrnl control reg
signal sr_i : std_logic_vector(0 to 7); -- intrnl statuss reg
signal dtr_i : std_logic_vector(0 to 7); -- intrnl dta trnsmt reg
signal drr_i : std_logic_vector(0 to 7); -- intrnl dta receive reg
signal adr_i : std_logic_vector(0 to 7); -- intrnl slave addr reg
signal rc_fifo_pirq_i : std_logic_vector(4 to 7); -- intrnl slave addr reg
signal ten_adr_i : std_logic_vector(5 to 7) := (others => '0');
-- intrnl slave addr reg
signal ro_a : std_logic; -- receive overrun SRFF
signal ro_i : std_logic; -- receive overrun SRFF
signal dtre_i : std_logic; -- data tranmit register empty register
signal new_rcv_dta_d1 : std_logic; -- delay new_rcv_dta to find rising edge
signal msms_d1 : std_logic; -- delay msms cr(5)
signal ro_prev_i : std_logic; -- internal Ro_prev
signal msms_set_i : std_logic; -- SRFF set on falling edge of msms
signal rtx_i : std_logic_vector(0 to 7);
signal rrc_i : std_logic_vector(0 to 7);
signal rtn_i : std_logic_vector(0 to 7);
signal rpq_i : std_logic_vector(0 to 7);
signal gpo_i : std_logic_vector(32 - C_GPO_WIDTH to 31); -- GPO
signal timing_param_tsusta_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tsusto_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thdsta_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tsudat_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tbuf_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thigh_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tlow_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thddat_i : std_logic_vector(C_SIZE-1 downto 0);
signal rback_data : std_logic_vector(0 to 32 * C_NUM_IIC_REGS - 1)
:= (others => '0');
begin
----------------------------------------------------------------------------
-- CONTROL_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
CONTROL_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
cr_i <= (others => '0');
elsif -- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
Bus2IIC_WrCE(0) = '1' then
cr_i(0 to 7) <= Bus2IIC_Data(24 to 31);
else -- Load Control Register with iic data
cr_i(0) <= cr_i(0);
cr_i(1) <= cr_i(1);
cr_i(2) <= (cr_i(2) or DynRstaSet) and not(Rsta_rst);
cr_i(3) <= cr_i(3);
cr_i(4) <= (cr_i(4) or Cr_txModeSelect_set) and
not(Cr_txModeSelect_clr);
cr_i(5) <= (cr_i(5) or DynMsmsSet) and not (Msms_rst);
cr_i(6) <= cr_i(6);
cr_i(7) <= cr_i(7);
end if;
end if;
end process CONTROL_REGISTER_PROCESS;
Cr <= cr_i;
----------------------------------------------------------------------------
-- Delay msms by one clock to find falling edge
----------------------------------------------------------------------------
MSMS_DELAY_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
msms_d1 <= '0';
else
msms_d1 <= cr_i(5);
end if;
end if;
end process MSMS_DELAY_PROCESS;
----------------------------------------------------------------------------
-- Set when a fall edge of msms has occurred and Ro_prev is active
-- This will prevent a throttle condition when a master receiver and
-- trying to initiate a stop condition.
----------------------------------------------------------------------------
MSMS_EDGE_SET_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
msms_set_i <= '0';
elsif ro_prev_i = '1' and cr_i(5) = '0' and msms_d1 = '1' then
msms_set_i <= '1';
elsif (cr_i(5) = '1' and msms_d1 = '0') or Bb = '0' then
msms_set_i <= '0';
else
msms_set_i <= msms_set_i;
end if;
end if;
end process MSMS_EDGE_SET_PROCESS;
Msms_set <= msms_set_i;
----------------------------------------------------------------------------
-- STATUS_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process resets the status register. The status register is read only
----------------------------------------------------------------------------
STATUS_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
sr_i <= (others => '0');
else -- Load Status Register with iic data
sr_i(0) <= not Tx_data_exists;
sr_i(1) <= not Rc_data_Exists;
sr_i(2) <= Rc_fifo_Full;
sr_i(3) <= Tx_fifo_Full; -- addressed by a general call
sr_i(4) <= Srw; -- slave read/write
sr_i(5) <= Bb; -- bus busy
sr_i(6) <= Aas; -- addressed as slave
sr_i(7) <= Abgc; -- addressed by a general call
end if;
end if;
end process STATUS_REGISTER_PROCESS;
----------------------------------------------------------------------------
-- Transmit FIFO CONTROL signal GENERATION
----------------------------------------------------------------------------
-- This process allows the AXI to write data to the write FIFO and assigns
-- that data to the output port and to the internal signals for reading
----------------------------------------------------------------------------
FIFO_GEN_DTR : if C_TX_FIFO_EXIST generate
-------------------------------------------------------------------------
-- FIFO_WR_CNTL_PROCESS - Tx fifo write process
-------------------------------------------------------------------------
FIFO_WR_CNTL_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Tx_fifo_wr <= '0';
elsif
Bus2IIC_WrCE(2) = '1' then
Tx_fifo_wr <= '1';
else
Tx_fifo_wr <= '0';
end if;
end if;
end process FIFO_WR_CNTL_PROCESS;
-------------------------------------------------------------------------
-- FIFO_DTR_REG_PROCESS
-------------------------------------------------------------------------
FIFO_DTR_REG_PROCESS : process (Tx_fifo_data)
begin -- process
Dtr <= Tx_fifo_data;
dtr_i <= Tx_fifo_data;
end process FIFO_DTR_REG_PROCESS;
-------------------------------------------------------------------------
-- Tx_FIFO_RD_PROCESS
-------------------------------------------------------------------------
-- This process generates the Read from the Transmit FIFO
-------------------------------------------------------------------------
Tx_FIFO_RD_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Tx_fifo_rd <= '0';
elsif Rdy_new_xmt = '1' then
Tx_fifo_rd <= '1';
elsif Rdy_new_xmt = '0' --and Tx_data_exists = '1'
then Tx_fifo_rd <= '0';
end if;
end if;
end process Tx_FIFO_RD_PROCESS;
-------------------------------------------------------------------------
-- DTRE_PROCESS
-------------------------------------------------------------------------
-- This process generates the Data Transmit Register Empty Interrupt
-- Interrupt(2)
-------------------------------------------------------------------------
DTRE_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
dtre_i <= '0';
else
dtre_i <= not (Tx_data_exists);
end if;
end if;
end process DTRE_PROCESS;
-------------------------------------------------------------------------
-- Additional FIFO Interrupt
-------------------------------------------------------------------------
-- FIFO_Int_PROCESS generates interrupts back to the IPIF when Tx FIFO
-- exists
-------------------------------------------------------------------------
FIFO_INT_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
IIC2Bus_IntrEvent(7) <= '0';
else
IIC2Bus_IntrEvent(7) <= not Tx_addr(3); -- Tx FIFO half empty
end if;
end if;
end process FIFO_INT_PROCESS;
-------------------------------------------------------------------------
-- Tx_FIFO_RESET_PROCESS
-------------------------------------------------------------------------
-- This process generates the Data Transmit Register Empty Interrupt
-- Interrupt(2)
-------------------------------------------------------------------------
TX_FIFO_RESET_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Tx_fifo_rst <= '1';
else
Tx_fifo_rst <= cr_i(6);
end if;
end if;
end process TX_FIFO_RESET_PROCESS;
end generate FIFO_GEN_DTR;
Dtre <= dtre_i;
----------------------------------------------------------------------------
-- If a read FIFO exists then generate control signals
----------------------------------------------------------------------------
RD_FIFO_CNTRL : if (C_RC_FIFO_EXIST) generate
-------------------------------------------------------------------------
-- WRITE_TO_READ_FIFO_PROCESS
-------------------------------------------------------------------------
WRITE_TO_READ_FIFO_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Rc_fifo_wr <= '0';
-- Load iic Data When new data x-fer complete and not x-mitting
elsif
New_rcv_dta = '1' and new_rcv_dta_d1 = '0' then
Rc_fifo_wr <= '1';
else
Rc_fifo_wr <= '0';
end if;
end if;
end process WRITE_TO_READ_FIFO_PROCESS;
-------------------------------------------------------------------------
-- Assign the Receive FIFO data to the DRR so AXI can read the data
-------------------------------------------------------------------------
AXI_READ_FROM_READ_FIFO_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
Rc_fifo_rd <= '0';
elsif Bus2IIC_RdCE(3) = '1' then
Rc_fifo_rd <= '1';
else
Rc_fifo_rd <= '0';
end if;
end if;
end process AXI_READ_FROM_READ_FIFO_PROCESS;
-------------------------------------------------------------------------
-- Assign the Receive FIFO data to the DRR so AXI can read the data
-------------------------------------------------------------------------
RD_FIFO_DRR_PROCESS : process (Rc_fifo_data)
begin
Drr <= Rc_fifo_data;
drr_i <= Rc_fifo_data;
end process RD_FIFO_DRR_PROCESS;
-------------------------------------------------------------------------
-- Rc_FIFO_PIRQ
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Rc_FIFO_PIRQ register is enabled.
-------------------------------------------------------------------------
Rc_FIFO_PIRQ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
rc_fifo_pirq_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
Bus2IIC_WrCE(8) = '1' then
rc_fifo_pirq_i(4 to 7) <= Bus2IIC_Data(28 to 31);
else
rc_fifo_pirq_i(4 to 7) <= rc_fifo_pirq_i(4 to 7);
end if;
end if;
end process Rc_FIFO_PIRQ_PROCESS;
-------------------------------------------------------------------------
-- RC_FIFO_FULL_PROCESS
-------------------------------------------------------------------------
-- This process throttles the bus when receiving and the RC_FIFO_PIRQ is
-- equalto the Receive FIFO Occupancy value
-------------------------------------------------------------------------
RC_FIFO_FULL_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
ro_prev_i <= '0';
elsif msms_set_i = '1' then
ro_prev_i <= '0';
elsif (rc_fifo_pirq_i(4) = Rc_addr(3) and
rc_fifo_pirq_i(5) = Rc_addr(2) and
rc_fifo_pirq_i(6) = Rc_addr(1) and
rc_fifo_pirq_i(7) = Rc_addr(0)) and
Rc_data_Exists = '1'
then
ro_prev_i <= '1';
else
ro_prev_i <= '0';
end if;
end if;
end process RC_FIFO_FULL_PROCESS;
Ro_prev <= ro_prev_i;
end generate RD_FIFO_CNTRL;
----------------------------------------------------------------------------
-- RCV_OVRUN_PROCESS
----------------------------------------------------------------------------
-- This process determines when the data receive register has had new data
-- written to it without a read of the old data
----------------------------------------------------------------------------
NEW_RECIEVE_DATA_PROCESS : process (Clk) -- delay new_rcv_dta to find edge
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
new_rcv_dta_d1 <= '0';
else
new_rcv_dta_d1 <= New_rcv_dta;
end if;
end if;
end process NEW_RECIEVE_DATA_PROCESS;
----------------------------------------------------------------------------
-- RCV_OVRUN_PROCESS
----------------------------------------------------------------------------
RCV_OVRUN_PROCESS : process (Clk)
begin
-- SRFF set when new data is received, reset when a read of DRR occurs
-- The second SRFF is set when new data is again received before a
-- read of DRR occurs. This sets the Receive Overrun Status Bit
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
ro_a <= '0';
elsif New_rcv_dta = '1' and new_rcv_dta_d1 = '0' then
ro_a <= '1';
elsif New_rcv_dta = '0' and Bus2IIC_RdCE(3) = '1'
then ro_a <= '0';
else
ro_a <= ro_a;
end if;
end if;
end process RCV_OVRUN_PROCESS;
----------------------------------------------------------------------------
-- ADDRESS_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the address register is enabled.
----------------------------------------------------------------------------
ADDRESS_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
adr_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
-- Bus2IIC_WrReq = '1' and Bus2IIC_WrCE(4) = '1' then
Bus2IIC_WrCE(4) = '1' then
adr_i(0 to 7) <= Bus2IIC_Data(24 to 31);
else
adr_i <= adr_i;
end if;
end if;
end process ADDRESS_REGISTER_PROCESS;
Adr <= adr_i;
--PER_BIT_0_TO_31_GEN : for i in 0 to C_S_AXI_DATA_WIDTH-1 generate
-- BIT_0_TO_31_LOOP : process (rback_data, Bus2IIC_RdCE) is
-- begin
-- if (or_reduce(Bus2IIC_RdCE) = '1') then
-- for m in 0 to C_NUM_IIC_REGS-1 loop
-- if (Bus2IIC_RdCE(m) = '1') then
-- IIC2Bus_Data(i) <= rback_data(m*32 + i);
-- else
-- IIC2Bus_Data(i) <= '0';
-- end if;
-- end loop;
-- else
-- IIC2Bus_Data(i) <= '0';
-- end if;
-- end process BIT_0_TO_31_LOOP;
--end generate PER_BIT_0_TO_31_GEN;
OUTPUT_DATA_GEN_P : process (rback_data, Bus2IIC_RdCE, Bus2IIC_Addr) is
begin
if (or_reduce(Bus2IIC_RdCE) = '1') then
--IIC2Bus_Data <= rback_data((32*TO_INTEGER(unsigned(Bus2IIC_Addr(24 to 29))))
-- to ((32*TO_INTEGER(unsigned(Bus2IIC_Addr(24 to 29))))+31)); -- CR
--case Bus2IIC_Addr(C_S_AXI_ADDR_WIDTH-8 to C_S_AXI_ADDR_WIDTH-1) is
case Bus2IIC_Addr(1 to 8) is
when X"00" => IIC2Bus_Data <= rback_data(0 to 31); -- CR
when X"04" => IIC2Bus_Data <= rback_data(32 to 63); -- SR
when X"08" => IIC2Bus_Data <= rback_data(64 to 95); -- TX_FIFO
when X"0C" => IIC2Bus_Data <= rback_data(96 to 127); -- RX_FIFO
when X"10" => IIC2Bus_Data <= rback_data(128 to 159); -- ADR
when X"14" => IIC2Bus_Data <= rback_data(160 to 191); -- TX_FIFO_OCY
when X"18" => IIC2Bus_Data <= rback_data(192 to 223); -- RX_FIFO_OCY
when X"1C" => IIC2Bus_Data <= rback_data(224 to 255); -- TEN_ADR
when X"20" => IIC2Bus_Data <= rback_data(256 to 287); -- RX_FIFO_PIRQ
when X"24" => IIC2Bus_Data <= rback_data(288 to 319); -- GPO
when X"28" => IIC2Bus_Data <= rback_data(320 to 351); -- TSUSTA
when X"2C" => IIC2Bus_Data <= rback_data(352 to 383); -- TSUSTO
when X"30" => IIC2Bus_Data <= rback_data(384 to 415); -- THDSTA
when X"34" => IIC2Bus_Data <= rback_data(416 to 447); -- TSUDAT
when X"38" => IIC2Bus_Data <= rback_data(448 to 479); -- TBUF
when X"3C" => IIC2Bus_Data <= rback_data(480 to 511); -- THIGH
when X"40" => IIC2Bus_Data <= rback_data(512 to 543); -- TLOW
when X"44" => IIC2Bus_Data <= rback_data(544 to 575); -- THDDAT
when others => IIC2Bus_Data <= (others => '0');
end case;
else
IIC2Bus_Data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
----------------------------------------------------------------------------
-- READ_REGISTER_PROCESS
----------------------------------------------------------------------------
rback_data(32*1-8 to 32*1-1) <= cr_i(0 to 7);
rback_data(32*2-9 to 32*2-1) <= '0' & sr_i(0 to 7);--reg_empty & sr_i(0 to 7);
rback_data(32*3-8 to 32*3-1) <= dtr_i(0 to 7);
rback_data(32*4-8 to 32*4-1) <= drr_i(0 to 7);
rback_data(32*5-8 to 32*5-2) <= adr_i(0 to 6);
rback_data(32*6-8 to 32*6-1) <= rtx_i(0 to 7);
rback_data(32*7-8 to 32*7-1) <= rrc_i(0 to 7);
rback_data(32*8-8 to 32*8-1) <= rtn_i(0 to 7);
rback_data(32*9-8 to 32*9-1) <= rpq_i(0 to 7);
----------------------------------------------------------------------------
-- GPO_RBACK_GEN generate
----------------------------------------------------------------------------
GPO_RBACK_GEN : if C_GPO_WIDTH /= 0 generate
rback_data(32*10-C_GPO_WIDTH to 32*10-1)
<= gpo_i(32 - C_GPO_WIDTH to C_S_AXI_DATA_WIDTH - 1);
end generate GPO_RBACK_GEN;
rback_data(32*11-C_SIZE to 32*11-1) <= timing_param_tsusta_i(C_SIZE-1 downto 0);
rback_data(32*12-C_SIZE to 32*12-1) <= timing_param_tsusto_i(C_SIZE-1 downto 0);
rback_data(32*13-C_SIZE to 32*13-1) <= timing_param_thdsta_i(C_SIZE-1 downto 0);
rback_data(32*14-C_SIZE to 32*14-1) <= timing_param_tsudat_i(C_SIZE-1 downto 0);
rback_data(32*15-C_SIZE to 32*15-1) <= timing_param_tbuf_i(C_SIZE-1 downto 0);
rback_data(32*16-C_SIZE to 32*16-1) <= timing_param_thigh_i(C_SIZE-1 downto 0);
rback_data(32*17-C_SIZE to 32*17-1) <= timing_param_tlow_i(C_SIZE-1 downto 0);
rback_data(32*18-C_SIZE to 32*18-1) <= timing_param_thddat_i(C_SIZE-1 downto 0);
rtx_i(0 to 3) <= (others => '0');
rtx_i(4) <= Tx_addr(3);
rtx_i(5) <= Tx_addr(2);
rtx_i(6) <= Tx_addr(1);
rtx_i(7) <= Tx_addr(0);
rrc_i(0 to 3) <= (others => '0');
rrc_i(4) <= Rc_addr(3);
rrc_i(5) <= Rc_addr(2);
rrc_i(6) <= Rc_addr(1);
rrc_i(7) <= Rc_addr(0);
rtn_i(0 to 4) <= (others => '0');
rtn_i(5 to 7) <= ten_adr_i(5 to 7);
rpq_i(0 to 3) <= (others => '0');
rpq_i(4 to 7) <= rc_fifo_pirq_i(4 to 7);
----------------------------------------------------------------------------
-- Interrupts
----------------------------------------------------------------------------
-- Int_PROCESS generates interrupts back to the IPIF
----------------------------------------------------------------------------
INT_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
IIC2Bus_IntrEvent(0 to 6) <= (others => '0');
else
IIC2Bus_IntrEvent(0) <= Al; -- arbitration lost interrupt
IIC2Bus_IntrEvent(1) <= Txer; -- transmit error interrupt
IIC2Bus_IntrEvent(2) <= Tx_under_prev; --dtre_i;
-- Data Tx Register Empty interrupt
IIC2Bus_IntrEvent(3) <= ro_prev_i; --New_rcv_dta;
-- Data Rc Register Full interrupt
IIC2Bus_IntrEvent(4) <= not Bb;
IIC2Bus_IntrEvent(5) <= Aas;
IIC2Bus_IntrEvent(6) <= not Aas;
end if;
end if;
end process INT_PROCESS;
----------------------------------------------------------------------------
-- Ten Bit Slave Address Generate
----------------------------------------------------------------------------
-- Int_PROCESS generates interrupts back to the IPIF
----------------------------------------------------------------------------
TEN_ADR_GEN : if (C_TEN_BIT_ADR = 1) generate
-------------------------------------------------------------------------
-- TEN_ADR_REGISTER_PROCESS
-------------------------------------------------------------------------
TEN_ADR_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
ten_adr_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
Bus2IIC_WrCE(7) = '1' then
ten_adr_i(5 to 7) <= Bus2IIC_Data(29 to 31);
else
ten_adr_i <= ten_adr_i;
end if;
end if;
end process TEN_ADR_REGISTER_PROCESS;
Ten_adr <= ten_adr_i;
end generate TEN_ADR_GEN;
----------------------------------------------------------------------------
-- General Purpose Ouput Register Generate
----------------------------------------------------------------------------
-- Generate the GPO if C_GPO_WIDTH is not equal to zero
----------------------------------------------------------------------------
GPO_GEN : if (C_GPO_WIDTH /= 0) generate
-------------------------------------------------------------------------
-- GPO_REGISTER_PROCESS
-------------------------------------------------------------------------
GPO_REGISTER_PROCESS : process (Clk)
begin -- process
if Clk'event and Clk = '1' then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
gpo_i <= C_DEFAULT_VALUE(C_GPO_WIDTH - 1 downto 0);
elsif -- Load Status Register with AXI
-- data if there is a write CE
--Bus2IIC_WrCE(C_NUM_IIC_REGS - 1) = '1' then
Bus2IIC_WrCE(9) = '1' then
gpo_i(32 - C_GPO_WIDTH to 31) <=
Bus2IIC_Data(32 - C_GPO_WIDTH to 31);
else
gpo_i <= gpo_i;
end if;
end if;
end process GPO_REGISTER_PROCESS;
Gpo <= gpo_i;
end generate GPO_GEN;
----------------------------------------------------------------------------
-- TSUSTA_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tsusta register is enabled.
----------------------------------------------------------------------------
TSUSTA_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
--timing_param_tsusta_i <= (others => '0');
timing_param_tsusta_i <= TSUSTA;
elsif -- Load tsusta Register with AXI
-- data if there is a write request
-- and the tsusta register is enabled
Bus2IIC_WrCE(10) = '1' then
timing_param_tsusta_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsusta_i(C_SIZE-1 downto 0) <= timing_param_tsusta_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUSTA_REGISTER_PROCESS;
Timing_param_tsusta <= timing_param_tsusta_i;
----------------------------------------------------------------------------
-- TSUSTO_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tsusto register is enabled.
----------------------------------------------------------------------------
TSUSTO_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
--timing_param_tsusto_i <= (others => '0');
timing_param_tsusto_i <= TSUSTO;
elsif -- Load tsusto Register with AXI
-- data if there is a write request
-- and the tsusto register is enabled
Bus2IIC_WrCE(11) = '1' then
timing_param_tsusto_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsusto_i(C_SIZE-1 downto 0) <= timing_param_tsusto_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUSTO_REGISTER_PROCESS;
Timing_param_tsusto <= timing_param_tsusto_i;
----------------------------------------------------------------------------
-- THDSTA_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thdsta register is enabled.
----------------------------------------------------------------------------
THDSTA_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_thdsta_i <= THDSTA;
elsif -- Load thdsta Register with AXI
-- data if there is a write request
-- and the thdsta register is enabled
Bus2IIC_WrCE(12) = '1' then
timing_param_thdsta_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thdsta_i(C_SIZE-1 downto 0) <= timing_param_thdsta_i(C_SIZE-1 downto 0);
end if;
end if;
end process THDSTA_REGISTER_PROCESS;
Timing_param_thdsta <= timing_param_thdsta_i;
----------------------------------------------------------------------------
-- TSUDAT_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thdsta register is enabled.
----------------------------------------------------------------------------
TSUDAT_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_tsudat_i <= TSUDAT;
elsif -- Load tsudat Register with AXI
-- data if there is a write request
-- and the tsudat register is enabled
Bus2IIC_WrCE(13) = '1' then
timing_param_tsudat_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsudat_i(C_SIZE-1 downto 0) <= timing_param_tsudat_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUDAT_REGISTER_PROCESS;
Timing_param_tsudat <= timing_param_tsudat_i;
----------------------------------------------------------------------------
-- TBUF_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tbuf register is enabled.
----------------------------------------------------------------------------
TBUF_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_tbuf_i <= TBUF;
elsif -- Load tbuf Register with AXI
-- data if there is a write request
-- and the tbuf register is enabled
Bus2IIC_WrCE(14) = '1' then
timing_param_tbuf_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tbuf_i(C_SIZE-1 downto 0) <= timing_param_tbuf_i(C_SIZE-1 downto 0);
end if;
end if;
end process TBUF_REGISTER_PROCESS;
Timing_param_tbuf <= timing_param_tbuf_i;
----------------------------------------------------------------------------
-- THIGH_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thigh register is enabled.
----------------------------------------------------------------------------
THIGH_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_thigh_i <= HIGH_CNT;
elsif -- Load thigh Register with AXI
-- data if there is a write request
-- and the thigh register is enabled
Bus2IIC_WrCE(15) = '1' then
timing_param_thigh_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thigh_i(C_SIZE-1 downto 0) <= timing_param_thigh_i(C_SIZE-1 downto 0);
end if;
end if;
end process THIGH_REGISTER_PROCESS;
Timing_param_thigh <= timing_param_thigh_i;
----------------------------------------------------------------------------
-- TLOW_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thigh register is enabled.
----------------------------------------------------------------------------
TLOW_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_tlow_i <= LOW_CNT;
elsif -- Load tlow Register with AXI
-- data if there is a write request
-- and the tlow register is enabled
Bus2IIC_WrCE(16) = '1' then
timing_param_tlow_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tlow_i(C_SIZE-1 downto 0) <= timing_param_tlow_i(C_SIZE-1 downto 0);
end if;
end if;
end process TLOW_REGISTER_PROCESS;
Timing_param_tlow <= timing_param_tlow_i;
----------------------------------------------------------------------------
-- THDDAT_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thddat register is enabled.
----------------------------------------------------------------------------
THDDAT_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0_14.iic_pkg.RESET_ACTIVE then
timing_param_thddat_i <= THDDAT;
elsif -- Load thddat Register with AXI
-- data if there is a write request
-- and the thddat register is enabled
Bus2IIC_WrCE(17) = '1' then
timing_param_thddat_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thddat_i(C_SIZE-1 downto 0) <= timing_param_thddat_i(C_SIZE-1 downto 0);
end if;
end if;
end process THDDAT_REGISTER_PROCESS;
Timing_param_thddat <= timing_param_thddat_i;
end architecture RTL;
-------------------------------------------------------------------------------
-- iic_control.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
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-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
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-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic_control.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the main state machines for the iic
-- bus interface logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- - Added function calc_tbuf to calculate the TBUF delay
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Fixed the CR#613282
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.iic_pkg.all;
use axi_iic_v2_0_14.upcnt_n;
use axi_iic_v2_0_14.shift8;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_ACLK_FREQ_HZ-- Specifies AXI clock frequency
-- C_IIC_FREQ -- Maximum IIC frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
--
-- Definition of Ports:
-- Sys_clk -- System clock
-- Reset -- System Reset
-- Sda_I -- IIC serial data input
-- Sda_O -- IIC serial data output
-- Sda_T -- IIC seral data output enable
-- Scl_I -- IIC serial clock input
-- Scl_O -- IIC serial clock output
-- Scl_T -- IIC serial clock output enable
-- Txak -- Value for acknowledge when xmit
-- Gc_en -- General purpose outputs
-- Ro_prev -- Receive over run prevent
-- Dtre -- Data transmit register empty
-- Msms -- Data transmit register empty
-- Msms_rst -- Msms Reset signal
-- Msms_set -- Msms set
-- Rsta -- Repeated start
-- Rsta_rst -- Repeated start Reset
-- Tx -- Master read/write
-- Dtr -- Data transmit register
-- Adr -- IIC slave address
-- Ten_adr -- IIC slave 10 bit address
-- Bb -- Bus busy indicator
-- Dtc -- Data transfer
-- Aas -- Addressed as slave indicator
-- Al -- Arbitration lost indicator
-- Srw -- Slave read/write indicator
-- Txer -- Received acknowledge indicator
-- Abgc -- Addressed by general call indicator
-- Data_i2c -- IIC data for processor
-- New_rcv_dta -- New Receive Data ready
-- Rdy_new_xmt -- New data loaded in shift reg indicator
-- Tx_under_prev -- DTR or Tx FIFO empty IRQ indicator
-- EarlyAckHdr -- ACK_HEADER state strobe signal
-- EarlyAckDataState -- Data ack early acknowledge signal
-- AckDataState -- Data ack acknowledge signal
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity iic_control is
generic(
C_SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_SIZE : integer := 32;
C_TEN_BIT_ADR : integer := 0;
C_SDA_LEVEL : integer := 1;
C_SMBUS_PMBUS_HOST : integer := 0 -- SMBUS/PMBUS support
);
port(
-- System signals
Sys_clk : in std_logic;
Reset : in std_logic;
-- iic bus tristate driver control signals
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Timing_param_tsusta : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsusto : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thdsta : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsudat : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tbuf : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thigh : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tlow : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thddat : in std_logic_vector(C_SIZE-1 downto 0);
-- interface signals from uP
Txak : in std_logic;
Gc_en : in std_logic;
Ro_prev : in std_logic;
Dtre : in std_logic;
Msms : in std_logic;
Msms_rst : out std_logic;
Msms_set : in std_logic;
Rsta : in std_logic;
Rsta_rst : out std_logic;
Tx : in std_logic;
Dtr : in std_logic_vector(7 downto 0);
Adr : in std_logic_vector(7 downto 0);
Ten_adr : in std_logic_vector(7 downto 5);
Bb : out std_logic;
Dtc : out std_logic;
Aas : out std_logic;
Al : out std_logic;
Srw : out std_logic;
Txer : out std_logic;
Abgc : out std_logic;
Data_i2c : out std_logic_vector(7 downto 0);
New_rcv_dta : out std_logic;
Rdy_new_xmt : out std_logic;
Tx_under_prev : out std_logic;
EarlyAckHdr : out std_logic;
EarlyAckDataState : out std_logic;
AckDataState : out std_logic;
reg_empty :out std_logic
);
end iic_control;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of iic_control is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- Bus free time.
constant CLR_REG : std_logic_vector(7 downto 0) := "00000000";
constant START_CNT : std_logic_vector(3 downto 0) := "0000";
constant CNT_DONE : std_logic_vector(3 downto 0) := "1000";
constant ZERO_CNT : std_logic_vector(C_SIZE-1 downto 0):= (others => '0');
constant ZERO : std_logic := '0';
constant ENABLE_N : std_logic := '0';
constant CNT_ALMOST_DONE : std_logic_vector (3 downto 0) := "0111";
type state_type is (IDLE,
HEADER,
ACK_HEADER,
RCV_DATA,
ACK_DATA,
XMIT_DATA,
WAIT_ACK);
signal state : state_type;
type scl_state_type is (SCL_IDLE,
START_WAIT,
START,
START_EDGE,
SCL_LOW_EDGE,
SCL_LOW,
SCL_HIGH_EDGE,
SCL_HIGH,
STOP_EDGE,
STOP_WAIT);
signal scl_state : scl_state_type;
signal next_scl_state : scl_state_type;
signal scl_rin : std_logic; -- sampled version of scl
signal scl_d1 : std_logic; -- sampled version of scl
signal scl_rin_d1 : std_logic; -- delayed version of Scl_rin
signal scl_cout : std_logic; -- combinatorial scl output
signal scl_cout_reg : std_logic; -- registered version of scl_cout
signal scl_rising_edge : std_logic; -- falling edge of SCL
signal scl_falling_edge : std_logic; -- falling edge of SCL
signal scl_f_edg_d1 : std_logic; -- falling edge of SCL delayed one
-- clock
signal scl_f_edg_d2 : std_logic; -- falling edge of SCL delayed two
-- clock
signal scl_f_edg_d3 : std_logic; -- falling edge of SCL delayed three
-- clock
signal sda_rin : std_logic; -- sampled version of sda
signal sda_d1 : std_logic; -- sampled version of sda
signal sda_rin_d1 : std_logic; -- delayed version of sda_rin
signal sda_falling : std_logic; -- Pulses when SDA falls
signal sda_rising : std_logic; -- Pulses when SDA rises
signal sda_changing : std_logic; -- Pulses when SDA changes
signal sda_setup : std_logic; -- SDA setup time in progress
signal sda_setup_cnt : std_logic_vector (C_SIZE-1 downto 0);
-- SDA setup time count
signal sda_cout : std_logic; -- combinatorial sda output
signal sda_cout_reg : std_logic; -- registered version of sda_cout
signal sda_cout_reg_d1 : std_logic; -- delayed sda output for arb
-- comparison
signal sda_sample : std_logic; -- SDA_RIN sampled at SCL rising edge
signal slave_sda : std_logic; -- sda value when slave
signal master_sda : std_logic; -- sda value when master
signal sda_oe : std_logic;
signal master_slave : std_logic; -- 1 if master, 0 if slave
-- Shift Register and the controls
signal shift_reg : std_logic_vector(7 downto 0); -- iic data shift reg
signal shift_out : std_logic;
signal shift_reg_en : std_logic;
signal shift_reg_ld : std_logic;
signal shift_reg_ld_d1 : std_logic;
signal i2c_header : std_logic_vector(7 downto 0);-- I2C header register
signal i2c_header_en : std_logic;
signal i2c_header_ld : std_logic;
signal i2c_shiftout : std_logic;
-- Used to check slave address detected
signal addr_match : std_logic;
signal arb_lost : std_logic; -- 1 if arbitration is lost
signal msms_d1 : std_logic; -- Msms processed to initiate a stop
-- sequence after data has been transmitted
signal msms_d2 : std_logic; -- delayed sample of msms_d1
signal msms_rst_i : std_logic; -- internal msms_rst
signal detect_start : std_logic; -- START condition has been detected
signal detect_stop : std_logic; -- STOP condition has been detected
signal detect_stop_b: std_logic;
signal sm_stop : std_logic; -- STOP condition needs to be generated
-- from state machine
signal bus_busy : std_logic; -- indicates that the bus is busy
-- set when START, cleared when STOP
signal bus_busy_d1 : std_logic; -- delayed sample of bus busy
signal gen_start : std_logic; -- uP wants to generate a START
signal gen_stop : std_logic; -- uP wants to generate a STOP
signal rep_start : std_logic; -- uP wants to generate a repeated START
signal stop_scl : std_logic; -- signal in SCL state machine
-- indicating a STOP
signal stop_scl_reg : std_logic; -- registered version of STOP_SCL
-- Bit counter 0 to 7
signal bit_cnt : std_logic_vector(3 downto 0);
signal bit_cnt_ld : std_logic;
signal bit_cnt_clr : std_logic;
signal bit_cnt_en : std_logic;
-- Clock Counter
signal clk_cnt : std_logic_vector (C_SIZE-1 downto 0);
signal clk_cnt_rst : std_logic;
signal clk_cnt_en : std_logic;
signal stop_start_wait : std_logic;
-- the following signals are only here because Viewlogic's VHDL compiler won't
-- allow a constant to be used in a component instantiation
signal reg_clr : std_logic_vector(7 downto 0);
signal zero_sig : std_logic;
signal cnt_zero : std_logic_vector(C_SIZE-1 downto 0);
signal cnt_start : std_logic_vector(3 downto 0);
signal data_i2c_i : std_logic_vector(7 downto 0);
signal aas_i : std_logic; -- internal addressed as slave
-- signal
signal srw_i : std_logic; -- internal slave read write signal
signal abgc_i : std_logic; -- internal addressed by a general
-- call
signal dtc_i : std_logic; -- internal data transmit compete
-- signal
signal dtc_i_d1 : std_logic; -- delayed internal data transmit
-- complete
signal dtc_i_d2 : std_logic; -- 2nd register delay of dtc
signal al_i : std_logic; -- internal arbitration lost signal
signal al_prevent : std_logic; -- prevent arbitration lost when
-- last word
signal rdy_new_xmt_i : std_logic; -- internal ready to transmit new
-- data
signal tx_under_prev_i : std_logic; -- TX underflow prevent signal
signal rsta_tx_under_prev : std_logic; -- Repeated Start Tx underflow
-- prevent
signal rsta_d1 : std_logic; -- Delayed one clock version of Rsta
signal dtre_d1 : std_logic; -- Delayed one clock version of Dtre
signal txer_i : std_logic; -- internal Txer signal
signal txer_edge : std_logic; -- Pulse for Txer IRQ
-- the following signal are used only when 10-bit addressing has been
-- selected
signal msb_wr : std_logic; -- the 1st byte of 10 bit addressing
-- comp
signal msb_wr_d : std_logic; -- delayed version of msb_wr
signal msb_wr_d1 : std_logic; -- delayed version of msb_wr_d
signal sec_addr : std_logic := '0'; -- 2nd byte qualifier
signal sec_adr_match : std_logic; -- 2nd byte compare
signal adr_dta_l : std_logic := '0'; -- prevents 2nd adr byte load
-- in DRR
signal new_rcv_dta_i : std_logic; -- internal New_rcv_dta
signal ro_prev_d1 : std_logic; -- delayed version of Ro_prev
signal gen_stop_and_scl_hi : std_logic; -- signal to prevent SCL state
-- machine from getting stuck during a No Ack
signal setup_cnt_rst : std_logic;
signal tx_under_prev_d1 : std_logic;
signal tx_under_prev_fe : std_logic;
signal rsta_re : std_logic;
signal gen_stop_d1 : std_logic;
signal gen_stop_re : std_logic;
----Mathew
signal shift_cnt : std_logic_vector(8 downto 0);
-- signal reg_empty : std_logic;
----------
begin
----------------------------------------------------------------------------
-- SCL Tristate driver controls for open-collector emulation
----------------------------------------------------------------------------
Scl_T <= '0' when scl_cout_reg = '0'
-- Receive fifo overflow throttle condition
or Ro_prev = '1'
-- SDA changing requires additional setup to SCL change
or (sda_setup = '1' )
-- Restart w/ transmit underflow prevention throttle
-- condition
or rsta_tx_under_prev = '1' else
'1';
Scl_O <= '0';
----------------------------------------------------------------------------
-- SDA Tristate driver controls for open-collector emulation
----------------------------------------------------------------------------
Sda_T <= '0' when ((master_slave = '1' and arb_lost = '0'
and sda_cout_reg = '0')
or (master_slave = '0' and slave_sda = '0')
or stop_scl_reg = '1') else
'1';
Sda_O <= '0';
-- the following signals are only here because Viewlogic's VHDL compiler
-- won't allow a constant to be used in a component instantiation
reg_clr <= CLR_REG;
zero_sig <= ZERO;
cnt_zero <= ZERO_CNT;
cnt_start <= START_CNT;
----------------------------------------------------------------------------
-- INT_DTRE_RSTA_DELAY_PROCESS
----------------------------------------------------------------------------
-- This process delays Dtre and RSTA by one clock to edge detect
-- Dtre = data transmit register empty
-- Rsta = firmware restart command
----------------------------------------------------------------------------
INT_DTRE_RSTA_DELAY_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
rsta_d1 <= '0';
dtre_d1 <= '0';
ro_prev_d1 <= '0';
gen_stop_d1 <= '0';
tx_under_prev_d1 <= '0';
else
rsta_d1 <= Rsta;
dtre_d1 <= Dtre;
ro_prev_d1 <= Ro_prev;
gen_stop_d1 <= gen_stop;
tx_under_prev_d1 <= tx_under_prev_i;
end if;
end if;
end process INT_DTRE_RSTA_DELAY_PROCESS;
tx_under_prev_fe <= tx_under_prev_d1 and not tx_under_prev_i;
rsta_re <= Rsta and not rsta_d1 ;
gen_stop_re <= gen_stop and not gen_stop_d1;
----------------------------------------------------------------------------
-- INT_RSTA_TX_UNDER_PREV_PROCESS
----------------------------------------------------------------------------
-- This process creates a signal that prevent SCL from going high when a
-- underflow condition would be caused, by a repeated start condition.
----------------------------------------------------------------------------
INT_RSTA_TX_UNDER_PREV_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
rsta_tx_under_prev <= '0';
elsif (Rsta = '1' and rsta_d1 = '0' and Dtre = '1' ) then
rsta_tx_under_prev <= '1';
elsif (Dtre = '0' and dtre_d1 = '1') then
rsta_tx_under_prev <= '0';
else
rsta_tx_under_prev <= rsta_tx_under_prev;
end if;
end if;
end process INT_RSTA_TX_UNDER_PREV_PROCESS;
----------------------------------------------------------------------------
-- INT_TX_UNDER_PREV_PROCESS
----------------------------------------------------------------------------
-- This process creates a signal that prevent SCL from going high when a
-- underflow condition would be caused. Transmit underflow can occur in both
-- master and slave situations
----------------------------------------------------------------------------
INT_TX_UNDER_PREV_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
tx_under_prev_i <= '0';
elsif (Dtre = '1' and (state = WAIT_ACK or state = ACK_HEADER)
and scl_falling_edge = '1' and gen_stop = '0'
and ((aas_i = '0' and srw_i = '0')
or (aas_i = '1' and srw_i = '1'))) then
tx_under_prev_i <= '1';
elsif (state = RCV_DATA or state = IDLE or Dtre='0') then
tx_under_prev_i <= '0';
end if;
end if;
end process INT_TX_UNDER_PREV_PROCESS;
Tx_under_prev <= tx_under_prev_i;
----------------------------------------------------------------------------
-- SDASETUP
----------------------------------------------------------------------------
-- Whenever SDA changes there is an associated setup time that must be
-- obeyed before SCL can change. (The exceptions are starts/stops which
-- haven't other timing specifications.) It doesn't matter whether this is
-- a Slave | Master, TX | RX. The "setup" counter and the "sdasetup" process
-- guarantee this time is met regardless of the devices on the bus and their
-- attempts to manage setup time. The signal sda_setup, when asserted,
-- causes SCL to be held low until the setup condition is removed. Anytime a
-- change in SDA is detected on the bus the setup process is invoked. Also,
-- sda_setup is asserted if the transmit throttle condition is active.
-- When it deactivates, SDA **may** change on the SDA bus. In this way,
-- the SCL_STATE machine will be held off as well because it waits for SCL
-- to actually go high.
----------------------------------------------------------------------------
SETUP_CNT : entity axi_iic_v2_0_14.upcnt_n
generic map (
C_SIZE => C_SIZE
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_zero,
Cnt_en => sda_setup,
Load => sda_changing,
Qout => sda_setup_cnt
);
----------------------------------------------------------------------------
-- SDASETUP Process
----------------------------------------------------------------------------
SDASETUP : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
sda_setup <= '0';
elsif (
-- If SDA is changing on the bus then enforce setup time
sda_changing = '1'
-- or if SDA is about to change ...
or tx_under_prev_i = '1') -- modified
-- For either of the above cases the controller only cares
-- about SDA setup when it is legal to change SDA.
and scl_rin='0' then
sda_setup <= '1';
elsif (sda_setup_cnt=Timing_param_tsudat) then
sda_setup <= '0';
end if;
end if;
end process SDASETUP;
----------------------------------------------------------------------------
-- Arbitration Process
-- This process checks the master's outgoing SDA with the incoming SDA to
-- determine if control of the bus has been lost. SDA is checked only when
-- SCL is high and during the states HEADER and XMIT_DATA (when data is
-- actively being clocked out of the controller). When arbitration is lost,
-- a Reset is generated for the Msms bit per the product spec.
-- Note that when arbitration is lost, the mode is switched to slave.
-- arb_lost stays set until scl state machine goes to IDLE state
----------------------------------------------------------------------------
ARBITRATION : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
arb_lost <= '0';
msms_rst_i <= '0';
elsif scl_state = SCL_IDLE or scl_state = STOP_WAIT then
arb_lost <= '0';
msms_rst_i <= '0';
elsif (master_slave = '1') then
-- Actively generating SCL clock as the master and (possibly)
-- participating in multi-master arbitration.
if (scl_rising_edge='1'
and (state = HEADER or state = XMIT_DATA)) then
if (sda_cout_reg='1' and sda_rin = '0') then
-- Other master drove SDA to 0 but the controller is trying
-- to drive a 1. That is the exact case for loss of
-- arbitration
arb_lost <= '1';
msms_rst_i <= '1';
else
arb_lost <= '0';
msms_rst_i <= '0';
end if;
else
msms_rst_i <= '0';
end if;
end if;
end if;
end process ARBITRATION;
Msms_rst <= msms_rst_i
-- The spec states that the Msms bit should be cleared when an
-- address is not-acknowledged. The sm_stop indicates that
-- a not-acknowledge occured on either a data or address
-- (header) transfer. This fixes CR439859.
or sm_stop;
----------------------------------------------------------------------------
-- SCL_GENERATOR_COMB Process
-- This process generates SCL and SDA when in Master mode. It generates the
-- START and STOP conditions. If arbitration is lost, SCL will not be
-- generated until the end of the byte transfer.
----------------------------------------------------------------------------
SCL_GENERATOR_COMB : process (
scl_state,
arb_lost,
sm_stop,
gen_stop,
rep_start,
bus_busy,
gen_start,
master_slave,
stop_scl_reg,
clk_cnt,
scl_rin,
sda_rin,
state,
sda_cout_reg,
master_sda,
detect_stop_b,
stop_start_wait,
Timing_param_tsusta,
Timing_param_tsusto,
Timing_param_thdsta,
Timing_param_thddat,
Timing_param_tbuf,
Timing_param_tlow,
Timing_param_thigh
)
begin
-- state machine defaults
scl_cout <= '1';
sda_cout <= sda_cout_reg;
stop_scl <= stop_scl_reg;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
next_scl_state <= scl_state;
Rsta_rst <= (ENABLE_N);
stop_start_wait <= detect_stop_b;
case scl_state is
when SCL_IDLE =>
sda_cout <= '1';
stop_scl <= '0';
clk_cnt_en <= detect_stop_b;
clk_cnt_rst <= not(detect_stop_b);
stop_start_wait <= detect_stop_b;
if clk_cnt = Timing_param_tbuf then
clk_cnt_rst <= '1';
clk_cnt_en <= '0';
stop_start_wait <= '0';
end if;
-- leave IDLE state when master, bus is idle, and gen_start
if master_slave = '1' and bus_busy = '0' and gen_start = '1' then
if stop_start_wait = '1' then
next_scl_state <= START_WAIT;
else
next_scl_state <= START;
end if;
else
next_scl_state <= SCL_IDLE;
end if;
when START_WAIT =>
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
stop_scl <= '0';
if clk_cnt = Timing_param_tbuf then
next_scl_state <= START;
stop_start_wait <= '0';
else
next_scl_state <= START_WAIT;
end if;
when START =>
-- generate start condition
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
sda_cout <= '0';
stop_scl <= '0';
if sda_rin='0' then
next_scl_state <= START_EDGE;
else
next_scl_state <= START;
end if;
when START_EDGE =>
-- This state ensures that the hold time for the (repeated) start
-- condition is met. The hold time is measured from the Vih level
-- of SDA so it is critical for SDA to be sampled low prior to
-- starting the hold time counter.
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
-- generate Reset for repeat start bit if repeat start condition
if rep_start = '1' then
Rsta_rst <= not(ENABLE_N);
end if;
if clk_cnt = Timing_param_thdsta then
next_scl_state <= SCL_LOW_EDGE;
else
next_scl_state <= START_EDGE;
end if;
when SCL_LOW_EDGE =>
clk_cnt_rst <= '1';
scl_cout <= '0';
stop_scl <= '0';
if (scl_rin='0') then
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
end if;
if ((scl_rin = '0') and (clk_cnt = Timing_param_thddat)) then
-- SCL sampled to be 0 so everything on the bus can see that it
-- is low too. The very large propagation delays caused by
-- potentially large (~300ns or more) fall time should not be
-- ignored by the controller.It must VERIFY that the bus is low.
next_scl_state <= SCL_LOW;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
else
next_scl_state <= SCL_LOW_EDGE;
end if;
when SCL_LOW =>
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
scl_cout <= '0';
stop_scl <= '0';
-- SDA (the data) can only be changed when SCL is low. Note that
-- STOPS and RESTARTS could appear after the SCL low period
-- has expired because the controller is throttled.
if (sm_stop = '1' or gen_stop = '1')
and state /= ACK_DATA
and state /= ACK_HEADER
and state /= WAIT_ACK then
stop_scl <= '1';
-- Pull SDA low in anticipation of raising it to generate the
-- STOP edge
sda_cout <= '0';
elsif rep_start = '1' then
-- Release SDA in anticipation of dropping it to generate the
-- START edge
sda_cout <= '1';
else
sda_cout <= master_sda;
end if;
-- Wait until minimum low clock period requirement is met then
-- proceed to release the SCL_COUT so that it is "possible" for the
-- scl clock to go high on the bus. Note that a SLAVE device can
-- continue to hold SCL low to throttle the bus OR the master
-- itself may hold SCL low because of an internal throttle
-- condition.
if clk_cnt = Timing_param_tlow then
next_scl_state <= SCL_HIGH_EDGE;
else
next_scl_state <= SCL_LOW;
end if;
when SCL_HIGH_EDGE =>
clk_cnt_rst <= '1';
stop_scl <= '0';
-- SCL low time met. Try to release SCL to make it go high.
scl_cout <= '1';
-- SDA (the data) can only be changed when SCL is low. In this
-- state the fsm wants to change SCL to high and is waiting to see
-- it go high. However, other processes may be inhibiting SCL from
-- going high because the controller is throttled. While throttled,
-- and scl is still low:
-- (1) a STOP may be requested by the firmware, **OR**
-- (2) a RESTART may be requested (with or without data available)
-- by the firmware, **OR**
-- (3) new data may get loaded into the TX_FIFO and the first bit
-- is available to be loaded onto the SDA pin
-- Removed this condition as sda_cout should not go low when
-- SCL goes high. SDA should be changed in SCL_LOW state.
if (sm_stop = '1' or gen_stop = '1')
and state /= ACK_DATA
and state /= ACK_HEADER
and state /= WAIT_ACK then
stop_scl <= '1';
-- -- Pull SDA low in anticipation of raising it to generate the
-- -- STOP edge
sda_cout <= '0';
elsif rep_start = '1' then
--if stop_scl_reg = '1' then
-- stop_scl <= '1';
-- sda_cout <= '0';
--elsif rep_start = '1' then
-- Release SDA in anticipation of dropping it to generate the
-- START edge
sda_cout <= '1';
else
sda_cout <= master_sda;
end if;
-- Nothing in the controller should
-- a) sample SDA_RIN until the controller actually verifies that
-- SCL has gone high, and
-- b) change SDA_COUT given that it is trying to change SCL now.
-- Note that other processes may inhibit SCL from going high to
-- wait for the transmit data register to be filled with data. In
-- that case data setup requirements imposed by the I2C spec must
-- be satisfied. Regardless, the SCL clock generator can wait here
-- in SCL_HIGH_EDGE until that is accomplished.
if (scl_rin='1') then
next_scl_state <= SCL_HIGH;
else
next_scl_state <= SCL_HIGH_EDGE;
end if;
when SCL_HIGH =>
-- SCL is now high (released) on the external bus. At this point
-- the state machine doesn't have to worry about any throttle
-- conditions -- by definition they are removed as SCL is no longer
-- low. The firmware **must** signal the desire to STOP or Repeat
-- Start when throttled.
-- It is decision time. Should another SCL clock pulse get
-- generated? (IE a low period + high period?) The answer depends
-- on whether the previous clock was a DATA XFER clock or an ACK
-- CLOCK. Should a Repeated Start be generated? Should a STOP be
-- generated?
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
scl_cout <= '1';
if (arb_lost='1') then
-- No point in continuing! The other master will generate the
-- clock.
next_scl_state <= SCL_IDLE;
else
-- Determine HIGH time based on need to generate a repeated
-- start, a stop or the full high period of the SCL clock.
-- (Without some analysis it isn't clear if rep_start and
-- stop_scl_reg are mutually exclusive. Hence the priority
-- encoder.)
if rep_start = '1' then
if (clk_cnt=Timing_param_tsusta) then
-- The hidden assumption here is that SDA has been released
-- by the slave|master receiver after the ACK clock so that
-- a repeated start is possible
next_scl_state <= START;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
end if;
elsif stop_scl_reg = '1' then
if (clk_cnt=Timing_param_tsusto) then
-- The hidden assumption here is that SDA has been pulled
-- low by the master after the ACK clock so that a
-- stop is possible
next_scl_state <= STOP_EDGE;
clk_cnt_rst <= '1';
clk_cnt_en <= '0';
sda_cout <= '1'; -- issue the stop
stop_scl <= '0';
end if;
else
-- Neither repeated start nor stop requested
if clk_cnt= Timing_param_thigh then
next_scl_state <= SCL_LOW_EDGE;
clk_cnt_rst <= '1';
clk_cnt_en <= '0';
end if;
end if;
end if;
when STOP_EDGE =>
if (sda_rin='1') then
next_scl_state <= STOP_WAIT;
else
next_scl_state <= STOP_EDGE;
end if;
when STOP_WAIT =>
-- The Stop setup time was satisfied and SDA was sampled high
-- indicating the stop occured. Now wait the TBUF time required
-- between a stop and the next start.
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
stop_scl <= '0';
if clk_cnt = Timing_param_tbuf then
next_scl_state <= SCL_IDLE;
else
next_scl_state <= STOP_WAIT;
end if;
-- coverage off
when others =>
next_scl_state <= SCL_IDLE;
-- coverage on
end case;
end process SCL_GENERATOR_COMB;
----------------------------------------------------------------------------
--PROCESS : SCL_GENERATOR_REGS
----------------------------------------------------------------------------
SCL_GENERATOR_REGS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
scl_state <= SCL_IDLE;
sda_cout_reg <= '1';
scl_cout_reg <= '1';
stop_scl_reg <= '0';
else
scl_state <= next_scl_state;
sda_cout_reg <= sda_cout;
-- Ro_prev = receive overflow prevent = case where controller must
-- hold SCL low itself until receive fifo is emptied by the firmware
scl_cout_reg <= scl_cout and not Ro_prev;
stop_scl_reg <= stop_scl;
end if;
end if;
end process SCL_GENERATOR_REGS;
----------------------------------------------------------------------------
-- Clock Counter Implementation
-- The following code implements the counter that divides the sys_clock for
-- creation of SCL. Control lines for this counter are set in SCL state
-- machine
----------------------------------------------------------------------------
CLKCNT : entity axi_iic_v2_0_14.upcnt_n
generic map (
C_SIZE => C_SIZE
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_zero,
Cnt_en => clk_cnt_en,
Load => clk_cnt_rst,
Qout => clk_cnt
);
----------------------------------------------------------------------------
-- Input Registers Process
-- This process samples the incoming SDA and SCL with the system clock
----------------------------------------------------------------------------
sda_rin <= Sda_I;
scl_rin <= Scl_I;
INPUT_REGS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
sda_rin_d1 <= sda_rin; -- delay sda_rin to find edges
scl_rin_d1 <= scl_rin; -- delay Scl_rin to find edges
sda_cout_reg_d1 <= sda_cout_reg;
end if;
end process INPUT_REGS;
----------------------------------------------------------------------------
-- Master Slave Mode Select Process
-- This process allows software to write the value of Msms with each data
-- word to be transmitted. So writing a '0' to Msms will initiate a stop
-- sequence on the I2C bus after the that byte in the DTR has been sent.
----------------------------------------------------------------------------
MSMS_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msms_d1 <= '0';
msms_d2 <= '0';
else
msms_d1 <= (Msms and not msms_rst_i)
or ((msms_d1 and not (dtc_i_d1 and not dtc_i_d2) and
not msms_rst_i)
and not Msms_set and not txer_i) ;
msms_d2 <= msms_d1;
end if;
end if;
end process MSMS_PROCESS;
----------------------------------------------------------------------------
-- START/STOP Detect Process
-- This process detects the start condition by finding the falling edge of
-- sda_rin and checking that SCL is high. It detects the stop condition on
-- the bus by finding a rising edge of SDA when SCL is high.
----------------------------------------------------------------------------
sda_falling <= sda_rin_d1 and not sda_rin;
sda_rising <= not sda_rin_d1 and sda_rin;
sda_changing <= sda_falling or sda_rising or tx_under_prev_fe
or rsta_re or gen_stop_re;
----------------------------------------------------------------------------
-- START Detect Process
----------------------------------------------------------------------------
START_DET_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or state = HEADER then
detect_start <= '0';
elsif sda_falling = '1' then
if scl_rin = '1' then
detect_start <= '1';
else
detect_start <= '0';
end if;
end if;
end if;
end process START_DET_PROCESS;
----------------------------------------------------------------------------
-- STOP Detect Process
----------------------------------------------------------------------------
STOP_DET_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or detect_start = '1' then
detect_stop <= '0';
elsif sda_rising = '1' then
if scl_rin = '1' then
detect_stop <= '1';
else
detect_stop <= '0';
end if;
elsif msms_d2 = '0' and msms_d1 = '1' then
-- rising edge of Msms - generate start condition
detect_stop <= '0'; -- clear on a generate start condition
end if;
end if;
end process STOP_DET_PROCESS;
STOP_DET_PROCESS_B : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or detect_start = '1' then
detect_stop_b <= '0';
elsif sda_rising = '1' then
if scl_rin = '1' then
detect_stop_b <= '1';
else
detect_stop_b <= '0';
end if;
elsif scl_state = START then
-- rising edge of Msms - generate start condition
detect_stop_b <= '0'; -- clear on a generate start condition
end if;
end if;
end process STOP_DET_PROCESS_B;
----------------------------------------------------------------------------
-- Bus Busy Process
-- This process sets bus_busy as soon as START is detected which would
-- always set arb lost (Al).
----------------------------------------------------------------------------
SET_BUS_BUSY_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bus_busy <= '0';
else
if detect_stop = '1' then
bus_busy <= '0';
elsif detect_start = '1' then
bus_busy <= '1';
end if;
end if;
end if;
end process SET_BUS_BUSY_PROCESS;
----------------------------------------------------------------------------
-- BUS_BUSY_REG_PROCESS:
-- This process describes a delayed version of the bus busy bit which is
-- used to determine arb lost (Al).
----------------------------------------------------------------------------
BUS_BUSY_REG_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bus_busy_d1 <= '0';
else
bus_busy_d1 <= bus_busy;
end if;
end if;
end process BUS_BUSY_REG_PROCESS;
----------------------------------------------------------------------------
-- GEN_START_PROCESS
-- This process detects the rising and falling edges of Msms and sets
-- signals to control generation of start condition
----------------------------------------------------------------------------
GEN_START_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_start <= '0';
else
if msms_d2 = '0' and msms_d1 = '1' then
-- rising edge of Msms - generate start condition
gen_start <= '1';
elsif detect_start = '1' then
gen_start <= '0';
end if;
end if;
end if;
end process GEN_START_PROCESS;
----------------------------------------------------------------------------
-- GEN_STOP_PROCESS
-- This process detects the rising and falling edges of Msms and sets
-- signals to control generation of stop condition
----------------------------------------------------------------------------
GEN_STOP_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_stop <= '0';
else
if arb_lost = '0' and msms_d2 = '1' and msms_d1 = '0' then
-- falling edge of Msms - generate stop condition only
-- if arbitration has not been lost
gen_stop <= '1';
elsif detect_stop = '1' then
gen_stop <= '0';
end if;
end if;
end if;
end process GEN_STOP_PROCESS;
----------------------------------------------------------------------------
-- GEN_MASTRE_SLAVE_PROCESS
-- This process sets the master slave bit based on Msms if and only if
-- it is not in the middle of a cycle, i.e. bus_busy = '0'
----------------------------------------------------------------------------
GEN_MASTRE_SLAVE_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_slave <= '0';
else
if bus_busy = '0' then
master_slave <= msms_d1;
elsif arb_lost = '1' then
master_slave <= '0';
else
master_slave <= master_slave;
end if;
end if;
end if;
end process GEN_MASTRE_SLAVE_PROCESS;
rep_start <= Rsta; -- repeat start signal is Rsta control bit
----------------------------------------------------------------------------
-- GEN_STOP_AND_SCL_HIGH
----------------------------------------------------------------------------
-- This process does not go high until both gen_stop and SCL have gone high
-- This is used to prevent the SCL state machine from getting stuck when a
-- slave no acks during the last data byte being transmitted
----------------------------------------------------------------------------
GEN_STOP_AND_SCL_HIGH : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_stop_and_scl_hi <= '0';
elsif gen_stop = '0' then
gen_stop_and_scl_hi <= '0'; --clear
elsif gen_stop = '1' and scl_rin = '1' then
gen_stop_and_scl_hi <= '1';
else
gen_stop_and_scl_hi <= gen_stop_and_scl_hi; --hold condition
end if;
end if;
end process GEN_STOP_AND_SCL_HIGH;
----------------------------------------------------------------------------
-- SCL_EDGE_PROCESS
----------------------------------------------------------------------------
-- This process generates a 1 Sys_clk wide pulse for both the rising edge
-- and the falling edge of SCL_RIN
----------------------------------------------------------------------------
SCL_EDGE_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
scl_falling_edge <= '0';
scl_rising_edge <= '0';
scl_f_edg_d1 <= '0';
scl_f_edg_d2 <= '0';
scl_f_edg_d3 <= '0';
else
scl_falling_edge <= scl_rin_d1 and (not scl_rin); -- 1 to 0
scl_rising_edge <= (not scl_rin_d1) and scl_rin; -- 0 to 1
scl_f_edg_d1 <= scl_falling_edge;
scl_f_edg_d2 <= scl_f_edg_d1;
scl_f_edg_d3 <= scl_f_edg_d2;
end if;
end if;
end process SCL_EDGE_PROCESS;
----------------------------------------------------------------------------
-- EARLY_ACK_HDR_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- the ACK_HEADER state
----------------------------------------------------------------------------
EARLY_ACK_HDR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
EarlyAckHdr <= '0';
elsif (scl_f_edg_d3 = '1' and state = ACK_HEADER) then
EarlyAckHdr <= '1';
else
EarlyAckHdr <= '0';
end if;
end if;
end process EARLY_ACK_HDR_PROCESS;
----------------------------------------------------------------------------
-- ACK_DATA_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- ACK_DATA state
----------------------------------------------------------------------------
ACK_DATA_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
AckDataState <= '0';
elsif (state = ACK_DATA) then
AckDataState <= '1';
else
AckDataState <= '0';
end if;
end if;
end process ACK_DATA_PROCESS;
----------------------------------------------------------------------------
-- EARLY_ACK_DATA_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- the ACK_DATA ot RCV_DATA state state
----------------------------------------------------------------------------
EARLY_ACK_DATA_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
EarlyAckDataState <= '0';
elsif (state = ACK_DATA or (state = RCV_DATA and
(bit_cnt = CNT_ALMOST_DONE or bit_cnt = CNT_DONE))) then
EarlyAckDataState <= '1';
else
EarlyAckDataState <= '0';
end if;
end if;
end process EARLY_ACK_DATA_PROCESS;
----------------------------------------------------------------------------
-- uP Status Register Bits Processes
-- Dtc - data transfer complete. Since this only checks whether the
-- bit_cnt="0111" it will be true for both data and address transfers.
-- While one byte of data is being transferred, this bit is cleared.
-- It is set by the falling edge of the 9th clock of a byte transfer and
-- is not cleared at Reset
----------------------------------------------------------------------------
DTC_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
dtc_i <= '0';
elsif scl_falling_edge = '1' then
if bit_cnt = "0111" then
dtc_i <= '1';
else
dtc_i <= '0';
end if;
end if;
end if;
end process DTC_I_BIT;
Dtc <= dtc_i;
----------------------------------------------------------------------------
-- DTC_DELAY_PROCESS
----------------------------------------------------------------------------
DTC_DELAY_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
dtc_i_d1 <= '0';
dtc_i_d2 <= '0';
else
dtc_i_d1 <= dtc_i;
dtc_i_d2 <= dtc_i_d1;
end if;
end if;
end process DTC_DELAY_PROCESS;
----------------------------------------------------------------------------
-- aas_i - Addressed As Slave Bit
----------------------------------------------------------------------------
-- When its own specific address (adr) matches the I2C Address, this bit is
-- set.
-- Then the CPU needs to check the Srw bit and this bit when a
-- TX-RX mode accordingly.
----------------------------------------------------------------------------
AAS_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
aas_i <= '0';
elsif detect_stop = '1' or addr_match = '0' then
aas_i <= '0';
elsif state = ACK_HEADER then
aas_i <= addr_match;
-- the signal address match compares adr with I2_ADDR
else
aas_i <= aas_i;
end if;
end if;
end process AAS_I_BIT;
----------------------------------------------------------------------------
-- INT_AAS_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal aas_i signal to the output port Aas
----------------------------------------------------------------------------
INT_AAS_PROCESS : process (aas_i, sec_adr_match)
begin -- process
Aas <= aas_i and sec_adr_match;
end process INT_AAS_PROCESS;
----------------------------------------------------------------------------
-- Bb - Bus Busy Bit
----------------------------------------------------------------------------
-- This bit indicates the status of the bus. This bit is set when a START
-- signal is detected and cleared when a stop signal is detected. It is
-- also cleared on Reset. This bit is identical to the signal bus_busy set
-- in the process set_bus_busy.
----------------------------------------------------------------------------
Bb <= bus_busy;
----------------------------------------------------------------------------
-- Al - Arbitration Lost Bit
----------------------------------------------------------------------------
-- This bit is set when the arbitration procedure is lost.
-- Arbitration is lost when:
-- 1. SDA is sampled low when the master drives high during addr or data
-- transmit cycle
-- 2. SDA is sampled low when the master drives high during the
-- acknowledge bit of a data receive cycle
-- 3. A start cycle is attempted when the bus is busy
-- 4. A repeated start is requested in slave mode
-- 5. A stop condition is detected that the master did not request it.
-- This bit is cleared upon Reset and when the software writes a '0' to it
-- Conditions 1 & 2 above simply result in sda_rin not matching sda_cout
-- while SCL is high. This design will not generate a START condition while
-- the bus is busy. When a START is detected, this hardware will set the bus
-- busy bit and gen_start stays set until detect_start asserts, therefore
-- will have to compare with a delayed version of bus_busy. Condition 3 is
-- really just a check on the uP software control registers as is condition
-- 4. Condition 5 is also taken care of by the fact that sda_rin does not
-- equal sda_cout, however, this process also tests for if a stop condition
-- has been detected when this master did not generate it
----------------------------------------------------------------------------
AL_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
al_i <= '0';
elsif master_slave = '1' then
if (arb_lost = '1') or
(bus_busy_d1 = '1' and gen_start = '1') or
(detect_stop = '1' and al_prevent = '0' and sm_stop = '0') then
al_i <= '1';
else
al_i <= '0'; -- generate a pulse on al_i, arb lost interrupt
end if;
elsif Rsta = '1' then
-- repeated start requested while slave
al_i <= '1';
else
al_i <= '0';
end if;
end if;
end process AL_I_BIT;
----------------------------------------------------------------------------
-- INT_ARB_LOST_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal al_i signal to the output port Al
----------------------------------------------------------------------------
INT_ARB_LOST_PROCESS : process (al_i)
begin -- process
Al <= al_i;
end process INT_ARB_LOST_PROCESS;
----------------------------------------------------------------------------
-- PREVENT_ARB_LOST_PROCESS
----------------------------------------------------------------------------
-- This process prevents arb lost (al_i) when a stop has been initiated by
-- this device operating as a master.
----------------------------------------------------------------------------
PREVENT_ARB_LOST_PROCESS : process (Sys_clk)
begin -- make an SR flip flop that sets on gen_stop and resets on
-- detect_start
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
al_prevent <= '0';
elsif (gen_stop = '1' and detect_start = '0')
or (sm_stop = '1' and detect_start = '0')then
al_prevent <= '1';
elsif detect_start = '1' then
al_prevent <= '0';
else
al_prevent <= al_prevent;
end if;
end if;
end process PREVENT_ARB_LOST_PROCESS;
----------------------------------------------------------------------------
-- srw_i - Slave Read/Write Bit
----------------------------------------------------------------------------
-- When aas_i is set, srw_i indicates the value of the R/W command bit of
-- the calling address sent from the master. This bit is only valid when a
-- complete transfer has occurred and no other transfers have been
-- initiated. The CPU uses this bit to set the slave transmit/receive mode.
-- This bit is Reset by Reset
----------------------------------------------------------------------------
SRW_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
srw_i <= '0';
elsif state = ACK_HEADER then
srw_i <= i2c_header(0);
else
srw_i <= srw_i;
end if;
end if;
end process SRW_I_BIT;
Srw <= srw_i;
----------------------------------------------------------------------------
-- TXER_BIT process
----------------------------------------------------------------------------
-- This process determines the state of the acknowledge bit which may be
-- used as a transmit error or by a master receiver to indicate to the
-- slave that the last byte has been transmitted
----------------------------------------------------------------------------
TXER_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
txer_i <= '0';
elsif scl_falling_edge = '1' then
if state = ACK_HEADER or state = ACK_DATA or state = WAIT_ACK then
txer_i <= sda_sample;
end if;
end if;
end if;
end process TXER_BIT;
----------------------------------------------------------------------------
-- TXER_EDGE process
----------------------------------------------------------------------------
-- This process creates a one wide clock pulse for Txer IRQ
----------------------------------------------------------------------------
TXER_EDGE_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
txer_edge <= '0';
elsif scl_falling_edge = '1' then
if state = ACK_HEADER or state = ACK_DATA or state = WAIT_ACK then
txer_edge <= sda_sample;
end if;
elsif scl_f_edg_d2 = '1' then
txer_edge <= '0';
end if;
end if;
end process TXER_EDGE_PROCESS;
Txer <= txer_edge;
----------------------------------------------------------------------------
-- uP Data Register
-- Register for uP interface data_i2c_i
----------------------------------------------------------------------------
DATA_I2C_I_PROC : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
data_i2c_i <= (others => '0');
new_rcv_dta_i <= '0';
elsif (state = ACK_DATA) and Ro_prev = '0' and scl_falling_edge = '1'
and adr_dta_l = '0' then
data_i2c_i <= shift_reg;
new_rcv_dta_i <= '1';
else
data_i2c_i <= data_i2c_i;
new_rcv_dta_i <= '0';
end if;
end if;
end process DATA_I2C_I_PROC;
----------------------------------------------------------------------------
-- INT_NEW_RCV_DATA_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal receive data signals to the output port
----------------------------------------------------------------------------
INT_NEW_RCV_DATA_PROCESS : process (new_rcv_dta_i)
begin -- process
New_rcv_dta <= new_rcv_dta_i;
end process INT_NEW_RCV_DATA_PROCESS;
Data_i2c <= data_i2c_i;
----------------------------------------------------------------------------
-- Determine if Addressed As Slave or by General Call
----------------------------------------------------------------------------
-- This process determines when the I2C has been addressed as a slave
-- that is the I2C header matches the slave address stored in ADR or a
-- general call has happened
----------------------------------------------------------------------------
NO_TEN_BIT_GEN : if C_TEN_BIT_ADR = 0 generate
addr_match <= '1' when (i2c_header(7 downto 1) = Adr(7 downto 1))
or (abgc_i = '1')
else '0';
-- Seven bit addressing, sec_adr_match is always true.
sec_adr_match <= '1';
end generate NO_TEN_BIT_GEN;
TEN_BIT_GEN : if (C_TEN_BIT_ADR = 1) generate
-------------------------------------------------------------------------
-- The msb_wr signal indicates that the just received i2c_header matches
-- the required first byte of a 2-byte, 10-bit address. Since the
-- i2c_header shift register clocks on the scl rising edge but the timing
-- of signals dependent on msb_wr expect it to change on the falling edge
-- the scl_f_edge_d1 qualifier is used to create the expected timing.
-------------------------------------------------------------------------
MSB_WR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msb_wr <= '0';
elsif (abgc_i = '1') or
(scl_f_edg_d1 = '1'
and i2c_header(7 downto 3) = "11110"
and (i2c_header(2 downto 1) = Ten_adr(7 downto 6)))
then
msb_wr <= '1';
elsif (scl_f_edg_d1='1') then
msb_wr <= '0';
end if;
end if;
end process MSB_WR_PROCESS;
-------------------------------------------------------------------------
-- MSB_WR_D_PROCESS
-------------------------------------------------------------------------
-- msb_wr delay process
-------------------------------------------------------------------------
MSB_WR_D_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msb_wr_d <= '0';
msb_wr_d1 <= '0';
else
msb_wr_d <= msb_wr;
msb_wr_d1 <= msb_wr_d; -- delayed to align with srw_i
end if;
end if;
end process MSB_WR_D_PROCESS;
-------------------------------------------------------------------------
-- SRFF set on leading edge of MSB_WR, Reset on DTC and SCL falling edge
-- this will qualify the 2nd byte as address and prevent it from being
-- loaded into the DRR or Rc FIFO
-------------------------------------------------------------------------
SECOND_ADDR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
sec_addr <= '0';
elsif (msb_wr = '1' and msb_wr_d = '0'
and i2c_header(0) = '0') then
-- First byte of two byte (10-bit addr) matched and
-- direction=write. Set sec_addr flag to indicate next byte
-- should be checked against remainder of the address.
sec_addr <= '1';
elsif dtc_i = '1' and Ro_prev = '0' and scl_f_edg_d1 = '1'
then
sec_addr <= '0';
else
sec_addr <= sec_addr;
end if;
end if;
end process SECOND_ADDR_PROCESS;
-------------------------------------------------------------------------
-- Compare 2nd byte to see if it matches slave address
-- A repeated start with the Master writing to the slave must also
-- compare the second address byte.
-- A repeated start with the Master reading from the slave only compares
-- the first (most significant).
-------------------------------------------------------------------------
SECOND_ADDR_COMP_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
sec_adr_match <= '0';
elsif detect_stop = '1'
-- Repeated Start and Master Writing to Slave
or (state = ACK_HEADER and i2c_header(0) = '0'
and master_slave = '0' and msb_wr_d = '1' and abgc_i = '0') then
sec_adr_match <= '0';
elsif (abgc_i = '1')
or (sec_addr = '1' and (shift_reg(7) = Ten_adr(5)
and shift_reg(6 downto 0) = Adr (7 downto 1)
and dtc_i = '1' and msb_wr_d1 = '1')) then
sec_adr_match <= '1';
else
sec_adr_match <= sec_adr_match;
end if;
end if;
end process SECOND_ADDR_COMP_PROCESS;
-------------------------------------------------------------------------
-- Prevents 2nd byte of 10 bit address from being loaded into DRR.
-- When in ACK_HEADER and srw_i is lo then a repeated start or start
-- condition occured and data is being written to slave so the next
-- byte will be the remaining portion of the 10 bit address
-------------------------------------------------------------------------
ADR_DTA_L_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
adr_dta_l <= '0';
elsif ((i2c_header(0) = '0' and
msb_wr = '1' and
msb_wr_d = '0') and
sec_adr_match = '0') or
(state = ACK_HEADER and srw_i = '0' and
master_slave = '0' and
msb_wr_d1 = '1') then
adr_dta_l <= '1';
elsif (state = ACK_HEADER and
master_slave = '1' and
msb_wr_d1 = '0') then
adr_dta_l <= '0';
elsif (state = ACK_DATA and Ro_prev = '0'
and scl_falling_edge = '1')
or (detect_start = '1') or (abgc_i = '1')
-- or (state = ACK_HEADER and srw_i = '1' and master_slave = '0')
then
adr_dta_l <= '0';
else
adr_dta_l <= adr_dta_l;
end if;
end if;
end process ADR_DTA_L_PROCESS;
-- Set address match high to get 2nd byte of slave address
addr_match <= '1' when (msb_wr = '1' and sec_adr_match = '1')
or (sec_addr = '1')
else '0';
end generate TEN_BIT_GEN;
----------------------------------------------------------------------------
-- Process : SDA_SMPL
-- Address by general call process
----------------------------------------------------------------------------
ABGC_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
abgc_i <= '0';
elsif detect_stop = '1' or detect_start = '1' then
abgc_i <= '0';
elsif i2c_header(7 downto 0) = "00000000" and Gc_en = '1'
and (state = ACK_HEADER) then
abgc_i <= '1';
end if;
end if;
end process ABGC_PROCESS;
Abgc <= abgc_i;
----------------------------------------------------------------------------
-- Process : SDA_SMPL
-- Sample the SDA_RIN for use in checking the acknowledge bit received by
-- the controller
----------------------------------------------------------------------------
SDA_SMPL: process (Sys_clk) is
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
sda_sample <= '0';
elsif (scl_rising_edge='1') then
sda_sample <= sda_rin;
end if;
end if;
end process SDA_SMPL;
----------------------------------------------------------------------------
-- Main State Machine Process
-- The following process contains the main I2C state machine for both master
-- and slave modes. This state machine is clocked on the falling edge of SCL
-- DETECT_STOP must stay as an asynchronous Reset because once STOP has been
-- generated, SCL clock stops. Note that the bit_cnt signal updates on the
-- scl_falling_edge pulse and is available on scl_f_edg_d1. So the count is
-- available prior to the STATE changing.
----------------------------------------------------------------------------
STATE_MACHINE : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or detect_stop = '1' then
state <= IDLE;
sm_stop <= '0';
elsif scl_f_edg_d2 = '1' or (Ro_prev = '0' and ro_prev_d1 = '1') then
case state is
------------- IDLE STATE -------------
when IDLE =>
--sm_stop <= sm_stop ;
if detect_start = '1' then
state <= HEADER;
end if;
------------- HEADER STATE -------------
when HEADER =>
--sm_stop <= sm_stop ;
if bit_cnt = CNT_DONE then
state <= ACK_HEADER;
end if;
------------- ACK_HEADER STATE -------------
when ACK_HEADER =>
-- sm_stop <= sm_stop ;
if arb_lost = '1' then
state <= IDLE;
elsif sda_sample = '0' then
-- ack has been received, check for master/slave
if master_slave = '1' then
-- master, so check tx bit for direction
if Tx = '0' then
-- receive mode
state <= RCV_DATA;
else
--transmit mode
state <= XMIT_DATA;
end if;
else
if addr_match = '1' then
--if aas_i = '1' then
-- addressed slave, so check I2C_HEADER(0)
-- for direction
if i2c_header(0) = '0' then
-- receive mode
state <= RCV_DATA;
else
-- transmit mode
state <= XMIT_DATA;
end if;
else
-- not addressed, go back to IDLE
state <= IDLE;
end if;
end if;
else
-- not acknowledge received, stop as the address put on
-- the bus was not recognized/accepted by any slave
state <= IDLE;
if master_slave = '1' then
sm_stop <= '1';
end if;
end if;
------------- RCV_DATA State --------------
when RCV_DATA =>
--sm_stop <= sm_stop ;
-- check for repeated start
if (detect_start = '1') then
state <= HEADER;
elsif bit_cnt = CNT_DONE then
if master_slave = '0' and addr_match = '0' then
state <= IDLE;
else
-- Send an acknowledge
state <= ACK_DATA;
end if;
end if;
------------ XMIT_DATA State --------------
when XMIT_DATA =>
--sm_stop <= sm_stop ;
-- check for repeated start
if (detect_start = '1') then
state <= HEADER;
elsif bit_cnt = CNT_DONE then
-- Wait for acknowledge
state <= WAIT_ACK;
end if;
------------- ACK_DATA State --------------
when ACK_DATA =>
--sm_stop <= sm_stop ;
if Ro_prev = '0' then -- stay in ACK_DATA until
state <= RCV_DATA; -- a read of DRR has occurred
else
state <= ACK_DATA;
end if;
------------- WAIT_ACK State --------------
when WAIT_ACK =>
if arb_lost = '1' then
state <= IDLE;
elsif (sda_sample = '0') then
if (master_slave = '0' and addr_match = '0') then
state <= IDLE;
else
state <= XMIT_DATA;
end if;
else
-- not acknowledge received. The master transmitter is
-- being told to quit sending data as the slave won't take
-- anymore. Generate a STOP per spec. (Note that it
-- isn't strickly necessary for the master to get off the
-- bus at this point. It could retain ownership. However,
-- product specification indicates that it will get off
-- the bus) The slave transmitter is being informed by the
-- master that it won't take any more data.
if master_slave = '1' then
sm_stop <= '1';
end if;
state <= IDLE;
end if;
-- coverage off
when others =>
state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process STATE_MACHINE;
LEVEL_1_GEN: if C_SDA_LEVEL = 1 generate
begin
----------------------------------------------------------------------------
-- Master SDA
----------------------------------------------------------------------------
MAS_SDA : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_sda <= '1';
-- elsif state = HEADER or state = XMIT_DATA then
-- master_sda <= shift_out;
elsif state = HEADER or (state = XMIT_DATA and
tx_under_prev_i = '0' ) then
master_sda <= shift_out;
---------------------------------
-- Updated for CR 555648
---------------------------------
elsif (tx_under_prev_i = '1' and state = XMIT_DATA) then
master_sda <= '1';
elsif state = ACK_DATA then
master_sda <= Txak;
else
master_sda <= '1';
end if;
end if;
end process MAS_SDA;
end generate LEVEL_1_GEN;
LEVEL_0_GEN: if C_SDA_LEVEL = 0 generate
begin
----------------------------------------------------------------------------
-- Master SDA
----------------------------------------------------------------------------
MAS_SDA : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_sda <= '1';
-- elsif state = HEADER or state = XMIT_DATA then
-- master_sda <= shift_out;
elsif state = HEADER or (state = XMIT_DATA and
tx_under_prev_i = '0' ) then
master_sda <= shift_out;
---------------------------------
-- Updated for CR 555648
---------------------------------
elsif (tx_under_prev_i = '1' and state = XMIT_DATA) then
master_sda <= '0';
elsif state = ACK_DATA then
master_sda <= Txak;
else
master_sda <= '1';
end if;
end if;
end process MAS_SDA;
end generate LEVEL_0_GEN;
----------------------------------------------------------------------------
-- Slave SDA
----------------------------------------------------------------------------
SLV_SDA : process(Sys_clk)
begin
-- For the slave SDA, address match(aas_i) only has to be checked when
-- state is ACK_HEADER because state
-- machine will never get to state XMIT_DATA or ACK_DATA
-- unless address match is a one.
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
slave_sda <= '1';
elsif (addr_match = '1' and state = ACK_HEADER) or
(state = ACK_DATA) then
slave_sda <= Txak;
elsif (state = XMIT_DATA) then
slave_sda <= shift_out;
else
slave_sda <= '1';
end if;
end if;
end process SLV_SDA;
------------------------------------------------------------
--Mathew : Added below process for CR 707697
SHIFT_COUNT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_cnt <= "000000000";
elsif(shift_reg_ld = '1') then
shift_cnt <= "000000001";
elsif(shift_reg_en = '1') then
shift_cnt <= shift_cnt(7 downto 0) & shift_cnt(8);
else
shift_cnt <= shift_cnt;
end if;
end if;
end process SHIFT_COUNT ;
reg_empty <= '1' when shift_cnt(8) = '1' else '0';
------------------------------------------------------------
----------------------------------------------------------------------------
-- I2C Data Shift Register
----------------------------------------------------------------------------
I2CDATA_REG : entity axi_iic_v2_0_14.shift8
port map (
Clk => Sys_clk,
Clr => Reset,
Data_ld => shift_reg_ld,
Data_in => Dtr,
Shift_in => sda_rin,
Shift_en => shift_reg_en,
Shift_out => shift_out,
Data_out => shift_reg);
----------------------------------------------------------------------------
-- Process : I2CDATA_REG_EN_CTRL
----------------------------------------------------------------------------
I2CDATA_REG_EN_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_en <= '0';
elsif (
-- Grab second byte of 10-bit address?
(master_slave = '1' and state = HEADER and scl_rising_edge='1')
-- Grab data byte
or (state = RCV_DATA and scl_rising_edge='1'
and detect_start = '0')
-- Send data byte. Note use of scl_f_edg_d2 which is the 2 clock
-- delayed version of the SCL falling edge signal
or (state = XMIT_DATA and scl_f_edg_d2 = '1'
and detect_start = '0')) then
shift_reg_en <= '1';
else
shift_reg_en <= '0';
end if;
end if;
end process I2CDATA_REG_EN_CTRL;
----------------------------------------------------------------------------
-- Process : I2CDATA_REG_LD_CTRL
----------------------------------------------------------------------------
I2CDATA_REG_LD_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_ld <= '0';
elsif (
(master_slave = '1' and state = IDLE)
or (state = WAIT_ACK)
-- Slave Transmitter (i2c_header(0)='1' mean master wants to read)
or (state = ACK_HEADER and i2c_header(0) = '1'
and master_slave = '0')
-- Master has a byte to transmit
or (state = ACK_HEADER and Tx = '1' and master_slave = '1')
-- ??
or (state = RCV_DATA and detect_start = '1'))
or tx_under_prev_i = '1' then
shift_reg_ld <= '1';
else
shift_reg_ld <= '0';
end if;
end if;
end process I2CDATA_REG_LD_CTRL;
----------------------------------------------------------------------------
-- SHFT_REG_LD_PROCESS
----------------------------------------------------------------------------
-- This process registers shift_reg_ld signal
----------------------------------------------------------------------------
SHFT_REG_LD_PROCESS : process (Sys_clk)
begin -- process
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_ld_d1 <= '0';
else -- Delay shift_reg_ld one clock
shift_reg_ld_d1 <= shift_reg_ld;
end if;
end if;
end process SHFT_REG_LD_PROCESS;
----------------------------------------------------------------------------
-- NEW_XMT_PROCESS
----------------------------------------------------------------------------
-- This process sets Rdy_new_xmt signal high for one sysclk after data has
-- been loaded into the shift register. This is used to create the Dtre
-- interrupt.
----------------------------------------------------------------------------
NEW_XMT_PROCESS : process (Sys_clk)
begin -- process
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
rdy_new_xmt_i <= '0';
elsif state = XMIT_DATA or (state = HEADER and Msms = '1') then
rdy_new_xmt_i <= (not (shift_reg_ld)) and shift_reg_ld_d1;
end if;
end if;
end process NEW_XMT_PROCESS;
Rdy_new_xmt <= rdy_new_xmt_i;
----------------------------------------------------------------------------
-- I2C Header Shift Register
-- Header/Address Shift Register
----------------------------------------------------------------------------
I2CHEADER_REG : entity axi_iic_v2_0_14.shift8
port map (
Clk => Sys_clk,
Clr => Reset,
Data_ld => i2c_header_ld,
Data_in => reg_clr,
Shift_in => sda_rin,
Shift_en => i2c_header_en,
Shift_out => i2c_shiftout,
Data_out => i2c_header);
----------------------------------------------------------------------------
-- Process : I2CHEADER_REG_CTRL
----------------------------------------------------------------------------
I2CHEADER_REG_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
i2c_header_en <= '0';
elsif (state = HEADER and scl_rising_edge='1') then
i2c_header_en <= '1';
else
i2c_header_en <= '0';
end if;
end if;
end process I2CHEADER_REG_CTRL;
i2c_header_ld <= '0';
----------------------------------------------------------------------------
-- Bit Counter
----------------------------------------------------------------------------
BITCNT : entity axi_iic_v2_0_14.upcnt_n
generic map (
C_SIZE => 4
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_start,
Cnt_en => bit_cnt_en,
Load => bit_cnt_ld,
Qout => bit_cnt);
----------------------------------------------------------------------------
-- Process : Counter control lines
----------------------------------------------------------------------------
BIT_CNT_EN_CNTL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bit_cnt_en <= '0';
elsif (state = HEADER and scl_falling_edge = '1')
or (state = RCV_DATA and scl_falling_edge = '1')
or (state = XMIT_DATA and scl_falling_edge = '1') then
bit_cnt_en <= '1';
else
bit_cnt_en <= '0';
end if;
end if;
end process BIT_CNT_EN_CNTL;
bit_cnt_ld <= '1' when (state = IDLE) or (state = ACK_HEADER)
or (state = ACK_DATA)
or (state = WAIT_ACK)
or (detect_start = '1') else '0';
end architecture RTL;
-------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: filter.vhd
-- Version: v1.01.b
-- Description:
-- This file implements a simple debounce (inertial delay)
-- filter to remove short glitches from the SCL and SDA signals
-- using user definable delay parameters. SCL cross couples to
-- SDA to prevent SDA from changing near changes in SDA.
-- Notes:
-- 1) The default value for both debounce instances is '1' to conform to the
-- IIC bus default value of '1' ('H').
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.debounce;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- SCL_INERTIAL_DELAY -- SCL filtering delay
-- SDA_INERTIAL_DELAY -- SDA filtering delay
-- Definition of Ports:
-- Sysclk -- System clock
-- Scl_noisy -- IIC SCL is noisy
-- Scl_clean -- IIC SCL is clean
-- Sda_noisy -- IIC SDA is Noisy
-- Sda_clean -- IIC SDA is clean
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity filter is
generic (
SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
SDA_INERTIAL_DELAY : integer range 0 to 255 := 5
);
port (
Sysclk : in std_logic;
Rst : in std_logic;
Scl_noisy : in std_logic;
Scl_clean : out std_logic;
Sda_noisy : in std_logic;
Sda_clean : out std_logic
);
end entity filter;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of filter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
signal scl_unstable_n : std_logic;
begin
----------------------------------------------------------------------------
-- The inertial delay is cross coupled between the two IIC signals to ensure
-- that a delay in SCL because of a glitch also prevents any changes in SDA
-- until SCL is clean. This prevents inertial delay on SCL from creating a
-- situation whereby SCL is held high but SDA transitions low to high thus
-- making the core think a STOP has occured. Changes on SDA do not inihibit
-- SCL because that could alter the timing relationships for the clock
-- edges. If other I2C devices follow the spec then SDA should be stable
-- prior to the rising edge of SCL anyway. (Excluding noise of course)
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Assertion that reports the SCL inertial delay
----------------------------------------------------------------------------
ASSERT (FALSE) REPORT "axi_iic configured for SCL inertial delay of "
& integer'image(SCL_INERTIAL_DELAY) & " clocks."
SEVERITY NOTE;
----------------------------------------------------------------------------
-- Instantiating component debounce
----------------------------------------------------------------------------
SCL_DEBOUNCE : entity axi_iic_v2_0_14.debounce
generic map (
C_INERTIAL_DELAY => SCL_INERTIAL_DELAY,
C_DEFAULT => '1')
port map (
Sysclk => Sysclk,
Rst => Rst,
Stable => '1',
Unstable_n => scl_unstable_n,
Noisy => Scl_noisy,
Clean => Scl_clean);
----------------------------------------------------------------------------
-- Assertion that reports the SDA inertial delay
----------------------------------------------------------------------------
ASSERT (FALSE) REPORT "axi_iic configured for SDA inertial delay of "
& integer'image(SDA_INERTIAL_DELAY) & " clocks."
SEVERITY NOTE;
----------------------------------------------------------------------------
-- Instantiating component debounce
----------------------------------------------------------------------------
SDA_DEBOUNCE : entity axi_iic_v2_0_14.debounce
generic map (
C_INERTIAL_DELAY => SDA_INERTIAL_DELAY,
C_DEFAULT => '1')
port map (
Sysclk => Sysclk,
Rst => Rst,
Stable => scl_unstable_n,
Unstable_n => open,
Noisy => Sda_noisy,
Clean => Sda_clean);
end architecture RTL;
-------------------------------------------------------------------------------
-- dynamic_master.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: dynamic_master.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the control logic for the dynamic master.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clk -- System clock
-- Rst -- System reset
-- Dynamic_MSMS -- Dynamic master slave mode select
-- Cr -- Control register
-- Tx_fifo_rd_i -- Transmit FIFO read
-- Tx_data_exists -- Trnasmit FIFO exists
-- AckDataState -- Data ack acknowledge signal
-- Tx_fifo_data -- Transmit FIFO read input
-- EarlyAckHdr -- Ack_header state strobe signal
-- EarlyAckDataState -- Data ack early acknowledge signal
-- Bb -- Bus busy indicator
-- Msms_rst_r -- MSMS reset indicator
-- DynMsmsSet -- Dynamic MSMS set signal
-- DynRstaSet -- Dynamic repeated start set signal
-- Msms_rst -- MSMS reset signal
-- TxFifoRd -- Transmit FIFO read output signal
-- Txak -- Transmit ack signal
-- Cr_txModeSelect_set -- Sets transmit mode select
-- Cr_txModeSelect_clr -- Clears transmit mode select
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity dynamic_master is
port(
Clk : in std_logic;
Rst : in std_logic;
Dynamic_MSMS : in std_logic_vector(0 to 1);
Cr : in std_logic_vector(0 to 7);
Tx_fifo_rd_i : in std_logic;
Tx_data_exists : in std_logic;
AckDataState : in std_logic;
Tx_fifo_data : in std_logic_vector(0 to 7);
EarlyAckHdr : in std_logic;
EarlyAckDataState : in std_logic;
Bb : in std_logic;
Msms_rst_r : in std_logic;
DynMsmsSet : out std_logic;
DynRstaSet : out std_logic;
Msms_rst : out std_logic;
TxFifoRd : out std_logic;
Txak : out std_logic;
Cr_txModeSelect_set : out std_logic;
Cr_txModeSelect_clr : out std_logic
);
end dynamic_master;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of dynamic_master is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal firstDynStartSeen : std_logic; -- used to detect re-start during
-- dynamic start generation
signal dynamic_MSMS_d : std_logic_vector(0 to 1);
signal rxCntDone : std_logic;
signal forceTxakHigh : std_logic;
signal earlyAckDataState_d1: std_logic;
signal ackDataState_d1 : std_logic;
signal rdByteCntr : unsigned(0 to 7);
signal rdCntrFrmTxFifo : std_logic;
signal callingReadAccess : std_logic;
signal dynamic_start : std_logic;
signal dynamic_stop : std_logic;
-------------------------------------------------------------------------------
begin
-- In the case where the tx fifo only contains a single byte (the address)
-- which contains both start and stop bits set the controller has to rely on
-- the tx fifo data exists flag to qualify the fifo output. Otherwise the
-- controller emits a continous stream of bytes. This fixes CR439857
dynamic_start <= Dynamic_MSMS(1) and Tx_data_exists;
dynamic_stop <= Dynamic_MSMS(0) and Tx_data_exists;
DynMsmsSet <= dynamic_start -- issue dynamic start by setting MSMS
and not(Cr(5)) -- when MSMS is not already set and
and not(Bb); -- bus isn't busy
DynRstaSet <= dynamic_start -- issue repeated start when
and Tx_fifo_rd_i
and firstDynStartSeen; -- MSMS is already set
Msms_rst <= (dynamic_stop and Tx_fifo_rd_i)
or Msms_rst_r
or rxCntDone;
TxFifoRd <= Tx_fifo_rd_i or rdCntrFrmTxFifo;
forceTxakHigh <= '1' when (EarlyAckDataState='1' and callingReadAccess='1'
and rdByteCntr = 0) else
'0';
Txak <= Cr(3) or forceTxakHigh;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MSMS_DLY_PROCESS
-- purpose: Dynamic Master MSMS registering
-----------------------------------------------------------------------------
DYN_MSMS_DLY_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
dynamic_MSMS_d <= (others => '0');
else
dynamic_MSMS_d <= Dynamic_MSMS;
end if;
end if;
end process DYN_MSMS_DLY_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_START_PROCESS
-- purpose: reset firstDynStartSeen if CR(5) MSMS is cleared
-----------------------------------------------------------------------------
DYN_START_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
firstDynStartSeen <= '0';
else
if(Cr(5) = '0') then
firstDynStartSeen <= '0';
elsif(firstDynStartSeen = '0' and Tx_fifo_rd_i = '1'
and dynamic_start = '1') then
firstDynStartSeen <= '1';
end if;
end if;
end if;
end process DYN_START_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_ACCESS_PROCESS
-- purpose: capture access direction initiated via dynamic Start
-----------------------------------------------------------------------------
DYN_RD_ACCESS_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
callingReadAccess <= '0';
else
if(Tx_fifo_rd_i = '1' and dynamic_start = '1') then
callingReadAccess <= Tx_fifo_data(7);
end if;
end if;
end if;
end process DYN_RD_ACCESS_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MODE_SELECT_SET_PROCESS
-- purpose: Set the tx Mode Select bit in the CR register at the begining of
-- each ack_header state
-----------------------------------------------------------------------------
DYN_MODE_SELECT_SET_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Cr_txModeSelect_set <= '0';
elsif(EarlyAckHdr='1' and firstDynStartSeen='1') then
Cr_txModeSelect_set <= not callingReadAccess;
else
Cr_txModeSelect_set <= '0';
end if;
end if;
end process DYN_MODE_SELECT_SET_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MODE_SELECT_CLR_PROCESS
-- purpose: Clear the tx Mode Select bit in the CR register at the begining of
-- each ack_header state
-----------------------------------------------------------------------------
DYN_MODE_SELECT_CLR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Cr_txModeSelect_clr <= '0';
elsif(EarlyAckHdr='1' and firstDynStartSeen='1') then
Cr_txModeSelect_clr <= callingReadAccess;
else
Cr_txModeSelect_clr <= '0';
end if;
end if;
end process DYN_MODE_SELECT_CLR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_CNTR_PROCESS
-- purpose: If this iic cycle is generating a read access, create a read
-- of the tx fifo to get the number of tx to process
-----------------------------------------------------------------------------
DYN_RD_CNTR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rdCntrFrmTxFifo <= '0';
else
if(EarlyAckHdr='1' and Tx_data_exists='1'
and callingReadAccess='1') then
rdCntrFrmTxFifo <= '1';
else
rdCntrFrmTxFifo <= '0';
end if;
end if;
end if;
end process DYN_RD_CNTR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_BYTE_CNTR_PROCESS
-- purpose: If this iic cycle is generating a read access, create a read
-- of the tx fifo to get the number of rx bytes to process
-----------------------------------------------------------------------------
DYN_RD_BYTE_CNTR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rdByteCntr <= (others => '0');
else
if(rdCntrFrmTxFifo='1') then
rdByteCntr <= unsigned(Tx_fifo_data);
elsif(EarlyAckDataState='1' and earlyAckDataState_d1='0'
and rdByteCntr /= 0) then
rdByteCntr <= rdByteCntr - 1;
end if;
end if;
end if;
end process DYN_RD_BYTE_CNTR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_BYTE_CNTR_PROCESS
-- purpose: Initialize read byte counter in order to control master
-- generation of ack to slave.
-----------------------------------------------------------------------------
DYN_EARLY_DATA_ACK_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
earlyAckDataState_d1 <= '0';
else
earlyAckDataState_d1 <= EarlyAckDataState;
end if;
end if;
end process DYN_EARLY_DATA_ACK_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_STATE_DATA_ACK_PROCESS
-- purpose: Register ackdatastate
-----------------------------------------------------------------------------
DYN_STATE_DATA_ACK_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
ackDataState_d1 <= '0';
else
ackDataState_d1 <= AckDataState;
end if;
end if;
end process DYN_STATE_DATA_ACK_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_STATE_DATA_ACK_PROCESS
-- purpose: Generation of receive count done to generate stop
-----------------------------------------------------------------------------
DYN_RX_CNT_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxCntDone <= '0';
else
if(AckDataState='1' and ackDataState_d1='0' and callingReadAccess='1'
and rdByteCntr = 0) then
rxCntDone <= '1';
else
rxCntDone <= '0';
end if;
end if;
end if;
end process DYN_RX_CNT_PROCESS;
end architecture RTL;
-------------------------------------------------------------------------------
-- axi_ipif_ssp1.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_ipif_ssp1.vhd
-- Version: v1.01.b
--
-- Description: AXI IPIF Slave Services Package 1
-- This block provides the following services:
-- - wraps the axi_lite_ipif interface to IPIC block and
-- sets up its address decoding.
-- - Provides the Software Reset register
-- - Provides interrupt servicing
-- - IPIC multiplexing service between the external IIC
-- register block IP2Bus data path and the internal
-- Interrupt controller's IP2Bus data path.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
-- NLR 01/07/11
-- ^^^^^^
-- - Updated the version to v1_01_b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;
library axi_iic_v2_0_14;
library axi_lite_ipif_v3_0_4;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library interrupt_control_v3_1_4;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_IIC_REGS -- Number of IIC registers
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- Target FPGA architecture
-------------------------------------------------------------------------------
-- Definition of Ports:
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IP interconnect port signals
-- Bus2IP_Clk -- Bus to IIC clock
-- Bus2IP_Reset -- Bus to IIC reset
-- Bus2IIC_Addr -- Bus to IIC address
-- Bus2IIC_Data -- Bus to IIC data bus
-- Bus2IIC_RNW -- Bus to IIC read not write
-- Bus2IIC_RdCE -- Bus to IIC read chip enable
-- Bus2IIC_WrCE -- Bus to IIC write chip enable
-- IIC2Bus_Data -- IIC to Bus data bus
-- IIC2Bus_IntrEvent -- IIC Interrupt events
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_ipif_ssp1 is
generic
(
C_NUM_IIC_REGS : integer := 10;
-- Number of IIC Registers
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7"
-- Select the target architecture type
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2Bus_IntrEvent : in std_logic_vector (0 to 7);
-- IIC Interrupt events
IIC2INTC_Irpt : out std_logic; -- IP-2-interrupt controller
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IP Interconnect (IPIC) port signals used by the IIC registers.
Bus2IIC_Clk : out std_logic;
Bus2IIC_Reset : out std_logic;
Bus2IIC_Addr : out std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
Bus2IIC_Data : out std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
Bus2IIC_RNW : out std_logic;
Bus2IIC_RdCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
Bus2IIC_WrCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
IIC2Bus_Data : in std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1)
);
end entity axi_ipif_ssp1;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_ipif_ssp1 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ZEROES : std_logic_vector(0 to 31) := X"00000000";
constant INTR_BASEADDR : std_logic_vector := X"00000000";
constant INTR_HIGHADDR : std_logic_vector
:= X"0000003F";
constant RST_BASEADDR : std_logic_vector
:= X"00000040";
constant RST_HIGHADDR : std_logic_vector
:= X"00000043";
constant IIC_REG_BASEADDR : std_logic_vector
:= X"00000100";
constant IIC_REG_HIGHADDR : std_logic_vector
:= X"000001FF";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZEROES & INTR_BASEADDR, -- Interrupt controller
ZEROES & INTR_HIGHADDR,
ZEROES & RST_BASEADDR, -- Software reset register
ZEROES & RST_HIGHADDR,
ZEROES & IIC_REG_BASEADDR, -- IIC registers
ZEROES & IIC_REG_HIGHADDR
);
constant C_ARD_IDX_INTERRUPT : integer := 0;
constant C_ARD_IDX_RESET : integer := 1;
constant C_ARD_IDX_IIC_REGS : integer := 2;
-- The C_IP_INTR_MODE_ARRAY must have the same width as the IP2Bus_IntrEvent
-- entity port.
constant C_IP_INTR_MODE_ARRAY : integer_array_type
:= (3, 3, 3, 3, 3, 3, 3, 3);
constant C_INCLUDE_DEV_PENCODER : boolean := FALSE;
constant C_INCLUDE_DEV_ISC : boolean := FALSE;
constant C_NUM_INTERRUPT_REGS : integer := 16;
constant C_NUM_RESET_REGS : integer := 1;
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
C_ARD_IDX_INTERRUPT => C_NUM_INTERRUPT_REGS,
C_ARD_IDX_RESET => C_NUM_RESET_REGS,
C_ARD_IDX_IIC_REGS => C_NUM_IIC_REGS
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"000001FF";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
SUBTYPE INTERRUPT_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)+C_ARD_NUM_CE_ARRAY(0)-1;
SUBTYPE RESET_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)+C_ARD_NUM_CE_ARRAY(1)-1;
SUBTYPE IIC_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)+C_ARD_NUM_CE_ARRAY(2)-1;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Signals
signal AXI_Bus2IP_Clk : std_logic;
signal AXI_Bus2IP_Resetn: std_logic;
signal AXI_Bus2IP_Reset : std_logic;
signal AXI_IP2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_IP2Bus_WrAck : std_logic;
signal AXI_IP2Bus_RdAck : std_logic;
signal AXI_IP2Bus_WrAck1 : std_logic;
signal AXI_IP2Bus_RdAck1 : std_logic;
signal AXI_IP2Bus_WrAck2 : std_logic;
signal AXI_IP2Bus_RdAck2 : std_logic;
signal Intr2Bus_WrAck : std_logic;
signal Intr2Bus_RdAck : std_logic;
signal AXI_IP2Bus_Error : std_logic;
signal AXI_Bus2IP_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal AXI_Bus2IP_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_Bus2IP_RNW : std_logic;
signal AXI_Bus2IP_CS : std_logic_vector(0 to
((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal AXI_Bus2IP_RdCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal AXI_Bus2IP_WrCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-- Derived IPIC signals for use with the reset register functionality
signal reset2Bus_Error : std_logic;
signal reset2IP_Reset : std_logic;
-- Derived IPIC signals for use with the interrupt controller
signal Intr2Bus_DevIntr : std_logic;
signal Intr2Bus_DBus : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
AXI_Bus2IP_Reset <= not AXI_Bus2IP_Resetn;
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
-- System signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
-- AXI Interface signals
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Resetn => AXI_Bus2IP_Resetn,
IP2Bus_Data => AXI_IP2Bus_Data,
IP2Bus_WrAck => AXI_IP2Bus_WrAck,
IP2Bus_RdAck => AXI_IP2Bus_RdAck,
IP2Bus_Error => AXI_IP2Bus_Error,
Bus2IP_Addr => AXI_Bus2IP_Addr,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_RNW => AXI_Bus2IP_RNW,
Bus2IP_BE => open,
Bus2IP_CS => AXI_Bus2IP_CS,
Bus2IP_RdCE => AXI_Bus2IP_RdCE,
Bus2IP_WrCE => AXI_Bus2IP_WrCE
);
-------------------------------------------------------------------------------
-- INTERRUPT DEVICE
-------------------------------------------------------------------------------
X_INTERRUPT_CONTROL : entity interrupt_control_v3_1_4.interrupt_control
generic map (
C_NUM_CE => C_NUM_INTERRUPT_REGS, -- [integer range 4 to 16]
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC => 1, -- [integer range 1 to 29]
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY, -- [INTEGER_ARRAY_TYPE]
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER => C_INCLUDE_DEV_PENCODER, -- [boolean]
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC => C_INCLUDE_DEV_ISC, -- [boolean]
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH -- [integer range 32 to 128]
)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Reset => reset2IP_Reset,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
Interrupt_RdCE => AXI_Bus2IP_RdCE(INTERRUPT_CE_RNG),
Interrupt_WrCE => AXI_Bus2IP_WrCE(INTERRUPT_CE_RNG),
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => "00",
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => "0",
-- Inputs from the IP Interface
IP2Bus_IntrEvent => IIC2Bus_IntrEvent,
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IIC2INTC_Irpt,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => Intr2Bus_DBus,
Intr2Bus_WrAck => open,
Intr2Bus_RdAck => open,
Intr2Bus_Error => open,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-------------------------------------------------------------------------------
-- SOFT RESET REGISTER
-------------------------------------------------------------------------------
X_SOFT_RESET : entity axi_iic_v2_0_14.soft_reset
generic map (
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH, -- [integer]
-- Width of the write data bus
C_RESET_WIDTH => 4)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Reset => AXI_Bus2IP_Reset,
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_WrCE => AXI_Bus2IP_WrCE(RESET_CE_RNG'LEFT),
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
-- Final Device Reset Output
reset2IP_Reset => reset2IP_Reset,
-- Status Reply Outputs to the Bus
reset2Bus_WrAck => open,
reset2Bus_Error => reset2Bus_Error,
Reset2Bus_ToutSup => open);
-------------------------------------------------------------------------------
-- IIC Register (External) Connections
-------------------------------------------------------------------------------
Bus2IIC_Clk <= AXI_Bus2IP_Clk;
Bus2IIC_Reset <= reset2IP_Reset;
Bus2IIC_Addr <= AXI_Bus2IP_Addr;
Bus2IIC_Data <= AXI_Bus2IP_Data;
Bus2IIC_RNW <= AXI_Bus2IP_RNW;
Bus2IIC_RdCE <= AXI_Bus2IP_RdCE(IIC_CE_RNG);
Bus2IIC_WrCE <= AXI_Bus2IP_WrCE(IIC_CE_RNG);
-------------------------------------------------------------------------------
-- Read Ack/Write Ack generation
-------------------------------------------------------------------------------
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_RdAck2 <= or_reduce(AXI_Bus2IP_CS) and AXI_Bus2IP_RNW;
AXI_IP2Bus_RdAck1 <= AXI_IP2Bus_RdAck2;
end if;
end process;
AXI_IP2Bus_RdAck <= (not (AXI_IP2Bus_RdAck1)) and AXI_IP2Bus_RdAck2;
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_WrAck2 <= (or_reduce(AXI_Bus2IP_CS) and not AXI_Bus2IP_RNW);
AXI_IP2Bus_WrAck1 <= AXI_IP2Bus_WrAck2;
end if;
end process;
AXI_IP2Bus_WrAck <= (not AXI_IP2Bus_WrAck1) and AXI_IP2Bus_WrAck2;
-------------------------------------------------------------------------------
-- Data and Error generation
-------------------------------------------------------------------------------
AXI_IP2Bus_Data <= Intr2Bus_DBus or IIC2Bus_Data;
AXI_IP2Bus_Error <= reset2Bus_Error;
end architecture RTL;
-------------------------------------------------------------------------------
-- iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the top level file for the iic Bus
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- - Fixed the CR#613282
-- ~~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_IIC_REGS -- Number of IIC Registers
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_TX_FIFO_EXIST -- IIC transmit FIFO exist
-- C_RC_FIFO_EXIST -- IIC receive FIFO exist
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IIC Signals
-- Sda_I -- IIC serial data input
-- Sda_O -- IIC serial data output
-- Sda_T -- IIC seral data output enable
-- Scl_I -- IIC serial clock input
-- Scl_O -- IIC serial clock output
-- Scl_T -- IIC serial clock output enable
-- Gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity iic is
generic (
-- System Generics
C_NUM_IIC_REGS : integer := 10;
--IIC Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 0;
C_SCL_INERTIAL_DELAY : integer := 0;
C_SDA_INERTIAL_DELAY : integer := 0;
C_SDA_LEVEL : integer := 1;
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_TX_FIFO_EXIST : boolean := TRUE;
C_RC_FIFO_EXIST : boolean := TRUE;
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7";
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IIC Bus Signals
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(0 to C_GPO_WIDTH-1)
);
end entity iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- Calls the function from the iic_pkg.vhd
constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
signal Msms_rst : std_logic;
signal Msms_set : std_logic;
signal Rsta_rst : std_logic;
signal Dtc : std_logic;
signal Rdy_new_xmt : std_logic;
signal New_rcv_dta : std_logic;
signal Ro_prev : std_logic;
signal Dtre : std_logic;
signal Bb : std_logic;
signal Aas : std_logic;
signal Al : std_logic;
signal Srw : std_logic;
signal Txer : std_logic;
signal Tx_under_prev : std_logic;
signal Abgc : std_logic;
signal Data_i2c : std_logic_vector(0 to 7);
signal Adr : std_logic_vector(0 to 7);
signal Ten_adr : std_logic_vector(5 to 7);
signal Cr : std_logic_vector(0 to 7);
signal Drr : std_logic_vector(0 to 7);
signal Dtr : std_logic_vector(0 to 7);
signal Tx_fifo_data : std_logic_vector(0 to 7);
signal Tx_data_exists : std_logic;
signal Tx_fifo_wr : std_logic;
signal Tx_fifo_wr_i : std_logic;
signal Tx_fifo_wr_d : std_logic;
signal Tx_fifo_rd : std_logic;
signal Tx_fifo_rd_i : std_logic;
signal Tx_fifo_rd_d : std_logic;
signal Tx_fifo_rst : std_logic;
signal Tx_fifo_full : std_logic;
signal Tx_addr : std_logic_vector(0 to TX_FIFO_BITS - 1);
signal Rc_fifo_data : std_logic_vector(0 to 7);
signal Rc_fifo_wr : std_logic;
signal Rc_fifo_wr_i : std_logic;
signal Rc_fifo_wr_d : std_logic;
signal Rc_fifo_rd : std_logic;
signal Rc_fifo_rd_i : std_logic;
signal Rc_fifo_rd_d : std_logic;
signal Rc_fifo_full : std_logic;
signal Rc_Data_Exists : std_logic;
signal Rc_addr : std_logic_vector(0 to RC_FIFO_BITS -1);
signal Bus2IIC_Clk : std_logic;
signal Bus2IIC_Reset : std_logic;
signal IIC2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1) :=
(others => '0');
signal IIC2Bus_IntrEvent : std_logic_vector(0 to 7) := (others => '0');
signal Bus2IIC_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal Bus2IIC_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal Bus2IIC_RNW : std_logic;
signal Bus2IIC_RdCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
signal Bus2IIC_WrCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
-- signals for dynamic start/stop
signal ctrlFifoDin : std_logic_vector(0 to 1);
signal dynamic_MSMS : std_logic_vector(0 to 1);
signal dynRstaSet : std_logic;
signal dynMsmsSet : std_logic;
signal txak : std_logic;
signal earlyAckDataState : std_logic;
signal ackDataState : std_logic;
signal earlyAckHdr : std_logic;
signal cr_txModeSelect_set : std_logic;
signal cr_txModeSelect_clr : std_logic;
signal txFifoRd : std_logic;
signal Msms_rst_r : std_logic;
signal ctrl_fifo_wr_i : std_logic;
-- Cleaned up inputs
signal scl_clean : std_logic;
signal sda_clean : std_logic;
-- Timing Parameters
signal Timing_param_tsusta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsusto : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thdsta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsudat : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tbuf : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thigh : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tlow : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thddat : std_logic_vector(C_SIZE-1 downto 0);
----------Mathew
-- signal transfer_done : std_logic;
signal reg_empty : std_logic;
----------Mathew
begin
----------------------------------------------------------------------------
-- axi_ipif_ssp1 instantiation
----------------------------------------------------------------------------
X_AXI_IPIF_SSP1 : entity axi_iic_v2_0_14.axi_ipif_ssp1
generic map (
C_NUM_IIC_REGS => C_NUM_IIC_REGS,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
-- Width of AXI Data Bus (in bits) Must be 32
C_FAMILY => C_FAMILY)
port map (
-- System signals ----------------------------------------------------
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent, -- IIC Interrupt events
IIC2INTC_Irpt => IIC2INTC_Irpt,
-- AXI Interface signals --------------
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals used by the IIC registers. ----
Bus2IIC_Clk => Bus2IIC_Clk,
Bus2IIC_Reset => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data,
Bus2IIC_RNW => Bus2IIC_RNW,
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data
);
----------------------------------------------------------------------------
-- reg_interface instantiation
----------------------------------------------------------------------------
REG_INTERFACE_I : entity axi_iic_v2_0_14.reg_interface
generic map (
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
C_TX_FIFO_EXIST => C_TX_FIFO_EXIST ,
C_TX_FIFO_BITS => 4 ,
C_RC_FIFO_EXIST => C_RC_FIFO_EXIST ,
C_RC_FIFO_BITS => 4 ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR ,
C_GPO_WIDTH => C_GPO_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SIZE => C_SIZE ,
C_NUM_IIC_REGS => C_NUM_IIC_REGS ,
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map (
Clk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data(0 to C_S_AXI_DATA_WIDTH - 1),
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data(0 to C_S_AXI_DATA_WIDTH - 1),
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent,
Gpo => Gpo(0 to C_GPO_WIDTH-1),
Cr => Cr,
Dtr => Dtr,
Drr => Drr,
Adr => Adr,
Ten_adr => Ten_adr,
Msms_set => Msms_set,
Msms_rst => Msms_rst,
DynMsmsSet => dynMsmsSet,
DynRstaSet => dynRstaSet,
Cr_txModeSelect_set => cr_txModeSelect_set,
Cr_txModeSelect_clr => cr_txModeSelect_clr,
Rsta_rst => Rsta_rst,
Rdy_new_xmt => Rdy_new_xmt,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Aas => Aas,
Bb => Bb,
Srw => Srw,
Al => Al,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Tx_fifo_data => Tx_fifo_data(0 to 7),
Tx_data_exists => Tx_data_exists,
Tx_fifo_wr => Tx_fifo_wr,
Tx_fifo_rd => Tx_fifo_rd,
Tx_fifo_full => Tx_fifo_full,
Tx_fifo_rst => Tx_fifo_rst,
Tx_addr => Tx_addr(0 to TX_FIFO_BITS - 1),
Rc_fifo_data => Rc_fifo_data(0 to 7),
Rc_fifo_wr => Rc_fifo_wr,
Rc_fifo_rd => Rc_fifo_rd,
Rc_fifo_full => Rc_fifo_full,
Rc_Data_Exists => Rc_Data_Exists,
Rc_addr => Rc_addr(0 to RC_FIFO_BITS - 1),
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- The V5 inputs are so fast that they typically create glitches longer then
-- the clock period due to the extremely slow rise/fall times on SDA/SCL
-- signals. The inertial delay filter removes these.
----------------------------------------------------------------------------
FILTER_I: entity axi_iic_v2_0_14.filter
generic map (
SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY -- [range 0 to 255]
)
port map
(
Sysclk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Scl_noisy => Scl_I,
Scl_clean => scl_clean,
Sda_noisy => Sda_I,
Sda_clean => sda_clean
);
----------------------------------------------------------------------------
-- iic_control instantiation
----------------------------------------------------------------------------
IIC_CONTROL_I : entity axi_iic_v2_0_14.iic_control
generic map
(
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SIZE => C_SIZE ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR,
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST
)
port map
(
Sys_clk => Bus2IIC_Clk,
Reset => Cr(7),
Sda_I => sda_clean,
Sda_O => Sda_O,
Sda_T => Sda_T,
Scl_I => scl_clean,
Scl_O => Scl_O,
Scl_T => Scl_T,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Txak => txak,
Msms => Cr(5),
Msms_set => Msms_set,
Msms_rst => Msms_rst_r,
Rsta => Cr(2),
Rsta_rst => Rsta_rst,
Tx => Cr(4),
Gc_en => Cr(1),
Dtr => Dtr,
Adr => Adr,
Ten_adr => Ten_adr,
Bb => Bb,
Dtc => Dtc,
Aas => Aas,
Al => Al,
Srw => Srw,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Rdy_new_xmt => Rdy_new_xmt,
EarlyAckHdr => earlyAckHdr,
EarlyAckDataState => earlyAckDataState,
AckDataState => ackDataState,
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- Transmitter FIFO instantiation
----------------------------------------------------------------------------
WRITE_FIFO_I : entity axi_iic_v2_0_14.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => Tx_fifo_wr_i,
Data_In => Bus2IIC_Data(24 to 31),
FIFO_Read => txFifoRd,
Data_Out => Tx_fifo_data(0 to 7),
FIFO_Full => Tx_fifo_full,
Data_Exists => Tx_data_exists,
Addr => Tx_addr(0 to TX_FIFO_BITS - 1)
);
-------Mathew
-- transfer_done <= '1' when Tx_data_exists = '0' and reg_empty ='1' else '0';
-------Mathew
----------------------------------------------------------------------------
-- Receiver FIFO instantiation
----------------------------------------------------------------------------
READ_FIFO_I : entity axi_iic_v2_0_14.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => RC_FIFO_BITS
)
port map (
Clk => Bus2IIC_Clk,
Reset => Bus2IIC_Reset,
FIFO_Write => Rc_fifo_wr_i,
Data_In => Data_i2c(0 to 7),
FIFO_Read => Rc_fifo_rd_i,
Data_Out => Rc_fifo_data(0 to 7),
FIFO_Full => Rc_fifo_full,
Data_Exists => Rc_Data_Exists,
Addr => Rc_addr(0 to RC_FIFO_BITS - 1)
);
----------------------------------------------------------------------------
-- PROCESS: TX_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
TX_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Tx_fifo_wr_d <= '0';
Tx_fifo_rd_d <= '0';
else
Tx_fifo_wr_d <= Tx_fifo_wr;
Tx_fifo_rd_d <= Tx_fifo_rd;
end if;
end if;
end process TX_FIFO_WR_GEN;
----------------------------------------------------------------------------
-- PROCESS: RC_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
RC_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Rc_fifo_wr_d <= '0';
Rc_fifo_rd_d <= '0';
else
Rc_fifo_wr_d <= Rc_fifo_wr;
Rc_fifo_rd_d <= Rc_fifo_rd;
end if;
end if;
end process RC_FIFO_WR_GEN;
Tx_fifo_wr_i <= Tx_fifo_wr and (not Tx_fifo_wr_d);
Rc_fifo_wr_i <= Rc_fifo_wr and (not Rc_fifo_wr_d);
Tx_fifo_rd_i <= Tx_fifo_rd and (not Tx_fifo_rd_d);
Rc_fifo_rd_i <= Rc_fifo_rd and (not Rc_fifo_rd_d);
----------------------------------------------------------------------------
-- Dynamic master interface
-- Dynamic master start/stop and control logic
----------------------------------------------------------------------------
DYN_MASTER_I : entity axi_iic_v2_0_14.dynamic_master
port map (
Clk => Bus2IIC_Clk ,
Rst => Tx_fifo_rst ,
dynamic_MSMS => dynamic_MSMS ,
Cr => Cr ,
Tx_fifo_rd_i => Tx_fifo_rd_i ,
Tx_data_exists => Tx_data_exists ,
ackDataState => ackDataState ,
Tx_fifo_data => Tx_fifo_data ,
earlyAckHdr => earlyAckHdr ,
earlyAckDataState => earlyAckDataState ,
Bb => Bb ,
Msms_rst_r => Msms_rst_r ,
dynMsmsSet => dynMsmsSet ,
dynRstaSet => dynRstaSet ,
Msms_rst => Msms_rst ,
txFifoRd => txFifoRd ,
txak => txak ,
cr_txModeSelect_set => cr_txModeSelect_set,
cr_txModeSelect_clr => cr_txModeSelect_clr
);
-- virtual reset. Since srl fifo address is rst at the same time, only the
-- first entry in the srl fifo needs to have a value of '00' to appear
-- reset. Also, force data to 0 if a byte write is done to the txFifo.
ctrlFifoDin <= Bus2IIC_Data(22 to 23) when (Tx_fifo_rst = '0' and
Bus2IIC_Reset = '0') else
"00";
-- continuously write srl fifo while reset active
ctrl_fifo_wr_i <= Tx_fifo_rst or Bus2IIC_Reset or Tx_fifo_wr_i;
----------------------------------------------------------------------------
-- Control FIFO instantiation
-- fifo used to set/reset MSMS bit in control register to create automatic
-- START/STOP conditions
----------------------------------------------------------------------------
WRITE_FIFO_CTRL_I : entity axi_iic_v2_0_14.srl_fifo
generic map (
C_DATA_BITS => 2,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => ctrl_fifo_wr_i,
Data_In => ctrlFifoDin,
FIFO_Read => txFifoRd,
Data_Out => dynamic_MSMS,
FIFO_Full => open,
Data_Exists => open,
Addr => open
);
end architecture RTL;
-------------------------------------------------------------------------------
-- axi_iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_iic.vhd
-- Version: v1.01.b
-- Description:
-- This file is the top level file that contains the IIC AXI
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- - Added function calc_tbuf in iic_control to calculate the TBUF delay
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Fixed the CR#613282 and CR#613486
-- - Release of v1.01.b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0_14;
use axi_iic_v2_0_14.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_SMBUS_PMBUS_HOST -- Acts as SMBus/PMBus host when enabled
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- IIC Signals
-- sda_i -- IIC serial data input
-- sda_o -- IIC serial data output
-- sda_t -- IIC seral data output enable
-- scl_i -- IIC serial clock input
-- scl_o -- IIC serial clock output
-- scl_t -- IIC serial clock output enable
-- gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_iic is
generic (
-- FPGA Family Type specification
C_FAMILY : string := "virtex7";
-- Select the target architecture type
-- AXI Parameters
--C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32; --9
C_S_AXI_ADDR_WIDTH : integer := 9; --9
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-- AXI IIC Feature generics
C_IIC_FREQ : integer := 100E3;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 1;
C_S_AXI_ACLK_FREQ_HZ : integer := 25E6;
C_SCL_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_LEVEL : integer := 1; -- delay in nanoseconds
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port (
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic := '1';
iic2intc_irpt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
--((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- IIC interface signals
sda_i : in std_logic;
sda_o : out std_logic;
sda_t : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
scl_t : out std_logic;
gpo : out std_logic_vector(C_GPO_WIDTH-1 downto 0)
);
end entity axi_iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant C_NUM_IIC_REGS : integer := 18;
begin
X_IIC: entity axi_iic_v2_0_14.iic
generic map (
-- System Generics
C_NUM_IIC_REGS => C_NUM_IIC_REGS, -- Number of IIC Registers
--iic Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ, -- default iic Serial 100KHz
C_TEN_BIT_ADR => C_TEN_BIT_ADR, -- [integer]
C_GPO_WIDTH => C_GPO_WIDTH, -- [integer]
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
-- Transmit FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_TX_FIFO_EXIST => TRUE, -- [boolean]
-- Recieve FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_RC_FIFO_EXIST => TRUE, -- [boolean]
-- AXI interface generics
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, -- [integer 9]
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, -- [integer range 32 to 32]
-- Width of the AXI Data Bus (in bits)
C_FAMILY => C_FAMILY, -- [string]
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map
(
-- System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
IIC2INTC_IRPT => iic2intc_iRPT,
-- AXI Interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IIC Bus Signals
SDA_I => sda_i,
SDA_O => sda_o,
SDA_T => sda_t,
SCL_I => scl_i,
SCL_O => scl_o,
SCL_T => scl_t,
GPO => gpo
);
end architecture RTL;
|
apache-2.0
|
09ef9ed41ac5aa94c13422ba4a7d29f5
| 0.436543 | 4.4813 | false | false | false | false |
daniw/add
|
floppy/mcu/cpu_alu.vhd
| 2 | 6,822 |
-------------------------------------------------------------------------------
-- Entity: cpu_alu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- ALU for the RISC-CPU of the von-Neuman MCU.
-- The ALU is purely combinational, and thus no .enb signal in the alu_in
-- is required.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_alu is
port(clk : in std_logic;
-- CPU internal interfaces
alu_in : in t_ctr2alu;
alu_out : out t_alu2ctr;
oper1 : in std_logic_vector(DW-1 downto 0);
oper2 : in std_logic_vector(DW-1 downto 0);
result : out std_logic_vector(DW-1 downto 0)
);
end cpu_alu;
architecture rtl of cpu_alu is
signal result_int : std_logic_vector(DW-1 downto 0);
signal imml : std_logic_vector(DW-1 downto 0);
signal immh : std_logic_vector(DW-1 downto 0);
constant ext_0 : std_logic_vector(IOWW-1 downto 0) := (others => '0');
constant ext_1 : std_logic_vector(IOWW-1 downto 0) := (others => '1');
begin
-- output assignment
result <= result_int;
-- helper signals for addil/addih instructions with sign extension
imml <= (ext_0 & alu_in.imm) when alu_in.imm(alu_in.imm'left) = '0' else
(ext_1 & alu_in.imm);
immh <= alu_in.imm & ext_0;
-----------------------------------------------------------------------------
-- ISE workaround (:-((
-----------------------------------------------------------------------------
g_ISE: if ISE_TOOL generate
with to_integer(unsigned(alu_in.op)) select result_int <=
-- Opcode 0: add
std_logic_vector(unsigned(oper1) + unsigned(oper2)) when 0,
-- Opcode 1: sub
std_logic_vector(unsigned(oper1) - unsigned(oper2)) when 1,
-- Opcode 2: and
oper1 and oper2 when 2,
-- Opcode 3: or
oper1 or oper2 when 3,
-- Opcode 4: xor
oper1 xor oper2 when 4,
-- Opcode 5: slai
oper1(DW-2 downto 0) & '0' when 5,
-- Opcode 6: srai
oper1(DW-1) & oper1(DW-1 downto 1) when 6,
-- Opcode 7: mov
oper1 when 7,
-- Opcode 12: addil
std_logic_vector(unsigned(oper1) + unsigned(imml)) when 12,
-- Opcode 13: addih
std_logic_vector(unsigned(oper1) + unsigned(immh)) when 13,
-- other (ensures memory-less process)
(others => '0') when others;
end generate g_ISE;
-----------------------------------------------------------------------------
-- More elegant solution using type attribute 'val. Unfortunately, this
-- attribute is not supported by ISE XST, but works fine with Vivado.
-- (also note that the complementary attribute to 'val is 'pos)
-----------------------------------------------------------------------------
g_NOT_ISE: if not ISE_TOOL generate
with t_alu_instr'val(to_integer(unsigned(alu_in.op))) select result_int <=
std_logic_vector(unsigned(oper1) + unsigned(oper2)) when add,
std_logic_vector(unsigned(oper1) - unsigned(oper2)) when sub,
oper1 and oper2 when andi,
oper1 or oper2 when ori,
oper1 xor oper2 when xori,
oper1(DW-2 downto 0) & '0' when slai,
oper1(DW-1) & oper1(DW-1 downto 1) when srai,
oper1 when mov,
std_logic_vector(unsigned(oper1) + unsigned(imml)) when addil,
std_logic_vector(unsigned(oper1) + unsigned(immh)) when addih,
(others =>'0') when others;
end generate g_NOT_ISE;
-----------------------------------------------------------------------------
-- Update and register flags N, Z, C, O with valid ALU results
-----------------------------------------------------------------------------
P_flag: process(clk)
variable v_op2 : std_logic_vector(DW-1 downto 0);
begin
if rising_edge(clk) then
if alu_in.enb = '1' then
-- get correct Operand 2 for add/addil/addih
if (to_integer(unsigned(alu_in.op)) = 0) then
v_op2 := oper2; --add
elsif (to_integer(unsigned(alu_in.op)) = 12) then
v_op2 := imml; --addil
else
v_op2 := immh; --addih
end if;
-- N, updated with each operation -------------------------------------
alu_out.flag(N) <= result_int(DW-1);
-- Z, updated with each operation -------------------------------------
alu_out.flag(Z) <= '0';
if to_integer(unsigned(result_int)) = 0 then
alu_out.flag(Z) <= '1';
end if;
-- C, updated with add/addil/addih/sub only ---------------------------
if (to_integer(unsigned(alu_in.op)) = 0) or
(to_integer(unsigned(alu_in.op)) = 12) or
(to_integer(unsigned(alu_in.op)) = 13) then
-- add/addil/addih (use v_op2)
alu_out.flag(C) <= (oper1(DW-1) and v_op2(DW-1)) or
(oper1(DW-1) and not result_int(DW-1)) or
(v_op2(DW-1) and not result_int(DW-1));
elsif to_integer(unsigned(alu_in.op)) = 1 then
-- sub (use oper2)
alu_out.flag(C) <= (oper2(DW-1) and not oper1(DW-1)) or
(result_int(DW-1) and not oper1(DW-1)) or
(oper2(DW-1) and result_int(DW-1));
end if;
-- O, updated with add/addil/addih/sub only ---------------------------
if (to_integer(unsigned(alu_in.op)) = 0) or
(to_integer(unsigned(alu_in.op)) = 12) or
(to_integer(unsigned(alu_in.op)) = 13) then
-- add/addil/addih (use v_op2)
alu_out.flag(O) <= (not oper1(DW-1) and not v_op2(DW-1) and result_int(DW-1)) or
( oper1(DW-1) and v_op2(DW-1) and not result_int(DW-1));
elsif to_integer(unsigned(alu_in.op)) = 1 then
-- sub (use oper2)
alu_out.flag(O) <= ( oper1(DW-1) and not oper2(DW-1) and not result_int(DW-1)) or
(not oper1(DW-1) and oper2(DW-1) and result_int(DW-1));
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
3926fa79218df6d915479393c2b0859e
| 0.451774 | 3.884966 | false | false | false | false |
daniw/add
|
rot_enc/cpu_reg.vhd
| 3 | 2,773 |
-------------------------------------------------------------------------------
-- Entity: cpu_reg
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Register block for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 8 x 16
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_reg is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
reg_in : in t_ctr2reg;
reg_out : out t_reg2ctr;
alu_res : in std_logic_vector(DW-1 downto 0);
alu_op1 : out std_logic_vector(DW-1 downto 0);
alu_op2 : out std_logic_vector(DW-1 downto 0)
);
end cpu_reg;
architecture rtl of cpu_reg is
signal reg_blk : t_regblk;
begin
-----------------------------------------------------------------------------
-- Mux and register data/address to Control Unit depending on source info.
-----------------------------------------------------------------------------
P_mux: process(clk)
begin
if rising_edge(clk) then
reg_out.data <= reg_blk(to_integer(unsigned(reg_in.dest)));
reg_out.addr <= reg_blk(to_integer(unsigned(reg_in.src1)))(AW-1 downto 0);
end if;
end process;
-----------------------------------------------------------------------------
-- Mux input data to ALU combinationally depending on source info from
-- control unit.
-----------------------------------------------------------------------------
alu_op1 <= reg_blk(to_integer(unsigned(reg_in.src1)));
alu_op2 <= reg_blk(to_integer(unsigned(reg_in.src2)));
-----------------------------------------------------------------------------
-- CPU register block
-- Store ALU result or data from control unit depending on different enable
-- signals and destination info given from the control unit.
-- Note: Some CPU registers have non-zero reset values to allow simulation
-- of register-to-register instructions without load-instructions.
-----------------------------------------------------------------------------
P_reg: process(rst, clk)
begin
if rst = '1' then
reg_blk <= (others => (others => '0'));
elsif rising_edge(clk) then
if reg_in.enb_res = '1' then
-- store result from ALU
reg_blk(to_integer(unsigned(reg_in.dest))) <= alu_res;
elsif reg_in.enb_data = '1' then
-- store data from Ctrl (ld instruction)
reg_blk(to_integer(unsigned(reg_in.dest))) <= reg_in.data;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
338c9c90372bad2aa96df13325a988bf
| 0.456545 | 4.472581 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_axi_intc_0/system_microblaze_0_axi_intc_0_sim_netlist.vhdl
| 1 | 215,050 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:06 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_axi_intc_0/system_microblaze_0_axi_intc_0_sim_netlist.vhdl
-- Design : system_microblaze_0_axi_intc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_address_decoder is
port (
p_17_in : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ : out STD_LOGIC;
ip2bus_wrack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic : out STD_LOGIC;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ : out STD_LOGIC;
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ : out STD_LOGIC;
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ : out STD_LOGIC;
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ : out STD_LOGIC;
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ : out STD_LOGIC;
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ : out STD_LOGIC;
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
ip2bus_rdack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic19_out : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ : out STD_LOGIC;
\mer_int_reg[0]\ : out STD_LOGIC;
\mer_int_reg[1]\ : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
ip2bus_wrack_int_d1 : in STD_LOGIC;
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ : in STD_LOGIC;
p_0_in2_in : in STD_LOGIC;
p_0_in5_in : in STD_LOGIC;
p_0_in8_in : in STD_LOGIC;
p_0_in11_in : in STD_LOGIC;
p_0_in14_in : in STD_LOGIC;
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack : in STD_LOGIC;
is_read : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]\ : in STD_LOGIC;
\Douta_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]\ : in STD_LOGIC;
\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]_1\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_1\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]_2\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_2\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]_3\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_3\ : in STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC;
ip2bus_rdack_int_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\ : in STD_LOGIC;
p_0_in118_in : in STD_LOGIC;
p_0_in107_in : in STD_LOGIC;
p_0_in96_in : in STD_LOGIC;
p_0_in85_in : in STD_LOGIC;
p_0_in74_in : in STD_LOGIC;
p_0_in64_in : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ : in STD_LOGIC;
p_0_in59_in : in STD_LOGIC;
p_0_in57_in : in STD_LOGIC;
p_0_in55_in : in STD_LOGIC;
p_0_in53_in : in STD_LOGIC;
p_0_in51_in : in STD_LOGIC;
p_0_in49_in : in STD_LOGIC;
\mer_int_reg[0]_0\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_address_decoder : entity is "address_decoder";
end system_microblaze_0_axi_intc_0_address_decoder;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ : STD_LOGIC;
signal \^sie_gen.sie_bit_gen[0].sie_reg[0]\ : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \eqOp__2\ : STD_LOGIC;
signal ip2bus_wrack_int_d1_i_2_n_0 : STD_LOGIC;
signal ip2bus_wrack_int_d1_i_3_n_0 : STD_LOGIC;
signal ip2bus_wrack_int_d1_i_4_n_0 : STD_LOGIC;
signal ip2bus_wrack_int_d1_i_5_n_0 : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal \^p_17_in\ : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_0 : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_5_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \REG_GEN[0].IMR_FAST_MODE_GEN.imr[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \REG_GEN[0].ier[0]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of ip2bus_wrack_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ip2bus_wrack_int_d1_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \mer_int[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \s_axi_rdata_i[31]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[6]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[6]_i_5\ : label is "soft_lutpair1";
begin
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ <= \^sie_gen.sie_bit_gen[0].sie_reg[0]\;
p_17_in <= \^p_17_in\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[0].cie[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(0),
O => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\
);
\CIE_GEN.CIE_BIT_GEN[1].cie[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in59_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(1),
O => \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\
);
\CIE_GEN.CIE_BIT_GEN[2].cie[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in57_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(2),
O => \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\
);
\CIE_GEN.CIE_BIT_GEN[3].cie[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in55_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(3),
O => \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\
);
\CIE_GEN.CIE_BIT_GEN[4].cie[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in53_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(4),
O => \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\
);
\CIE_GEN.CIE_BIT_GEN[5].cie[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in51_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(5),
O => \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\
);
\CIE_GEN.CIE_BIT_GEN[6].cie[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in49_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(6),
O => \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
O => \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0\,
Q => \^p_17_in\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_5_out,
Q => p_7_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
O => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => \bus2ip_addr_i_reg[8]\(4),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(3),
O => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0\,
Q => p_6_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_3_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_3_out,
Q => p_5_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_2_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_2_out,
Q => p_4_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_1_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_1_out,
Q => p_3_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEFFFFF"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(5),
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(2),
O => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_15_out,
Q => p_2_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFCF8FFFFFFFF"
)
port map (
I0 => is_write_reg,
I1 => \eqOp__2\,
I2 => ip2bus_wrack,
I3 => is_read,
I4 => ip2bus_rdack,
I5 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(5),
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => Q,
O => pselect_hit_i_0
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
O => \eqOp__2\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => pselect_hit_i_0,
Q => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_14_out,
Q => p_16_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_13_out,
Q => p_15_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => \bus2ip_addr_i_reg[8]\(4),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(3),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0\,
Q => p_14_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_11_out,
Q => p_13_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_10_out,
Q => p_12_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \bus2ip_addr_i_reg[8]\(3),
I4 => pselect_hit_i_1,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(4),
I1 => Q,
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(5),
O => pselect_hit_i_1
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_9_out,
Q => p_11_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_8_out,
Q => p_10_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_7_out,
Q => p_9_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_6_out,
Q => p_8_in,
R => cs_ce_clr
);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\,
O => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\
);
\REG_GEN[0].IMR_FAST_MODE_GEN.imr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_9_in,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => bus2ip_wrce(1)
);
\REG_GEN[0].ier[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_15_in,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => \bus2ip_wrce__0\(0)
);
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in14_in,
O => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\
);
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in11_in,
O => \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\
);
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in8_in,
O => \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\
);
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in5_in,
O => \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\
);
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in2_in,
O => \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\
);
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\,
O => \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\
);
\SIE_GEN.SIE_BIT_GEN[0].sie[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(0),
I3 => s_axi_aresetn,
I4 => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\,
O => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\
);
\SIE_GEN.SIE_BIT_GEN[1].sie[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(1),
I3 => s_axi_aresetn,
I4 => p_0_in118_in,
O => \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\
);
\SIE_GEN.SIE_BIT_GEN[2].sie[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(2),
I3 => s_axi_aresetn,
I4 => p_0_in107_in,
O => \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\
);
\SIE_GEN.SIE_BIT_GEN[3].sie[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(3),
I3 => s_axi_aresetn,
I4 => p_0_in96_in,
O => \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\
);
\SIE_GEN.SIE_BIT_GEN[4].sie[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(4),
I3 => s_axi_aresetn,
I4 => p_0_in85_in,
O => \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\
);
\SIE_GEN.SIE_BIT_GEN[5].sie[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(5),
I3 => s_axi_aresetn,
I4 => p_0_in74_in,
O => \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\
);
\SIE_GEN.SIE_BIT_GEN[6].sie[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(6),
I3 => s_axi_aresetn,
I4 => p_0_in64_in,
O => \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\
);
ip2bus_rdack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFCCC8"
)
port map (
I0 => p_14_in,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => ip2bus_wrack_int_d1_i_4_n_0,
I4 => \s_axi_rdata_i[31]_i_3_n_0\,
I5 => ip2bus_rdack_int_d1,
O => ip2bus_rdack_prev2
);
ip2bus_rdack_int_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFAAFEAA"
)
port map (
I0 => \s_axi_rdata_i[31]_i_3_n_0\,
I1 => ip2bus_wrack_int_d1_i_4_n_0,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I4 => p_14_in,
O => Or128_vec2stdlogic19_out
);
ip2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF32"
)
port map (
I0 => ip2bus_wrack_int_d1_i_4_n_0,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => ip2bus_wrack_int_d1_i_3_n_0,
I3 => ip2bus_wrack_int_d1_i_2_n_0,
I4 => ip2bus_wrack_int_d1,
O => ip2bus_wrack_prev2
);
ip2bus_wrack_int_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AFAE"
)
port map (
I0 => ip2bus_wrack_int_d1_i_2_n_0,
I1 => ip2bus_wrack_int_d1_i_3_n_0,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => ip2bus_wrack_int_d1_i_4_n_0,
O => Or128_vec2stdlogic
);
ip2bus_wrack_int_d1_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF00FE"
)
port map (
I0 => p_14_in,
I1 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I2 => p_10_in,
I3 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I4 => p_15_in,
O => ip2bus_wrack_int_d1_i_2_n_0
);
ip2bus_wrack_int_d1_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_9_in,
I2 => \^p_17_in\,
I3 => p_8_in,
I4 => p_11_in,
O => ip2bus_wrack_int_d1_i_3_n_0
);
ip2bus_wrack_int_d1_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_5_in,
I1 => p_4_in,
I2 => p_7_in,
I3 => p_6_in,
I4 => ip2bus_wrack_int_d1_i_5_n_0,
O => ip2bus_wrack_int_d1_i_4_n_0
);
ip2bus_wrack_int_d1_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_2_in,
I1 => p_3_in,
I2 => p_13_in,
I3 => p_12_in,
O => ip2bus_wrack_int_d1_i_5_n_0
);
\mer_int[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_10_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => \mer_int_reg[0]_0\,
O => \mer_int_reg[0]\
);
\mer_int[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF20"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => p_10_in,
I3 => p_0_in,
O => \mer_int_reg[1]\
);
ram_reg_0_15_0_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => bus2ip_wrce(0)
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE0E0E0"
)
port map (
I0 => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[5]\,
I2 => \s_axi_rdata_i[6]_i_4_n_0\,
I3 => \Douta_reg[31]\(0),
I4 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(0)
);
\s_axi_rdata_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(10),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(10)
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(11),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(11)
);
\s_axi_rdata_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(12),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(12)
);
\s_axi_rdata_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(13),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(13)
);
\s_axi_rdata_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(14),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(14)
);
\s_axi_rdata_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(15),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(15)
);
\s_axi_rdata_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(16),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(16)
);
\s_axi_rdata_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(17),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(17)
);
\s_axi_rdata_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(18),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(18)
);
\s_axi_rdata_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(19),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(19)
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE0E0E0"
)
port map (
I0 => \REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]\,
I1 => \bus2ip_addr_i_reg[5]\,
I2 => \s_axi_rdata_i[6]_i_4_n_0\,
I3 => \Douta_reg[31]\(1),
I4 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(1)
);
\s_axi_rdata_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(20),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(20)
);
\s_axi_rdata_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(21),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(21)
);
\s_axi_rdata_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(22),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(22)
);
\s_axi_rdata_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(23),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(23)
);
\s_axi_rdata_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(24),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(24)
);
\s_axi_rdata_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(25),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(25)
);
\s_axi_rdata_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(26),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(26)
);
\s_axi_rdata_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(27),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(27)
);
\s_axi_rdata_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(28),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(28)
);
\s_axi_rdata_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(29),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(29)
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[3]\,
I1 => \bus2ip_addr_i_reg[5]\,
I2 => \REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(2),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(2)
);
\s_axi_rdata_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(30),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(30)
);
\s_axi_rdata_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(31),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(31)
);
\s_axi_rdata_i[31]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => ip2bus_wrack_int_d1_i_3_n_0,
I1 => p_10_in,
I2 => p_15_in,
I3 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => \s_axi_rdata_i[31]_i_3_n_0\
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \bus2ip_addr_i_reg[3]_0\,
I2 => \bus2ip_addr_i_reg[5]_0\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(3),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(3)
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \bus2ip_addr_i_reg[3]_1\,
I2 => \bus2ip_addr_i_reg[5]_1\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(4),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(4)
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \bus2ip_addr_i_reg[3]_2\,
I2 => \bus2ip_addr_i_reg[5]_2\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(5),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(5)
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \bus2ip_addr_i_reg[3]_3\,
I2 => \bus2ip_addr_i_reg[5]_3\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(6),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(6)
);
\s_axi_rdata_i[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AAA8"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_15_in,
I2 => p_10_in,
I3 => ip2bus_wrack_int_d1_i_3_n_0,
I4 => \bus2ip_addr_i_reg[6]\,
O => \s_axi_rdata_i[6]_i_4_n_0\
);
\s_axi_rdata_i[6]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => p_15_in,
I3 => p_10_in,
I4 => ip2bus_wrack_int_d1_i_3_n_0,
O => \s_axi_rdata_i[6]_i_5_n_0\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(7),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(7)
);
\s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(8),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(8)
);
\s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(9),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_shared_ram_ivar is
port (
Douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 );
\bus2ip_addr_i_reg[5]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ivar_index_axi_clk : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_shared_ram_ivar : entity is "shared_ram_ivar";
end system_microblaze_0_axi_intc_0_shared_ram_ivar;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_shared_ram_ivar is
signal Doutb0 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ram_reg_0_15_0_0_n_1 : STD_LOGIC;
signal ram_reg_0_15_10_10_n_1 : STD_LOGIC;
signal ram_reg_0_15_11_11_n_1 : STD_LOGIC;
signal ram_reg_0_15_12_12_n_1 : STD_LOGIC;
signal ram_reg_0_15_13_13_n_1 : STD_LOGIC;
signal ram_reg_0_15_14_14_n_1 : STD_LOGIC;
signal ram_reg_0_15_15_15_n_1 : STD_LOGIC;
signal ram_reg_0_15_16_16_n_1 : STD_LOGIC;
signal ram_reg_0_15_17_17_n_1 : STD_LOGIC;
signal ram_reg_0_15_18_18_n_1 : STD_LOGIC;
signal ram_reg_0_15_19_19_n_1 : STD_LOGIC;
signal ram_reg_0_15_1_1_n_1 : STD_LOGIC;
signal ram_reg_0_15_20_20_n_1 : STD_LOGIC;
signal ram_reg_0_15_21_21_n_1 : STD_LOGIC;
signal ram_reg_0_15_22_22_n_1 : STD_LOGIC;
signal ram_reg_0_15_23_23_n_1 : STD_LOGIC;
signal ram_reg_0_15_24_24_n_1 : STD_LOGIC;
signal ram_reg_0_15_25_25_n_1 : STD_LOGIC;
signal ram_reg_0_15_26_26_n_1 : STD_LOGIC;
signal ram_reg_0_15_27_27_n_1 : STD_LOGIC;
signal ram_reg_0_15_28_28_n_1 : STD_LOGIC;
signal ram_reg_0_15_29_29_n_1 : STD_LOGIC;
signal ram_reg_0_15_2_2_n_1 : STD_LOGIC;
signal ram_reg_0_15_30_30_n_1 : STD_LOGIC;
signal ram_reg_0_15_31_31_n_1 : STD_LOGIC;
signal ram_reg_0_15_3_3_n_1 : STD_LOGIC;
signal ram_reg_0_15_4_4_n_1 : STD_LOGIC;
signal ram_reg_0_15_5_5_n_1 : STD_LOGIC;
signal ram_reg_0_15_6_6_n_1 : STD_LOGIC;
signal ram_reg_0_15_7_7_n_1 : STD_LOGIC;
signal ram_reg_0_15_8_8_n_1 : STD_LOGIC;
signal ram_reg_0_15_9_9_n_1 : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_0_0 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_10_10 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_11_11 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_12_12 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_13_13 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_14_14 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_15_15 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_16_16 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_17_17 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_18_18 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_19_19 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_1_1 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_20_20 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_21_21 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_22_22 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_23_23 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_24_24 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_25_25 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_26_26 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_27_27 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_28_28 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_29_29 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_2_2 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_30_30 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_31_31 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_3_3 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_4_4 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_5_5 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_6_6 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_7_7 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_8_8 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_9_9 : label is "RAM16X1D";
begin
\Douta_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_0_0_n_1,
Q => Douta(0),
R => '0'
);
\Douta_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_10_10_n_1,
Q => Douta(10),
R => '0'
);
\Douta_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_11_11_n_1,
Q => Douta(11),
R => '0'
);
\Douta_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_12_12_n_1,
Q => Douta(12),
R => '0'
);
\Douta_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_13_13_n_1,
Q => Douta(13),
R => '0'
);
\Douta_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_14_14_n_1,
Q => Douta(14),
R => '0'
);
\Douta_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_15_15_n_1,
Q => Douta(15),
R => '0'
);
\Douta_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_16_16_n_1,
Q => Douta(16),
R => '0'
);
\Douta_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_17_17_n_1,
Q => Douta(17),
R => '0'
);
\Douta_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_18_18_n_1,
Q => Douta(18),
R => '0'
);
\Douta_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_19_19_n_1,
Q => Douta(19),
R => '0'
);
\Douta_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_1_1_n_1,
Q => Douta(1),
R => '0'
);
\Douta_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_20_20_n_1,
Q => Douta(20),
R => '0'
);
\Douta_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_21_21_n_1,
Q => Douta(21),
R => '0'
);
\Douta_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_22_22_n_1,
Q => Douta(22),
R => '0'
);
\Douta_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_23_23_n_1,
Q => Douta(23),
R => '0'
);
\Douta_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_24_24_n_1,
Q => Douta(24),
R => '0'
);
\Douta_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_25_25_n_1,
Q => Douta(25),
R => '0'
);
\Douta_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_26_26_n_1,
Q => Douta(26),
R => '0'
);
\Douta_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_27_27_n_1,
Q => Douta(27),
R => '0'
);
\Douta_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_28_28_n_1,
Q => Douta(28),
R => '0'
);
\Douta_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_29_29_n_1,
Q => Douta(29),
R => '0'
);
\Douta_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_2_2_n_1,
Q => Douta(2),
R => '0'
);
\Douta_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_30_30_n_1,
Q => Douta(30),
R => '0'
);
\Douta_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_31_31_n_1,
Q => Douta(31),
R => '0'
);
\Douta_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_3_3_n_1,
Q => Douta(3),
R => '0'
);
\Douta_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_4_4_n_1,
Q => Douta(4),
R => '0'
);
\Douta_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_5_5_n_1,
Q => Douta(5),
R => '0'
);
\Douta_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_6_6_n_1,
Q => Douta(6),
R => '0'
);
\Douta_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_7_7_n_1,
Q => Douta(7),
R => '0'
);
\Douta_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_8_8_n_1,
Q => Douta(8),
R => '0'
);
\Douta_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_9_9_n_1,
Q => Douta(9),
R => '0'
);
\Doutb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(0),
Q => interrupt_address(0),
R => '0'
);
\Doutb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(10),
Q => interrupt_address(10),
R => '0'
);
\Doutb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(11),
Q => interrupt_address(11),
R => '0'
);
\Doutb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(12),
Q => interrupt_address(12),
R => '0'
);
\Doutb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(13),
Q => interrupt_address(13),
R => '0'
);
\Doutb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(14),
Q => interrupt_address(14),
R => '0'
);
\Doutb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(15),
Q => interrupt_address(15),
R => '0'
);
\Doutb_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(16),
Q => interrupt_address(16),
R => '0'
);
\Doutb_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(17),
Q => interrupt_address(17),
R => '0'
);
\Doutb_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(18),
Q => interrupt_address(18),
R => '0'
);
\Doutb_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(19),
Q => interrupt_address(19),
R => '0'
);
\Doutb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(1),
Q => interrupt_address(1),
R => '0'
);
\Doutb_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(20),
Q => interrupt_address(20),
R => '0'
);
\Doutb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(21),
Q => interrupt_address(21),
R => '0'
);
\Doutb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(22),
Q => interrupt_address(22),
R => '0'
);
\Doutb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(23),
Q => interrupt_address(23),
R => '0'
);
\Doutb_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(24),
Q => interrupt_address(24),
R => '0'
);
\Doutb_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(25),
Q => interrupt_address(25),
R => '0'
);
\Doutb_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(26),
Q => interrupt_address(26),
R => '0'
);
\Doutb_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(27),
Q => interrupt_address(27),
R => '0'
);
\Doutb_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(28),
Q => interrupt_address(28),
R => '0'
);
\Doutb_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(29),
Q => interrupt_address(29),
R => '0'
);
\Doutb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(2),
Q => interrupt_address(2),
R => '0'
);
\Doutb_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(30),
Q => interrupt_address(30),
R => '0'
);
\Doutb_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(31),
Q => interrupt_address(31),
R => '0'
);
\Doutb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(3),
Q => interrupt_address(3),
R => '0'
);
\Doutb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(4),
Q => interrupt_address(4),
R => '0'
);
\Doutb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(5),
Q => interrupt_address(5),
R => '0'
);
\Doutb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(6),
Q => interrupt_address(6),
R => '0'
);
\Doutb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(7),
Q => interrupt_address(7),
R => '0'
);
\Doutb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(8),
Q => interrupt_address(8),
R => '0'
);
\Doutb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(9),
Q => interrupt_address(9),
R => '0'
);
ram_reg_0_15_0_0: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(0),
DPO => Doutb0(0),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_0_0_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_10_10: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(10),
DPO => Doutb0(10),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_10_10_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_11_11: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(11),
DPO => Doutb0(11),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_11_11_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_12_12: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(12),
DPO => Doutb0(12),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_12_12_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_13_13: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(13),
DPO => Doutb0(13),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_13_13_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_14_14: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(14),
DPO => Doutb0(14),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_14_14_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_15_15: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(15),
DPO => Doutb0(15),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_15_15_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_16_16: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(16),
DPO => Doutb0(16),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_16_16_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_17_17: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(17),
DPO => Doutb0(17),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_17_17_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_18_18: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(18),
DPO => Doutb0(18),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_18_18_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_19_19: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(19),
DPO => Doutb0(19),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_19_19_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_1_1: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(1),
DPO => Doutb0(1),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_1_1_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_20_20: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(20),
DPO => Doutb0(20),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_20_20_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_21_21: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(21),
DPO => Doutb0(21),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_21_21_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_22_22: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(22),
DPO => Doutb0(22),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_22_22_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_23_23: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(23),
DPO => Doutb0(23),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_23_23_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_24_24: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(24),
DPO => Doutb0(24),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_24_24_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_25_25: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(25),
DPO => Doutb0(25),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_25_25_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_26_26: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(26),
DPO => Doutb0(26),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_26_26_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_27_27: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(27),
DPO => Doutb0(27),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_27_27_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_28_28: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(28),
DPO => Doutb0(28),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_28_28_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_29_29: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(29),
DPO => Doutb0(29),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_29_29_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_2_2: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(2),
DPO => Doutb0(2),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_2_2_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_30_30: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(30),
DPO => Doutb0(30),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_30_30_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_31_31: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(31),
DPO => Doutb0(31),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_31_31_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_3_3: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(3),
DPO => Doutb0(3),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_3_3_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_4_4: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"0000FFFF"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(4),
DPO => Doutb0(4),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_4_4_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_5_5: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(5),
DPO => Doutb0(5),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_5_5_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_6_6: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(6),
DPO => Doutb0(6),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_6_6_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_7_7: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(7),
DPO => Doutb0(7),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_7_7_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_8_8: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(8),
DPO => Doutb0(8),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_8_8_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_9_9: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(9),
DPO => Doutb0(9),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_9_9_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_intc_core is
port (
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0\ : out STD_LOGIC;
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in14_in : out STD_LOGIC;
p_0_in11_in : out STD_LOGIC;
p_0_in8_in : out STD_LOGIC;
p_0_in5_in : out STD_LOGIC;
p_0_in2_in : out STD_LOGIC;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0\ : out STD_LOGIC;
\IVR_GEN.ivr_reg[1]_0\ : out STD_LOGIC;
p_0_in28_in : out STD_LOGIC;
p_0_in26_in : out STD_LOGIC;
p_0_in24_in : out STD_LOGIC;
p_0_in22_in : out STD_LOGIC;
p_0_in20_in : out STD_LOGIC;
p_0_in19_in : out STD_LOGIC;
irq : out STD_LOGIC;
\REG_GEN[0].ier_reg[0]_0\ : out STD_LOGIC;
p_0_in118_in : out STD_LOGIC;
p_0_in107_in : out STD_LOGIC;
p_0_in96_in : out STD_LOGIC;
p_0_in85_in : out STD_LOGIC;
p_0_in74_in : out STD_LOGIC;
p_0_in64_in : out STD_LOGIC;
\REG_GEN[0].ier_reg[0]_1\ : out STD_LOGIC;
p_0_in59_in : out STD_LOGIC;
p_0_in57_in : out STD_LOGIC;
p_0_in55_in : out STD_LOGIC;
p_0_in53_in : out STD_LOGIC;
p_0_in51_in : out STD_LOGIC;
p_0_in49_in : out STD_LOGIC;
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0\ : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\IVR_GEN.ivr_reg[1]_1\ : out STD_LOGIC;
p_1_in29_in : out STD_LOGIC;
p_1_in27_in : out STD_LOGIC;
p_1_in25_in : out STD_LOGIC;
p_1_in23_in : out STD_LOGIC;
p_1_in21_in : out STD_LOGIC;
p_1_in : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0\ : out STD_LOGIC;
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
Douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 6 downto 0 );
Bus_RNW_reg_reg : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\bus2ip_addr_i_reg[5]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
Bus_RNW_reg_reg_7 : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_17_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_intc_core : entity is "intc_core";
end system_microblaze_0_axi_intc_0_intc_core;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_intc_core is
signal \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0\ : STD_LOGIC;
signal \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0\ : STD_LOGIC;
signal \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1]\ : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1]\ : signal is "true";
signal \INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[0]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[1]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[2]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[3]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[4]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[5]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[6]_i_1_n_0\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0\ : STD_LOGIC;
signal \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0\ : STD_LOGIC;
signal \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0\ : STD_LOGIC;
signal \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0\ : STD_LOGIC;
signal \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\ : STD_LOGIC;
signal \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\ : STD_LOGIC;
signal \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\ : STD_LOGIC;
signal \IVR_GEN.ivr[0]_i_2_n_0\ : STD_LOGIC;
signal \IVR_GEN.ivr[1]_i_1_n_0\ : STD_LOGIC;
signal \IVR_GEN.ivr[1]_i_2_n_0\ : STD_LOGIC;
signal \IVR_GEN.ivr[1]_i_3_n_0\ : STD_LOGIC;
signal \IVR_GEN.ivr[2]_i_1_n_0\ : STD_LOGIC;
signal \^ivr_gen.ivr_reg[1]_0\ : STD_LOGIC;
signal \^ivr_gen.ivr_reg[1]_1\ : STD_LOGIC;
signal Irq_i : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0\ : STD_LOGIC;
signal \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\ : STD_LOGIC;
signal \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\ : STD_LOGIC;
signal \^reg_gen[0].ier_reg[0]_0\ : STD_LOGIC;
signal \^reg_gen[0].ier_reg[0]_1\ : STD_LOGIC;
signal \REG_GEN[0].isr[0]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\ : STD_LOGIC;
signal \REG_GEN[1].isr[1]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[2].isr[2]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[3].isr[3]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[4].isr[4]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[5].isr[5]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0\ : STD_LOGIC;
signal \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\ : STD_LOGIC;
signal \REG_GEN[6].isr[6]_i_2_n_0\ : STD_LOGIC;
signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ack_or : STD_LOGIC;
signal ack_or_i : STD_LOGIC;
signal ack_or_i_2_n_0 : STD_LOGIC;
signal current_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal first_ack : STD_LOGIC;
signal first_ack_active : STD_LOGIC;
signal hw_intr : STD_LOGIC_VECTOR ( 6 downto 0 );
signal idle_and_irq : STD_LOGIC;
signal idle_and_irq_d1 : STD_LOGIC;
signal in_idle : STD_LOGIC;
signal intr_d1 : STD_LOGIC;
signal intr_ff : STD_LOGIC_VECTOR ( 0 to 1 );
attribute async_reg of intr_ff : signal is "true";
signal irq_gen : STD_LOGIC;
signal irq_gen_i_1_n_0 : STD_LOGIC;
signal irq_gen_i_2_n_0 : STD_LOGIC;
signal ivar_index_axi_clk : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ivar_index_sample_en : STD_LOGIC;
signal ivar_index_sample_en_i : STD_LOGIC;
signal ivr_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \^p_0_in107_in\ : STD_LOGIC;
signal \^p_0_in118_in\ : STD_LOGIC;
signal \^p_0_in11_in\ : STD_LOGIC;
signal \^p_0_in14_in\ : STD_LOGIC;
signal \^p_0_in19_in\ : STD_LOGIC;
signal \^p_0_in20_in\ : STD_LOGIC;
signal \^p_0_in22_in\ : STD_LOGIC;
signal \^p_0_in24_in\ : STD_LOGIC;
signal \^p_0_in26_in\ : STD_LOGIC;
signal \^p_0_in28_in\ : STD_LOGIC;
signal \^p_0_in2_in\ : STD_LOGIC;
signal \^p_0_in49_in\ : STD_LOGIC;
signal \^p_0_in51_in\ : STD_LOGIC;
signal \^p_0_in53_in\ : STD_LOGIC;
signal \^p_0_in55_in\ : STD_LOGIC;
signal \^p_0_in57_in\ : STD_LOGIC;
signal \^p_0_in59_in\ : STD_LOGIC;
signal \^p_0_in5_in\ : STD_LOGIC;
signal \^p_0_in64_in\ : STD_LOGIC;
signal \^p_0_in74_in\ : STD_LOGIC;
signal \^p_0_in85_in\ : STD_LOGIC;
signal \^p_0_in8_in\ : STD_LOGIC;
signal \^p_0_in96_in\ : STD_LOGIC;
signal p_17_out : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
signal \^p_1_in21_in\ : STD_LOGIC;
signal \^p_1_in23_in\ : STD_LOGIC;
signal \^p_1_in25_in\ : STD_LOGIC;
signal \^p_1_in27_in\ : STD_LOGIC;
signal \^p_1_in29_in\ : STD_LOGIC;
signal \p_1_out__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute async_reg of \p_1_out__0\ : signal is "true";
signal p_21_out : STD_LOGIC;
signal p_25_out : STD_LOGIC;
signal p_29_out : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_33_out : STD_LOGIC;
signal p_37_out : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_41_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_43_out : STD_LOGIC;
signal p_44_out : STD_LOGIC;
signal p_45_out : STD_LOGIC;
signal p_46_out : STD_LOGIC;
signal p_47_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal second_ack : STD_LOGIC;
signal second_ack_sync_d1 : STD_LOGIC;
signal second_ack_sync_d2 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1\ : label is "soft_lutpair28";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1\ : label is "soft_lutpair27";
attribute ASYNC_REG_boolean of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]\ : label is std.standard.true;
attribute KEEP of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of \IPR_GEN.ipr[3]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \IPR_GEN.ipr[5]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.idle_and_irq_d1_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_sample_en_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \IVR_GEN.ivr[1]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \IVR_GEN.ivr[1]_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \IVR_GEN.ivr[2]_i_1\ : label is "soft_lutpair27";
begin
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0\ <= \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\;
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0\ <= \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\;
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1\ <= \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\;
\IVR_GEN.ivr_reg[1]_0\ <= \^ivr_gen.ivr_reg[1]_0\;
\IVR_GEN.ivr_reg[1]_1\ <= \^ivr_gen.ivr_reg[1]_1\;
Q(0) <= \^q\(0);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0\ <= \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\;
\REG_GEN[0].ier_reg[0]_0\ <= \^reg_gen[0].ier_reg[0]_0\;
\REG_GEN[0].ier_reg[0]_1\ <= \^reg_gen[0].ier_reg[0]_1\;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0\ <= \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\;
SS(0) <= \^ss\(0);
p_0_in <= \^p_0_in\;
p_0_in107_in <= \^p_0_in107_in\;
p_0_in118_in <= \^p_0_in118_in\;
p_0_in11_in <= \^p_0_in11_in\;
p_0_in14_in <= \^p_0_in14_in\;
p_0_in19_in <= \^p_0_in19_in\;
p_0_in20_in <= \^p_0_in20_in\;
p_0_in22_in <= \^p_0_in22_in\;
p_0_in24_in <= \^p_0_in24_in\;
p_0_in26_in <= \^p_0_in26_in\;
p_0_in28_in <= \^p_0_in28_in\;
p_0_in2_in <= \^p_0_in2_in\;
p_0_in49_in <= \^p_0_in49_in\;
p_0_in51_in <= \^p_0_in51_in\;
p_0_in53_in <= \^p_0_in53_in\;
p_0_in55_in <= \^p_0_in55_in\;
p_0_in57_in <= \^p_0_in57_in\;
p_0_in59_in <= \^p_0_in59_in\;
p_0_in5_in <= \^p_0_in5_in\;
p_0_in64_in <= \^p_0_in64_in\;
p_0_in74_in <= \^p_0_in74_in\;
p_0_in85_in <= \^p_0_in85_in\;
p_0_in8_in <= \^p_0_in8_in\;
p_0_in96_in <= \^p_0_in96_in\;
p_1_in <= \^p_1_in\;
p_1_in21_in <= \^p_1_in21_in\;
p_1_in23_in <= \^p_1_in23_in\;
p_1_in25_in <= \^p_1_in25_in\;
p_1_in27_in <= \^p_1_in27_in\;
p_1_in29_in <= \^p_1_in29_in\;
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => processor_ack(0),
I1 => processor_ack(1),
I2 => first_ack_active,
O => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0\
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0\,
Q => first_ack_active,
R => \^ss\(0)
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => processor_ack(0),
I1 => processor_ack(1),
O => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0\
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0\,
Q => first_ack,
R => \^ss\(0)
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => first_ack_active,
I1 => processor_ack(1),
O => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0\
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0\,
Q => second_ack,
R => \^ss\(0)
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_sync_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => second_ack,
Q => second_ack_sync_d1,
R => \^ss\(0)
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_sync_d2_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => second_ack_sync_d1,
Q => second_ack_sync_d2,
R => \^ss\(0)
);
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\,
Q => \^reg_gen[0].ier_reg[0]_1\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0\,
Q => \^p_0_in59_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0\,
Q => \^p_0_in57_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0\,
Q => \^p_0_in55_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0\,
Q => \^p_0_in53_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0\,
Q => \^p_0_in51_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0\,
Q => \^p_0_in49_in\,
R => '0'
);
\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => hw_intr(0),
I1 => intr(0),
I2 => s_axi_aresetn,
I3 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
O => \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0\
);
\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0\,
Q => hw_intr(0),
R => '0'
);
\INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => intr(1),
Q => intr_ff(0),
R => '0'
);
\INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => intr_ff(0),
Q => intr_ff(1),
R => '0'
);
\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => hw_intr(1),
I1 => intr_ff(1),
I2 => intr_d1,
I3 => s_axi_aresetn,
I4 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
O => \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0\
);
\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0\,
Q => hw_intr(1),
R => '0'
);
\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.intr_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_ff(1),
Q => intr_d1,
R => \^ss\(0)
);
\INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => hw_intr(2),
I1 => intr(2),
I2 => s_axi_aresetn,
I3 => p_2_in,
O => \INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0\
);
\INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0\,
Q => hw_intr(2),
R => '0'
);
\INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => hw_intr(3),
I1 => intr(3),
I2 => s_axi_aresetn,
I3 => p_3_in,
O => \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0\
);
\INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0\,
Q => hw_intr(3),
R => '0'
);
\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => hw_intr(4),
I1 => intr(4),
I2 => \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0\,
I3 => s_axi_aresetn,
I4 => p_4_in,
O => \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0\
);
\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0\,
Q => hw_intr(4),
R => '0'
);
\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr(4),
Q => \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0\,
R => \^ss\(0)
);
\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => hw_intr(5),
I1 => intr(5),
I2 => \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0\,
I3 => s_axi_aresetn,
I4 => p_5_in,
O => \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0\
);
\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0\,
Q => hw_intr(5),
R => '0'
);
\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr(5),
Q => \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0\,
R => \^ss\(0)
);
\INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => intr(6),
Q => \p_1_out__0\(0),
R => '0'
);
\INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \p_1_out__0\(0),
Q => \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1]\,
R => '0'
);
\INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => hw_intr(6),
I1 => \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1]\,
I2 => s_axi_aresetn,
I3 => p_6_in,
O => \INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0\
);
\INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0\,
Q => hw_intr(6),
R => '0'
);
\IPR_GEN.ipr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^ivr_gen.ivr_reg[1]_1\,
I1 => \^ivr_gen.ivr_reg[1]_0\,
O => \IPR_GEN.ipr[0]_i_1_n_0\
);
\IPR_GEN.ipr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in29_in\,
I1 => \^p_0_in28_in\,
O => \IPR_GEN.ipr[1]_i_1_n_0\
);
\IPR_GEN.ipr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in27_in\,
I1 => \^p_0_in26_in\,
O => \IPR_GEN.ipr[2]_i_1_n_0\
);
\IPR_GEN.ipr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in25_in\,
I1 => \^p_0_in24_in\,
O => \IPR_GEN.ipr[3]_i_1_n_0\
);
\IPR_GEN.ipr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in23_in\,
I1 => \^p_0_in22_in\,
O => \IPR_GEN.ipr[4]_i_1_n_0\
);
\IPR_GEN.ipr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in21_in\,
I1 => \^p_0_in20_in\,
O => \IPR_GEN.ipr[5]_i_1_n_0\
);
\IPR_GEN.ipr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in\,
I1 => \^p_0_in19_in\,
O => \IPR_GEN.ipr[6]_i_1_n_0\
);
\IPR_GEN.ipr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[0]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(0),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[1]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(1),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[2]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(2),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[3]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(3),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[4]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(4),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[5]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(5),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[6]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(6),
R => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
I1 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
O => Irq_i
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Irq_i,
Q => irq,
R => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000737F404C"
)
port map (
I0 => first_ack,
I1 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
I2 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0\,
I3 => ack_or,
I4 => ivar_index_sample_en,
I5 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
O => current_state(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00C05500"
)
port map (
I0 => second_ack_sync_d2,
I1 => first_ack,
I2 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0\,
I3 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
I4 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
O => current_state(1)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFAFCFA0C0AFC0A0"
)
port map (
I0 => \^p_0_in14_in\,
I1 => \^p_0_in8_in\,
I2 => ivar_index_axi_clk(0),
I3 => ivar_index_axi_clk(1),
I4 => \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\,
I5 => \^p_0_in11_in\,
O => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0\
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00CCF0AA"
)
port map (
I0 => \^p_0_in5_in\,
I1 => \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\,
I2 => \^p_0_in2_in\,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0\
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => current_state(0),
Q => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
R => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => current_state(1),
Q => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
R => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0\,
I1 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0\,
O => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0\,
S => ivar_index_axi_clk(2)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
I1 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
O => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0\
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0\,
Q => in_idle,
R => \^ss\(0)
);
\IVAR_FAST_MODE_GEN.IVAR_REG_MEM_AXI_CLK_GEN.IVAR_REG_MEM_I\: entity work.system_microblaze_0_axi_intc_0_shared_ram_ivar
port map (
Douta(31 downto 0) => Douta(31 downto 0),
\bus2ip_addr_i_reg[5]\(3 downto 0) => \bus2ip_addr_i_reg[5]\(3 downto 0),
bus2ip_wrce(0) => bus2ip_wrce(0),
interrupt_address(31 downto 0) => interrupt_address(31 downto 0),
ivar_index_axi_clk(2 downto 0) => ivar_index_axi_clk(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.idle_and_irq_d1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I1 => in_idle,
I2 => irq_gen,
O => idle_and_irq
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.idle_and_irq_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => idle_and_irq,
Q => idle_and_irq_d1,
R => \^ss\(0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^q\(0),
I1 => irq_gen,
I2 => in_idle,
I3 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I4 => idle_and_irq_d1,
I5 => ivar_index_axi_clk(0),
O => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0\
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\,
I1 => irq_gen,
I2 => in_idle,
I3 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I4 => idle_and_irq_d1,
I5 => ivar_index_axi_clk(1),
O => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0\
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\,
I1 => irq_gen,
I2 => in_idle,
I3 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I4 => idle_and_irq_d1,
I5 => ivar_index_axi_clk(2),
O => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0\
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0\,
Q => ivar_index_axi_clk(0),
R => \^ss\(0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0\,
Q => ivar_index_axi_clk(1),
R => \^ss\(0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0\,
Q => ivar_index_axi_clk(2),
R => \^ss\(0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_sample_en_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => irq_gen,
I1 => in_idle,
I2 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I3 => idle_and_irq_d1,
O => ivar_index_sample_en_i
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_sample_en_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ivar_index_sample_en_i,
Q => ivar_index_sample_en,
R => \^ss\(0)
);
\IVR_GEN.ivr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF002A002A002A"
)
port map (
I0 => \IVR_GEN.ivr[0]_i_2_n_0\,
I1 => \^p_0_in26_in\,
I2 => \^p_1_in27_in\,
I3 => \IPR_GEN.ipr[0]_i_1_n_0\,
I4 => \^p_1_in29_in\,
I5 => \^p_0_in28_in\,
O => ivr_in(0)
);
\IVR_GEN.ivr[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888F888FFFF"
)
port map (
I0 => \^p_1_in25_in\,
I1 => \^p_0_in24_in\,
I2 => \^p_0_in20_in\,
I3 => \^p_1_in21_in\,
I4 => \IPR_GEN.ipr[6]_i_1_n_0\,
I5 => \IPR_GEN.ipr[4]_i_1_n_0\,
O => \IVR_GEN.ivr[0]_i_2_n_0\
);
\IVR_GEN.ivr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555F7F7F7"
)
port map (
I0 => s_axi_aresetn,
I1 => \IVR_GEN.ivr[1]_i_2_n_0\,
I2 => \IVR_GEN.ivr[1]_i_3_n_0\,
I3 => \^ivr_gen.ivr_reg[1]_0\,
I4 => \^ivr_gen.ivr_reg[1]_1\,
I5 => \IPR_GEN.ipr[1]_i_1_n_0\,
O => \IVR_GEN.ivr[1]_i_1_n_0\
);
\IVR_GEN.ivr[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^p_0_in20_in\,
I1 => \^p_1_in21_in\,
I2 => \^p_0_in22_in\,
I3 => \^p_1_in23_in\,
O => \IVR_GEN.ivr[1]_i_2_n_0\
);
\IVR_GEN.ivr[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^p_0_in24_in\,
I1 => \^p_1_in25_in\,
I2 => \^p_0_in26_in\,
I3 => \^p_1_in27_in\,
O => \IVR_GEN.ivr[1]_i_3_n_0\
);
\IVR_GEN.ivr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_aresetn,
I1 => irq_gen_i_2_n_0,
O => \IVR_GEN.ivr[2]_i_1_n_0\
);
\IVR_GEN.ivr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => ivr_in(0),
Q => \^q\(0),
S => \^ss\(0)
);
\IVR_GEN.ivr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVR_GEN.ivr[1]_i_1_n_0\,
Q => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\,
R => '0'
);
\IVR_GEN.ivr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVR_GEN.ivr[2]_i_1_n_0\,
Q => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\,
R => '0'
);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_7,
I1 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0\,
I2 => second_ack,
I3 => s_axi_wdata(0),
I4 => s_axi_aresetn,
I5 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
O => \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0\
);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000040"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\,
I2 => second_ack,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0\
);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0\,
Q => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
R => '0'
);
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(0),
Q => \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\,
R => \^ss\(0)
);
\REG_GEN[0].ier[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^ivr_gen.ivr_reg[1]_0\,
I1 => s_axi_aresetn,
I2 => \^reg_gen[0].ier_reg[0]_1\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^reg_gen[0].ier_reg[0]_0\,
I5 => s_axi_wdata(0),
O => p_41_out
);
\REG_GEN[0].ier_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_41_out,
Q => \^ivr_gen.ivr_reg[1]_0\,
R => '0'
);
\REG_GEN[0].isr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
I1 => s_axi_aresetn,
O => p_48_out
);
\REG_GEN[0].isr[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(0),
I1 => s_axi_wdata(0),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^ivr_gen.ivr_reg[1]_1\,
O => \REG_GEN[0].isr[0]_i_2_n_0\
);
\REG_GEN[0].isr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[0].isr[0]_i_2_n_0\,
Q => \^ivr_gen.ivr_reg[1]_1\,
R => p_48_out
);
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_8,
I1 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0\,
I2 => first_ack,
I3 => s_axi_wdata(1),
I4 => s_axi_aresetn,
I5 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
O => \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0\
);
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^p_0_in14_in\,
I2 => first_ack,
I3 => ivar_index_axi_clk(1),
I4 => ivar_index_axi_clk(0),
O => \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0\
);
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0\,
Q => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
R => '0'
);
\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(1),
Q => \^p_0_in14_in\,
R => \^ss\(0)
);
\REG_GEN[1].ier[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in28_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in59_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in118_in\,
I5 => s_axi_wdata(1),
O => p_37_out
);
\REG_GEN[1].ier_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_37_out,
Q => \^p_0_in28_in\,
R => '0'
);
\REG_GEN[1].isr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
I1 => s_axi_aresetn,
O => p_47_out
);
\REG_GEN[1].isr[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(1),
I1 => s_axi_wdata(1),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in29_in\,
O => \REG_GEN[1].isr[1]_i_2_n_0\
);
\REG_GEN[1].isr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[1].isr[1]_i_2_n_0\,
Q => \^p_1_in29_in\,
R => p_47_out
);
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_9,
I1 => \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0\,
I2 => second_ack,
I3 => s_axi_wdata(2),
I4 => s_axi_aresetn,
I5 => p_2_in,
O => \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0\
);
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^p_0_in11_in\,
I2 => second_ack,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0\
);
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0\,
Q => p_2_in,
R => '0'
);
\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(2),
Q => \^p_0_in11_in\,
R => \^ss\(0)
);
\REG_GEN[2].ier[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in26_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in57_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in107_in\,
I5 => s_axi_wdata(2),
O => p_33_out
);
\REG_GEN[2].ier_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_33_out,
Q => \^p_0_in26_in\,
R => '0'
);
\REG_GEN[2].isr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_2_in,
I1 => s_axi_aresetn,
O => p_46_out
);
\REG_GEN[2].isr[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(2),
I1 => s_axi_wdata(2),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in27_in\,
O => \REG_GEN[2].isr[2]_i_2_n_0\
);
\REG_GEN[2].isr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[2].isr[2]_i_2_n_0\,
Q => \^p_1_in27_in\,
R => p_46_out
);
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_10,
I1 => \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0\,
I2 => second_ack,
I3 => s_axi_wdata(3),
I4 => s_axi_aresetn,
I5 => p_3_in,
O => \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0\
);
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000000"
)
port map (
I0 => ivar_index_axi_clk(0),
I1 => ivar_index_axi_clk(1),
I2 => ivar_index_axi_clk(2),
I3 => second_ack,
I4 => \^p_0_in8_in\,
O => \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0\
);
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0\,
Q => p_3_in,
R => '0'
);
\REG_GEN[3].IMR_FAST_MODE_GEN.imr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(3),
Q => \^p_0_in8_in\,
R => \^ss\(0)
);
\REG_GEN[3].ier[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in24_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in55_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in96_in\,
I5 => s_axi_wdata(3),
O => p_29_out
);
\REG_GEN[3].ier_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_29_out,
Q => \^p_0_in24_in\,
R => '0'
);
\REG_GEN[3].isr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_3_in,
I1 => s_axi_aresetn,
O => p_45_out
);
\REG_GEN[3].isr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(3),
I1 => s_axi_wdata(3),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in25_in\,
O => \REG_GEN[3].isr[3]_i_2_n_0\
);
\REG_GEN[3].isr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[3].isr[3]_i_2_n_0\,
Q => \^p_1_in25_in\,
R => p_45_out
);
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_11,
I1 => \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0\,
I2 => first_ack,
I3 => s_axi_wdata(4),
I4 => s_axi_aresetn,
I5 => p_4_in,
O => \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0\
);
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^p_0_in5_in\,
I2 => first_ack,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0\
);
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0\,
Q => p_4_in,
R => '0'
);
\REG_GEN[4].IMR_FAST_MODE_GEN.imr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(4),
Q => \^p_0_in5_in\,
R => \^ss\(0)
);
\REG_GEN[4].ier[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in22_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in53_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in85_in\,
I5 => s_axi_wdata(4),
O => p_25_out
);
\REG_GEN[4].ier_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_25_out,
Q => \^p_0_in22_in\,
R => '0'
);
\REG_GEN[4].isr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_4_in,
I1 => s_axi_aresetn,
O => p_44_out
);
\REG_GEN[4].isr[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(4),
I1 => s_axi_wdata(4),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in23_in\,
O => \REG_GEN[4].isr[4]_i_2_n_0\
);
\REG_GEN[4].isr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[4].isr[4]_i_2_n_0\,
Q => \^p_1_in23_in\,
R => p_44_out
);
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_12,
I1 => \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0\,
I2 => first_ack,
I3 => s_axi_wdata(5),
I4 => s_axi_aresetn,
I5 => p_5_in,
O => \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0\
);
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^p_0_in2_in\,
I2 => first_ack,
I3 => ivar_index_axi_clk(1),
I4 => ivar_index_axi_clk(0),
O => \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0\
);
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0\,
Q => p_5_in,
R => '0'
);
\REG_GEN[5].IMR_FAST_MODE_GEN.imr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(5),
Q => \^p_0_in2_in\,
R => \^ss\(0)
);
\REG_GEN[5].ier[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in20_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in51_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in74_in\,
I5 => s_axi_wdata(5),
O => p_21_out
);
\REG_GEN[5].ier_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_21_out,
Q => \^p_0_in20_in\,
R => '0'
);
\REG_GEN[5].isr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_5_in,
I1 => s_axi_aresetn,
O => p_43_out
);
\REG_GEN[5].isr[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(5),
I1 => s_axi_wdata(5),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in21_in\,
O => \REG_GEN[5].isr[5]_i_2_n_0\
);
\REG_GEN[5].isr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[5].isr[5]_i_2_n_0\,
Q => \^p_1_in21_in\,
R => p_43_out
);
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_13,
I1 => \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0\,
I2 => second_ack,
I3 => s_axi_wdata(6),
I4 => s_axi_aresetn,
I5 => p_6_in,
O => \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0\
);
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\,
I2 => second_ack,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0\
);
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0\,
Q => p_6_in,
R => '0'
);
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(6),
Q => \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\,
R => \^ss\(0)
);
\REG_GEN[6].ier[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in19_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in49_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in64_in\,
I5 => s_axi_wdata(6),
O => p_17_out
);
\REG_GEN[6].ier_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_17_out,
Q => \^p_0_in19_in\,
R => '0'
);
\REG_GEN[6].isr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_6_in,
I1 => s_axi_aresetn,
O => p_42_out
);
\REG_GEN[6].isr[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(6),
I1 => s_axi_wdata(6),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in\,
O => \REG_GEN[6].isr[6]_i_2_n_0\
);
\REG_GEN[6].isr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[6].isr[6]_i_2_n_0\,
Q => \^p_1_in\,
R => p_42_out
);
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg,
Q => \^reg_gen[0].ier_reg[0]_0\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_0,
Q => \^p_0_in118_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_1,
Q => \^p_0_in107_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_2,
Q => \^p_0_in96_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_3,
Q => \^p_0_in85_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_4,
Q => \^p_0_in74_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_5,
Q => \^p_0_in64_in\,
R => '0'
);
ack_or_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => ack_or_i_2_n_0,
I1 => p_6_in,
I2 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
I3 => p_3_in,
O => ack_or_i
);
ack_or_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_4_in,
I1 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
I2 => p_2_in,
I3 => p_5_in,
O => ack_or_i_2_n_0
);
ack_or_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ack_or_i,
Q => ack_or,
R => \^ss\(0)
);
irq_gen_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF8F8F8"
)
port map (
I0 => \^p_0_in19_in\,
I1 => \^p_1_in\,
I2 => irq_gen_i_2_n_0,
I3 => \^p_0_in20_in\,
I4 => \^p_1_in21_in\,
I5 => \IPR_GEN.ipr[4]_i_1_n_0\,
O => irq_gen_i_1_n_0
);
irq_gen_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEEEFEEEFEEE"
)
port map (
I0 => \IPR_GEN.ipr[1]_i_1_n_0\,
I1 => \IPR_GEN.ipr[0]_i_1_n_0\,
I2 => \^p_1_in27_in\,
I3 => \^p_0_in26_in\,
I4 => \^p_1_in25_in\,
I5 => \^p_0_in24_in\,
O => irq_gen_i_2_n_0
);
irq_gen_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irq_gen_i_1_n_0,
Q => irq_gen,
R => \^ss\(0)
);
\mer_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\,
Q => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
R => \^ss\(0)
);
\mer_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_6,
Q => \^p_0_in\,
R => \^ss\(0)
);
\s_axi_rdata_i[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800080008000"
)
port map (
I0 => \^q\(0),
I1 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\,
I2 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\,
I3 => \bus2ip_addr_i_reg[5]\(2),
I4 => \bus2ip_addr_i_reg[5]\(0),
I5 => \bus2ip_addr_i_reg[5]\(1),
O => \s_axi_rdata_i_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_slave_attachment is
port (
p_17_in : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2bus_wrack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic : out STD_LOGIC;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ : out STD_LOGIC;
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ : out STD_LOGIC;
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ : out STD_LOGIC;
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ : out STD_LOGIC;
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ : out STD_LOGIC;
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ : out STD_LOGIC;
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_rdack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic19_out : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ : out STD_LOGIC;
\mer_int_reg[0]\ : out STD_LOGIC;
\mer_int_reg[1]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
ip2bus_wrack_int_d1 : in STD_LOGIC;
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ : in STD_LOGIC;
p_0_in2_in : in STD_LOGIC;
p_0_in5_in : in STD_LOGIC;
p_0_in8_in : in STD_LOGIC;
p_0_in11_in : in STD_LOGIC;
p_0_in14_in : in STD_LOGIC;
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ : in STD_LOGIC;
ip2bus_wrack : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\Douta_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\IPR_GEN.ipr_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\REG_GEN[0].ier_reg[0]\ : in STD_LOGIC;
\REG_GEN[0].isr_reg[0]\ : in STD_LOGIC;
p_0_in28_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_0_in26_in : in STD_LOGIC;
p_1_in27_in : in STD_LOGIC;
p_0_in24_in : in STD_LOGIC;
p_1_in25_in : in STD_LOGIC;
p_0_in22_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_0_in20_in : in STD_LOGIC;
p_1_in21_in : in STD_LOGIC;
p_0_in19_in : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\IVR_GEN.ivr_reg[0]\ : in STD_LOGIC;
\mer_int_reg[0]_0\ : in STD_LOGIC;
\IVR_GEN.ivr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : in STD_LOGIC;
\IVR_GEN.ivr_reg[1]\ : in STD_LOGIC;
\IVR_GEN.ivr_reg[2]\ : in STD_LOGIC;
ip2bus_rdack_int_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\ : in STD_LOGIC;
p_0_in118_in : in STD_LOGIC;
p_0_in107_in : in STD_LOGIC;
p_0_in96_in : in STD_LOGIC;
p_0_in85_in : in STD_LOGIC;
p_0_in74_in : in STD_LOGIC;
p_0_in64_in : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ : in STD_LOGIC;
p_0_in59_in : in STD_LOGIC;
p_0_in57_in : in STD_LOGIC;
p_0_in55_in : in STD_LOGIC;
p_0_in53_in : in STD_LOGIC;
p_0_in51_in : in STD_LOGIC;
p_0_in49_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_slave_attachment : entity is "slave_attachment";
end system_microblaze_0_axi_intc_0_slave_attachment;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal IP2Bus_Data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[5]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[6]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[7]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw_i_reg_n_0 : STD_LOGIC;
signal ip2bus_error : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \s_axi_bresp_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_5_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_6_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \s_axi_rdata_i[2]_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \s_axi_rdata_i[31]_i_4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \s_axi_rdata_i[3]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \s_axi_rdata_i[4]_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \s_axi_rdata_i[5]_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \s_axi_rdata_i[6]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair16";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_axi_bresp(0) <= \^s_axi_bresp\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
I_DECODER: entity work.system_microblaze_0_axi_intc_0_address_decoder
port map (
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ => \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ => \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ => \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ => \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ => \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ => \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\,
D(31 downto 0) => IP2Bus_Data(31 downto 0),
\Douta_reg[31]\(31 downto 0) => \Douta_reg[31]\(31 downto 0),
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Or128_vec2stdlogic => Or128_vec2stdlogic,
Or128_vec2stdlogic19_out => Or128_vec2stdlogic19_out,
Q => start2,
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0\ => \s_axi_rdata_i[0]_i_2_n_0\,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\,
\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]\ => \s_axi_rdata_i[1]_i_2_n_0\,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ => \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\,
\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]\ => \s_axi_rdata_i[2]_i_4_n_0\,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ => \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ => \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ => \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ => \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ => \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ => \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ => \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ => \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ => \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ => \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ => \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\,
\bus2ip_addr_i_reg[2]\ => \s_axi_rdata_i[31]_i_4_n_0\,
\bus2ip_addr_i_reg[3]\ => \s_axi_rdata_i[2]_i_2_n_0\,
\bus2ip_addr_i_reg[3]_0\ => \s_axi_rdata_i[3]_i_2_n_0\,
\bus2ip_addr_i_reg[3]_1\ => \s_axi_rdata_i[4]_i_2_n_0\,
\bus2ip_addr_i_reg[3]_2\ => \s_axi_rdata_i[5]_i_2_n_0\,
\bus2ip_addr_i_reg[3]_3\ => \s_axi_rdata_i[6]_i_2_n_0\,
\bus2ip_addr_i_reg[5]\ => \s_axi_rdata_i[2]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_0\ => \s_axi_rdata_i[3]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_1\ => \s_axi_rdata_i[4]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_2\ => \s_axi_rdata_i[5]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_3\ => \s_axi_rdata_i[6]_i_3_n_0\,
\bus2ip_addr_i_reg[6]\ => \s_axi_rdata_i[31]_i_5_n_0\,
\bus2ip_addr_i_reg[8]\(6 downto 4) => bus2ip_addr(8 downto 6),
\bus2ip_addr_i_reg[8]\(3 downto 0) => \^q\(3 downto 0),
bus2ip_rnw_i_reg => bus2ip_rnw_i_reg_n_0,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_rdack_int_d1 => ip2bus_rdack_int_d1,
ip2bus_rdack_prev2 => ip2bus_rdack_prev2,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int_d1 => ip2bus_wrack_int_d1,
ip2bus_wrack_prev2 => ip2bus_wrack_prev2,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
\mer_int_reg[0]\ => \mer_int_reg[0]\,
\mer_int_reg[0]_0\ => \mer_int_reg[0]_0\,
\mer_int_reg[1]\ => \mer_int_reg[1]\,
p_0_in => p_0_in,
p_0_in107_in => p_0_in107_in,
p_0_in118_in => p_0_in118_in,
p_0_in11_in => p_0_in11_in,
p_0_in14_in => p_0_in14_in,
p_0_in2_in => p_0_in2_in,
p_0_in49_in => p_0_in49_in,
p_0_in51_in => p_0_in51_in,
p_0_in53_in => p_0_in53_in,
p_0_in55_in => p_0_in55_in,
p_0_in57_in => p_0_in57_in,
p_0_in59_in => p_0_in59_in,
p_0_in5_in => p_0_in5_in,
p_0_in64_in => p_0_in64_in,
p_0_in74_in => p_0_in74_in,
p_0_in85_in => p_0_in85_in,
p_0_in8_in => p_0_in8_in,
p_0_in96_in => p_0_in96_in,
p_17_in => p_17_in,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0)
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(3),
O => \bus2ip_addr_i[5]_i_1_n_0\
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(4),
O => \bus2ip_addr_i[6]_i_1_n_0\
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(5),
O => \bus2ip_addr_i[7]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020202"
)
port map (
I0 => s_axi_arvalid,
I1 => state(1),
I2 => state(0),
I3 => s_axi_awvalid,
I4 => s_axi_wvalid,
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(6),
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \^q\(0),
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \^q\(1),
R => rst
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_1_n_0\,
Q => \^q\(2),
R => rst
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[5]_i_1_n_0\,
Q => \^q\(3),
R => rst
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[6]_i_1_n_0\,
Q => bus2ip_addr(6),
R => rst
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[7]_i_1_n_0\,
Q => bus2ip_addr(7),
R => rst
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(8),
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i_i_1_n_0
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i_i_1_n_0,
Q => bus2ip_rnw_i_reg_n_0,
R => rst
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => rst
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => SS(0),
Q => rst,
R => '0'
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => is_read,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I5 => ip2bus_rdack,
O => \^s_axi_arready\
);
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => ip2bus_error,
I1 => state(1),
I2 => state(0),
I3 => \^s_axi_bresp\(0),
O => \s_axi_bresp_i[1]_i_1_n_0\
);
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_bresp_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => rst
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF02FF02FF0200"
)
port map (
I0 => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\,
I1 => \^q\(2),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \s_axi_rdata_i[0]_i_3_n_0\,
I5 => \s_axi_rdata_i[0]_i_4_n_0\,
O => \s_axi_rdata_i[0]_i_2_n_0\
);
\s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8C008000"
)
port map (
I0 => \mer_int_reg[0]_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \IVR_GEN.ivr_reg[0]_0\(0),
O => \s_axi_rdata_i[0]_i_3_n_0\
);
\s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1505110114041000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(0),
I4 => \REG_GEN[0].ier_reg[0]\,
I5 => \REG_GEN[0].isr_reg[0]\,
O => \s_axi_rdata_i[0]_i_4_n_0\
);
\s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF02FF02FF0200"
)
port map (
I0 => p_0_in14_in,
I1 => \^q\(2),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \s_axi_rdata_i[1]_i_3_n_0\,
I5 => \s_axi_rdata_i[1]_i_4_n_0\,
O => \s_axi_rdata_i[1]_i_2_n_0\
);
\s_axi_rdata_i[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8C008000"
)
port map (
I0 => p_0_in,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \IVR_GEN.ivr_reg[1]\,
O => \s_axi_rdata_i[1]_i_3_n_0\
);
\s_axi_rdata_i[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1505110114041000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(1),
I4 => p_0_in28_in,
I5 => p_1_in29_in,
O => \s_axi_rdata_i[1]_i_4_n_0\
);
\s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(2),
I4 => p_0_in26_in,
I5 => p_1_in27_in,
O => \s_axi_rdata_i[2]_i_2_n_0\
);
\s_axi_rdata_i[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \s_axi_rdata_i[2]_i_3_n_0\
);
\s_axi_rdata_i[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00220C0000220000"
)
port map (
I0 => p_0_in11_in,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \IVR_GEN.ivr_reg[2]\,
O => \s_axi_rdata_i[2]_i_4_n_0\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i[31]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"000AC000"
)
port map (
I0 => \^q\(0),
I1 => \IVR_GEN.ivr_reg[0]\,
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(3),
O => \s_axi_rdata_i[31]_i_4_n_0\
);
\s_axi_rdata_i[31]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bus2ip_addr(6),
I1 => bus2ip_addr(8),
I2 => bus2ip_addr(7),
O => \s_axi_rdata_i[31]_i_5_n_0\
);
\s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(3),
I4 => p_0_in24_in,
I5 => p_1_in25_in,
O => \s_axi_rdata_i[3]_i_2_n_0\
);
\s_axi_rdata_i[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => p_0_in8_in,
O => \s_axi_rdata_i[3]_i_3_n_0\
);
\s_axi_rdata_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(4),
I4 => p_0_in22_in,
I5 => p_1_in23_in,
O => \s_axi_rdata_i[4]_i_2_n_0\
);
\s_axi_rdata_i[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => p_0_in5_in,
O => \s_axi_rdata_i[4]_i_3_n_0\
);
\s_axi_rdata_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(5),
I4 => p_0_in20_in,
I5 => p_1_in21_in,
O => \s_axi_rdata_i[5]_i_2_n_0\
);
\s_axi_rdata_i[5]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => p_0_in2_in,
O => \s_axi_rdata_i[5]_i_3_n_0\
);
\s_axi_rdata_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(6),
I4 => p_0_in19_in,
I5 => p_1_in,
O => \s_axi_rdata_i[6]_i_2_n_0\
);
\s_axi_rdata_i[6]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\,
O => \s_axi_rdata_i[6]_i_3_n_0\
);
\s_axi_rdata_i[6]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
O => \s_axi_rdata_i[6]_i_6_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(0),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(10),
Q => s_axi_rdata(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(11),
Q => s_axi_rdata(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(12),
Q => s_axi_rdata(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(13),
Q => s_axi_rdata(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(14),
Q => s_axi_rdata(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(15),
Q => s_axi_rdata(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(16),
Q => s_axi_rdata(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(17),
Q => s_axi_rdata(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(18),
Q => s_axi_rdata(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(19),
Q => s_axi_rdata(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(1),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(20),
Q => s_axi_rdata(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(21),
Q => s_axi_rdata(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(22),
Q => s_axi_rdata(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(23),
Q => s_axi_rdata(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(24),
Q => s_axi_rdata(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(25),
Q => s_axi_rdata(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(26),
Q => s_axi_rdata(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(27),
Q => s_axi_rdata(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(28),
Q => s_axi_rdata(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(29),
Q => s_axi_rdata(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(2),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(30),
Q => s_axi_rdata(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(31),
Q => s_axi_rdata(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(3),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(4),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(5),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(6),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(7),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(8),
Q => s_axi_rdata(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(9),
Q => s_axi_rdata(9),
R => rst
);
\s_axi_rresp_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"070F0F0F"
)
port map (
I0 => s_axi_wstrb(1),
I1 => s_axi_wstrb(2),
I2 => bus2ip_rnw_i_reg_n_0,
I3 => s_axi_wstrb(0),
I4 => s_axi_wstrb(3),
O => ip2bus_error
);
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => ip2bus_error,
Q => s_axi_rresp(0),
R => rst
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => rst
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => is_write_reg_n_0,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I5 => ip2bus_wrack,
O => \^s_axi_wready\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000F0008"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => state(1),
I3 => state(0),
I4 => s_axi_arvalid,
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"55FFE4E4"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => \^s_axi_wready\,
I3 => \state1__2\,
I4 => state(0),
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3AFF3AF0"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state1__2\,
I2 => state(1),
I3 => state(0),
I4 => \state[1]_i_3_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_axi_lite_ipif is
port (
p_17_in : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2bus_wrack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic : out STD_LOGIC;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ : out STD_LOGIC;
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ : out STD_LOGIC;
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ : out STD_LOGIC;
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ : out STD_LOGIC;
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ : out STD_LOGIC;
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ : out STD_LOGIC;
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_rdack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic19_out : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ : out STD_LOGIC;
\mer_int_reg[0]\ : out STD_LOGIC;
\mer_int_reg[1]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
ip2bus_wrack_int_d1 : in STD_LOGIC;
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ : in STD_LOGIC;
p_0_in2_in : in STD_LOGIC;
p_0_in5_in : in STD_LOGIC;
p_0_in8_in : in STD_LOGIC;
p_0_in11_in : in STD_LOGIC;
p_0_in14_in : in STD_LOGIC;
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ : in STD_LOGIC;
ip2bus_wrack : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\Douta_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\IPR_GEN.ipr_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\REG_GEN[0].ier_reg[0]\ : in STD_LOGIC;
\REG_GEN[0].isr_reg[0]\ : in STD_LOGIC;
p_0_in28_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_0_in26_in : in STD_LOGIC;
p_1_in27_in : in STD_LOGIC;
p_0_in24_in : in STD_LOGIC;
p_1_in25_in : in STD_LOGIC;
p_0_in22_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_0_in20_in : in STD_LOGIC;
p_1_in21_in : in STD_LOGIC;
p_0_in19_in : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\IVR_GEN.ivr_reg[0]\ : in STD_LOGIC;
\mer_int_reg[0]_0\ : in STD_LOGIC;
\IVR_GEN.ivr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : in STD_LOGIC;
\IVR_GEN.ivr_reg[1]\ : in STD_LOGIC;
\IVR_GEN.ivr_reg[2]\ : in STD_LOGIC;
ip2bus_rdack_int_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ : in STD_LOGIC;
p_0_in118_in : in STD_LOGIC;
p_0_in107_in : in STD_LOGIC;
p_0_in96_in : in STD_LOGIC;
p_0_in85_in : in STD_LOGIC;
p_0_in74_in : in STD_LOGIC;
p_0_in64_in : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ : in STD_LOGIC;
p_0_in59_in : in STD_LOGIC;
p_0_in57_in : in STD_LOGIC;
p_0_in55_in : in STD_LOGIC;
p_0_in53_in : in STD_LOGIC;
p_0_in51_in : in STD_LOGIC;
p_0_in49_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_microblaze_0_axi_intc_0_axi_lite_ipif;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_microblaze_0_axi_intc_0_slave_attachment
port map (
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ => \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ => \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ => \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ => \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ => \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ => \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\,
\Douta_reg[31]\(31 downto 0) => \Douta_reg[31]\(31 downto 0),
\IPR_GEN.ipr_reg[6]\(6 downto 0) => \IPR_GEN.ipr_reg[6]\(6 downto 0),
\IVR_GEN.ivr_reg[0]\ => \IVR_GEN.ivr_reg[0]\,
\IVR_GEN.ivr_reg[0]_0\(0) => \IVR_GEN.ivr_reg[0]_0\(0),
\IVR_GEN.ivr_reg[1]\ => \IVR_GEN.ivr_reg[1]\,
\IVR_GEN.ivr_reg[2]\ => \IVR_GEN.ivr_reg[2]\,
Or128_vec2stdlogic => Or128_vec2stdlogic,
Or128_vec2stdlogic19_out => Or128_vec2stdlogic19_out,
Q(3 downto 0) => Q(3 downto 0),
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\,
\REG_GEN[0].ier_reg[0]\ => \REG_GEN[0].ier_reg[0]\,
\REG_GEN[0].isr_reg[0]\ => \REG_GEN[0].isr_reg[0]\,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ => \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ => \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ => \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ => \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ => \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ => \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ => Bus_RNW_reg,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ => \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ => \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ => \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ => \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ => \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ => \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\,
SS(0) => SS(0),
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_rdack_int_d1 => ip2bus_rdack_int_d1,
ip2bus_rdack_prev2 => ip2bus_rdack_prev2,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int_d1 => ip2bus_wrack_int_d1,
ip2bus_wrack_prev2 => ip2bus_wrack_prev2,
\mer_int_reg[0]\ => \mer_int_reg[0]\,
\mer_int_reg[0]_0\ => \mer_int_reg[0]_0\,
\mer_int_reg[1]\ => \mer_int_reg[1]\,
p_0_in => p_0_in,
p_0_in107_in => p_0_in107_in,
p_0_in118_in => p_0_in118_in,
p_0_in11_in => p_0_in11_in,
p_0_in14_in => p_0_in14_in,
p_0_in19_in => p_0_in19_in,
p_0_in20_in => p_0_in20_in,
p_0_in22_in => p_0_in22_in,
p_0_in24_in => p_0_in24_in,
p_0_in26_in => p_0_in26_in,
p_0_in28_in => p_0_in28_in,
p_0_in2_in => p_0_in2_in,
p_0_in49_in => p_0_in49_in,
p_0_in51_in => p_0_in51_in,
p_0_in53_in => p_0_in53_in,
p_0_in55_in => p_0_in55_in,
p_0_in57_in => p_0_in57_in,
p_0_in59_in => p_0_in59_in,
p_0_in5_in => p_0_in5_in,
p_0_in64_in => p_0_in64_in,
p_0_in74_in => p_0_in74_in,
p_0_in85_in => p_0_in85_in,
p_0_in8_in => p_0_in8_in,
p_0_in96_in => p_0_in96_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_1_in21_in => p_1_in21_in,
p_1_in23_in => p_1_in23_in,
p_1_in25_in => p_1_in25_in,
p_1_in27_in => p_1_in27_in,
p_1_in29_in => p_1_in29_in,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_axi_intc is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 6 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 );
irq_in : in STD_LOGIC;
interrupt_address_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
processor_ack_out : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute C_ASYNC_INTR : integer;
attribute C_ASYNC_INTR of system_microblaze_0_axi_intc_0_axi_intc : entity is -62;
attribute C_CASCADE_MASTER : integer;
attribute C_CASCADE_MASTER of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_DISABLE_SYNCHRONIZERS : integer;
attribute C_DISABLE_SYNCHRONIZERS of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_ENABLE_ASYNC : integer;
attribute C_ENABLE_ASYNC of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_EN_CASCADE_MODE : integer;
attribute C_EN_CASCADE_MODE of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_microblaze_0_axi_intc_0_axi_intc : entity is "artix7";
attribute C_HAS_CIE : integer;
attribute C_HAS_CIE of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_HAS_FAST : integer;
attribute C_HAS_FAST of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_HAS_ILR : integer;
attribute C_HAS_ILR of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_HAS_IPR : integer;
attribute C_HAS_IPR of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_HAS_IVR : integer;
attribute C_HAS_IVR of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_HAS_SIE : integer;
attribute C_HAS_SIE of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of system_microblaze_0_axi_intc_0_axi_intc : entity is "system_microblaze_0_axi_intc_0";
attribute C_IRQ_ACTIVE : string;
attribute C_IRQ_ACTIVE of system_microblaze_0_axi_intc_0_axi_intc : entity is "1'b1";
attribute C_IRQ_IS_LEVEL : integer;
attribute C_IRQ_IS_LEVEL of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_IVAR_RESET_VALUE : integer;
attribute C_IVAR_RESET_VALUE of system_microblaze_0_axi_intc_0_axi_intc : entity is 16;
attribute C_KIND_OF_EDGE : integer;
attribute C_KIND_OF_EDGE of system_microblaze_0_axi_intc_0_axi_intc : entity is -1;
attribute C_KIND_OF_INTR : integer;
attribute C_KIND_OF_INTR of system_microblaze_0_axi_intc_0_axi_intc : entity is -78;
attribute C_KIND_OF_LVL : integer;
attribute C_KIND_OF_LVL of system_microblaze_0_axi_intc_0_axi_intc : entity is -1;
attribute C_MB_CLK_NOT_CONNECTED : integer;
attribute C_MB_CLK_NOT_CONNECTED of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_NUM_INTR_INPUTS : integer;
attribute C_NUM_INTR_INPUTS of system_microblaze_0_axi_intc_0_axi_intc : entity is 7;
attribute C_NUM_SW_INTR : integer;
attribute C_NUM_SW_INTR of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_NUM_SYNC_FF : integer;
attribute C_NUM_SYNC_FF of system_microblaze_0_axi_intc_0_axi_intc : entity is 2;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_microblaze_0_axi_intc_0_axi_intc : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_microblaze_0_axi_intc_0_axi_intc : entity is 32;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_axi_intc : entity is "axi_intc";
attribute hdl : string;
attribute hdl of system_microblaze_0_axi_intc_0_axi_intc : entity is "VHDL";
attribute imp_netlist : string;
attribute imp_netlist of system_microblaze_0_axi_intc_0_axi_intc : entity is "TRUE";
attribute ip_group : string;
attribute ip_group of system_microblaze_0_axi_intc_0_axi_intc : entity is "LOGICORE";
attribute iptype : string;
attribute iptype of system_microblaze_0_axi_intc_0_axi_intc : entity is "PERIPHERAL";
attribute run_ngcbuild : string;
attribute run_ngcbuild of system_microblaze_0_axi_intc_0_axi_intc : entity is "TRUE";
attribute style : string;
attribute style of system_microblaze_0_axi_intc_0_axi_intc : entity is "HDL";
end system_microblaze_0_axi_intc_0_axi_intc;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_axi_intc is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_37 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_38 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_39 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_40 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_41 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_9 : STD_LOGIC;
signal Douta : STD_LOGIC_VECTOR ( 31 downto 0 );
signal INTC_CORE_I_n_0 : STD_LOGIC;
signal INTC_CORE_I_n_16 : STD_LOGIC;
signal INTC_CORE_I_n_23 : STD_LOGIC;
signal INTC_CORE_I_n_30 : STD_LOGIC;
signal INTC_CORE_I_n_32 : STD_LOGIC;
signal INTC_CORE_I_n_39 : STD_LOGIC;
signal INTC_CORE_I_n_40 : STD_LOGIC;
signal INTC_CORE_I_n_41 : STD_LOGIC;
signal INTC_CORE_I_n_42 : STD_LOGIC;
signal INTC_CORE_I_n_7 : STD_LOGIC;
signal INTC_CORE_I_n_8 : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in\ : STD_LOGIC;
signal Or128_vec2stdlogic : STD_LOGIC;
signal Or128_vec2stdlogic19_out : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 5 downto 2 );
signal bus2ip_wrce : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \bus2ip_wrce__0\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal ip2bus_rdack : STD_LOGIC;
signal ip2bus_rdack_int_d1 : STD_LOGIC;
signal ip2bus_rdack_prev2 : STD_LOGIC;
signal ip2bus_wrack : STD_LOGIC;
signal ip2bus_wrack_int_d1 : STD_LOGIC;
signal ip2bus_wrack_prev2 : STD_LOGIC;
signal ipr : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_0_in : STD_LOGIC;
signal p_0_in107_in : STD_LOGIC;
signal p_0_in118_in : STD_LOGIC;
signal p_0_in11_in : STD_LOGIC;
signal p_0_in14_in : STD_LOGIC;
signal p_0_in19_in : STD_LOGIC;
signal p_0_in20_in : STD_LOGIC;
signal p_0_in22_in : STD_LOGIC;
signal p_0_in24_in : STD_LOGIC;
signal p_0_in26_in : STD_LOGIC;
signal p_0_in28_in : STD_LOGIC;
signal p_0_in2_in : STD_LOGIC;
signal p_0_in49_in : STD_LOGIC;
signal p_0_in51_in : STD_LOGIC;
signal p_0_in53_in : STD_LOGIC;
signal p_0_in55_in : STD_LOGIC;
signal p_0_in57_in : STD_LOGIC;
signal p_0_in59_in : STD_LOGIC;
signal p_0_in5_in : STD_LOGIC;
signal p_0_in64_in : STD_LOGIC;
signal p_0_in74_in : STD_LOGIC;
signal p_0_in85_in : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
signal p_0_in96_in : STD_LOGIC;
signal p_0_in_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_1_in21_in : STD_LOGIC;
signal p_1_in23_in : STD_LOGIC;
signal p_1_in25_in : STD_LOGIC;
signal p_1_in27_in : STD_LOGIC;
signal p_1_in29_in : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
processor_ack_out(1) <= \<const0>\;
processor_ack_out(0) <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \^s_axi_bresp\(1);
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \^s_axi_rresp\(1);
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_microblaze_0_axi_intc_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ => AXI_LITE_IPIF_I_n_33,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ => INTC_CORE_I_n_23,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ => AXI_LITE_IPIF_I_n_34,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ => AXI_LITE_IPIF_I_n_35,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ => AXI_LITE_IPIF_I_n_36,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ => AXI_LITE_IPIF_I_n_37,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ => AXI_LITE_IPIF_I_n_38,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ => AXI_LITE_IPIF_I_n_39,
\Douta_reg[31]\(31 downto 0) => Douta(31 downto 0),
\IPR_GEN.ipr_reg[6]\(6 downto 0) => ipr(6 downto 0),
\IVR_GEN.ivr_reg[0]\ => INTC_CORE_I_n_39,
\IVR_GEN.ivr_reg[0]_0\(0) => INTC_CORE_I_n_40,
\IVR_GEN.ivr_reg[1]\ => INTC_CORE_I_n_41,
\IVR_GEN.ivr_reg[2]\ => INTC_CORE_I_n_42,
Or128_vec2stdlogic => Or128_vec2stdlogic,
Or128_vec2stdlogic19_out => Or128_vec2stdlogic19_out,
Q(3 downto 0) => bus2ip_addr(5 downto 2),
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ => AXI_LITE_IPIF_I_n_14,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ => INTC_CORE_I_n_0,
\REG_GEN[0].ier_reg[0]\ => INTC_CORE_I_n_8,
\REG_GEN[0].isr_reg[0]\ => INTC_CORE_I_n_32,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ => AXI_LITE_IPIF_I_n_13,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ => AXI_LITE_IPIF_I_n_12,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ => AXI_LITE_IPIF_I_n_11,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ => AXI_LITE_IPIF_I_n_10,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ => AXI_LITE_IPIF_I_n_9,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ => AXI_LITE_IPIF_I_n_8,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ => INTC_CORE_I_n_7,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ => AXI_LITE_IPIF_I_n_26,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ => INTC_CORE_I_n_16,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ => AXI_LITE_IPIF_I_n_27,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ => AXI_LITE_IPIF_I_n_28,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ => AXI_LITE_IPIF_I_n_29,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ => AXI_LITE_IPIF_I_n_30,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ => AXI_LITE_IPIF_I_n_31,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ => AXI_LITE_IPIF_I_n_32,
SS(0) => p_0_in,
bus2ip_wrce(1) => bus2ip_wrce(8),
bus2ip_wrce(0) => bus2ip_wrce(0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(14),
ip2bus_rdack => ip2bus_rdack,
ip2bus_rdack_int_d1 => ip2bus_rdack_int_d1,
ip2bus_rdack_prev2 => ip2bus_rdack_prev2,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int_d1 => ip2bus_wrack_int_d1,
ip2bus_wrack_prev2 => ip2bus_wrack_prev2,
\mer_int_reg[0]\ => AXI_LITE_IPIF_I_n_40,
\mer_int_reg[0]_0\ => INTC_CORE_I_n_30,
\mer_int_reg[1]\ => AXI_LITE_IPIF_I_n_41,
p_0_in => p_0_in_0,
p_0_in107_in => p_0_in107_in,
p_0_in118_in => p_0_in118_in,
p_0_in11_in => p_0_in11_in,
p_0_in14_in => p_0_in14_in,
p_0_in19_in => p_0_in19_in,
p_0_in20_in => p_0_in20_in,
p_0_in22_in => p_0_in22_in,
p_0_in24_in => p_0_in24_in,
p_0_in26_in => p_0_in26_in,
p_0_in28_in => p_0_in28_in,
p_0_in2_in => p_0_in2_in,
p_0_in49_in => p_0_in49_in,
p_0_in51_in => p_0_in51_in,
p_0_in53_in => p_0_in53_in,
p_0_in55_in => p_0_in55_in,
p_0_in57_in => p_0_in57_in,
p_0_in59_in => p_0_in59_in,
p_0_in5_in => p_0_in5_in,
p_0_in64_in => p_0_in64_in,
p_0_in74_in => p_0_in74_in,
p_0_in85_in => p_0_in85_in,
p_0_in8_in => p_0_in8_in,
p_0_in96_in => p_0_in96_in,
p_17_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in\,
p_1_in => p_1_in,
p_1_in21_in => p_1_in21_in,
p_1_in23_in => p_1_in23_in,
p_1_in25_in => p_1_in25_in,
p_1_in27_in => p_1_in27_in,
p_1_in29_in => p_1_in29_in,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(1),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => \^s_axi_rresp\(1),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
INTC_CORE_I: entity work.system_microblaze_0_axi_intc_0_intc_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_26,
Bus_RNW_reg_reg_0 => AXI_LITE_IPIF_I_n_27,
Bus_RNW_reg_reg_1 => AXI_LITE_IPIF_I_n_28,
Bus_RNW_reg_reg_10 => AXI_LITE_IPIF_I_n_11,
Bus_RNW_reg_reg_11 => AXI_LITE_IPIF_I_n_10,
Bus_RNW_reg_reg_12 => AXI_LITE_IPIF_I_n_9,
Bus_RNW_reg_reg_13 => AXI_LITE_IPIF_I_n_8,
Bus_RNW_reg_reg_2 => AXI_LITE_IPIF_I_n_29,
Bus_RNW_reg_reg_3 => AXI_LITE_IPIF_I_n_30,
Bus_RNW_reg_reg_4 => AXI_LITE_IPIF_I_n_31,
Bus_RNW_reg_reg_5 => AXI_LITE_IPIF_I_n_32,
Bus_RNW_reg_reg_6 => AXI_LITE_IPIF_I_n_41,
Bus_RNW_reg_reg_7 => AXI_LITE_IPIF_I_n_14,
Bus_RNW_reg_reg_8 => AXI_LITE_IPIF_I_n_13,
Bus_RNW_reg_reg_9 => AXI_LITE_IPIF_I_n_12,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ => AXI_LITE_IPIF_I_n_33,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0\ => AXI_LITE_IPIF_I_n_34,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0\ => AXI_LITE_IPIF_I_n_35,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0\ => AXI_LITE_IPIF_I_n_36,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0\ => AXI_LITE_IPIF_I_n_37,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0\ => AXI_LITE_IPIF_I_n_38,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0\ => AXI_LITE_IPIF_I_n_39,
Douta(31 downto 0) => Douta(31 downto 0),
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ => AXI_LITE_IPIF_I_n_40,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0\ => INTC_CORE_I_n_41,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0\ => INTC_CORE_I_n_30,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1\ => INTC_CORE_I_n_42,
\IVR_GEN.ivr_reg[1]_0\ => INTC_CORE_I_n_8,
\IVR_GEN.ivr_reg[1]_1\ => INTC_CORE_I_n_32,
Q(0) => INTC_CORE_I_n_40,
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0\ => INTC_CORE_I_n_0,
\REG_GEN[0].ier_reg[0]_0\ => INTC_CORE_I_n_16,
\REG_GEN[0].ier_reg[0]_1\ => INTC_CORE_I_n_23,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0\ => INTC_CORE_I_n_7,
SS(0) => p_0_in,
\bus2ip_addr_i_reg[5]\(3 downto 0) => bus2ip_addr(5 downto 2),
bus2ip_wrce(1) => bus2ip_wrce(8),
bus2ip_wrce(0) => bus2ip_wrce(0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(14),
interrupt_address(31 downto 0) => interrupt_address(31 downto 0),
intr(6 downto 0) => intr(6 downto 0),
irq => irq,
p_0_in => p_0_in_0,
p_0_in107_in => p_0_in107_in,
p_0_in118_in => p_0_in118_in,
p_0_in11_in => p_0_in11_in,
p_0_in14_in => p_0_in14_in,
p_0_in19_in => p_0_in19_in,
p_0_in20_in => p_0_in20_in,
p_0_in22_in => p_0_in22_in,
p_0_in24_in => p_0_in24_in,
p_0_in26_in => p_0_in26_in,
p_0_in28_in => p_0_in28_in,
p_0_in2_in => p_0_in2_in,
p_0_in49_in => p_0_in49_in,
p_0_in51_in => p_0_in51_in,
p_0_in53_in => p_0_in53_in,
p_0_in55_in => p_0_in55_in,
p_0_in57_in => p_0_in57_in,
p_0_in59_in => p_0_in59_in,
p_0_in5_in => p_0_in5_in,
p_0_in64_in => p_0_in64_in,
p_0_in74_in => p_0_in74_in,
p_0_in85_in => p_0_in85_in,
p_0_in8_in => p_0_in8_in,
p_0_in96_in => p_0_in96_in,
p_17_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in\,
p_1_in => p_1_in,
p_1_in21_in => p_1_in21_in,
p_1_in23_in => p_1_in23_in,
p_1_in25_in => p_1_in25_in,
p_1_in27_in => p_1_in27_in,
p_1_in29_in => p_1_in29_in,
processor_ack(1 downto 0) => processor_ack(1 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[3]\ => INTC_CORE_I_n_39,
\s_axi_rdata_i_reg[6]\(6 downto 0) => ipr(6 downto 0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0)
);
ip2bus_rdack_int_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Or128_vec2stdlogic19_out,
Q => ip2bus_rdack_int_d1,
R => p_0_in
);
ip2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_prev2,
Q => ip2bus_rdack,
R => p_0_in
);
ip2bus_wrack_int_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Or128_vec2stdlogic,
Q => ip2bus_wrack_int_d1,
R => p_0_in
);
ip2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_prev2,
Q => ip2bus_wrack,
R => p_0_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 6 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_microblaze_0_axi_intc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_microblaze_0_axi_intc_0 : entity is "system_microblaze_0_axi_intc_0,axi_intc,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_microblaze_0_axi_intc_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_microblaze_0_axi_intc_0 : entity is "axi_intc,Vivado 2016.4";
end system_microblaze_0_axi_intc_0;
architecture STRUCTURE of system_microblaze_0_axi_intc_0 is
signal NLW_U0_processor_ack_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ASYNC_INTR : integer;
attribute C_ASYNC_INTR of U0 : label is -62;
attribute C_CASCADE_MASTER : integer;
attribute C_CASCADE_MASTER of U0 : label is 0;
attribute C_DISABLE_SYNCHRONIZERS : integer;
attribute C_DISABLE_SYNCHRONIZERS of U0 : label is 0;
attribute C_ENABLE_ASYNC : integer;
attribute C_ENABLE_ASYNC of U0 : label is 0;
attribute C_EN_CASCADE_MODE : integer;
attribute C_EN_CASCADE_MODE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_CIE : integer;
attribute C_HAS_CIE of U0 : label is 1;
attribute C_HAS_FAST : integer;
attribute C_HAS_FAST of U0 : label is 1;
attribute C_HAS_ILR : integer;
attribute C_HAS_ILR of U0 : label is 0;
attribute C_HAS_IPR : integer;
attribute C_HAS_IPR of U0 : label is 1;
attribute C_HAS_IVR : integer;
attribute C_HAS_IVR of U0 : label is 1;
attribute C_HAS_SIE : integer;
attribute C_HAS_SIE of U0 : label is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of U0 : label is "system_microblaze_0_axi_intc_0";
attribute C_IRQ_ACTIVE : string;
attribute C_IRQ_ACTIVE of U0 : label is "1'b1";
attribute C_IRQ_IS_LEVEL : integer;
attribute C_IRQ_IS_LEVEL of U0 : label is 1;
attribute C_IVAR_RESET_VALUE : integer;
attribute C_IVAR_RESET_VALUE of U0 : label is 16;
attribute C_KIND_OF_EDGE : integer;
attribute C_KIND_OF_EDGE of U0 : label is -1;
attribute C_KIND_OF_INTR : integer;
attribute C_KIND_OF_INTR of U0 : label is -78;
attribute C_KIND_OF_LVL : integer;
attribute C_KIND_OF_LVL of U0 : label is -1;
attribute C_MB_CLK_NOT_CONNECTED : integer;
attribute C_MB_CLK_NOT_CONNECTED of U0 : label is 1;
attribute C_NUM_INTR_INPUTS : integer;
attribute C_NUM_INTR_INPUTS of U0 : label is 7;
attribute C_NUM_SW_INTR : integer;
attribute C_NUM_SW_INTR of U0 : label is 0;
attribute C_NUM_SYNC_FF : integer;
attribute C_NUM_SYNC_FF of U0 : label is 2;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute hdl : string;
attribute hdl of U0 : label is "VHDL";
attribute imp_netlist : string;
attribute imp_netlist of U0 : label is "TRUE";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute iptype : string;
attribute iptype of U0 : label is "PERIPHERAL";
attribute run_ngcbuild : string;
attribute run_ngcbuild of U0 : label is "TRUE";
attribute style : string;
attribute style of U0 : label is "HDL";
begin
U0: entity work.system_microblaze_0_axi_intc_0_axi_intc
port map (
interrupt_address(31 downto 0) => interrupt_address(31 downto 0),
interrupt_address_in(31 downto 0) => B"00000000000000000000000000000000",
intr(6 downto 0) => intr(6 downto 0),
irq => irq,
irq_in => '0',
processor_ack(1 downto 0) => processor_ack(1 downto 0),
processor_ack_out(1 downto 0) => NLW_U0_processor_ack_out_UNCONNECTED(1 downto 0),
processor_clk => processor_clk,
processor_rst => processor_rst,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
apache-2.0
|
052bc7c2480997c9747af19c14c1d32c
| 0.533643 | 2.462555 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_ilmb_bram_if_cntlr_0/system_ilmb_bram_if_cntlr_0_sim_netlist.vhdl
| 1 | 25,450 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:45:39 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_ilmb_bram_if_cntlr_0/system_ilmb_bram_if_cntlr_0_sim_netlist.vhdl
-- Design : system_ilmb_bram_if_cntlr_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
LMB1_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB1_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB1_AddrStrobe : in STD_LOGIC;
LMB1_ReadStrobe : in STD_LOGIC;
LMB1_WriteStrobe : in STD_LOGIC;
LMB1_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl1_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl1_Ready : out STD_LOGIC;
Sl1_Wait : out STD_LOGIC;
Sl1_UE : out STD_LOGIC;
Sl1_CE : out STD_LOGIC;
LMB2_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB2_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB2_AddrStrobe : in STD_LOGIC;
LMB2_ReadStrobe : in STD_LOGIC;
LMB2_WriteStrobe : in STD_LOGIC;
LMB2_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl2_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl2_Ready : out STD_LOGIC;
Sl2_Wait : out STD_LOGIC;
Sl2_UE : out STD_LOGIC;
Sl2_CE : out STD_LOGIC;
LMB3_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB3_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB3_AddrStrobe : in STD_LOGIC;
LMB3_ReadStrobe : in STD_LOGIC;
LMB3_WriteStrobe : in STD_LOGIC;
LMB3_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl3_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl3_Ready : out STD_LOGIC;
Sl3_Wait : out STD_LOGIC;
Sl3_UE : out STD_LOGIC;
Sl3_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 );
S_AXI_CTRL_ACLK : in STD_LOGIC;
S_AXI_CTRL_ARESETN : in STD_LOGIC;
S_AXI_CTRL_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_AWVALID : in STD_LOGIC;
S_AXI_CTRL_AWREADY : out STD_LOGIC;
S_AXI_CTRL_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_CTRL_WVALID : in STD_LOGIC;
S_AXI_CTRL_WREADY : out STD_LOGIC;
S_AXI_CTRL_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_BVALID : out STD_LOGIC;
S_AXI_CTRL_BREADY : in STD_LOGIC;
S_AXI_CTRL_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_ARVALID : in STD_LOGIC;
S_AXI_CTRL_ARREADY : out STD_LOGIC;
S_AXI_CTRL_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_RVALID : out STD_LOGIC;
S_AXI_CTRL_RREADY : in STD_LOGIC;
UE : out STD_LOGIC;
CE : out STD_LOGIC;
Interrupt : out STD_LOGIC
);
attribute C_BASEADDR : string;
attribute C_BASEADDR of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_BRAM_AWIDTH : integer;
attribute C_BRAM_AWIDTH of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_CE_COUNTER_WIDTH : integer;
attribute C_CE_COUNTER_WIDTH of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_CE_FAILING_REGISTERS : integer;
attribute C_CE_FAILING_REGISTERS of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC : integer;
attribute C_ECC of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC_ONOFF_REGISTER : integer;
attribute C_ECC_ONOFF_REGISTER of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 1;
attribute C_ECC_STATUS_REGISTERS : integer;
attribute C_ECC_STATUS_REGISTERS of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "artix7";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_HIGHADDR : string;
attribute C_HIGHADDR of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000000000000111111111111111";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_MASK : string;
attribute C_MASK of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000010000000000000000000000000000000";
attribute C_MASK1 : string;
attribute C_MASK1 of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK2 : string;
attribute C_MASK2 of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK3 : string;
attribute C_MASK3 of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_NUM_LMB : integer;
attribute C_NUM_LMB of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 1;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_S_AXI_CTRL_BASEADDR : string;
attribute C_S_AXI_CTRL_BASEADDR of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "32'b11111111111111111111111111111111";
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 32;
attribute C_S_AXI_CTRL_HIGHADDR : string;
attribute C_S_AXI_CTRL_HIGHADDR of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "32'b00000000000000000000000000000000";
attribute C_UE_FAILING_REGISTERS : integer;
attribute C_UE_FAILING_REGISTERS of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is 2;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr : entity is "lmb_bram_if_cntlr";
end system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr;
architecture STRUCTURE of system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr is
signal \<const0>\ : STD_LOGIC;
signal \^bram_din_a\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^lmb_abus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^lmb_addrstrobe\ : STD_LOGIC;
signal \^lmb_clk\ : STD_LOGIC;
signal \^lmb_writedbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \No_ECC.Sl_Rdy_i_1_n_0\ : STD_LOGIC;
signal \No_ECC.lmb_as_i_1_n_0\ : STD_LOGIC;
signal Sl_Rdy : STD_LOGIC;
signal lmb_as : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \BRAM_WEN_A[0]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \BRAM_WEN_A[1]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \BRAM_WEN_A[2]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \BRAM_WEN_A[3]_INST_0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \No_ECC.Sl_Rdy_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \No_ECC.lmb_as_i_1\ : label is "soft_lutpair2";
begin
BRAM_Addr_A(0 to 31) <= \^lmb_abus\(0 to 31);
BRAM_Clk_A <= \^lmb_clk\;
BRAM_Dout_A(0 to 31) <= \^lmb_writedbus\(0 to 31);
BRAM_EN_A <= \^lmb_addrstrobe\;
BRAM_Rst_A <= \<const0>\;
CE <= \<const0>\;
Interrupt <= \<const0>\;
S_AXI_CTRL_ARREADY <= \<const0>\;
S_AXI_CTRL_AWREADY <= \<const0>\;
S_AXI_CTRL_BRESP(1) <= \<const0>\;
S_AXI_CTRL_BRESP(0) <= \<const0>\;
S_AXI_CTRL_BVALID <= \<const0>\;
S_AXI_CTRL_RDATA(31) <= \<const0>\;
S_AXI_CTRL_RDATA(30) <= \<const0>\;
S_AXI_CTRL_RDATA(29) <= \<const0>\;
S_AXI_CTRL_RDATA(28) <= \<const0>\;
S_AXI_CTRL_RDATA(27) <= \<const0>\;
S_AXI_CTRL_RDATA(26) <= \<const0>\;
S_AXI_CTRL_RDATA(25) <= \<const0>\;
S_AXI_CTRL_RDATA(24) <= \<const0>\;
S_AXI_CTRL_RDATA(23) <= \<const0>\;
S_AXI_CTRL_RDATA(22) <= \<const0>\;
S_AXI_CTRL_RDATA(21) <= \<const0>\;
S_AXI_CTRL_RDATA(20) <= \<const0>\;
S_AXI_CTRL_RDATA(19) <= \<const0>\;
S_AXI_CTRL_RDATA(18) <= \<const0>\;
S_AXI_CTRL_RDATA(17) <= \<const0>\;
S_AXI_CTRL_RDATA(16) <= \<const0>\;
S_AXI_CTRL_RDATA(15) <= \<const0>\;
S_AXI_CTRL_RDATA(14) <= \<const0>\;
S_AXI_CTRL_RDATA(13) <= \<const0>\;
S_AXI_CTRL_RDATA(12) <= \<const0>\;
S_AXI_CTRL_RDATA(11) <= \<const0>\;
S_AXI_CTRL_RDATA(10) <= \<const0>\;
S_AXI_CTRL_RDATA(9) <= \<const0>\;
S_AXI_CTRL_RDATA(8) <= \<const0>\;
S_AXI_CTRL_RDATA(7) <= \<const0>\;
S_AXI_CTRL_RDATA(6) <= \<const0>\;
S_AXI_CTRL_RDATA(5) <= \<const0>\;
S_AXI_CTRL_RDATA(4) <= \<const0>\;
S_AXI_CTRL_RDATA(3) <= \<const0>\;
S_AXI_CTRL_RDATA(2) <= \<const0>\;
S_AXI_CTRL_RDATA(1) <= \<const0>\;
S_AXI_CTRL_RDATA(0) <= \<const0>\;
S_AXI_CTRL_RRESP(1) <= \<const0>\;
S_AXI_CTRL_RRESP(0) <= \<const0>\;
S_AXI_CTRL_RVALID <= \<const0>\;
S_AXI_CTRL_WREADY <= \<const0>\;
Sl1_CE <= \<const0>\;
Sl1_DBus(0) <= \<const0>\;
Sl1_DBus(1) <= \<const0>\;
Sl1_DBus(2) <= \<const0>\;
Sl1_DBus(3) <= \<const0>\;
Sl1_DBus(4) <= \<const0>\;
Sl1_DBus(5) <= \<const0>\;
Sl1_DBus(6) <= \<const0>\;
Sl1_DBus(7) <= \<const0>\;
Sl1_DBus(8) <= \<const0>\;
Sl1_DBus(9) <= \<const0>\;
Sl1_DBus(10) <= \<const0>\;
Sl1_DBus(11) <= \<const0>\;
Sl1_DBus(12) <= \<const0>\;
Sl1_DBus(13) <= \<const0>\;
Sl1_DBus(14) <= \<const0>\;
Sl1_DBus(15) <= \<const0>\;
Sl1_DBus(16) <= \<const0>\;
Sl1_DBus(17) <= \<const0>\;
Sl1_DBus(18) <= \<const0>\;
Sl1_DBus(19) <= \<const0>\;
Sl1_DBus(20) <= \<const0>\;
Sl1_DBus(21) <= \<const0>\;
Sl1_DBus(22) <= \<const0>\;
Sl1_DBus(23) <= \<const0>\;
Sl1_DBus(24) <= \<const0>\;
Sl1_DBus(25) <= \<const0>\;
Sl1_DBus(26) <= \<const0>\;
Sl1_DBus(27) <= \<const0>\;
Sl1_DBus(28) <= \<const0>\;
Sl1_DBus(29) <= \<const0>\;
Sl1_DBus(30) <= \<const0>\;
Sl1_DBus(31) <= \<const0>\;
Sl1_Ready <= \<const0>\;
Sl1_UE <= \<const0>\;
Sl1_Wait <= \<const0>\;
Sl2_CE <= \<const0>\;
Sl2_DBus(0) <= \<const0>\;
Sl2_DBus(1) <= \<const0>\;
Sl2_DBus(2) <= \<const0>\;
Sl2_DBus(3) <= \<const0>\;
Sl2_DBus(4) <= \<const0>\;
Sl2_DBus(5) <= \<const0>\;
Sl2_DBus(6) <= \<const0>\;
Sl2_DBus(7) <= \<const0>\;
Sl2_DBus(8) <= \<const0>\;
Sl2_DBus(9) <= \<const0>\;
Sl2_DBus(10) <= \<const0>\;
Sl2_DBus(11) <= \<const0>\;
Sl2_DBus(12) <= \<const0>\;
Sl2_DBus(13) <= \<const0>\;
Sl2_DBus(14) <= \<const0>\;
Sl2_DBus(15) <= \<const0>\;
Sl2_DBus(16) <= \<const0>\;
Sl2_DBus(17) <= \<const0>\;
Sl2_DBus(18) <= \<const0>\;
Sl2_DBus(19) <= \<const0>\;
Sl2_DBus(20) <= \<const0>\;
Sl2_DBus(21) <= \<const0>\;
Sl2_DBus(22) <= \<const0>\;
Sl2_DBus(23) <= \<const0>\;
Sl2_DBus(24) <= \<const0>\;
Sl2_DBus(25) <= \<const0>\;
Sl2_DBus(26) <= \<const0>\;
Sl2_DBus(27) <= \<const0>\;
Sl2_DBus(28) <= \<const0>\;
Sl2_DBus(29) <= \<const0>\;
Sl2_DBus(30) <= \<const0>\;
Sl2_DBus(31) <= \<const0>\;
Sl2_Ready <= \<const0>\;
Sl2_UE <= \<const0>\;
Sl2_Wait <= \<const0>\;
Sl3_CE <= \<const0>\;
Sl3_DBus(0) <= \<const0>\;
Sl3_DBus(1) <= \<const0>\;
Sl3_DBus(2) <= \<const0>\;
Sl3_DBus(3) <= \<const0>\;
Sl3_DBus(4) <= \<const0>\;
Sl3_DBus(5) <= \<const0>\;
Sl3_DBus(6) <= \<const0>\;
Sl3_DBus(7) <= \<const0>\;
Sl3_DBus(8) <= \<const0>\;
Sl3_DBus(9) <= \<const0>\;
Sl3_DBus(10) <= \<const0>\;
Sl3_DBus(11) <= \<const0>\;
Sl3_DBus(12) <= \<const0>\;
Sl3_DBus(13) <= \<const0>\;
Sl3_DBus(14) <= \<const0>\;
Sl3_DBus(15) <= \<const0>\;
Sl3_DBus(16) <= \<const0>\;
Sl3_DBus(17) <= \<const0>\;
Sl3_DBus(18) <= \<const0>\;
Sl3_DBus(19) <= \<const0>\;
Sl3_DBus(20) <= \<const0>\;
Sl3_DBus(21) <= \<const0>\;
Sl3_DBus(22) <= \<const0>\;
Sl3_DBus(23) <= \<const0>\;
Sl3_DBus(24) <= \<const0>\;
Sl3_DBus(25) <= \<const0>\;
Sl3_DBus(26) <= \<const0>\;
Sl3_DBus(27) <= \<const0>\;
Sl3_DBus(28) <= \<const0>\;
Sl3_DBus(29) <= \<const0>\;
Sl3_DBus(30) <= \<const0>\;
Sl3_DBus(31) <= \<const0>\;
Sl3_Ready <= \<const0>\;
Sl3_UE <= \<const0>\;
Sl3_Wait <= \<const0>\;
Sl_CE <= \<const0>\;
Sl_DBus(0 to 31) <= \^bram_din_a\(0 to 31);
Sl_UE <= \<const0>\;
Sl_Wait <= \<const0>\;
UE <= \<const0>\;
\^bram_din_a\(0 to 31) <= BRAM_Din_A(0 to 31);
\^lmb_abus\(0 to 31) <= LMB_ABus(0 to 31);
\^lmb_addrstrobe\ <= LMB_AddrStrobe;
\^lmb_clk\ <= LMB_Clk;
\^lmb_writedbus\(0 to 31) <= LMB_WriteDBus(0 to 31);
\BRAM_WEN_A[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => LMB_WriteStrobe,
I1 => \^lmb_abus\(0),
I2 => LMB_BE(0),
O => BRAM_WEN_A(0)
);
\BRAM_WEN_A[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^lmb_abus\(0),
I1 => LMB_WriteStrobe,
I2 => LMB_BE(1),
O => BRAM_WEN_A(1)
);
\BRAM_WEN_A[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^lmb_abus\(0),
I1 => LMB_WriteStrobe,
I2 => LMB_BE(2),
O => BRAM_WEN_A(2)
);
\BRAM_WEN_A[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^lmb_abus\(0),
I1 => LMB_WriteStrobe,
I2 => LMB_BE(3),
O => BRAM_WEN_A(3)
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\No_ECC.Sl_Rdy_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^lmb_abus\(0),
I1 => LMB_Rst,
O => \No_ECC.Sl_Rdy_i_1_n_0\
);
\No_ECC.Sl_Rdy_reg\: unisim.vcomponents.FDRE
port map (
C => \^lmb_clk\,
CE => '1',
D => \No_ECC.Sl_Rdy_i_1_n_0\,
Q => Sl_Rdy,
R => '0'
);
\No_ECC.lmb_as_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^lmb_addrstrobe\,
I1 => LMB_Rst,
O => \No_ECC.lmb_as_i_1_n_0\
);
\No_ECC.lmb_as_reg\: unisim.vcomponents.FDRE
port map (
C => \^lmb_clk\,
CE => '1',
D => \No_ECC.lmb_as_i_1_n_0\,
Q => lmb_as,
R => '0'
);
Sl_Ready_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => Sl_Rdy,
I1 => lmb_as,
O => Sl_Ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ilmb_bram_if_cntlr_0 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ilmb_bram_if_cntlr_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ilmb_bram_if_cntlr_0 : entity is "system_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ilmb_bram_if_cntlr_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ilmb_bram_if_cntlr_0 : entity is "lmb_bram_if_cntlr,Vivado 2016.4";
end system_ilmb_bram_if_cntlr_0;
architecture STRUCTURE of system_ilmb_bram_if_cntlr_0 is
signal NLW_U0_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl1_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl2_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_CE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_Ready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_Sl3_Wait_UNCONNECTED : STD_LOGIC;
signal NLW_U0_UE_UNCONNECTED : STD_LOGIC;
signal NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_Sl1_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_Sl2_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
signal NLW_U0_Sl3_DBus_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
attribute C_BASEADDR : string;
attribute C_BASEADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute C_BRAM_AWIDTH : integer;
attribute C_BRAM_AWIDTH of U0 : label is 32;
attribute C_CE_COUNTER_WIDTH : integer;
attribute C_CE_COUNTER_WIDTH of U0 : label is 0;
attribute C_CE_FAILING_REGISTERS : integer;
attribute C_CE_FAILING_REGISTERS of U0 : label is 0;
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_REGISTER : integer;
attribute C_ECC_ONOFF_REGISTER of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 1;
attribute C_ECC_STATUS_REGISTERS : integer;
attribute C_ECC_STATUS_REGISTERS of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_HIGHADDR : string;
attribute C_HIGHADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000111111111111111";
attribute C_INTERCONNECT : integer;
attribute C_INTERCONNECT of U0 : label is 0;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of U0 : label is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of U0 : label is 32;
attribute C_MASK : string;
attribute C_MASK of U0 : label is "64'b0000000000000000000000000000000010000000000000000000000000000000";
attribute C_MASK1 : string;
attribute C_MASK1 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK2 : string;
attribute C_MASK2 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_MASK3 : string;
attribute C_MASK3 of U0 : label is "64'b0000000000000000000000000000000000000000100000000000000000000000";
attribute C_NUM_LMB : integer;
attribute C_NUM_LMB of U0 : label is 1;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_BASEADDR : string;
attribute C_S_AXI_CTRL_BASEADDR of U0 : label is "32'b11111111111111111111111111111111";
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_HIGHADDR : string;
attribute C_S_AXI_CTRL_HIGHADDR of U0 : label is "32'b00000000000000000000000000000000";
attribute C_UE_FAILING_REGISTERS : integer;
attribute C_UE_FAILING_REGISTERS of U0 : label is 0;
attribute C_WRITE_ACCESS : integer;
attribute C_WRITE_ACCESS of U0 : label is 2;
begin
U0: entity work.system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr
port map (
BRAM_Addr_A(0 to 31) => BRAM_Addr_A(0 to 31),
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Din_A(0 to 31) => BRAM_Din_A(0 to 31),
BRAM_Dout_A(0 to 31) => BRAM_Dout_A(0 to 31),
BRAM_EN_A => BRAM_EN_A,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_WEN_A(0 to 3) => BRAM_WEN_A(0 to 3),
CE => NLW_U0_CE_UNCONNECTED,
Interrupt => NLW_U0_Interrupt_UNCONNECTED,
LMB1_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB1_AddrStrobe => '0',
LMB1_BE(0 to 3) => B"0000",
LMB1_ReadStrobe => '0',
LMB1_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB1_WriteStrobe => '0',
LMB2_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB2_AddrStrobe => '0',
LMB2_BE(0 to 3) => B"0000",
LMB2_ReadStrobe => '0',
LMB2_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB2_WriteStrobe => '0',
LMB3_ABus(0 to 31) => B"00000000000000000000000000000000",
LMB3_AddrStrobe => '0',
LMB3_BE(0 to 3) => B"0000",
LMB3_ReadStrobe => '0',
LMB3_WriteDBus(0 to 31) => B"00000000000000000000000000000000",
LMB3_WriteStrobe => '0',
LMB_ABus(0 to 31) => LMB_ABus(0 to 31),
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_BE(0 to 3) => LMB_BE(0 to 3),
LMB_Clk => LMB_Clk,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_Rst => LMB_Rst,
LMB_WriteDBus(0 to 31) => LMB_WriteDBus(0 to 31),
LMB_WriteStrobe => LMB_WriteStrobe,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_ARREADY => NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED,
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_AWREADY => NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED,
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_BRESP(1 downto 0) => NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED(1 downto 0),
S_AXI_CTRL_BVALID => NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED,
S_AXI_CTRL_RDATA(31 downto 0) => NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED(31 downto 0),
S_AXI_CTRL_RREADY => '0',
S_AXI_CTRL_RRESP(1 downto 0) => NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED(1 downto 0),
S_AXI_CTRL_RVALID => NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED,
S_AXI_CTRL_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_CTRL_WREADY => NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED,
S_AXI_CTRL_WSTRB(3 downto 0) => B"0000",
S_AXI_CTRL_WVALID => '0',
Sl1_CE => NLW_U0_Sl1_CE_UNCONNECTED,
Sl1_DBus(0 to 31) => NLW_U0_Sl1_DBus_UNCONNECTED(0 to 31),
Sl1_Ready => NLW_U0_Sl1_Ready_UNCONNECTED,
Sl1_UE => NLW_U0_Sl1_UE_UNCONNECTED,
Sl1_Wait => NLW_U0_Sl1_Wait_UNCONNECTED,
Sl2_CE => NLW_U0_Sl2_CE_UNCONNECTED,
Sl2_DBus(0 to 31) => NLW_U0_Sl2_DBus_UNCONNECTED(0 to 31),
Sl2_Ready => NLW_U0_Sl2_Ready_UNCONNECTED,
Sl2_UE => NLW_U0_Sl2_UE_UNCONNECTED,
Sl2_Wait => NLW_U0_Sl2_Wait_UNCONNECTED,
Sl3_CE => NLW_U0_Sl3_CE_UNCONNECTED,
Sl3_DBus(0 to 31) => NLW_U0_Sl3_DBus_UNCONNECTED(0 to 31),
Sl3_Ready => NLW_U0_Sl3_Ready_UNCONNECTED,
Sl3_UE => NLW_U0_Sl3_UE_UNCONNECTED,
Sl3_Wait => NLW_U0_Sl3_Wait_UNCONNECTED,
Sl_CE => Sl_CE,
Sl_DBus(0 to 31) => Sl_DBus(0 to 31),
Sl_Ready => Sl_Ready,
Sl_UE => Sl_UE,
Sl_Wait => Sl_Wait,
UE => NLW_U0_UE_UNCONNECTED
);
end STRUCTURE;
|
apache-2.0
|
5e4dff47aad73c1314e79037db321c54
| 0.631631 | 2.914233 | false | false | false | false |
eaglewyng/FPGA2048
|
grid.vhd
| 1 | 65,880 |
----------------------------------------------------------------------------------
-- Company: Parker Ridd and Travis Chambers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
entity Grid is
port (
clk : in std_logic;
rst : in std_logic;
grid_color : in std_logic_vector(7 downto 0);
pixel_x : in std_logic_vector(9 downto 0);
pixel_y : in std_logic_vector(9 downto 0);
btn : in std_logic_vector(3 downto 0);
draw_grid : out std_logic;
rgbOut : out std_logic_vector(7 downto 0);
gameOver : out std_logic;
score : out std_logic_vector(15 downto 0)
);
end Grid;
architecture Behavioral of Grid is
--grid signals
signal gridOn : std_logic;
signal rgbWire : std_logic_vector(7 downto 0);
signal drawBox1,drawBox2,drawBox3,drawBox4,drawBox5,drawBox6,drawBox7,drawBox8,drawBox9,
drawBox10,drawBox11,drawBox12,drawBox13,drawBox14,drawBox15,drawBox16 : std_logic;
signal box1x,box2x,box3x,box4x,box5x,box6x,box7x,box8x,box9x,
box10x,box11x,box12x,box13x,box14x,box15x,box16x : UNSIGNED(9 downto 0);
signal box1y,box2y,box3y,box4y,box5y,box6y,box7y,box8y,box9y,
box10y,box11y,box12y,box13y,box14y,box15y,box16y : UNSIGNED(9 downto 0);
signal drawBox_combined : STD_LOGIC_VECTOR(15 downto 0);
signal boxValueToDraw : UNSIGNED(11 downto 0);
signal boxXToDraw, boxYToDraw : UNSIGNED(9 downto 0);
signal draw_number : STD_LOGIC;
signal number_color : STD_LOGIC_VECTOR(7 downto 0);
signal boxBGRGB : STD_LOGIC_VECTOR(7 downto 0);
signal boxFinalRGB : STD_LOGIC_VECTOR(7 downto 0);
--register to check merge against
signal merge_reg, merge_next : STD_LOGIC_VECTOR(3 downto 0);
--score register
signal score_reg, score_next : UNSIGNED(15 downto 0);
-- 16 wires of 12 bits each
type value is array (15 downto 0) of unsigned(11 downto 0);
signal boxValues, boxValues_next: value;
signal btn_edgedet, btn_edgedet_next : STD_LOGIC_VECTOR(3 downto 0);
signal btn_posedge0, btn_posedge1, btn_posedge2, btn_posedge3 : STD_LOGIC;
signal btn_posedge : STD_LOGIC_VECTOR(3 downto 0);
--random number
signal random_num : unsigned(3 downto 0);
signal INrandom_num : std_logic_vector(3 downto 0);
--state register
type state_type is(randupdate, idle, merge1, move1, merge2, move2, merge3, move3);
signal state_reg, state_next : state_type;
signal btn_posedge_next : STD_LOGIC_VECTOR(3 downto 0);
begin
--button edge detector
--this is a positive edge detector, so we don't repeat moves unnecessarily
btn_posedge0 <= (btn(0) xor btn_edgedet(0)) when (btn(0) = '0') else '0';
btn_posedge1 <= (btn(1) xor btn_edgedet(1)) when (btn(1) = '0') else '0';
btn_posedge2 <= (btn(2) xor btn_edgedet(2)) when (btn(2) = '0') else '0';
btn_posedge3 <= (btn(3) xor btn_edgedet(3)) when (btn(3) = '0') else '0';
btn_edgedet_next <= btn;
--============================================================================
------------------Registers---------------------------------------------------
--============================================================================
process(clk, rst)
begin
if(rst = '1') then
boxValues <= (others => (others => '0'));
btn_edgedet <= (others => '0');
state_reg <= randUpdate;
btn_posedge <= (others => '0');
score_reg <= (others => '0');
merge_reg <= (others => '0');
elsif(clk'event and clk = '1') then
boxValues <= boxValues_next;
btn_edgedet <= btn_edgedet_next;
state_reg <= state_next;
btn_posedge <= btn_posedge_next;
score_reg <= score_next;
merge_reg <= merge_next;
end if;
end process;
---------------------------------------------------------------
-- Draw Grid Logic
---------------------------------------------------------------
gridOn <= '1' when ((unsigned(pixel_y) > 40 and unsigned(pixel_y) <= 440) and
(unsigned(pixel_x) > 120 and unsigned(pixel_x) <=520)) else
'0';
draw_grid <= '1' when unsigned(rgbWire) > 0 else
'0';
---------------------------------------------------------------
-- Grid/Box Color Logic
---------------------------------------------------------------
rgbWire <= boxFinalRGB when UNSIGNED(drawbox_combined) > 0 else
grid_color when gridOn = '1' else
"00000000";
rgbOut <= rgbWire;
--============================================================================
------------------Entity Instantiations---------------------------------------
--============================================================================
Random1 : entity work.randomGenerator
generic map(
width => 4
)
port map (
clk => clk,
random_num => INrandom_num
);
random_num <= UNSIGNED(INrandom_num);
Box1 : entity work.Box
generic map(
XPOS => 128,
YPOS => 48
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box1x,
posYPixOut => box1y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox1
);
Box2 : entity work.Box
generic map(
XPOS => 226,
YPOS => 48
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box2x,
posYPixOut => box2y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox2
);
Box3 : entity work.Box
generic map(
XPOS => 324,
YPOS => 48
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box3x,
posYPixOut => box3y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox3
);
Box4 : entity work.Box
generic map(
XPOS => 422,
YPOS => 48
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box4x,
posYPixOut => box4y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox4
);
Box5 : entity work.Box
generic map(
XPOS => 128,
YPOS => 146
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box5x,
posYPixOut => box5y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox5
);
Box6 : entity work.Box
generic map(
XPOS => 226,
YPOS => 146
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box6x,
posYPixOut => box6y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox6
);
Box7 : entity work.Box
generic map(
XPOS => 324,
YPOS => 146
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box7x,
posYPixOut => box7y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox7
);
Box8 : entity work.Box
generic map(
XPOS => 422,
YPOS => 146
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box8x,
posYPixOut => box8y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox8
);
Box9 : entity work.Box
generic map(
XPOS => 128,
YPOS => 244
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box9x,
posYPixOut => box9y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox9
);
Box10 : entity work.Box
generic map(
XPOS => 226,
YPOS => 244
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box10x,
posYPixOut => box10y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox10
);
Box11 : entity work.Box
generic map(
XPOS => 324,
YPOS => 244
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box11x,
posYPixOut => box11y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox11
);
Box12 : entity work.Box
generic map(
XPOS => 422,
YPOS => 244
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box12x,
posYPixOut => box12y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox12
);
Box13 : entity work.Box
generic map(
XPOS => 128,
YPOS => 342
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box13x,
posYPixOut => box13y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox13
);
Box14 : entity work.Box
generic map(
XPOS => 226,
YPOS => 342
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box14x,
posYPixOut => box14y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox14
);
Box15 : entity work.Box
generic map(
XPOS => 324,
YPOS => 342
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box15x,
posYPixOut => box15y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox15
);
Box16 : entity work.Box
generic map(
XPOS => 422,
YPOS => 342
)
port map(
pixel_x => pixel_x,
pixel_y => pixel_y,
posXPixOut => box16x,
posYPixOut => box16y,
--this signal is so we can tell whether we should actually draw the color
--being output by the box or not!
drawBox => drawBox16
);
process(btn_posedge, boxValues, state_reg, random_num, score_reg, btn_posedge3, btn_posedge2, btn_posedge1, btn_posedge0, merge_reg)
begin
boxValues_next <= boxValues;
gameOver <= '0';
state_next <= state_reg;
btn_posedge_next <= btn_posedge;
score_next <= score_reg;
merge_next <= merge_reg;
if(state_reg = idle) then
merge_next <= (others => '0');
if(unsigned(btn_posedge) > 0) then
state_next <= merge1;
score_next <= score_reg + 1;
else
btn_posedge_next <= btn_posedge3 & btn_posedge2 & btn_posedge1 & btn_posedge0;
end if;
elsif(state_reg = merge1 or state_reg = merge2 or state_reg = merge3) then
--next state logic
if(state_reg = merge1) then
state_next <= move1;
elsif(state_reg = merge2) then
state_next <= move2;
else
state_next <= move3;
end if;
case btn_posedge is
--right button
when "0001" =>
--first row
if(merge_reg(0) = '0') then
if(boxValues(0) = boxValues(1) and boxValues(2) = boxValues(3)) then
boxValues_next(0) <= (others => '0');
boxValues_next(1) <= (others => '0');
boxValues_next(2) <= boxValues(0) + boxValues(1);
boxValues_next(3) <= boxValues(2) + boxValues(3);
merge_next(0) <= '1';
elsif(boxValues(2) = boxValues(3)) then
boxValues_next(0) <= (others => '0');
boxValues_next(1) <= boxValues(0);
boxValues_next(2) <= boxValues(1);
boxValues_next(3) <= boxValues(2) + boxValues(3);
merge_next(0) <= '1';
elsif(boxValues(1) = boxvalues(2)) then
boxValues_next(0) <= (others => '0');
boxValues_next(1) <= boxValues(0);
boxValues_next(2) <= boxValues(1) + boxValues(2);
boxValues_next(3) <= boxValues(3);
merge_next(0) <= '1';
elsif(boxValues(0) = boxValues(1)) then
boxValues_next(0) <= (others => '0');
boxValues_next(1) <= boxValues(0) + boxValues(1);
boxValues_next(2) <= boxValues(2);
boxValues_next(3) <= boxValues(3);
merge_next(0) <= '1';
end if;
end if;
--second row
if(merge_reg(1) = '0') then
if(boxValues(4) = boxValues(5) and boxValues(6) = boxValues(7)) then
boxValues_next(4) <= (others => '0');
boxValues_next(5) <= (others => '0');
boxValues_next(6) <= boxValues(4) + boxValues(5);
boxValues_next(7) <= boxValues(6) + boxValues(7);
merge_next(1) <= '1';
elsif(boxValues(6) = boxValues(7)) then
boxValues_next(4) <= (others => '0');
boxValues_next(5) <= boxValues(4);
boxValues_next(6) <= boxValues(5);
boxValues_next(7) <= boxValues(6) + boxValues(7);
merge_next(1) <= '1';
elsif(boxValues(5) = boxvalues(6)) then
boxValues_next(4) <= (others => '0');
boxValues_next(5) <= boxValues(4);
boxValues_next(6) <= boxValues(5) + boxValues(6);
boxValues_next(7) <= boxValues(7);
merge_next(1) <= '1';
elsif(boxValues(4) = boxValues(5)) then
boxValues_next(4) <= (others => '0');
boxValues_next(5) <= boxValues(4) + boxValues(5);
boxValues_next(6) <= boxValues(6);
boxValues_next(7) <= boxValues(7);
merge_next(1) <= '1';
end if;
end if;
--third row
if(merge_reg(2) = '0') then
if(boxValues(8) = boxValues(9) and boxValues(10) = boxValues(11)) then
boxValues_next(8) <= (others => '0');
boxValues_next(9) <= (others => '0');
boxValues_next(10) <= boxValues(8) + boxValues(9);
boxValues_next(11) <= boxValues(10) + boxValues(11);
merge_next(2) <= '1';
elsif(boxValues(10) = boxValues(11)) then
boxValues_next(8) <= (others => '0');
boxValues_next(9) <= boxValues(8);
boxValues_next(10) <= boxValues(9);
boxValues_next(11) <= boxValues(10) + boxValues(11);
merge_next(2) <= '1';
elsif(boxValues(9) = boxvalues(10)) then
boxValues_next(8) <= (others => '0');
boxValues_next(9) <= boxValues(8);
boxValues_next(10) <= boxValues(9) + boxValues(10);
boxValues_next(11) <= boxValues(11);
merge_next(2) <= '1';
elsif(boxValues(8) = boxValues(9)) then
boxValues_next(8) <= (others => '0');
boxValues_next(9) <= boxValues(8) + boxValues(9);
boxValues_next(10) <= boxValues(10);
boxValues_next(11) <= boxValues(11);
merge_next(2) <= '1';
end if;
end if;
--fourth row
if(merge_reg(3) = '0') then
if(boxValues(12) = boxValues(13) and boxValues(14) = boxValues(15)) then
boxValues_next(12) <= (others => '0');
boxValues_next(13) <= (others => '0');
boxValues_next(14) <= boxValues(12) + boxValues(13);
boxValues_next(15) <= boxValues(14) + boxValues(15);
merge_next(3) <= '1';
elsif(boxValues(14) = boxValues(15)) then
boxValues_next(12) <= (others => '0');
boxValues_next(13) <= boxValues(12);
boxValues_next(14) <= boxValues(13);
boxValues_next(15) <= boxValues(14) + boxValues(15);
merge_next(3) <= '1';
elsif(boxValues(13) = boxvalues(14)) then
boxValues_next(12) <= (others => '0');
boxValues_next(13) <= boxValues(12);
boxValues_next(14) <= boxValues(13) + boxValues(14);
boxValues_next(15) <= boxValues(15);
merge_next(3) <= '1';
elsif(boxValues(12) = boxValues(13)) then
boxValues_next(12) <= (others => '0');
boxValues_next(13) <= boxValues(12) + boxValues(13);
boxValues_next(14) <= boxValues(14);
boxValues_next(15) <= boxValues(15);
merge_next(3) <= '1';
end if;
end if;
--left button
when "0010" =>
--first row
if(merge_reg(0) = '0') then
if(boxValues(0) = boxValues(1) and boxValues(2) = boxValues(3)) then
boxValues_next(0) <= boxValues(0) + boxValues(1);
boxValues_next(1) <= boxValues(2) + boxValues(3);
boxValues_next(2) <= (others => '0');
boxValues_next(3) <= (others => '0');
merge_next(0) <= '1';
elsif(boxValues(0) = boxValues(1)) then
boxValues_next(0) <= boxValues(0) + boxValues(1);
boxValues_next(1) <= boxValues(2);
boxValues_next(2) <= boxValues(3);
boxValues_next(3) <= (others => '0');
merge_next(0) <= '1';
elsif(boxValues(1) = boxvalues(2)) then
boxValues_next(0) <= boxValues(0);
boxValues_next(1) <= boxValues(1) + boxValues(2);
boxValues_next(2) <= boxValues(3);
boxValues_next(3) <= (others => '0');
merge_next(0) <= '1';
elsif(boxValues(2) = boxValues(3)) then
boxValues_next(0) <= boxValues(0);
boxValues_next(1) <= boxValues(1);
boxValues_next(2) <= boxValues(2) + boxValues(3);
boxValues_next(3) <= (others => '0');
merge_next(0) <= '1';
end if;
end if;
--second row
if(merge_reg(1) = '0') then
if(boxValues(4) = boxValues(5) and boxValues(6) = boxValues(7)) then
boxValues_next(4) <= boxValues(4) + boxValues(5);
boxValues_next(5) <= boxValues(6) + boxValues(7);
boxValues_next(6) <= (others => '0');
boxValues_next(7) <= (others => '0');
merge_next(1) <= '1';
elsif(boxValues(4) = boxValues(5)) then
boxValues_next(4) <= boxValues(4) + boxValues(5);
boxValues_next(5) <= boxValues(6);
boxValues_next(6) <= boxValues(7);
boxValues_next(7) <= (others => '0');
merge_next(1) <= '1';
elsif(boxValues(5) = boxvalues(6)) then
boxValues_next(4) <= boxValues(4);
boxValues_next(5) <= boxValues(5) + boxValues(6);
boxValues_next(6) <= boxValues(7);
boxValues_next(7) <= (others => '0');
merge_next(1) <= '1';
elsif(boxValues(6) = boxValues(7)) then
boxValues_next(4) <= boxValues(4);
boxValues_next(5) <= boxValues(5);
boxValues_next(6) <= boxValues(6) + boxValues(7);
boxValues_next(7) <= (others => '0');
merge_next(1) <= '1';
end if;
end if;
--third row
if(merge_reg(2) = '0') then
if(boxValues(8) = boxValues(9) and boxValues(10) = boxValues(11)) then
boxValues_next(8) <= boxValues(8) + boxValues(9);
boxValues_next(9) <= boxValues(10) + boxValues(11);
boxValues_next(10) <= (others => '0');
boxValues_next(11) <= (others => '0');
merge_next(2) <= '1';
elsif(boxValues(8) = boxValues(9)) then
boxValues_next(8) <= boxValues(8) + boxValues(9);
boxValues_next(9) <= boxValues(10);
boxValues_next(10) <= boxValues(11);
boxValues_next(11) <= (others => '0');
merge_next(2) <= '1';
elsif(boxValues(9) = boxvalues(10)) then
boxValues_next(8) <= boxValues(8);
boxValues_next(9) <= boxValues(9) + boxValues(10);
boxValues_next(10) <= boxValues(11);
boxValues_next(11) <= (others => '0');
merge_next(2) <= '1';
elsif(boxValues(10) = boxValues(11)) then
boxValues_next(8) <= boxValues(8);
boxValues_next(9) <= boxValues(9);
boxValues_next(10) <= boxValues(10) + boxValues(11);
boxValues_next(11) <= (others => '0');
merge_next(2) <= '1';
end if;
end if;
--fourth row
if(merge_reg(3) = '0') then
if(boxValues(12) = boxValues(13) and boxValues(14) = boxValues(15)) then
boxValues_next(12) <= boxValues(12) + boxValues(13);
boxValues_next(13) <= boxValues(14) + boxValues(15);
boxValues_next(14) <= (others => '0');
boxValues_next(15) <= (others => '0');
merge_next(3) <= '1';
elsif(boxValues(12) = boxValues(13)) then
boxValues_next(12) <= boxValues(12) + boxValues(13);
boxValues_next(13) <= boxValues(14);
boxValues_next(14) <= boxValues(15);
boxValues_next(15) <= (others => '0');
merge_next(3) <= '1';
elsif(boxValues(13) = boxvalues(14)) then
boxValues_next(12) <= boxValues(12);
boxValues_next(13) <= boxValues(13) + boxValues(14);
boxValues_next(14) <= boxValues(15);
boxValues_next(15) <= (others => '0');
merge_next(3) <= '1';
elsif(boxValues(14) = boxValues(15)) then
boxValues_next(12) <= boxValues(12);
boxValues_next(13) <= boxValues(13);
boxValues_next(14) <= boxValues(14) + boxValues(15);
boxValues_next(15) <= (others => '0');
merge_next(3) <= '1';
end if;
end if;
--down button
when "0100" =>
--first column
if(merge_reg(0) = '0') then
if(boxValues(0) = boxValues(4) and boxValues(8) = boxValues(12)) then
boxValues_next(0) <= (others => '0');
boxValues_next(4) <= (others => '0');
boxValues_next(8) <= boxValues(0) + boxValues(4);
boxValues_next(12) <= boxValues(8) + boxValues(12);
merge_next(0) <= '1';
elsif(boxValues(8) = boxValues(12)) then
boxValues_next(0) <= (others => '0');
boxValues_next(4) <= boxValues(0);
boxValues_next(8) <= boxValues(4);
boxValues_next(12) <= boxValues(8) + boxValues(12);
merge_next(0) <= '1';
elsif(boxValues(4) = boxValues(8)) then
boxValues_next(0) <= (others => '0');
boxValues_next(4) <= boxValues(0);
boxValues_next(8) <= boxValues(4) + boxValues(8);
boxValues_next(12) <= boxValues(12);
merge_next(0) <= '1';
elsif(boxValues(0) = boxValues(4)) then
boxValues_next(0) <= (others => '0');
boxValues_next(4) <= boxValues(0) + boxValues(4);
boxValues_next(8) <= boxValues(8);
boxValues_next(12) <= boxValues(12);
merge_next(0) <= '1';
end if;
end if;
--second column
if(merge_reg(1) = '0') then
if(boxValues(1) = boxValues(5) and boxValues(9) = boxValues(13)) then
boxValues_next(1) <= (others => '0');
boxValues_next(5) <= (others => '0');
boxValues_next(9) <= boxValues(1) + boxValues(5);
boxValues_next(13) <= boxValues(9) + boxValues(13);
merge_next(1) <= '1';
elsif(boxValues(9) = boxValues(13)) then
boxValues_next(1) <= (others => '0');
boxValues_next(5) <= boxValues(1);
boxValues_next(9) <= boxValues(5);
boxValues_next(13) <= boxValues(9) + boxValues(13);
merge_next(1) <= '1';
elsif(boxValues(5) = boxValues(9)) then
boxValues_next(1) <= (others => '0');
boxValues_next(5) <= boxValues(1);
boxValues_next(9) <= boxValues(5) + boxValues(9);
boxValues_next(13) <= boxValues(13);
merge_next(1) <= '1';
elsif(boxValues(1) = boxValues(5)) then
boxValues_next(1) <= (others => '0');
boxValues_next(5) <= boxValues(1) + boxValues(5);
boxValues_next(9) <= boxValues(9);
boxValues_next(13) <= boxValues(13);
merge_next(1) <= '1';
end if;
end if;
--third column
if(merge_reg(2) = '0') then
if(boxValues(2) = boxValues(6) and boxValues(10) = boxValues(14)) then
boxValues_next(2) <= (others => '0');
boxValues_next(6) <= (others => '0');
boxValues_next(10) <= boxValues(2) + boxValues(6);
boxValues_next(14) <= boxValues(10) + boxValues(14);
merge_next(2) <= '1';
elsif(boxValues(10) = boxValues(14)) then
boxValues_next(2) <= (others => '0');
boxValues_next(6) <= boxValues(2);
boxValues_next(10) <= boxValues(6);
boxValues_next(14) <= boxValues(10) + boxValues(14);
merge_next(2) <= '1';
elsif(boxValues(6) = boxValues(10)) then
boxValues_next(2) <= (others => '0');
boxValues_next(6) <= boxValues(2);
boxValues_next(10) <= boxValues(6) + boxValues(10);
boxValues_next(14) <= boxValues(14);
merge_next(2) <= '1';
elsif(boxValues(2) = boxValues(6)) then
boxValues_next(2) <= (others => '0');
boxValues_next(6) <= boxValues(2) + boxValues(6);
boxValues_next(10) <= boxValues(10);
boxValues_next(14) <= boxValues(14);
merge_next(2) <= '1';
end if;
end if;
--fourth column
if(merge_reg(3) = '0') then
if(boxValues(3) = boxValues(7) and boxValues(11) = boxValues(15)) then
boxValues_next(3) <= (others => '0');
boxValues_next(7) <= (others => '0');
boxValues_next(11) <= boxValues(3) + boxValues(7);
boxValues_next(15) <= boxValues(11) + boxValues(15);
merge_next(3) <= '1';
elsif(boxValues(11) = boxValues(15)) then
boxValues_next(3) <= (others => '0');
boxValues_next(7) <= boxValues(3);
boxValues_next(11) <= boxValues(7);
boxValues_next(15) <= boxValues(11) + boxValues(15);
merge_next(3) <= '1';
elsif(boxValues(7) = boxValues(11)) then
boxValues_next(3) <= (others => '0');
boxValues_next(7) <= boxValues(3);
boxValues_next(11) <= boxValues(7) + boxValues(11);
boxValues_next(15) <= boxValues(15);
merge_next(3) <= '1';
elsif(boxValues(3) = boxValues(7)) then
boxValues_next(3) <= (others => '0');
boxValues_next(7) <= boxValues(3) + boxValues(7);
boxValues_next(11) <= boxValues(11);
boxValues_next(15) <= boxValues(15);
merge_next(3) <= '1';
end if;
end if;
--up button
when "1000" =>
--first column
if(merge_reg(0) = '0') then
if(boxValues(0) = boxValues(4) and boxValues(8) = boxValues(12)) then
boxValues_next(0) <= boxValues(0) + boxValues(4);
boxValues_next(4) <= boxValues(8) + boxValues(12);
boxValues_next(8) <= (others => '0');
boxValues_next(12) <= (others => '0');
merge_next(0) <= '1';
elsif(boxValues(0) = boxValues(4)) then
boxValues_next(0) <= boxValues(0) + boxValues(4);
boxValues_next(4) <= boxValues(8);
boxValues_next(8) <= boxValues(12);
boxValues_next(12) <= (others => '0');
merge_next(0) <= '1';
elsif(boxValues(4) = boxvalues(8)) then
boxValues_next(0) <= boxValues(0);
boxValues_next(4) <= boxValues(4) + boxValues(8);
boxValues_next(8) <= boxValues(12);
boxValues_next(12) <= (others => '0');
merge_next(0) <= '1';
elsif(boxValues(8) = boxValues(12)) then
boxValues_next(0) <= boxValues(0);
boxValues_next(4) <= boxValues(4);
boxValues_next(8) <= boxValues(8) + boxValues(12);
boxValues_next(12) <= (others => '0');
merge_next(0) <= '1';
end if;
end if;
--second column
if(merge_reg(1) = '0') then
if(boxValues(1) = boxValues(5) and boxValues(9) = boxValues(13)) then
boxValues_next(1) <= boxValues(1) + boxValues(5);
boxValues_next(5) <= boxValues(9) + boxValues(13);
boxValues_next(9) <= (others => '0');
boxValues_next(13) <= (others => '0');
merge_next(1) <= '1';
elsif(boxValues(1) = boxValues(5)) then
boxValues_next(1) <= boxValues(1) + boxValues(5);
boxValues_next(5) <= boxValues(9);
boxValues_next(9) <= boxValues(13);
boxValues_next(13) <= (others => '0');
merge_next(1) <= '1';
elsif(boxValues(5) = boxvalues(9)) then
boxValues_next(1) <= boxValues(1);
boxValues_next(5) <= boxValues(5) + boxValues(9);
boxValues_next(9) <= boxValues(13);
boxValues_next(13) <= (others => '0');
merge_next(1) <= '1';
elsif(boxValues(9) = boxValues(13)) then
boxValues_next(1) <= boxValues(1);
boxValues_next(5) <= boxValues(5);
boxValues_next(9) <= boxValues(9) + boxValues(13);
boxValues_next(13) <= (others => '0');
merge_next(1) <= '1';
end if;
end if;
--third column
if(merge_reg(2) = '0') then
if(boxValues(2) = boxValues(6) and boxValues(10) = boxValues(14)) then
boxValues_next(2) <= boxValues(2) + boxValues(6);
boxValues_next(6) <= boxValues(10) + boxValues(14);
boxValues_next(10) <= (others => '0');
boxValues_next(14) <= (others => '0');
merge_next(2) <= '1';
elsif(boxValues(2) = boxValues(6)) then
boxValues_next(2) <= boxValues(2) + boxValues(6);
boxValues_next(6) <= boxValues(10);
boxValues_next(10) <= boxValues(14);
boxValues_next(14) <= (others => '0');
merge_next(2) <= '1';
elsif(boxValues(6) = boxvalues(10)) then
boxValues_next(2) <= boxValues(2);
boxValues_next(6) <= boxValues(6) + boxValues(10);
boxValues_next(10) <= boxValues(14);
boxValues_next(14) <= (others => '0');
merge_next(2) <= '1';
elsif(boxValues(10) = boxValues(14)) then
boxValues_next(2) <= boxValues(2);
boxValues_next(6) <= boxValues(6);
boxValues_next(10) <= boxValues(10) + boxValues(14);
boxValues_next(14) <= (others => '0');
merge_next(2) <= '1';
end if;
end if;
--fourth column
if(merge_reg(3) = '0') then
if(boxValues(3) = boxValues(7) and boxValues(11) = boxValues(15)) then
boxValues_next(3) <= boxValues(3) + boxValues(7);
boxValues_next(7) <= boxValues(11) + boxValues(15);
boxValues_next(11) <= (others => '0');
boxValues_next(15) <= (others => '0');
merge_next(3) <= '1';
elsif(boxValues(3) = boxValues(7)) then
boxValues_next(3) <= boxValues(3) + boxValues(7);
boxValues_next(7) <= boxValues(11);
boxValues_next(11) <= boxValues(15);
boxValues_next(15) <= (others => '0');
merge_next(3) <= '1';
elsif(boxValues(7) = boxvalues(11)) then
boxValues_next(3) <= boxValues(3);
boxValues_next(7) <= boxValues(7) + boxValues(11);
boxValues_next(11) <= boxValues(15);
boxValues_next(15) <= (others => '0');
merge_next(3) <= '1';
elsif(boxValues(11) = boxValues(15)) then
boxValues_next(3) <= boxValues(3);
boxValues_next(7) <= boxValues(7);
boxValues_next(11) <= boxValues(11) + boxValues(15);
boxValues_next(15) <= (others => '0');
merge_next(3) <= '1';
end if;
end if;
when others =>
state_next <= idle;
end case;
--what to do in move states
elsif(state_reg = move1 or state_reg = move2 or state_reg = move3) then
--update the state reg
if(state_reg = move1) then
state_next <= merge2;
elsif(state_reg = move2) then
state_next <= merge3;
else
state_next <= randupdate;
end if;
case btn_posedge is
--right button
when "0001" =>
--first row
if(boxValues(2) > 0 and boxValues(3) = 0) then
boxValues_next(0) <= TO_UNSIGNED(0, 12);
boxValues_next(1) <= boxValues(0);
boxValues_next(2) <= boxValues(1);
boxValues_next(3) <= boxValues(2);
elsif(boxValues(1) > 0 and boxValues(2) = 0) then
boxValues_next(0) <= TO_UNSIGNED(0, 12);
boxValues_next(1) <= boxValues(0);
boxValues_next(2) <= boxValues(1);
elsif(boxValues(0) > 0 and boxValues(1) = 0) then
boxValues_next(0) <= TO_UNSIGNED(0, 12);
boxValues_next(1) <= boxValues(0);
end if;
--second row
if(boxValues(6) > 0 and boxValues(7) = 0) then
boxValues_next(4) <= TO_UNSIGNED(0, 12);
boxValues_next(5) <= boxValues(4);
boxValues_next(6) <= boxValues(5);
boxValues_next(7) <= boxValues(6);
elsif(boxValues(5) > 0 and boxValues(6) = 0) then
boxValues_next(4) <= TO_UNSIGNED(0, 12);
boxValues_next(5) <= boxValues(4);
boxValues_next(6) <= boxValues(5);
elsif(boxValues(4) > 0 and boxValues(5) = 0) then
boxValues_next(4) <= TO_UNSIGNED(0, 12);
boxValues_next(5) <= boxValues(4);
end if;
--third row
if(boxValues(10) > 0 and boxValues(11) = 0) then
boxValues_next(8) <= TO_UNSIGNED(0, 12);
boxValues_next(9) <= boxValues(8);
boxValues_next(10) <= boxValues(9);
boxValues_next(11) <= boxValues(10);
elsif(boxValues(9) > 0 and boxValues(10) = 0) then
boxValues_next(8) <= TO_UNSIGNED(0, 12);
boxValues_next(9) <= boxValues(8);
boxValues_next(10) <= boxValues(9);
elsif(boxValues(8) > 0 and boxValues(9) = 0) then
boxValues_next(8) <= TO_UNSIGNED(0, 12);
boxValues_next(9) <= boxValues(8);
end if;
--fourth row
if(boxValues(14) > 0 and boxValues(15) = 0) then
boxValues_next(12) <= TO_UNSIGNED(0, 12);
boxValues_next(13) <= boxValues(12);
boxValues_next(14) <= boxValues(13);
boxValues_next(15) <= boxValues(14);
elsif(boxValues(13) > 0 and boxValues(14) = 0) then
boxValues_next(12) <= TO_UNSIGNED(0, 12);
boxValues_next(13) <= boxValues(12);
boxValues_next(14) <= boxValues(13);
elsif(boxValues(12) > 0 and boxValues(13) = 0) then
boxValues_next(12) <= TO_UNSIGNED(0, 12);
boxValues_next(13) <= boxValues(12);
end if;
--left button
when "0010" =>
--first row
if(boxValues(1) > 0 and boxValues(0) = 0) then
boxValues_next(3) <= TO_UNSIGNED(0, 12);
boxValues_next(2) <= boxValues(3);
boxValues_next(1) <= boxValues(2);
boxValues_next(0) <= boxValues(1);
elsif(boxValues(2) > 0 and boxValues(1) = 0) then
boxValues_next(3) <= TO_UNSIGNED(0, 12);
boxValues_next(2) <= boxValues(3);
boxValues_next(1) <= boxValues(2);
elsif(boxValues(3) > 0 and boxValues(2) = 0) then
boxValues_next(3) <= TO_UNSIGNED(0, 12);
boxValues_next(2) <= boxValues(3);
end if;
--second row
if(boxValues(5) > 0 and boxValues(4) = 0) then
boxValues_next(7) <= TO_UNSIGNED(0, 12);
boxValues_next(6) <= boxValues(7);
boxValues_next(5) <= boxValues(6);
boxValues_next(4) <= boxValues(5);
elsif(boxValues(6) > 0 and boxValues(5) = 0) then
boxValues_next(7) <= TO_UNSIGNED(0, 12);
boxValues_next(6) <= boxValues(7);
boxValues_next(5) <= boxValues(6);
elsif(boxValues(7) > 0 and boxValues(6) = 0) then
boxValues_next(7) <= TO_UNSIGNED(0, 12);
boxValues_next(6) <= boxValues(7);
end if;
--third row
if(boxValues(9) > 0 and boxValues(8) = 0) then
boxValues_next(11) <= TO_UNSIGNED(0, 12);
boxValues_next(10) <= boxValues(11);
boxValues_next(9) <= boxValues(10);
boxValues_next(8) <= boxValues(9);
elsif(boxValues(10) > 0 and boxValues(9) = 0) then
boxValues_next(11) <= TO_UNSIGNED(0, 12);
boxValues_next(10) <= boxValues(11);
boxValues_next(9) <= boxValues(10);
elsif(boxValues(11) > 0 and boxValues(10) = 0) then
boxValues_next(11) <= TO_UNSIGNED(0, 12);
boxValues_next(10) <= boxValues(11);
end if;
--fourth row
if(boxValues(13) > 0 and boxValues(12) = 0) then
boxValues_next(15) <= TO_UNSIGNED(0, 12);
boxValues_next(14) <= boxValues(15);
boxValues_next(13) <= boxValues(14);
boxValues_next(12) <= boxValues(13);
elsif(boxValues(14) > 0 and boxValues(13) = 0) then
boxValues_next(15) <= TO_UNSIGNED(0, 12);
boxValues_next(14) <= boxValues(15);
boxValues_next(13) <= boxValues(14);
elsif(boxValues(15) > 0 and boxValues(14) = 0) then
boxValues_next(15) <= TO_UNSIGNED(0, 12);
boxValues_next(14) <= boxValues(15);
end if;
--down button
when "0100" =>
--first column
if(boxValues(8) > 0 and boxValues(12) = 0) then
boxValues_next(0) <= TO_UNSIGNED(0, 12);
boxValues_next(4) <= boxValues(0);
boxValues_next(8) <= boxValues(4);
boxValues_next(12) <= boxValues(8);
elsif(boxValues(4) > 0 and boxValues(8) = 0) then
boxValues_next(0) <= TO_UNSIGNED(0, 12);
boxValues_next(4) <= boxValues(0);
boxValues_next(8) <= boxValues(4);
elsif(boxValues(0) > 0 and boxValues(4) = 0) then
boxValues_next(0) <= TO_UNSIGNED(0, 12);
boxValues_next(4) <= boxValues(0);
end if;
--second column
if(boxValues(9) > 0 and boxValues(13) = 0) then
boxValues_next(1) <= TO_UNSIGNED(0, 12);
boxValues_next(5) <= boxValues(1);
boxValues_next(9) <= boxValues(5);
boxValues_next(13) <= boxValues(9);
elsif(boxValues(5) > 0 and boxValues(9) = 0) then
boxValues_next(1) <= TO_UNSIGNED(0, 12);
boxValues_next(5) <= boxValues(1);
boxValues_next(9) <= boxValues(5);
elsif(boxValues(1) > 0 and boxValues(5) = 0) then
boxValues_next(1) <= TO_UNSIGNED(0, 12);
boxValues_next(5) <= boxValues(1);
end if;
--third column
if(boxValues(10) > 0 and boxValues(14) = 0) then
boxValues_next(2) <= TO_UNSIGNED(0, 12);
boxValues_next(6) <= boxValues(2);
boxValues_next(10) <= boxValues(6);
boxValues_next(14) <= boxValues(10);
elsif(boxValues(6) > 0 and boxValues(10) = 0) then
boxValues_next(2) <= TO_UNSIGNED(0, 12);
boxValues_next(6) <= boxValues(2);
boxValues_next(10) <= boxValues(6);
elsif(boxValues(2) > 0 and boxValues(6) = 0) then
boxValues_next(2) <= TO_UNSIGNED(0, 12);
boxValues_next(6) <= boxValues(2);
end if;
--fourth column
if(boxValues(11) > 0 and boxValues(15) = 0) then
boxValues_next(3) <= TO_UNSIGNED(0, 12);
boxValues_next(7) <= boxValues(3);
boxValues_next(11) <= boxValues(7);
boxValues_next(15) <= boxValues(11);
elsif(boxValues(7) > 0 and boxValues(11) = 0) then
boxValues_next(3) <= TO_UNSIGNED(0, 12);
boxValues_next(7) <= boxValues(3);
boxValues_next(11) <= boxValues(7);
elsif(boxValues(3) > 0 and boxValues(7) = 0) then
boxValues_next(3) <= TO_UNSIGNED(0, 12);
boxValues_next(7) <= boxValues(3);
end if;
--up button
when "1000" =>
--first column
if(boxValues(4) > 0 and boxValues(0) = 0) then
boxValues_next(12) <= TO_UNSIGNED(0, 12);
boxValues_next(8) <= boxValues(12);
boxValues_next(4) <= boxValues(8);
boxValues_next(0) <= boxValues(4);
elsif(boxValues(8) > 0 and boxValues(4) = 0) then
boxValues_next(12) <= TO_UNSIGNED(0, 12);
boxValues_next(8) <= boxValues(12);
boxValues_next(4) <= boxValues(8);
elsif(boxValues(12) > 0 and boxValues(8) = 0) then
boxValues_next(12) <= TO_UNSIGNED(0, 12);
boxValues_next(8) <= boxValues(12);
end if;
--second column
if(boxValues(5) > 0 and boxValues(1) = 0) then
boxValues_next(13) <= TO_UNSIGNED(0, 12);
boxValues_next(9) <= boxValues(13);
boxValues_next(5) <= boxValues(9);
boxValues_next(1) <= boxValues(5);
elsif(boxValues(9) > 0 and boxValues(5) = 0) then
boxValues_next(13) <= TO_UNSIGNED(0, 12);
boxValues_next(9) <= boxValues(13);
boxValues_next(5) <= boxValues(9);
elsif(boxValues(13) > 0 and boxValues(9) = 0) then
boxValues_next(13) <= TO_UNSIGNED(0, 12);
boxValues_next(9) <= boxValues(13);
end if;
--third column
if(boxValues(6) > 0 and boxValues(2) = 0) then
boxValues_next(14) <= TO_UNSIGNED(0, 12);
boxValues_next(10) <= boxValues(14);
boxValues_next(6) <= boxValues(10);
boxValues_next(2) <= boxValues(6);
elsif(boxValues(10) > 0 and boxValues(6) = 0) then
boxValues_next(14) <= TO_UNSIGNED(0, 12);
boxValues_next(10) <= boxValues(14);
boxValues_next(6) <= boxValues(10);
elsif(boxValues(14) > 0 and boxValues(10) = 0) then
boxValues_next(14) <= TO_UNSIGNED(0, 12);
boxValues_next(10) <= boxValues(14);
end if;
--fourth column
if(boxValues(7) > 0 and boxValues(3) = 0) then
boxValues_next(15) <= TO_UNSIGNED(0, 12);
boxValues_next(11) <= boxValues(15);
boxValues_next(7) <= boxValues(11);
boxValues_next(3) <= boxValues(7);
elsif(boxValues(11) > 0 and boxValues(7) = 0) then
boxValues_next(15) <= TO_UNSIGNED(0, 12);
boxValues_next(11) <= boxValues(15);
boxValues_next(7) <= boxValues(11);
elsif(boxValues(15) > 0 and boxValues(11) = 0) then
boxValues_next(15) <= TO_UNSIGNED(0, 12);
boxValues_next(11) <= boxValues(15);
end if;
when others =>
state_next <= idle;
end case;
elsif(state_reg = randupdate) then
btn_posedge_next <= btn_posedge3 & btn_posedge2 & btn_posedge1 & btn_posedge0;
--next state logic
state_next <= idle;
if boxValues(to_integer(random_num)) = 0 then
boxValues_next(to_integer(random_num)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 1)) = 0) then
boxValues_next(to_integer(random_num + 1)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 2)) = 0) then
boxValues_next(to_integer(random_num + 2)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 3)) = 0) then
boxValues_next(to_integer(random_num + 3)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 4)) = 0) then
boxValues_next(to_integer(random_num + 4)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 5)) = 0) then
boxValues_next(to_integer(random_num + 5)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 6)) = 0) then
boxValues_next(to_integer(random_num + 6)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 7)) = 0) then
boxValues_next(to_integer(random_num + 7)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 8)) = 0) then
boxValues_next(to_integer(random_num + 8)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 9)) = 0) then
boxValues_next(to_integer(random_num + 9)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 10)) = 0) then
boxValues_next(to_integer(random_num + 10)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 11)) = 0) then
boxValues_next(to_integer(random_num + 11)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 12)) = 0) then
boxValues_next(to_integer(random_num + 12)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 13)) = 0) then
boxValues_next(to_integer(random_num + 13)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 14)) = 0) then
boxValues_next(to_integer(random_num + 14)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 15)) = 0) then
boxValues_next(to_integer(random_num + 15)) <= to_unsigned(2,12);
elsif (boxValues(to_integer(random_num + 16)) = 0) then
boxValues_next(to_integer(random_num + 16)) <= to_unsigned(2,12);
else
gameOver <= '1';
end if;
end if;
end process;
score <= STD_LOGIC_VECTOR(score_reg);
--find the array index of the box to draw
process(drawBox_combined, box1x,box2x,box3x,box4x,box5x,box6x,box7x,box8x,box9x,
box10x,box11x,box12x,box13x,box14x,box15x,box16x, boxValues, box1y,box2y,box3y,box4y,box5y,box6y,box7y,box8y,box9y,
box10y,box11y,box12y,box13y,box14y,box15y,box16y)
begin
case drawBox_combined is
when "0000000000000001" =>
boxValueToDraw <= boxValues(0);
boxXToDraw <= box1x;
boxYToDraw <= box1y;
when "0000000000000010" =>
boxValueToDraw <= boxValues(1);
boxXToDraw <= box2x;
boxYToDraw <= box2y;
when "0000000000000100" =>
boxValueToDraw <= boxValues(2);
boxXToDraw <= box3x;
boxYToDraw <= box3y;
when "0000000000001000" =>
boxValueToDraw <= boxValues(3);
boxXToDraw <= box4x;
boxYToDraw <= box4y;
when "0000000000010000" =>
boxValueToDraw <= boxValues(4);
boxXToDraw <= box5x;
boxYToDraw <= box5y;
when "0000000000100000" =>
boxValueToDraw <= boxValues(5);
boxXToDraw <= box6x;
boxYToDraw <= box6y;
when "0000000001000000" =>
boxValueToDraw <= boxValues(6);
boxXToDraw <= box7x;
boxYToDraw <= box7y;
when "0000000010000000" =>
boxValueToDraw <= boxValues(7);
boxXToDraw <= box8x;
boxYToDraw <= box8y;
when "0000000100000000" =>
boxValueToDraw <= boxValues(8);
boxXToDraw <= box9x;
boxYToDraw <= box9y;
when "0000001000000000" =>
boxValueToDraw <= boxValues(9);
boxXToDraw <= box10x;
boxYToDraw <= box10y;
when "0000010000000000" =>
boxValueToDraw <= boxValues(10);
boxXToDraw <= box11x;
boxYToDraw <= box11y;
when "0000100000000000" =>
boxValueToDraw <= boxValues(11);
boxXToDraw <= box12x;
boxYToDraw <= box12y;
when "0001000000000000" =>
boxValueToDraw <= boxValues(12);
boxXToDraw <= box13x;
boxYToDraw <= box13y;
when "0010000000000000" =>
boxValueToDraw <= boxValues(13);
boxXToDraw <= box14x;
boxYToDraw <= box14y;
when "0100000000000000" =>
boxValueToDraw <= boxValues(14);
boxXToDraw <= box15x;
boxYToDraw <= box15y;
when "1000000000000000" =>
boxValueToDraw <= boxValues(15);
boxXToDraw <= box16x;
boxYToDraw <= box16y;
when others =>
boxValueToDraw <= (others => '0');
boxXToDraw <= (others => '0');
boxYToDraw <= (others => '0');
end case;
end process;
--drawing the box's background
with boxValueToDraw select
boxBGRGB <=
"10001111" when "000000000000",
"11111110" when "000000000010",
"11111000" when "000000000100",
"11110000" when "000000001000",
"11100000" when "000000010000",
"11001100" when "000000100000",
"11011000" when "000001000000",
"10011000" when "000010000000",
"00011100" when "000100000000",
"00011111" when "001000000000",
"00011011" when "010000000000",
"00000011" when others;
boxFinalRGB <= number_color when draw_number = '1' else
boxBGRGB when UNSIGNED(drawBox_Combined) > 0 else
"00000000";
--drawing the numbers
process(boxValueToDraw, pixel_x, pixel_y, boxXToDraw, boxYToDraw)
begin
draw_number <= '0';
number_color <= "00000000";
case boxValueToDraw is
--0
when "000000000000" =>
--don't draw anything
--2
when "000000000010" =>
if(boxXToDraw >= 30 and boxXToDraw < 60) then
if (boxYToDraw >= 20 and boxYToDraw < 30) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 30 and boxYToDraw < 40) then
if (boxXToDraw >= 30 and boxXToDraw < 42) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 40 and boxYToDraw < 50) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 50 and boxYToDraw < 60) then
if (boxXToDraw >= 48 and boxXToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 60 and boxYToDraw < 70) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--4
when "000000000100" =>
if(boxXToDraw >= 30 and boxXToDraw < 60) then
if (boxYToDraw >= 20 and boxYToDraw < 45) then
if (boxXToDraw >= 50 and boxXToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 45 and boxYToDraw < 55) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 55 and boxYToDraw < 70) then
if (boxXToDraw >= 30 and boxXToDraw < 42) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 48 and boxXToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
end if;
--8
when "000000001000" =>
if(boxXToDraw >= 30 and boxXToDraw < 60) then
if (boxYToDraw >= 20 and boxYToDraw < 30) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 30 and boxYToDraw < 40) then
if (boxXToDraw >= 30 and boxXToDraw < 40) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 50 and boxXToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 40 and boxYToDraw < 50) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 50 and boxYToDraw < 60) then
if (boxXToDraw >= 30 and boxXToDraw < 40) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 50 and boxXToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 60 and boxYToDraw < 70) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--16
when "000000010000" =>
-- for the "1"
if (boxXToDraw >= 15 and boxXToDraw < 43) then
if (boxYToDraw >= 24 and boxYToDraw < 34) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 34 and boxYToDraw < 53) then
if (boxXToDraw >= 24 and boxXToDraw < 34) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 53 and boxYToDraw < 64) then
if (boxXToDraw >= 15 and boxXToDraw < 34) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
-- for the "6"
elsif (boxXToDraw >= 47 and boxXToDraw < 75) then
if (boxYToDraw >= 24 and boxYToDraw < 32) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 32 and boxYToDraw < 40) then
if (boxXToDraw >= 47 and boxXToDraw < 56) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 66 and boxXToDraw < 75) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 40 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 56) then
if (boxXToDraw >= 47 and boxXToDraw < 56) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 56 and boxYToDraw < 64) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--32
when "000000100000" =>
--for the "3"
if (boxXToDraw >= 15 and boxXToDraw < 43) then
if (boxYToDraw >= 24 and boxYToDraw < 32) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 32 and boxYToDraw < 40) then
if (boxXToDraw >= 34 and boxXToDraw < 43) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 40 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 56) then
if (boxXToDraw >= 34 and boxXToDraw < 43) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 56 and boxYToDraw < 64) then
number_color <= "11111111";
draw_number <= '1';
end if;
--for the "2"
elsif (boxXToDraw >= 47 and boxXToDraw < 75) then
if (boxYToDraw >= 24 and boxYToDraw < 32) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 32 and boxYToDraw < 40) then
if (boxXToDraw >= 47 and boxXToDraw < 56) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 40 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 56) then
if (boxXToDraw >= 66 and boxXToDraw < 75) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 56 and boxYToDraw < 64) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--64
when "000001000000" =>
-- for the "6"
if (boxXToDraw >= 15 and boxXToDraw < 43) then
if (boxYToDraw >= 24 and boxYToDraw < 32) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 32 and boxYToDraw < 40) then
if (boxXToDraw >= 15 and boxXToDraw < 24) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 34 and boxXToDraw < 43) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 40 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 56) then
if (boxXToDraw >= 15 and boxXToDraw < 24) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 56 and boxYToDraw < 64) then
number_color <= "11111111";
draw_number <= '1';
end if;
-- for the "4"
elsif (boxXToDraw >= 47 and boxXToDraw < 75) then
if (boxYToDraw >= 24 and boxYToDraw < 40) then
if (boxXToDraw >= 66 and boxXToDraw < 75) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 40 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 64) then
if (boxXToDraw >= 47 and boxXToDraw < 56) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 66 and boxXToDraw < 75) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
end if;
--128
when "000010000000" =>
--for the "1"
if (boxXToDraw >= 16 and boxXToDraw < 25) then
if (boxYToDraw >= 24 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
if (boxXToDraw >= 9 and boxXToDraw < 25) then
if (boxYToDraw >= 57 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
if (boxXToDraw >= 9 and boxXToDraw < 32) then
if (boxYToDraw >= 24 and boxYToDraw < 33) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--for the "2"
if (boxXToDraw >= 34 and boxXToDraw < 56) then
if (boxYToDraw >= 24 and boxYToDraw < 33) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 33 and boxYToDraw < 41) then
if (boxXToDraw >= 34 and boxXToDraw < 43) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 41 and boxYToDraw < 49) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 49 and boxYToDraw < 57) then
if (boxXToDraw >= 47 and boxXToDraw < 56) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 57 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--for the "8"
if (boxXToDraw >= 58 and boxXToDraw < 81) then
if (boxYToDraw >= 24 and boxYToDraw < 33) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 33 and boxYToDraw < 42) then
if (boxXToDraw >= 58 and boxXToDraw < 65) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 74 and boxXToDraw < 81) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 42 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 57) then
if (boxXToDraw >= 58 and boxXToDraw < 65) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 74 and boxXToDraw < 81) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 57 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
-- 256
when "000100000000" =>
--for the "2"
if (boxXToDraw >= 9 and boxXToDraw < 32) then
if (boxYToDraw >= 24 and boxYToDraw < 33) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 33 and boxYToDraw < 41) then
if (boxXToDraw >= 9 and boxXToDraw < 18) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 41 and boxYToDraw < 49) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 49 and boxYToDraw < 57) then
if (boxXToDraw >= 22 and boxXToDraw < 32) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 57 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
--for the "5"
elsif (boxXToDraw >= 34 and boxXToDraw < 56) then
if (boxYToDraw >= 24 and boxYToDraw < 33) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 33 and boxYToDraw < 41) then
if (boxXToDraw >= 46 and boxXToDraw < 56) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 41 and boxYToDraw < 49) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 49 and boxYToDraw < 57) then
if (boxXToDraw >= 34 and boxXToDraw < 42) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 57 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
--for the "6"
elsif (boxXToDraw >= 58 and boxXToDraw <= 81) then
if (boxYToDraw >= 24 and boxYToDraw < 33) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 33 and boxYToDraw < 41) then
if (boxXToDraw >= 58 and boxXToDraw <= 66) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 73 and boxXToDraw < 81) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 41 and boxYToDraw < 49) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 49 and boxYToDraw < 57) then
if (boxXToDraw >= 58 and boxXToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 57 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--512
when "001000000000" =>
-- for the "5"
if (boxXToDraw >= 9 and boxXToDraw < 32) then
if (boxYToDraw >= 24 and boxYToDraw <= 33) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 33 and boxYToDraw < 41) then
if (boxXToDraw >= 24 and boxXToDraw < 32) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 41 and boxYToDraw < 49) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 49 and boxYToDraw < 57) then
if (boxXToDraw >= 9 and boxXToDraw < 18) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 57 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
-- for the "1"
elsif (boxXToDraw >= 34 and boxXToDraw < 56) then
if (boxYToDraw >= 24 and boxYToDraw < 33) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 33 and boxYToDraw < 57) then
if (boxXToDraw >= 40 and boxXToDraw < 49) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 57 and boxYToDraw < 66) then
if (boxXToDraw >= 34 and boxXToDraw < 49) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--for the "2"
elsif (boxXToDraw >= 58 and boxXToDraw < 81) then
if (boxYToDraw >= 24 and boxYToDraw < 33) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 33 and boxYToDraw < 41) then
if (boxXToDraw >= 58 and boxXToDraw < 67) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 41 and boxYToDraw < 49) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 49 and boxYToDraw < 57) then
if (boxXToDraw >= 72 and boxXToDraw < 81) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 57 and boxYToDraw < 66) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--1024
when "010000000000" =>
--for the "1"
if (boxXToDraw >= 6 and boxXToDraw < 24) then
if (boxYToDraw >= 30 and boxYToDraw < 36) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 36 and boxYToDraw < 54) then
if (boxXToDraw >= 12 and boxXToDraw < 18) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 54 and boxYToDraw < 60) then
if (boxXToDraw >= 6 and boxXToDraw < 18) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--for the "0"
elsif (boxXToDraw >= 26 and boxXToDraw < 44) then
if (boxYToDraw >= 30 and boxYToDraw < 36) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 36 and boxYToDraw < 54) then
if (boxXToDraw >= 26 and boxXToDraw < 32) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 38 and boxXToDraw < 44) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 54 and boxYToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
--for the "2"
elsif (boxXToDraw >= 46 and boxXToDraw < 64) then
if (boxYToDraw >= 30 and boxYToDraw < 36) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 36 and boxYToDraw < 42) then
if (boxXToDraw >= 46 and boxXToDraw < 52) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 42 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 54) then
if (boxXToDraw >= 58 and boxXToDraw < 64) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 54 and boxYToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
--for the "4"
elsif (boxXToDraw >= 66 and boxXToDraw < 84) then
if (boxYToDraw >= 30 and boxYToDraw < 42) then
if (boxXToDraw >= 78 and boxXToDraw < 84) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 42 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 60) then
if (boxXToDraw >= 66 and boxXToDraw < 72) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 78 and boxXToDraw < 84) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
end if;
--2048
when others =>
--for the "2"
if (boxXToDraw >= 6 and boxXToDraw < 24) then
if (boxYToDraw >= 30 and boxYToDraw < 36) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 36 and boxYToDraw < 42) then
if (boxXToDraw >= 6 and boxXToDraw < 12) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 42 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 54) then
if (boxXToDraw >= 18 and boxXToDraw < 24) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 54 and boxYToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
--for the "0"
elsif (boxXToDraw >= 26 and boxXToDraw < 44) then
if (boxYToDraw >= 30 and boxYToDraw < 36) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 36 and boxYToDraw < 54) then
if (boxXToDraw >= 26 and boxXToDraw < 32) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 38 and boxXToDraw < 44) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 54 and boxYToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
--for the "4"
elsif (boxXToDraw >= 46 and boxXToDraw < 64) then
if (boxYToDraw >= 30 and boxYToDraw < 42) then
if (boxXToDraw >= 58 and boxXToDraw < 64) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 42 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 60) then
if (boxXToDraw >= 46 and boxXToDraw < 52) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 58 and boxXToDraw < 64) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
--for the "8"
elsif (boxXToDraw >= 66 and boxXToDraw < 84) then
if (boxYToDraw >= 30 and boxYToDraw < 36) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 36 and boxYToDraw < 42) then
if (boxXToDraw >= 66 and boxXToDraw < 72) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 78 and boxXToDraw < 84) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 42 and boxYToDraw < 48) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxYToDraw >= 48 and boxYToDraw < 54) then
if (boxXToDraw >= 66 and boxXToDraw < 72) then
number_color <= "11111111";
draw_number <= '1';
elsif (boxXToDraw >= 78 and boxXToDraw < 84) then
number_color <= "11111111";
draw_number <= '1';
end if;
elsif (boxYToDraw >= 54 and boxYToDraw < 60) then
number_color <= "11111111";
draw_number <= '1';
end if;
end if;
end case;
end process;
--combined box drawing logic
drawBox_combined <= drawBox16 & drawBox15 & drawBox14 & drawBox13 & drawBox12 & drawBox11 & drawBox10 &
drawBox9 & drawBox8 & drawBox7 & drawBox6 & drawBox5 & drawBox4 & drawBox3 & drawBox2 &
drawBox1;
end Behavioral;
|
mit
|
567f95342d942c91ed02fdf8e6759047
| 0.580085 | 3.224354 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_rst_clk_wiz_1_100M_0/system_rst_clk_wiz_1_100M_0_sim_netlist.vhdl
| 1 | 32,658 |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:44:30 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_rst_clk_wiz_1_100M_0/system_rst_clk_wiz_1_100M_0_sim_netlist.vhdl
-- Design : system_rst_clk_wiz_1_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_cdc_sync : entity is "cdc_sync";
end system_rst_clk_wiz_1_100M_0_cdc_sync;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_cdc_sync_0 : entity is "cdc_sync";
end system_rst_clk_wiz_1_100M_0_cdc_sync_0;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_upcnt_n : entity is "upcnt_n";
end system_rst_clk_wiz_1_100M_0_upcnt_n;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_lpf : entity is "lpf";
end system_rst_clk_wiz_1_100M_0_lpf;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.system_rst_clk_wiz_1_100M_0_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.system_rst_clk_wiz_1_100M_0_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_sequence_psr : entity is "sequence_psr";
end system_rst_clk_wiz_1_100M_0_sequence_psr;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.system_rst_clk_wiz_1_100M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is "proc_sys_reset";
end system_rst_clk_wiz_1_100M_0_proc_sys_reset;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.system_rst_clk_wiz_1_100M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.system_rst_clk_wiz_1_100M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rst_clk_wiz_1_100M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rst_clk_wiz_1_100M_0 : entity is "system_rst_clk_wiz_1_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rst_clk_wiz_1_100M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rst_clk_wiz_1_100M_0 : entity is "proc_sys_reset,Vivado 2016.4";
end system_rst_clk_wiz_1_100M_0;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.system_rst_clk_wiz_1_100M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
apache-2.0
|
ac49e40a8a456aeaea58bc7177fa5386
| 0.573948 | 2.837852 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/amba.vhd
| 1 | 5,659 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/19/2016
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This is the package for all sort of axi interfaces. AHBi,
-- APB etc.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Changed indentation
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package amba is
------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------
constant AHBDW : integer := 32;
constant HTRANS_IDLE : std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY : std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ : std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ : std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE : std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR : std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4 : std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4 : std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8 : std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8 : std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16 : std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16 : std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE : std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD : std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD : std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD : std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD : std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD : std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD : std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD : std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY : std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR : std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY : std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT : std_logic_vector(1 downto 0) := "11";
------------------------------------------------------------------------------
-- AHB slave inputs
------------------------------------------------------------------------------
type t_ahb_slave_in is record
hsel : std_ulogic; -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(3 downto 0); -- burst type
hwdata : std_logic_vector(31 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection protocol
hready : std_ulogic; -- transfer done
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(3 downto 0); -- memory bank select
hcache : std_ulogic; -- cachable
end record;
-- AHB slave outputs
type t_ahb_slave_out is record
hreadyout : std_ulogic;
hresp : std_logic_vector(1 downto 0);
hrdata : std_logic_vector(31 downto 0);
end record;
type t_apb3_slave_in is record
psel : std_ulogic;
paddr : std_logic_vector(31 downto 0);
end record;
------------------------------------------------------------------------------
-- functions and procedures
------------------------------------------------------------------------------
-- function ahb_write_word (
-- hdata : std_logic_vector(AHBDW-1 downto 0);
-- haddr : std_logic_vector(4 downto 2))
-- return std_logic_vector;
procedure ahb_write_data (
haddr : in std_logic_vector(4 downto 2);
hdata : in std_logic_vector(AHBDW-1 downto 0));
function ahb_read_word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector;
procedure ahb_read_word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(AHBDW-1 downto 0));
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
component ahb_slave
port (
hclk : in std_ulogic;
hreset_n : in std_ulogic;
ahb_in : in t_ahb_slave_in;
ahb_out : out t_ahb_slave_out
);
end component;
end amba;
package body amba is
procedure ahb_write_data (
haddr : in std_logic_vector(4 downto 2);
hdata : in std_logic_vector(AHBDW-1 downto 0)) is
begin
end ahb_write_data;
function ahb_read_word (
hdata : std_logic_vector(AHBDW-1 downto 0);
haddr : std_logic_vector(4 downto 2))
return std_logic_vector is
variable data : std_logic_vector(AHBDW-1 downto 0);
begin
data := hdata;
return data;
end ahb_read_word;
procedure ahb_read_word (
hdata : in std_logic_vector(AHBDW-1 downto 0);
haddr : in std_logic_vector(4 downto 2);
data : out std_logic_vector(AHBDW-1 downto 0)) is
begin
data := ahb_read_word(hdata, haddr);
end ahb_read_word;
end;
|
gpl-3.0
|
9973f64601d48d1518ad6d040c084ef1
| 0.540378 | 3.821067 | false | false | false | false |
jeffmagina/ECE368
|
Project1/EXECUTE/execute.vhd
| 1 | 2,210 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:41:32 03/25/2015
-- Design Name:
-- Module Name: execute - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity execute is
Port( CLK : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR (3 downto 0);
OP1 : IN STD_LOGIC_VECTOR (15 downto 0);
OP2 : IN STD_LOGIC_VECTOR (15 downto 0);
Dec_Reg_A_IN : IN STD_LOGIC_VECTOR (3 downto 0);
OPA_REG_A : OUT STD_LOGIC_VECTOR (15 downto 0);
Dec_Reg_A_OUT : OUT STD_LOGIC_VECTOR (3 downto 0);
DEC_OPCODE_OUT: OUT STD_LOGIC_VECTOR (3 downto 0);
EX_FWD_OUT : OUT STD_LOGIC_VECTOR (15 downto 0);
FPU_OUT : OUT STD_LOGIC_VECTOR (15 downto 0);
CCR : OUT STD_LOGIC_VECTOR (3 downto 0)
);
end execute;
architecture Structural of execute is
signal s_ALU_OUT, s_OP1_IN, s_OP2_IN : STD_LOGIC_VECTOR (15 downto 0);
begin
U0: entity work.Register_RE_16
Port Map( CLK => CLK,
ENB => '1',
D => OP1,
Q => s_OP1_IN
);
U1: entity work.Register_RE_16
Port Map( CLK => CLK,
ENB => '1',
D => OP2,
Q => s_OP2_IN
);
OPA_REG_A <= OP1;
DEC_OPCODE:entity work.Register_FE_4
Port Map ( CLK => CLK,
ENB => '1',
D => OPCODE,
Q => DEC_OPCODE_OUT
);
U2: entity work.ALU
Port Map( CLK => CLK,
RA => s_OP1_IN, --15 downto 0
RB => s_OP2_IN, --15 downto 0
OPCODE => OPCODE,
CCR => CCR,
ALU_OUT => s_ALU_OUT
--LDST_OUT => --15 downto 0
);
EX_FWD_OUT <= s_ALU_OUT;
U3: entity work.Register_FE_16
Port Map( CLK => CLK,
ENB => '1',
D => s_ALU_OUT,
Q => FPU_OUT
);
DEC_REG_A: entity work.Register_FE_4
Port Map( CLK => CLK,
ENB => '1',
D => Dec_Reg_A_IN,
Q => Dec_Reg_A_OUT
);
end Structural;
|
mit
|
93e6a8438487d064fac1005c0790c8a6
| 0.498643 | 2.97043 | false | false | false | false |
daniw/add
|
lab1/Ex3/FIR_5x5_load_coeff/vhd/fir_2d_trn_load.vhd
| 2 | 9,103 |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 26-May-11
-- Project : RT Video Lab 1: Exercise 3
-- Description: 2D 5x5-FIR filter in transposed form with loadable coefficients
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity fir_2d_trn_load is
port (ce_1 : in std_logic;
clk_1 : in std_logic;
coef : in std_logic_vector (6 downto 0);
gain : in std_logic_vector (19 downto 0);
line1 : in std_logic_vector (7 downto 0);
line2 : in std_logic_vector (7 downto 0);
line3 : in std_logic_vector (7 downto 0);
line4 : in std_logic_vector (7 downto 0);
line5 : in std_logic_vector (7 downto 0);
load_1 : in std_logic;
load_2 : in std_logic;
load_3 : in std_logic;
load_4 : in std_logic;
load_5 : in std_logic;
dout : out std_logic_vector (7 downto 0)
);
end fir_2d_trn_load;
architecture Behavioral of fir_2d_trn_load is
constant len_inData_vec : integer := line1'length * 5;
constant len_inLoad_vec : integer := 5;
constant number_of_firs : integer := 5;
constant DW_OUT_FIR_5x5 : integer := 8;
constant binary_Point_Gain : integer := 17;
signal fir_data_in : std_logic_vector(len_inData_vec-1 downto 0) := (others => '0');
signal fir_load_in : std_logic_vector(len_inLoad_vec-1 downto 0) := (others => '0');
signal fir_dout : std_logic_vector(number_of_firs*19-1 downto 0) := (others => '0');
signal fir_1_dout : std_logic_vector(18 downto 0) := (others => '0');
signal fir_2_dout : std_logic_vector(18 downto 0) := (others => '0');
signal fir_3_dout : std_logic_vector(18 downto 0) := (others => '0');
signal fir_4_dout : std_logic_vector(18 downto 0) := (others => '0');
signal fir_5_dout : std_logic_vector(18 downto 0) := (others => '0');
signal adder_1_dout : std_logic_vector(19 downto 0) := (others => '0');
signal adder_2_dout : std_logic_vector(19 downto 0) := (others => '0');
signal adder_3_dout : std_logic_vector(20 downto 0) := (others => '0');
signal adder_4_dout : std_logic_vector(21 downto 0) := (others => '0');
signal reg1_dout : std_logic_vector(18 downto 0) := (others => '0');
signal reg2_dout : std_logic_vector(18 downto 0) := (others => '0');
signal reg2_dout_ext : std_logic_vector(20 downto 0) := (others => '0');
signal reg3_dout : std_logic_vector(19 downto 0) := (others => '0');
signal abs_dout : std_logic_vector(21 downto 0) := (others => '0');
signal mult_dout : std_logic_vector(41 downto 0) := (others => '0');
component fir_1d_trn_load is
generic(
IN_DW : integer; -- Input word width
OUT_DW : integer; -- Output word width
COEF_DW : integer; -- coefficient word width
TAPS : integer; -- # of taps + 1 output register
DELAY : integer -- output delay line
-- (to adapt latency to system architecture)
);
port(
ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector(COEF_DW-1 downto 0);
din : in std_logic_vector(IN_DW-1 downto 0);
out_data : out std_logic_vector(OUT_DW-1 downto 0)
);
end component;
component MULT is
generic(
DW_IN_1 : integer;
DW_IN_2 : integer;
DELAY : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
FACTOR_IN_1 : in std_logic_vector(DW_IN_1-1 downto 0);
FACTOR_IN_2 : in std_logic_vector(DW_IN_2-1 downto 0);
PRODUCT_OUT : out std_logic_vector((DW_IN_1 + DW_IN_2 - 1) downto 0)
);
end component;
component ADDER is
generic(
DW_IN : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
S_IN_1 : in std_logic_vector(DW_IN-1 downto 0);
S_IN_2 : in std_logic_vector(DW_IN-1 downto 0);
SUM_OUT : out std_logic_vector(DW_IN downto 0)
);
end component;
component ABS_VAL is
generic(
DW : integer
);
port(
ce_1 : in std_logic;
clk_1 : in std_logic;
VAL_IN : in std_logic_vector(DW-1 downto 0);
VAL_OUT : out std_logic_vector(DW-1 downto 0)
);
end component;
component Pipeline_Reg is
generic(
DW_IN : integer
);
port(
clk_1 : in std_logic;
en : in std_logic;
D : in std_logic_vector(DW_IN-1 downto 0);
Q : out std_logic_vector(DW_IN-1 downto 0)
);
end component;
component CONVERT is
generic(
DW_IN : integer;
DW_OUT : integer;
BIN_PNT : integer
);
port(
clk_1 : in std_logic;
ce_1 : in std_logic;
din : in std_logic_vector(DW_IN-1 downto 0);
dout : out std_logic_vector(DW_OUT-1 downto 0)
);
end component;
begin
-- Concatenate input signals to enable 1D-FIR instantiation
-- line
fir_data_in(1*8-1 downto 0) <= line1;
fir_data_in(2*8-1 downto 1*7+1) <= line2;
fir_data_in(3*8-1 downto 2*7+2) <= line3;
fir_data_in(4*8-1 downto 3*7+3) <= line4;
fir_data_in(5*8-1 downto 4*7+4) <= line5;
-- load
fir_load_in(0) <= load_1;
fir_load_in(1) <= load_2;
fir_load_in(2) <= load_3;
fir_load_in(3) <= load_4;
fir_load_in(4) <= load_5;
-- De-concatenate 1D-FIR outpus
fir_1_dout <= fir_dout(1*19-1 downto 0);
fir_2_dout <= fir_dout(2*19-1 downto 1*18+1);
fir_3_dout <= fir_dout(3*19-1 downto 2*18+2);
fir_4_dout <= fir_dout(4*19-1 downto 3*18+3);
fir_5_dout <= fir_dout(5*19-1 downto 4*18+4);
-- instantiate 5 1D-FIR filter
FIR_5x5 : for N in 0 to 4 generate
fir_N : fir_1d_trn_load
generic map(
IN_DW => 8,
OUT_DW => 19,
COEF_DW => 7,
TAPS => 5,
DELAY => 8
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
load => fir_load_in(N),
coef => coef,
din => fir_data_in((N+1)*8-1 downto N*7+N),
out_data => fir_dout((N+1)*19-1 downto N*18+N)
);
end generate;
-- instantiate adder tree
ADDER_1 : ADDER
generic map(
DW_IN => fir_1_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
S_IN_1 => fir_1_dout,
S_IN_2 => fir_2_dout,
SUM_OUT => adder_1_dout
);
ADDER_2 : ADDER
generic map(
DW_IN => fir_3_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
S_IN_1 => fir_3_dout,
S_IN_2 => fir_4_dout,
SUM_OUT => adder_2_dout
);
ADDER_3 : ADDER
generic map(
DW_IN => adder_1_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
S_IN_1 => adder_1_dout,
S_IN_2 => adder_2_dout,
SUM_OUT => adder_3_dout
);
reg2_dout_ext <= "00" & reg2_dout;
ADDER_4 : ADDER
generic map(
DW_IN => adder_3_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
S_IN_1 => adder_3_dout,
S_IN_2 => reg2_dout_ext,
SUM_OUT => adder_4_dout
);
REG_1 : Pipeline_Reg
generic map(
DW_IN => fir_5_dout'length
)
port map(
clk_1 => clk_1,
en => '1',
D => fir_5_dout,
Q => reg1_dout
);
REG_2 : Pipeline_Reg
generic map(
DW_IN => reg1_dout'length
)
port map(
clk_1 => clk_1,
en => '1',
D => reg1_dout,
Q => reg2_dout
);
-- instantiate components for output scaling
REG_GAIN : Pipeline_Reg
generic map(
DW_IN => gain'length
)
port map(
clk_1 => clk_1,
en => load_5,
D => gain,
Q => reg3_dout
);
ABS_1 : ABS_VAL
generic map(
DW => adder_4_dout'length
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
VAL_IN => adder_4_dout,
VAL_OUT => abs_dout
);
MULT_1 : MULT
generic map(
DW_IN_1 => abs_dout'length,
DW_IN_2 => reg3_dout'length,
DELAY => 3
)
port map(
ce_1 => ce_1,
clk_1 => clk_1,
FACTOR_IN_1 => abs_dout,
FACTOR_IN_2 => reg3_dout,
PRODUCT_OUT => mult_dout
);
CONV_1 : CONVERT
generic map(
DW_IN => mult_dout'length,
DW_OUT => DW_OUT_FIR_5x5,
BIN_PNT => binary_Point_Gain
)
port map(
clk_1 => clk_1,
ce_1 => ce_1,
din => mult_dout,
dout => dout
);
end Behavioral;
|
gpl-2.0
|
c9261a1b8bc25c5098ad3c505b2a3faa
| 0.500165 | 3.051626 | false | false | false | false |
daniw/add
|
floppy/mcu/cpu_ctrl.vhd
| 2 | 8,758 |
-------------------------------------------------------------------------------
-- Entity: cpu_ctrl
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Control unit without instruction pipelining for the RISC-CPU of the
-- von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: (2*16 + 2) + 3
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_ctrl is
port(rst : in std_logic;
clk : in std_logic;
-- bus interface signals
data_in : in std_logic_vector(DW-1 downto 0);
addr : out std_logic_vector(AW-1 downto 0);
data_out : out std_logic_vector(DW-1 downto 0);
r_wb : out std_logic;
-- CPU internal interfaces
reg_in : in t_reg2ctr;
reg_out : out t_ctr2reg;
prc_in : in t_prc2ctr;
prc_out : out t_ctr2prc;
alu_in : in t_alu2ctr;
alu_out : out t_ctr2alu
);
end cpu_ctrl;
architecture rtl of cpu_ctrl is
-- FSM signals
type state is (s_if, s_id, s_ex, s_ma, s_rw);
signal c_st, n_st : state;
-- Instruction register & decoding
signal instr_reg : std_logic_vector(DW-1 downto 0);
signal instr_enb : std_logic;
-- register write enable signals registered
signal reg_enb_low : std_logic;
signal reg_enb_high : std_logic;
-- opcode signal decoded from instruction register(used in several processes)
-- This signal could be of type t_instr when using 'val attribute,
-- but this is not supported by ISE XST.
-- t_instr'val(to_integer(unsigned(instr_reg(DW-1 downto DW-(OPCW-OPAW)))))
signal opcode : natural range 0 to 2**DW-1;
begin
-----------------------------------------------------------------------------
-- Bus Interface
-----------------------------------------------------------------------------
data_out <= reg_in.data;
-----------------------------------------------------------------------------
-- PC Interface
-----------------------------------------------------------------------------
prc_out.addr <= instr_reg(AW-1 downto 0);
-----------------------------------------------------------------------------
-- Instruction register & data register to Register Block
-----------------------------------------------------------------------------
P_ir: process(clk)
begin
if rising_edge(clk) then
-- instruction register
if instr_enb = '1' then
instr_reg <= data_in;
end if;
-- write enable and data signals to reg block; registered to break comb.
-- path from ROM to register block
reg_out.enb_data_low <= reg_enb_low;
reg_out.enb_data_high <= reg_enb_high;
if opcode = 16 then
-- load instruction, register low & high byte from bus system
reg_out.data <= data_in;
elsif opcode = 15 then
-- setih instruction, register low byte from instr. reg as high byte
reg_out.data(DW-1 downto DW/2) <= instr_reg(DW/2-1 downto 0);
else
-- e.g. setil instruction, register low byte from instr. reg as low byte
reg_out.data <= instr_reg;
end if;
end if;
end process;
-- Instruction register decoding
opcode <= to_integer(unsigned(instr_reg(DW-1 downto DW-OPCW)));
alu_out.op <= instr_reg(DW-1-(OPCW-OPAW) downto DW-OPCW);
alu_out.imm <= instr_reg(IOWW-1 downto 0);
reg_out.dest <= instr_reg(10 downto 8);
reg_out.src1 <= instr_reg(10 downto 8) when (opcode = 12 or opcode = 13) else
instr_reg( 7 downto 5);
reg_out.src2 <= instr_reg( 4 downto 2);
-----------------------------------------------------------------------------
-- FSM: Mealy-type
-- Inputs : c_st, opcode
-- Outputs: n_st, r_wb, instr_enb, reg_out.enb_res, reg_enb_low,
-- reg_enb_high, alu_out.enb, prc_out.enb, prc_out.mode
-----------------------------------------------------------------------------
-- memoryless process
p_fsm_com: process (c_st, opcode, alu_in, reg_in, prc_in)
begin
-- default assignments
n_st <= c_st; -- remain in current state
r_wb <= '1'; -- default: read
instr_enb <= '0';
reg_out.enb_res <= '0';
reg_enb_low <= '0';
reg_enb_high <= '0';
alu_out.enb <= '0';
prc_out.enb <= '0';
prc_out.mode <= linear;
addr <= (others => '1'); -- reset vector
-- specific assignments
case c_st is
when s_if =>
-- instruction fetch -------------------------------------------------
if prc_in.exc = no_err then
-- normal fetch if no exception, otherwise go to reset vector
addr <= prc_in.pc;
end if;
n_st <= s_id;
when s_id =>
-- instruction decode ------------------------------------------------
instr_enb <= '1';
n_st <= s_ex;
when s_ex =>
-- instruction execute -----------------------------------------------
if opcode <= 7 or opcode = 12 or opcode = 13 then
-- reg/reg-instruction or addil/h instruction
-- increase PC, store result/flags from ALU, start next instr. cycle
prc_out.enb <= '1';
reg_out.enb_res <= '1';
alu_out.enb <= '1';
n_st <= s_if;
elsif opcode = 14 then
-- setil instruction
-- increase PC, enable storage of low-byte, start next instr. cycle
prc_out.enb <= '1';
reg_enb_low <= '1';
n_st <= s_if;
elsif opcode = 15 then
-- setih instruction
-- increase PC, enable storage of high-byte, start next instr. cycle
prc_out.enb <= '1';
reg_enb_high <= '1';
n_st <= s_if;
elsif opcode = 16 or opcode = 17 then
-- load/store instruction
-- increase PC, go to "Memory Access" state
prc_out.enb <= '1';
n_st <= s_ma;
elsif opcode = 24 then
-- jump instruction
-- set PC to absolute address, start next instr. cycle
prc_out.enb <= '1';
prc_out.mode <= abs_jump;
n_st <= s_if;
elsif opcode >= 25 and opcode <= 29 then
-- branch instructions
prc_out.enb <= '1';
n_st <= s_if;
-- bne: branch if not equal (not Z)
if opcode = 25 and alu_in.flag(Z) = '0' then
prc_out.mode <= rel_offset;
end if;
-- bge: branch if greater/equal (not N or Z)
if opcode = 26 and (alu_in.flag(N) = '0' or alu_in.flag(Z) = '1') then
prc_out.mode <= rel_offset;
end if;
-- blt: branch if less than (N)
if opcode = 27 and alu_in.flag(N) = '1' then
prc_out.mode <= rel_offset;
end if;
-- bca: branch if carry set (C)
if opcode = 28 and alu_in.flag(C) = '1' then
prc_out.mode <= rel_offset;
end if;
-- bov: branch if overflow set (O)
if opcode = 29 and alu_in.flag(O) = '1' then
prc_out.mode <= rel_offset;
end if;
else
-- NOP instruction
prc_out.enb <= '1';
n_st <= s_if;
end if;
when s_ma =>
-- memory access ---------------------------------------------------
if opcode = 16 then
-- load instruction
-- read data from memory and go to "Register Write-Back" state
n_st <= s_rw;
else
-- store instruction
-- write data from register to memory and start next instr. cycle
r_wb <= '0'; -- active-low write
n_st <= s_if;
end if;
addr <= reg_in.addr;
when s_rw =>
-- register write-back --------------------------------------------
-- store data from memory in register and start next instr. cycle
reg_enb_low <= '1';
reg_enb_high <= '1';
n_st <= s_if;
when others =>
n_st <= s_if; -- handle parasitic states
end case;
end process;
-------------------------------------------------------------------------
-- sequential process
-- # of FFs: 3 (assuming binary state encoding)
P_fsm_seq: process(rst, clk)
begin
if rst = '1' then
c_st <= s_if;
elsif rising_edge(clk) then
c_st <= n_st;
end if;
end process;
end rtl;
|
gpl-2.0
|
9cff3faffafe4120c4fcfbb40a9fbe50
| 0.452843 | 4.086794 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG_for lab/ASCII_BUFFER.vhd
| 1 | 3,195 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: DEBUG UNIT
-- Project Name: DEBUG UNIT
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debug Unit for part 4 of Lab 1
-- Takes in a 0 - F on the ASCII_DATA line
-- and outputs it to the BUFFER concatenated
-- together to form the Instruction
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ASCII_BUFFER is
port(
ASCII_DATA : in STD_LOGIC_VECTOR(7 downto 0);
ASCII_RD: in STD_LOGIC;
ASCII_WE: in STD_LOGIC;
CLK: in STD_LOGIC;
RST: in STD_LOGIC;
ASCII_BUFF: out STD_LOGIC_VECTOR(19 downto 0)
);
end ASCII_BUFFER;
architecture dataflow of ASCII_BUFFER is
type StateType is (init, idle, VALID_KEY, SPECIAL_KEY, BACKSPACE, FLUSH);
signal STATE : StateType := init;
type ram_type is array (0 to 5) of STD_LOGIC_VECTOR(3 downto 0);
signal ram_addr : integer range 0 to 5;
signal ram : ram_type;
signal KEY : STD_LOGIC_VECTOR(3 downto 0);
signal INST: STD_LOGIC_VECTOR(19 downto 0) := (OTHERS => '0');
begin
with ASCII_DATA select
KEY <=
x"f" when x"66",
x"e" when x"65",
x"d" when x"64",
x"c" when x"63",
x"b" when x"62",
x"a" when x"61",
x"F" when x"46",
x"E" when x"45",
x"D" when x"44",
x"C" when x"43",
x"B" when x"42",
x"A" when x"41",
x"9" when x"39",
x"8" when x"38",
x"7" when x"37",
x"6" when x"36",
x"5" when x"35",
x"4" when x"34",
x"3" when x"33",
x"2" when x"32",
x"1" when x"31",
x"0" when x"30",
x"0" when OTHERS; -- Null
PROCESS(CLK,RST)
BEGIN
if(RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '1' ) then
case STATE is
when init =>
ASCII_BUFF <= (OTHERS => '0');
ram(0) <= x"0";
ram(1) <= x"0";
ram(2) <= x"0";
ram(3) <= x"0";
ram(4) <= x"0";
ram_addr <= 0;
state <= idle;
when idle =>
ASCII_BUFF <= INST;
if ASCII_RD = '1' and ASCII_WE = '1' then
state <= VALID_KEY;
-- A Valid key was pressed
elsif ASCII_RD = '1' and ASCII_WE = '0' then
state <= SPECIAL_KEY;
--Special key was pressed
else
state <= idle;
end if;
when VALID_KEY =>
if ram_addr < 5 then
ram(ram_addr) <= key;
ram_addr <= ram_addr + 1;
else
ram_addr <= 5;
end if;
state <= idle;
when SPECIAL_KEY =>
if ASCII_DATA = x"0D" then --0D = enterkey
state <= FLUSH;
elsif ASCII_DATA = x"08" then -- 08 = backspace
state <= BACKSPACE;
else
state <= idle;
end if;
when BACKSPACE =>
if ram_addr > 0 then
ram_addr <= ram_addr - 1;
end if;
ram(ram_addr) <= x"0";
state <= idle;
when FLUSH =>
INST <= ram(0) & ram(1) & ram(2) & ram(3) & ram(4);
state <= init;
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
|
mit
|
5879c7fc1fdbf8a6adc435a2aa14f9d5
| 0.548983 | 2.886179 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/InstructionMemory_tb.vhd
| 1 | 1,372 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY InstructionMemory_tb IS
END InstructionMemory_tb;
ARCHITECTURE behavior OF InstructionMemory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT InstructionMemory
PORT(
Address : IN std_logic_vector(5 downto 0);
rst: IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Address : std_logic_vector(5 downto 0) := (others => '0');
signal rst: std_logic:= '0';
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: InstructionMemory PORT MAP (
Address => Address,
rst =>rst,
Instruction => Instruction
);
-- Stimulus process
stim_proc: process
begin
rst<='0';
Address<=(others=>'0');
wait for 20 ns;
Address<="000001";
wait for 40 ns;
Address<="000010";
wait for 40 ns;
Address<="000011";
wait for 40 ns;
Address<="000100";
wait for 40 ns;
Address<="000101";
wait for 40 ns;
Address<="000110";
wait for 40 ns;
Address<="000111";
wait for 40 ns;
rst<='1';
Address<="000001";
wait for 40 ns;
Address<="000100";
wait;
end process;
END;
|
mit
|
df3b9d1522044054187df961160769c0
| 0.580904 | 3.897727 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALUwithInput/button_controller.vhd
| 1 | 1,410 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Button Controller
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Switch Controller
-- Maintain input from the four buttons on Nexys
-- Built in debouncer for buttons
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity buttoncontrol is
Port ( CLK : in STD_LOGIC;
BTN : in STD_LOGIC_VECTOR (3 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (3 downto 0));
end buttoncontrol;
architecture Structural of buttoncontrol is
begin
----- Structural Components: -----
BTN_0: entity work.debounce
port map( CLK => CLK,
INPUT => BTN(0),
OUTPUT => OUTPUT(0));
BTN_1: entity work.debounce
port map( CLK => CLK,
INPUT => BTN(1),
OUTPUT => OUTPUT(1));
BTN_2: entity work.debounce
port map( CLK => CLK,
INPUT => BTN(2),
OUTPUT => OUTPUT(2));
BTN_3: entity work.debounce
port map( CLK => CLK,
INPUT => BTN(3),
OUTPUT => OUTPUT(3));
----- End Structural Components -----
end Structural;
|
mit
|
5940b8ee756a07306ba7515bb15b5377
| 0.563121 | 4.221557 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_ilmb_v10_0/sim/system_ilmb_v10_0.vhd
| 1 | 8,370 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_v10_v3_0_9;
USE lmb_v10_v3_0_9.lmb_v10;
ENTITY system_ilmb_v10_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END system_ilmb_v10_0;
ARCHITECTURE system_ilmb_v10_0_arch OF system_ilmb_v10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ilmb_v10_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_v10 IS
GENERIC (
C_LMB_NUM_SLAVES : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_LMB_AWIDTH : INTEGER;
C_EXT_RESET_HIGH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END COMPONENT lmb_v10;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
BEGIN
U0 : lmb_v10
GENERIC MAP (
C_LMB_NUM_SLAVES => 1,
C_LMB_DWIDTH => 32,
C_LMB_AWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
PORT MAP (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
END system_ilmb_v10_0_arch;
|
apache-2.0
|
f5e432f05638667123e3f4a7e5b8ea20
| 0.689486 | 3.360096 | false | true | false | false |
jeffmagina/ECE368
|
Lab1/CounterTest/button_controller.vhd
| 2 | 1,578 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Button Controller
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Switch Controller
-- Maintain input from the four buttons on Nexys
-- Built in debouncer for buttons
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity buttoncontrol is
Port ( CLK : in STD_LOGIC;
SW : in STD_LOGIC;
BTN : in STD_LOGIC_VECTOR (3 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0));
end buttoncontrol;
architecture Structural of buttoncontrol is
begin
----- Structural Components: -----
BTN_0: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(0),
OUTPUT => LED(0));
BTN_1: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(1),
OUTPUT => LED(1));
BTN_2: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(2),
OUTPUT => LED(2));
BTN_3: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(3),
OUTPUT => LED(3));
----- End Structural Components -----
end Structural;
|
mit
|
877d77ac218fbc197e347a4154ccc90a
| 0.511407 | 4.288043 | false | false | false | false |
daniw/add
|
lab1/Ex1/FIR_1x5_const_coeff/vhd/fir_1d_tb.vhd
| 1 | 5,533 |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 28-Mar-11
-- Project : RT Video Lab 1: Exercise 1
-- Description: Testbench for 5-tap FIR filter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std; use std.textio.all;
entity fir_1d_tb IS
end fir_1d_tb;
architecture behavior of fir_1d_tb is
-- Component Declaration for the Unit Under Test (UUT)
component fir_1d_dir is
generic
(IN_DW, OUT_DW, COEF_DW, TAPS, DELAY : integer);
port
(ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector; -- coefficients
din : in std_logic_vector; -- data input
out_data : out std_logic_vector -- filtered output data
);
end component;
-- clock frequency definition
constant clk_freq : real := 100.0; -- 100 MHz
constant t_clk : time := 1000.0/clk_freq * 1 ns; -- one clock period
-- define delays for timing-simulation
constant t_stim : time := 0.25*t_clk; -- delay time for stimuli application
constant t_prop : time := 0.25*t_clk; -- propagation delay for UUT mimic
-- design parameters
constant IN_DW : integer := 8;
constant OUT_DW : integer := 19;
constant COEF_DW: integer := 7;
constant TAPS : integer := 5;
constant DELAY : integer := 8; -- adapt to adjust filter latency!!!
-- inputs signals
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal coef : std_logic_vector(COEF_DW-1 downto 0) := (others => '0');
signal din : std_logic_vector(IN_DW-1 downto 0) := (others => '0');
-- outputs signals
signal out_data : std_logic_vector(OUT_DW-1 downto 0) := (others => '0');
-- local testbench control signals
signal err_cnt : natural := 0;
-- I/O files
-- Expeceted responses are generated for the middle row of the corresponding
-- filter mask, which correspnds to the following coefficients:
-- Filter : b0 b1 b2 b3 b4
------------------------------------------
-- 1_Identity : 0 0 1 0 0
-- 2_Edge : 0 -1 8 -1 0
-- 3_SobelX : 0 2 0 -2 0
-- 4_SobelY : 0 0 0 0 0
-- 5_SobelXY : 0 -1 0 1 0
-- 6_Blur : 1 0 0 0 1
-- 7_Smooth : 1 5 44 5 1
-- 8_Sharpen : 0 -2 32 -2 0
-- 9_Gaussian : 2 4 8 4 2
------------------------------------------
constant mask_type : string := "9_Gaussian";
file f_stimuli : text is in "../1x5_Filter/" & mask_type & "/FIR_IN.txt";
file f_exp_resp : text is in "../1x5_Filter/" & mask_type & "/FIR_OUT.txt";
file f_act_resp : text is out "../1x5_Filter/" & mask_type & "/FIR_VHDL_OUT.txt";
begin
-- Instantiate the Unit Under Test
uut : fir_1d_dir
generic map (
IN_DW => IN_DW,
OUT_DW => OUT_DW,
COEF_DW => COEF_DW,
TAPS => TAPS,
DELAY => DELAY
)
port map (
ce_1 => '1',
clk_1 => clk,
load => load,
coef => coef,
din => din,
out_data => out_data
);
-- Clock generation
p_clk :process
begin
wait for t_clk/2;
clk <= not clk;
end process;
-- apply stimuli to UUT
p_stim:process(clk)
variable inline : line;
variable char : character;
begin
if clk'event and clk = '1' then
if not endfile(f_stimuli) then
readline(f_stimuli,inline);
for k in IN_DW-1 downto 0 loop
read(inline,char);
if char = '0' then
din(k) <= '0' after t_stim;
else
din(k) <= '1' after t_stim;
end if;
end loop;
else
-- end of simulation
assert false report "******** End of simulation : " &
"Total Number of Mismatches detected = " &
integer'image(err_cnt) &
" ********"
severity failure;
end if;
end if;
end process;
-- compare expected with actual responses and write output file
p_check: process(clk)
variable line_exp, line_act : line;
variable str_exp, str_act : string(OUT_DW downto 1);
variable do_check : boolean;
begin
if clk'event and clk = '1' then
do_check := true;
-- read expected value from file
readline(f_exp_resp,line_exp);
for k in OUT_DW-1 downto 0 loop
-- get all bits in actual output
if out_data(k) = '0' then
str_act(k+1) := '0';
elsif out_data(k) = '1' then
str_act(k+1) := '1';
else
-- skip checking when output data is 'U'
do_check := false;
end if;
write(line_act,str_act(k+1));
-- get all bits in expected output
read(line_exp,str_exp(k+1));
end loop;
-- write actual value to file
writeline(f_act_resp,line_act);
-- compare actual and expected output vector
if do_check and not (str_exp = str_act) then
assert false report "expected: " & str_exp & " actual: " & str_act severity note;
err_cnt <= err_cnt + 1;
end if;
end if;
end process;
end;
|
gpl-2.0
|
a3159a7691c7427d92b3ae5b29d22e1a
| 0.510934 | 3.551348 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 3/PSRModifier.vhd
| 1 | 1,731 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSRModifier is
Port ( ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : in STD_LOGIC_VECTOR (31 downto 0);
NZVC : out STD_LOGIC_VECTOR (3 downto 0));
end PSRModifier;
architecture Behavioral of PSRModifier is
begin
process(ALUOP,Oper2,Oper1,ALURESULT)
begin
if(ALUOP="010100" or ALUOP="001011" or ALUOP="001100" or ALUOP="001101" or ALUOP="001110" or ALUOP="001111" or ALUOP="010000" or ALUOP="010001" or ALUOP="010011" or ALUOP="010110" or ALUOP="010100")then
--ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc,ADDcc,ADDXcc,SUBcc,SUBXcc
if(ALURESULT="00000000000000000000000000000000") then
NZVC(2)<='1';
else
NZVC(2)<='0';
end if;
NZVC(3)<=ALURESULT(31);
if(ALUOP="001011" or ALUOP="001100" or ALUOP="001101" or ALUOP="001110" or ALUOP="001111" or ALUOP="010000") then
--ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
NZVC(1 downto 0)<="00";
elsif(ALUOP="010001" or ALUOP="010011") then --ADDcc, ADDXcc
NZVC(1)<=((Oper1(31) and Oper2(31) and (not ALURESULT(31))) or ((not Oper1(31)) and (not Oper2(31)) and ALURESULT(31)));
NZVC(0)<=(Oper1(31) and Oper2(31)) or ((not ALURESULT(31)) and (Oper1(31) or Oper2(31)));
else--(ALUOP="010100" or ALUOP="010110") SUBcc, SUBXcc
NZVC(1)<=(Oper1(31) and (not Oper2(31)) and (not ALURESULT(31))) or ((not Oper1(31)) and Oper2(31) and ALURESULT(31));
NZVC(0)<=((not Oper1(31)) and Oper2(31)) or (ALURESULT(31) and ((not Oper1(31)) or Oper2(31)));
end if;
--else
-- NZVC<="1111";
end if;
end process;
end Behavioral;
|
mit
|
8af9eff39dcf5d1c6ba3185393be345d
| 0.642403 | 3.164534 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALU/alu_arithmetic_unit.vhd
| 1 | 1,599 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(7); -- Negative
CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(8) xor arith(7); -- Overflow
CCR(0) <= arith(8); --Carry
RESULT <= arith(7 downto 0);
end Combinational;
|
mit
|
316fc66d4b473426c9268c8e716c3e18
| 0.552846 | 3.522026 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_microblaze_0_xlconcat_0/sim/system_microblaze_0_xlconcat_0.vhd
| 1 | 7,924 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY system_microblaze_0_xlconcat_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END system_microblaze_0_xlconcat_0;
ARCHITECTURE system_microblaze_0_xlconcat_0_arch OF system_microblaze_0_xlconcat_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT xlconcat;
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 7,
NUM_PORTS => 7
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => In6,
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END system_microblaze_0_xlconcat_0_arch;
|
apache-2.0
|
bd7fa0eb99d35bb207176f3e5a1fc449
| 0.631625 | 3.384878 | false | false | false | false |
daniw/add
|
floppy/mcu/cpu_reg.vhd
| 2 | 3,059 |
-------------------------------------------------------------------------------
-- Entity: cpu_reg
-- Author: Waj
-- Date : 28-Feb-14
-------------------------------------------------------------------------------
-- Description:
-- Register block for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 8 * 16
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_reg is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
reg_in : in t_ctr2reg;
reg_out : out t_reg2ctr;
alu_res : in std_logic_vector(DW-1 downto 0);
alu_op1 : out std_logic_vector(DW-1 downto 0);
alu_op2 : out std_logic_vector(DW-1 downto 0)
);
end cpu_reg;
architecture rtl of cpu_reg is
signal reg_blk : t_regblk;
begin
-----------------------------------------------------------------------------
-- Mux input data to ALU combinationally depending on source info from
-- control unit.
-----------------------------------------------------------------------------
alu_op1 <= reg_blk(to_integer(unsigned(reg_in.src1)));
alu_op2 <= reg_blk(to_integer(unsigned(reg_in.src2)));
-----------------------------------------------------------------------------
-- Mux and register data/address to Control Unit depending on source info.
-----------------------------------------------------------------------------
P_mux: process(clk)
begin
if rising_edge(clk) then
reg_out.data <= reg_blk(to_integer(unsigned(reg_in.dest)));
reg_out.addr <= reg_blk(to_integer(unsigned(reg_in.src1)))(AW-1 downto 0);
end if;
end process;
-----------------------------------------------------------------------------
-- CPU register block
-- Store ALU result or data from control unit depending on different enable
-- signals and destination info given from the control unit.
-- Note: Non-zero reset values may be used to allow simulation before the
-- complete instruction set has been implemented.
-----------------------------------------------------------------------------
P_reg: process(rst, clk)
begin
if rst = '1' then
reg_blk <= (others => (others => '0'));
elsif rising_edge(clk) then
if reg_in.enb_res = '1' then
-- store result from ALU
reg_blk(to_integer(unsigned(reg_in.dest))) <= alu_res;
else
if reg_in.enb_data_low = '1' then
-- store low-byte (ld & setil instruction)
reg_blk(to_integer(unsigned(reg_in.dest)))(DW/2-1 downto 0) <= reg_in.data(DW/2-1 downto 0);
end if;
if reg_in.enb_data_high = '1' then
-- store high-byte (ld & setih instruction)
reg_blk(to_integer(unsigned(reg_in.dest)))(DW-1 downto DW/2) <= reg_in.data(DW-1 downto DW/2);
end if;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
142d046046531c9e857ba6243d4b6bb0
| 0.462243 | 4.225138 | false | false | false | false |
daniw/add
|
edk/IVK_HW/t01_hello/hdl/ilmb_cntlr_wrapper.vhd
| 1 | 14,262 |
-------------------------------------------------------------------------------
-- ilmb_cntlr_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_if_cntlr_v3_00_b;
use lmb_bram_if_cntlr_v3_00_b.all;
entity ilmb_cntlr_wrapper is
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to 31);
LMB_WriteDBus : in std_logic_vector(0 to 31);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to 3);
Sl_DBus : out std_logic_vector(0 to 31);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to 3);
BRAM_Addr_A : out std_logic_vector(0 to 31);
BRAM_Din_A : in std_logic_vector(0 to 31);
BRAM_Dout_A : out std_logic_vector(0 to 31);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to 0);
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to 31);
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to 31);
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to 0);
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to 0);
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to 0);
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(31 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(31 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of ilmb_cntlr_wrapper : entity is "lmb_bram_if_cntlr_v3_00_b";
end ilmb_cntlr_wrapper;
architecture STRUCTURE of ilmb_cntlr_wrapper is
component lmb_bram_if_cntlr is
generic (
C_BASEADDR : std_logic_vector(0 to 31);
C_HIGHADDR : std_logic_vector(0 to 31);
C_FAMILY : string;
C_MASK : std_logic_vector(0 to 31);
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_ECC : integer;
C_INTERCONNECT : integer;
C_FAULT_INJECT : integer;
C_CE_FAILING_REGISTERS : integer;
C_UE_FAILING_REGISTERS : integer;
C_ECC_STATUS_REGISTERS : integer;
C_ECC_ONOFF_REGISTER : integer;
C_ECC_ONOFF_RESET_VALUE : integer;
C_CE_COUNTER_WIDTH : integer;
C_WRITE_ACCESS : integer;
C_SPLB_CTRL_BASEADDR : std_logic_vector;
C_SPLB_CTRL_HIGHADDR : std_logic_vector;
C_SPLB_CTRL_AWIDTH : INTEGER;
C_SPLB_CTRL_DWIDTH : INTEGER;
C_SPLB_CTRL_P2P : INTEGER;
C_SPLB_CTRL_MID_WIDTH : INTEGER;
C_SPLB_CTRL_NUM_MASTERS : INTEGER;
C_SPLB_CTRL_SUPPORT_BURSTS : INTEGER;
C_SPLB_CTRL_NATIVE_DWIDTH : INTEGER;
C_S_AXI_CTRL_BASEADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_HIGHADDR : std_logic_vector(31 downto 0);
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to C_LMB_DWIDTH/8-1);
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to ((C_LMB_DWIDTH+8*C_ECC)/8)-1);
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1+8*C_ECC);
Interrupt : out std_logic;
SPLB_CTRL_PLB_ABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_PAValid : in std_logic;
SPLB_CTRL_PLB_masterID : in std_logic_vector(0 to (C_SPLB_CTRL_MID_WIDTH-1));
SPLB_CTRL_PLB_RNW : in std_logic;
SPLB_CTRL_PLB_BE : in std_logic_vector(0 to ((C_SPLB_CTRL_DWIDTH/8)-1));
SPLB_CTRL_PLB_size : in std_logic_vector(0 to 3);
SPLB_CTRL_PLB_type : in std_logic_vector(0 to 2);
SPLB_CTRL_PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_addrAck : out std_logic;
SPLB_CTRL_Sl_SSize : out std_logic_vector(0 to 1);
SPLB_CTRL_Sl_wait : out std_logic;
SPLB_CTRL_Sl_rearbitrate : out std_logic;
SPLB_CTRL_Sl_wrDAck : out std_logic;
SPLB_CTRL_Sl_wrComp : out std_logic;
SPLB_CTRL_Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_CTRL_DWIDTH-1));
SPLB_CTRL_Sl_rdDAck : out std_logic;
SPLB_CTRL_Sl_rdComp : out std_logic;
SPLB_CTRL_Sl_MBusy : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
SPLB_CTRL_PLB_UABus : in std_logic_vector(0 to 31);
SPLB_CTRL_PLB_SAValid : in std_logic;
SPLB_CTRL_PLB_rdPrim : in std_logic;
SPLB_CTRL_PLB_wrPrim : in std_logic;
SPLB_CTRL_PLB_abort : in std_logic;
SPLB_CTRL_PLB_busLock : in std_logic;
SPLB_CTRL_PLB_MSize : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_lockErr : in std_logic;
SPLB_CTRL_PLB_wrBurst : in std_logic;
SPLB_CTRL_PLB_rdBurst : in std_logic;
SPLB_CTRL_PLB_wrPendReq : in std_logic;
SPLB_CTRL_PLB_rdPendReq : in std_logic;
SPLB_CTRL_PLB_wrPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_rdPendPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_reqPri : in std_logic_vector(0 to 1);
SPLB_CTRL_PLB_TAttribute : in std_logic_vector(0 to 15);
SPLB_CTRL_Sl_wrBTerm : out std_logic;
SPLB_CTRL_Sl_rdWdAddr : out std_logic_vector(0 to 3);
SPLB_CTRL_Sl_rdBTerm : out std_logic;
SPLB_CTRL_Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_CTRL_NUM_MASTERS-1));
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector(((C_S_AXI_CTRL_DATA_WIDTH/8)-1) downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector((C_S_AXI_CTRL_ADDR_WIDTH-1) downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH-1) downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic
);
end component;
begin
ilmb_cntlr : lmb_bram_if_cntlr
generic map (
C_BASEADDR => X"00000000",
C_HIGHADDR => X"00007fff",
C_FAMILY => "spartan6",
C_MASK => X"80000000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_SPLB_CTRL_BASEADDR => X"FFFFFFFF",
C_SPLB_CTRL_HIGHADDR => X"00000000",
C_SPLB_CTRL_AWIDTH => 32,
C_SPLB_CTRL_DWIDTH => 32,
C_SPLB_CTRL_P2P => 0,
C_SPLB_CTRL_MID_WIDTH => 1,
C_SPLB_CTRL_NUM_MASTERS => 1,
C_SPLB_CTRL_SUPPORT_BURSTS => 0,
C_SPLB_CTRL_NATIVE_DWIDTH => 32,
C_S_AXI_CTRL_BASEADDR => X"FFFFFFFF",
C_S_AXI_CTRL_HIGHADDR => X"00000000",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
Interrupt => Interrupt,
SPLB_CTRL_PLB_ABus => SPLB_CTRL_PLB_ABus,
SPLB_CTRL_PLB_PAValid => SPLB_CTRL_PLB_PAValid,
SPLB_CTRL_PLB_masterID => SPLB_CTRL_PLB_masterID,
SPLB_CTRL_PLB_RNW => SPLB_CTRL_PLB_RNW,
SPLB_CTRL_PLB_BE => SPLB_CTRL_PLB_BE,
SPLB_CTRL_PLB_size => SPLB_CTRL_PLB_size,
SPLB_CTRL_PLB_type => SPLB_CTRL_PLB_type,
SPLB_CTRL_PLB_wrDBus => SPLB_CTRL_PLB_wrDBus,
SPLB_CTRL_Sl_addrAck => SPLB_CTRL_Sl_addrAck,
SPLB_CTRL_Sl_SSize => SPLB_CTRL_Sl_SSize,
SPLB_CTRL_Sl_wait => SPLB_CTRL_Sl_wait,
SPLB_CTRL_Sl_rearbitrate => SPLB_CTRL_Sl_rearbitrate,
SPLB_CTRL_Sl_wrDAck => SPLB_CTRL_Sl_wrDAck,
SPLB_CTRL_Sl_wrComp => SPLB_CTRL_Sl_wrComp,
SPLB_CTRL_Sl_rdDBus => SPLB_CTRL_Sl_rdDBus,
SPLB_CTRL_Sl_rdDAck => SPLB_CTRL_Sl_rdDAck,
SPLB_CTRL_Sl_rdComp => SPLB_CTRL_Sl_rdComp,
SPLB_CTRL_Sl_MBusy => SPLB_CTRL_Sl_MBusy,
SPLB_CTRL_Sl_MWrErr => SPLB_CTRL_Sl_MWrErr,
SPLB_CTRL_Sl_MRdErr => SPLB_CTRL_Sl_MRdErr,
SPLB_CTRL_PLB_UABus => SPLB_CTRL_PLB_UABus,
SPLB_CTRL_PLB_SAValid => SPLB_CTRL_PLB_SAValid,
SPLB_CTRL_PLB_rdPrim => SPLB_CTRL_PLB_rdPrim,
SPLB_CTRL_PLB_wrPrim => SPLB_CTRL_PLB_wrPrim,
SPLB_CTRL_PLB_abort => SPLB_CTRL_PLB_abort,
SPLB_CTRL_PLB_busLock => SPLB_CTRL_PLB_busLock,
SPLB_CTRL_PLB_MSize => SPLB_CTRL_PLB_MSize,
SPLB_CTRL_PLB_lockErr => SPLB_CTRL_PLB_lockErr,
SPLB_CTRL_PLB_wrBurst => SPLB_CTRL_PLB_wrBurst,
SPLB_CTRL_PLB_rdBurst => SPLB_CTRL_PLB_rdBurst,
SPLB_CTRL_PLB_wrPendReq => SPLB_CTRL_PLB_wrPendReq,
SPLB_CTRL_PLB_rdPendReq => SPLB_CTRL_PLB_rdPendReq,
SPLB_CTRL_PLB_wrPendPri => SPLB_CTRL_PLB_wrPendPri,
SPLB_CTRL_PLB_rdPendPri => SPLB_CTRL_PLB_rdPendPri,
SPLB_CTRL_PLB_reqPri => SPLB_CTRL_PLB_reqPri,
SPLB_CTRL_PLB_TAttribute => SPLB_CTRL_PLB_TAttribute,
SPLB_CTRL_Sl_wrBTerm => SPLB_CTRL_Sl_wrBTerm,
SPLB_CTRL_Sl_rdWdAddr => SPLB_CTRL_Sl_rdWdAddr,
SPLB_CTRL_Sl_rdBTerm => SPLB_CTRL_Sl_rdBTerm,
SPLB_CTRL_Sl_MIRQ => SPLB_CTRL_Sl_MIRQ,
S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY
);
end architecture STRUCTURE;
|
gpl-2.0
|
7baa8b41508b5ce0861081cc2a44a039
| 0.6206 | 2.949132 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/71de/hdl/mdm_v3_2_vh_rfs.vhd
| 1 | 721,019 |
-------------------------------------------------------------------------------
-- mdm_funcs.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_funcs.vhd
--
-- Description: Support functions for mdm
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mdm_funcs.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
package mdm_funcs is
type TARGET_FAMILY_TYPE is (
-- pragma xilinx_rtl_off
non_RTL,
-- pragma xilinx_rtl_on
RTL
);
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE;
end package mdm_funcs;
package body mdm_funcs is
function LowerCase_Char(char : character) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' or char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a'; when 'B' => return 'b'; when 'C' => return 'c'; when 'D' => return 'd';
when 'E' => return 'e'; when 'F' => return 'f'; when 'G' => return 'g'; when 'H' => return 'h';
when 'I' => return 'i'; when 'J' => return 'j'; when 'K' => return 'k'; when 'L' => return 'l';
when 'M' => return 'm'; when 'N' => return 'n'; when 'O' => return 'o'; when 'P' => return 'p';
when 'Q' => return 'q'; when 'R' => return 'r'; when 'S' => return 's'; when 'T' => return 't';
when 'U' => return 'u'; when 'V' => return 'v'; when 'W' => return 'w'; when 'X' => return 'x';
when 'Y' => return 'y'; when 'Z' => return 'z';
when others => return char;
end case;
end LowerCase_Char;
function LowerCase_String (s : string) return string is
variable res : string(s'range);
begin -- function LoweerCase_String
for I in s'range loop
res(I) := LowerCase_Char(s(I));
end loop; -- I
return res;
end function LowerCase_String;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function Equal_String( str1, str2 : string ) return boolean is
constant len1 : integer := str1'length;
constant len2 : integer := str2'length;
variable equal : boolean := true;
begin
if not (len1=len2) then
equal := false;
else
for i in str1'range loop
if not (LowerCase_Char(str1(i)) = LowerCase_Char(str2(i))) then
equal := false;
end if;
end loop;
end if;
return equal;
end Equal_String;
function String_To_Family (S : string; Select_RTL : boolean) return TARGET_FAMILY_TYPE is
begin -- function String_To_Family
if ((Select_RTL) or Equal_String(S, "rtl")) then
return RTL;
else
return non_RTL;
end if;
end function String_To_Family;
end package body mdm_funcs;
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_primitives.vhd
--
-- Description: one bit AND function using carry-chain
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2014-05-23 First Version
-- stefana 2016-06-01 Added wrappers for unisim primitives
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
----- entity BSCANE2 -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_BSCANE2 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_logic := 'H';
DRCK : out std_logic := 'H';
RESET : out std_logic := 'H';
RUNTEST : out std_logic := 'L';
SEL : out std_logic := 'L';
SHIFT : out std_logic := 'L';
TCK : out std_logic := 'L';
TDI : out std_logic := 'L';
TMS : out std_logic := 'L';
UPDATE : out std_logic := 'L';
TDO : in std_logic := 'X'
);
end entity MB_BSCANE2;
library unisim;
use unisim.vcomponents.all;
architecture IMP of MB_BSCANE2 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
assert false report "Illegal use of implementation primitives" severity failure;
end generate Using_RTL;
Use_E2: if ( C_TARGET /= RTL ) generate
begin
BSCANE2_I: BSCANE2
generic map (
DISABLE_JTAG => DISABLE_JTAG,
JTAG_CHAIN => JTAG_CHAIN)
port map (
CAPTURE => CAPTURE,
DRCK => DRCK,
RESET => RESET,
RUNTEST => RUNTEST,
SEL => SEL,
SHIFT => SHIFT,
TCK => TCK,
TDI => TDI,
TMS => TMS,
UPDATE => UPDATE,
TDO => TDO);
end generate Use_E2;
end architecture IMP;
----- entity BUFG -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_BUFG is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I : in std_logic
);
end entity MB_BUFG;
library unisim;
use unisim.vcomponents.all;
architecture IMP of MB_BUFG is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= TO_X01(I);
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: BUFG
port map (
O => O,
I => I
);
end generate Using_FPGA;
end architecture IMP;
----- entity BUFGCTRL -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_BUFGCTRL is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT_OUT : integer := 0;
IS_CE0_INVERTED : bit := '0';
IS_CE1_INVERTED : bit := '0';
IS_I0_INVERTED : bit := '0';
IS_I1_INVERTED : bit := '0';
IS_IGNORE0_INVERTED : bit := '0';
IS_IGNORE1_INVERTED : bit := '0';
IS_S0_INVERTED : bit := '0';
IS_S1_INVERTED : bit := '0';
PRESELECT_I0 : boolean := false;
PRESELECT_I1 : boolean := false
);
port (
O : out std_logic;
CE0 : in std_logic;
CE1 : in std_logic;
I0 : in std_logic;
I1 : in std_logic;
IGNORE0 : in std_logic;
IGNORE1 : in std_logic;
S0 : in std_logic;
S1 : in std_logic
);
end entity MB_BUFGCTRL;
library unisim;
use unisim.vcomponents.all;
architecture IMP of MB_BUFGCTRL is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
assert false report "Illegal use of implementation primitives" severity failure;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: BUFGCTRL
generic map (
INIT_OUT => INIT_OUT,
IS_CE0_INVERTED => IS_CE0_INVERTED,
IS_CE1_INVERTED => IS_CE1_INVERTED,
IS_I0_INVERTED => IS_I0_INVERTED,
IS_I1_INVERTED => IS_I1_INVERTED,
IS_IGNORE0_INVERTED => IS_IGNORE0_INVERTED,
IS_IGNORE1_INVERTED => IS_IGNORE1_INVERTED,
IS_S0_INVERTED => IS_S0_INVERTED,
IS_S1_INVERTED => IS_S1_INVERTED,
PRESELECT_I0 => PRESELECT_I0,
PRESELECT_I1 => PRESELECT_I1
)
port map (
O => O,
CE0 => CE0,
CE1 => CE1,
I0 => I0,
I1 => I1,
IGNORE0 => IGNORE0,
IGNORE1 => IGNORE1,
S0 => S0,
S1 => S1
);
end generate Using_FPGA;
end architecture IMP;
----- entity FDRE -----
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_FDRE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end entity MB_FDRE;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_FDRE is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
function To_StdLogic(A : in bit ) return std_logic is
begin
if( A = '1' ) then
return '1';
end if;
return '0';
end;
signal q_o : std_logic := To_StdLogic(INIT);
begin
Q <= q_o;
process(C)
begin
if (rising_edge(C)) then
if (R = '1') then
q_o <= '0';
elsif (CE = '1') then
q_o <= D;
end if;
end if;
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: FDRE
generic map(
INIT => INIT
)
port map(
Q => Q,
C => C,
CE => CE,
D => D,
R => R
);
end generate Using_FPGA;
end architecture IMP;
----- entity PLLE2_BASE -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_PLLE2_BASE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.000;
CLKIN1_PERIOD : real := 0.000;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.010;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
PWRDWN : in std_logic;
RST : in std_logic
);
end entity MB_PLLE2_BASE;
library unisim;
use unisim.vcomponents.all;
architecture IMP of MB_PLLE2_BASE is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
assert false report "Illegal use of implementation primitives" severity failure;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: PLLE2_BASE
generic map (
BANDWIDTH => BANDWIDTH,
CLKFBOUT_MULT => CLKFBOUT_MULT,
CLKFBOUT_PHASE => CLKFBOUT_PHASE,
CLKIN1_PERIOD => CLKIN1_PERIOD,
CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
CLKOUT0_DUTY_CYCLE => CLKOUT0_DUTY_CYCLE,
CLKOUT0_PHASE => CLKOUT0_PHASE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT1_DUTY_CYCLE => CLKOUT1_DUTY_CYCLE,
CLKOUT1_PHASE => CLKOUT1_PHASE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT2_DUTY_CYCLE => CLKOUT2_DUTY_CYCLE,
CLKOUT2_PHASE => CLKOUT2_PHASE,
CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
CLKOUT3_DUTY_CYCLE => CLKOUT3_DUTY_CYCLE,
CLKOUT3_PHASE => CLKOUT3_PHASE,
CLKOUT4_DIVIDE => CLKOUT4_DIVIDE,
CLKOUT4_DUTY_CYCLE => CLKOUT4_DUTY_CYCLE,
CLKOUT4_PHASE => CLKOUT4_PHASE,
CLKOUT5_DIVIDE => CLKOUT5_DIVIDE,
CLKOUT5_DUTY_CYCLE => CLKOUT5_DUTY_CYCLE,
CLKOUT5_PHASE => CLKOUT5_PHASE,
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
REF_JITTER1 => REF_JITTER1,
STARTUP_WAIT => STARTUP_WAIT
)
port map (
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1,
CLKOUT2 => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
LOCKED => LOCKED,
CLKFBIN => CLKFBIN,
CLKIN1 => CLKIN1,
PWRDWN => PWRDWN,
RST => RST
);
end generate Using_FPGA;
end architecture IMP;
----- entity FDC_1 -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_FDC_1 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end entity MB_FDC_1;
library unisim;
use unisim.vcomponents.all;
architecture IMP of MB_FDC_1 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
signal q_out : std_logic := TO_X01(INIT);
begin
Q <= q_out;
FunctionalBehavior : process(C, CLR)
begin
if CLR = '1' then
q_out <= '0';
elsif (falling_edge(C)) then
q_out <= D;
end if;
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: FDC_1
generic map (
INIT => INIT
)
port map (
Q => Q,
C => C,
CLR => CLR,
D => D
);
end generate Using_FPGA;
end architecture IMP;
----- entity FDRE_1 -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_FDRE_1 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end entity MB_FDRE_1;
library unisim;
use unisim.vcomponents.all;
architecture IMP of MB_FDRE_1 is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
signal q_out : std_logic := TO_X01(INIT);
begin
Q <= q_out;
FunctionalBehavior : process(C)
begin
if C'EVENT and C = '0' then
if R = '1' then
q_out <= '0';
elsif CE = '1' or CE = 'Z' then
q_out <= D;
end if;
end if;
end process;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: FDRE_1
generic map (
INIT => INIT
)
port map (
Q => Q,
C => C,
CE => CE,
D => D,
R => R
);
end generate Using_FPGA;
end architecture IMP;
----- entity SRL16E -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_SRL16E is
generic(
C_TARGET : TARGET_FAMILY_TYPE;
C_STATIC : boolean := false;
INIT : bit_vector := X"0000");
port(
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic);
end entity MB_SRL16E;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.numeric_std.all;
architecture IMP of MB_SRL16E is
begin -- architecture IMP
Use_unisim: if ( C_TARGET /= RTL ) generate
MB_SRL16E_I1: SRL16E
generic map (
INIT => INIT) -- [bit_vector]
port map (
Q => Q, -- [out std_logic]
A0 => A0, -- [in std_logic]
A1 => A1, -- [in std_logic]
A2 => A2, -- [in std_logic]
A3 => A3, -- [in std_logic]
CE => CE, -- [in std_logic]
CLK => CLK, -- [in std_logic]
D => D); -- [in std_logic]
end generate Use_unisim;
Use_RTL : if ( C_TARGET = RTL ) generate
signal shift_reg : std_logic_vector(15 downto 0) := to_stdLogicVector(INIT);
constant shift_reg_const : std_logic_vector(15 downto 0) := to_stdLogicVector(INIT);
attribute shreg_extract : string;
attribute shreg_extract of SHIFT_REG : signal is "no";
begin
Static_Values: if (C_STATIC) generate
begin
Q <= shift_reg_const(to_integer(unsigned(to_stdLogicVector(A3 & A2 & A1 & A0))));
end generate Static_Values;
Dynamic_Values: if (not C_STATIC) generate
begin
Q <= shift_reg(to_integer(unsigned(to_stdLogicVector(A3 & A2 & A1 & A0))));
process(CLK)
begin
if (rising_edge(CLK)) then
if CE = '1' then
shift_reg <= shift_reg(14 downto 0) & D;
end if;
end if;
end process;
end generate Dynamic_Values;
end generate Use_RTL;
end architecture IMP;
----- entity FDRSE -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_FDRSE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0';
IS_CE_INVERTED : bit := '0';
IS_C_INVERTED : bit := '0';
IS_D_INVERTED : bit := '0';
IS_R_INVERTED : bit := '0';
IS_S_INVERTED : bit := '0'
);
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end entity MB_FDRSE;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.numeric_std.all;
architecture IMP of MB_FDRSE is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
signal q_out : std_logic := TO_X01(INIT);
signal ce_in : std_logic;
signal d_in : std_logic;
signal s_in : std_logic;
signal r_in : std_logic;
signal IS_CE_INVERTED_BIN : std_logic := TO_X01(IS_CE_INVERTED);
signal IS_D_INVERTED_BIN : std_logic := TO_X01(IS_D_INVERTED);
signal IS_S_INVERTED_BIN : std_logic := TO_X01(IS_S_INVERTED);
signal IS_R_INVERTED_BIN : std_logic := TO_X01(IS_R_INVERTED);
begin
Q <= q_out;
ce_in <= IS_CE_INVERTED_BIN xor CE;
d_in <= IS_D_INVERTED_BIN xor D;
s_in <= IS_S_INVERTED_BIN xor S;
r_in <= IS_R_INVERTED_BIN xor R;
Rising: if IS_C_INVERTED = '0' generate
begin
FunctionalBehavior : process(C)
begin
if (rising_edge(C)) then
if (r_in = '1') then
q_out <= '0';
elsif (s_in = '1') then
q_out <= '1';
elsif (ce_in = '1') then
q_out <= D;
end if;
end if;
end process;
end generate Rising;
Falling: if IS_C_INVERTED /= '0' generate
begin
FunctionalBehavior : process(C)
begin
if (falling_edge(C)) then
if (r_in = '1') then
q_out <= '0';
elsif (s_in = '1') then
q_out <= '1';
elsif (ce_in = '1') then
q_out <= D;
end if;
end if;
end process;
end generate Falling;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: FDRSE
generic map (
INIT => INIT,
IS_C_INVERTED => IS_C_INVERTED,
IS_CE_INVERTED => IS_CE_INVERTED,
IS_D_INVERTED => IS_D_INVERTED,
IS_R_INVERTED => IS_R_INVERTED,
IS_S_INVERTED => IS_S_INVERTED
)
port map (
Q => Q,
C => C,
CE => CE,
R => R,
S => S,
D => D
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXCY with XORCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_MUXCY_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end entity MB_MUXCY_XORCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXCY_XORCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= (CI xor S);
LO <= DI when S = '0' else CI;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native_I1: MUXCY_L
port map(
LO => LO,
CI => CI,
DI => DI,
S => S
);
Native_I2: XORCY
port map(
O => O,
CI => CI,
LI => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity MUXCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end entity MB_MUXCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_MUXCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
LO <= DI when S = '0' else CI;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: MUXCY_L
port map(
LO => LO,
CI => CI,
DI => DI,
S => S
);
end generate Using_FPGA;
end architecture IMP;
----- entity XORCY -----
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end entity MB_XORCY;
library Unisim;
use Unisim.vcomponents.all;
architecture IMP of MB_XORCY is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
begin
O <= (CI xor LI);
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: XORCY
port map(
O => O,
CI => CI,
LI => LI
);
end generate Using_FPGA;
end architecture IMP;
----- entity SRLC32E -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MB_SRLC32E is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"00000000";
IS_CLK_INVERTED : bit := '0'
);
port (
Q : out STD_LOGIC;
Q31 : out STD_LOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0) := "00000";
CE : in STD_LOGIC;
CLK : in STD_LOGIC;
D : in STD_LOGIC
);
end entity MB_SRLC32E;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.numeric_std.all;
architecture IMP of MB_SRLC32E is
begin
Using_RTL: if ( C_TARGET = RTL ) generate
signal shift_reg : std_logic_vector(31 downto 0) := to_stdLogicVector(INIT);
attribute shreg_extract : string;
attribute shreg_extract of shift_reg : signal is "no";
begin
Q <= shift_reg(to_integer(unsigned(A)));
Q31 <= shift_reg(31);
Rising: if IS_CLK_INVERTED = '0' generate
begin
process(CLK)
begin
if (rising_edge(CLK)) then
if CE = '1' then
shift_reg <= shift_reg(30 downto 0) & D;
end if;
end if;
end process;
end generate Rising;
Falling: if IS_CLK_INVERTED /= '0' generate
begin
process(CLK)
begin
if (falling_edge(CLK)) then
if CE = '1' then
shift_reg <= shift_reg(30 downto 0) & D;
end if;
end if;
end process;
end generate Falling;
end generate Using_RTL;
Using_FPGA: if ( C_TARGET /= RTL ) generate
begin
Native: SRLC32E
generic map (
INIT => INIT,
IS_CLK_INVERTED => IS_CLK_INVERTED
)
port map (
Q => Q,
Q31 => Q31,
A => A,
CE => CE,
CLK => CLK,
D => D
);
end generate Using_FPGA;
end architecture IMP;
----- entity carry_and -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity carry_and is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_and;
architecture IMP of carry_and is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
signal carry_out_i : std_logic;
begin -- architecture IMP
MUXCY_I : MB_MUXCY
generic map (
C_TARGET => C_TARGET
)
port map (
DI => '0',
CI => Carry_IN,
S => A,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
----- entity carry_or_vec -----
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity carry_or_vec is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end entity carry_or_vec;
architecture IMP of carry_or_vec is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
constant C_BITS_PER_LUT : natural := 6;
signal sel : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));
signal sig1 : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
begin -- architecture IMP
assign_sigs : process (In_Vec) is
begin -- process assign_sigs
sig1 <= (others => '0');
sig1(0 to Size-1) <= In_Vec;
end process assign_sigs;
carry(carry'right) <= Carry_In;
The_Compare : for I in sel'right downto sel'left generate
begin
Compare_All_Bits: process(sig1)
variable sel_I : std_logic;
begin
sel_I := '0';
Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
sel_I := sel_I or ( sig1(C_BITS_PER_LUT * I + J) );
end loop Compare_Bits;
sel(I) <= not sel_I;
end process Compare_All_Bits;
MUXCY_L_I1 : MB_MUXCY
generic map (
C_TARGET => C_TARGET
)
port map (
DI => '1', -- [in std_logic S = 0]
CI => Carry(I+1), -- [in std_logic S = 1]
S => sel(I), -- [in std_logic (Select)]
LO => Carry(I)); -- [out std_logic]
end generate The_Compare;
Carry_Out <= Carry(0);
end architecture IMP;
----- entity carry_or -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity carry_or is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_or;
architecture IMP of carry_or is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
signal carry_out_i : std_logic;
signal A_N : std_logic;
begin -- architecture IMP
A_N <= not A;
MUXCY_I : MB_MUXCY
generic map (
C_TARGET => C_TARGET
)
port map (
DI => '1',
CI => Carry_IN,
S => A_N,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
----- entity select_bit -----
library ieee;
use ieee.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity select_bit is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end entity select_bit;
architecture IMP of select_bit is
component MB_MUXCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY;
signal di : std_logic;
signal sel : std_logic;
begin -- architecture IMP
-- Just pass the carry value if none is requesting or is enabled
sel <= not( (Request(1) and Mask(1)) or (Request(0) and Mask(0)));
di <= ((Request(0) and Mask(0) and sel_value(0))) or
( not(Request(0) and Mask(0)) and Request(1) and Mask(1) and sel_value(1));
MUXCY_I : MB_MUXCY
generic map (
C_TARGET => C_TARGET
)
port map (
DI => di,
CI => Carry_In,
S => sel,
LO => Carry_Out);
end architecture IMP;
-------------------------------------------------------------------------------
-- arbiter.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: arbiter.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- arbiter.vhd
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2014/05/08 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity Arbiter is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Size : natural := 32;
Size_Log2 : natural := 5);
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
Requests : in std_logic_vector(Size-1 downto 0);
Granted : out std_logic_vector(Size-1 downto 0);
Valid_Sel : out std_logic;
Selected : out std_logic_vector(Size_Log2-1 downto 0));
end entity Arbiter;
architecture IMP of Arbiter is
component select_bit
generic (
C_TARGET : TARGET_FAMILY_TYPE;
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end component select_bit;
component carry_or_vec
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end component carry_or_vec;
component carry_and
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end component carry_and;
component carry_or
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end component carry_or;
subtype index_type is std_logic_vector(Size_Log2-1 downto 0);
type int_array_type is array (natural range 2*Size-1 downto 0) of index_type;
function init_index_table return int_array_type is
variable tmp : int_array_type;
begin -- function init_index_table
for I in 0 to Size-1 loop
tmp(I) := std_logic_vector(to_unsigned(I, Size_Log2));
tmp(Size+I) := std_logic_vector(to_unsigned(I, Size_Log2));
end loop; -- I
return tmp;
end function init_index_table;
constant index_table : int_array_type := init_index_table;
signal long_req : std_logic_vector(2*Size-1 downto 0);
signal mask : std_logic_vector(2*Size-1 downto 0);
signal grant_sel : std_logic_vector(Size_Log2-1 downto 0);
signal new_granted : std_logic;
signal reset_loop : std_logic;
signal mask_reset : std_logic;
signal valid_grant : std_logic;
begin -- architecture IMP
long_req <= Requests & Requests;
Request_Or : carry_or_vec
generic map (
C_TARGET => C_TARGET,
Size => Size)
port map (
Carry_In => Enable,
In_Vec => Requests, -- in
Carry_Out => new_granted); -- out
Valid_Sel <= new_granted;
-----------------------------------------------------------------------------
-- Generate Carry-Chain structure
-----------------------------------------------------------------------------
Chain: for I in Size_Log2-1 downto 0 generate
signal carry : std_logic_vector(Size downto 0); -- Assumes 2 bit/muxcy
begin -- generate Bits
carry(Size) <= '0';
Bits: for J in Size-1 downto 0 generate
constant sel1 : std_logic := index_table(2*J+1)(I);
constant sel0 : std_logic := index_table(2*J)(I);
attribute keep_hierarchy : string;
attribute keep_hierarchy of Select_bits : label is "yes";
begin -- generate Bits
Select_bits : select_bit
generic map (
C_TARGET => C_TARGET,
sel_value => sel1 & sel0)
port map (
Mask => mask(2*J+1 downto 2*J), -- in
Request => long_req(2*J+1 downto 2*J), -- in
Carry_In => carry(J+1), -- in
Carry_Out => carry(J)); -- out
end generate Bits;
grant_sel(I) <= carry(0);
end generate Chain;
Selected <= grant_sel;
-----------------------------------------------------------------------------
-- Handling Mask value
-----------------------------------------------------------------------------
-- if (Reset = '1') or ((new_granted and mask(1)) = '1') then
Reset_loop_and : carry_and
generic map (
C_TARGET => C_TARGET)
port map (
Carry_IN => new_granted, -- in
A => mask(1), -- in
Carry_OUT => reset_loop); -- out
Mask_Reset_carry : carry_or
generic map (
C_TARGET => C_TARGET)
port map (
Carry_IN => reset_loop, -- in
A => Reset, -- in
Carry_OUT => mask_reset); -- out
Mask_Handler : process (Clk) is
begin -- process Mask_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (mask_reset = '1') then -- synchronous reset (active high)
mask(2*Size-1 downto Size) <= (others => '1');
mask(Size-1 downto 0) <= (others => '0');
else
if (new_granted = '1') then
mask(2*Size-1 downto 1) <= mask(1) & mask(2*Size-1 downto 2);
end if;
end if;
end if;
end process Mask_Handler;
-----------------------------------------------------------------------------
-- Generate grant signal
-----------------------------------------------------------------------------
Grant_Signals: for K in Size-1 downto 1 generate
signal tmp : std_logic;
attribute keep : string;
attribute keep of tmp : signal is "true";
begin -- generate Grant_Signals
tmp <= '1' when (K = to_integer(unsigned(grant_sel))) else '0';
granted(K) <= tmp;
end generate Grant_Signals;
Granted(0) <= Requests(0) when to_integer(unsigned(grant_sel)) = 0 else '0';
end architecture IMP;
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2001-06-12 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2013-11-01 Added support for depth 32
-- stefana 2016-06-01 Added wrappers for unisim primitives
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity SRL_FIFO is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
component MB_MUXCY_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MB_MUXCY_XORCY;
component MB_XORCY is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component MB_XORCY;
component MB_FDRE is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component MB_FDRE;
component MB_SRL16E is
generic(
C_TARGET : TARGET_FAMILY_TYPE;
C_STATIC : boolean := false;
INIT : bit_vector := X"0000");
port(
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component MB_SRL16E;
component MB_SRLC32E
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"00000000";
IS_CLK_INVERTED : bit := '0'
);
port (
Q : out STD_LOGIC;
Q31 : out STD_LOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0) := "00000";
CE : in STD_LOGIC;
CLK : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
constant C_ADDR_BITS : integer := 4 + boolean'pos(C_DEPTH = 32);
signal Addr : std_logic_vector(0 to C_ADDR_BITS - 1);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic := '0';
signal data_Exists_I : std_logic := '0';
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal sum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal addr_cy : std_logic_vector(0 to C_ADDR_BITS - 1);
begin -- architecture IMP
assert (C_DEPTH = 16) or (C_DEPTH = 32) report "SRL FIFO: C_DEPTH must be 16 or 32" severity FAILURE;
buffer_Full <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '1')) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '0')) else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to C_ADDR_BITS - 1 generate
begin
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(C_ADDR_BITS) is not used anywhere
Used_MuxCY: if I < C_ADDR_BITS - 1 generate
begin
MUXCY_L_I : MB_MUXCY_XORCY
generic map (
C_TARGET => C_TARGET
)
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
O => sum_A(I), -- [out std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
No_MuxCY: if I = C_ADDR_BITS - 1 generate
begin
XORCY_I : MB_XORCY
generic map (
C_TARGET => C_TARGET
)
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
end generate No_MuxCY;
FDRE_I : MB_FDRE
generic map (
C_TARGET => C_TARGET
)
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS - 1 generate
begin
D16 : if C_DEPTH = 16 generate
begin
SRL16E_I : MB_SRL16E
generic map (
C_TARGET => C_TARGET,
INIT => x"0000"
)
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D16;
D32 : if C_DEPTH = 32 generate
begin
SRLC32E_I : MB_SRLC32E
generic map (
C_TARGET => C_TARGET,
INIT => x"00000000")
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
CLK => Clk, -- [in std_logic]
A(4) => Addr(4), -- [in std_logic]
A(3) => Addr(3), -- [in std_logic]
A(2) => Addr(2), -- [in std_logic]
A(1) => Addr(1), -- [in std_logic]
A(0) => Addr(0), -- [in std_logic]
Q31 => open, -- [out std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D32;
end generate FIFO_RAM;
end architecture IMP;
-------------------------------------------------------------------------------
-- bus_master.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: bus_master.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- bus_master.vhd
-- - srl_fifo
-- - srl_fifo
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2013-11-01 First Version
-- stefana 2013-06-15 Added direct write port
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity bus_master is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_M_AXI_DATA_WIDTH : natural := 32;
C_M_AXI_THREAD_ID_WIDTH : natural := 4;
C_M_AXI_ADDR_WIDTH : natural := 32;
C_DATA_SIZE : natural := 32;
C_HAS_FIFO_PORTS : boolean := true;
C_HAS_DIRECT_PORT : boolean := false
);
port (
-- Bus read and write transaction
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
-- Bus read and write data
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
-- Direct write port
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
-- LMB bus
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- AXI bus
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end entity bus_master;
library IEEE;
use ieee.numeric_std.all;
library mdm_v3_2_8;
use mdm_v3_2_8.all;
architecture IMP of bus_master is
component SRL_FIFO is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_DATA_BITS : natural;
C_DEPTH : natural
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end component SRL_FIFO;
-- Calculate WSTRB given size and low address bits
function Calc_WSTRB (Wr_Size : std_logic_vector(1 downto 0);
Wr_Addr : std_logic_vector(1 downto 0)) return std_logic_vector is
begin
if Wr_Size = "00" then -- Byte
case Wr_Addr is
when "00" => return "0001";
when "01" => return "0010";
when "10" => return "0100";
when "11" => return "1000";
when others => null;
end case;
end if;
if Wr_Size = "01" then -- Halfword
if Wr_Addr(1) = '0' then
return "0011";
else
return "1100";
end if;
end if;
return "1111"; -- Word
end function Calc_WSTRB;
type wr_state_type is (idle, start, wait_on_ready, wait_on_bchan);
signal wr_state : wr_state_type;
signal wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal wstrb : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
signal axi_wvalid : std_logic; -- internal M_AXI_WVALID
signal axi_wr_start : std_logic; -- LMB did not respond, start AXI write
signal axi_wr_idle : std_logic; -- AXI write is idle
signal axi_wr_resp : std_logic_vector(1 downto 0); -- AXI write response
signal axi_do_read : std_logic; -- read word from write FIFO for AXI
signal axi_dwr_addr : std_logic_vector(31 downto 0);
signal axi_dwr_len : std_logic_vector(4 downto 0);
signal axi_dwr_size : std_logic_vector(1 downto 0);
signal axi_dwr_exclusive : std_logic;
signal axi_dwr_start : std_logic;
signal axi_dwr_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal axi_dwr_wstrb : std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
signal axi_dwr_sel : std_logic;
signal axi_dwr_done : std_logic;
begin -- architecture IMP
assert (C_DATA_SIZE = C_M_AXI_DATA_WIDTH)
report "LMB and AXI data widths must be the same" severity FAILURE;
Has_FIFO: if C_HAS_FIFO_PORTS generate
type lmb_state_type is (idle, start_rd, wait_rd, start_wr, wait_wr, sample_rd, sample_wr, direct_wr);
type rd_state_type is (idle, start, wait_on_ready, wait_on_data);
signal lmb_state : lmb_state_type;
signal rd_state : rd_state_type;
signal reset : std_logic;
signal rdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal do_read : std_logic;
signal do_write : std_logic;
signal lmb_addr : std_logic_vector(4 downto 0); -- LMB word address
signal lmb_addr_next : std_logic_vector(4 downto 0); -- LMB word address incremented
signal lmb_len : std_logic_vector(4 downto 0); -- LMB length
signal lmb_len_next : std_logic_vector(4 downto 0); -- LMB length decremented
signal lmb_rd_idle : std_logic; -- LMB read is idle
signal lmb_wr_idle : std_logic; -- LMB write is idle
signal lmb_rd_resp : std_logic_vector(1 downto 0); -- LMB read response
signal lmb_wr_resp : std_logic_vector(1 downto 0); -- LMB write response
signal axi_rready : std_logic; -- internal M_AXI_RREADY
signal axi_rd_start : std_logic; -- LMB did not respond, start AXI read
signal axi_rd_idle : std_logic; -- AXI read is idle
signal axi_rd_resp : std_logic_vector(1 downto 0); -- AXI read response
signal axi_do_write : std_logic; -- write word to read FIFO for AXI
signal wdata_exists : std_logic; -- write FIFO has data
begin
reset <= not M_AXI_ARESETn;
-- Read FIFO instantiation
Read_FIFO : SRL_FIFO
generic map (
C_TARGET => C_TARGET,
C_DATA_BITS => 32,
C_DEPTH => 32
)
port map (
Clk => M_AXI_ACLK,
Reset => reset,
FIFO_Write => do_write,
Data_In => rdata,
FIFO_Read => Data_Rd,
Data_Out => Data_Out,
FIFO_Full => open,
Data_Exists => Data_Exists
);
-- Write FIFO instantiation
Write_FIFO : SRL_FIFO
generic map (
C_TARGET => C_TARGET,
C_DATA_BITS => 32,
C_DEPTH => 32
)
port map (
Clk => M_AXI_ACLK,
Reset => reset,
FIFO_Write => Data_Wr,
Data_In => Data_In,
FIFO_Read => do_read,
Data_Out => wdata,
FIFO_Full => open,
Data_Exists => wdata_exists
);
-- Common signals
Data_Empty <= not wdata_exists;
Rd_Idle <= lmb_rd_idle and axi_rd_idle;
Rd_Response <= lmb_rd_resp or axi_rd_resp;
Wr_Idle <= lmb_wr_idle and axi_wr_idle;
Wr_Response <= lmb_wr_resp or axi_wr_resp;
wstrb <= Calc_WSTRB(Wr_Size, Wr_Addr(1 downto 0));
rdata <= LMB_Data_Read when (LMB_Ready = '1' and lmb_rd_idle = '0') else M_AXI_RDATA;
do_write <= (LMB_Ready and not lmb_rd_idle) or axi_do_write;
do_read <= (LMB_Ready and not lmb_wr_idle) or axi_do_read;
-- LMB implementation
LMB_Data_Addr <= Wr_Addr(C_M_AXI_ADDR_WIDTH-1 downto 7) & lmb_addr & Wr_Addr(1 downto 0);
LMB_Data_Write <= wdata;
LMB_Byte_Enable <= wstrb;
lmb_addr_next <= std_logic_vector(unsigned(lmb_addr) + 1);
lmb_len_next <= std_logic_vector(unsigned(lmb_len) - 1);
LMB_Executing : process (M_AXI_ACLK) is
variable ue : std_logic;
begin -- process LMB_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then
if (M_AXI_ARESETn = '0') then
lmb_state <= idle;
axi_dwr_sel <= '0';
axi_rd_start <= '0';
axi_wr_start <= '0';
lmb_addr <= (others => '0');
lmb_rd_idle <= '1';
lmb_wr_idle <= '1';
lmb_len <= (others => '0');
lmb_rd_resp <= "00";
lmb_wr_resp <= "00";
ue := '0';
LMB_Addr_Strobe <= '0';
LMB_Read_Strobe <= '0';
LMB_Write_Strobe <= '0';
else
axi_rd_start <= '0';
axi_wr_start <= '0';
case lmb_state is
when idle =>
lmb_addr <= Wr_Addr(6 downto 2);
lmb_len <= Wr_Len;
lmb_rd_idle <= '1';
lmb_wr_idle <= '1';
ue := '0';
if (Direct_Wr_Start = '1' and C_HAS_DIRECT_PORT) then
lmb_state <= direct_wr;
axi_dwr_sel <= '1';
end if;
if (Rd_Start = '1') then
lmb_state <= start_rd;
axi_dwr_sel <= '0';
lmb_rd_idle <= '0';
lmb_rd_resp <= "00";
LMB_Addr_Strobe <= '1';
LMB_Read_Strobe <= '1';
end if;
if (Wr_Start = '1') then
lmb_state <= start_wr;
axi_dwr_sel <= '0';
lmb_wr_idle <= '0';
lmb_wr_resp <= "00";
LMB_Addr_Strobe <= '1';
LMB_Write_Strobe <= '1';
end if;
when start_rd =>
lmb_state <= wait_rd;
LMB_Addr_Strobe <= '0';
LMB_Read_Strobe <= '0';
when wait_rd =>
lmb_state <= sample_rd;
when sample_rd =>
if (LMB_Ready = '1') then
if (lmb_len = (lmb_len'range => '0')) then
lmb_state <= idle;
else
lmb_state <= start_rd;
LMB_Addr_Strobe <= '1';
LMB_Read_Strobe <= '1';
end if;
lmb_addr <= lmb_addr_next;
lmb_len <= lmb_len_next;
ue := LMB_UE or ue;
lmb_rd_resp <= ue & '0';
elsif (LMB_Wait = '0') then
lmb_state <= idle;
axi_rd_start <= '1';
end if;
when start_wr =>
lmb_state <= wait_wr;
LMB_Addr_Strobe <= '0';
LMB_Write_Strobe <= '0';
when wait_wr =>
lmb_state <= sample_wr;
when sample_wr =>
if (LMB_Ready = '1') then
if (lmb_len = (lmb_len'range => '0')) then
lmb_state <= idle;
else
lmb_state <= start_wr;
LMB_Addr_Strobe <= '1';
LMB_Write_Strobe <= '1';
end if;
lmb_addr <= lmb_addr_next;
lmb_len <= lmb_len_next;
ue := LMB_UE or ue;
lmb_wr_resp <= ue & '0';
elsif (LMB_Wait = '0') then
lmb_state <= idle;
axi_wr_start <= '1';
end if;
when direct_wr => -- Handle AXI direct write
if axi_dwr_done = '1' and Direct_Wr_Start = '0' then
lmb_state <= idle;
axi_dwr_sel <= '0';
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process LMB_Executing;
-- AXI Read FSM
Rd_Executing : process (M_AXI_ACLK) is
variable rd_resp : std_logic_vector(1 downto 0);
begin -- process Rd_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then -- rising clock edge
if (M_AXI_ARESETn = '0') then -- synchronous reset (active low)
rd_resp := "00";
axi_rready <= '0';
axi_rd_idle <= '1';
axi_rd_resp <= "00";
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= "010"; -- 32-bit accesses
M_AXI_ARLOCK <= '0'; -- No locking
M_AXI_ARVALID <= '0';
rd_state <= idle;
else
case rd_state is
when idle =>
rd_resp := "00";
axi_rd_idle <= '1';
if axi_rd_start = '1' then
rd_state <= start;
axi_rd_idle <= '0';
axi_rd_resp <= "00";
end if;
when start =>
M_AXI_ARVALID <= '1';
M_AXI_ARADDR <= Rd_Addr;
M_AXI_ARLEN <= "000" & Rd_Len;
M_AXI_ARSIZE <= "0" & Rd_Size;
M_AXI_ARLOCK <= Rd_Exclusive;
rd_state <= wait_on_ready;
when wait_on_ready =>
if (M_AXI_ARREADY = '1') then
M_AXI_ARVALID <= '0';
axi_rready <= '1';
rd_state <= wait_on_data;
end if;
when wait_on_data =>
if (M_AXI_RVALID = '1') then
if rd_resp = "00" and M_AXI_RRESP /= "00" then
rd_resp := M_AXI_RRESP; -- Sticky error response
end if;
if (M_AXI_RLAST = '1') then
rd_state <= idle;
axi_rd_resp <= rd_resp;
axi_rready <= '0';
end if;
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process Rd_Executing;
axi_do_write <= axi_rready and M_AXI_RVALID;
end generate Has_FIFO;
No_FIFO: if not C_HAS_FIFO_PORTS generate
type state_type is (idle, direct_wr);
signal state : state_type;
begin
Rd_Idle <= '1';
Rd_Response <= "00";
Data_Out <= (others => '0');
Data_Exists <= '0';
Data_Empty <= '0';
Wr_Idle <= '0';
Wr_Response <= "00";
LMB_Data_Addr <= (others => '0');
LMB_Data_Write <= (others => '0');
LMB_Addr_Strobe <= '0';
LMB_Read_Strobe <= '0';
LMB_Write_Strobe <= '0';
LMB_Byte_Enable <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARVALID <= '0';
wdata <= (others => '0');
wstrb <= (others => '0');
axi_wr_start <= '0';
AXI_Direct_Write: process (M_AXI_ACLK) is
begin -- process AXI_Direct_Write
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then -- rising clock edge
if (M_AXI_ARESETn = '0') then -- synchronous reset (active low)
state <= idle;
axi_dwr_sel <= '0';
else
case state is
when idle =>
if Direct_Wr_Start = '1' then
state <= direct_wr;
axi_dwr_sel <= '1';
end if;
when direct_wr =>
if axi_dwr_done = '1' and Direct_Wr_Start = '0' then
state <= idle;
axi_dwr_sel <= '0';
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process AXI_Direct_Write;
end generate No_FIFO;
Has_Direct_Write: if C_HAS_DIRECT_PORT generate
begin
Direct_Wr_Next <= axi_do_read when axi_dwr_sel = '1' else '0';
Direct_Wr_Done <= axi_dwr_done when axi_dwr_sel = '1' else '0';
Direct_Wr_Resp <= axi_wr_resp;
axi_dwr_addr <= Direct_Wr_Addr when axi_dwr_sel = '1' else Wr_Addr;
axi_dwr_len <= Direct_Wr_Len when axi_dwr_sel = '1' else Wr_Len;
axi_dwr_size <= "10" when axi_dwr_sel = '1' else Wr_Size;
axi_dwr_exclusive <= '0' when axi_dwr_sel = '1' else Wr_Exclusive;
axi_dwr_start <= Direct_Wr_Start when axi_dwr_sel = '1' else axi_wr_start;
axi_dwr_wdata <= Direct_Wr_Data when axi_dwr_sel = '1' else wdata;
axi_dwr_wstrb <= "1111" when axi_dwr_sel = '1' else wstrb;
end generate Has_Direct_Write;
No_Direct_Write: if not C_HAS_DIRECT_PORT generate
begin
Direct_Wr_Next <= '0';
Direct_Wr_Done <= '0';
Direct_Wr_Resp <= "00";
axi_dwr_addr <= Wr_Addr;
axi_dwr_len <= Wr_Len;
axi_dwr_size <= Wr_Size;
axi_dwr_exclusive <= Wr_Exclusive;
axi_dwr_start <= axi_wr_start;
axi_dwr_wdata <= wdata;
axi_dwr_wstrb <= wstrb;
end generate No_Direct_Write;
-- AW signals constant values
M_AXI_AWPROT <= "010"; -- Non-secure data accesses only
M_AXI_AWQOS <= "0000"; -- Don't participate in QoS handling
M_AXI_AWID <= (others => '0'); -- ID fixed to zero
M_AXI_AWBURST <= "01"; -- Only INCR bursts
M_AXI_AWCACHE <= "0011"; -- Set "Modifiable" and "Bufferable" bit
-- AR signals constant values
M_AXI_ARPROT <= "010"; -- Normal and non-secure Data access only
M_AXI_ARQOS <= "0000"; -- Don't participate in QoS handling
M_AXI_ARID <= (others => '0'); -- ID fixed to zero
M_AXI_ARBURST <= "01"; -- Only INCR bursts
M_AXI_ARCACHE <= "0011"; -- Set "Modifiable" and "Bufferable" bit
-- R signals constant values
M_AXI_RREADY <= '1'; -- Always accepting read data
-- B signals value
M_AXI_BREADY <= '1' when wr_state = wait_on_bchan else '0';
-- AXI Write FSM
Wr_Executing : process (M_AXI_ACLK) is
variable address_done : boolean;
variable data_done : boolean;
variable len : std_logic_vector(4 downto 0);
begin -- process Wr_Executing
if (M_AXI_ACLK'event and M_AXI_ACLK = '1') then -- rising clock edge
if (M_AXI_ARESETn = '0') then -- synchronous reset (active low)
axi_wr_idle <= '1';
axi_wr_resp <= "00";
axi_wvalid <= '0';
M_AXI_WVALID <= '0';
M_AXI_WLAST <= '0';
M_AXI_WSTRB <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= "010"; -- 32-bit accesses
M_AXI_AWLOCK <= '0'; -- No locking
M_AXI_AWVALID <= '0';
axi_dwr_done <= '0';
address_done := false;
data_done := false;
len := (others => '0');
wr_state <= idle;
else
case wr_state is
when idle =>
axi_wr_idle <= '1';
axi_dwr_done <= '0';
address_done := false;
data_done := false;
len := (others => '0');
if axi_dwr_start = '1' then
wr_state <= start;
axi_wr_idle <= '0';
axi_wr_resp <= "00";
end if;
when start =>
M_AXI_WLAST <= '0';
M_AXI_AWVALID <= '1';
M_AXI_AWADDR <= axi_dwr_addr;
M_AXI_AWLEN <= "000" & axi_dwr_len;
M_AXI_AWSIZE <= "0" & axi_dwr_size;
M_AXI_AWLOCK <= axi_dwr_exclusive;
axi_wvalid <= '1';
M_AXI_WVALID <= '1';
if axi_dwr_len = "00000" then
M_AXI_WLAST <= '1';
end if;
M_AXI_WSTRB <= axi_dwr_wstrb;
len := axi_dwr_len;
wr_state <= wait_on_ready;
when wait_on_ready =>
if M_AXI_AWREADY = '1' then
M_AXI_AWVALID <= '0';
address_done := true;
end if;
if M_AXI_WREADY = '1' then
if len = "00000" then
axi_wvalid <= '0';
M_AXI_WVALID <= '0';
data_done := true;
else
if len = "00001" then
M_AXI_WLAST <= '1';
end if;
len := std_logic_vector(unsigned(len) - 1);
end if;
end if;
if (address_done and data_done) then
wr_state <= wait_on_bchan;
end if;
when wait_on_bchan =>
if (M_AXI_BVALID = '1') then
wr_state <= idle;
axi_dwr_done <= '1';
axi_wr_resp <= M_AXI_BRESP;
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
end if;
end if;
end process Wr_Executing;
axi_do_read <= axi_wvalid and M_AXI_WREADY;
M_AXI_WDATA <= axi_dwr_wdata;
end architecture IMP;
-------------------------------------------------------------------------------
-- jtag_control.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: jtag_control.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- jtag_control.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2003-02-13 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2013-06-15 Added support for external trace
-- stefana 2016-04-25 Added parallel synchronous debug interface
-- stefana 2016-06-01 Added wrappers for unisim primitives
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity JTAG_CONTROL is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_USE_BSCAN : integer;
C_MB_DBG_PORTS : integer;
C_USE_CONFIG_RESET : integer;
C_DEBUG_INTERFACE : integer;
C_DBG_REG_ACCESS : integer;
C_DBG_MEM_ACCESS : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_EN_WIDTH : integer := 1
);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
Clk : in std_logic;
Rst : in std_logic;
Clear_Ext_BRK : in std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic := '0';
Debug_SYS_Rst : out std_logic := '0';
Debug_Rst : out std_logic := '0';
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_UART_WIDTH-1);
RX_Data_Present : out std_logic;
RX_BUFFER_FULL : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_UART_WIDTH-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic;
-- Debug Register Access signals
DbgReg_Access_Lock : in std_logic;
DbgReg_Force_Lock : in std_logic;
DbgReg_Unlocked : in std_logic;
JTAG_Access_Lock : out std_logic;
JTAG_Force_Lock : out std_logic;
JTAG_AXI_Overrun : in std_logic;
JTAG_Clear_Overrun : out std_logic;
AXI_Transaction : in std_logic;
AXI_Instr_Overrun : in std_logic;
AXI_Data_Overrun : in std_logic;
AXI_Completion_On : out std_logic;
AXI_Block : out std_logic;
-- MDM signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- Bus Master signals
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- MicroBlaze Debug Signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
Dbg_Clk : out std_logic;
Dbg_TDI : out std_logic;
Dbg_TDO : in std_logic;
Dbg_Reg_En : out std_logic_vector(0 to 7);
Dbg_Capture : out std_logic;
Dbg_Shift : out std_logic;
Dbg_Update : out std_logic;
Dbg_data_cmd : out std_logic;
Dbg_command : out std_logic_vector(0 to 7);
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- Trace signals
Trace_Clk : in std_logic;
Trace_Reset : in std_logic;
Trace_Test_Pattern : out std_logic_vector(0 to 3);
Trace_Test_Start : out std_logic;
Trace_Test_Stop : out std_logic;
Trace_Test_Timed : out std_logic;
Trace_Delay : out std_logic_vector(0 to 7);
Trace_Stopped : out std_logic
);
end entity JTAG_CONTROL;
library mdm_v3_2_8;
use mdm_v3_2_8.SRL_FIFO;
architecture IMP of JTAG_CONTROL is
component SRL_FIFO
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_DATA_BITS : natural;
C_DEPTH : natural
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end component SRL_FIFO;
component MB_FDC_1
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
component MB_FDRE_1
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component MB_SRL16E is
generic(
C_TARGET : TARGET_FAMILY_TYPE;
C_STATIC : boolean := false;
INIT : bit_vector := X"0000");
port(
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component MB_SRL16E;
component MB_FDRSE
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0';
IS_CE_INVERTED : bit := '0';
IS_C_INVERTED : bit := '0';
IS_D_INVERTED : bit := '0';
IS_R_INVERTED : bit := '0';
IS_S_INVERTED : bit := '0'
);
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
--
-- Old Config Word in previous versions
--
-- Magic String + Has FSL + 0 + Has UART + UART Width + Num MB + Num hw ports + Debug Version
-- 8 bits + 1 bit + 1 bit + 1 bit + 5 bits + 8 bits + 4 bits + 4 bits
--
-- New Config Word in mdm v2
--
-- Magic String + 00 + Has UART + UART Width + Num MB + UART version + Debug Version
-- 8 bits + 2 bits + 1 bit + 5 bits + 8 bits + 4 bits + 4 bits
--
-- New Config Word in mdm v2 with extended debug
--
-- Extended Config + Magic String + 1 + Extended + Has UART + UART Width + Num MB + UART version + Debug Version
-- 5 bits + 8 bits + 1 bit + 1 bit + 1 bit + 5 bits + 8 bits + 4 bits + 4 bits
--
-- Debug Version Table
-- 0,1,2: Obsolete
-- 3,4: Watchpoint support
-- 5: Remove sync
-- 6: Change command and Reg_En signals to 8 bits
-- 7: Change MB_Debug_Enabled to 32 bits
--
-- UART Version Table
-- 0: Get version from Debug Version Table
-- 6: Non-buffered mode support
--
function TDI_Shifter_Size return integer is
begin
if C_USE_CROSS_TRIGGER = 1 or C_TRACE_OUTPUT = 3 then
if C_MB_DBG_PORTS < 16 then
return 16;
else
return C_MB_DBG_PORTS;
end if;
elsif C_TRACE_OUTPUT = 1 then
if C_MB_DBG_PORTS < 14 then
return 14;
else
return C_MB_DBG_PORTS;
end if;
elsif C_MB_DBG_PORTS > 8 then
return C_MB_DBG_PORTS;
end if;
return 8;
end function TDI_Shifter_Size;
function Which_MB_Reg_Size return integer is
begin
if C_MB_DBG_PORTS > 8 then
return C_MB_DBG_PORTS;
end if;
return 8;
end function Which_MB_Reg_Size;
constant No_MicroBlazes : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(natural(C_MB_DBG_PORTS), 8));
constant UART_VERSION : std_logic_vector(3 downto 0) := "0110";
constant DEBUG_VERSION : std_logic_vector(3 downto 0) := "0111";
constant Config_Init_Word_S : std_logic_vector(15 downto 0) :=
(No_MicroBlazes & UART_VERSION & DEBUG_VERSION);
constant Config_Init_Word : bit_vector(15 downto 0) :=
to_bitvector(Config_Init_Word_S);
constant C_EXT_CONFIG : integer :=
Boolean'Pos(C_DBG_MEM_ACCESS > 0 or C_DBG_REG_ACCESS > 0 or C_USE_CROSS_TRIGGER > 0 or C_TRACE_OUTPUT > 0);
constant HAVE_EXTENDED : std_logic_vector(0 to 0) :=
std_logic_vector(to_unsigned(natural(C_EXT_CONFIG), 1));
constant HAVE_UART : std_logic_vector(0 to 0) :=
std_logic_vector(to_unsigned(natural(C_USE_UART), 1));
constant UART_WIDTH : std_logic_vector(0 to 4) :=
std_logic_vector(to_unsigned(natural(C_UART_WIDTH-1), 5));
constant MAGIC_STRING : std_logic_vector(0 to 7) := "01000010";
constant Config_Init_Word2_S : std_logic_vector(15 downto 0) :=
(MAGIC_STRING & '1' & HAVE_EXTENDED & HAVE_UART & UART_WIDTH);
constant Config_Init_Word2 : bit_vector(15 downto 0) :=
to_bitvector(Config_Init_Word2_S);
constant Config_Init_Word3_S : std_logic_vector(15 downto 0) :=
std_logic_vector(to_unsigned(0, 11) &
to_unsigned(natural(C_TRACE_OUTPUT), 2) &
to_unsigned(natural(C_USE_CROSS_TRIGGER), 1) &
to_unsigned(natural(C_DBG_REG_ACCESS), 1) &
to_unsigned(natural(C_DBG_MEM_ACCESS), 1));
constant Config_Init_Word3 : bit_vector(15 downto 0) :=
to_bitvector(Config_Init_Word3_S);
signal config_TDO_1 : std_logic;
signal config_TDO_2 : std_logic;
signal config_TDO_3 : std_logic;
signal config_TDO : std_logic;
signal ID_TDO : std_logic;
signal ID_TDO_1 : std_logic;
signal ID_TDO_2 : std_logic;
signal uart_TDO : std_logic;
signal compl_TDO : std_logic;
signal master_TDO : std_logic;
signal axis_TDO : std_logic;
signal ct_TDO : std_logic;
signal trace_TDO : std_logic;
-----------------------------------------------------------------------------
-- JTAG signals
-----------------------------------------------------------------------------
signal data_cmd : std_logic;
signal data_cmd_n : std_logic;
signal data_cmd_noblock : std_logic;
signal sel_n : std_logic;
signal command : std_logic_vector(0 to 7) := (others => '0');
signal command_1 : std_logic_vector(0 to 7) := (others => '0');
signal tdi_shifter : std_logic_vector(0 to TDI_Shifter_Size - 1) := (others => '0');
signal shifting_Data : std_logic;
signal sync_detected : std_logic;
signal sync : std_logic;
constant SYNC_CONST : std_logic_vector(1 to 8) := "01101001";
signal shift_Count : std_logic_vector(4 + C_EXT_CONFIG downto 0) := (others => '0');
signal mb_debug_enabled_i : std_logic_vector(C_EN_WIDTH-1 downto 0);
constant C_NUM_DBG_CT : integer := 8;
constant C_NUM_EXT_CT : integer := 4;
type dbg_trig_type is array (0 to 31) of std_logic_vector(0 to C_NUM_DBG_CT - 1);
signal dbg_trig_ack_in_i : dbg_trig_type;
signal dbg_trig_out_i : dbg_trig_type;
signal ext_trig_ack_in_i : std_logic_vector(0 to C_NUM_EXT_CT - 1);
signal ext_trig_out_i : std_logic_vector(0 to C_NUM_EXT_CT - 1);
signal completion_ctrl : std_logic_vector(0 downto 0) := (others => '0');
signal completion_status : std_logic_vector(15 downto 0) := (others => '0');
signal completion_block : std_logic := '0';
signal clear_overrun : std_logic := '0';
signal master_overrun : std_logic;
signal master_error : std_logic;
-----------------------------------------------------------------------------
-- Register handling
-----------------------------------------------------------------------------
constant MDM_DEBUG_ID : std_logic_vector(0 to 7) := "00000000";
constant MB_WRITE_CONTROL : std_logic_vector(0 to 7) := "00000001";
constant MB_WRITE_COMMAND : std_logic_vector(0 to 7) := "00000010";
constant MB_READ_STATUS : std_logic_vector(0 to 7) := "00000011";
constant MB_WRITE_INSTR : std_logic_vector(0 to 7) := "00000100";
--constant MB_WRITE_DATA : std_logic_vector(0 to 7) := "00000101";
constant MB_READ_DATA : std_logic_vector(0 to 7) := "00000110";
constant MB_READ_CONFIG : std_logic_vector(0 to 7) := "00000111";
constant MB_WRITE_BRK_RST_CTRL : std_logic_vector(0 to 7) := "00001000";
constant UART_WRITE_BYTE : std_logic_vector(0 to 7) := "00001001";
constant UART_READ_STATUS : std_logic_vector(0 to 7) := "00001010";
constant UART_READ_BYTE : std_logic_vector(0 to 7) := "00001011";
constant MDM_READ_CONFIG : std_logic_vector(0 to 7) := "00001100";
constant MDM_WRITE_WHICH_MB : std_logic_vector(0 to 7) := "00001101";
constant UART_WRITE_CONTROL : std_logic_vector(0 to 7) := "00001110";
--constant MDM_WRITE_TO_FSL : std_logic_vector(0 to 7) := "00001111";
-- registers "00010000" to "00011111" are pc breakpoints 1-16
constant BUSM_WRITE_DATA : std_logic_vector(0 to 7) := "00100001";
constant BUSM_READ_STATUS : std_logic_vector(0 to 7) := "00100010";
constant BUSM_READ_DATA : std_logic_vector(0 to 7) := "00100011";
constant BUSM_WRITE_COMMAND : std_logic_vector(0 to 7) := "00100101";
constant BUSM_WRITE_CONTROL : std_logic_vector(0 to 7) := "00100110";
constant MDM_READ_COMPL_STATUS : std_logic_vector(0 to 7) := "00101010";
constant MDM_WRITE_COMPL_CTRL : std_logic_vector(0 to 7) := "00101101";
constant AXIS_READ_STATUS : std_logic_vector(0 to 7) := "00110010";
constant AXIS_WRITE_COMMAND : std_logic_vector(0 to 7) := "00110110";
constant CT_WRITE_EXT_CTRL : std_logic_vector(0 to 7) := "01000000";
constant CT_READ_STATUS : std_logic_vector(0 to 7) := "01000010";
constant CT_WRITE_CTRL : std_logic_vector(0 to 7) := "01000110";
constant TRACE_READ_STATUS : std_logic_vector(0 to 7) := "01001010";
constant TRACE_READ_ADDR : std_logic_vector(0 to 7) := "01001011";
constant TRACE_WRITE_LOW_ADDR : std_logic_vector(0 to 7) := "01001100";
constant TRACE_WRITE_HIGH_ADDR : std_logic_vector(0 to 7) := "01001101";
constant TRACE_WRITE_CONTROL : std_logic_vector(0 to 7) := "01001110";
-- registers "01010000" to "11111111" are reserved for MicroBlaze
-----------------------------------------------------------------------------
-- Internal signals for debugging
-----------------------------------------------------------------------------
signal set_Ext_BRK : std_logic := '0';
signal ext_BRK_i : std_logic := '0';
signal Ext_NM_BRK_i : std_logic := '0';
signal Debug_SYS_Rst_i : std_logic := '0';
signal Debug_Rst_i : std_logic := '0';
constant ID_Init_Word1 : bit_vector(15 downto 0) := x"4443"; -- Ascii
constant ID_Init_Word2 : bit_vector(15 downto 0) := x"584D"; -- "XMDC"
signal config_with_scan_reset : std_logic;
attribute KEEP : string;
begin -- architecture IMP
config_with_scan_reset <= Config_Reset when Scan_Reset_Sel = '0' else
Scan_Reset;
-----------------------------------------------------------------------------
-- Control logic
-----------------------------------------------------------------------------
-- data_cmd | meaning
-- ======================
-- 0 | Command phase
-- 1 | Data phase
FDC_I : MB_FDC_1
generic map (
C_TARGET => C_TARGET
)
port map (
Q => data_cmd_noblock, -- [out std_logic]
C => Update, -- [in std_logic]
D => data_cmd_n, -- [in std_logic]
CLR => sel_n); -- [in std_logic]
data_cmd_n <= not data_cmd_noblock;
data_cmd <= data_cmd_noblock and not completion_block;
Sel_DFF: process (DRCK, config_with_scan_reset) is
begin
if config_with_scan_reset = '1' then
sel_n <= '1';
elsif DRCK'event and DRCK = '1' then
if CAPTURE = '1' then
sel_n <= not SEL;
end if;
end if;
end process Sel_DFF;
Input_shifter : process (DRCK, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
tdi_shifter <= (others => '0');
elsif DRCK'event and DRCK = '1' then
if SEL = '1' and SHIFT = '1' then
tdi_shifter <= TDI & tdi_shifter(0 to tdi_shifter'right - 1);
end if;
end if;
end process Input_shifter;
Command_update : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
command <= (others => '0');
elsif UPDATE'event and UPDATE = '0' then
if SEL = '1' then
command <= command_1;
end if;
end if;
end process Command_update;
Command_update_1 : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
command_1 <= (others => '0');
elsif UPDATE'event and UPDATE = '1' then
if SEL = '1' and data_cmd = '0' then
command_1 <= tdi_shifter (0 to 7);
end if;
end if;
end process Command_update_1;
Use_BSCAN : if (C_USE_BSCAN /= 3) generate
begin
Dbg_Clk <= DRCK;
Dbg_Reg_En <= command when data_cmd = '1' else (others => '0');
Dbg_TDI <= TDI;
Dbg_Capture <= CAPTURE;
Dbg_Update <= UPDATE;
Dbg_Shift <= shifting_Data;
Dbg_data_cmd <= data_cmd;
Dbg_command <= command when SEL = '1' else (others => '0');
end generate Use_BSCAN;
No_BSCAN : if (C_USE_BSCAN = 3) generate
begin
-- Unused serial signals
Dbg_Clk <= '0';
Dbg_Reg_En <= (others => '0');
Dbg_TDI <= '0';
Dbg_Capture <= '0';
Dbg_Update <= '0';
Dbg_Shift <= '0';
Dbg_data_cmd <= '0';
Dbg_Command <= (others => '0');
end generate No_BSCAN;
-- No sync word requirement for commands other than "Write Instruction"
shifting_Data <= (SHIFT and sync)
when (command = MB_WRITE_INSTR) and (data_cmd = '1')
else SHIFT;
sync_detected <= '1' when tdi_shifter(0 to 7) = SYNC_CONST and data_cmd = '1'
else '0';
SYNC_FDRE : MB_FDRE_1
generic map (
C_TARGET => C_TARGET
)
port map (
Q => sync,
C => DRCK,
CE => sync_detected,
D => '1',
R => data_cmd_n);
-----------------------------------------------------------------------------
-- Shift Counter
-----------------------------------------------------------------------------
-- Keep a counter on the number of bits in the data phase after a sync has
-- been detected
Shift_Counter : process (DRCK, config_with_scan_reset) is
begin -- process Shift_Counter
if config_with_scan_reset = '1' then
shift_Count <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if SHIFT = '0' then
shift_Count <= (others => '0');
else
shift_Count <= std_logic_vector(unsigned(Shift_Count) + 1);
end if;
end if;
end process Shift_Counter;
-----------------------------------------------------------------------------
-- Config Register
-----------------------------------------------------------------------------
Use_Config_SRL16E : if (C_USE_CONFIG_RESET = 0) generate
begin
SRL16E_1 : MB_SRL16E
generic map (
C_TARGET => C_TARGET,
C_STATIC => true,
INIT => Config_Init_Word
)
port map (
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
Clk => DRCK, -- [in std_logic]
A0 => shift_Count(0), -- [in std_logic]
A1 => shift_Count(1), -- [in std_logic]
A2 => shift_Count(2), -- [in std_logic]
A3 => shift_Count(3), -- [in std_logic]
Q => config_TDO_1); -- [out std_logic]
SRL16E_2 : MB_SRL16E
generic map (
C_TARGET => C_TARGET,
C_STATIC => true,
INIT => Config_Init_Word2
)
port map (
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
Clk => DRCK, -- [in std_logic]
A0 => shift_Count(0), -- [in std_logic]
A1 => shift_Count(1), -- [in std_logic]
A2 => shift_Count(2), -- [in std_logic]
A3 => shift_Count(3), -- [in std_logic]
Q => config_TDO_2); -- [out std_logic]
Use_Ext_Config: if (C_EXT_CONFIG > 0) generate
begin
SRL16E_3 : MB_SRL16E
generic map (
C_TARGET => C_TARGET,
C_STATIC => true,
INIT => Config_Init_Word3
)
port map (
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
Clk => DRCK, -- [in std_logic]
A0 => shift_Count(0), -- [in std_logic]
A1 => shift_Count(1), -- [in std_logic]
A2 => shift_Count(2), -- [in std_logic]
A3 => shift_Count(3), -- [in std_logic]
Q => config_TDO_3); -- [out std_logic]
end generate Use_Ext_Config;
end generate Use_Config_SRL16E;
No_Config_SRL16E : if (C_USE_CONFIG_RESET = 1) generate
begin
config_TDO_1 <= Config_Init_Word_S(to_integer(unsigned(shift_Count(3 downto 0))));
config_TDO_2 <= Config_Init_Word2_S(to_integer(unsigned(shift_Count(3 downto 0))));
Use_Ext_Config: if (C_EXT_CONFIG > 0) generate
begin
config_TDO_3 <= Config_Init_Word3_S(to_integer(unsigned(shift_Count(3 downto 0))));
end generate Use_Ext_Config;
end generate No_Config_SRL16E;
Use_Ext_Config: if (C_EXT_CONFIG > 0) generate
begin
config_TDO <= config_TDO_1 when shift_Count(5 downto 4) = "00" else
config_TDO_2 when shift_Count(5 downto 4) = "01" else
config_TDO_3;
end generate Use_Ext_Config;
No_Ext_Config: if (C_EXT_CONFIG = 0) generate
begin
config_TDO_3 <= '0'; -- Unused
config_TDO <= config_TDO_1 when shift_Count(4) = '0' else config_TDO_2;
end generate No_Ext_Config;
-----------------------------------------------------------------------------
-- ID Register
-----------------------------------------------------------------------------
Use_ID_SRL16E : if (C_USE_CONFIG_RESET = 0) generate
begin
SRL16E_ID_1 : MB_SRL16E
generic map (
C_TARGET => C_TARGET,
C_STATIC => true,
INIT => ID_Init_Word1
)
port map (
CE => '0',
D => '0',
Clk => DRCK,
A0 => shift_Count(0),
A1 => shift_Count(1),
A2 => shift_Count(2),
A3 => shift_Count(3),
Q => ID_TDO_1);
SRL16E_ID_2 : MB_SRL16E
generic map (
C_TARGET => C_TARGET,
C_STATIC => true,
INIT => ID_Init_Word2
)
port map (
CE => '0',
D => '0',
Clk => DRCK,
A0 => shift_Count(0),
A1 => shift_Count(1),
A2 => shift_Count(2),
A3 => shift_Count(3),
Q => ID_TDO_2);
end generate Use_ID_SRL16E;
No_ID_SRL16E : if (C_USE_CONFIG_RESET = 1) generate
begin
ID_TDO_1 <= To_X01(ID_Init_Word1(to_integer(unsigned(shift_Count(3 downto 0)))));
ID_TDO_2 <= To_X01(ID_Init_Word2(to_integer(unsigned(shift_Count(3 downto 0)))));
end generate No_ID_SRL16E;
ID_TDO <= ID_TDO_1 when shift_Count(4) = '0' else ID_TDO_2;
-----------------------------------------------------------------------------
-- Handling the Which_MB register
-----------------------------------------------------------------------------
More_Than_One_MB : if (C_MB_DBG_PORTS > 1) generate
signal Which_MB_Reg : std_logic_vector(Which_MB_Reg_Size - 1 downto 0) := (others => '0');
begin
Which_MB_Reg_Handle : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
Which_MB_Reg <= (others => '0');
elsif UPDATE'event and UPDATE = '0' then
if SEL = '1' and data_cmd = '1' and command = MDM_WRITE_WHICH_MB then
Which_MB_Reg <= tdi_shifter(0 to Which_MB_Reg_Size - 1);
end if;
end if;
end process Which_MB_Reg_Handle;
mb_debug_enabled_i(C_MB_DBG_PORTS-1 downto 0) <=
Which_MB_Reg(C_MB_DBG_PORTS-1 downto 0);
end generate More_Than_One_MB;
Only_One_MB : if (C_MB_DBG_PORTS = 1) generate
mb_debug_enabled_i(0) <= '1';
end generate Only_One_MB;
No_MB : if (C_MB_DBG_PORTS = 0) generate
mb_debug_enabled_i(0) <= '0';
end generate No_MB;
MB_Debug_Enabled <= mb_debug_enabled_i;
-----------------------------------------------------------------------------
-- Reset Control
-----------------------------------------------------------------------------
Reset_Control : process (UPDATE, config_with_scan_reset)
begin -- process Reset_Control
if config_with_scan_reset = '1' then
Debug_Rst_i <= '0';
Debug_SYS_Rst_i <= '0';
set_Ext_BRK <= '0';
Ext_NM_BRK_i <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = MB_WRITE_BRK_RST_CTRL and data_cmd = '1' then
Debug_Rst_i <= tdi_shifter(0);
Debug_SYS_Rst_i <= tdi_shifter(1);
set_Ext_BRK <= tdi_shifter(2);
Ext_NM_BRK_i <= tdi_shifter(3);
end if;
end if;
end process Reset_Control;
-----------------------------------------------------------------------------
-- Execute Commands
-----------------------------------------------------------------------------
Debug_SYS_Rst <= Debug_SYS_Rst_i;
Debug_Rst <= Debug_Rst_i;
Ext_NM_BRK <= Ext_NM_BRK_i;
Ext_BRK <= ext_BRK_i;
-----------------------------------------------------------------------------
-- TDO Mux
-----------------------------------------------------------------------------
with command select
TDO <=
ID_TDO when MDM_DEBUG_ID,
uart_TDO when UART_READ_BYTE,
uart_TDO when UART_READ_STATUS,
config_TDO when MDM_READ_CONFIG,
master_TDO when BUSM_READ_DATA,
master_TDO when BUSM_READ_STATUS,
compl_TDO when MDM_READ_COMPL_STATUS,
axis_TDO when AXIS_READ_STATUS,
ct_TDO when CT_READ_STATUS,
trace_TDO when TRACE_READ_ADDR,
trace_TDO when TRACE_READ_STATUS,
Dbg_TDO when others;
-----------------------------------------------------------------------------
-- Unified Overrun and Error Detection section
-----------------------------------------------------------------------------
-- Completion Control (clears completion count and block):
-- 0 Enable completion block
Completion_Control_Register : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
completion_ctrl <= (others => '0');
elsif UPDATE'event and UPDATE = '1' then
if command = MDM_WRITE_COMPL_CTRL and data_cmd_noblock = '1' then
completion_ctrl <= tdi_shifter(0 to 0);
end if;
end if;
end process Completion_Control_Register;
compl_TDO <= completion_status(completion_status'right);
Use_Serial_Unified_Completion : if C_DEBUG_INTERFACE = 0 generate
signal mb_instr_overrun : std_logic := '0';
signal mb_instr_error : std_logic := '0';
signal mb_data_overrun : std_logic := '0';
begin
-- Completion Status:
-- 0-9 Command count
-- 10 MicroBlaze instruction insert overrun
-- 11 MicroBlaze instruction insert exception occurred
-- 12 MicroBlaze data read overrun
-- 13 Bus Master interface overrun
-- 14 Bus Master interface error occurred
-- 15 AXI Slave interface access locked
Completion_Status_Register : process (DRCK, config_with_scan_reset) is
variable sample : std_logic_vector(15 downto 13);
variable sample_1 : std_logic_vector(15 downto 10);
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
begin -- process Completion_Status_Register
if config_with_scan_reset = '1' then
completion_status <= (others => '0');
completion_block <= '0';
clear_overrun <= '0';
sample := (others => '0');
sample_1 := (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if command = MDM_READ_COMPL_STATUS and data_cmd_noblock = '1' then
if CAPTURE = '1' then
completion_status(sample_1'range) <= sample_1;
elsif SHIFT = '1' then
completion_status <= '0' & completion_status(completion_status'left downto completion_status'right + 1);
end if;
elsif command = MDM_WRITE_COMPL_CTRL and data_cmd_noblock = '1' then
if CAPTURE = '1' then
completion_status(9 downto 0) <= (others => '0');
completion_block <= '0';
clear_overrun <= '1';
end if;
else
-- Sample and detect status change
if completion_ctrl(0) = '1' then
if (sample_1(10) = '0' and mb_instr_overrun = '1') or
(sample_1(11) = '0' and mb_instr_error = '1') or
(sample_1(12) = '0' and mb_data_overrun = '1') or
(sample_1(13) = '0' and sample(13) = '1') or
(sample_1(14) = '0' and sample(14) = '1') or
(sample_1(15) = '0' and sample(15) = '1') then
completion_block <= '1';
end if;
end if;
sample_1(15 downto 13) := sample;
sample_1(10) := mb_instr_overrun;
sample_1(11) := mb_instr_error;
sample_1(12) := mb_data_overrun;
sample(13) := master_overrun;
sample(14) := master_error;
sample(15) := JTAG_AXI_Overrun;
-- Increment command count
if CAPTURE = '1' then
if data_cmd = '0' and completion_block = '0' then
completion_status(9 downto 0) <= std_logic_vector(unsigned(completion_status(9 downto 0)) + 1);
end if;
clear_overrun <= '0';
end if;
end if;
end if;
end process Completion_Status_Register;
Write_Instr_Status : process (DRCK, config_with_scan_reset) is
variable count : std_logic_vector(0 to 1) := "00";
begin -- process Write_Instr_Status
if config_with_scan_reset = '1' then
mb_instr_overrun <= '0';
mb_instr_error <= '0';
count := "00";
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if command = MB_WRITE_INSTR and data_cmd = '1' then
if CAPTURE = '1' then
mb_instr_overrun <= '0';
mb_instr_error <= '0';
count := "00";
elsif shifting_Data = '1' and count(0) = '0' then
if count(1) = '0' then
mb_instr_overrun <= Dbg_TDO;
end if;
if count(1) = '1' then
mb_instr_error <= Dbg_TDO;
end if;
count := std_logic_vector(unsigned(count) + 1);
end if;
elsif command = MDM_WRITE_COMPL_CTRL and data_cmd_noblock = '1' then
if CAPTURE = '1' then
mb_instr_overrun <= '0';
mb_instr_error <= '0';
end if;
end if;
end if;
end process Write_Instr_Status;
Data_Read_Status : process (DRCK, config_with_scan_reset) is
variable count : std_logic_vector(0 to 5) := "000000";
begin -- process Data_Read_Status
if config_with_scan_reset = '1' then
mb_data_overrun <= '0';
count := "000000";
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if command = MB_READ_DATA and data_cmd = '1' then
if CAPTURE = '1' then
mb_data_overrun <= '0';
count := "000000";
elsif SHIFT = '1' then
if count = "100000" then
mb_data_overrun <= not Dbg_TDO;
end if;
count := std_logic_vector(unsigned(count) + 1);
end if;
elsif command = MDM_WRITE_COMPL_CTRL and data_cmd_noblock = '1' then
if CAPTURE = '1' then
mb_data_overrun <= '0';
end if;
end if;
end if;
end process Data_Read_Status;
-- Unused
AXI_Completion_On <= '0';
AXI_Block <= '0';
end generate Use_Serial_Unified_Completion;
Use_Parallel_Unified_Completion : if C_DEBUG_INTERFACE = 1 generate
signal axi_completion_status : std_logic_vector(15 downto 0) := (others => '0');
signal write_compl_ctrl : std_logic;
signal jtag_command : std_logic;
begin
-- Completion Status:
-- 0-9 Command count + AXI transactions
-- 10 MicroBlaze instruction insert overrun or exception
-- 12 MicroBlaze data read overrun
-- 13 Bus Master interface overrun
-- 14 Bus Master interface error occurred
-- 15 AXI Slave interface access locked
AXI_Completion_Status_Register : process (Clk) is
variable sample : std_logic_vector(14 downto 13);
variable sample_1 : std_logic_vector(15 downto 10);
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
begin -- process AXI_Completion_Status_Register
if Clk'event and Clk = '1' then -- rising clock edge
if Rst = '1' then -- synchronous reset (active high)
axi_completion_status <= (others => '0');
completion_block <= '0';
clear_overrun <= '0';
else
axi_completion_status(sample_1'range) <= sample_1;
if write_compl_ctrl = '1' then
axi_completion_status(9 downto 0) <= (others => '0');
completion_block <= '0';
clear_overrun <= '1';
end if;
-- Sample and detect status change
if completion_ctrl(0) = '1' then
if (sample_1(10) = '0' and AXI_instr_overrun = '1') or
(sample_1(12) = '0' and AXI_data_overrun = '1') or
(sample_1(13) = '0' and sample(13) = '1') or
(sample_1(14) = '0' and sample(14) = '1') or
(sample_1(15) = '0' and JTAG_AXI_Overrun = '1') then
completion_block <= '1';
end if;
end if;
sample_1(10) := AXI_instr_overrun;
sample_1(11) := '0';
sample_1(12) := AXI_data_overrun;
sample_1(14 downto 13) := sample;
sample_1(15) := JTAG_AXI_Overrun;
sample(13) := master_overrun;
sample(14) := master_error;
-- Increment command count
if (AXI_Transaction = '1' or jtag_command = '1') and (completion_block = '0') then
axi_completion_status(9 downto 0) <= std_logic_vector(unsigned(axi_completion_status(9 downto 0)) + 1);
clear_overrun <= '0';
end if;
end if;
end if;
end process AXI_Completion_Status_Register;
Sample_Commands : process (Clk) is
variable sample : std_logic_vector(0 to 1) := (others => '0');
variable sample_1 : std_logic_vector(0 to 1) := (others => '0');
variable sample_2 : std_logic_vector(0 to 1) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
attribute ASYNC_REG of sample_1 : variable is "TRUE";
begin -- process Sample_Commmands
if Clk'event and Clk = '1' then -- rising clock edge
if Rst = '1' then -- synchronous reset (active high)
write_compl_ctrl <= '0';
jtag_command <= '0';
sample_2 := (others => '0');
sample_1 := (others => '0');
sample := (others => '0');
else
write_compl_ctrl <= sample_1(1) and not sample_2(1);
jtag_command <= sample_1(0) and not sample_2(0);
sample_2 := sample_1;
sample_1 := sample;
if command = MDM_WRITE_COMPL_CTRL and data_cmd_noblock = '1' then
sample(1) := '1';
else
sample(1) := '0';
end if;
sample(0) := CAPTURE and not data_cmd_noblock;
end if;
end if;
end process Sample_Commands;
Completion_Status_Register : process (DRCK, config_with_scan_reset) is
begin -- process Completion_Status_Register
if config_with_scan_reset = '1' then
completion_status <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if command = MDM_READ_COMPL_STATUS and data_cmd_noblock = '1' then
if CAPTURE = '1' then
completion_status <= axi_completion_status;
elsif SHIFT = '1' then
completion_status <= '0' & completion_status(completion_status'left downto completion_status'right + 1);
end if;
end if;
end if;
end process Completion_Status_Register;
AXI_Completion_On <= completion_ctrl(0);
AXI_Block <= completion_block;
end generate Use_Parallel_Unified_Completion;
-----------------------------------------------------------------------------
-- UART section
-----------------------------------------------------------------------------
Use_UART : if (C_USE_UART = 1) generate
signal execute : std_logic := '0';
signal execute_1 : std_logic := '0';
signal execute_2 : std_logic := '0';
signal execute_3 : std_logic := '0';
signal fifo_DOut : std_logic_vector(0 to C_UART_WIDTH-1);
signal fifo_Data_Present : std_logic := '0';
signal fifo_Din : std_logic_vector(0 to C_UART_WIDTH-1);
signal fifo_Read : std_logic := '0';
signal fifo_Write : std_logic := '0';
signal rx_Buffer_Full_I : std_logic := '0';
signal rx_Data_Present_I : std_logic := '0';
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
signal tdo_reg : std_logic_vector(0 to C_UART_WIDTH-1) := (others => '0');
signal tx_Buffer_Full_I : std_logic := '0';
signal tx_buffered : std_logic := '0'; -- Non-buffered mode on startup
signal tx_buffered_1 : std_logic := '0';
signal tx_buffered_2 : std_logic := '0';
signal tx_fifo_wen : std_logic;
signal data_cmd_reset : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of execute_1 : signal is "TRUE";
attribute ASYNC_REG of execute_2 : signal is "TRUE";
attribute ASYNC_REG of tx_buffered_1 : signal is "TRUE";
attribute ASYNC_REG of tx_buffered_2 : signal is "TRUE";
begin
Ext_BRK_FDRSE : MB_FDRSE
generic map (
C_TARGET => C_TARGET
)
port map (
Q => ext_BRK_i, -- [out std_logic]
C => Clk, -- [in std_logic]
CE => '0', -- [in std_logic]
D => '0', -- [in std_logic]
R => Clear_Ext_BRK, -- [in std_logic]
S => set_Ext_BRK); -- [in std_logic]
-----------------------------------------------------------------------------
-- Control Register
-----------------------------------------------------------------------------
-- Register accessible on the JTAG interface only
Control_Register : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
tx_buffered <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = UART_WRITE_CONTROL and data_cmd = '1' then
tx_buffered <= tdi_shifter(0);
end if;
end if;
end process Control_Register;
Tx_Buffered_DFF: process (Clk)
begin -- process Tx_Buffered_DFF
if Clk'event and Clk = '1' then
tx_buffered_2 <= tx_buffered_1;
tx_buffered_1 <= tx_buffered;
end if;
end process Tx_Buffered_DFF;
data_cmd_reset <= data_cmd when Scan_Reset_Sel = '0' else
not Scan_Reset;
Execute_UART_Command : process (UPDATE, data_cmd_reset)
begin -- process Execute_UART_Command
if data_cmd_reset = '0' then
execute <= '0';
elsif UPDATE'event and UPDATE = '1' then
if (command = UART_READ_BYTE) or
(command = UART_WRITE_BYTE) then
execute <= '1';
else
execute <= '0';
end if;
end if;
end process Execute_UART_Command;
Execute_FIFO_Command : process (Clk)
begin -- process Execute_FIFO_Command
if Clk'event and Clk = '1' then
fifo_Write <= '0';
fifo_Read <= '0';
if (execute_3 = '0') and (execute_2 = '1') then
if (command = UART_WRITE_BYTE) then
fifo_Write <= '1';
end if;
if (command = UART_READ_BYTE) then
fifo_Read <= '1';
end if;
end if;
execute_3 <= execute_2;
execute_2 <= execute_1;
execute_1 <= execute;
end if;
end process Execute_FIFO_Command;
-- Since only one bit can change in the status register at time
-- we don't need to synchronize them with the DRCK clock
status_reg(7) <= fifo_Data_Present;
status_reg(6) <= tx_Buffer_Full_I;
status_reg(5) <= not rx_Data_Present_I;
status_reg(4) <= rx_Buffer_Full_I;
status_reg(3) <= '0'; -- FSL0_S_Exists;
status_reg(2) <= '0'; -- FSL0_M_Full;
status_reg(1) <= '0'; -- FSL_Read_UnderRun;
status_reg(0) <= '0'; -- FSL_Write_OverRun;
-- Read UART registers
TDO_Register : process (DRCK, config_with_scan_reset) is
begin -- process TDO_Register
if config_with_scan_reset = '1' then
tdo_reg <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if (CAPTURE = '1') then
case Command is
when UART_READ_STATUS =>
tdo_reg <= (others => '0');
tdo_reg(tdo_reg'right-status_reg'length+1 to tdo_reg'right) <= status_reg;
when others =>
tdo_reg <= fifo_DOut;
end case;
elsif SHIFT = '1' then
tdo_reg <= '0' & tdo_reg(tdo_reg'left to tdo_reg'right-1);
end if;
end if;
end process TDO_Register;
uart_TDO <= tdo_reg(tdo_reg'right);
-----------------------------------------------------------------------------
-- TDI Register
-----------------------------------------------------------------------------
TDI_Register : process (DRCK, config_with_scan_reset) is
begin -- process TDI_Register
if config_with_scan_reset = '1' then
fifo_Din <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if shifting_Data = '1' then
fifo_Din(fifo_Din'left+1 to fifo_Din'right) <=
fifo_Din(fifo_Din'left to fifo_Din'right-1);
fifo_Din(0) <= TDI;
end if;
end if;
end process TDI_Register;
---------------------------------------------------------------------------
-- FIFO
---------------------------------------------------------------------------
RX_FIFO_I : SRL_FIFO
generic map (
C_TARGET => C_TARGET, -- [TARGET_FAMILY_TYPE]
C_DATA_BITS => C_UART_WIDTH, -- [natural]
C_DEPTH => 16) -- [natural]
port map (
Clk => Clk, -- [in std_logic]
Reset => Reset_RX_FIFO, -- [in std_logic]
FIFO_Write => fifo_Write, -- [in std_logic]
Data_In => fifo_Din(0 to C_UART_WIDTH-1), -- [in std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Read => Read_RX_FIFO, -- [in std_logic]
Data_Out => RX_Data, -- [out std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Full => rx_Buffer_Full_I, -- [out std_logic]
Data_Exists => rx_Data_Present_I); -- [out std_logic]
RX_Data_Present <= rx_Data_Present_I;
RX_Buffer_Full <= rx_Buffer_Full_I;
-- Discard transmit data until XMD enables buffered mode.
tx_fifo_wen <= Write_TX_FIFO and tx_buffered_2;
TX_FIFO_I : SRL_FIFO
generic map (
C_TARGET => C_TARGET, -- [TARGET_FAMILY_TYPE]
C_DATA_BITS => C_UART_WIDTH, -- [natural]
C_DEPTH => 16) -- [natural]
port map (
Clk => Clk, -- [in std_logic]
Reset => Reset_TX_FIFO, -- [in std_logic]
FIFO_Write => tx_fifo_wen, -- [in std_logic]
Data_In => TX_Data, -- [in std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Read => fifo_Read, -- [in std_logic]
Data_Out => fifo_DOut, -- [out std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Full => TX_Buffer_Full_I, -- [out std_logic]
Data_Exists => fifo_Data_Present); -- [out std_logic]
TX_Buffer_Full <= TX_Buffer_Full_I;
TX_Buffer_Empty <= not fifo_Data_Present;
end generate Use_UART;
No_UART : if (C_USE_UART = 0) generate
begin
ext_BRK_i <= '0';
uart_TDO <= '0';
RX_Data <= (others => '0');
RX_Data_Present <= '0';
RX_BUFFER_FULL <= '0';
TX_Buffer_Full <= '0';
TX_Buffer_Empty <= '1';
end generate No_UART;
-----------------------------------------------------------------------------
-- Bus Master Debug Memory Access section
-----------------------------------------------------------------------------
Use_Dbg_Mem_Access : if (C_DBG_MEM_ACCESS = 1) generate
signal input : std_logic_vector(0 to C_M_AXI_DATA_WIDTH-1);
signal output : std_logic_vector(0 to C_M_AXI_DATA_WIDTH-1);
signal status : std_logic_vector(0 to 7);
signal execute : std_logic := '0';
signal execute_1 : std_logic := '0';
signal execute_2 : std_logic := '0';
signal execute_3 : std_logic := '0';
signal clear_overrun_1 : std_logic := '0';
signal clear_overrun_2 : std_logic := '0';
signal access_idle_1 : std_logic := '0';
signal access_idle_2 : std_logic := '0';
signal rd_wr_len : std_logic_vector(0 to 4) := (others => '0');
signal rd_wr_size : std_logic_vector(0 to 1) := (others => '0');
signal rd_wr_excl : std_logic := '0';
signal rd_resp_zero : boolean;
signal wr_resp_zero : boolean;
signal data_cmd_reset : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of execute_1 : signal is "TRUE";
attribute ASYNC_REG of execute_2 : signal is "TRUE";
attribute ASYNC_REG of clear_overrun_1 : signal is "TRUE";
attribute ASYNC_REG of clear_overrun_2 : signal is "TRUE";
attribute ASYNC_REG of access_idle_1 : signal is "TRUE";
attribute ASYNC_REG of access_idle_2 : signal is "TRUE";
begin
-----------------------------------------------------------------------------
-- Control Register
-----------------------------------------------------------------------------
Control_Register : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
rd_wr_excl <= '0'; -- no exclusive
rd_wr_size <= "10"; -- word size
rd_wr_len <= (others => '0'); -- single word burst
elsif UPDATE'event and UPDATE = '1' then
if command = BUSM_WRITE_CONTROL and data_cmd = '1' then
rd_wr_excl <= tdi_shifter(0);
rd_wr_size <= tdi_shifter(1 to 2);
rd_wr_len <= tdi_shifter(3 to 7);
end if;
end if;
end process Control_Register;
Master_rd_len <= rd_wr_len;
Master_wr_len <= rd_wr_len;
Master_rd_size <= rd_wr_size;
Master_wr_size <= rd_wr_size;
Master_rd_excl <= rd_wr_excl;
Master_wr_excl <= rd_wr_excl;
-----------------------------------------------------------------------------
-- Command Registers
-----------------------------------------------------------------------------
data_cmd_reset <= data_cmd when Scan_Reset_Sel = '0' else
not Scan_Reset;
Execute_Bus_Command : process (UPDATE, data_cmd_reset)
begin -- process Execute_Bus_Command
if data_cmd_reset = '0' then
execute <= '0';
elsif UPDATE'event and UPDATE = '1' then
if (command = BUSM_WRITE_COMMAND) or
(command = BUSM_READ_DATA) or
(command = BUSM_WRITE_DATA) then
execute <= '1';
else
execute <= '0';
end if;
end if;
end process Execute_Bus_Command;
Execute_Data_Command : process (M_AXI_ACLK)
begin -- process Execute_Data_Command
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then
if M_AXI_ARESETn = '0' then
execute_3 <= '0';
execute_2 <= '0';
execute_1 <= '0';
Master_data_wr <= '0';
Master_data_rd <= '0';
Master_rd_start <= '0';
Master_wr_start <= '0';
master_overrun <= '0';
master_error <= '0';
clear_overrun_2 <= '0';
clear_overrun_1 <= '0';
rd_resp_zero <= true;
wr_resp_zero <= true;
else
Master_data_wr <= '0';
Master_data_rd <= '0';
Master_rd_start <= '0';
Master_wr_start <= '0';
if (execute_3 = '0') and (execute_2 = '1') then
if (Master_rd_idle = '1') and (Master_wr_idle = '1') then
if (command = BUSM_WRITE_DATA) then
Master_data_wr <= '1';
end if;
if (command = BUSM_READ_DATA) then
Master_data_rd <= '1';
end if;
if (command = BUSM_WRITE_COMMAND) then
Master_rd_start <= Master_data_empty;
Master_wr_start <= not Master_data_empty;
master_error <= '0';
end if;
master_overrun <= '0';
else
master_overrun <= '1';
end if;
end if;
execute_3 <= execute_2;
execute_2 <= execute_1;
execute_1 <= execute;
if clear_overrun_2 = '1' then
master_overrun <= '0';
master_error <= '0';
end if;
clear_overrun_2 <= clear_overrun_1;
clear_overrun_1 <= clear_overrun;
if (Master_rd_resp /= "00" and rd_resp_zero) or (Master_wr_resp /= "00" and wr_resp_zero) then
master_error <= '1';
end if;
rd_resp_zero <= Master_rd_resp = "00";
wr_resp_zero <= Master_wr_resp = "00";
end if;
end if;
end process Execute_Data_Command;
-----------------------------------------------------------------------------
-- Status Register and Data Read Register
-----------------------------------------------------------------------------
-- We don't need to synchronize status with DRCK clock
status(7) <= '0';
status(6) <= '0';
status(4 to 5) <= Master_rd_resp;
status(2 to 3) <= Master_wr_resp;
status(1) <= Master_rd_idle;
status(0) <= Master_wr_idle;
Output_Register : process (DRCK, config_with_scan_reset) is
begin -- process Output_Register
if config_with_scan_reset = '1' then
output <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if (CAPTURE = '1') then
case Command is
when BUSM_READ_STATUS =>
output <= (others => '0');
output(output'right-status'length+1 to output'right) <= status;
when others =>
output <= Master_data_out;
end case;
elsif SHIFT = '1' then
output <= '0' & output(output'left to output'right-1);
end if;
end if;
end process Output_Register;
master_TDO <= output(output'right);
-----------------------------------------------------------------------------
-- Write Data and Read/Write Address Register
-----------------------------------------------------------------------------
Input_Register : process (DRCK, config_with_scan_reset) is
begin -- process Input_Register
if config_with_scan_reset = '1' then
input <= (others => '0');
access_idle_2 <= '0';
access_idle_1 <= '0';
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if shifting_Data = '1' and data_cmd = '1' and access_idle_2 = '1' and
(command = BUSM_WRITE_DATA or command = BUSM_WRITE_COMMAND) then
input(input'left+1 to input'right) <= input(input'left to input'right-1);
input(0) <= TDI;
end if;
access_idle_2 <= access_idle_1;
access_idle_1 <= Master_rd_idle and Master_wr_idle;
end if;
end process Input_Register;
Master_rd_addr <= input;
Master_wr_addr <= input;
Master_data_in <= input;
end generate Use_Dbg_Mem_Access;
No_Dbg_Mem_Access : if (C_DBG_MEM_ACCESS = 0) generate
begin
master_TDO <= '0';
master_overrun <= '0';
master_error <= '0';
Master_rd_start <= '0';
Master_rd_addr <= (others => '0');
Master_rd_len <= (others => '0');
Master_rd_size <= (others => '0');
Master_rd_excl <= '0';
Master_wr_start <= '0';
Master_wr_addr <= (others => '0');
Master_wr_len <= (others => '0');
Master_wr_size <= (others => '0');
Master_wr_excl <= '0';
Master_data_rd <= '0';
Master_data_wr <= '0';
Master_data_in <= (others => '0');
end generate No_Dbg_Mem_Access;
-----------------------------------------------------------------------------
-- AXI Slave Debug Register Access section
-----------------------------------------------------------------------------
Use_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 1 and C_USE_BSCAN /= 3) generate
signal access_lock : std_logic := '0';
signal access_lock_cmd_rst : std_logic;
signal dbgreg_access_lock_1 : std_logic := '0';
signal force_lock : std_logic := '0';
signal force_lock_cmd_rst : std_logic;
signal status_reg : std_logic_vector(0 to 1);
signal tdo_reg : std_logic_vector(0 to 1) := (others => '0');
begin
-----------------------------------------------------------------------------
-- Handle force lock command: first set it on update and then remove after
-- it has been detected in the other clock region
-----------------------------------------------------------------------------
force_lock_cmd_rst <= Config_Reset or dbgreg_unlocked when Scan_Reset_Sel = '0' else
Scan_Reset;
Force_Lock_Command_Handle : process (UPDATE, force_lock_cmd_rst)
begin -- process Force_Lock_Command_Handle
if force_lock_cmd_rst = '1' then
force_lock <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = AXIS_WRITE_COMMAND and data_cmd = '1' then
force_lock <= tdi_shifter(0);
end if;
end if;
end process Force_Lock_Command_Handle;
JTAG_Force_Lock <= force_lock;
-----------------------------------------------------------------------------
-- Handle normal lock command: set it on update if not locked by other clock
-- region and remove if force lock by other clock region
-----------------------------------------------------------------------------
access_lock_cmd_rst <= Config_Reset or DbgReg_Force_Lock when Scan_Reset_Sel = '0' else
Scan_Reset;
Access_Lock_Command_Handle : process (UPDATE, access_lock_cmd_rst)
begin -- process Access_Lock_Command_Handle
if access_lock_cmd_rst = '1' then
access_lock <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = AXIS_WRITE_COMMAND and data_cmd = '1' then
access_lock <= tdi_shifter(1) and not dbgreg_access_lock_1;
end if;
end if;
end process Access_Lock_Command_Handle;
Sync_Access_Lock : process (DRCK, config_with_scan_reset) is
begin -- process Sync_Access_Lock
if config_with_scan_reset = '1' then
dbgreg_access_lock_1 <= '0';
elsif DRCK'event and DRCK = '1' then -- rising clock edge
dbgreg_access_lock_1 <= DbgReg_Access_Lock;
end if;
end process Sync_Access_Lock;
JTAG_Access_Lock <= access_lock;
-----------------------------------------------------------------------------
-- Read AXI Slave status register
-----------------------------------------------------------------------------
status_reg(1) <= access_lock;
status_reg(0) <= dbgreg_access_lock_1;
TDO_Register : process (DRCK, config_with_scan_reset) is
begin -- process TDO_Register
if config_with_scan_reset = '1' then
tdo_reg <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if CAPTURE = '1' then
-- AXIS_READ_STATUS
tdo_reg <= status_reg;
elsif SHIFT = '1' then
tdo_reg <= '0' & tdo_reg(tdo_reg'left to tdo_reg'right-1);
end if;
end if;
end process TDO_Register;
axis_TDO <= tdo_reg(tdo_reg'right);
JTAG_Clear_Overrun <= clear_overrun;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Acess : if (C_DBG_REG_ACCESS = 0 or C_USE_BSCAN = 3) generate
begin
axis_TDO <= '0';
JTAG_Access_Lock <= '0';
JTAG_Force_Lock <= '0';
JTAG_Clear_Overrun <= '0';
end generate No_Dbg_Reg_Acess;
-----------------------------------------------------------------------------
-- Cross trigger section
-----------------------------------------------------------------------------
Use_Cross_Trigger : if (C_USE_CROSS_TRIGGER = 1) generate
constant C_NUM_CT : integer := C_NUM_DBG_CT + C_NUM_EXT_CT;
type dbg_in_all_type is array(0 to C_EN_WIDTH - 1) of std_logic_vector(0 to C_NUM_DBG_CT - 1);
type in_all_type is array(0 to C_EN_WIDTH - 1) of std_logic_vector(0 to C_NUM_CT - 1);
type dbg_out_type is array(0 to C_NUM_DBG_CT - 1) of std_logic_vector(0 to 3);
type dbg_out_all_type is array(0 to C_EN_WIDTH - 1) of dbg_out_type;
type ext_out_type is array(0 to C_NUM_EXT_CT - 1) of std_logic_vector(0 to 3);
constant C_DBG_IN_CTRL : std_logic_vector(0 to C_NUM_DBG_CT - 1) := (0 to C_NUM_EXT_CT - 1 => '1', others => '0');
constant C_DBG_OUT_CTRL : dbg_out_type := ("1001", "1010", "1011", "1100", "1101", "1101", "1101", "1101");
constant C_EXT_IN_CTRL : std_logic_vector(0 to C_NUM_EXT_CT - 1) := (others => '1');
constant C_EXT_OUT_CTRL : ext_out_type := ("0001", "0010", "0011", "0100");
signal dbg_trig_in_i : dbg_trig_type;
signal dbg_trig_Ack_Out_i : dbg_trig_type;
signal in_andor_ctrl : std_logic := '0';
signal in_ctrl : dbg_in_all_type := (others => C_DBG_IN_CTRL);
signal out_ctrl : dbg_out_all_type := (others => C_DBG_OUT_CTRL);
signal ext_in_ctrl : std_logic_vector(0 to C_NUM_EXT_CT - 1) := C_EXT_IN_CTRL;
signal ext_out_ctrl : ext_out_type := C_EXT_OUT_CTRL;
signal status_reg : std_logic_vector(0 to C_NUM_CT * 2 - 1) := (others => '0');
signal tdo_reg : std_logic_vector(0 to C_NUM_CT * 2 - 1) := (others => '0');
begin
-----------------------------------------------------------------------------
-- Assign trigger outputs
-----------------------------------------------------------------------------
Assign_Outputs: process (in_ctrl, in_andor_ctrl, ext_in_ctrl,
out_ctrl, ext_out_ctrl, dbg_trig_in_i, Ext_Trig_In,
dbg_trig_ack_out_i, Ext_Trig_Ack_Out) is
variable in_value_or : dbg_in_all_type;
variable in_value_and : dbg_in_all_type;
variable in_value : in_all_type;
variable in_value_ext_or : std_logic_vector(0 to C_NUM_DBG_CT - 1);
variable in_value_ext_and : std_logic_vector(0 to C_NUM_DBG_CT - 1);
variable in_value_ext : std_logic_vector(0 to C_NUM_CT - 1);
variable out_value : std_logic_vector(0 to 15);
variable out_ack_value : std_logic_vector(0 to 15);
variable dbg_ack_value : dbg_in_all_type;
variable ext_ack_value : std_logic_vector(0 to C_NUM_EXT_CT - 1);
variable index : integer range 0 to 15;
begin -- process Assign_Outputs
-- Determine in_value per processor from inputs and input select control registers
for N in 0 to C_EN_WIDTH - 1 loop
for K in 0 to C_NUM_DBG_CT - 1 loop
in_value_or(N)(K) := '0';
in_value_and(N)(K) := '1';
for I in 0 to C_EN_WIDTH - 1 loop
if N /= I then -- exclude own processor input
in_value_or(N)(K) := in_value_or(N)(K) or (dbg_trig_in_i(I)(K) and in_ctrl(I)(K));
in_value_and(N)(K) := in_value_and(N)(K) and (dbg_trig_in_i(I)(K) and in_ctrl(I)(K));
end if;
end loop;
end loop;
if in_andor_ctrl = '1' then
in_value(N)(0 to C_NUM_DBG_CT - 1) := in_value_and(N);
else
in_value(N)(0 to C_NUM_DBG_CT - 1) := in_value_or(N);
end if;
for K in 0 to C_NUM_EXT_CT - 1 loop
in_value(N)(K + C_NUM_DBG_CT) := Ext_Trig_In(K) and ext_in_ctrl(K);
end loop;
end loop;
-- Determine in_value_ext from inputs and input select control registers
for K in 0 to C_NUM_DBG_CT - 1 loop
in_value_ext_or(K) := '0';
in_value_ext_and(K) := '1';
for I in 0 to C_EN_WIDTH - 1 loop
in_value_ext_or(K) := in_value_ext_or(K) or (dbg_trig_in_i(I)(K) and in_ctrl(I)(K));
in_value_ext_and(K) := in_value_ext_and(K) and (dbg_trig_in_i(I)(K) and in_ctrl(I)(K));
end loop;
if in_andor_ctrl = '1' then
in_value_ext(0 to C_NUM_DBG_CT - 1) := in_value_ext_and;
else
in_value_ext(0 to C_NUM_DBG_CT - 1) := in_value_ext_or;
end if;
for K in 0 to C_NUM_EXT_CT - 1 loop
in_value_ext(K + C_NUM_DBG_CT) := Ext_Trig_In(K) and ext_in_ctrl(K);
end loop;
end loop;
-- Assign outputs from out_value based on out_ctrl control register
dbg_trig_out_i <= (others => (others => '0'));
for N in 0 to C_EN_WIDTH - 1 loop
out_value := '1' & in_value(N) & "000"; -- 0000: constant 1, N=K: constant 0
for K in 0 to C_NUM_DBG_CT - 1 loop
index := to_integer(unsigned(out_ctrl(N)(K)));
dbg_trig_out_i(N)(K) <= out_value(index);
end loop;
end loop;
-- Assign external outputs from in_value based on ext_out_ctrl control register
ext_trig_out_i <= (others => '0');
out_value := '1' & in_value_ext & "000"; -- 0000: constant 1, 1101: constant 0
for K in 0 to C_NUM_EXT_CT - 1 loop
index := to_integer(unsigned(ext_out_ctrl(K)));
ext_trig_out_i(K) <= out_value(index);
end loop;
-- Assign dbg_trig_ack_in_i from dbg_ack_value and Ext_Trig_Ack_Out
-- Create combined acknowledge from all processors and external trig
dbg_ack_value := (others => (others => '0'));
dbg_trig_ack_in_i <= (others => (others => '0'));
for K in 0 to C_NUM_DBG_CT - 1 loop
for N in 0 to C_EN_WIDTH - 1 loop
index := to_integer(unsigned(out_ctrl(N)(K)));
out_ack_value := '0' & dbg_trig_ack_out_i(N) & Ext_Trig_Ack_Out & "000";
dbg_ack_value(N)(K) := dbg_ack_value(N)(K) or out_ack_value(index);
end loop;
end loop;
for K in 0 to C_NUM_DBG_CT - 1 loop
for N in 0 to C_EN_WIDTH - 1 loop
dbg_trig_ack_in_i(N)(K) <= dbg_ack_value(N)(K) and in_ctrl(N)(K);
end loop;
end loop;
-- Assign ext_trig_ack_in_i from dbg_ack_value and Ext_Trig_Ack_Out
-- Create combined acknowledge from all processors and external trig
ext_ack_value := (others => '0');
ext_trig_ack_in_i <= (others => '0');
for K in 0 to C_NUM_EXT_CT - 1 loop
index := to_integer(unsigned(ext_out_ctrl(K)));
for N in 0 to C_EN_WIDTH - 1 loop
out_ack_value := '0' & dbg_trig_ack_out_i(N) & Ext_Trig_Ack_Out & "000";
ext_ack_value(K) := ext_ack_value(K) or out_ack_value(index);
end loop;
end loop;
for K in 0 to C_NUM_EXT_CT - 1 loop
ext_trig_ack_in_i(K) <= ext_ack_value(K) and ext_in_ctrl(K);
end loop;
end process Assign_Outputs;
-----------------------------------------------------------------------------
-- Control Registers:
-- 4 output select + 8 input mask + and/or + 3 (index 0-7) = 16
-- 4 output select + 4 input mask + 2 (index 0-3) = 10
-----------------------------------------------------------------------------
Control_Registers : process (UPDATE, config_with_scan_reset)
variable dbg_index : std_logic_vector(0 to 2);
variable ext_index : std_logic_vector(0 to 1);
variable K : integer;
begin
if config_with_scan_reset = '1' then
in_andor_ctrl <= '0';
in_ctrl <= (others => C_DBG_IN_CTRL);
out_ctrl <= (others => C_DBG_OUT_CTRL);
ext_in_ctrl <= C_EXT_IN_CTRL;
ext_out_ctrl <= C_EXT_OUT_CTRL;
elsif UPDATE'event and UPDATE = '1' then
if data_cmd = '1' then
if command = CT_WRITE_CTRL and data_cmd = '1' then
dbg_index := tdi_shifter(4 + C_NUM_DBG_CT + 1 to 4 + C_NUM_DBG_CT + 1 + 2);
K := to_integer(unsigned(dbg_index));
for I in 0 to C_EN_WIDTH - 1 loop
if mb_debug_enabled_i(I) = '1' then
out_ctrl(I)(K) <= tdi_shifter(0 to 3);
in_ctrl(I) <= tdi_shifter(4 to 4 + C_NUM_DBG_CT - 1);
end if;
end loop;
in_andor_ctrl <= tdi_shifter(4 + C_NUM_DBG_CT);
end if;
if command = CT_WRITE_EXT_CTRL and data_cmd = '1' then
ext_index := tdi_shifter(4 + C_NUM_EXT_CT to 4 + C_NUM_EXT_CT + 1);
K := to_integer(unsigned(ext_index));
ext_out_ctrl(K) <= tdi_shifter(0 to 3);
ext_in_ctrl <= tdi_shifter(4 to 4 + C_NUM_EXT_CT - 1);
end if;
end if;
end if;
end process Control_Registers;
-----------------------------------------------------------------------------
-- Status Register
-----------------------------------------------------------------------------
Assign_Status: process (dbg_trig_out_i, ext_trig_out_i, dbg_trig_in_i, Ext_Trig_In, mb_debug_enabled_i) is
begin -- process Assign_Status
status_reg <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
if mb_debug_enabled_i(I) = '1' then
status_reg(0 to C_NUM_DBG_CT * 2 - 1) <= dbg_trig_out_i(I) & dbg_trig_in_i(I);
end if;
end loop;
status_reg(C_NUM_DBG_CT * 2 to C_NUM_CT * 2 - 1) <= ext_trig_out_i & Ext_Trig_In;
end process Assign_Status;
TDO_Register : process (DRCK, config_with_scan_reset) is
begin -- process TDO_Register
if config_with_scan_reset = '1' then
tdo_reg <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if (CAPTURE = '1') then
-- CT_READ_STATUS
tdo_reg <= status_reg;
elsif SHIFT = '1' then
tdo_reg <= '0' & tdo_reg(tdo_reg'left to tdo_reg'right-1);
end if;
end if;
end process TDO_Register;
ct_TDO <= tdo_reg(tdo_reg'right);
dbg_trig_in_i(0) <= Dbg_Trig_In_0;
dbg_trig_in_i(1) <= Dbg_Trig_In_1;
dbg_trig_in_i(2) <= Dbg_Trig_In_2;
dbg_trig_in_i(3) <= Dbg_Trig_In_3;
dbg_trig_in_i(4) <= Dbg_Trig_In_4;
dbg_trig_in_i(5) <= Dbg_Trig_In_5;
dbg_trig_in_i(6) <= Dbg_Trig_In_6;
dbg_trig_in_i(7) <= Dbg_Trig_In_7;
dbg_trig_in_i(8) <= Dbg_Trig_In_8;
dbg_trig_in_i(9) <= Dbg_Trig_In_9;
dbg_trig_in_i(10) <= Dbg_Trig_In_10;
dbg_trig_in_i(11) <= Dbg_Trig_In_11;
dbg_trig_in_i(12) <= Dbg_Trig_In_12;
dbg_trig_in_i(13) <= Dbg_Trig_In_13;
dbg_trig_in_i(14) <= Dbg_Trig_In_14;
dbg_trig_in_i(15) <= Dbg_Trig_In_15;
dbg_trig_in_i(16) <= Dbg_Trig_In_16;
dbg_trig_in_i(17) <= Dbg_Trig_In_17;
dbg_trig_in_i(18) <= Dbg_Trig_In_18;
dbg_trig_in_i(19) <= Dbg_Trig_In_19;
dbg_trig_in_i(20) <= Dbg_Trig_In_20;
dbg_trig_in_i(21) <= Dbg_Trig_In_21;
dbg_trig_in_i(22) <= Dbg_Trig_In_22;
dbg_trig_in_i(23) <= Dbg_Trig_In_23;
dbg_trig_in_i(24) <= Dbg_Trig_In_24;
dbg_trig_in_i(25) <= Dbg_Trig_In_25;
dbg_trig_in_i(26) <= Dbg_Trig_In_26;
dbg_trig_in_i(27) <= Dbg_Trig_In_27;
dbg_trig_in_i(28) <= Dbg_Trig_In_28;
dbg_trig_in_i(29) <= Dbg_Trig_In_29;
dbg_trig_in_i(30) <= Dbg_Trig_In_30;
dbg_trig_in_i(31) <= Dbg_Trig_In_31;
dbg_trig_ack_out_i(0) <= Dbg_Trig_Ack_Out_0;
dbg_trig_ack_out_i(1) <= Dbg_Trig_Ack_Out_1;
dbg_trig_ack_out_i(2) <= Dbg_Trig_Ack_Out_2;
dbg_trig_ack_out_i(3) <= Dbg_Trig_Ack_Out_3;
dbg_trig_ack_out_i(4) <= Dbg_Trig_Ack_Out_4;
dbg_trig_ack_out_i(5) <= Dbg_Trig_Ack_Out_5;
dbg_trig_ack_out_i(6) <= Dbg_Trig_Ack_Out_6;
dbg_trig_ack_out_i(7) <= Dbg_Trig_Ack_Out_7;
dbg_trig_ack_out_i(8) <= Dbg_Trig_Ack_Out_8;
dbg_trig_ack_out_i(9) <= Dbg_Trig_Ack_Out_9;
dbg_trig_ack_out_i(10) <= Dbg_Trig_Ack_Out_10;
dbg_trig_ack_out_i(11) <= Dbg_Trig_Ack_Out_11;
dbg_trig_ack_out_i(12) <= Dbg_Trig_Ack_Out_12;
dbg_trig_ack_out_i(13) <= Dbg_Trig_Ack_Out_13;
dbg_trig_ack_out_i(14) <= Dbg_Trig_Ack_Out_14;
dbg_trig_ack_out_i(15) <= Dbg_Trig_Ack_Out_15;
dbg_trig_ack_out_i(16) <= Dbg_Trig_Ack_Out_16;
dbg_trig_ack_out_i(17) <= Dbg_Trig_Ack_Out_17;
dbg_trig_ack_out_i(18) <= Dbg_Trig_Ack_Out_18;
dbg_trig_ack_out_i(19) <= Dbg_Trig_Ack_Out_19;
dbg_trig_ack_out_i(20) <= Dbg_Trig_Ack_Out_20;
dbg_trig_ack_out_i(21) <= Dbg_Trig_Ack_Out_21;
dbg_trig_ack_out_i(22) <= Dbg_Trig_Ack_Out_22;
dbg_trig_ack_out_i(23) <= Dbg_Trig_Ack_Out_23;
dbg_trig_ack_out_i(24) <= Dbg_Trig_Ack_Out_24;
dbg_trig_ack_out_i(25) <= Dbg_Trig_Ack_Out_25;
dbg_trig_ack_out_i(26) <= Dbg_Trig_Ack_Out_26;
dbg_trig_ack_out_i(27) <= Dbg_Trig_Ack_Out_27;
dbg_trig_ack_out_i(28) <= Dbg_Trig_Ack_Out_28;
dbg_trig_ack_out_i(29) <= Dbg_Trig_Ack_Out_29;
dbg_trig_ack_out_i(30) <= Dbg_Trig_Ack_Out_30;
dbg_trig_ack_out_i(31) <= Dbg_Trig_Ack_Out_31;
end generate Use_Cross_Trigger;
No_Cross_Trigger : if (C_USE_CROSS_TRIGGER = 0) generate
begin
dbg_trig_ack_in_i <= (others => (others => '0'));
dbg_trig_out_i <= (others => (others => '0'));
ext_trig_ack_in_i <= (others => '0');
ext_trig_out_i <= (others => '0');
ct_TDO <= '0';
end generate No_Cross_Trigger;
Dbg_Trig_Ack_In_0 <= dbg_trig_ack_in_i(0);
Dbg_Trig_Ack_In_1 <= dbg_trig_ack_in_i(1);
Dbg_Trig_Ack_In_2 <= dbg_trig_ack_in_i(2);
Dbg_Trig_Ack_In_3 <= dbg_trig_ack_in_i(3);
Dbg_Trig_Ack_In_4 <= dbg_trig_ack_in_i(4);
Dbg_Trig_Ack_In_5 <= dbg_trig_ack_in_i(5);
Dbg_Trig_Ack_In_6 <= dbg_trig_ack_in_i(6);
Dbg_Trig_Ack_In_7 <= dbg_trig_ack_in_i(7);
Dbg_Trig_Ack_In_8 <= dbg_trig_ack_in_i(8);
Dbg_Trig_Ack_In_9 <= dbg_trig_ack_in_i(9);
Dbg_Trig_Ack_In_10 <= dbg_trig_ack_in_i(10);
Dbg_Trig_Ack_In_11 <= dbg_trig_ack_in_i(11);
Dbg_Trig_Ack_In_12 <= dbg_trig_ack_in_i(12);
Dbg_Trig_Ack_In_13 <= dbg_trig_ack_in_i(13);
Dbg_Trig_Ack_In_14 <= dbg_trig_ack_in_i(14);
Dbg_Trig_Ack_In_15 <= dbg_trig_ack_in_i(15);
Dbg_Trig_Ack_In_16 <= dbg_trig_ack_in_i(16);
Dbg_Trig_Ack_In_17 <= dbg_trig_ack_in_i(17);
Dbg_Trig_Ack_In_18 <= dbg_trig_ack_in_i(18);
Dbg_Trig_Ack_In_19 <= dbg_trig_ack_in_i(19);
Dbg_Trig_Ack_In_20 <= dbg_trig_ack_in_i(20);
Dbg_Trig_Ack_In_21 <= dbg_trig_ack_in_i(21);
Dbg_Trig_Ack_In_22 <= dbg_trig_ack_in_i(22);
Dbg_Trig_Ack_In_23 <= dbg_trig_ack_in_i(23);
Dbg_Trig_Ack_In_24 <= dbg_trig_ack_in_i(24);
Dbg_Trig_Ack_In_25 <= dbg_trig_ack_in_i(25);
Dbg_Trig_Ack_In_26 <= dbg_trig_ack_in_i(26);
Dbg_Trig_Ack_In_27 <= dbg_trig_ack_in_i(27);
Dbg_Trig_Ack_In_28 <= dbg_trig_ack_in_i(28);
Dbg_Trig_Ack_In_29 <= dbg_trig_ack_in_i(29);
Dbg_Trig_Ack_In_30 <= dbg_trig_ack_in_i(30);
Dbg_Trig_Ack_In_31 <= dbg_trig_ack_in_i(31);
Dbg_Trig_Out_0 <= dbg_trig_out_i(0);
Dbg_Trig_Out_1 <= dbg_trig_out_i(1);
Dbg_Trig_Out_2 <= dbg_trig_out_i(2);
Dbg_Trig_Out_3 <= dbg_trig_out_i(3);
Dbg_Trig_Out_4 <= dbg_trig_out_i(4);
Dbg_Trig_Out_5 <= dbg_trig_out_i(5);
Dbg_Trig_Out_6 <= dbg_trig_out_i(6);
Dbg_Trig_Out_7 <= dbg_trig_out_i(7);
Dbg_Trig_Out_8 <= dbg_trig_out_i(8);
Dbg_Trig_Out_9 <= dbg_trig_out_i(9);
Dbg_Trig_Out_10 <= dbg_trig_out_i(10);
Dbg_Trig_Out_11 <= dbg_trig_out_i(11);
Dbg_Trig_Out_12 <= dbg_trig_out_i(12);
Dbg_Trig_Out_13 <= dbg_trig_out_i(13);
Dbg_Trig_Out_14 <= dbg_trig_out_i(14);
Dbg_Trig_Out_15 <= dbg_trig_out_i(15);
Dbg_Trig_Out_16 <= dbg_trig_out_i(16);
Dbg_Trig_Out_17 <= dbg_trig_out_i(17);
Dbg_Trig_Out_18 <= dbg_trig_out_i(18);
Dbg_Trig_Out_19 <= dbg_trig_out_i(19);
Dbg_Trig_Out_20 <= dbg_trig_out_i(20);
Dbg_Trig_Out_21 <= dbg_trig_out_i(21);
Dbg_Trig_Out_22 <= dbg_trig_out_i(22);
Dbg_Trig_Out_23 <= dbg_trig_out_i(23);
Dbg_Trig_Out_24 <= dbg_trig_out_i(24);
Dbg_Trig_Out_25 <= dbg_trig_out_i(25);
Dbg_Trig_Out_26 <= dbg_trig_out_i(26);
Dbg_Trig_Out_27 <= dbg_trig_out_i(27);
Dbg_Trig_Out_28 <= dbg_trig_out_i(28);
Dbg_Trig_Out_29 <= dbg_trig_out_i(29);
Dbg_Trig_Out_30 <= dbg_trig_out_i(30);
Dbg_Trig_Out_31 <= dbg_trig_out_i(31);
Ext_Trig_Ack_In <= ext_trig_ack_in_i;
Ext_Trig_Out <= ext_trig_out_i;
-----------------------------------------------------------------------------
-- Trace section (external, AXI stream, AXI master)
-----------------------------------------------------------------------------
Use_Trace_External : if (C_TRACE_OUTPUT = 1) generate
signal test_pattern : std_logic_vector(0 to 3) := (others => '0');
signal test_timed : std_logic := '0';
signal test_cont : std_logic := '0';
signal delay : std_logic_vector(0 to 7) := (others => '0');
signal new_test_pattern : std_logic_vector(0 to 3) := (others => '0');
signal new_test_start : std_logic := '0';
signal new_test_stop : std_logic := '0';
signal new_test_timed : std_logic := '0';
signal new_delay : std_logic_vector(0 to 7) := (others => '0');
signal trace_stopped_i : std_logic := '0';
signal execute : std_logic := '0';
signal execute_1 : std_logic := '0';
signal execute_2 : std_logic := '0';
signal execute_3 : std_logic := '0';
signal data_cmd_reset : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of execute_1 : signal is "TRUE";
attribute ASYNC_REG of execute_2 : signal is "TRUE";
begin
-----------------------------------------------------------------------------
-- Control Register (14 bits)
-----------------------------------------------------------------------------
Control_Register : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
test_pattern <= "0000"; -- no test pattern
test_timed <= '0'; -- no timed test pattern
test_cont <= '0'; -- no continuous test pattern
delay <= (others => '0'); -- no delay
elsif UPDATE'event and UPDATE = '1' then
if command = TRACE_WRITE_CONTROL and data_cmd = '1' then
test_pattern <= tdi_shifter(0 to 3);
test_timed <= tdi_shifter(4);
test_cont <= tdi_shifter(5);
delay <= tdi_shifter(6 to 13);
end if;
end if;
end process Control_Register;
data_cmd_reset <= data_cmd when Scan_Reset_Sel = '0' else
not Scan_Reset;
Execute_Command : process (UPDATE, data_cmd_reset)
begin -- process Execute_Command
if data_cmd_reset = '0' then
execute <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = TRACE_WRITE_CONTROL then
execute <= '1';
else
execute <= '0';
end if;
end if;
end process Execute_Command;
Execute_Test_Command : process (Trace_Clk)
begin -- process Execute_Test_Command
if Trace_Clk'event and Trace_Clk = '1' then
if Trace_Reset = '1' then
execute_3 <= '0';
execute_2 <= '0';
execute_1 <= '0';
else
if (execute_3 = '0') and (execute_2 = '1') then
-- Execute test
new_test_pattern <= test_pattern;
new_test_start <= test_cont or test_timed;
new_test_stop <= not (test_cont or test_timed);
new_test_timed <= test_timed;
new_delay <= delay;
trace_stopped_i <= test_cont or test_timed;
else
new_test_start <= '0';
new_test_stop <= '0';
end if;
execute_3 <= execute_2;
execute_2 <= execute_1;
execute_1 <= execute;
end if;
end if;
end process Execute_Test_Command;
Trace_Test_Pattern <= new_test_pattern;
Trace_Test_Start <= new_test_start;
Trace_Test_Stop <= new_test_stop;
Trace_Test_Timed <= new_test_timed;
Trace_Delay <= new_delay;
Trace_Stopped <= trace_stopped_i;
-- Unused
Master_dwr_addr <= (others => '0');
Master_dwr_len <= (others => '0');
trace_TDO <= '0';
end generate Use_Trace_External;
Use_Trace_AXI_Stream : if (C_TRACE_OUTPUT = 2) generate
signal delay : std_logic_vector(0 to 7) := (others => '0');
begin
-----------------------------------------------------------------------------
-- Control Register (8 bits)
-----------------------------------------------------------------------------
Control_Register : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
delay <= (others => '0'); -- no delay
elsif UPDATE'event and UPDATE = '1' then
if command = TRACE_WRITE_CONTROL and data_cmd = '1' then
delay <= tdi_shifter(0 to 7);
end if;
end if;
end process Control_Register;
Trace_Delay <= delay;
-- Unused
Trace_Test_Pattern <= (others => '0');
Trace_Test_Start <= '0';
Trace_Test_Stop <= '0';
Trace_Test_Timed <= '0';
Trace_Stopped <= '0';
Master_dwr_addr <= (others => '0');
Master_dwr_len <= (others => '0');
trace_TDO <= '0';
end generate Use_Trace_AXI_Stream;
Use_Trace_AXI_Master : if (C_TRACE_OUTPUT = 3) generate
constant C_BURST_LEN : integer := 4; -- Burst length 4 - Packet size 4*5 = 20
signal full_stop : std_logic := '0';
signal wrap : std_logic;
signal wr_resp : std_logic_vector(0 to 1);
signal output : std_logic_vector(0 to 31);
signal status : std_logic_vector(0 to 2);
signal low_addr : std_logic_vector(0 to 15) := (others => '0');
signal high_addr : std_logic_vector(0 to 15) := (others => '0');
signal execute : std_logic := '0';
signal execute_1 : std_logic := '0';
signal execute_2 : std_logic := '0';
signal execute_3 : std_logic := '0';
signal current_addr : std_logic_vector(0 to 29);
signal next_addr : std_logic_vector(0 to 29);
signal data_cmd_reset : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of execute_1 : signal is "TRUE";
attribute ASYNC_REG of execute_2 : signal is "TRUE";
begin
-----------------------------------------------------------------------------
-- Control Register (1 bit)
-----------------------------------------------------------------------------
Control_Register : process (UPDATE, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
full_stop <= '0'; -- no stop when full
elsif UPDATE'event and UPDATE = '1' then
if command = TRACE_WRITE_CONTROL and data_cmd = '1' then
full_stop <= tdi_shifter(0);
end if;
end if;
end process Control_Register;
-- Unused
Trace_Test_Pattern <= (others => '0');
Trace_Test_Start <= '0';
Trace_Test_Stop <= '0';
Trace_Test_Timed <= '0';
Trace_Delay <= (others => '0');
-----------------------------------------------------------------------------
-- Status Register
-----------------------------------------------------------------------------
-- We don't need to synchronize status with DRCK clock
status(0) <= wrap;
status(1 to 2) <= wr_resp;
Output_Register : process (DRCK, config_with_scan_reset) is
begin -- process Output_Register
if config_with_scan_reset = '1' then
output <= (others => '0');
elsif DRCK'event and DRCK = '1' then -- rising clock edge
if (CAPTURE = '1') then
case Command is
when TRACE_READ_STATUS =>
output <= (others => '0');
output(output'right-status'length+1 to output'right) <= status;
when others =>
output <= current_addr & "00";
end case;
elsif SHIFT = '1' then
output <= '0' & output(output'left to output'right-1);
end if;
end if;
end process Output_Register;
trace_TDO <= output(output'right);
-----------------------------------------------------------------------------
-- Low and High Address Registers
-----------------------------------------------------------------------------
Address_Registers : process (UPDATE, config_with_scan_reset) is
begin -- process Address_Registers
if config_with_scan_reset = '1' then
low_addr <= (others => '0');
high_addr <= (others => '0');
elsif UPDATE'event and UPDATE = '1' then
if data_cmd = '1' then
if command = TRACE_WRITE_LOW_ADDR then
low_addr <= tdi_shifter(0 to 15);
end if;
if command = TRACE_WRITE_HIGH_ADDR then
high_addr <= tdi_shifter(0 to 15);
end if;
end if;
end if;
end process Address_Registers;
-----------------------------------------------------------------------------
-- Handle current address and status
-----------------------------------------------------------------------------
data_cmd_reset <= data_cmd when Scan_Reset_Sel = '0' else
not Scan_Reset;
Execute_Command : process (UPDATE, data_cmd_reset)
begin -- process Execute_Command
if data_cmd_reset = '0' then
execute <= '0';
elsif UPDATE'event and UPDATE = '1' then
if command = TRACE_WRITE_CONTROL then
execute <= '1';
else
execute <= '0';
end if;
end if;
end process Execute_Command;
Execute_Addr_Status_Command : process (M_AXI_ACLK)
begin -- process Execute_Addr_Status_Command
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then
if M_AXI_ARESETn = '0' then
execute_3 <= '0';
execute_2 <= '0';
execute_1 <= '0';
wrap <= '0';
wr_resp <= (others => '0');
current_addr <= (others => '0');
Trace_Stopped <= '0';
else
if (execute_3 = '0') and (execute_2 = '1') then
-- Reset current address and clear status
wrap <= '0';
wr_resp <= (others => '0');
current_addr <= low_addr & (16 to 29 => '0');
Trace_Stopped <= '0';
else
-- Increment current address and set sticky response status after each write
if Master_dwr_done = '1' then
if wr_resp = "00" then
wr_resp <= Master_dwr_resp;
end if;
current_addr <= next_addr;
end if;
-- Stop trace or wrap if buffer full
if current_addr(0 to 15) = high_addr and current_addr(16 to 25) = (16 to 25 => '1') then
if full_stop = '1' then
Trace_Stopped <= '1';
else
wrap <= '1';
current_addr <= low_addr & (16 to 29 => '0');
end if;
end if;
end if;
execute_3 <= execute_2;
execute_2 <= execute_1;
execute_1 <= execute;
end if;
end if;
end process Execute_Addr_Status_Command;
next_addr <= std_logic_vector(unsigned(current_addr) + C_BURST_LEN);
Master_dwr_addr <= current_addr & "00";
Master_dwr_len <= std_logic_vector(to_unsigned(C_BURST_LEN - 1, 5));
end generate Use_Trace_AXI_Master;
No_Trace : if (C_TRACE_OUTPUT = 0) generate
begin
Trace_Test_Pattern <= (others => '0');
Trace_Test_Start <= '0';
Trace_Test_Stop <= '0';
Trace_Test_Timed <= '0';
Trace_Delay <= (others => '0');
Trace_Stopped <= '0';
Master_dwr_addr <= (others => '0');
Master_dwr_len <= (others => '0');
trace_TDO <= '0';
end generate No_Trace;
end architecture IMP;
-------------------------------------------------------------------------------
-- mdm_core.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_core.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- mdm_core.vhd
-- jtag_control.vhd
-- arbiter.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2003-02-13 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
-- stefana 2016-04-25 Added parallel synchronous debug interface
-- stefana 2016-06-01 Added wrappers for unisim primitives
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
entity MDM_Core is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_DEBUG_INTERFACE : integer;
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ADDR_WIDTH : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer
);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE+C_DEBUG_INTERFACE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE+C_DEBUG_INTERFACE-1);
bus2ip_cs : in std_logic_vector(0 to C_DEBUG_INTERFACE);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Disable_0 : out std_logic;
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_AWADDR_0 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_0 : out std_logic;
Dbg_AWREADY_0 : in std_logic;
Dbg_WDATA_0 : out std_logic_vector(31 downto 0);
Dbg_WVALID_0 : out std_logic;
Dbg_WREADY_0 : in std_logic;
Dbg_BRESP_0 : in std_logic_vector(1 downto 0);
Dbg_BVALID_0 : in std_logic;
Dbg_BREADY_0 : out std_logic;
Dbg_ARADDR_0 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_0 : out std_logic;
Dbg_ARREADY_0 : in std_logic;
Dbg_RDATA_0 : in std_logic_vector(31 downto 0);
Dbg_RRESP_0 : in std_logic_vector(1 downto 0);
Dbg_RVALID_0 : in std_logic;
Dbg_RREADY_0 : out std_logic;
Dbg_Disable_1 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_AWADDR_1 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_1 : out std_logic;
Dbg_AWREADY_1 : in std_logic;
Dbg_WDATA_1 : out std_logic_vector(31 downto 0);
Dbg_WVALID_1 : out std_logic;
Dbg_WREADY_1 : in std_logic;
Dbg_BRESP_1 : in std_logic_vector(1 downto 0);
Dbg_BVALID_1 : in std_logic;
Dbg_BREADY_1 : out std_logic;
Dbg_ARADDR_1 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_1 : out std_logic;
Dbg_ARREADY_1 : in std_logic;
Dbg_RDATA_1 : in std_logic_vector(31 downto 0);
Dbg_RRESP_1 : in std_logic_vector(1 downto 0);
Dbg_RVALID_1 : in std_logic;
Dbg_RREADY_1 : out std_logic;
Dbg_Disable_2 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_AWADDR_2 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_2 : out std_logic;
Dbg_AWREADY_2 : in std_logic;
Dbg_WDATA_2 : out std_logic_vector(31 downto 0);
Dbg_WVALID_2 : out std_logic;
Dbg_WREADY_2 : in std_logic;
Dbg_BRESP_2 : in std_logic_vector(1 downto 0);
Dbg_BVALID_2 : in std_logic;
Dbg_BREADY_2 : out std_logic;
Dbg_ARADDR_2 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_2 : out std_logic;
Dbg_ARREADY_2 : in std_logic;
Dbg_RDATA_2 : in std_logic_vector(31 downto 0);
Dbg_RRESP_2 : in std_logic_vector(1 downto 0);
Dbg_RVALID_2 : in std_logic;
Dbg_RREADY_2 : out std_logic;
Dbg_Disable_3 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_AWADDR_3 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_3 : out std_logic;
Dbg_AWREADY_3 : in std_logic;
Dbg_WDATA_3 : out std_logic_vector(31 downto 0);
Dbg_WVALID_3 : out std_logic;
Dbg_WREADY_3 : in std_logic;
Dbg_BRESP_3 : in std_logic_vector(1 downto 0);
Dbg_BVALID_3 : in std_logic;
Dbg_BREADY_3 : out std_logic;
Dbg_ARADDR_3 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_3 : out std_logic;
Dbg_ARREADY_3 : in std_logic;
Dbg_RDATA_3 : in std_logic_vector(31 downto 0);
Dbg_RRESP_3 : in std_logic_vector(1 downto 0);
Dbg_RVALID_3 : in std_logic;
Dbg_RREADY_3 : out std_logic;
Dbg_Disable_4 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_AWADDR_4 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_4 : out std_logic;
Dbg_AWREADY_4 : in std_logic;
Dbg_WDATA_4 : out std_logic_vector(31 downto 0);
Dbg_WVALID_4 : out std_logic;
Dbg_WREADY_4 : in std_logic;
Dbg_BRESP_4 : in std_logic_vector(1 downto 0);
Dbg_BVALID_4 : in std_logic;
Dbg_BREADY_4 : out std_logic;
Dbg_ARADDR_4 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_4 : out std_logic;
Dbg_ARREADY_4 : in std_logic;
Dbg_RDATA_4 : in std_logic_vector(31 downto 0);
Dbg_RRESP_4 : in std_logic_vector(1 downto 0);
Dbg_RVALID_4 : in std_logic;
Dbg_RREADY_4 : out std_logic;
Dbg_Disable_5 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_AWADDR_5 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_5 : out std_logic;
Dbg_AWREADY_5 : in std_logic;
Dbg_WDATA_5 : out std_logic_vector(31 downto 0);
Dbg_WVALID_5 : out std_logic;
Dbg_WREADY_5 : in std_logic;
Dbg_BRESP_5 : in std_logic_vector(1 downto 0);
Dbg_BVALID_5 : in std_logic;
Dbg_BREADY_5 : out std_logic;
Dbg_ARADDR_5 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_5 : out std_logic;
Dbg_ARREADY_5 : in std_logic;
Dbg_RDATA_5 : in std_logic_vector(31 downto 0);
Dbg_RRESP_5 : in std_logic_vector(1 downto 0);
Dbg_RVALID_5 : in std_logic;
Dbg_RREADY_5 : out std_logic;
Dbg_Disable_6 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_AWADDR_6 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_6 : out std_logic;
Dbg_AWREADY_6 : in std_logic;
Dbg_WDATA_6 : out std_logic_vector(31 downto 0);
Dbg_WVALID_6 : out std_logic;
Dbg_WREADY_6 : in std_logic;
Dbg_BRESP_6 : in std_logic_vector(1 downto 0);
Dbg_BVALID_6 : in std_logic;
Dbg_BREADY_6 : out std_logic;
Dbg_ARADDR_6 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_6 : out std_logic;
Dbg_ARREADY_6 : in std_logic;
Dbg_RDATA_6 : in std_logic_vector(31 downto 0);
Dbg_RRESP_6 : in std_logic_vector(1 downto 0);
Dbg_RVALID_6 : in std_logic;
Dbg_RREADY_6 : out std_logic;
Dbg_Disable_7 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_AWADDR_7 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_7 : out std_logic;
Dbg_AWREADY_7 : in std_logic;
Dbg_WDATA_7 : out std_logic_vector(31 downto 0);
Dbg_WVALID_7 : out std_logic;
Dbg_WREADY_7 : in std_logic;
Dbg_BRESP_7 : in std_logic_vector(1 downto 0);
Dbg_BVALID_7 : in std_logic;
Dbg_BREADY_7 : out std_logic;
Dbg_ARADDR_7 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_7 : out std_logic;
Dbg_ARREADY_7 : in std_logic;
Dbg_RDATA_7 : in std_logic_vector(31 downto 0);
Dbg_RRESP_7 : in std_logic_vector(1 downto 0);
Dbg_RVALID_7 : in std_logic;
Dbg_RREADY_7 : out std_logic;
Dbg_Disable_8 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_AWADDR_8 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_8 : out std_logic;
Dbg_AWREADY_8 : in std_logic;
Dbg_WDATA_8 : out std_logic_vector(31 downto 0);
Dbg_WVALID_8 : out std_logic;
Dbg_WREADY_8 : in std_logic;
Dbg_BRESP_8 : in std_logic_vector(1 downto 0);
Dbg_BVALID_8 : in std_logic;
Dbg_BREADY_8 : out std_logic;
Dbg_ARADDR_8 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_8 : out std_logic;
Dbg_ARREADY_8 : in std_logic;
Dbg_RDATA_8 : in std_logic_vector(31 downto 0);
Dbg_RRESP_8 : in std_logic_vector(1 downto 0);
Dbg_RVALID_8 : in std_logic;
Dbg_RREADY_8 : out std_logic;
Dbg_Disable_9 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_AWADDR_9 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_9 : out std_logic;
Dbg_AWREADY_9 : in std_logic;
Dbg_WDATA_9 : out std_logic_vector(31 downto 0);
Dbg_WVALID_9 : out std_logic;
Dbg_WREADY_9 : in std_logic;
Dbg_BRESP_9 : in std_logic_vector(1 downto 0);
Dbg_BVALID_9 : in std_logic;
Dbg_BREADY_9 : out std_logic;
Dbg_ARADDR_9 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_9 : out std_logic;
Dbg_ARREADY_9 : in std_logic;
Dbg_RDATA_9 : in std_logic_vector(31 downto 0);
Dbg_RRESP_9 : in std_logic_vector(1 downto 0);
Dbg_RVALID_9 : in std_logic;
Dbg_RREADY_9 : out std_logic;
Dbg_Disable_10 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_AWADDR_10 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_10 : out std_logic;
Dbg_AWREADY_10 : in std_logic;
Dbg_WDATA_10 : out std_logic_vector(31 downto 0);
Dbg_WVALID_10 : out std_logic;
Dbg_WREADY_10 : in std_logic;
Dbg_BRESP_10 : in std_logic_vector(1 downto 0);
Dbg_BVALID_10 : in std_logic;
Dbg_BREADY_10 : out std_logic;
Dbg_ARADDR_10 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_10 : out std_logic;
Dbg_ARREADY_10 : in std_logic;
Dbg_RDATA_10 : in std_logic_vector(31 downto 0);
Dbg_RRESP_10 : in std_logic_vector(1 downto 0);
Dbg_RVALID_10 : in std_logic;
Dbg_RREADY_10 : out std_logic;
Dbg_Disable_11 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_AWADDR_11 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_11 : out std_logic;
Dbg_AWREADY_11 : in std_logic;
Dbg_WDATA_11 : out std_logic_vector(31 downto 0);
Dbg_WVALID_11 : out std_logic;
Dbg_WREADY_11 : in std_logic;
Dbg_BRESP_11 : in std_logic_vector(1 downto 0);
Dbg_BVALID_11 : in std_logic;
Dbg_BREADY_11 : out std_logic;
Dbg_ARADDR_11 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_11 : out std_logic;
Dbg_ARREADY_11 : in std_logic;
Dbg_RDATA_11 : in std_logic_vector(31 downto 0);
Dbg_RRESP_11 : in std_logic_vector(1 downto 0);
Dbg_RVALID_11 : in std_logic;
Dbg_RREADY_11 : out std_logic;
Dbg_Disable_12 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_AWADDR_12 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_12 : out std_logic;
Dbg_AWREADY_12 : in std_logic;
Dbg_WDATA_12 : out std_logic_vector(31 downto 0);
Dbg_WVALID_12 : out std_logic;
Dbg_WREADY_12 : in std_logic;
Dbg_BRESP_12 : in std_logic_vector(1 downto 0);
Dbg_BVALID_12 : in std_logic;
Dbg_BREADY_12 : out std_logic;
Dbg_ARADDR_12 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_12 : out std_logic;
Dbg_ARREADY_12 : in std_logic;
Dbg_RDATA_12 : in std_logic_vector(31 downto 0);
Dbg_RRESP_12 : in std_logic_vector(1 downto 0);
Dbg_RVALID_12 : in std_logic;
Dbg_RREADY_12 : out std_logic;
Dbg_Disable_13 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_AWADDR_13 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_13 : out std_logic;
Dbg_AWREADY_13 : in std_logic;
Dbg_WDATA_13 : out std_logic_vector(31 downto 0);
Dbg_WVALID_13 : out std_logic;
Dbg_WREADY_13 : in std_logic;
Dbg_BRESP_13 : in std_logic_vector(1 downto 0);
Dbg_BVALID_13 : in std_logic;
Dbg_BREADY_13 : out std_logic;
Dbg_ARADDR_13 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_13 : out std_logic;
Dbg_ARREADY_13 : in std_logic;
Dbg_RDATA_13 : in std_logic_vector(31 downto 0);
Dbg_RRESP_13 : in std_logic_vector(1 downto 0);
Dbg_RVALID_13 : in std_logic;
Dbg_RREADY_13 : out std_logic;
Dbg_Disable_14 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_AWADDR_14 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_14 : out std_logic;
Dbg_AWREADY_14 : in std_logic;
Dbg_WDATA_14 : out std_logic_vector(31 downto 0);
Dbg_WVALID_14 : out std_logic;
Dbg_WREADY_14 : in std_logic;
Dbg_BRESP_14 : in std_logic_vector(1 downto 0);
Dbg_BVALID_14 : in std_logic;
Dbg_BREADY_14 : out std_logic;
Dbg_ARADDR_14 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_14 : out std_logic;
Dbg_ARREADY_14 : in std_logic;
Dbg_RDATA_14 : in std_logic_vector(31 downto 0);
Dbg_RRESP_14 : in std_logic_vector(1 downto 0);
Dbg_RVALID_14 : in std_logic;
Dbg_RREADY_14 : out std_logic;
Dbg_Disable_15 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_AWADDR_15 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_15 : out std_logic;
Dbg_AWREADY_15 : in std_logic;
Dbg_WDATA_15 : out std_logic_vector(31 downto 0);
Dbg_WVALID_15 : out std_logic;
Dbg_WREADY_15 : in std_logic;
Dbg_BRESP_15 : in std_logic_vector(1 downto 0);
Dbg_BVALID_15 : in std_logic;
Dbg_BREADY_15 : out std_logic;
Dbg_ARADDR_15 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_15 : out std_logic;
Dbg_ARREADY_15 : in std_logic;
Dbg_RDATA_15 : in std_logic_vector(31 downto 0);
Dbg_RRESP_15 : in std_logic_vector(1 downto 0);
Dbg_RVALID_15 : in std_logic;
Dbg_RREADY_15 : out std_logic;
Dbg_Disable_16 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_AWADDR_16 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_16 : out std_logic;
Dbg_AWREADY_16 : in std_logic;
Dbg_WDATA_16 : out std_logic_vector(31 downto 0);
Dbg_WVALID_16 : out std_logic;
Dbg_WREADY_16 : in std_logic;
Dbg_BRESP_16 : in std_logic_vector(1 downto 0);
Dbg_BVALID_16 : in std_logic;
Dbg_BREADY_16 : out std_logic;
Dbg_ARADDR_16 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_16 : out std_logic;
Dbg_ARREADY_16 : in std_logic;
Dbg_RDATA_16 : in std_logic_vector(31 downto 0);
Dbg_RRESP_16 : in std_logic_vector(1 downto 0);
Dbg_RVALID_16 : in std_logic;
Dbg_RREADY_16 : out std_logic;
Dbg_Disable_17 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_AWADDR_17 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_17 : out std_logic;
Dbg_AWREADY_17 : in std_logic;
Dbg_WDATA_17 : out std_logic_vector(31 downto 0);
Dbg_WVALID_17 : out std_logic;
Dbg_WREADY_17 : in std_logic;
Dbg_BRESP_17 : in std_logic_vector(1 downto 0);
Dbg_BVALID_17 : in std_logic;
Dbg_BREADY_17 : out std_logic;
Dbg_ARADDR_17 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_17 : out std_logic;
Dbg_ARREADY_17 : in std_logic;
Dbg_RDATA_17 : in std_logic_vector(31 downto 0);
Dbg_RRESP_17 : in std_logic_vector(1 downto 0);
Dbg_RVALID_17 : in std_logic;
Dbg_RREADY_17 : out std_logic;
Dbg_Disable_18 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_AWADDR_18 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_18 : out std_logic;
Dbg_AWREADY_18 : in std_logic;
Dbg_WDATA_18 : out std_logic_vector(31 downto 0);
Dbg_WVALID_18 : out std_logic;
Dbg_WREADY_18 : in std_logic;
Dbg_BRESP_18 : in std_logic_vector(1 downto 0);
Dbg_BVALID_18 : in std_logic;
Dbg_BREADY_18 : out std_logic;
Dbg_ARADDR_18 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_18 : out std_logic;
Dbg_ARREADY_18 : in std_logic;
Dbg_RDATA_18 : in std_logic_vector(31 downto 0);
Dbg_RRESP_18 : in std_logic_vector(1 downto 0);
Dbg_RVALID_18 : in std_logic;
Dbg_RREADY_18 : out std_logic;
Dbg_Disable_19 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_AWADDR_19 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_19 : out std_logic;
Dbg_AWREADY_19 : in std_logic;
Dbg_WDATA_19 : out std_logic_vector(31 downto 0);
Dbg_WVALID_19 : out std_logic;
Dbg_WREADY_19 : in std_logic;
Dbg_BRESP_19 : in std_logic_vector(1 downto 0);
Dbg_BVALID_19 : in std_logic;
Dbg_BREADY_19 : out std_logic;
Dbg_ARADDR_19 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_19 : out std_logic;
Dbg_ARREADY_19 : in std_logic;
Dbg_RDATA_19 : in std_logic_vector(31 downto 0);
Dbg_RRESP_19 : in std_logic_vector(1 downto 0);
Dbg_RVALID_19 : in std_logic;
Dbg_RREADY_19 : out std_logic;
Dbg_Disable_20 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_AWADDR_20 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_20 : out std_logic;
Dbg_AWREADY_20 : in std_logic;
Dbg_WDATA_20 : out std_logic_vector(31 downto 0);
Dbg_WVALID_20 : out std_logic;
Dbg_WREADY_20 : in std_logic;
Dbg_BRESP_20 : in std_logic_vector(1 downto 0);
Dbg_BVALID_20 : in std_logic;
Dbg_BREADY_20 : out std_logic;
Dbg_ARADDR_20 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_20 : out std_logic;
Dbg_ARREADY_20 : in std_logic;
Dbg_RDATA_20 : in std_logic_vector(31 downto 0);
Dbg_RRESP_20 : in std_logic_vector(1 downto 0);
Dbg_RVALID_20 : in std_logic;
Dbg_RREADY_20 : out std_logic;
Dbg_Disable_21 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_AWADDR_21 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_21 : out std_logic;
Dbg_AWREADY_21 : in std_logic;
Dbg_WDATA_21 : out std_logic_vector(31 downto 0);
Dbg_WVALID_21 : out std_logic;
Dbg_WREADY_21 : in std_logic;
Dbg_BRESP_21 : in std_logic_vector(1 downto 0);
Dbg_BVALID_21 : in std_logic;
Dbg_BREADY_21 : out std_logic;
Dbg_ARADDR_21 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_21 : out std_logic;
Dbg_ARREADY_21 : in std_logic;
Dbg_RDATA_21 : in std_logic_vector(31 downto 0);
Dbg_RRESP_21 : in std_logic_vector(1 downto 0);
Dbg_RVALID_21 : in std_logic;
Dbg_RREADY_21 : out std_logic;
Dbg_Disable_22 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_AWADDR_22 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_22 : out std_logic;
Dbg_AWREADY_22 : in std_logic;
Dbg_WDATA_22 : out std_logic_vector(31 downto 0);
Dbg_WVALID_22 : out std_logic;
Dbg_WREADY_22 : in std_logic;
Dbg_BRESP_22 : in std_logic_vector(1 downto 0);
Dbg_BVALID_22 : in std_logic;
Dbg_BREADY_22 : out std_logic;
Dbg_ARADDR_22 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_22 : out std_logic;
Dbg_ARREADY_22 : in std_logic;
Dbg_RDATA_22 : in std_logic_vector(31 downto 0);
Dbg_RRESP_22 : in std_logic_vector(1 downto 0);
Dbg_RVALID_22 : in std_logic;
Dbg_RREADY_22 : out std_logic;
Dbg_Disable_23 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_AWADDR_23 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_23 : out std_logic;
Dbg_AWREADY_23 : in std_logic;
Dbg_WDATA_23 : out std_logic_vector(31 downto 0);
Dbg_WVALID_23 : out std_logic;
Dbg_WREADY_23 : in std_logic;
Dbg_BRESP_23 : in std_logic_vector(1 downto 0);
Dbg_BVALID_23 : in std_logic;
Dbg_BREADY_23 : out std_logic;
Dbg_ARADDR_23 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_23 : out std_logic;
Dbg_ARREADY_23 : in std_logic;
Dbg_RDATA_23 : in std_logic_vector(31 downto 0);
Dbg_RRESP_23 : in std_logic_vector(1 downto 0);
Dbg_RVALID_23 : in std_logic;
Dbg_RREADY_23 : out std_logic;
Dbg_Disable_24 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_AWADDR_24 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_24 : out std_logic;
Dbg_AWREADY_24 : in std_logic;
Dbg_WDATA_24 : out std_logic_vector(31 downto 0);
Dbg_WVALID_24 : out std_logic;
Dbg_WREADY_24 : in std_logic;
Dbg_BRESP_24 : in std_logic_vector(1 downto 0);
Dbg_BVALID_24 : in std_logic;
Dbg_BREADY_24 : out std_logic;
Dbg_ARADDR_24 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_24 : out std_logic;
Dbg_ARREADY_24 : in std_logic;
Dbg_RDATA_24 : in std_logic_vector(31 downto 0);
Dbg_RRESP_24 : in std_logic_vector(1 downto 0);
Dbg_RVALID_24 : in std_logic;
Dbg_RREADY_24 : out std_logic;
Dbg_Disable_25 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_AWADDR_25 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_25 : out std_logic;
Dbg_AWREADY_25 : in std_logic;
Dbg_WDATA_25 : out std_logic_vector(31 downto 0);
Dbg_WVALID_25 : out std_logic;
Dbg_WREADY_25 : in std_logic;
Dbg_BRESP_25 : in std_logic_vector(1 downto 0);
Dbg_BVALID_25 : in std_logic;
Dbg_BREADY_25 : out std_logic;
Dbg_ARADDR_25 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_25 : out std_logic;
Dbg_ARREADY_25 : in std_logic;
Dbg_RDATA_25 : in std_logic_vector(31 downto 0);
Dbg_RRESP_25 : in std_logic_vector(1 downto 0);
Dbg_RVALID_25 : in std_logic;
Dbg_RREADY_25 : out std_logic;
Dbg_Disable_26 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_AWADDR_26 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_26 : out std_logic;
Dbg_AWREADY_26 : in std_logic;
Dbg_WDATA_26 : out std_logic_vector(31 downto 0);
Dbg_WVALID_26 : out std_logic;
Dbg_WREADY_26 : in std_logic;
Dbg_BRESP_26 : in std_logic_vector(1 downto 0);
Dbg_BVALID_26 : in std_logic;
Dbg_BREADY_26 : out std_logic;
Dbg_ARADDR_26 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_26 : out std_logic;
Dbg_ARREADY_26 : in std_logic;
Dbg_RDATA_26 : in std_logic_vector(31 downto 0);
Dbg_RRESP_26 : in std_logic_vector(1 downto 0);
Dbg_RVALID_26 : in std_logic;
Dbg_RREADY_26 : out std_logic;
Dbg_Disable_27 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_AWADDR_27 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_27 : out std_logic;
Dbg_AWREADY_27 : in std_logic;
Dbg_WDATA_27 : out std_logic_vector(31 downto 0);
Dbg_WVALID_27 : out std_logic;
Dbg_WREADY_27 : in std_logic;
Dbg_BRESP_27 : in std_logic_vector(1 downto 0);
Dbg_BVALID_27 : in std_logic;
Dbg_BREADY_27 : out std_logic;
Dbg_ARADDR_27 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_27 : out std_logic;
Dbg_ARREADY_27 : in std_logic;
Dbg_RDATA_27 : in std_logic_vector(31 downto 0);
Dbg_RRESP_27 : in std_logic_vector(1 downto 0);
Dbg_RVALID_27 : in std_logic;
Dbg_RREADY_27 : out std_logic;
Dbg_Disable_28 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_AWADDR_28 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_28 : out std_logic;
Dbg_AWREADY_28 : in std_logic;
Dbg_WDATA_28 : out std_logic_vector(31 downto 0);
Dbg_WVALID_28 : out std_logic;
Dbg_WREADY_28 : in std_logic;
Dbg_BRESP_28 : in std_logic_vector(1 downto 0);
Dbg_BVALID_28 : in std_logic;
Dbg_BREADY_28 : out std_logic;
Dbg_ARADDR_28 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_28 : out std_logic;
Dbg_ARREADY_28 : in std_logic;
Dbg_RDATA_28 : in std_logic_vector(31 downto 0);
Dbg_RRESP_28 : in std_logic_vector(1 downto 0);
Dbg_RVALID_28 : in std_logic;
Dbg_RREADY_28 : out std_logic;
Dbg_Disable_29 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_AWADDR_29 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_29 : out std_logic;
Dbg_AWREADY_29 : in std_logic;
Dbg_WDATA_29 : out std_logic_vector(31 downto 0);
Dbg_WVALID_29 : out std_logic;
Dbg_WREADY_29 : in std_logic;
Dbg_BRESP_29 : in std_logic_vector(1 downto 0);
Dbg_BVALID_29 : in std_logic;
Dbg_BREADY_29 : out std_logic;
Dbg_ARADDR_29 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_29 : out std_logic;
Dbg_ARREADY_29 : in std_logic;
Dbg_RDATA_29 : in std_logic_vector(31 downto 0);
Dbg_RRESP_29 : in std_logic_vector(1 downto 0);
Dbg_RVALID_29 : in std_logic;
Dbg_RREADY_29 : out std_logic;
Dbg_Disable_30 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_AWADDR_30 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_30 : out std_logic;
Dbg_AWREADY_30 : in std_logic;
Dbg_WDATA_30 : out std_logic_vector(31 downto 0);
Dbg_WVALID_30 : out std_logic;
Dbg_WREADY_30 : in std_logic;
Dbg_BRESP_30 : in std_logic_vector(1 downto 0);
Dbg_BVALID_30 : in std_logic;
Dbg_BREADY_30 : out std_logic;
Dbg_ARADDR_30 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_30 : out std_logic;
Dbg_ARREADY_30 : in std_logic;
Dbg_RDATA_30 : in std_logic_vector(31 downto 0);
Dbg_RRESP_30 : in std_logic_vector(1 downto 0);
Dbg_RVALID_30 : in std_logic;
Dbg_RREADY_30 : out std_logic;
Dbg_Disable_31 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
Dbg_AWADDR_31 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_31 : out std_logic;
Dbg_AWREADY_31 : in std_logic;
Dbg_WDATA_31 : out std_logic_vector(31 downto 0);
Dbg_WVALID_31 : out std_logic;
Dbg_WREADY_31 : in std_logic;
Dbg_BRESP_31 : in std_logic_vector(1 downto 0);
Dbg_BVALID_31 : in std_logic;
Dbg_BREADY_31 : out std_logic;
Dbg_ARADDR_31 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_31 : out std_logic;
Dbg_ARREADY_31 : in std_logic;
Dbg_RDATA_31 : in std_logic_vector(31 downto 0);
Dbg_RRESP_31 : in std_logic_vector(1 downto 0);
Dbg_RVALID_31 : in std_logic;
Dbg_RREADY_31 : out std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG Signals
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM_Core;
library IEEE;
use IEEE.numeric_std.all;
library mdm_v3_2_8;
use mdm_v3_2_8.all;
architecture IMP of MDM_CORE is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
constant C_DRCK_FREQ_HZ : integer := 30000000;
constant C_CLOCK_BITS : integer := log2(C_S_AXI_ACLK_FREQ_HZ / C_DRCK_FREQ_HZ);
constant MB_WRITE_INSTR : std_logic_vector(0 to 7) := "00000100";
constant MB_READ_DATA : std_logic_vector(0 to 7) := "00000110";
component JTAG_CONTROL
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_USE_BSCAN : integer;
C_MB_DBG_PORTS : integer;
C_USE_CONFIG_RESET : integer;
C_DEBUG_INTERFACE : integer;
C_DBG_REG_ACCESS : integer;
C_DBG_MEM_ACCESS : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer;
C_TRACE_OUTPUT : integer;
C_EN_WIDTH : integer := 1
);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
Clk : in std_logic;
Rst : in std_logic;
Clear_Ext_BRK : in std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
Debug_Rst : out std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_UART_WIDTH-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_UART_WIDTH-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic;
-- Debug Register Access signals
DbgReg_Access_Lock : in std_logic;
DbgReg_Force_Lock : in std_logic;
DbgReg_Unlocked : in std_logic;
JTAG_Access_Lock : out std_logic;
JTAG_Force_Lock : out std_logic;
JTAG_AXI_Overrun : in std_logic;
JTAG_Clear_Overrun : out std_logic;
AXI_Transaction : in std_logic;
AXI_Instr_Overrun : in std_logic;
AXI_Data_Overrun : in std_logic;
AXI_Completion_On : out std_logic;
AXI_Block : out std_logic;
-- MDM signals
TDI : in std_logic;
RESET : in std_logic;
UPDATE : in std_logic;
SHIFT : in std_logic;
CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
TDO : out std_logic;
-- Bus Master signals
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- MicroBlaze Debug Signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
Dbg_Clk : out std_logic;
Dbg_TDI : out std_logic;
Dbg_TDO : in std_logic;
Dbg_Reg_En : out std_logic_vector(0 to 7);
Dbg_Capture : out std_logic;
Dbg_Shift : out std_logic;
Dbg_Update : out std_logic;
Dbg_data_cmd : out std_logic;
Dbg_command : out std_logic_vector(0 to 7);
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
Trace_Clk : in std_logic;
Trace_Reset : in std_logic;
Trace_Test_Pattern : out std_logic_vector(0 to 3);
Trace_Test_Start : out std_logic;
Trace_Test_Stop : out std_logic;
Trace_Test_Timed : out std_logic;
Trace_Delay : out std_logic_vector(0 to 7);
Trace_Stopped : out std_logic
);
end component JTAG_CONTROL;
component Arbiter is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
Size : natural;
Size_Log2 : natural);
port (
Clk : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
Requests : in std_logic_vector(Size-1 downto 0);
Granted : out std_logic_vector(Size-1 downto 0);
Valid_Sel : out std_logic;
Selected : out std_logic_vector(Size_Log2-1 downto 0)
);
end component Arbiter;
component SRL_FIFO
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_DATA_BITS : natural;
C_DEPTH : natural
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end component SRL_FIFO;
component MB_FDRE
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit := '0'
);
port (
Q : out std_logic := TO_X01(INIT);
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component MB_PLLE2_BASE
generic (
C_TARGET : TARGET_FAMILY_TYPE;
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT : integer := 5;
CLKFBOUT_PHASE : real := 0.000;
CLKIN1_PERIOD : real := 0.000;
CLKOUT0_DIVIDE : integer := 1;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.010;
STARTUP_WAIT : string := "FALSE"
);
port (
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
LOCKED : out std_logic;
CLKFBIN : in std_logic;
CLKIN1 : in std_logic;
PWRDWN : in std_logic;
RST : in std_logic
);
end component;
component MB_BUFG
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I : in std_logic
);
end component;
signal config_reset_i : std_logic;
signal clear_Ext_BRK : std_logic;
signal enable_interrupts : std_logic;
signal read_RX_FIFO : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal tx_Data : std_logic_vector(0 to C_UART_WIDTH-1);
signal write_TX_FIFO : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal xfer_Ack : std_logic;
signal mdm_Dbus_i : std_logic_vector(0 to 31); -- Check!
signal mdm_CS : std_logic; -- Valid address in a address phase
signal mdm_CS_1 : std_logic; -- Active as long as mdm_CS is active
signal mdm_CS_2 : std_logic;
signal mdm_CS_3 : std_logic;
signal valid_access : std_logic; -- Active during the address phase (2 clock cycles)
signal valid_access_1 : std_logic; -- Will be a 1 clock delayed valid_access signal
signal valid_access_2 : std_logic; -- Active only 1 clock cycle
signal reading : std_logic; -- Valid reading access
signal valid_access_2_reading : std_logic; -- signal to drive out data bus on a read access
signal sl_rdDAck_i : std_logic;
signal sl_wrDAck_i : std_logic;
signal TDI : std_logic;
signal RESET : std_logic;
signal SHIFT : std_logic;
signal CAPTURE : std_logic;
signal TDO : std_logic;
signal mb_debug_enabled_i : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal jtag_disable : std_logic := '1';
signal disable : std_logic;
signal Debug_SYS_Rst_i : std_logic;
signal Debug_Rst_i : std_logic;
-- Interface signals
signal Dbg_Disable : std_logic_vector(0 to 31);
signal Dbg_Rst_I : std_logic_vector(0 to 31);
signal Dbg_TrClk : std_logic;
signal Dbg_TrReady : std_logic_vector(0 to 31);
-- Serial interface signals
signal Dbg_Clk : std_logic;
signal Dbg_TDI : std_logic;
signal Dbg_TDO : std_logic;
signal Dbg_Reg_En : std_logic_vector(0 to 7);
signal Dbg_Capture : std_logic;
signal Dbg_Shift : std_logic;
signal Dbg_Update : std_logic;
signal Dbg_data_cmd : std_logic;
signal Dbg_command : std_logic_vector(0 to 7);
subtype Reg_En_TYPE is std_logic_vector(0 to 7);
type Reg_EN_ARRAY is array(0 to 31) of Reg_En_TYPE;
signal Dbg_TDO_I : std_logic_vector(0 to 31);
signal Dbg_Reg_En_I : Reg_EN_ARRAY;
-- Parallel interface signals
signal Dbg_AWADDR : std_logic_vector(14 downto 2);
signal Dbg_AWVALID : std_logic_vector(0 to 31);
signal Dbg_WVALID : std_logic_vector(0 to 31);
signal Dbg_WDATA : std_logic_vector(31 downto 0);
signal Dbg_BREADY : std_logic_vector(0 to 31);
signal Dbg_ARADDR : std_logic_vector(14 downto 2);
signal Dbg_ARVALID : std_logic_vector(0 to 31);
signal Dbg_RREADY : std_logic_vector(0 to 31);
subtype Resp_TYPE is std_logic_vector(1 downto 0);
type Resp_ARRAY is array(0 to 31) of Resp_TYPE;
subtype RData_TYPE is std_logic_vector(31 downto 0);
type RData_ARRAY is array(0 to 31) of RData_TYPE;
signal Dbg_AWREADY_I : std_logic_vector(0 to 31);
signal Dbg_WREADY_I : std_logic_vector(0 to 31);
signal Dbg_BRESP_I : Resp_ARRAY;
signal Dbg_BVALID_I : std_logic_vector(0 to 31);
signal Dbg_ARREADY_I : std_logic_vector(0 to 31);
signal Dbg_RDATA_I : RData_ARRAY;
signal Dbg_RRESP_I : Resp_ARRAY;
signal Dbg_RVALID_I : std_logic_vector(0 to 31);
signal Dbg_AWVALID_I : std_logic;
signal Dbg_AWREADY : std_logic;
signal Dbg_WVALID_I : std_logic;
signal Dbg_WREADY : std_logic;
signal Dbg_ARVALID_I : std_logic;
signal Dbg_ARREADY : std_logic;
signal Dbg_BRESP : std_logic;
signal Dbg_BVALID : std_logic;
signal Dbg_RDATA : std_logic_vector(31 downto 0);
signal Dbg_RRESP : std_logic;
signal Dbg_RVALID : std_logic;
-- Other signals
signal Sl_rdDBus_int : std_logic_vector(0 to 31);
signal bus_rst : std_logic;
signal uart_ip2bus_rdack : std_logic;
signal uart_ip2bus_wrack : std_logic;
signal uart_ip2bus_error : std_logic;
signal uart_ip2bus_data : std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
signal dbgreg_ip2bus_rdack : std_logic;
signal dbgreg_ip2bus_wrack : std_logic;
signal dbgreg_ip2bus_error : std_logic;
signal dbgreg_ip2bus_data : std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
signal dbgreg_access_lock : std_logic;
signal dbgreg_force_lock : std_logic;
signal dbgreg_unlocked : std_logic;
signal jtag_access_lock : std_logic;
signal jtag_force_lock : std_logic;
signal jtag_axi_overrun : std_logic;
signal jtag_clear_overrun : std_logic;
signal axi_transaction : std_logic;
signal axi_instr_overrun : std_logic;
signal axi_data_overrun : std_logic;
signal axi_completion_on : std_logic;
signal axi_block : std_logic;
-- Full frame synchronization packet
constant C_FF_SYNC_PACKET : std_logic_vector(31 downto 0) := (31 => '0', others => '1');
signal trace_clk_i : std_logic;
signal trace_reset : std_logic;
signal trace_word : std_logic_vector(31 downto 0);
signal trace_index : std_logic_vector(4 downto 0);
signal trace_trdata : std_logic_vector(35 downto 0);
signal trace_valid : std_logic;
signal trace_last_word : std_logic;
signal trace_started : std_logic;
signal trace_ready : std_logic;
signal trace_trready : std_logic;
signal trace_count_last : std_logic;
signal trace_test_pattern : std_logic_vector(0 to 3);
signal trace_test_start : std_logic;
signal trace_test_stop : std_logic;
signal trace_test_timed : std_logic;
signal trace_delay : std_logic_vector(0 to 7);
signal trace_stopped : std_logic;
signal Old_MDM_DRCK : std_logic;
signal Old_MDM_TDI : std_logic;
signal Old_MDM_TDO : std_logic;
signal Old_MDM_SEL : std_logic;
signal Old_MDM_SEL_Mux : std_logic;
signal Old_MDM_SHIFT : std_logic;
signal Old_MDM_UPDATE : std_logic;
signal Old_MDM_RESET : std_logic;
signal Old_MDM_CAPTURE : std_logic;
signal JTAG_Dec_Sel : std_logic_vector(15 downto 0);
begin -- architecture IMP
config_reset_i <= Config_Reset when C_USE_CONFIG_RESET /= 0 else '0';
Use_BSCAN : if (C_USE_BSCAN /= 3) generate
-----------------------------------------------------------------------------
-- Register mapping
-----------------------------------------------------------------------------
-- Magic string "01000010" + "00000000" + No of Jtag peripheral units "0010"
-- + MDM Version no "00000110"
--
-- MDM Versions table:
-- 0,1,2,3: Not used
-- 4: opb_mdm v3
-- 5: mdm v1
-- 6: mdm v2
constant New_MDM_Config_Word : std_logic_vector(31 downto 0) :=
"01000010000000000000001000000110";
signal config_scan_reset : std_logic;
signal sel_n_reset : std_logic;
signal shift_n_reset : std_logic;
signal PORT_Selector : std_logic_vector(3 downto 0) := (others => '0');
signal PORT_Selector_1 : std_logic_vector(3 downto 0) := (others => '0');
signal TDI_Shifter : std_logic_vector(3 downto 0) := (others => '0');
signal Config_Reg : std_logic_vector(31 downto 0) := New_MDM_Config_Word;
signal MDM_SEL : std_logic;
begin
config_scan_reset <= config_reset_i when Scan_Reset_Sel = '0' else
Scan_Reset;
sel_n_reset <= not SEL or config_reset_i when Scan_Reset_Sel = '0' else
Scan_Reset;
shift_n_reset <= not SHIFT or config_reset_i when Scan_Reset_Sel = '0' else
Scan_Reset;
-----------------------------------------------------------------------------
-- TDI Shift Register
-----------------------------------------------------------------------------
-- Shifts data in when PORT 0 is selected. PORT 0 does not actually
-- exist externaly, but gets selected after asserting the SELECT signal.
-- The first value shifted in after SELECT goes high will select the new
-- PORT.
JTAG_Mux_Shifting : process (DRCK, sel_n_reset)
begin
if sel_n_reset = '1' then
TDI_Shifter <= (others => '0');
elsif DRCK'event and DRCK = '1' then
if MDM_SEL = '1' and SHIFT = '1' then
TDI_Shifter <= TDI & TDI_Shifter(3 downto 1);
end if;
end if;
end process JTAG_Mux_Shifting;
-----------------------------------------------------------------------------
-- PORT Selector Register
-----------------------------------------------------------------------------
-- Captures the shifted data when PORT 0 is selected. The data is captured at
-- the end of the BSCAN transaction (i.e. when the update signal goes low) to
-- prevent any other BSCAN signals to assert incorrectly.
-- Reference : XAPP 139
PORT_Selector_Updating : process (UPDATE, sel_n_reset)
begin
if sel_n_reset = '1' then
PORT_Selector <= (others => '0');
elsif Update'event and Update = '0' then
PORT_Selector <= Port_Selector_1;
end if;
end process PORT_Selector_Updating;
PORT_Selector_Updating_1 : process (UPDATE, sel_n_reset)
begin
if sel_n_reset = '1' then
PORT_Selector_1 <= (others => '0');
elsif Update'event and Update = '1' then
if MDM_SEL = '1' then
PORT_Selector_1 <= TDI_Shifter;
end if;
end if;
end process PORT_Selector_Updating_1;
-----------------------------------------------------------------------------
-- Configuration register
-----------------------------------------------------------------------------
-- TODO Can be replaced by SRLs
Config_Shifting : process (DRCK, shift_n_reset)
begin
if shift_n_reset = '1' then
Config_Reg <= New_MDM_Config_Word;
elsif DRCK'event and DRCK = '1' then -- rising clock edge
Config_Reg <= '0' & Config_Reg(31 downto 1);
end if;
end process Config_Shifting;
-----------------------------------------------------------------------------
-- Muxing and demuxing of JTAG Bscan User 1/2/3/4 signals
--
-- This block enables the older MDM/JTAG to co-exist with the newer
-- JTAG multiplexer block
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- TDO Mux
-----------------------------------------------------------------------------
with PORT_Selector select
TDO <=
Config_Reg(0) when "0000",
Old_MDM_TDO when "0001",
Ext_JTAG_TDO when "0010",
'1' when others;
-----------------------------------------------------------------------------
-- SELECT Decoder
-----------------------------------------------------------------------------
MDM_SEL <= SEL when PORT_Selector = "0000" else '0';
Old_MDM_SEL_Mux <= SEL when PORT_Selector = "0001" else '0';
Ext_JTAG_SEL <= SEL when PORT_Selector = "0010" else '0';
-----------------------------------------------------------------------------
-- Disable handling
-----------------------------------------------------------------------------
Disable_Updating : process (UPDATE, config_scan_reset)
begin
if config_scan_reset = '1' then
jtag_disable <= '1';
elsif Update'event and Update = '1' then
jtag_disable <= '0';
end if;
end process Disable_Updating;
end generate Use_BSCAN;
No_BSCAN : if (C_USE_BSCAN = 3) generate
begin
TDO <= '1';
Old_MDM_SEL_Mux <= '0';
Ext_JTAG_SEL <= '0';
jtag_disable <= '1';
end generate No_BSCAN;
-----------------------------------------------------------------------------
-- Old MDM signals
-----------------------------------------------------------------------------
Old_MDM_DRCK <= DRCK;
Old_MDM_TDI <= TDI;
Old_MDM_CAPTURE <= CAPTURE;
Old_MDM_SHIFT <= SHIFT;
Old_MDM_UPDATE <= UPDATE;
Old_MDM_RESET <= RESET;
-----------------------------------------------------------------------------
-- External JTAG signals
-----------------------------------------------------------------------------
Ext_JTAG_DRCK <= DRCK;
Ext_JTAG_TDI <= TDI;
Ext_JTAG_CAPTURE <= CAPTURE;
Ext_JTAG_SHIFT <= SHIFT;
Ext_JTAG_UPDATE <= UPDATE;
Ext_JTAG_RESET <= RESET;
-----------------------------------------------------------------------------
-- AXI bus interface
-----------------------------------------------------------------------------
ip2bus_rdack <= uart_ip2bus_rdack or dbgreg_ip2bus_rdack;
ip2bus_wrack <= uart_ip2bus_wrack or dbgreg_ip2bus_wrack;
ip2bus_error <= uart_ip2bus_error or dbgreg_ip2bus_error;
ip2bus_data <= uart_ip2bus_data or dbgreg_ip2bus_data;
bus_rst <= not bus2ip_resetn;
-----------------------------------------------------------------------------
-- UART
-----------------------------------------------------------------------------
Use_Uart : if (C_USE_UART = 1) generate
-- Read Only
signal status_Reg : std_logic_vector(7 downto 0);
-- bit 4 enable_interrupts
-- bit 3 tx_Buffer_Full
-- bit 2 tx_Buffer_Empty
-- bit 1 rx_Buffer_Full
-- bit 0 rx_Data_Present
-- Write Only
-- Control Register
-- bit 7-5 Dont'Care
-- bit 4 enable_interrupts
-- bit 3 Dont'Care
-- bit 2 Clear Ext BRK signal
-- bit 1 Reset_RX_FIFO
-- bit 0 Reset_TX_FIFO
signal tx_Buffer_Empty_Pre : std_logic;
begin
---------------------------------------------------------------------------
-- Acknowledgement and error signals
---------------------------------------------------------------------------
uart_ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
uart_ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
uart_ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
---------------------------------------------------------------------------
-- Status register
---------------------------------------------------------------------------
status_Reg(0) <= rx_Data_Present;
status_Reg(1) <= rx_Buffer_Full;
status_Reg(2) <= tx_Buffer_Empty;
status_Reg(3) <= tx_Buffer_Full;
status_Reg(4) <= enable_interrupts;
status_Reg(7 downto 5) <= "000";
---------------------------------------------------------------------------
-- Control Register
---------------------------------------------------------------------------
CTRL_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
reset_RX_FIFO <= '1';
reset_TX_FIFO <= '1';
elsif (bus2ip_wrce(3) = '1') then -- Control Register is reg 3
enable_interrupts <= bus2ip_data(4); -- Bit 4 in control reg
clear_Ext_BRK <= bus2ip_data(2); -- Bit 2 in control reg
reset_RX_FIFO <= bus2ip_data(1); -- Bit 1 in control reg
reset_TX_FIFO <= bus2ip_data(0); -- Bit 0 in control reg
else
clear_Ext_BRK <= '0';
reset_RX_FIFO <= '0';
reset_TX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
---------------------------------------------------------------------------
-- Read bus interface
---------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin
uart_ip2bus_data <= (others => '0');
if (bus2ip_rdce(2) = '1') then -- Status register is reg 2
uart_ip2bus_data(status_reg'length-1 downto 0) <= status_reg;
elsif (bus2ip_rdce(0) = '1') then -- RX FIFO is reg 0
uart_ip2bus_data(C_UART_WIDTH-1 downto 0) <= rx_Data;
end if;
end process READ_MUX;
---------------------------------------------------------------------------
-- Write bus interface
---------------------------------------------------------------------------
tx_Data <= bus2ip_data(C_UART_WIDTH-1 downto 0);
---------------------------------------------------------------------------
-- Read and write pulses to the FIFOs
---------------------------------------------------------------------------
write_TX_FIFO <= bus2ip_wrce(1); -- TX FIFO is reg 1
read_RX_FIFO <= bus2ip_rdce(0); -- RX FIFO is reg 0
-- Sample the tx_Buffer_Empty signal in order to detect a rising edge
TX_Buffer_Empty_FDRE : MB_FDRE
generic map (
C_TARGET => C_TARGET
)
port map (
Q => tx_Buffer_Empty_Pre,
C => bus2ip_clk,
CE => '1',
D => tx_Buffer_Empty,
R => write_TX_FIFO);
---------------------------------------------------------------------------
-- Interrupt handling
---------------------------------------------------------------------------
Interrupt <= enable_interrupts and ( rx_Data_Present or
( tx_Buffer_Empty and
not tx_Buffer_Empty_Pre ) );
end generate Use_UART;
No_UART : if (C_USE_UART = 0) generate
begin
uart_ip2bus_rdack <= '0';
uart_ip2bus_wrack <= '0';
uart_ip2bus_error <= '0';
uart_ip2bus_data <= (others => '0');
Interrupt <= '0';
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
clear_Ext_BRK <= '0';
tx_Data <= (others => '0');
write_TX_FIFO <= '0';
read_RX_FIFO <= '0';
end generate No_UART;
-----------------------------------------------------------------------------
-- Debug Register Access
-----------------------------------------------------------------------------
Use_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 1) generate
type state_type is
(idle, select_dr, capture_dr, shift_dr, exit1, pause, exit2, update_dr, cmd_done, data_done);
signal bit_size : std_logic_vector(8 downto 0);
signal cmd_val : std_logic_vector(7 downto 0);
signal type_lock : std_logic_vector(1 downto 0);
signal use_mdm : std_logic;
signal reg_data : std_logic_vector(31 downto 0);
signal bit_cnt : std_logic_vector(0 to 8);
signal clk_cnt : std_logic_vector(0 to C_CLOCK_BITS / 2);
signal clk_fall : boolean;
signal clk_rise : boolean;
signal shifting : boolean;
signal data_shift : boolean;
signal direction : std_logic;
signal rd_wr_n : boolean;
signal rdack_data : std_logic;
signal selected : std_logic := '0';
signal shift_index : std_logic_vector(0 to 4);
signal state : state_type;
signal unlocked : boolean;
signal wrack_data : std_logic;
signal next_bit : std_logic;
signal next_index : std_logic_vector(0 to 4);
signal reg_data_bit : std_logic;
signal mb_instr : boolean;
signal dbgreg_TDI : std_logic;
signal dbgreg_RESET : std_logic;
signal dbgreg_SHIFT : std_logic;
signal dbgreg_CAPTURE : std_logic;
signal dbgreg_SEL : std_logic;
signal dbgreg_disable : std_logic := '1';
signal wrack_bus : std_logic;
signal rdack_bus : std_logic;
signal error_bus : std_logic;
signal bus_data : std_logic_vector(31 downto 0);
begin
---------------------------------------------------------------------------
-- Acknowledgement and error signals
---------------------------------------------------------------------------
dbgreg_ip2bus_rdack <= bus2ip_rdce(4) or rdack_data or rdack_bus;
dbgreg_ip2bus_wrack <= bus2ip_wrce(4) or bus2ip_wrce(6) or wrack_data or wrack_bus;
dbgreg_ip2bus_error <= error_bus;
---------------------------------------------------------------------------
-- Control register
---------------------------------------------------------------------------
CTRL_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
use_mdm <= '0';
type_lock <= (others => '0');
cmd_val <= (others => '0');
bit_size <= (others => '0');
elsif (bus2ip_wrce(4) = '1') and unlocked then -- Control Register is reg 4
type_lock <= bus2ip_data(19 downto 18);
use_mdm <= bus2ip_data(17);
cmd_val <= bus2ip_data(16 downto 9);
bit_size <= bus2ip_data(8 downto 0);
end if;
end if;
end process CTRL_REG_DFF;
---------------------------------------------------------------------------
-- Data register and TAP state machine
---------------------------------------------------------------------------
DATA_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
reg_data <= (others => '0');
rdack_data <= '0';
wrack_data <= '0';
state <= idle;
shifting <= false;
data_shift <= false;
direction <= '1';
rd_wr_n <= false;
clk_rise <= false;
clk_fall <= false;
clk_cnt <= (others => '0');
bit_cnt <= "000000111";
shift_index <= "00000";
dbgreg_TDI <= '0';
dbgreg_RESET <= '0';
dbgreg_SHIFT <= '0';
dbgreg_CAPTURE <= '0';
dbgreg_SEL <= '0';
DbgReg_DRCK <= '0';
DbgReg_UPDATE <= '0';
selected <= '0';
next_bit <= '0';
else
rdack_data <= '0';
wrack_data <= '0';
if unlocked and dbgreg_access_lock = '1' and not shifting then
if bus2ip_wrce(5) = '1' then
reg_data <= bus2ip_data;
shifting <= true;
rd_wr_n <= false;
end if;
if bus2ip_rdce(5) = '1' then
reg_data <= (others => '0');
shifting <= true;
rd_wr_n <= true;
end if;
end if;
if clk_rise then
case state is
when idle =>
-- Idle - Start when data access occurs
if shifting then
state <= select_dr;
end if;
bit_cnt <= "000000111";
shift_index <= "00000";
selected <= '0';
next_bit <= cmd_val(0);
when select_dr =>
-- TAP state Select DR - Set SEL
state <= capture_dr;
dbgreg_SEL <= '1';
selected <= '1';
when capture_dr =>
-- TAP state Capture DR - Set CAPTURE and pulse DRCK
state <= shift_dr;
dbgreg_CAPTURE <= '1';
DbgReg_DRCK <= '1';
when shift_dr =>
-- TAP state Shift DR - Set SHIFT and pulse DRCK until done or pause
if bit_cnt = (bit_cnt'range => '0') then
state <= exit2; -- Shift done
elsif shift_index = (shift_index'range => direction) then
state <= exit1; -- Acknowledge and pause until next word
if rd_wr_n then
rdack_data <= '1';
else
wrack_data <= '1';
end if;
elsif data_shift then
next_bit <= reg_data(to_integer(unsigned(next_index)));
else
next_bit <= cmd_val(to_integer(unsigned(next_index)));
end if;
if data_shift then
reg_data(to_integer(unsigned(shift_index))) <= Old_MDM_TDO;
end if;
dbgreg_CAPTURE <= '0';
dbgreg_SHIFT <= '1';
DbgReg_DRCK <= '1';
bit_cnt <= std_logic_vector(unsigned(bit_cnt) - 1);
shift_index <= next_index;
when exit1 =>
-- TAP state Exit1 DR - End shift and go to pause
state <= pause;
shifting <= false;
dbgreg_SHIFT <= '0';
DbgReg_DRCK <= '0';
when pause =>
-- TAP state Pause DR - Pause until new data access or abort
if dbgreg_access_lock = '0' then
state <= exit2; -- Abort shift
elsif shifting then
state <= shift_dr; -- Continue with next word
end if;
if direction = '1' then
next_bit <= reg_data(0);
elsif bit_cnt(0 to 3) = "0000" and not mb_instr then
shift_index <= bit_size(shift_index'length - 1 downto 0);
next_bit <= reg_data_bit;
else
next_bit <= reg_data(reg_data'left);
end if;
DbgReg_DRCK <= '0';
when exit2 =>
-- TAP state Exit2 DR - Delay before update
state <= update_dr;
dbgreg_SHIFT <= '0';
DbgReg_DRCK <= '0';
when update_dr =>
-- TAP state Update DR - Pulse UPDATE and acknowledge data access
if data_shift then
state <= data_done;
if rd_wr_n then
rdack_data <= '1';
else
wrack_data <= '1';
end if;
else
state <= cmd_done;
end if;
DbgReg_UPDATE <= '1';
when cmd_done =>
-- Command phase done - Continue with data phase
state <= select_dr;
data_shift <= true;
bit_cnt <= bit_size;
if use_mdm = '1' then
shift_index <= (others => '0');
next_bit <= reg_data(0);
elsif bit_size(bit_size'left downto shift_index'length) = "0000" or mb_instr then
shift_index <= bit_size(shift_index'length - 1 downto 0);
next_bit <= reg_data_bit;
else
shift_index <= (others => '1');
next_bit <= reg_data(reg_data'left);
end if;
direction <= use_mdm;
DbgReg_UPDATE <= '0';
when data_done =>
-- Data phase done - End shifting and go back to idle
state <= idle;
data_shift <= false;
shifting <= false;
direction <= '1';
DbgReg_UPDATE <= '0';
end case;
elsif clk_fall then
DbgReg_DRCK <= '0';
dbgreg_TDI <= next_bit;
end if;
if clk_cnt(clk_cnt'left + 1 to clk_cnt'right) = (clk_cnt'left + 1 to clk_cnt'right => '0') then
clk_rise <= (clk_cnt(clk_cnt'left) = '0');
clk_fall <= (clk_cnt(clk_cnt'left) = '1');
else
clk_rise <= false;
clk_fall <= false;
end if;
clk_cnt <= std_logic_vector(unsigned(clk_cnt) - 1);
end if;
end if;
end process DATA_REG_DFF;
next_index <= std_logic_vector(unsigned(shift_index) + 1) when direction = '1' else
std_logic_vector(unsigned(shift_index) - 1);
reg_data_bit <= reg_data(to_integer(unsigned(bit_size(shift_index'length - 1 downto 0))));
mb_instr <= cmd_val = MB_WRITE_INSTR;
---------------------------------------------------------------------------
-- Lock register
---------------------------------------------------------------------------
LOCK_REG_DFF : process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
unlocked <= false;
elsif (bus2ip_wrce(6) = '1') then -- Lock Register is reg 6
unlocked <= (bus2ip_data(15 downto 0) = X"EBAB") and (not unlocked);
end if;
end if;
end process LOCK_REG_DFF;
---------------------------------------------------------------------------
-- Read bus interface
---------------------------------------------------------------------------
READ_MUX : process (bus2ip_rdce(4), rdack_data, dbgreg_access_lock, reg_data, rdack_bus, bus_data) is
begin
dbgreg_ip2bus_data <= (others => '0');
if (bus2ip_rdce(4) = '1') then -- Status register is reg 4
dbgreg_ip2bus_data(0) <= dbgreg_access_lock;
elsif rdack_data = '1' then -- Data register is reg 5
dbgreg_ip2bus_data <= reg_data;
elsif rdack_bus = '1' and C_DEBUG_INTERFACE = 1 then -- Parallel bus access
dbgreg_ip2bus_data <= bus_data;
end if;
end process READ_MUX;
---------------------------------------------------------------------------
-- Access lock handling
---------------------------------------------------------------------------
Handle_Access_Lock : process (bus2ip_clk) is
variable jtag_access_lock_1 : std_logic;
variable jtag_force_lock_1 : std_logic;
variable jtag_clear_overrun_1 : std_logic;
variable jtag_busy_1 : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of jtag_access_lock_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_force_lock_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_clear_overrun_1 : variable is "TRUE";
attribute ASYNC_REG of jtag_busy_1 : variable is "TRUE";
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
dbgreg_access_lock <= '0';
dbgreg_force_lock <= '0';
dbgreg_unlocked <= '0';
jtag_axi_overrun <= '0';
jtag_access_lock_1 := '0';
jtag_force_lock_1 := '0';
jtag_clear_overrun_1 := '0';
jtag_busy_1 := '0';
else
-- Unlock after last access for type "01"
if state = data_done and type_lock = "01" then
dbgreg_access_lock <= '0';
end if;
-- Write to Debug Access Control Register
if bus2ip_wrce(4) = '1' then
case bus2ip_data(19 downto 18) is
when "00" => -- Release lock to abort atomic sequence
dbgreg_access_lock <= '0';
when "01" | "10" => -- Lock before first access
if dbgreg_access_lock = '0' and jtag_busy_1 = '0' and jtag_access_lock_1 = '0' then
dbgreg_access_lock <= '1';
end if;
when "11" => -- Force access lock
dbgreg_access_lock <= '1';
dbgreg_force_lock <= '1';
-- coverage off
when others =>
null;
-- coverage on
end case;
else
dbgreg_force_lock <= '0';
end if;
jtag_access_lock_1 := JTAG_Access_Lock;
-- JTAG force lock
if jtag_force_lock_1 = '1' then
dbgreg_access_lock <= '0';
dbgreg_unlocked <= '1';
else
dbgreg_unlocked <= '0';
end if;
jtag_force_lock_1 := jtag_force_lock;
-- JTAG overrun detection
if selected = '1' and jtag_busy_1 = '1' then
jtag_axi_overrun <= '1';
elsif jtag_clear_overrun_1 = '1' then
jtag_axi_overrun <= '0';
end if;
jtag_clear_overrun_1 := jtag_clear_overrun;
jtag_busy_1 := jtag_busy;
end if;
end if;
end process;
DbgReg_Select <= selected;
-----------------------------------------------------------------------------
-- Disable handling
-----------------------------------------------------------------------------
Disable_Updating : process (bus2ip_clk, bus2ip_resetn)
begin
if bus2ip_resetn = '0' then
dbgreg_disable <= '1';
elsif bus2ip_clk'event and bus2ip_clk = '1' then
if unlocked then
dbgreg_disable <= '0';
end if;
end if;
end process Disable_Updating;
Old_MDM_SEL <= dbgreg_SEL when selected = '1' else Old_MDM_SEL_Mux;
TDI <= dbgreg_TDI when selected = '1' else JTAG_TDI;
RESET <= dbgreg_RESET when selected = '1' else JTAG_RESET;
SHIFT <= dbgreg_SHIFT when selected = '1' else JTAG_SHIFT;
CAPTURE <= dbgreg_CAPTURE when selected = '1' else JTAG_CAPTURE;
JTAG_TDO <= '0' when selected = '1' else TDO;
disable <= '0' when dbgreg_disable = '0' or jtag_disable = '0' else '1';
Use_Parallel_Access : if (C_DEBUG_INTERFACE = 1) generate
signal dbgreg_AWADDR : std_logic_vector(14 downto 2);
signal dbgreg_WDATA : std_logic_vector(31 downto 0);
signal dbgreg_ARADDR : std_logic_vector(14 downto 2);
signal dbgreg_AWVALID : std_logic;
signal dbgreg_WVALID : std_logic;
signal dbgreg_ARVALID : std_logic;
signal dbgreg_access : std_logic;
signal dbgreg_block : std_logic;
signal dbgreg_mb_instr : boolean;
signal dbgreg_mb_data : boolean;
signal dbgreg_transaction : std_logic;
signal jtag_mb_instr : std_logic;
signal jtag_mb_data : std_logic;
begin
dbgreg_AWADDR <= S_AXI_AWADDR(14 downto 2);
dbgreg_WDATA <= bus2ip_data;
dbgreg_ARADDR <= S_AXI_ARADDR(14 downto 2);
Valid_DFF: process (bus2ip_clk) is
begin
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
Dbgreg_AWVALID <= '0';
Dbgreg_WVALID <= '0';
Dbgreg_ARVALID <= '0';
dbgreg_access <= '0';
dbgreg_block <= '0';
dbgreg_mb_instr <= false;
dbgreg_mb_data <= false;
dbgreg_transaction <= '0';
else
if Dbg_AWREADY = '1' then
dbgreg_AWVALID <= '0';
end if;
if Dbg_WREADY = '1' then
dbgreg_WVALID <= '0';
end if;
if bus2ip_wrce(8) = '1' and dbgreg_access = '0' then
dbgreg_AWVALID <= not axi_block;
dbgreg_WVALID <= not axi_block;
dbgreg_access <= '1';
dbgreg_block <= axi_block;
dbgreg_mb_instr <= S_AXI_AWADDR(13 downto 6) = MB_WRITE_INSTR;
end if;
if Dbg_ARREADY = '1' then
dbgreg_ARVALID <= '0';
end if;
if bus2ip_rdce(8) = '1' and dbgreg_access = '0' then
dbgreg_ARVALID <= not axi_block;
dbgreg_access <= '1';
dbgreg_block <= axi_block;
dbgreg_mb_data <= S_AXI_ARADDR(13 downto 6) = MB_READ_DATA;
end if;
if (Dbg_BVALID = '1' or Dbg_RVALID = '1' or dbgreg_block = '1') and (dbgreg_access = '1') then
dbgreg_access <= '0';
dbgreg_block <= '0';
dbgreg_mb_instr <= false;
dbgreg_mb_data <= false;
dbgreg_transaction <= '1';
else
dbgreg_transaction <= '0';
end if;
end if;
end if;
end process Valid_DFF;
Write_Instr_Status : process (bus2ip_clk) is
begin -- process Write_Instr_Status
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
axi_instr_overrun <= '0';
else
if (dbgreg_mb_instr or jtag_mb_instr = '1') and Dbg_BVALID = '1' and Dbg_BRESP = '1' then
axi_instr_overrun <= '1';
end if;
if JTAG_Clear_Overrun = '1' then
axi_instr_overrun <= '0';
end if;
end if;
end if;
end process Write_Instr_Status;
Data_Read_Status : process (bus2ip_clk) is
begin -- process Data_Read_Status
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
axi_data_overrun <= '0';
else
if (dbgreg_mb_data or jtag_mb_data = '1') and Dbg_RVALID = '1' and Dbg_RRESP = '1' then
axi_data_overrun <= '1';
end if;
if JTAG_Clear_Overrun = '1' then
axi_data_overrun <= '0';
end if;
end if;
end if;
end process Data_Read_Status;
wrack_bus <= (Dbg_BVALID or dbgreg_block) and dbgreg_access;
rdack_bus <= (Dbg_RVALID or dbgreg_block) and dbgreg_access;
error_bus <= (Dbg_BRESP or Dbg_RRESP) and (not axi_completion_on) and dbgreg_access;
bus_data <= Dbg_RDATA;
Use_BSCAN : if (C_USE_BSCAN /= 3) generate
signal jtag_AWADDR : std_logic_vector(14 downto 2);
signal jtag_AWVALID : std_logic;
signal jtag_WVALID : std_logic;
signal jtag_WDATA : std_logic_vector(31 downto 0);
signal jtag_ARADDR : std_logic_vector(14 downto 2);
signal jtag_ARVALID : std_logic;
signal jtag_RDATA : std_logic_vector(31 downto 0);
signal jtag_access : boolean;
signal rd_shiftreg : std_logic_vector(0 to 31) := (others => '0');
signal rd_shiftcount : std_logic_vector(0 to 4) := (others => '0');
signal rd_shiftindex : std_logic_vector(0 to 4) := (others => '0');
signal rd_wordcount : std_logic_vector(0 to 3) := (others => '0');
signal readstart : std_logic := '0';
signal next_rd_shiftcount : std_logic_vector(0 to 5);
signal rd_jtag_access : boolean;
signal wr_shiftreg : std_logic_vector(0 to 255) := (others => '0');
signal wr_shiftcount : std_logic_vector(0 to 8) := (others => '0');
signal wr_wordcount : std_logic_vector(0 to 2);
signal writestart : std_logic := '0';
signal next_wr_shiftcount : std_logic_vector(0 to 8);
signal wr_lowaddr : std_logic_vector(0 to 2);
signal wr_command : std_logic_vector(0 to 7);
signal wr_index : integer range 0 to 7;
signal wr_jtag_access : boolean;
signal wr_data_in : std_logic_vector(0 to 42);
signal wr_data_write : std_logic;
signal wr_data_out : std_logic_vector(0 to 42);
signal wr_data_read : std_logic;
signal wr_data_exists : std_logic;
signal config_with_scan_reset : std_logic;
begin
BSCAN_FIFO_I : SRL_FIFO
generic map (
C_TARGET => C_TARGET, -- [TARGET_FAMILY_TYPE]
C_DATA_BITS => 43, -- [natural]
C_DEPTH => 16) -- [natural]
port map (
Clk => bus2ip_clk, -- [in std_logic]
Reset => bus_rst, -- [in std_logic]
FIFO_Write => wr_data_write, -- [in std_logic]
Data_In => wr_data_in, -- [in std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Read => wr_data_read, -- [in std_logic]
Data_Out => wr_data_out, -- [out std_logic_vector(0 to C_DATA_BITS-1)]
FIFO_Full => open, -- [out std_logic]
Data_Exists => wr_data_exists); -- [out std_logic]
wr_index <= 7 - to_integer(unsigned(wr_wordcount));
wr_data_in <= wr_shiftreg(wr_index * 32 to wr_index * 32 + 31) & wr_command & wr_lowaddr;
wr_data_read <= '1' when Dbg_BVALID = '1' and wr_jtag_access else '0';
jtag_WDATA <= wr_data_out(0 to 31);
jtag_AWADDR <= '1' & wr_data_out(32 to 39) & '0' & wr_data_out(40 to 42);
jtag_ARADDR <= '1' & Dbg_Command & rd_wordcount;
jtag_mb_instr <= '1' when Dbg_Reg_En = MB_WRITE_INSTR else '0';
jtag_mb_data <= '1' when Dbg_Reg_En = MB_READ_DATA else '0';
Data_Read : process (bus2ip_clk) is
begin -- process Data_Read
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
jtag_RDATA <= (others => '0');
elsif Dbg_RVALID = '1' then
jtag_RDATA <= Dbg_RDATA;
end if;
end if;
end process Data_Read;
Valid_DFF : process (bus2ip_clk)
variable sample : std_logic_vector(0 to 3) := (others => '0');
variable sample_1 : std_logic_vector(0 to 3) := (others => '0');
variable sample_2 : std_logic_vector(0 to 3) := (others => '0');
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
attribute ASYNC_REG of sample_1 : variable is "TRUE";
begin -- process Valid_DFF
if bus2ip_clk'event and bus2ip_clk = '1' then -- rising clock edge
if bus2ip_resetn = '0' then -- synchronous reset (active low)
jtag_AWVALID <= '0';
jtag_WVALID <= '0';
jtag_ARVALID <= '0';
jtag_access <= false;
rd_jtag_access <= false;
wr_wordcount <= (others => '0');
wr_lowaddr <= (others => '0');
wr_command <= (others => '0');
wr_data_write <= '0';
wr_jtag_access <= false;
sample_2 := (others => '0');
sample_1 := (others => '0');
sample := (others => '0');
else
if Dbg_AWREADY = '1' then
jtag_AWVALID <= '0';
end if;
if Dbg_WREADY = '1' then
jtag_WVALID <= '0';
end if;
if Dbg_ARREADY = '1' then
jtag_ARVALID <= '0';
end if;
-- Sample and edge-detect
if (sample_1(0) = '1' and sample_1(1) = '1' and sample_2(0) = '0') or
(sample_1(3) = '1' and sample_1(1) = '1' and sample_2(3) = '0') then
-- Rising edge of update with data_cmd = 1: Write word to FIFO if not IIR
-- Rising edge of writestart with data_cmd = 1: Write word to FIFO
wr_wordcount <= "000";
if Dbg_Reg_En(0 to 3) = "0001" and wr_shiftcount(0) = '0' then -- BP (128)
wr_wordcount <= "011";
end if;
if Dbg_Reg_En(0 to 3) = "0001" and wr_shiftcount(0) = '1' then -- WP (256)
wr_wordcount <= "111";
end if;
if Dbg_Reg_En = "01110110" then -- PDRR (36)
wr_wordcount <= "001";
end if;
wr_lowaddr <= (others => '0');
wr_command <= Dbg_Command;
wr_data_write <= not jtag_mb_instr or (sample_1(3) and not sample_2(3));
elsif wr_wordcount = "000" then
-- Write done
wr_data_write <= '0';
else
-- Write next word to FIFO
wr_wordcount <= std_logic_vector(unsigned(wr_wordcount) - 1);
wr_lowaddr <= std_logic_vector(unsigned(wr_lowaddr) + 1);
end if;
if (sample_1(1) = '1' and sample_2(1) = '0') or
(sample_1(2) = '1' and sample_1(1) = '1' and sample_2(2) = '0') then
-- Rising edge of data_cmd
-- Rising edge of readstart with data_cmd = 1
jtag_ARVALID <= '1';
rd_jtag_access <= true;
jtag_access <= true;
elsif (Dbg_BVALID = '1' and not rd_jtag_access) or
(Dbg_RVALID = '1' and not wr_jtag_access) then
jtag_access <= false;
end if;
sample_2 := sample_1;
sample_1 := sample;
sample(0) := Dbg_Update;
sample(1) := Dbg_data_cmd;
sample(2) := readstart;
sample(3) := writestart;
-- Start write transaction if FIFO not empty and no ongoing access
if wr_data_exists = '1' and not wr_jtag_access then
jtag_AWVALID <= '1';
jtag_WVALID <= '1';
wr_jtag_access <= true;
jtag_access <= true;
elsif (Dbg_BVALID = '1' and not rd_jtag_access) or
(Dbg_RVALID = '1' and not wr_jtag_access) then
jtag_access <= false;
end if;
if Dbg_BVALID = '1' then
wr_jtag_access <= false;
end if;
if Dbg_RVALID = '1' then
rd_jtag_access <= false;
end if;
end if;
end if;
end process Valid_DFF;
config_with_scan_reset <= Config_Reset when Scan_Reset_Sel = '0' else
Scan_Reset;
Shifter : process (DRCK, config_with_scan_reset)
begin
if config_with_scan_reset = '1' then
rd_shiftreg <= (others => '0');
rd_shiftcount <= (others => '0');
rd_shiftindex <= (others => '0');
rd_wordcount <= (others => '0');
readstart <= '0';
wr_shiftreg <= (others => '0');
wr_shiftcount <= (others => '0');
writestart <= '0';
elsif DRCK'event and DRCK = '1' then
readstart <= '0';
if Dbg_Shift = '1' then
rd_shiftreg <= rd_shiftreg(1 to rd_shiftreg'right) & '0';
rd_shiftcount <= next_rd_shiftcount(1 to next_rd_shiftcount'right);
wr_shiftreg <= wr_shiftreg(1 to wr_shiftreg'right) & Dbg_TDI;
wr_shiftcount <= next_wr_shiftcount;
end if;
if Dbg_Capture = '1' or next_rd_shiftcount(0) = '1' then
rd_shiftreg <= jtag_RDATA;
rd_wordcount <= std_logic_vector(unsigned(rd_wordcount) + 1);
readstart <= '1';
end if;
if Dbg_Capture = '1' then
rd_shiftcount <= (others => '0');
rd_shiftindex <= (others => '0');
if Dbg_Reg_En = "00000011" then -- SR (30)
rd_shiftindex <= "00010";
end if;
if Dbg_Reg_En = "01010011" then -- PCSR (2)
rd_shiftindex <= "11110";
end if;
if Dbg_Reg_En = "01100011" or Dbg_Reg_En = "01100110" then -- TSR, TDRR (18)
rd_shiftindex <= "01110";
end if;
wr_shiftcount <= (others => '0');
end if;
if next_rd_shiftcount(0) = '1' then
rd_shiftcount <= (others => '0');
rd_shiftindex <= (others => '0');
if Dbg_Reg_En = "00000110" and rd_wordcount = "0001" then -- DRR (32 + 1)
rd_shiftindex <= "11111";
end if;
if Dbg_Reg_En = "01110110" and rd_wordcount = "0001" then -- PDRR (32 + 4)
rd_shiftindex <= "11100";
end if;
end if;
if Dbg_Capture = '1' and Dbg_data_cmd = '0' then
rd_wordcount <= (others => '0');
end if;
if next_wr_shiftcount(3) = '1' and Dbg_Reg_En = "00000100" then -- IIR (32)
writestart <= '1';
wr_shiftcount <= (others => '0');
else
writestart <= '0';
end if;
end if;
end process Shifter;
next_rd_shiftcount <= std_logic_vector(unsigned('0' & rd_shiftcount) + 1);
next_wr_shiftcount <= std_logic_vector(unsigned(wr_shiftcount) + 1);
Dbg_TDO <= rd_shiftreg(to_integer(unsigned(rd_shiftindex)));
axi_transaction <= '0' when jtag_access else dbgreg_transaction;
Dbg_AWADDR <= jtag_AWADDR when jtag_access else dbgreg_AWADDR;
Dbg_WDATA <= jtag_WDATA when jtag_access else dbgreg_WDATA;
Dbg_ARADDR <= jtag_ARADDR when jtag_access else dbgreg_ARADDR;
Dbg_AWVALID_I <= jtag_AWVALID when jtag_access else dbgreg_AWVALID;
Dbg_WVALID_I <= jtag_WVALID when jtag_access else dbgreg_WVALID;
Dbg_ARVALID_I <= jtag_ARVALID when jtag_access else dbgreg_ARVALID;
end generate Use_BSCAN;
No_BSCAN : if (C_USE_BSCAN = 3) generate
begin
jtag_mb_instr <= '0';
jtag_mb_data <= '0';
Dbg_TDO <= '0';
axi_transaction <= dbgreg_transaction;
Dbg_AWADDR <= dbgreg_AWADDR;
Dbg_WDATA <= dbgreg_WDATA;
Dbg_ARADDR <= dbgreg_ARADDR;
Dbg_AWVALID_I <= dbgreg_AWVALID;
Dbg_WVALID_I <= dbgreg_WVALID;
Dbg_ARVALID_I <= dbgreg_ARVALID;
end generate No_BSCAN;
end generate Use_Parallel_Access;
Use_Serial_Access : if (C_DEBUG_INTERFACE = 0) generate
begin
axi_transaction <= '0';
axi_instr_overrun <= '0';
axi_data_overrun <= '0';
wrack_bus <= '0';
rdack_bus <= '0';
error_bus <= '0';
bus_data <= (others => '0');
end generate Use_Serial_Access;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if (C_DBG_REG_ACCESS = 0) generate
begin
DbgReg_DRCK <= '0';
DbgReg_UPDATE <= '0';
DbgReg_Select <= '0';
dbgreg_ip2bus_rdack <= '0';
dbgreg_ip2bus_wrack <= '0';
dbgreg_ip2bus_error <= '0';
dbgreg_ip2bus_data <= (others => '0');
dbgreg_access_lock <= '0';
dbgreg_force_lock <= '0';
dbgreg_unlocked <= '0';
jtag_axi_overrun <= '0';
axi_transaction <= '0';
axi_instr_overrun <= '0';
axi_data_overrun <= '0';
Old_MDM_SEL <= Old_MDM_SEL_Mux;
TDI <= JTAG_TDI;
RESET <= JTAG_RESET;
SHIFT <= JTAG_SHIFT;
CAPTURE <= JTAG_CAPTURE;
JTAG_TDO <= TDO;
disable <= jtag_disable;
end generate No_Dbg_Reg_Access;
-----------------------------------------------------------------------------
-- Trace: External Output, AXI Stream Output and AXI Master Output
-----------------------------------------------------------------------------
Use_Trace : if (C_TRACE_OUTPUT > 0) generate
type TrData_Type is array(0 to 31) of std_logic_vector(0 to 35);
signal Dbg_TrData : TrData_Type;
signal Dbg_TrValid : std_logic_vector(31 downto 0);
begin
More_Than_One_MB : if (C_MB_DBG_PORTS > 1) generate
constant C_LOG2_MB_DBG_PORTS : natural := log2(C_MB_DBG_PORTS);
signal index : std_logic_vector(C_LOG2_MB_DBG_PORTS-1 downto 0);
signal valid : std_logic;
signal idle : std_logic;
begin
Arbiter_i : Arbiter
generic map (
C_TARGET => C_TARGET, -- [TARGET_FAMILY_TYPE]
Size => C_MB_DBG_PORTS, -- [natural]
Size_Log2 => C_LOG2_MB_DBG_PORTS) -- [natural]
port map (
Clk => trace_clk_i, -- [in std_logic]
Reset => trace_reset, -- [in std_logic]
Enable => '0', -- [in std_logic]
Requests => Dbg_TrValid(C_MB_DBG_PORTS-1 downto 0), -- [in std_logic_vector(Size-1 downto 0)]
Granted => open, -- [out std_logic_vector(Size-1 downto 0)]
Valid_Sel => valid, -- [out std_logic]
Selected => index -- [out std_logic_vector(Size_Log2-1 downto 0)]
);
Arbiter_Keep: process (trace_clk_i) is
begin -- process Arbiter_Keep
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_index(C_LOG2_MB_DBG_PORTS-1 downto 0) <= (others => '0');
trace_valid <= '0';
idle <= '1';
else
if idle = '1' or trace_last_word = '1' then
trace_index(C_LOG2_MB_DBG_PORTS-1 downto 0) <= index;
trace_valid <= valid;
idle <= not valid;
end if;
end if;
end if;
end process Arbiter_Keep;
trace_index(4 downto C_LOG2_MB_DBG_PORTS) <= (others => '0');
trace_trdata <= Dbg_TrData(to_integer(unsigned(trace_index)));
Assign_Ready: process (trace_trready, trace_index) is
begin -- process Assign_Ready
Dbg_TrReady <= (others => '0');
Dbg_TrReady(to_integer(unsigned(trace_index))) <= trace_trready;
end process Assign_Ready;
end generate More_Than_One_MB;
Only_One_MB : if (C_MB_DBG_PORTS = 1) generate
begin
trace_index <= "00000";
trace_trdata <= Dbg_TrData(0);
trace_valid <= Dbg_TrValid(0);
Dbg_TrReady(0) <= trace_trready;
Dbg_TrReady(1 to 31) <= (others => '0');
end generate Only_One_MB;
No_MB : if (C_MB_DBG_PORTS = 0) generate
begin
trace_index <= "00000";
trace_trdata <= (others => '0');
trace_valid <= '0';
Dbg_TrReady <= (others => '0');
end generate No_MB;
Dbg_TrData(0) <= Dbg_TrData_0;
Dbg_TrData(1) <= Dbg_TrData_1;
Dbg_TrData(2) <= Dbg_TrData_2;
Dbg_TrData(3) <= Dbg_TrData_3;
Dbg_TrData(4) <= Dbg_TrData_4;
Dbg_TrData(5) <= Dbg_TrData_5;
Dbg_TrData(6) <= Dbg_TrData_6;
Dbg_TrData(7) <= Dbg_TrData_7;
Dbg_TrData(8) <= Dbg_TrData_8;
Dbg_TrData(9) <= Dbg_TrData_9;
Dbg_TrData(10) <= Dbg_TrData_10;
Dbg_TrData(11) <= Dbg_TrData_11;
Dbg_TrData(12) <= Dbg_TrData_12;
Dbg_TrData(13) <= Dbg_TrData_13;
Dbg_TrData(14) <= Dbg_TrData_14;
Dbg_TrData(15) <= Dbg_TrData_15;
Dbg_TrData(16) <= Dbg_TrData_16;
Dbg_TrData(17) <= Dbg_TrData_17;
Dbg_TrData(18) <= Dbg_TrData_18;
Dbg_TrData(19) <= Dbg_TrData_19;
Dbg_TrData(20) <= Dbg_TrData_20;
Dbg_TrData(21) <= Dbg_TrData_21;
Dbg_TrData(22) <= Dbg_TrData_22;
Dbg_TrData(23) <= Dbg_TrData_23;
Dbg_TrData(24) <= Dbg_TrData_24;
Dbg_TrData(25) <= Dbg_TrData_25;
Dbg_TrData(26) <= Dbg_TrData_26;
Dbg_TrData(27) <= Dbg_TrData_27;
Dbg_TrData(28) <= Dbg_TrData_28;
Dbg_TrData(29) <= Dbg_TrData_29;
Dbg_TrData(30) <= Dbg_TrData_30;
Dbg_TrData(31) <= Dbg_TrData_31;
Dbg_TrValid(0) <= Dbg_TrValid_0;
Dbg_TrValid(1) <= Dbg_TrValid_1;
Dbg_TrValid(2) <= Dbg_TrValid_2;
Dbg_TrValid(3) <= Dbg_TrValid_3;
Dbg_TrValid(4) <= Dbg_TrValid_4;
Dbg_TrValid(5) <= Dbg_TrValid_5;
Dbg_TrValid(6) <= Dbg_TrValid_6;
Dbg_TrValid(7) <= Dbg_TrValid_7;
Dbg_TrValid(8) <= Dbg_TrValid_8;
Dbg_TrValid(9) <= Dbg_TrValid_9;
Dbg_TrValid(10) <= Dbg_TrValid_10;
Dbg_TrValid(11) <= Dbg_TrValid_11;
Dbg_TrValid(12) <= Dbg_TrValid_12;
Dbg_TrValid(13) <= Dbg_TrValid_13;
Dbg_TrValid(14) <= Dbg_TrValid_14;
Dbg_TrValid(15) <= Dbg_TrValid_15;
Dbg_TrValid(16) <= Dbg_TrValid_16;
Dbg_TrValid(17) <= Dbg_TrValid_17;
Dbg_TrValid(18) <= Dbg_TrValid_18;
Dbg_TrValid(19) <= Dbg_TrValid_19;
Dbg_TrValid(20) <= Dbg_TrValid_20;
Dbg_TrValid(21) <= Dbg_TrValid_21;
Dbg_TrValid(22) <= Dbg_TrValid_22;
Dbg_TrValid(23) <= Dbg_TrValid_23;
Dbg_TrValid(24) <= Dbg_TrValid_24;
Dbg_TrValid(25) <= Dbg_TrValid_25;
Dbg_TrValid(26) <= Dbg_TrValid_26;
Dbg_TrValid(27) <= Dbg_TrValid_27;
Dbg_TrValid(28) <= Dbg_TrValid_28;
Dbg_TrValid(29) <= Dbg_TrValid_29;
Dbg_TrValid(30) <= Dbg_TrValid_30;
Dbg_TrValid(31) <= Dbg_TrValid_31;
end generate Use_Trace;
Use_Trace_External_AXI_Master : if (C_TRACE_OUTPUT = 1 or C_TRACE_OUTPUT = 3) generate
type ID_Type is array(integer range 0 to 1, integer range 1 to 4) of std_logic_vector(2 downto 0);
constant C_ID : ID_Type :=
(0 => ("010", "001", "011", "100"), -- C_USE_BSCAN = 0
1 => ("001", "001", "001", "001")); -- C_USE_BSCAN = 2 or 3
-- 16 x 32 bit LUTROM
type Mux_Select_Type is (Extra, Final, ID, D0, D1, D2, D3, S1, S2, S3);
type Mux_Select_Array_Type is array (3 downto 0) of Mux_Select_Type;
type Output_Select_Type is array(0 to 31) of Mux_Select_Array_Type;
constant output_select : Output_Select_Type := (
0 => (D2, D1, D0, ID),
1 => (D2, D1, D0, S3),
2 => (D1, D0, Extra, S3),
3 => (Final, D0, S3, S2),
4 => (Extra, S3, S2, S1), -- Only saved, block trready
5 => (D3, D2, D1, D0),
6 => (D3, D2, D1, D0),
7 => (Final, D1, D0, Extra),
8 => (D0, S3, S2, ID),
9 => (Extra, S3, S2, S1), -- Only saved, block trready
10 => (D3, D2, D1, D0),
11 => (Final, D2, D1, D0),
12 => (D1, D0, Extra, S3),
13 => (D1, D0, S3, S2),
14 => (D0, Extra, S3, S2),
15 => (Final, S3, S2, S1), -- Only saved, block trready
16 => (D2, D1, D0, ID),
17 => (D1, D0, Extra, S3),
18 => (D1, D0, S3, S2),
19 => (Final, Extra, S3, S2), -- Only saved, block trready
others => (D2, D1, D0, ID)
);
attribute rom_style : string;
attribute rom_style of output_select : constant is "distributed";
constant block_trready : std_logic_vector(0 to 31) := "00001000010000010001000000000000";
type Mux_Data_Select_Type is array(Mux_Select_Type) of std_logic_vector(7 downto 0);
signal dbg_trdata_mux : Mux_Data_Select_Type;
signal frame_word_index : std_logic_vector(0 to 4);
signal frame_word_first : std_logic;
signal frame_word_last : boolean;
signal frame_word_next_last : boolean;
signal output_select_data : Mux_Select_Array_Type;
signal block_trready_val : std_logic;
signal trace_data_0 : std_logic_vector(7 downto 0);
signal trace_data_1 : std_logic_vector(7 downto 0);
signal trace_data_2 : std_logic_vector(7 downto 0);
signal trace_data_3 : std_logic_vector(7 downto 0);
signal saved_extra : std_logic_vector(7 downto 0);
signal final_byte : std_logic_vector(7 downto 0);
signal saved_final : std_logic_vector(5 downto 0);
signal saved_trdata : std_logic_vector(31 downto 8);
signal trace_id : std_logic_vector(7 downto 0);
begin
output_select_data <= output_select(to_integer(unsigned(frame_word_index)));
block_trready_val <= block_trready(to_integer(unsigned(frame_word_index)));
dbg_trdata_mux <= (
ID => trace_id,
Extra => saved_extra,
Final => final_byte,
D0 => trace_trdata(7 downto 0),
D1 => trace_trdata(15 downto 8),
D2 => trace_trdata(25 downto 18),
D3 => trace_trdata(33 downto 26),
S1 => saved_trdata(15 downto 8),
S2 => saved_trdata(23 downto 16),
S3 => saved_trdata(31 downto 24)
);
trace_data_0 <= dbg_trdata_mux(output_select_data(0));
trace_data_1 <= dbg_trdata_mux(output_select_data(1));
trace_data_2 <= dbg_trdata_mux(output_select_data(2));
trace_data_3 <= dbg_trdata_mux(output_select_data(3));
final_byte <= trace_data_2(0) & trace_data_0(0) & saved_final;
Mux_Output: process (trace_clk_i) is
variable trace_data_0_lsb : std_logic;
begin -- process Mux_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_word <= C_FF_SYNC_PACKET;
saved_extra <= (others => '0');
saved_final <= (others => '0');
saved_trdata <= (others => '0');
frame_word_index <= (others => '0');
frame_word_first <= '0';
frame_word_last <= false;
trace_started <= '0';
trace_last_word <= '0';
else
if (trace_valid = '1' and trace_stopped = '0' and trace_count_last = '1') or (trace_started = '1') then
trace_last_word <= '0';
trace_started <= '1';
if trace_ready = '1' or trace_started = '0' then
if output_select_data(0) = ID then
trace_data_0_lsb := '1';
else
trace_data_0_lsb := '0';
end if;
trace_word(7 downto 0) <= trace_data_0(7 downto 1) & trace_data_0_lsb;
trace_word(15 downto 8) <= trace_data_1;
trace_word(23 downto 16) <= trace_data_2(7 downto 1) & '0';
trace_word(31 downto 24) <= trace_data_3;
if block_trready_val = '0' then
saved_extra <= trace_trdata(35 downto 34) & trace_trdata(17 downto 16) & saved_extra(7 downto 4);
end if;
saved_final <= trace_data_2(0) & trace_data_0(0) & saved_final(5 downto 2);
saved_trdata <= trace_trdata(33 downto 18) & trace_trdata(15 downto 8);
if frame_word_last then
frame_word_index <= (others => '0');
frame_word_first <= '1';
else
frame_word_index <= std_logic_vector(unsigned(frame_word_index) + 1);
frame_word_first <= '0';
end if;
if frame_word_next_last then
trace_last_word <= '1';
end if;
frame_word_last <= frame_word_next_last;
end if;
if trace_ready = '1' and frame_word_first = '1' then
trace_word <= C_FF_SYNC_PACKET;
frame_word_index <= (others => '0');
frame_word_first <= '0';
frame_word_last <= false;
trace_started <= '0';
end if;
else
trace_word <= C_FF_SYNC_PACKET;
saved_extra <= (others => '0');
saved_final <= (others => '0');
saved_trdata <= (others => '0');
frame_word_index <= (others => '0');
frame_word_first <= '0';
frame_word_last <= false;
trace_started <= '0';
trace_last_word <= '0';
end if;
end if;
end if;
end process Mux_Output;
frame_word_next_last <= frame_word_index = "10010"; -- 20 32-bit words per packet = 16 36-bit words
trace_id <= C_ID(Boolean'Pos(C_USE_BSCAN = 2 or C_USE_BSCAN = 3), C_JTAG_CHAIN) & trace_index;
trace_trready <=
(trace_valid and not trace_stopped and not trace_started) or -- first word
(trace_ready and trace_started and not block_trready_val and not frame_word_first); -- remaining words
end generate Use_Trace_External_AXI_Master;
Use_Trace_External : if (C_TRACE_OUTPUT = 1) generate
type pattern_select_type is (ZERO, IDLE, ONE, PAT_FE, SHIFT, PAT_55, PAT_AA);
type trig_type is array (natural range <>) of std_logic_vector(2 to 3);
signal pattern_sel : pattern_select_type := ZERO;
signal pattern : std_logic_vector(C_TRACE_DATA_WIDTH - 1 downto 0);
signal next_pattern : std_logic_vector(C_TRACE_DATA_WIDTH - 1 downto 0) := (others => '0');
signal delay_count : std_logic_vector(0 to 7) := (others => '0');
signal next_delay_count : std_logic_vector(0 to 7);
signal delay_count_zero : boolean;
signal sync_packet : std_logic := '0';
signal sync_count : std_logic_vector(0 to 4) := (others => '0');
signal testing : std_logic := '0';
signal test_ctl : std_logic := '1';
signal trace_clk_div2 : std_logic := '0';
signal trace_data_i : std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0) := (others => '0');
signal trace_ctl_i : std_logic := '1';
signal trace_ctl_o : std_logic := '1';
signal trace_ctl_next : std_logic;
signal trace_trig : trig_type(0 to 31);
signal trig_on : std_logic := '0';
signal trig_pending : std_logic := '0';
signal trig_counting : std_logic := '0';
signal trig_count : std_logic_vector(0 to 16) := (0 => '1', others => '0');
signal trig_count_init : std_logic_vector(0 to 16);
attribute dont_touch : string;
attribute dont_touch of trace_ctl_i : signal is "true"; -- Keep FF for internal use
attribute dont_touch of trace_ctl_o : signal is "true"; -- Keep FF for IOB insertion
begin
-- Generate test patterns
pattern(0) <= next_pattern(C_TRACE_DATA_WIDTH - 1) when pattern_sel = SHIFT else
'1' when pattern_sel = IDLE or
pattern_sel = ONE or
pattern_sel = PAT_55 else
'0';
Gen_Test_Pattern: for I in 1 to C_TRACE_DATA_WIDTH - 1 generate
begin
pattern(I) <= next_pattern(I-1) when (pattern_sel = SHIFT) else
'1' when (pattern_sel = ONE) or
(pattern_sel = PAT_FE) or
(pattern_sel = PAT_55 and (I mod 2) = 0) or
(pattern_sel = PAT_AA and (I mod 2) = 1) else
'0';
end generate Gen_Test_Pattern;
Pattern_DFF: process (trace_clk_i) is
type state_type is (IDLE, STARTING, WALKING_1, WALKING_0, PAT_AA, PAT_55, PAT_FF, PAT_00);
variable state : state_type := IDLE;
begin -- process Pattern_DFF
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
pattern_sel <= ZERO;
delay_count <= trace_delay;
testing <= '0';
test_ctl <= '1';
state := IDLE;
next_pattern <= (others => '0');
else
case state is
when IDLE =>
pattern_sel <= ZERO;
delay_count <= trace_delay;
testing <= '0';
test_ctl <= '1';
if trace_test_start = '1' then
state := STARTING;
end if;
when STARTING =>
pattern_sel <= ZERO;
delay_count <= trace_delay;
if trace_started = '0' and trace_count_last = '1' then
if trace_test_pattern(3) = '1' then -- Alternating FF/00
pattern_sel <= ONE;
state := PAT_FF;
elsif trace_test_pattern(2) = '1' then -- Alternating AA/55
pattern_sel <= PAT_55;
state := PAT_55;
elsif trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
end if;
testing <= '1';
test_ctl <= '0';
end if;
when PAT_FF =>
delay_count <= next_delay_count;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
if trace_test_pattern(2) = '1' then -- Alternating AA/55
pattern_sel <= PAT_55;
state := PAT_55;
elsif trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
else
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
else
pattern_sel <= ZERO;
state := PAT_00;
end if;
when PAT_00 =>
delay_count <= next_delay_count;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
if trace_test_pattern(2) = '1' then -- Alternating AA/55
pattern_sel <= PAT_55;
state := PAT_55;
elsif trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
else
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
else
pattern_sel <= ONE;
state := PAT_FF;
end if;
when PAT_55 =>
delay_count <= next_delay_count;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
if trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
else
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
else
pattern_sel <= PAT_AA;
state := PAT_AA;
end if;
when PAT_AA =>
delay_count <= next_delay_count;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
if trace_test_pattern(1) = '1' then -- Walking 0s
pattern_sel <= PAT_FE;
state := WALKING_0;
elsif trace_test_pattern(0) = '1' then -- Walking 1s
pattern_sel <= IDLE;
state := WALKING_1;
else
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
else
pattern_sel <= PAT_55;
state := PAT_55;
end if;
when WALKING_0 =>
delay_count <= next_delay_count;
pattern_sel <= SHIFT;
if trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
elsif delay_count_zero then
delay_count <= trace_delay;
pattern_sel <= IDLE;
if trace_test_pattern(0) = '1' then -- Walking 1s
state := WALKING_1;
else
test_ctl <= '1';
state := IDLE;
end if;
end if;
when WALKING_1 =>
delay_count <= next_delay_count;
pattern_sel <= SHIFT;
if delay_count_zero or trace_test_stop = '1' then
test_ctl <= '1';
pattern_sel <= IDLE;
state := IDLE;
end if;
-- coverage off
when others =>
null;
-- coverage on
end case;
next_pattern <= pattern;
end if;
end if;
end process Pattern_DFF;
next_delay_count <= std_logic_vector(unsigned(delay_count) - 1);
delay_count_zero <= delay_count = (delay_count'range => '0') and trace_test_timed = '1';
-- Output data or test pattern according to width
Has_Full_Width: if C_TRACE_DATA_WIDTH = 32 generate
begin
Data_Output: process (trace_clk_i) is
begin -- process Data_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_data_i <= (others => '0');
trace_data_i(0) <= '1';
trace_ctl_i <= '1';
trace_ctl_o <= '1';
else
if testing = '0' then
trace_ctl_i <= trace_ctl_next;
trace_ctl_o <= trace_ctl_next;
trace_data_i <= trace_word;
if trace_ctl_next = '1' then
trace_data_i <= (others => '0');
trace_data_i(0) <= '1'; -- Indicates trace disable when TRACE_CTL = '1'
if trig_on = '1' and sync_packet = '0' then
trace_data_i(1 downto 0) <= "10"; -- Indicates trigger when TRACE_CTL = '1'
end if;
end if;
else
trace_ctl_i <= test_ctl;
trace_ctl_o <= test_ctl;
trace_data_i <= pattern(C_TRACE_DATA_WIDTH - 1 downto 0);
end if;
end if;
end if;
end process Data_Output;
trace_ready <= not testing;
trace_count_last <= '1';
end generate Has_Full_Width;
Not_Full_Width: if C_TRACE_DATA_WIDTH < 32 generate
constant C_COUNTER_WIDTH : integer := log2(32 / C_TRACE_DATA_WIDTH);
signal data_count : std_logic_vector(0 to C_COUNTER_WIDTH - 1) := (others => '0');
signal data_count_next : std_logic_vector(0 to C_COUNTER_WIDTH - 1);
signal last_word_keep : std_logic := '0';
signal last_word_next : std_logic := '0';
begin
Data_Output: process (trace_clk_i) is
variable data_index : integer range 0 to 32 / C_TRACE_DATA_WIDTH - 1;
begin -- process Data_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_data_i <= (others => '0');
trace_data_i(0) <= '1';
data_count <= (others => '0');
trace_ctl_i <= '1';
trace_ctl_o <= '1';
last_word_keep <= '0';
last_word_next <= '0';
else
if testing = '0' then
trace_ctl_i <= trace_ctl_next;
trace_ctl_o <= trace_ctl_next;
data_index := to_integer(unsigned(data_count));
trace_data_i <= trace_word(data_index * C_TRACE_DATA_WIDTH + C_TRACE_DATA_WIDTH - 1 downto
data_index * C_TRACE_DATA_WIDTH);
if trace_last_word = '1' then
last_word_keep <= '1';
end if;
if trace_count_last = '1' then
data_count <= (others => '0');
last_word_next <= last_word_keep;
last_word_keep <= '0';
else
data_count <= data_count_next;
end if;
if trace_ctl_next = '1' then
trace_data_i <= (others => '0');
trace_data_i(0) <= '1'; -- Indicates trace disable when TRACE_CTL = '1'
if trig_on = '1' and sync_packet = '0' then
trace_data_i(1 downto 0) <= "10"; -- Indicates trigger when TRACE_CTL = '1'
end if;
end if;
else
trace_ctl_i <= test_ctl;
trace_ctl_o <= test_ctl;
trace_data_i <= pattern(C_TRACE_DATA_WIDTH - 1 downto 0);
data_count <= (others => '0');
end if;
end if;
end if;
end process Data_Output;
data_count_next <= std_logic_vector(unsigned(data_count) + 1);
trace_count_last <= '1' when data_count = (data_count'range => '1') else '0';
trace_ready <= (not trace_ctl_i) and trace_count_last;
end generate Not_Full_Width;
trace_ctl_next <= not (trace_started or sync_packet);
-- Synchronize reset
Reset_DFF: process (trace_clk_i) is
variable sample : std_logic_vector(0 to 1) := "11";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
begin -- process Sync_Reset
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
trace_reset <= sample(1);
sample(1) := sample(0);
sample(0) := Debug_SYS_Rst_i or config_reset_i;
end if;
end process Reset_DFF;
-- Generate half frequency output clock
Use_PLL: if C_TRACE_CLK_OUT_PHASE /= 0 generate
constant C_CLKFBOUT_MULT : integer := (800000000 + C_TRACE_CLK_FREQ_HZ - 1000000) / C_TRACE_CLK_FREQ_HZ;
constant C_CLKIN_PERIOD : real := 1000000000.0 / real(C_TRACE_CLK_FREQ_HZ);
constant C_CLKOUT0_DIVIDE : integer := C_CLKFBOUT_MULT * 2;
constant C_CLKOUT0_PHASE : real := real(C_TRACE_CLK_OUT_PHASE);
signal trace_clk_o : std_logic;
signal trace_clk_fbin : std_logic;
signal trace_clk_fbout : std_logic;
begin
PLL_TRACE_CLK : MB_PLLE2_BASE
generic map (
C_TARGET => C_TARGET,
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.000,
CLKIN1_PERIOD => C_CLKIN_PERIOD,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_PHASE => C_CLKOUT0_PHASE,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_PHASE => 0.000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_PHASE => 0.000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_PHASE => 0.000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_PHASE => 0.000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500,
CLKOUT5_PHASE => 0.000,
DIVCLK_DIVIDE => 1,
REF_JITTER1 => 0.010,
STARTUP_WAIT => "FALSE"
)
port map (
CLKFBOUT => trace_clk_fbout,
CLKOUT0 => trace_clk_div2,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
CLKFBIN => trace_clk_fbin,
CLKIN1 => trace_clk_i,
PWRDWN => '0',
RST => trace_reset
);
BUFG_TRACE_CLK_FB : MB_BUFG
generic map (
C_TARGET => C_TARGET
)
port map (
O => trace_clk_fbin,
I => trace_clk_fbout
);
BUFG_TRACE_CLK : MB_BUFG
generic map (
C_TARGET => C_TARGET
)
port map (
O => trace_clk_o,
I => trace_clk_div2
);
TRACE_CLK_OUT <= trace_clk_o;
end generate Use_PLL;
No_PLL: if C_TRACE_CLK_OUT_PHASE = 0 generate
signal trace_clk_div2 : std_logic := '0';
signal trace_clk_o : std_logic := '0';
attribute dont_touch : string;
attribute dont_touch of trace_clk_o : signal is "true"; -- Keep FF for IOB insertion
begin
TRACE_CLK_OUT_DFF: process (trace_clk_i) is
begin -- process TRACE_CLK_OUT_DFF
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
trace_clk_div2 <= not trace_clk_div2;
trace_clk_o <= trace_clk_div2;
end if;
end process TRACE_CLK_OUT_DFF;
TRACE_CLK_OUT <= trace_clk_o; -- Any clock delay, phase shift or buffering is done outside MDM
end generate No_PLL;
TRACE_CTL <= trace_ctl_o;
TRACE_DATA <= trace_data_i;
trace_clk_i <= TRACE_CLK; -- Any clock doubling from external port is done outside MDM
-- Generate synchronization packets
Sync_Gen: process (trace_clk_i) is
begin -- process Sync_Gen
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
sync_packet <= '0';
sync_count <= (others => '0');
else
if sync_count(0) = '1' then
sync_count <= (others => '0');
sync_packet <= '1';
elsif trace_last_word = '1' then
sync_count <= std_logic_vector(unsigned(sync_count) + 1);
end if;
if trace_started = '0' and sync_packet = '1' and trace_count_last = '1' then
sync_packet <= '0';
end if;
end if;
end if;
end process Sync_Gen;
-- Generate trigger
Tigger_Detect: process (trace_clk_i) is
variable sample : trig_type(0 to C_MB_DBG_PORTS - 1) := (others => (others => '0'));
variable sample_1 : trig_type(0 to C_MB_DBG_PORTS - 1) := (others => (others => '0'));
variable sample_2 : trig_type(0 to C_MB_DBG_PORTS - 1) := (others => (others => '0'));
attribute ASYNC_REG : string;
attribute ASYNC_REG of sample : variable is "TRUE";
attribute ASYNC_REG of sample_1 : variable is "TRUE";
begin -- process Tigger_Detect
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trig_on <= '0';
trig_pending <= '0';
trig_counting <= '0';
trig_count <= trig_count_init;
sample_2 := (others => (others => '0'));
sample_1 := (others => (others => '0'));
sample := (others => (others => '0'));
else
-- Sample and edge-detect triggers
for I in 0 to C_MB_DBG_PORTS - 1 loop
if sample_2(I)(2) = '0' and sample_1(I)(2) = '1' then
-- Trigger on trace stop, or start counting on trace stop
trig_pending <= trig_pending or trace_test_pattern(0);
trig_counting <= trig_counting or trace_test_pattern(1);
end if;
if sample_2(I)(3) = '0' and sample_1(I)(3) = '1' then
-- Trigger on trace start, or start counting on trace start
trig_pending <= trig_pending or trace_test_pattern(2);
trig_counting <= trig_counting or trace_test_pattern(3);
end if;
end loop;
sample_2 := sample_1;
sample_1 := sample;
sample := trace_trig(0 to C_MB_DBG_PORTS - 1);
-- Decrement trigger count
if trig_counting = '1' then
if trig_count(0) = '0' then
trig_count <= trig_count_init;
trig_counting <= '0';
trig_pending <= '1';
else
trig_count <= std_logic_vector(unsigned(trig_count) - 1);
end if;
else
trig_count <= trig_count_init;
end if;
-- Pending trigger output
if testing = '0' and trace_ctl_i = '1' and sync_packet = '0' and trace_count_last = '1' then
trig_on <= trig_pending;
trig_pending <= '0';
else
trig_on <= '0';
end if;
end if;
end if;
end process Tigger_Detect;
trig_count_init <= '1' & trace_delay & "00000000";
trace_trig(0) <= Dbg_Trig_In_0(2 to 3);
trace_trig(1) <= Dbg_Trig_In_1(2 to 3);
trace_trig(2) <= Dbg_Trig_In_2(2 to 3);
trace_trig(3) <= Dbg_Trig_In_3(2 to 3);
trace_trig(4) <= Dbg_Trig_In_4(2 to 3);
trace_trig(5) <= Dbg_Trig_In_5(2 to 3);
trace_trig(6) <= Dbg_Trig_In_6(2 to 3);
trace_trig(7) <= Dbg_Trig_In_7(2 to 3);
trace_trig(8) <= Dbg_Trig_In_8(2 to 3);
trace_trig(9) <= Dbg_Trig_In_9(2 to 3);
trace_trig(10) <= Dbg_Trig_In_10(2 to 3);
trace_trig(11) <= Dbg_Trig_In_11(2 to 3);
trace_trig(12) <= Dbg_Trig_In_12(2 to 3);
trace_trig(13) <= Dbg_Trig_In_13(2 to 3);
trace_trig(14) <= Dbg_Trig_In_14(2 to 3);
trace_trig(15) <= Dbg_Trig_In_15(2 to 3);
trace_trig(16) <= Dbg_Trig_In_16(2 to 3);
trace_trig(17) <= Dbg_Trig_In_17(2 to 3);
trace_trig(18) <= Dbg_Trig_In_18(2 to 3);
trace_trig(19) <= Dbg_Trig_In_19(2 to 3);
trace_trig(20) <= Dbg_Trig_In_20(2 to 3);
trace_trig(21) <= Dbg_Trig_In_21(2 to 3);
trace_trig(22) <= Dbg_Trig_In_22(2 to 3);
trace_trig(23) <= Dbg_Trig_In_23(2 to 3);
trace_trig(24) <= Dbg_Trig_In_24(2 to 3);
trace_trig(25) <= Dbg_Trig_In_25(2 to 3);
trace_trig(26) <= Dbg_Trig_In_26(2 to 3);
trace_trig(27) <= Dbg_Trig_In_27(2 to 3);
trace_trig(28) <= Dbg_Trig_In_28(2 to 3);
trace_trig(29) <= Dbg_Trig_In_29(2 to 3);
trace_trig(30) <= Dbg_Trig_In_30(2 to 3);
trace_trig(31) <= Dbg_Trig_In_31(2 to 3);
-- Unused
M_AXIS_TDATA <= (others => '0');
M_AXIS_TID <= (others => '0');
M_AXIS_TVALID <= '0';
Master_dwr_data <= (others => '0');
Master_dwr_start <= '0';
end generate Use_Trace_External;
Use_Trace_AXI_Stream : if (C_TRACE_OUTPUT = 2) generate
type ID_Type is array(integer range 0 to 1, integer range 1 to 4) of std_logic_vector(1 downto 0);
constant C_ID : ID_Type :=
(0 => ("01", "00", "10", "11"), -- C_USE_BSCAN = 0
1 => ("00", "00", "00", "00")); -- C_USE_BSCAN = 2 or 3
-- 12 x 32 bit LUTROM
type Mux_Select_Type is (Extra, D0, D1, D2, D3, S1, S2, S3);
type Mux_Select_Array_Type is array (3 downto 0) of Mux_Select_Type;
type Output_Select_Type is array(0 to 31) of Mux_Select_Array_Type;
constant output_select : Output_Select_Type := (
0 => (D3, D2, D1, D0),
1 => (D3, D2, D1, D0),
2 => (D2, D1, D0, Extra),
3 => (D2, D1, D0, S3),
4 => (D1, D0, Extra, S3),
5 => (D1, D0, S3, S2),
6 => (D0, Extra, S3, S2),
7 => (D0, S3, S2, S1),
8 => (Extra, S3, S2, S1), -- Only saved, block trready
9 => (D3, D2, D1, D0),
10 => (D3, D2, D1, D0),
11 => (D2, D1, D0, Extra),
12 => (D2, D1, D0, S3),
13 => (D1, D0, Extra, S3),
14 => (D1, D0, S3, S2),
15 => (D0, Extra, S3, S2),
16 => (D0, S3, S2, S1),
17 => (Extra, S3, S2, S1), -- Only saved, block trready
others => (Extra, Extra, Extra, Extra)
);
attribute rom_style : string;
attribute rom_style of output_select : constant is "distributed";
constant block_trready : std_logic_vector(0 to 31) := "00000000100000000100000000000000";
type Mux_Data_Select_Type is array(Mux_Select_Type) of std_logic_vector(7 downto 0);
signal dbg_trdata_mux : Mux_Data_Select_Type;
signal frame_word_index : std_logic_vector(0 to 4);
signal frame_word_first : std_logic;
signal output_select_data : Mux_Select_Array_Type;
signal block_trready_val : std_logic;
signal trace_data_0 : std_logic_vector(7 downto 0);
signal trace_data_1 : std_logic_vector(7 downto 0);
signal trace_data_2 : std_logic_vector(7 downto 0);
signal trace_data_3 : std_logic_vector(7 downto 0);
signal saved_extra : std_logic_vector(7 downto 0);
signal saved_trdata : std_logic_vector(31 downto 8);
signal delay_count : std_logic_vector(0 to 7);
signal delay_zero : std_logic;
signal trace_id : std_logic_vector(6 downto 0);
signal trace_tvalid : std_logic;
begin
output_select_data <= output_select(to_integer(unsigned(frame_word_index)));
block_trready_val <= block_trready(to_integer(unsigned(frame_word_index)));
dbg_trdata_mux <= (
Extra => saved_extra,
D0 => trace_trdata(7 downto 0),
D1 => trace_trdata(15 downto 8),
D2 => trace_trdata(25 downto 18),
D3 => trace_trdata(33 downto 26),
S1 => saved_trdata(15 downto 8),
S2 => saved_trdata(23 downto 16),
S3 => saved_trdata(31 downto 24)
);
trace_data_0 <= dbg_trdata_mux(output_select_data(0));
trace_data_1 <= dbg_trdata_mux(output_select_data(1));
trace_data_2 <= dbg_trdata_mux(output_select_data(2));
trace_data_3 <= dbg_trdata_mux(output_select_data(3));
Mux_Output: process (trace_clk_i) is
begin -- process Mux_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_word <= (others => '0');
saved_extra <= (others => '0');
saved_trdata <= (others => '0');
trace_started <= '0';
trace_last_word <= '0';
trace_tvalid <= '0';
frame_word_index <= (others => '0');
frame_word_first <= '0';
else
if (trace_valid = '1' or trace_started = '1') and (delay_zero = '1') then
trace_last_word <= '0';
trace_started <= '1';
trace_tvalid <= '1';
if trace_ready = '1' or trace_started = '0' then
trace_word(7 downto 0) <= trace_data_0;
trace_word(15 downto 8) <= trace_data_1;
trace_word(23 downto 16) <= trace_data_2;
trace_word(31 downto 24) <= trace_data_3;
saved_extra <= trace_trdata(35 downto 34) & trace_trdata(17 downto 16) & saved_extra(7 downto 4);
saved_trdata <= trace_trdata(33 downto 18) & trace_trdata(15 downto 8);
if (frame_word_index = "10001") then -- 18 32-bit words per packet = 16 36-bit words
frame_word_index <= (others => '0');
trace_started <= '0';
frame_word_first <= '1';
else
frame_word_index <= std_logic_vector(unsigned(frame_word_index) + 1);
frame_word_first <= '0';
end if;
if frame_word_index = "10000" then -- 18 32-bit words per packet = 16 36-bit words
trace_last_word <= '1';
end if;
end if;
if trace_ready = '1' and frame_word_first = '1' then
frame_word_first <= '0';
end if;
else
trace_tvalid <= '0';
frame_word_first <= '0';
end if;
end if;
end if;
end process Mux_Output;
Delay_Counter: process (trace_clk_i) is
begin -- process Delay_Counter
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
delay_count <= trace_delay;
delay_zero <= '1';
else
if trace_delay = (trace_delay'range => '0') then
delay_count <= trace_delay;
delay_zero <= '1';
elsif (trace_valid = '1' or trace_started = '1') and (delay_zero = '1') and
(trace_ready = '1' or trace_started = '0') then
delay_count <= trace_delay;
delay_zero <= '0';
elsif delay_count = (delay_count'range => '0') then
delay_zero <= '1';
else
delay_count <= std_logic_vector(unsigned(delay_count) - 1);
delay_zero <= '0';
end if;
end if;
end if;
end process Delay_Counter;
Trace_ID_Output: process (trace_clk_i) is
begin -- process Trace_ID_Output
if trace_clk_i'event and trace_clk_i = '1' then -- rising clock edge
if trace_reset = '1' then -- synchronous reset (active high)
trace_id <= (others => '0');
else
trace_id <= C_ID(Boolean'Pos(C_USE_BSCAN = 2 or C_USE_BSCAN = 3), C_JTAG_CHAIN) & trace_index;
end if;
end if;
end process Trace_ID_Output;
M_AXIS_TDATA <= trace_word;
M_AXIS_TVALID <= trace_tvalid;
M_AXIS_TID <= trace_id(C_M_AXIS_ID_WIDTH-1 downto 0);
trace_clk_i <= M_AXIS_ACLK;
trace_reset <= not M_AXIS_ARESETN;
trace_ready <= M_AXIS_TREADY;
trace_trready <=
(trace_valid and not trace_started and delay_zero) or -- first word
(trace_ready and trace_started and not block_trready_val and not frame_word_first and delay_zero); -- remaining
-- Unused
TRACE_CLK_OUT <= '0';
TRACE_CTL <= '1';
TRACE_DATA <= (others => '0');
Master_dwr_data <= (others => '0');
Master_dwr_start <= '0';
trace_count_last <= '0';
end generate Use_Trace_AXI_Stream;
Use_Trace_AXI_Master : if (C_TRACE_OUTPUT = 3) generate
begin
Master_dwr_data <= trace_word;
Master_dwr_start <= (trace_valid and not trace_stopped) or trace_started;
trace_clk_i <= M_AXI_ACLK;
trace_reset <= not M_AXI_ARESETN;
trace_ready <= Master_dwr_next;
trace_count_last <= '1';
-- Unused
M_AXIS_TDATA <= (others => '0');
M_AXIS_TID <= (others => '0');
M_AXIS_TVALID <= '0';
TRACE_CLK_OUT <= '0';
TRACE_CTL <= '1';
TRACE_DATA <= (others => '0');
end generate Use_Trace_AXI_Master;
No_Trace : if (C_TRACE_OUTPUT = 0) generate
begin
Dbg_TrReady <= (others => '0');
trace_clk_i <= '0';
trace_reset <= '0';
trace_word <= (others => '0');
trace_index <= (others => '0');
trace_trdata <= (others => '0');
trace_valid <= '0';
trace_last_word <= '0';
trace_ready <= '0';
trace_trready <= '0';
trace_started <= '0';
trace_count_last <= '0';
M_AXIS_TDATA <= (others => '0');
M_AXIS_TID <= (others => '0');
M_AXIS_TVALID <= '0';
TRACE_CLK_OUT <= '0';
TRACE_CTL <= '1';
TRACE_DATA <= (others => '0');
Master_dwr_data <= (others => '0');
Master_dwr_start <= '0';
end generate No_Trace;
Dbg_TrClk <= trace_clk_i;
---------------------------------------------------------------------------
-- Instantiating the receive and transmit modules
---------------------------------------------------------------------------
JTAG_CONTROL_I : JTAG_CONTROL
generic map (
C_TARGET => C_TARGET,
C_USE_BSCAN => C_USE_BSCAN,
C_MB_DBG_PORTS => C_MB_DBG_PORTS,
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET,
C_DEBUG_INTERFACE => C_DEBUG_INTERFACE,
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS,
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER,
C_USE_UART => C_USE_UART,
C_UART_WIDTH => C_UART_WIDTH,
C_TRACE_OUTPUT => C_TRACE_OUTPUT,
C_EN_WIDTH => C_EN_WIDTH
)
port map (
Config_Reset => config_reset_i, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
Clk => bus2ip_clk, -- [in std_logic]
Rst => bus_rst, -- [in std_logic]
Clear_Ext_BRK => clear_Ext_BRK, -- [in std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst_i, -- [out std_logic]
Debug_Rst => Debug_Rst_i, -- [out std_logic]
Read_RX_FIFO => read_RX_FIFO, -- [in std_logic]
Reset_RX_FIFO => reset_RX_FIFO, -- [in std_logic]
RX_Data => rx_Data, -- [out std_logic_vector(0 to 7)]
RX_Data_Present => rx_Data_Present, -- [out std_logic]
RX_Buffer_Full => rx_Buffer_Full, -- [out std_logic]
Write_TX_FIFO => write_TX_FIFO, -- [in std_logic]
Reset_TX_FIFO => reset_TX_FIFO, -- [in std_logic]
TX_Data => tx_Data, -- [in std_logic_vector(0 to 7)]
TX_Buffer_Full => tx_Buffer_Full, -- [out std_logic]
TX_Buffer_Empty => tx_Buffer_Empty, -- [out std_logic]
-- Debug Register Access signals
DbgReg_Access_Lock => dbgreg_access_lock, -- [in std_logic]
DbgReg_Force_Lock => dbgreg_force_lock, -- [in std_logic]
DbgReg_Unlocked => dbgreg_unlocked, -- [in std_logic]
JTAG_Access_Lock => jtag_access_lock, -- [out std_logic]
JTAG_Force_Lock => jtag_force_lock, -- [out std_logic]
JTAG_AXI_Overrun => jtag_axi_overrun, -- [in std_logic]
JTAG_Clear_Overrun => jtag_clear_overrun, -- [out std_logic]
AXI_Transaction => axi_transaction, -- [in std_logic]
AXI_Instr_Overrun => axi_instr_overrun, -- [in std_logic]
AXI_Data_Overrun => axi_data_overrun, -- [in std_logic]
AXI_Completion_On => axi_completion_on, -- [out std_logic]
AXI_Block => axi_block, -- [out std_logic]
-- MDM signals
TDI => Old_MDM_TDI, -- [in std_logic]
RESET => Old_MDM_RESET, -- [in std_logic]
UPDATE => Old_MDM_UPDATE, -- [in std_logic]
SHIFT => Old_MDM_SHIFT, -- [in std_logic]
CAPTURE => Old_MDM_CAPTURE, -- [in std_logic]
SEL => Old_MDM_SEL, -- [in std_logic]
DRCK => Old_MDM_DRCK, -- [in std_logic]
TDO => Old_MDM_TDO, -- [out std_logic]
-- AXI Master signals
M_AXI_ACLK => M_AXI_ACLK, -- [in std_logic]
M_AXI_ARESETn => M_AXI_ARESETn, -- [in std_logic]
Master_rd_start => Master_rd_start, -- [out std_logic]
Master_rd_addr => Master_rd_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_rd_len => Master_rd_len, -- [out std_logic_vector(4 downto 0)]
Master_rd_size => Master_rd_size, -- [out std_logic_vector(1 downto 0)]
Master_rd_excl => Master_rd_excl, -- [out std_logic]
Master_rd_idle => Master_rd_idle, -- [out std_logic]
Master_rd_resp => Master_rd_resp, -- [out std_logic_vector(1 downto 0)]
Master_wr_start => Master_wr_start, -- [out std_logic]
Master_wr_addr => Master_wr_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_wr_len => Master_wr_len, -- [out std_logic_vector(4 downto 0)]
Master_wr_size => Master_wr_size, -- [out std_logic_vector(1 downto 0)]
Master_wr_excl => Master_wr_excl, -- [out std_logic]
Master_wr_idle => Master_wr_idle, -- [out std_logic]
Master_wr_resp => Master_wr_resp, -- [out std_logic_vector(1 downto 0)]
Master_data_rd => Master_data_rd, -- [out std_logic]
Master_data_out => Master_data_out, -- [in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0)]
Master_data_exists => Master_data_exists, -- [in std_logic]
Master_data_wr => Master_data_wr, -- [out std_logic]
Master_data_in => Master_data_in, -- [out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0)]
Master_data_empty => Master_data_empty, -- [in std_logic]
Master_dwr_addr => Master_dwr_addr, -- [out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0)]
Master_dwr_len => Master_dwr_len, -- [out std_logic_vector(4 downto 0)]
Master_dwr_done => Master_dwr_done, -- [in std_logic]
Master_dwr_resp => Master_dwr_resp, -- [in std_logic]
-- MicroBlaze Debug Signals
MB_Debug_Enabled => mb_debug_enabled_i, -- [out std_logic_vector(7 downto 0)]
Dbg_Clk => Dbg_Clk, -- [out std_logic]
Dbg_TDI => Dbg_TDI, -- [out std_logic]
Dbg_TDO => Dbg_TDO, -- [in std_logic]
Dbg_Reg_En => Dbg_Reg_En, -- [out std_logic_vector(0 to 7)]
Dbg_Capture => Dbg_Capture, -- [out std_logic]
Dbg_Shift => Dbg_Shift, -- [out std_logic]
Dbg_Update => Dbg_Update, -- [out std_logic]
Dbg_data_cmd => Dbg_data_cmd, -- [out std_logic]
Dbg_command => Dbg_command, -- [out std_logic_vector(0 to 7)]
-- MicroBlaze Cross Trigger Signals
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Ext_Trig_In => Ext_Trig_In, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => Ext_Trig_Ack_In, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => Ext_Trig_Out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => Ext_Trig_Ack_Out, -- [in std_logic_vector(0 to 3)]
Trace_Clk => trace_clk_i, -- [in std_logic]
Trace_Reset => trace_reset, -- [in std_logic]
Trace_Test_Pattern => trace_test_pattern, -- [out std_logic_vector(0 to 3)]
Trace_Test_Start => trace_test_start, -- [out std_logic]
Trace_Test_Stop => trace_test_stop, -- [out std_logic]
Trace_Test_Timed => trace_test_timed, -- [out std_logic]
Trace_Delay => trace_delay, -- [out std_logic_vector(0 to 7)]
Trace_Stopped => trace_stopped -- [out std_logic]
);
-----------------------------------------------------------------------------
-- Enables for each debug port
-----------------------------------------------------------------------------
Generate_Dbg_Port_Signals : process (mb_debug_enabled_i, Debug_Rst_I, disable)
begin -- process Generate_Dbg_Port_Signals
for I in 0 to C_EN_WIDTH-1 loop
if (mb_debug_enabled_i(I) = '1') then
Dbg_Rst_I(I) <= Debug_Rst_i;
else
Dbg_Rst_I(I) <= '0';
end if;
Dbg_Disable(I) <= disable;
end loop; -- I
for I in C_EN_WIDTH to 31 loop
Dbg_Rst_I(I) <= '0';
Dbg_Disable(I) <= '1';
end loop; -- I
end process Generate_Dbg_Port_Signals;
Debug_SYS_Rst <= Debug_SYS_Rst_i;
MB_Debug_Enabled <= mb_debug_enabled_i;
Dbg_Disable_0 <= Dbg_Disable(0);
Dbg_Rst_0 <= Dbg_Rst_I(0);
Dbg_TrClk_0 <= Dbg_TrClk;
Dbg_TrReady_0 <= Dbg_TrReady(0);
Dbg_Disable_1 <= Dbg_Disable(1);
Dbg_Rst_1 <= Dbg_Rst_I(1);
Dbg_TrClk_1 <= Dbg_TrClk;
Dbg_TrReady_1 <= Dbg_TrReady(1);
Dbg_Disable_2 <= Dbg_Disable(2);
Dbg_Rst_2 <= Dbg_Rst_I(2);
Dbg_TrClk_2 <= Dbg_TrClk;
Dbg_TrReady_2 <= Dbg_TrReady(2);
Dbg_Disable_3 <= Dbg_Disable(3);
Dbg_Rst_3 <= Dbg_Rst_I(3);
Dbg_TrClk_3 <= Dbg_TrClk;
Dbg_TrReady_3 <= Dbg_TrReady(3);
Dbg_Disable_4 <= Dbg_Disable(4);
Dbg_Rst_4 <= Dbg_Rst_I(4);
Dbg_TrClk_4 <= Dbg_TrClk;
Dbg_TrReady_4 <= Dbg_TrReady(4);
Dbg_Disable_5 <= Dbg_Disable(5);
Dbg_Rst_5 <= Dbg_Rst_I(5);
Dbg_TrClk_5 <= Dbg_TrClk;
Dbg_TrReady_5 <= Dbg_TrReady(5);
Dbg_Disable_6 <= Dbg_Disable(6);
Dbg_Rst_6 <= Dbg_Rst_I(6);
Dbg_TrClk_6 <= Dbg_TrClk;
Dbg_TrReady_6 <= Dbg_TrReady(6);
Dbg_Disable_7 <= Dbg_Disable(7);
Dbg_Rst_7 <= Dbg_Rst_I(7);
Dbg_TrClk_7 <= Dbg_TrClk;
Dbg_TrReady_7 <= Dbg_TrReady(7);
Dbg_Disable_8 <= Dbg_Disable(8);
Dbg_Rst_8 <= Dbg_Rst_I(8);
Dbg_TrClk_8 <= Dbg_TrClk;
Dbg_TrReady_8 <= Dbg_TrReady(8);
Dbg_Disable_9 <= Dbg_Disable(9);
Dbg_Rst_9 <= Dbg_Rst_I(9);
Dbg_TrClk_9 <= Dbg_TrClk;
Dbg_TrReady_9 <= Dbg_TrReady(9);
Dbg_Disable_10 <= Dbg_Disable(10);
Dbg_Rst_10 <= Dbg_Rst_I(10);
Dbg_TrClk_10 <= Dbg_TrClk;
Dbg_TrReady_10 <= Dbg_TrReady(10);
Dbg_Disable_11 <= Dbg_Disable(11);
Dbg_Rst_11 <= Dbg_Rst_I(11);
Dbg_TrClk_11 <= Dbg_TrClk;
Dbg_TrReady_11 <= Dbg_TrReady(11);
Dbg_Disable_12 <= Dbg_Disable(12);
Dbg_Rst_12 <= Dbg_Rst_I(12);
Dbg_TrClk_12 <= Dbg_TrClk;
Dbg_TrReady_12 <= Dbg_TrReady(12);
Dbg_Disable_13 <= Dbg_Disable(13);
Dbg_Rst_13 <= Dbg_Rst_I(13);
Dbg_TrClk_13 <= Dbg_TrClk;
Dbg_TrReady_13 <= Dbg_TrReady(13);
Dbg_Disable_14 <= Dbg_Disable(14);
Dbg_Rst_14 <= Dbg_Rst_I(14);
Dbg_TrClk_14 <= Dbg_TrClk;
Dbg_TrReady_14 <= Dbg_TrReady(14);
Dbg_Disable_15 <= Dbg_Disable(15);
Dbg_Rst_15 <= Dbg_Rst_I(15);
Dbg_TrClk_15 <= Dbg_TrClk;
Dbg_TrReady_15 <= Dbg_TrReady(15);
Dbg_Disable_16 <= Dbg_Disable(16);
Dbg_Rst_16 <= Dbg_Rst_I(16);
Dbg_TrClk_16 <= Dbg_TrClk;
Dbg_TrReady_16 <= Dbg_TrReady(16);
Dbg_Disable_17 <= Dbg_Disable(17);
Dbg_Rst_17 <= Dbg_Rst_I(17);
Dbg_TrClk_17 <= Dbg_TrClk;
Dbg_TrReady_17 <= Dbg_TrReady(17);
Dbg_Disable_18 <= Dbg_Disable(18);
Dbg_Rst_18 <= Dbg_Rst_I(18);
Dbg_TrClk_18 <= Dbg_TrClk;
Dbg_TrReady_18 <= Dbg_TrReady(18);
Dbg_Disable_19 <= Dbg_Disable(19);
Dbg_Rst_19 <= Dbg_Rst_I(19);
Dbg_TrClk_19 <= Dbg_TrClk;
Dbg_TrReady_19 <= Dbg_TrReady(19);
Dbg_Disable_20 <= Dbg_Disable(20);
Dbg_Rst_20 <= Dbg_Rst_I(20);
Dbg_TrClk_20 <= Dbg_TrClk;
Dbg_TrReady_20 <= Dbg_TrReady(20);
Dbg_Disable_21 <= Dbg_Disable(21);
Dbg_Rst_21 <= Dbg_Rst_I(21);
Dbg_TrClk_21 <= Dbg_TrClk;
Dbg_TrReady_21 <= Dbg_TrReady(21);
Dbg_Disable_22 <= Dbg_Disable(22);
Dbg_Rst_22 <= Dbg_Rst_I(22);
Dbg_TrClk_22 <= Dbg_TrClk;
Dbg_TrReady_22 <= Dbg_TrReady(22);
Dbg_Disable_23 <= Dbg_Disable(23);
Dbg_Rst_23 <= Dbg_Rst_I(23);
Dbg_TrClk_23 <= Dbg_TrClk;
Dbg_TrReady_23 <= Dbg_TrReady(23);
Dbg_Disable_24 <= Dbg_Disable(24);
Dbg_Rst_24 <= Dbg_Rst_I(24);
Dbg_TrClk_24 <= Dbg_TrClk;
Dbg_TrReady_24 <= Dbg_TrReady(24);
Dbg_Disable_25 <= Dbg_Disable(25);
Dbg_Rst_25 <= Dbg_Rst_I(25);
Dbg_TrClk_25 <= Dbg_TrClk;
Dbg_TrReady_25 <= Dbg_TrReady(25);
Dbg_Disable_26 <= Dbg_Disable(26);
Dbg_Rst_26 <= Dbg_Rst_I(26);
Dbg_TrClk_26 <= Dbg_TrClk;
Dbg_TrReady_26 <= Dbg_TrReady(26);
Dbg_Disable_27 <= Dbg_Disable(27);
Dbg_Rst_27 <= Dbg_Rst_I(27);
Dbg_TrClk_27 <= Dbg_TrClk;
Dbg_TrReady_27 <= Dbg_TrReady(27);
Dbg_Disable_28 <= Dbg_Disable(28);
Dbg_Rst_28 <= Dbg_Rst_I(28);
Dbg_TrClk_28 <= Dbg_TrClk;
Dbg_TrReady_28 <= Dbg_TrReady(28);
Dbg_Disable_29 <= Dbg_Disable(29);
Dbg_Rst_29 <= Dbg_Rst_I(29);
Dbg_TrClk_29 <= Dbg_TrClk;
Dbg_TrReady_29 <= Dbg_TrReady(29);
Dbg_Disable_30 <= Dbg_Disable(30);
Dbg_Rst_30 <= Dbg_Rst_I(30);
Dbg_TrClk_30 <= Dbg_TrClk;
Dbg_TrReady_30 <= Dbg_TrReady(30);
Dbg_Disable_31 <= Dbg_Disable(31);
Dbg_Rst_31 <= Dbg_Rst_I(31);
Dbg_TrClk_31 <= Dbg_TrClk;
Dbg_TrReady_31 <= Dbg_TrReady(31);
Use_Serial : if C_DEBUG_INTERFACE = 0 generate
begin
Generate_Dbg_Port_Signals : process (mb_debug_enabled_i, Dbg_Reg_En, Dbg_TDO_I)
variable dbg_tdo_or : std_logic;
begin -- process Generate_Dbg_Port_Signals
dbg_tdo_or := '0';
for I in 0 to C_EN_WIDTH-1 loop
if (mb_debug_enabled_i(I) = '1') then
Dbg_Reg_En_I(I) <= Dbg_Reg_En;
else
Dbg_Reg_En_I(I) <= (others => '0');
end if;
dbg_tdo_or := dbg_tdo_or or Dbg_TDO_I(I);
end loop; -- I
for I in C_EN_WIDTH to 31 loop
Dbg_Reg_En_I(I) <= (others => '0');
end loop; -- I
Dbg_TDO <= dbg_tdo_or;
end process Generate_Dbg_Port_Signals;
Dbg_Disable_0 <= Dbg_Disable(0);
Dbg_Clk_0 <= Dbg_Clk;
Dbg_TDI_0 <= Dbg_TDI;
Dbg_Reg_En_0 <= Dbg_Reg_En_I(0);
Dbg_Capture_0 <= Dbg_Capture;
Dbg_Shift_0 <= Dbg_Shift;
Dbg_Update_0 <= Dbg_Update;
Dbg_Rst_0 <= Dbg_Rst_I(0);
Dbg_TDO_I(0) <= Dbg_TDO_0;
Dbg_TrClk_0 <= Dbg_TrClk;
Dbg_TrReady_0 <= Dbg_TrReady(0);
Dbg_Disable_1 <= Dbg_Disable(1);
Dbg_Clk_1 <= Dbg_Clk;
Dbg_TDI_1 <= Dbg_TDI;
Dbg_Reg_En_1 <= Dbg_Reg_En_I(1);
Dbg_Capture_1 <= Dbg_Capture;
Dbg_Shift_1 <= Dbg_Shift;
Dbg_Update_1 <= Dbg_Update;
Dbg_Rst_1 <= Dbg_Rst_I(1);
Dbg_TDO_I(1) <= Dbg_TDO_1;
Dbg_TrClk_1 <= Dbg_TrClk;
Dbg_TrReady_1 <= Dbg_TrReady(1);
Dbg_Disable_2 <= Dbg_Disable(2);
Dbg_Clk_2 <= Dbg_Clk;
Dbg_TDI_2 <= Dbg_TDI;
Dbg_Reg_En_2 <= Dbg_Reg_En_I(2);
Dbg_Capture_2 <= Dbg_Capture;
Dbg_Shift_2 <= Dbg_Shift;
Dbg_Update_2 <= Dbg_Update;
Dbg_Rst_2 <= Dbg_Rst_I(2);
Dbg_TDO_I(2) <= Dbg_TDO_2;
Dbg_TrClk_2 <= Dbg_TrClk;
Dbg_TrReady_2 <= Dbg_TrReady(2);
Dbg_Disable_3 <= Dbg_Disable(3);
Dbg_Clk_3 <= Dbg_Clk;
Dbg_TDI_3 <= Dbg_TDI;
Dbg_Reg_En_3 <= Dbg_Reg_En_I(3);
Dbg_Capture_3 <= Dbg_Capture;
Dbg_Shift_3 <= Dbg_Shift;
Dbg_Update_3 <= Dbg_Update;
Dbg_Rst_3 <= Dbg_Rst_I(3);
Dbg_TDO_I(3) <= Dbg_TDO_3;
Dbg_TrClk_3 <= Dbg_TrClk;
Dbg_TrReady_3 <= Dbg_TrReady(3);
Dbg_Disable_4 <= Dbg_Disable(4);
Dbg_Clk_4 <= Dbg_Clk;
Dbg_TDI_4 <= Dbg_TDI;
Dbg_Reg_En_4 <= Dbg_Reg_En_I(4);
Dbg_Capture_4 <= Dbg_Capture;
Dbg_Shift_4 <= Dbg_Shift;
Dbg_Update_4 <= Dbg_Update;
Dbg_Rst_4 <= Dbg_Rst_I(4);
Dbg_TDO_I(4) <= Dbg_TDO_4;
Dbg_TrClk_4 <= Dbg_TrClk;
Dbg_TrReady_4 <= Dbg_TrReady(4);
Dbg_Disable_5 <= Dbg_Disable(5);
Dbg_Clk_5 <= Dbg_Clk;
Dbg_TDI_5 <= Dbg_TDI;
Dbg_Reg_En_5 <= Dbg_Reg_En_I(5);
Dbg_Capture_5 <= Dbg_Capture;
Dbg_Shift_5 <= Dbg_Shift;
Dbg_Update_5 <= Dbg_Update;
Dbg_Rst_5 <= Dbg_Rst_I(5);
Dbg_TDO_I(5) <= Dbg_TDO_5;
Dbg_TrClk_5 <= Dbg_TrClk;
Dbg_TrReady_5 <= Dbg_TrReady(5);
Dbg_Disable_6 <= Dbg_Disable(6);
Dbg_Clk_6 <= Dbg_Clk;
Dbg_TDI_6 <= Dbg_TDI;
Dbg_Reg_En_6 <= Dbg_Reg_En_I(6);
Dbg_Capture_6 <= Dbg_Capture;
Dbg_Shift_6 <= Dbg_Shift;
Dbg_Update_6 <= Dbg_Update;
Dbg_Rst_6 <= Dbg_Rst_I(6);
Dbg_TDO_I(6) <= Dbg_TDO_6;
Dbg_TrClk_6 <= Dbg_TrClk;
Dbg_TrReady_6 <= Dbg_TrReady(6);
Dbg_Disable_7 <= Dbg_Disable(7);
Dbg_Clk_7 <= Dbg_Clk;
Dbg_TDI_7 <= Dbg_TDI;
Dbg_Reg_En_7 <= Dbg_Reg_En_I(7);
Dbg_Capture_7 <= Dbg_Capture;
Dbg_Shift_7 <= Dbg_Shift;
Dbg_Update_7 <= Dbg_Update;
Dbg_Rst_7 <= Dbg_Rst_I(7);
Dbg_TDO_I(7) <= Dbg_TDO_7;
Dbg_TrClk_7 <= Dbg_TrClk;
Dbg_TrReady_7 <= Dbg_TrReady(7);
Dbg_Disable_8 <= Dbg_Disable(8);
Dbg_Clk_8 <= Dbg_Clk;
Dbg_TDI_8 <= Dbg_TDI;
Dbg_Reg_En_8 <= Dbg_Reg_En_I(8);
Dbg_Capture_8 <= Dbg_Capture;
Dbg_Shift_8 <= Dbg_Shift;
Dbg_Update_8 <= Dbg_Update;
Dbg_Rst_8 <= Dbg_Rst_I(8);
Dbg_TDO_I(8) <= Dbg_TDO_8;
Dbg_TrClk_8 <= Dbg_TrClk;
Dbg_TrReady_8 <= Dbg_TrReady(8);
Dbg_Disable_9 <= Dbg_Disable(9);
Dbg_Clk_9 <= Dbg_Clk;
Dbg_TDI_9 <= Dbg_TDI;
Dbg_Reg_En_9 <= Dbg_Reg_En_I(9);
Dbg_Capture_9 <= Dbg_Capture;
Dbg_Shift_9 <= Dbg_Shift;
Dbg_Update_9 <= Dbg_Update;
Dbg_Rst_9 <= Dbg_Rst_I(9);
Dbg_TDO_I(9) <= Dbg_TDO_9;
Dbg_TrClk_9 <= Dbg_TrClk;
Dbg_TrReady_9 <= Dbg_TrReady(9);
Dbg_Disable_10 <= Dbg_Disable(10);
Dbg_Clk_10 <= Dbg_Clk;
Dbg_TDI_10 <= Dbg_TDI;
Dbg_Reg_En_10 <= Dbg_Reg_En_I(10);
Dbg_Capture_10 <= Dbg_Capture;
Dbg_Shift_10 <= Dbg_Shift;
Dbg_Update_10 <= Dbg_Update;
Dbg_Rst_10 <= Dbg_Rst_I(10);
Dbg_TDO_I(10) <= Dbg_TDO_10;
Dbg_TrClk_10 <= Dbg_TrClk;
Dbg_TrReady_10 <= Dbg_TrReady(10);
Dbg_Disable_11 <= Dbg_Disable(11);
Dbg_Clk_11 <= Dbg_Clk;
Dbg_TDI_11 <= Dbg_TDI;
Dbg_Reg_En_11 <= Dbg_Reg_En_I(11);
Dbg_Capture_11 <= Dbg_Capture;
Dbg_Shift_11 <= Dbg_Shift;
Dbg_Update_11 <= Dbg_Update;
Dbg_Rst_11 <= Dbg_Rst_I(11);
Dbg_TDO_I(11) <= Dbg_TDO_11;
Dbg_TrClk_11 <= Dbg_TrClk;
Dbg_TrReady_11 <= Dbg_TrReady(11);
Dbg_Disable_12 <= Dbg_Disable(12);
Dbg_Clk_12 <= Dbg_Clk;
Dbg_TDI_12 <= Dbg_TDI;
Dbg_Reg_En_12 <= Dbg_Reg_En_I(12);
Dbg_Capture_12 <= Dbg_Capture;
Dbg_Shift_12 <= Dbg_Shift;
Dbg_Update_12 <= Dbg_Update;
Dbg_Rst_12 <= Dbg_Rst_I(12);
Dbg_TDO_I(12) <= Dbg_TDO_12;
Dbg_TrClk_12 <= Dbg_TrClk;
Dbg_TrReady_12 <= Dbg_TrReady(12);
Dbg_Disable_13 <= Dbg_Disable(13);
Dbg_Clk_13 <= Dbg_Clk;
Dbg_TDI_13 <= Dbg_TDI;
Dbg_Reg_En_13 <= Dbg_Reg_En_I(13);
Dbg_Capture_13 <= Dbg_Capture;
Dbg_Shift_13 <= Dbg_Shift;
Dbg_Update_13 <= Dbg_Update;
Dbg_Rst_13 <= Dbg_Rst_I(13);
Dbg_TDO_I(13) <= Dbg_TDO_13;
Dbg_TrClk_13 <= Dbg_TrClk;
Dbg_TrReady_13 <= Dbg_TrReady(13);
Dbg_Disable_14 <= Dbg_Disable(14);
Dbg_Clk_14 <= Dbg_Clk;
Dbg_TDI_14 <= Dbg_TDI;
Dbg_Reg_En_14 <= Dbg_Reg_En_I(14);
Dbg_Capture_14 <= Dbg_Capture;
Dbg_Shift_14 <= Dbg_Shift;
Dbg_Update_14 <= Dbg_Update;
Dbg_Rst_14 <= Dbg_Rst_I(14);
Dbg_TDO_I(14) <= Dbg_TDO_14;
Dbg_TrClk_14 <= Dbg_TrClk;
Dbg_TrReady_14 <= Dbg_TrReady(14);
Dbg_Disable_15 <= Dbg_Disable(15);
Dbg_Clk_15 <= Dbg_Clk;
Dbg_TDI_15 <= Dbg_TDI;
Dbg_Reg_En_15 <= Dbg_Reg_En_I(15);
Dbg_Capture_15 <= Dbg_Capture;
Dbg_Shift_15 <= Dbg_Shift;
Dbg_Update_15 <= Dbg_Update;
Dbg_Rst_15 <= Dbg_Rst_I(15);
Dbg_TDO_I(15) <= Dbg_TDO_15;
Dbg_TrClk_15 <= Dbg_TrClk;
Dbg_TrReady_15 <= Dbg_TrReady(15);
Dbg_Disable_16 <= Dbg_Disable(16);
Dbg_Clk_16 <= Dbg_Clk;
Dbg_TDI_16 <= Dbg_TDI;
Dbg_Reg_En_16 <= Dbg_Reg_En_I(16);
Dbg_Capture_16 <= Dbg_Capture;
Dbg_Shift_16 <= Dbg_Shift;
Dbg_Update_16 <= Dbg_Update;
Dbg_Rst_16 <= Dbg_Rst_I(16);
Dbg_TDO_I(16) <= Dbg_TDO_16;
Dbg_TrClk_16 <= Dbg_TrClk;
Dbg_TrReady_16 <= Dbg_TrReady(16);
Dbg_Disable_17 <= Dbg_Disable(17);
Dbg_Clk_17 <= Dbg_Clk;
Dbg_TDI_17 <= Dbg_TDI;
Dbg_Reg_En_17 <= Dbg_Reg_En_I(17);
Dbg_Capture_17 <= Dbg_Capture;
Dbg_Shift_17 <= Dbg_Shift;
Dbg_Update_17 <= Dbg_Update;
Dbg_Rst_17 <= Dbg_Rst_I(17);
Dbg_TDO_I(17) <= Dbg_TDO_17;
Dbg_TrClk_17 <= Dbg_TrClk;
Dbg_TrReady_17 <= Dbg_TrReady(17);
Dbg_Disable_18 <= Dbg_Disable(18);
Dbg_Clk_18 <= Dbg_Clk;
Dbg_TDI_18 <= Dbg_TDI;
Dbg_Reg_En_18 <= Dbg_Reg_En_I(18);
Dbg_Capture_18 <= Dbg_Capture;
Dbg_Shift_18 <= Dbg_Shift;
Dbg_Update_18 <= Dbg_Update;
Dbg_Rst_18 <= Dbg_Rst_I(18);
Dbg_TDO_I(18) <= Dbg_TDO_18;
Dbg_TrClk_18 <= Dbg_TrClk;
Dbg_TrReady_18 <= Dbg_TrReady(18);
Dbg_Disable_19 <= Dbg_Disable(19);
Dbg_Clk_19 <= Dbg_Clk;
Dbg_TDI_19 <= Dbg_TDI;
Dbg_Reg_En_19 <= Dbg_Reg_En_I(19);
Dbg_Capture_19 <= Dbg_Capture;
Dbg_Shift_19 <= Dbg_Shift;
Dbg_Update_19 <= Dbg_Update;
Dbg_Rst_19 <= Dbg_Rst_I(19);
Dbg_TDO_I(19) <= Dbg_TDO_19;
Dbg_TrClk_19 <= Dbg_TrClk;
Dbg_TrReady_19 <= Dbg_TrReady(19);
Dbg_Disable_20 <= Dbg_Disable(20);
Dbg_Clk_20 <= Dbg_Clk;
Dbg_TDI_20 <= Dbg_TDI;
Dbg_Reg_En_20 <= Dbg_Reg_En_I(20);
Dbg_Capture_20 <= Dbg_Capture;
Dbg_Shift_20 <= Dbg_Shift;
Dbg_Update_20 <= Dbg_Update;
Dbg_Rst_20 <= Dbg_Rst_I(20);
Dbg_TDO_I(20) <= Dbg_TDO_20;
Dbg_TrClk_20 <= Dbg_TrClk;
Dbg_TrReady_20 <= Dbg_TrReady(20);
Dbg_Disable_21 <= Dbg_Disable(21);
Dbg_Clk_21 <= Dbg_Clk;
Dbg_TDI_21 <= Dbg_TDI;
Dbg_Reg_En_21 <= Dbg_Reg_En_I(21);
Dbg_Capture_21 <= Dbg_Capture;
Dbg_Shift_21 <= Dbg_Shift;
Dbg_Update_21 <= Dbg_Update;
Dbg_Rst_21 <= Dbg_Rst_I(21);
Dbg_TDO_I(21) <= Dbg_TDO_21;
Dbg_TrClk_21 <= Dbg_TrClk;
Dbg_TrReady_21 <= Dbg_TrReady(21);
Dbg_Disable_22 <= Dbg_Disable(22);
Dbg_Clk_22 <= Dbg_Clk;
Dbg_TDI_22 <= Dbg_TDI;
Dbg_Reg_En_22 <= Dbg_Reg_En_I(22);
Dbg_Capture_22 <= Dbg_Capture;
Dbg_Shift_22 <= Dbg_Shift;
Dbg_Update_22 <= Dbg_Update;
Dbg_Rst_22 <= Dbg_Rst_I(22);
Dbg_TDO_I(22) <= Dbg_TDO_22;
Dbg_TrClk_22 <= Dbg_TrClk;
Dbg_TrReady_22 <= Dbg_TrReady(22);
Dbg_Disable_23 <= Dbg_Disable(23);
Dbg_Clk_23 <= Dbg_Clk;
Dbg_TDI_23 <= Dbg_TDI;
Dbg_Reg_En_23 <= Dbg_Reg_En_I(23);
Dbg_Capture_23 <= Dbg_Capture;
Dbg_Shift_23 <= Dbg_Shift;
Dbg_Update_23 <= Dbg_Update;
Dbg_Rst_23 <= Dbg_Rst_I(23);
Dbg_TDO_I(23) <= Dbg_TDO_23;
Dbg_TrClk_23 <= Dbg_TrClk;
Dbg_TrReady_23 <= Dbg_TrReady(23);
Dbg_Disable_24 <= Dbg_Disable(24);
Dbg_Clk_24 <= Dbg_Clk;
Dbg_TDI_24 <= Dbg_TDI;
Dbg_Reg_En_24 <= Dbg_Reg_En_I(24);
Dbg_Capture_24 <= Dbg_Capture;
Dbg_Shift_24 <= Dbg_Shift;
Dbg_Update_24 <= Dbg_Update;
Dbg_Rst_24 <= Dbg_Rst_I(24);
Dbg_TDO_I(24) <= Dbg_TDO_24;
Dbg_TrClk_24 <= Dbg_TrClk;
Dbg_TrReady_24 <= Dbg_TrReady(24);
Dbg_Disable_25 <= Dbg_Disable(25);
Dbg_Clk_25 <= Dbg_Clk;
Dbg_TDI_25 <= Dbg_TDI;
Dbg_Reg_En_25 <= Dbg_Reg_En_I(25);
Dbg_Capture_25 <= Dbg_Capture;
Dbg_Shift_25 <= Dbg_Shift;
Dbg_Update_25 <= Dbg_Update;
Dbg_Rst_25 <= Dbg_Rst_I(25);
Dbg_TDO_I(25) <= Dbg_TDO_25;
Dbg_TrClk_25 <= Dbg_TrClk;
Dbg_TrReady_25 <= Dbg_TrReady(25);
Dbg_Disable_26 <= Dbg_Disable(26);
Dbg_Clk_26 <= Dbg_Clk;
Dbg_TDI_26 <= Dbg_TDI;
Dbg_Reg_En_26 <= Dbg_Reg_En_I(26);
Dbg_Capture_26 <= Dbg_Capture;
Dbg_Shift_26 <= Dbg_Shift;
Dbg_Update_26 <= Dbg_Update;
Dbg_Rst_26 <= Dbg_Rst_I(26);
Dbg_TDO_I(26) <= Dbg_TDO_26;
Dbg_TrClk_26 <= Dbg_TrClk;
Dbg_TrReady_26 <= Dbg_TrReady(26);
Dbg_Disable_27 <= Dbg_Disable(27);
Dbg_Clk_27 <= Dbg_Clk;
Dbg_TDI_27 <= Dbg_TDI;
Dbg_Reg_En_27 <= Dbg_Reg_En_I(27);
Dbg_Capture_27 <= Dbg_Capture;
Dbg_Shift_27 <= Dbg_Shift;
Dbg_Update_27 <= Dbg_Update;
Dbg_Rst_27 <= Dbg_Rst_I(27);
Dbg_TDO_I(27) <= Dbg_TDO_27;
Dbg_TrClk_27 <= Dbg_TrClk;
Dbg_TrReady_27 <= Dbg_TrReady(27);
Dbg_Disable_28 <= Dbg_Disable(28);
Dbg_Clk_28 <= Dbg_Clk;
Dbg_TDI_28 <= Dbg_TDI;
Dbg_Reg_En_28 <= Dbg_Reg_En_I(28);
Dbg_Capture_28 <= Dbg_Capture;
Dbg_Shift_28 <= Dbg_Shift;
Dbg_Update_28 <= Dbg_Update;
Dbg_Rst_28 <= Dbg_Rst_I(28);
Dbg_TDO_I(28) <= Dbg_TDO_28;
Dbg_TrClk_28 <= Dbg_TrClk;
Dbg_TrReady_28 <= Dbg_TrReady(28);
Dbg_Disable_29 <= Dbg_Disable(29);
Dbg_Clk_29 <= Dbg_Clk;
Dbg_TDI_29 <= Dbg_TDI;
Dbg_Reg_En_29 <= Dbg_Reg_En_I(29);
Dbg_Capture_29 <= Dbg_Capture;
Dbg_Shift_29 <= Dbg_Shift;
Dbg_Update_29 <= Dbg_Update;
Dbg_Rst_29 <= Dbg_Rst_I(29);
Dbg_TDO_I(29) <= Dbg_TDO_29;
Dbg_TrClk_29 <= Dbg_TrClk;
Dbg_TrReady_29 <= Dbg_TrReady(29);
Dbg_Disable_30 <= Dbg_Disable(30);
Dbg_Clk_30 <= Dbg_Clk;
Dbg_TDI_30 <= Dbg_TDI;
Dbg_Reg_En_30 <= Dbg_Reg_En_I(30);
Dbg_Capture_30 <= Dbg_Capture;
Dbg_Shift_30 <= Dbg_Shift;
Dbg_Update_30 <= Dbg_Update;
Dbg_Rst_30 <= Dbg_Rst_I(30);
Dbg_TDO_I(30) <= Dbg_TDO_30;
Dbg_TrClk_30 <= Dbg_TrClk;
Dbg_TrReady_30 <= Dbg_TrReady(30);
Dbg_Disable_31 <= Dbg_Disable(31);
Dbg_Clk_31 <= Dbg_Clk;
Dbg_TDI_31 <= Dbg_TDI;
Dbg_Reg_En_31 <= Dbg_Reg_En_I(31);
Dbg_Capture_31 <= Dbg_Capture;
Dbg_Shift_31 <= Dbg_Shift;
Dbg_Update_31 <= Dbg_Update;
Dbg_Rst_31 <= Dbg_Rst_I(31);
Dbg_TDO_I(31) <= Dbg_TDO_31;
Dbg_TrClk_31 <= Dbg_TrClk;
Dbg_TrReady_31 <= Dbg_TrReady(31);
-- Unused parallel signals
Dbg_BRESP <= '0';
Dbg_BVALID <= '0';
Dbg_RDATA <= (others => '0');
Dbg_RRESP <= '0';
Dbg_RVALID <= '0';
Dbg_AWADDR_0 <= (others => '0');
Dbg_AWVALID_0 <= '0';
Dbg_AWREADY_I(0) <= '0';
Dbg_WDATA_0 <= (others => '0');
Dbg_WVALID_0 <= '0';
Dbg_WREADY_I(0) <= '0';
Dbg_BRESP_I(0) <= (others => '0');
Dbg_BVALID_I(0) <= '0';
Dbg_BREADY_0 <= '0';
Dbg_ARADDR_0 <= (others => '0');
Dbg_ARVALID_0 <= '0';
Dbg_ARREADY_I(0) <= '0';
Dbg_RDATA_I(0) <= (others => '0');
Dbg_RRESP_I(0) <= (others => '0');
Dbg_RVALID_I(0) <= '0';
Dbg_RREADY_0 <= '0';
Dbg_AWADDR_1 <= (others => '0');
Dbg_AWVALID_1 <= '0';
Dbg_AWREADY_I(1) <= '0';
Dbg_WDATA_1 <= (others => '0');
Dbg_WVALID_1 <= '0';
Dbg_WREADY_I(1) <= '0';
Dbg_BRESP_I(1) <= (others => '0');
Dbg_BVALID_I(1) <= '0';
Dbg_BREADY_1 <= '0';
Dbg_ARADDR_1 <= (others => '0');
Dbg_ARVALID_1 <= '0';
Dbg_ARREADY_I(1) <= '0';
Dbg_RDATA_I(1) <= (others => '0');
Dbg_RRESP_I(1) <= (others => '0');
Dbg_RVALID_I(1) <= '0';
Dbg_RREADY_1 <= '0';
Dbg_AWADDR_2 <= (others => '0');
Dbg_AWVALID_2 <= '0';
Dbg_AWREADY_I(2) <= '0';
Dbg_WDATA_2 <= (others => '0');
Dbg_WVALID_2 <= '0';
Dbg_WREADY_I(2) <= '0';
Dbg_BRESP_I(2) <= (others => '0');
Dbg_BVALID_I(2) <= '0';
Dbg_BREADY_2 <= '0';
Dbg_ARADDR_2 <= (others => '0');
Dbg_ARVALID_2 <= '0';
Dbg_ARREADY_I(2) <= '0';
Dbg_RDATA_I(2) <= (others => '0');
Dbg_RRESP_I(2) <= (others => '0');
Dbg_RVALID_I(2) <= '0';
Dbg_RREADY_2 <= '0';
Dbg_AWADDR_3 <= (others => '0');
Dbg_AWVALID_3 <= '0';
Dbg_AWREADY_I(3) <= '0';
Dbg_WDATA_3 <= (others => '0');
Dbg_WVALID_3 <= '0';
Dbg_WREADY_I(3) <= '0';
Dbg_BRESP_I(3) <= (others => '0');
Dbg_BVALID_I(3) <= '0';
Dbg_BREADY_3 <= '0';
Dbg_ARADDR_3 <= (others => '0');
Dbg_ARVALID_3 <= '0';
Dbg_ARREADY_I(3) <= '0';
Dbg_RDATA_I(3) <= (others => '0');
Dbg_RRESP_I(3) <= (others => '0');
Dbg_RVALID_I(3) <= '0';
Dbg_RREADY_3 <= '0';
Dbg_AWADDR_4 <= (others => '0');
Dbg_AWVALID_4 <= '0';
Dbg_AWREADY_I(4) <= '0';
Dbg_WDATA_4 <= (others => '0');
Dbg_WVALID_4 <= '0';
Dbg_WREADY_I(4) <= '0';
Dbg_BRESP_I(4) <= (others => '0');
Dbg_BVALID_I(4) <= '0';
Dbg_BREADY_4 <= '0';
Dbg_ARADDR_4 <= (others => '0');
Dbg_ARVALID_4 <= '0';
Dbg_ARREADY_I(4) <= '0';
Dbg_RDATA_I(4) <= (others => '0');
Dbg_RRESP_I(4) <= (others => '0');
Dbg_RVALID_I(4) <= '0';
Dbg_RREADY_4 <= '0';
Dbg_AWADDR_5 <= (others => '0');
Dbg_AWVALID_5 <= '0';
Dbg_AWREADY_I(5) <= '0';
Dbg_WDATA_5 <= (others => '0');
Dbg_WVALID_5 <= '0';
Dbg_WREADY_I(5) <= '0';
Dbg_BRESP_I(5) <= (others => '0');
Dbg_BVALID_I(5) <= '0';
Dbg_BREADY_5 <= '0';
Dbg_ARADDR_5 <= (others => '0');
Dbg_ARVALID_5 <= '0';
Dbg_ARREADY_I(5) <= '0';
Dbg_RDATA_I(5) <= (others => '0');
Dbg_RRESP_I(5) <= (others => '0');
Dbg_RVALID_I(5) <= '0';
Dbg_RREADY_5 <= '0';
Dbg_AWADDR_6 <= (others => '0');
Dbg_AWVALID_6 <= '0';
Dbg_AWREADY_I(6) <= '0';
Dbg_WDATA_6 <= (others => '0');
Dbg_WVALID_6 <= '0';
Dbg_WREADY_I(6) <= '0';
Dbg_BRESP_I(6) <= (others => '0');
Dbg_BVALID_I(6) <= '0';
Dbg_BREADY_6 <= '0';
Dbg_ARADDR_6 <= (others => '0');
Dbg_ARVALID_6 <= '0';
Dbg_ARREADY_I(6) <= '0';
Dbg_RDATA_I(6) <= (others => '0');
Dbg_RRESP_I(6) <= (others => '0');
Dbg_RVALID_I(6) <= '0';
Dbg_RREADY_6 <= '0';
Dbg_AWADDR_7 <= (others => '0');
Dbg_AWVALID_7 <= '0';
Dbg_AWREADY_I(7) <= '0';
Dbg_WDATA_7 <= (others => '0');
Dbg_WVALID_7 <= '0';
Dbg_WREADY_I(7) <= '0';
Dbg_BRESP_I(7) <= (others => '0');
Dbg_BVALID_I(7) <= '0';
Dbg_BREADY_7 <= '0';
Dbg_ARADDR_7 <= (others => '0');
Dbg_ARVALID_7 <= '0';
Dbg_ARREADY_I(7) <= '0';
Dbg_RDATA_I(7) <= (others => '0');
Dbg_RRESP_I(7) <= (others => '0');
Dbg_RVALID_I(7) <= '0';
Dbg_RREADY_7 <= '0';
Dbg_AWADDR_8 <= (others => '0');
Dbg_AWVALID_8 <= '0';
Dbg_AWREADY_I(8) <= '0';
Dbg_WDATA_8 <= (others => '0');
Dbg_WVALID_8 <= '0';
Dbg_WREADY_I(8) <= '0';
Dbg_BRESP_I(8) <= (others => '0');
Dbg_BVALID_I(8) <= '0';
Dbg_BREADY_8 <= '0';
Dbg_ARADDR_8 <= (others => '0');
Dbg_ARVALID_8 <= '0';
Dbg_ARREADY_I(8) <= '0';
Dbg_RDATA_I(8) <= (others => '0');
Dbg_RRESP_I(8) <= (others => '0');
Dbg_RVALID_I(8) <= '0';
Dbg_RREADY_8 <= '0';
Dbg_AWADDR_9 <= (others => '0');
Dbg_AWVALID_9 <= '0';
Dbg_AWREADY_I(9) <= '0';
Dbg_WDATA_9 <= (others => '0');
Dbg_WVALID_9 <= '0';
Dbg_WREADY_I(9) <= '0';
Dbg_BRESP_I(9) <= (others => '0');
Dbg_BVALID_I(9) <= '0';
Dbg_BREADY_9 <= '0';
Dbg_ARADDR_9 <= (others => '0');
Dbg_ARVALID_9 <= '0';
Dbg_ARREADY_I(9) <= '0';
Dbg_RDATA_I(9) <= (others => '0');
Dbg_RRESP_I(9) <= (others => '0');
Dbg_RVALID_I(9) <= '0';
Dbg_RREADY_9 <= '0';
Dbg_AWADDR_10 <= (others => '0');
Dbg_AWVALID_10 <= '0';
Dbg_AWREADY_I(10) <= '0';
Dbg_WDATA_10 <= (others => '0');
Dbg_WVALID_10 <= '0';
Dbg_WREADY_I(10) <= '0';
Dbg_BRESP_I(10) <= (others => '0');
Dbg_BVALID_I(10) <= '0';
Dbg_BREADY_10 <= '0';
Dbg_ARADDR_10 <= (others => '0');
Dbg_ARVALID_10 <= '0';
Dbg_ARREADY_I(10) <= '0';
Dbg_RDATA_I(10) <= (others => '0');
Dbg_RRESP_I(10) <= (others => '0');
Dbg_RVALID_I(10) <= '0';
Dbg_RREADY_10 <= '0';
Dbg_AWADDR_11 <= (others => '0');
Dbg_AWVALID_11 <= '0';
Dbg_AWREADY_I(11) <= '0';
Dbg_WDATA_11 <= (others => '0');
Dbg_WVALID_11 <= '0';
Dbg_WREADY_I(11) <= '0';
Dbg_BRESP_I(11) <= (others => '0');
Dbg_BVALID_I(11) <= '0';
Dbg_BREADY_11 <= '0';
Dbg_ARADDR_11 <= (others => '0');
Dbg_ARVALID_11 <= '0';
Dbg_ARREADY_I(11) <= '0';
Dbg_RDATA_I(11) <= (others => '0');
Dbg_RRESP_I(11) <= (others => '0');
Dbg_RVALID_I(11) <= '0';
Dbg_RREADY_11 <= '0';
Dbg_AWADDR_12 <= (others => '0');
Dbg_AWVALID_12 <= '0';
Dbg_AWREADY_I(12) <= '0';
Dbg_WDATA_12 <= (others => '0');
Dbg_WVALID_12 <= '0';
Dbg_WREADY_I(12) <= '0';
Dbg_BRESP_I(12) <= (others => '0');
Dbg_BVALID_I(12) <= '0';
Dbg_BREADY_12 <= '0';
Dbg_ARADDR_12 <= (others => '0');
Dbg_ARVALID_12 <= '0';
Dbg_ARREADY_I(12) <= '0';
Dbg_RDATA_I(12) <= (others => '0');
Dbg_RRESP_I(12) <= (others => '0');
Dbg_RVALID_I(12) <= '0';
Dbg_RREADY_12 <= '0';
Dbg_AWADDR_13 <= (others => '0');
Dbg_AWVALID_13 <= '0';
Dbg_AWREADY_I(13) <= '0';
Dbg_WDATA_13 <= (others => '0');
Dbg_WVALID_13 <= '0';
Dbg_WREADY_I(13) <= '0';
Dbg_BRESP_I(13) <= (others => '0');
Dbg_BVALID_I(13) <= '0';
Dbg_BREADY_13 <= '0';
Dbg_ARADDR_13 <= (others => '0');
Dbg_ARVALID_13 <= '0';
Dbg_ARREADY_I(13) <= '0';
Dbg_RDATA_I(13) <= (others => '0');
Dbg_RRESP_I(13) <= (others => '0');
Dbg_RVALID_I(13) <= '0';
Dbg_RREADY_13 <= '0';
Dbg_AWADDR_14 <= (others => '0');
Dbg_AWVALID_14 <= '0';
Dbg_AWREADY_I(14) <= '0';
Dbg_WDATA_14 <= (others => '0');
Dbg_WVALID_14 <= '0';
Dbg_WREADY_I(14) <= '0';
Dbg_BRESP_I(14) <= (others => '0');
Dbg_BVALID_I(14) <= '0';
Dbg_BREADY_14 <= '0';
Dbg_ARADDR_14 <= (others => '0');
Dbg_ARVALID_14 <= '0';
Dbg_ARREADY_I(14) <= '0';
Dbg_RDATA_I(14) <= (others => '0');
Dbg_RRESP_I(14) <= (others => '0');
Dbg_RVALID_I(14) <= '0';
Dbg_RREADY_14 <= '0';
Dbg_AWADDR_15 <= (others => '0');
Dbg_AWVALID_15 <= '0';
Dbg_AWREADY_I(15) <= '0';
Dbg_WDATA_15 <= (others => '0');
Dbg_WVALID_15 <= '0';
Dbg_WREADY_I(15) <= '0';
Dbg_BRESP_I(15) <= (others => '0');
Dbg_BVALID_I(15) <= '0';
Dbg_BREADY_15 <= '0';
Dbg_ARADDR_15 <= (others => '0');
Dbg_ARVALID_15 <= '0';
Dbg_ARREADY_I(15) <= '0';
Dbg_RDATA_I(15) <= (others => '0');
Dbg_RRESP_I(15) <= (others => '0');
Dbg_RVALID_I(15) <= '0';
Dbg_RREADY_15 <= '0';
Dbg_AWADDR_16 <= (others => '0');
Dbg_AWVALID_16 <= '0';
Dbg_AWREADY_I(16) <= '0';
Dbg_WDATA_16 <= (others => '0');
Dbg_WVALID_16 <= '0';
Dbg_WREADY_I(16) <= '0';
Dbg_BRESP_I(16) <= (others => '0');
Dbg_BVALID_I(16) <= '0';
Dbg_BREADY_16 <= '0';
Dbg_ARADDR_16 <= (others => '0');
Dbg_ARVALID_16 <= '0';
Dbg_ARREADY_I(16) <= '0';
Dbg_RDATA_I(16) <= (others => '0');
Dbg_RRESP_I(16) <= (others => '0');
Dbg_RVALID_I(16) <= '0';
Dbg_RREADY_16 <= '0';
Dbg_AWADDR_17 <= (others => '0');
Dbg_AWVALID_17 <= '0';
Dbg_AWREADY_I(17) <= '0';
Dbg_WDATA_17 <= (others => '0');
Dbg_WVALID_17 <= '0';
Dbg_WREADY_I(17) <= '0';
Dbg_BRESP_I(17) <= (others => '0');
Dbg_BVALID_I(17) <= '0';
Dbg_BREADY_17 <= '0';
Dbg_ARADDR_17 <= (others => '0');
Dbg_ARVALID_17 <= '0';
Dbg_ARREADY_I(17) <= '0';
Dbg_RDATA_I(17) <= (others => '0');
Dbg_RRESP_I(17) <= (others => '0');
Dbg_RVALID_I(17) <= '0';
Dbg_RREADY_17 <= '0';
Dbg_AWADDR_18 <= (others => '0');
Dbg_AWVALID_18 <= '0';
Dbg_AWREADY_I(18) <= '0';
Dbg_WDATA_18 <= (others => '0');
Dbg_WVALID_18 <= '0';
Dbg_WREADY_I(18) <= '0';
Dbg_BRESP_I(18) <= (others => '0');
Dbg_BVALID_I(18) <= '0';
Dbg_BREADY_18 <= '0';
Dbg_ARADDR_18 <= (others => '0');
Dbg_ARVALID_18 <= '0';
Dbg_ARREADY_I(18) <= '0';
Dbg_RDATA_I(18) <= (others => '0');
Dbg_RRESP_I(18) <= (others => '0');
Dbg_RVALID_I(18) <= '0';
Dbg_RREADY_18 <= '0';
Dbg_AWADDR_19 <= (others => '0');
Dbg_AWVALID_19 <= '0';
Dbg_AWREADY_I(19) <= '0';
Dbg_WDATA_19 <= (others => '0');
Dbg_WVALID_19 <= '0';
Dbg_WREADY_I(19) <= '0';
Dbg_BRESP_I(19) <= (others => '0');
Dbg_BVALID_I(19) <= '0';
Dbg_BREADY_19 <= '0';
Dbg_ARADDR_19 <= (others => '0');
Dbg_ARVALID_19 <= '0';
Dbg_ARREADY_I(19) <= '0';
Dbg_RDATA_I(19) <= (others => '0');
Dbg_RRESP_I(19) <= (others => '0');
Dbg_RVALID_I(19) <= '0';
Dbg_RREADY_19 <= '0';
Dbg_AWADDR_20 <= (others => '0');
Dbg_AWVALID_20 <= '0';
Dbg_AWREADY_I(20) <= '0';
Dbg_WDATA_20 <= (others => '0');
Dbg_WVALID_20 <= '0';
Dbg_WREADY_I(20) <= '0';
Dbg_BRESP_I(20) <= (others => '0');
Dbg_BVALID_I(20) <= '0';
Dbg_BREADY_20 <= '0';
Dbg_ARADDR_20 <= (others => '0');
Dbg_ARVALID_20 <= '0';
Dbg_ARREADY_I(20) <= '0';
Dbg_RDATA_I(20) <= (others => '0');
Dbg_RRESP_I(20) <= (others => '0');
Dbg_RVALID_I(20) <= '0';
Dbg_RREADY_20 <= '0';
Dbg_AWADDR_21 <= (others => '0');
Dbg_AWVALID_21 <= '0';
Dbg_AWREADY_I(21) <= '0';
Dbg_WDATA_21 <= (others => '0');
Dbg_WVALID_21 <= '0';
Dbg_WREADY_I(21) <= '0';
Dbg_BRESP_I(21) <= (others => '0');
Dbg_BVALID_I(21) <= '0';
Dbg_BREADY_21 <= '0';
Dbg_ARADDR_21 <= (others => '0');
Dbg_ARVALID_21 <= '0';
Dbg_ARREADY_I(21) <= '0';
Dbg_RDATA_I(21) <= (others => '0');
Dbg_RRESP_I(21) <= (others => '0');
Dbg_RVALID_I(21) <= '0';
Dbg_RREADY_21 <= '0';
Dbg_AWADDR_22 <= (others => '0');
Dbg_AWVALID_22 <= '0';
Dbg_AWREADY_I(22) <= '0';
Dbg_WDATA_22 <= (others => '0');
Dbg_WVALID_22 <= '0';
Dbg_WREADY_I(22) <= '0';
Dbg_BRESP_I(22) <= (others => '0');
Dbg_BVALID_I(22) <= '0';
Dbg_BREADY_22 <= '0';
Dbg_ARADDR_22 <= (others => '0');
Dbg_ARVALID_22 <= '0';
Dbg_ARREADY_I(22) <= '0';
Dbg_RDATA_I(22) <= (others => '0');
Dbg_RRESP_I(22) <= (others => '0');
Dbg_RVALID_I(22) <= '0';
Dbg_RREADY_22 <= '0';
Dbg_AWADDR_23 <= (others => '0');
Dbg_AWVALID_23 <= '0';
Dbg_AWREADY_I(23) <= '0';
Dbg_WDATA_23 <= (others => '0');
Dbg_WVALID_23 <= '0';
Dbg_WREADY_I(23) <= '0';
Dbg_BRESP_I(23) <= (others => '0');
Dbg_BVALID_I(23) <= '0';
Dbg_BREADY_23 <= '0';
Dbg_ARADDR_23 <= (others => '0');
Dbg_ARVALID_23 <= '0';
Dbg_ARREADY_I(23) <= '0';
Dbg_RDATA_I(23) <= (others => '0');
Dbg_RRESP_I(23) <= (others => '0');
Dbg_RVALID_I(23) <= '0';
Dbg_RREADY_23 <= '0';
Dbg_AWADDR_24 <= (others => '0');
Dbg_AWVALID_24 <= '0';
Dbg_AWREADY_I(24) <= '0';
Dbg_WDATA_24 <= (others => '0');
Dbg_WVALID_24 <= '0';
Dbg_WREADY_I(24) <= '0';
Dbg_BRESP_I(24) <= (others => '0');
Dbg_BVALID_I(24) <= '0';
Dbg_BREADY_24 <= '0';
Dbg_ARADDR_24 <= (others => '0');
Dbg_ARVALID_24 <= '0';
Dbg_ARREADY_I(24) <= '0';
Dbg_RDATA_I(24) <= (others => '0');
Dbg_RRESP_I(24) <= (others => '0');
Dbg_RVALID_I(24) <= '0';
Dbg_RREADY_24 <= '0';
Dbg_AWADDR_25 <= (others => '0');
Dbg_AWVALID_25 <= '0';
Dbg_AWREADY_I(25) <= '0';
Dbg_WDATA_25 <= (others => '0');
Dbg_WVALID_25 <= '0';
Dbg_WREADY_I(25) <= '0';
Dbg_BRESP_I(25) <= (others => '0');
Dbg_BVALID_I(25) <= '0';
Dbg_BREADY_25 <= '0';
Dbg_ARADDR_25 <= (others => '0');
Dbg_ARVALID_25 <= '0';
Dbg_ARREADY_I(25) <= '0';
Dbg_RDATA_I(25) <= (others => '0');
Dbg_RRESP_I(25) <= (others => '0');
Dbg_RVALID_I(25) <= '0';
Dbg_RREADY_25 <= '0';
Dbg_AWADDR_26 <= (others => '0');
Dbg_AWVALID_26 <= '0';
Dbg_AWREADY_I(26) <= '0';
Dbg_WDATA_26 <= (others => '0');
Dbg_WVALID_26 <= '0';
Dbg_WREADY_I(26) <= '0';
Dbg_BRESP_I(26) <= (others => '0');
Dbg_BVALID_I(26) <= '0';
Dbg_BREADY_26 <= '0';
Dbg_ARADDR_26 <= (others => '0');
Dbg_ARVALID_26 <= '0';
Dbg_ARREADY_I(26) <= '0';
Dbg_RDATA_I(26) <= (others => '0');
Dbg_RRESP_I(26) <= (others => '0');
Dbg_RVALID_I(26) <= '0';
Dbg_RREADY_26 <= '0';
Dbg_AWADDR_27 <= (others => '0');
Dbg_AWVALID_27 <= '0';
Dbg_AWREADY_I(27) <= '0';
Dbg_WDATA_27 <= (others => '0');
Dbg_WVALID_27 <= '0';
Dbg_WREADY_I(27) <= '0';
Dbg_BRESP_I(27) <= (others => '0');
Dbg_BVALID_I(27) <= '0';
Dbg_BREADY_27 <= '0';
Dbg_ARADDR_27 <= (others => '0');
Dbg_ARVALID_27 <= '0';
Dbg_ARREADY_I(27) <= '0';
Dbg_RDATA_I(27) <= (others => '0');
Dbg_RRESP_I(27) <= (others => '0');
Dbg_RVALID_I(27) <= '0';
Dbg_RREADY_27 <= '0';
Dbg_AWADDR_28 <= (others => '0');
Dbg_AWVALID_28 <= '0';
Dbg_AWREADY_I(28) <= '0';
Dbg_WDATA_28 <= (others => '0');
Dbg_WVALID_28 <= '0';
Dbg_WREADY_I(28) <= '0';
Dbg_BRESP_I(28) <= (others => '0');
Dbg_BVALID_I(28) <= '0';
Dbg_BREADY_28 <= '0';
Dbg_ARADDR_28 <= (others => '0');
Dbg_ARVALID_28 <= '0';
Dbg_ARREADY_I(28) <= '0';
Dbg_RDATA_I(28) <= (others => '0');
Dbg_RRESP_I(28) <= (others => '0');
Dbg_RVALID_I(28) <= '0';
Dbg_RREADY_28 <= '0';
Dbg_AWADDR_29 <= (others => '0');
Dbg_AWVALID_29 <= '0';
Dbg_AWREADY_I(29) <= '0';
Dbg_WDATA_29 <= (others => '0');
Dbg_WVALID_29 <= '0';
Dbg_WREADY_I(29) <= '0';
Dbg_BRESP_I(29) <= (others => '0');
Dbg_BVALID_I(29) <= '0';
Dbg_BREADY_29 <= '0';
Dbg_ARADDR_29 <= (others => '0');
Dbg_ARVALID_29 <= '0';
Dbg_ARREADY_I(29) <= '0';
Dbg_RDATA_I(29) <= (others => '0');
Dbg_RRESP_I(29) <= (others => '0');
Dbg_RVALID_I(29) <= '0';
Dbg_RREADY_29 <= '0';
Dbg_AWADDR_30 <= (others => '0');
Dbg_AWVALID_30 <= '0';
Dbg_AWREADY_I(30) <= '0';
Dbg_WDATA_30 <= (others => '0');
Dbg_WVALID_30 <= '0';
Dbg_WREADY_I(30) <= '0';
Dbg_BRESP_I(30) <= (others => '0');
Dbg_BVALID_I(30) <= '0';
Dbg_BREADY_30 <= '0';
Dbg_ARADDR_30 <= (others => '0');
Dbg_ARVALID_30 <= '0';
Dbg_ARREADY_I(30) <= '0';
Dbg_RDATA_I(30) <= (others => '0');
Dbg_RRESP_I(30) <= (others => '0');
Dbg_RVALID_I(30) <= '0';
Dbg_RREADY_30 <= '0';
Dbg_AWADDR_31 <= (others => '0');
Dbg_AWVALID_31 <= '0';
Dbg_AWREADY_I(31) <= '0';
Dbg_WDATA_31 <= (others => '0');
Dbg_WVALID_31 <= '0';
Dbg_WREADY_I(31) <= '0';
Dbg_BRESP_I(31) <= (others => '0');
Dbg_BVALID_I(31) <= '0';
Dbg_BREADY_31 <= '0';
Dbg_ARADDR_31 <= (others => '0');
Dbg_ARVALID_31 <= '0';
Dbg_ARREADY_I(31) <= '0';
Dbg_RDATA_I(31) <= (others => '0');
Dbg_RRESP_I(31) <= (others => '0');
Dbg_RVALID_I(31) <= '0';
Dbg_RREADY_31 <= '0';
end generate Use_Serial;
Use_Parallel : if C_DEBUG_INTERFACE = 1 generate
begin
Generate_Dbg_Port_Signals : process (mb_debug_enabled_i,
Dbg_AWVALID_I, Dbg_AWREADY_I,
Dbg_WVALID_I, Dbg_WREADY_I,
Dbg_ARVALID_I, Dbg_ARREADY_I,
Dbg_BRESP_I, Dbg_BVALID_I,
Dbg_RDATA_I, Dbg_RRESP_I, Dbg_RVALID_I)
variable dbg_awready_or : std_logic;
variable dbg_wready_or : std_logic;
variable dbg_arready_or : std_logic;
variable dbg_bresp_or : std_logic;
variable dbg_bvalid_or : std_logic;
variable dbg_rdata_or : std_logic_vector(31 downto 0);
variable dbg_rresp_or : std_logic;
variable dbg_rvalid_or : std_logic;
begin -- process Generate_Dbg_Port_Signals
dbg_awready_or := '0';
dbg_wready_or := '0';
dbg_arready_or := '0';
dbg_bresp_or := '0';
dbg_bvalid_or := '0';
dbg_rdata_or := (others => '0');
dbg_rresp_or := '0';
dbg_rvalid_or := '0';
for I in 0 to C_EN_WIDTH-1 loop
if (mb_debug_enabled_i(I) = '1') then
Dbg_AWVALID(I) <= Dbg_AWVALID_I;
Dbg_WVALID(I) <= Dbg_WVALID_I;
Dbg_ARVALID(I) <= Dbg_ARVALID_I;
else
Dbg_AWVALID(I) <= '0';
Dbg_WVALID(I) <= '0';
Dbg_ARVALID(I) <= '0';
end if;
Dbg_BREADY(I) <= '1';
Dbg_RREADY(I) <= '1';
dbg_awready_or := dbg_awready_or or Dbg_AWREADY_I(I);
dbg_wready_or := dbg_wready_or or Dbg_WREADY_I(I);
dbg_arready_or := dbg_arready_or or Dbg_ARREADY_I(I);
dbg_bresp_or := dbg_bresp_or or Dbg_BRESP_I(I)(1);
dbg_bvalid_or := dbg_bvalid_or or Dbg_BVALID_I(I);
dbg_rdata_or := dbg_rdata_or or Dbg_RDATA_I(I);
dbg_rresp_or := dbg_rresp_or or Dbg_RRESP_I(I)(1);
dbg_rvalid_or := dbg_rvalid_or or Dbg_RVALID_I(I);
end loop; -- I
for I in C_EN_WIDTH to 31 loop
Dbg_AWVALID(I) <= '0';
Dbg_WVALID(I) <= '0';
Dbg_ARVALID(I) <= '0';
Dbg_BREADY(I) <= '0';
Dbg_RREADY(I) <= '0';
end loop; -- I
Dbg_AWREADY <= dbg_awready_or;
Dbg_WREADY <= dbg_wready_or;
Dbg_ARREADY <= dbg_arready_or;
Dbg_BRESP <= dbg_bresp_or;
Dbg_BVALID <= dbg_bvalid_or;
Dbg_RDATA <= dbg_rdata_or;
Dbg_RRESP <= dbg_rresp_or;
Dbg_RVALID <= dbg_rvalid_or;
end process Generate_Dbg_Port_Signals;
Dbg_AWADDR_0 <= Dbg_AWADDR;
Dbg_AWVALID_0 <= Dbg_WVALID(0);
Dbg_AWREADY_I(0) <= Dbg_AWREADY_0;
Dbg_WDATA_0 <= Dbg_WDATA;
Dbg_WVALID_0 <= Dbg_AWVALID(0);
Dbg_WREADY_I(0) <= Dbg_WREADY_0;
Dbg_BRESP_I(0) <= Dbg_BRESP_0;
Dbg_BVALID_I(0) <= Dbg_BVALID_0;
Dbg_BREADY_0 <= Dbg_BREADY(0);
Dbg_ARADDR_0 <= Dbg_ARADDR;
Dbg_ARVALID_0 <= Dbg_ARVALID(0);
Dbg_ARREADY_I(0) <= Dbg_ARREADY_0;
Dbg_RDATA_I(0) <= Dbg_RDATA_0;
Dbg_RRESP_I(0) <= Dbg_RRESP_0;
Dbg_RVALID_I(0) <= Dbg_RVALID_0;
Dbg_RREADY_0 <= Dbg_RREADY(0);
Dbg_AWADDR_1 <= Dbg_AWADDR;
Dbg_AWVALID_1 <= Dbg_WVALID(1);
Dbg_AWREADY_I(1) <= Dbg_AWREADY_1;
Dbg_WDATA_1 <= Dbg_WDATA;
Dbg_WVALID_1 <= Dbg_AWVALID(1);
Dbg_WREADY_I(1) <= Dbg_WREADY_1;
Dbg_BRESP_I(1) <= Dbg_BRESP_1;
Dbg_BVALID_I(1) <= Dbg_BVALID_1;
Dbg_BREADY_1 <= Dbg_BREADY(1);
Dbg_ARADDR_1 <= Dbg_ARADDR;
Dbg_ARVALID_1 <= Dbg_ARVALID(1);
Dbg_ARREADY_I(1) <= Dbg_ARREADY_1;
Dbg_RDATA_I(1) <= Dbg_RDATA_1;
Dbg_RRESP_I(1) <= Dbg_RRESP_1;
Dbg_RVALID_I(1) <= Dbg_RVALID_1;
Dbg_RREADY_1 <= Dbg_RREADY(1);
Dbg_AWADDR_2 <= Dbg_AWADDR;
Dbg_AWVALID_2 <= Dbg_WVALID(2);
Dbg_AWREADY_I(2) <= Dbg_AWREADY_2;
Dbg_WDATA_2 <= Dbg_WDATA;
Dbg_WVALID_2 <= Dbg_AWVALID(2);
Dbg_WREADY_I(2) <= Dbg_WREADY_2;
Dbg_BRESP_I(2) <= Dbg_BRESP_2;
Dbg_BVALID_I(2) <= Dbg_BVALID_2;
Dbg_BREADY_2 <= Dbg_BREADY(2);
Dbg_ARADDR_2 <= Dbg_ARADDR;
Dbg_ARVALID_2 <= Dbg_ARVALID(2);
Dbg_ARREADY_I(2) <= Dbg_ARREADY_2;
Dbg_RDATA_I(2) <= Dbg_RDATA_2;
Dbg_RRESP_I(2) <= Dbg_RRESP_2;
Dbg_RVALID_I(2) <= Dbg_RVALID_2;
Dbg_RREADY_2 <= Dbg_RREADY(2);
Dbg_AWADDR_3 <= Dbg_AWADDR;
Dbg_AWVALID_3 <= Dbg_WVALID(3);
Dbg_AWREADY_I(3) <= Dbg_AWREADY_3;
Dbg_WDATA_3 <= Dbg_WDATA;
Dbg_WVALID_3 <= Dbg_AWVALID(3);
Dbg_WREADY_I(3) <= Dbg_WREADY_3;
Dbg_BRESP_I(3) <= Dbg_BRESP_3;
Dbg_BVALID_I(3) <= Dbg_BVALID_3;
Dbg_BREADY_3 <= Dbg_BREADY(3);
Dbg_ARADDR_3 <= Dbg_ARADDR;
Dbg_ARVALID_3 <= Dbg_ARVALID(3);
Dbg_ARREADY_I(3) <= Dbg_ARREADY_3;
Dbg_RDATA_I(3) <= Dbg_RDATA_3;
Dbg_RRESP_I(3) <= Dbg_RRESP_3;
Dbg_RVALID_I(3) <= Dbg_RVALID_3;
Dbg_RREADY_3 <= Dbg_RREADY(3);
Dbg_AWADDR_4 <= Dbg_AWADDR;
Dbg_AWVALID_4 <= Dbg_WVALID(4);
Dbg_AWREADY_I(4) <= Dbg_AWREADY_4;
Dbg_WDATA_4 <= Dbg_WDATA;
Dbg_WVALID_4 <= Dbg_AWVALID(4);
Dbg_WREADY_I(4) <= Dbg_WREADY_4;
Dbg_BRESP_I(4) <= Dbg_BRESP_4;
Dbg_BVALID_I(4) <= Dbg_BVALID_4;
Dbg_BREADY_4 <= Dbg_BREADY(4);
Dbg_ARADDR_4 <= Dbg_ARADDR;
Dbg_ARVALID_4 <= Dbg_ARVALID(4);
Dbg_ARREADY_I(4) <= Dbg_ARREADY_4;
Dbg_RDATA_I(4) <= Dbg_RDATA_4;
Dbg_RRESP_I(4) <= Dbg_RRESP_4;
Dbg_RVALID_I(4) <= Dbg_RVALID_4;
Dbg_RREADY_4 <= Dbg_RREADY(4);
Dbg_AWADDR_5 <= Dbg_AWADDR;
Dbg_AWVALID_5 <= Dbg_WVALID(5);
Dbg_AWREADY_I(5) <= Dbg_AWREADY_5;
Dbg_WDATA_5 <= Dbg_WDATA;
Dbg_WVALID_5 <= Dbg_AWVALID(5);
Dbg_WREADY_I(5) <= Dbg_WREADY_5;
Dbg_BRESP_I(5) <= Dbg_BRESP_5;
Dbg_BVALID_I(5) <= Dbg_BVALID_5;
Dbg_BREADY_5 <= Dbg_BREADY(5);
Dbg_ARADDR_5 <= Dbg_ARADDR;
Dbg_ARVALID_5 <= Dbg_ARVALID(5);
Dbg_ARREADY_I(5) <= Dbg_ARREADY_5;
Dbg_RDATA_I(5) <= Dbg_RDATA_5;
Dbg_RRESP_I(5) <= Dbg_RRESP_5;
Dbg_RVALID_I(5) <= Dbg_RVALID_5;
Dbg_RREADY_5 <= Dbg_RREADY(5);
Dbg_AWADDR_6 <= Dbg_AWADDR;
Dbg_AWVALID_6 <= Dbg_WVALID(6);
Dbg_AWREADY_I(6) <= Dbg_AWREADY_6;
Dbg_WDATA_6 <= Dbg_WDATA;
Dbg_WVALID_6 <= Dbg_AWVALID(6);
Dbg_WREADY_I(6) <= Dbg_WREADY_6;
Dbg_BRESP_I(6) <= Dbg_BRESP_6;
Dbg_BVALID_I(6) <= Dbg_BVALID_6;
Dbg_BREADY_6 <= Dbg_BREADY(6);
Dbg_ARADDR_6 <= Dbg_ARADDR;
Dbg_ARVALID_6 <= Dbg_ARVALID(6);
Dbg_ARREADY_I(6) <= Dbg_ARREADY_6;
Dbg_RDATA_I(6) <= Dbg_RDATA_6;
Dbg_RRESP_I(6) <= Dbg_RRESP_6;
Dbg_RVALID_I(6) <= Dbg_RVALID_6;
Dbg_RREADY_6 <= Dbg_RREADY(6);
Dbg_AWADDR_7 <= Dbg_AWADDR;
Dbg_AWVALID_7 <= Dbg_WVALID(7);
Dbg_AWREADY_I(7) <= Dbg_AWREADY_7;
Dbg_WDATA_7 <= Dbg_WDATA;
Dbg_WVALID_7 <= Dbg_AWVALID(7);
Dbg_WREADY_I(7) <= Dbg_WREADY_7;
Dbg_BRESP_I(7) <= Dbg_BRESP_7;
Dbg_BVALID_I(7) <= Dbg_BVALID_7;
Dbg_BREADY_7 <= Dbg_BREADY(7);
Dbg_ARADDR_7 <= Dbg_ARADDR;
Dbg_ARVALID_7 <= Dbg_ARVALID(7);
Dbg_ARREADY_I(7) <= Dbg_ARREADY_7;
Dbg_RDATA_I(7) <= Dbg_RDATA_7;
Dbg_RRESP_I(7) <= Dbg_RRESP_7;
Dbg_RVALID_I(7) <= Dbg_RVALID_7;
Dbg_RREADY_7 <= Dbg_RREADY(7);
Dbg_AWADDR_8 <= Dbg_AWADDR;
Dbg_AWVALID_8 <= Dbg_WVALID(8);
Dbg_AWREADY_I(8) <= Dbg_AWREADY_8;
Dbg_WDATA_8 <= Dbg_WDATA;
Dbg_WVALID_8 <= Dbg_AWVALID(8);
Dbg_WREADY_I(8) <= Dbg_WREADY_8;
Dbg_BRESP_I(8) <= Dbg_BRESP_8;
Dbg_BVALID_I(8) <= Dbg_BVALID_8;
Dbg_BREADY_8 <= Dbg_BREADY(8);
Dbg_ARADDR_8 <= Dbg_ARADDR;
Dbg_ARVALID_8 <= Dbg_ARVALID(8);
Dbg_ARREADY_I(8) <= Dbg_ARREADY_8;
Dbg_RDATA_I(8) <= Dbg_RDATA_8;
Dbg_RRESP_I(8) <= Dbg_RRESP_8;
Dbg_RVALID_I(8) <= Dbg_RVALID_8;
Dbg_RREADY_8 <= Dbg_RREADY(8);
Dbg_AWADDR_9 <= Dbg_AWADDR;
Dbg_AWVALID_9 <= Dbg_WVALID(9);
Dbg_AWREADY_I(9) <= Dbg_AWREADY_9;
Dbg_WDATA_9 <= Dbg_WDATA;
Dbg_WVALID_9 <= Dbg_AWVALID(9);
Dbg_WREADY_I(9) <= Dbg_WREADY_9;
Dbg_BRESP_I(9) <= Dbg_BRESP_9;
Dbg_BVALID_I(9) <= Dbg_BVALID_9;
Dbg_BREADY_9 <= Dbg_BREADY(9);
Dbg_ARADDR_9 <= Dbg_ARADDR;
Dbg_ARVALID_9 <= Dbg_ARVALID(9);
Dbg_ARREADY_I(9) <= Dbg_ARREADY_9;
Dbg_RDATA_I(9) <= Dbg_RDATA_9;
Dbg_RRESP_I(9) <= Dbg_RRESP_9;
Dbg_RVALID_I(9) <= Dbg_RVALID_9;
Dbg_RREADY_9 <= Dbg_RREADY(9);
Dbg_AWADDR_10 <= Dbg_AWADDR;
Dbg_AWVALID_10 <= Dbg_WVALID(10);
Dbg_AWREADY_I(10) <= Dbg_AWREADY_10;
Dbg_WDATA_10 <= Dbg_WDATA;
Dbg_WVALID_10 <= Dbg_AWVALID(10);
Dbg_WREADY_I(10) <= Dbg_WREADY_10;
Dbg_BRESP_I(10) <= Dbg_BRESP_10;
Dbg_BVALID_I(10) <= Dbg_BVALID_10;
Dbg_BREADY_10 <= Dbg_BREADY(10);
Dbg_ARADDR_10 <= Dbg_ARADDR;
Dbg_ARVALID_10 <= Dbg_ARVALID(10);
Dbg_ARREADY_I(10) <= Dbg_ARREADY_10;
Dbg_RDATA_I(10) <= Dbg_RDATA_10;
Dbg_RRESP_I(10) <= Dbg_RRESP_10;
Dbg_RVALID_I(10) <= Dbg_RVALID_10;
Dbg_RREADY_10 <= Dbg_RREADY(10);
Dbg_AWADDR_11 <= Dbg_AWADDR;
Dbg_AWVALID_11 <= Dbg_WVALID(11);
Dbg_AWREADY_I(11) <= Dbg_AWREADY_11;
Dbg_WDATA_11 <= Dbg_WDATA;
Dbg_WVALID_11 <= Dbg_AWVALID(11);
Dbg_WREADY_I(11) <= Dbg_WREADY_11;
Dbg_BRESP_I(11) <= Dbg_BRESP_11;
Dbg_BVALID_I(11) <= Dbg_BVALID_11;
Dbg_BREADY_11 <= Dbg_BREADY(11);
Dbg_ARADDR_11 <= Dbg_ARADDR;
Dbg_ARVALID_11 <= Dbg_ARVALID(11);
Dbg_ARREADY_I(11) <= Dbg_ARREADY_11;
Dbg_RDATA_I(11) <= Dbg_RDATA_11;
Dbg_RRESP_I(11) <= Dbg_RRESP_11;
Dbg_RVALID_I(11) <= Dbg_RVALID_11;
Dbg_RREADY_11 <= Dbg_RREADY(11);
Dbg_AWADDR_12 <= Dbg_AWADDR;
Dbg_AWVALID_12 <= Dbg_WVALID(12);
Dbg_AWREADY_I(12) <= Dbg_AWREADY_12;
Dbg_WDATA_12 <= Dbg_WDATA;
Dbg_WVALID_12 <= Dbg_AWVALID(12);
Dbg_WREADY_I(12) <= Dbg_WREADY_12;
Dbg_BRESP_I(12) <= Dbg_BRESP_12;
Dbg_BVALID_I(12) <= Dbg_BVALID_12;
Dbg_BREADY_12 <= Dbg_BREADY(12);
Dbg_ARADDR_12 <= Dbg_ARADDR;
Dbg_ARVALID_12 <= Dbg_ARVALID(12);
Dbg_ARREADY_I(12) <= Dbg_ARREADY_12;
Dbg_RDATA_I(12) <= Dbg_RDATA_12;
Dbg_RRESP_I(12) <= Dbg_RRESP_12;
Dbg_RVALID_I(12) <= Dbg_RVALID_12;
Dbg_RREADY_12 <= Dbg_RREADY(12);
Dbg_AWADDR_13 <= Dbg_AWADDR;
Dbg_AWVALID_13 <= Dbg_WVALID(13);
Dbg_AWREADY_I(13) <= Dbg_AWREADY_13;
Dbg_WDATA_13 <= Dbg_WDATA;
Dbg_WVALID_13 <= Dbg_AWVALID(13);
Dbg_WREADY_I(13) <= Dbg_WREADY_13;
Dbg_BRESP_I(13) <= Dbg_BRESP_13;
Dbg_BVALID_I(13) <= Dbg_BVALID_13;
Dbg_BREADY_13 <= Dbg_BREADY(13);
Dbg_ARADDR_13 <= Dbg_ARADDR;
Dbg_ARVALID_13 <= Dbg_ARVALID(13);
Dbg_ARREADY_I(13) <= Dbg_ARREADY_13;
Dbg_RDATA_I(13) <= Dbg_RDATA_13;
Dbg_RRESP_I(13) <= Dbg_RRESP_13;
Dbg_RVALID_I(13) <= Dbg_RVALID_13;
Dbg_RREADY_13 <= Dbg_RREADY(13);
Dbg_AWADDR_14 <= Dbg_AWADDR;
Dbg_AWVALID_14 <= Dbg_WVALID(14);
Dbg_AWREADY_I(14) <= Dbg_AWREADY_14;
Dbg_WDATA_14 <= Dbg_WDATA;
Dbg_WVALID_14 <= Dbg_AWVALID(14);
Dbg_WREADY_I(14) <= Dbg_WREADY_14;
Dbg_BRESP_I(14) <= Dbg_BRESP_14;
Dbg_BVALID_I(14) <= Dbg_BVALID_14;
Dbg_BREADY_14 <= Dbg_BREADY(14);
Dbg_ARADDR_14 <= Dbg_ARADDR;
Dbg_ARVALID_14 <= Dbg_ARVALID(14);
Dbg_ARREADY_I(14) <= Dbg_ARREADY_14;
Dbg_RDATA_I(14) <= Dbg_RDATA_14;
Dbg_RRESP_I(14) <= Dbg_RRESP_14;
Dbg_RVALID_I(14) <= Dbg_RVALID_14;
Dbg_RREADY_14 <= Dbg_RREADY(14);
Dbg_AWADDR_15 <= Dbg_AWADDR;
Dbg_AWVALID_15 <= Dbg_WVALID(15);
Dbg_AWREADY_I(15) <= Dbg_AWREADY_15;
Dbg_WDATA_15 <= Dbg_WDATA;
Dbg_WVALID_15 <= Dbg_AWVALID(15);
Dbg_WREADY_I(15) <= Dbg_WREADY_15;
Dbg_BRESP_I(15) <= Dbg_BRESP_15;
Dbg_BVALID_I(15) <= Dbg_BVALID_15;
Dbg_BREADY_15 <= Dbg_BREADY(15);
Dbg_ARADDR_15 <= Dbg_ARADDR;
Dbg_ARVALID_15 <= Dbg_ARVALID(15);
Dbg_ARREADY_I(15) <= Dbg_ARREADY_15;
Dbg_RDATA_I(15) <= Dbg_RDATA_15;
Dbg_RRESP_I(15) <= Dbg_RRESP_15;
Dbg_RVALID_I(15) <= Dbg_RVALID_15;
Dbg_RREADY_15 <= Dbg_RREADY(15);
Dbg_AWADDR_16 <= Dbg_AWADDR;
Dbg_AWVALID_16 <= Dbg_WVALID(16);
Dbg_AWREADY_I(16) <= Dbg_AWREADY_16;
Dbg_WDATA_16 <= Dbg_WDATA;
Dbg_WVALID_16 <= Dbg_AWVALID(16);
Dbg_WREADY_I(16) <= Dbg_WREADY_16;
Dbg_BRESP_I(16) <= Dbg_BRESP_16;
Dbg_BVALID_I(16) <= Dbg_BVALID_16;
Dbg_BREADY_16 <= Dbg_BREADY(16);
Dbg_ARADDR_16 <= Dbg_ARADDR;
Dbg_ARVALID_16 <= Dbg_ARVALID(16);
Dbg_ARREADY_I(16) <= Dbg_ARREADY_16;
Dbg_RDATA_I(16) <= Dbg_RDATA_16;
Dbg_RRESP_I(16) <= Dbg_RRESP_16;
Dbg_RVALID_I(16) <= Dbg_RVALID_16;
Dbg_RREADY_16 <= Dbg_RREADY(16);
Dbg_AWADDR_17 <= Dbg_AWADDR;
Dbg_AWVALID_17 <= Dbg_WVALID(17);
Dbg_AWREADY_I(17) <= Dbg_AWREADY_17;
Dbg_WDATA_17 <= Dbg_WDATA;
Dbg_WVALID_17 <= Dbg_AWVALID(17);
Dbg_WREADY_I(17) <= Dbg_WREADY_17;
Dbg_BRESP_I(17) <= Dbg_BRESP_17;
Dbg_BVALID_I(17) <= Dbg_BVALID_17;
Dbg_BREADY_17 <= Dbg_BREADY(17);
Dbg_ARADDR_17 <= Dbg_ARADDR;
Dbg_ARVALID_17 <= Dbg_ARVALID(17);
Dbg_ARREADY_I(17) <= Dbg_ARREADY_17;
Dbg_RDATA_I(17) <= Dbg_RDATA_17;
Dbg_RRESP_I(17) <= Dbg_RRESP_17;
Dbg_RVALID_I(17) <= Dbg_RVALID_17;
Dbg_RREADY_17 <= Dbg_RREADY(17);
Dbg_AWADDR_18 <= Dbg_AWADDR;
Dbg_AWVALID_18 <= Dbg_WVALID(18);
Dbg_AWREADY_I(18) <= Dbg_AWREADY_18;
Dbg_WDATA_18 <= Dbg_WDATA;
Dbg_WVALID_18 <= Dbg_AWVALID(18);
Dbg_WREADY_I(18) <= Dbg_WREADY_18;
Dbg_BRESP_I(18) <= Dbg_BRESP_18;
Dbg_BVALID_I(18) <= Dbg_BVALID_18;
Dbg_BREADY_18 <= Dbg_BREADY(18);
Dbg_ARADDR_18 <= Dbg_ARADDR;
Dbg_ARVALID_18 <= Dbg_ARVALID(18);
Dbg_ARREADY_I(18) <= Dbg_ARREADY_18;
Dbg_RDATA_I(18) <= Dbg_RDATA_18;
Dbg_RRESP_I(18) <= Dbg_RRESP_18;
Dbg_RVALID_I(18) <= Dbg_RVALID_18;
Dbg_RREADY_18 <= Dbg_RREADY(18);
Dbg_AWADDR_19 <= Dbg_AWADDR;
Dbg_AWVALID_19 <= Dbg_WVALID(19);
Dbg_AWREADY_I(19) <= Dbg_AWREADY_19;
Dbg_WDATA_19 <= Dbg_WDATA;
Dbg_WVALID_19 <= Dbg_AWVALID(19);
Dbg_WREADY_I(19) <= Dbg_WREADY_19;
Dbg_BRESP_I(19) <= Dbg_BRESP_19;
Dbg_BVALID_I(19) <= Dbg_BVALID_19;
Dbg_BREADY_19 <= Dbg_BREADY(19);
Dbg_ARADDR_19 <= Dbg_ARADDR;
Dbg_ARVALID_19 <= Dbg_ARVALID(19);
Dbg_ARREADY_I(19) <= Dbg_ARREADY_19;
Dbg_RDATA_I(19) <= Dbg_RDATA_19;
Dbg_RRESP_I(19) <= Dbg_RRESP_19;
Dbg_RVALID_I(19) <= Dbg_RVALID_19;
Dbg_RREADY_19 <= Dbg_RREADY(19);
Dbg_AWADDR_20 <= Dbg_AWADDR;
Dbg_AWVALID_20 <= Dbg_WVALID(20);
Dbg_AWREADY_I(20) <= Dbg_AWREADY_20;
Dbg_WDATA_20 <= Dbg_WDATA;
Dbg_WVALID_20 <= Dbg_AWVALID(20);
Dbg_WREADY_I(20) <= Dbg_WREADY_20;
Dbg_BRESP_I(20) <= Dbg_BRESP_20;
Dbg_BVALID_I(20) <= Dbg_BVALID_20;
Dbg_BREADY_20 <= Dbg_BREADY(20);
Dbg_ARADDR_20 <= Dbg_ARADDR;
Dbg_ARVALID_20 <= Dbg_ARVALID(20);
Dbg_ARREADY_I(20) <= Dbg_ARREADY_20;
Dbg_RDATA_I(20) <= Dbg_RDATA_20;
Dbg_RRESP_I(20) <= Dbg_RRESP_20;
Dbg_RVALID_I(20) <= Dbg_RVALID_20;
Dbg_RREADY_20 <= Dbg_RREADY(20);
Dbg_AWADDR_21 <= Dbg_AWADDR;
Dbg_AWVALID_21 <= Dbg_WVALID(21);
Dbg_AWREADY_I(21) <= Dbg_AWREADY_21;
Dbg_WDATA_21 <= Dbg_WDATA;
Dbg_WVALID_21 <= Dbg_AWVALID(21);
Dbg_WREADY_I(21) <= Dbg_WREADY_21;
Dbg_BRESP_I(21) <= Dbg_BRESP_21;
Dbg_BVALID_I(21) <= Dbg_BVALID_21;
Dbg_BREADY_21 <= Dbg_BREADY(21);
Dbg_ARADDR_21 <= Dbg_ARADDR;
Dbg_ARVALID_21 <= Dbg_ARVALID(21);
Dbg_ARREADY_I(21) <= Dbg_ARREADY_21;
Dbg_RDATA_I(21) <= Dbg_RDATA_21;
Dbg_RRESP_I(21) <= Dbg_RRESP_21;
Dbg_RVALID_I(21) <= Dbg_RVALID_21;
Dbg_RREADY_21 <= Dbg_RREADY(21);
Dbg_AWADDR_22 <= Dbg_AWADDR;
Dbg_AWVALID_22 <= Dbg_WVALID(22);
Dbg_AWREADY_I(22) <= Dbg_AWREADY_22;
Dbg_WDATA_22 <= Dbg_WDATA;
Dbg_WVALID_22 <= Dbg_AWVALID(22);
Dbg_WREADY_I(22) <= Dbg_WREADY_22;
Dbg_BRESP_I(22) <= Dbg_BRESP_22;
Dbg_BVALID_I(22) <= Dbg_BVALID_22;
Dbg_BREADY_22 <= Dbg_BREADY(22);
Dbg_ARADDR_22 <= Dbg_ARADDR;
Dbg_ARVALID_22 <= Dbg_ARVALID(22);
Dbg_ARREADY_I(22) <= Dbg_ARREADY_22;
Dbg_RDATA_I(22) <= Dbg_RDATA_22;
Dbg_RRESP_I(22) <= Dbg_RRESP_22;
Dbg_RVALID_I(22) <= Dbg_RVALID_22;
Dbg_RREADY_22 <= Dbg_RREADY(22);
Dbg_AWADDR_23 <= Dbg_AWADDR;
Dbg_AWVALID_23 <= Dbg_WVALID(23);
Dbg_AWREADY_I(23) <= Dbg_AWREADY_23;
Dbg_WDATA_23 <= Dbg_WDATA;
Dbg_WVALID_23 <= Dbg_AWVALID(23);
Dbg_WREADY_I(23) <= Dbg_WREADY_23;
Dbg_BRESP_I(23) <= Dbg_BRESP_23;
Dbg_BVALID_I(23) <= Dbg_BVALID_23;
Dbg_BREADY_23 <= Dbg_BREADY(23);
Dbg_ARADDR_23 <= Dbg_ARADDR;
Dbg_ARVALID_23 <= Dbg_ARVALID(23);
Dbg_ARREADY_I(23) <= Dbg_ARREADY_23;
Dbg_RDATA_I(23) <= Dbg_RDATA_23;
Dbg_RRESP_I(23) <= Dbg_RRESP_23;
Dbg_RVALID_I(23) <= Dbg_RVALID_23;
Dbg_RREADY_23 <= Dbg_RREADY(23);
Dbg_AWADDR_24 <= Dbg_AWADDR;
Dbg_AWVALID_24 <= Dbg_WVALID(24);
Dbg_AWREADY_I(24) <= Dbg_AWREADY_24;
Dbg_WDATA_24 <= Dbg_WDATA;
Dbg_WVALID_24 <= Dbg_AWVALID(24);
Dbg_WREADY_I(24) <= Dbg_WREADY_24;
Dbg_BRESP_I(24) <= Dbg_BRESP_24;
Dbg_BVALID_I(24) <= Dbg_BVALID_24;
Dbg_BREADY_24 <= Dbg_BREADY(24);
Dbg_ARADDR_24 <= Dbg_ARADDR;
Dbg_ARVALID_24 <= Dbg_ARVALID(24);
Dbg_ARREADY_I(24) <= Dbg_ARREADY_24;
Dbg_RDATA_I(24) <= Dbg_RDATA_24;
Dbg_RRESP_I(24) <= Dbg_RRESP_24;
Dbg_RVALID_I(24) <= Dbg_RVALID_24;
Dbg_RREADY_24 <= Dbg_RREADY(24);
Dbg_AWADDR_25 <= Dbg_AWADDR;
Dbg_AWVALID_25 <= Dbg_WVALID(25);
Dbg_AWREADY_I(25) <= Dbg_AWREADY_25;
Dbg_WDATA_25 <= Dbg_WDATA;
Dbg_WVALID_25 <= Dbg_AWVALID(25);
Dbg_WREADY_I(25) <= Dbg_WREADY_25;
Dbg_BRESP_I(25) <= Dbg_BRESP_25;
Dbg_BVALID_I(25) <= Dbg_BVALID_25;
Dbg_BREADY_25 <= Dbg_BREADY(25);
Dbg_ARADDR_25 <= Dbg_ARADDR;
Dbg_ARVALID_25 <= Dbg_ARVALID(25);
Dbg_ARREADY_I(25) <= Dbg_ARREADY_25;
Dbg_RDATA_I(25) <= Dbg_RDATA_25;
Dbg_RRESP_I(25) <= Dbg_RRESP_25;
Dbg_RVALID_I(25) <= Dbg_RVALID_25;
Dbg_RREADY_25 <= Dbg_RREADY(25);
Dbg_AWADDR_26 <= Dbg_AWADDR;
Dbg_AWVALID_26 <= Dbg_WVALID(26);
Dbg_AWREADY_I(26) <= Dbg_AWREADY_26;
Dbg_WDATA_26 <= Dbg_WDATA;
Dbg_WVALID_26 <= Dbg_AWVALID(26);
Dbg_WREADY_I(26) <= Dbg_WREADY_26;
Dbg_BRESP_I(26) <= Dbg_BRESP_26;
Dbg_BVALID_I(26) <= Dbg_BVALID_26;
Dbg_BREADY_26 <= Dbg_BREADY(26);
Dbg_ARADDR_26 <= Dbg_ARADDR;
Dbg_ARVALID_26 <= Dbg_ARVALID(26);
Dbg_ARREADY_I(26) <= Dbg_ARREADY_26;
Dbg_RDATA_I(26) <= Dbg_RDATA_26;
Dbg_RRESP_I(26) <= Dbg_RRESP_26;
Dbg_RVALID_I(26) <= Dbg_RVALID_26;
Dbg_RREADY_26 <= Dbg_RREADY(26);
Dbg_AWADDR_27 <= Dbg_AWADDR;
Dbg_AWVALID_27 <= Dbg_WVALID(27);
Dbg_AWREADY_I(27) <= Dbg_AWREADY_27;
Dbg_WDATA_27 <= Dbg_WDATA;
Dbg_WVALID_27 <= Dbg_AWVALID(27);
Dbg_WREADY_I(27) <= Dbg_WREADY_27;
Dbg_BRESP_I(27) <= Dbg_BRESP_27;
Dbg_BVALID_I(27) <= Dbg_BVALID_27;
Dbg_BREADY_27 <= Dbg_BREADY(27);
Dbg_ARADDR_27 <= Dbg_ARADDR;
Dbg_ARVALID_27 <= Dbg_ARVALID(27);
Dbg_ARREADY_I(27) <= Dbg_ARREADY_27;
Dbg_RDATA_I(27) <= Dbg_RDATA_27;
Dbg_RRESP_I(27) <= Dbg_RRESP_27;
Dbg_RVALID_I(27) <= Dbg_RVALID_27;
Dbg_RREADY_27 <= Dbg_RREADY(27);
Dbg_AWADDR_28 <= Dbg_AWADDR;
Dbg_AWVALID_28 <= Dbg_WVALID(28);
Dbg_AWREADY_I(28) <= Dbg_AWREADY_28;
Dbg_WDATA_28 <= Dbg_WDATA;
Dbg_WVALID_28 <= Dbg_AWVALID(28);
Dbg_WREADY_I(28) <= Dbg_WREADY_28;
Dbg_BRESP_I(28) <= Dbg_BRESP_28;
Dbg_BVALID_I(28) <= Dbg_BVALID_28;
Dbg_BREADY_28 <= Dbg_BREADY(28);
Dbg_ARADDR_28 <= Dbg_ARADDR;
Dbg_ARVALID_28 <= Dbg_ARVALID(28);
Dbg_ARREADY_I(28) <= Dbg_ARREADY_28;
Dbg_RDATA_I(28) <= Dbg_RDATA_28;
Dbg_RRESP_I(28) <= Dbg_RRESP_28;
Dbg_RVALID_I(28) <= Dbg_RVALID_28;
Dbg_RREADY_28 <= Dbg_RREADY(28);
Dbg_AWADDR_29 <= Dbg_AWADDR;
Dbg_AWVALID_29 <= Dbg_WVALID(29);
Dbg_AWREADY_I(29) <= Dbg_AWREADY_29;
Dbg_WDATA_29 <= Dbg_WDATA;
Dbg_WVALID_29 <= Dbg_AWVALID(29);
Dbg_WREADY_I(29) <= Dbg_WREADY_29;
Dbg_BRESP_I(29) <= Dbg_BRESP_29;
Dbg_BVALID_I(29) <= Dbg_BVALID_29;
Dbg_BREADY_29 <= Dbg_BREADY(29);
Dbg_ARADDR_29 <= Dbg_ARADDR;
Dbg_ARVALID_29 <= Dbg_ARVALID(29);
Dbg_ARREADY_I(29) <= Dbg_ARREADY_29;
Dbg_RDATA_I(29) <= Dbg_RDATA_29;
Dbg_RRESP_I(29) <= Dbg_RRESP_29;
Dbg_RVALID_I(29) <= Dbg_RVALID_29;
Dbg_RREADY_29 <= Dbg_RREADY(29);
Dbg_AWADDR_30 <= Dbg_AWADDR;
Dbg_AWVALID_30 <= Dbg_WVALID(30);
Dbg_AWREADY_I(30) <= Dbg_AWREADY_30;
Dbg_WDATA_30 <= Dbg_WDATA;
Dbg_WVALID_30 <= Dbg_AWVALID(30);
Dbg_WREADY_I(30) <= Dbg_WREADY_30;
Dbg_BRESP_I(30) <= Dbg_BRESP_30;
Dbg_BVALID_I(30) <= Dbg_BVALID_30;
Dbg_BREADY_30 <= Dbg_BREADY(30);
Dbg_ARADDR_30 <= Dbg_ARADDR;
Dbg_ARVALID_30 <= Dbg_ARVALID(30);
Dbg_ARREADY_I(30) <= Dbg_ARREADY_30;
Dbg_RDATA_I(30) <= Dbg_RDATA_30;
Dbg_RRESP_I(30) <= Dbg_RRESP_30;
Dbg_RVALID_I(30) <= Dbg_RVALID_30;
Dbg_RREADY_30 <= Dbg_RREADY(30);
Dbg_AWADDR_31 <= Dbg_AWADDR;
Dbg_AWVALID_31 <= Dbg_WVALID(31);
Dbg_AWREADY_I(31) <= Dbg_AWREADY_31;
Dbg_WDATA_31 <= Dbg_WDATA;
Dbg_WVALID_31 <= Dbg_AWVALID(31);
Dbg_WREADY_I(31) <= Dbg_WREADY_31;
Dbg_BRESP_I(31) <= Dbg_BRESP_31;
Dbg_BVALID_I(31) <= Dbg_BVALID_31;
Dbg_BREADY_31 <= Dbg_BREADY(31);
Dbg_ARADDR_31 <= Dbg_ARADDR;
Dbg_ARVALID_31 <= Dbg_ARVALID(31);
Dbg_ARREADY_I(31) <= Dbg_ARREADY_31;
Dbg_RDATA_I(31) <= Dbg_RDATA_31;
Dbg_RRESP_I(31) <= Dbg_RRESP_31;
Dbg_RVALID_I(31) <= Dbg_RVALID_31;
Dbg_RREADY_31 <= Dbg_RREADY(31);
-- Unused serial signals
Dbg_Reg_En_I <= (others => (others => '0'));
Dbg_Clk_0 <= '0';
Dbg_TDI_0 <= '0';
Dbg_TDO_I(0) <= '0';
Dbg_Reg_En_0 <= (others => '0');
Dbg_Capture_0 <= '0';
Dbg_Shift_0 <= '0';
Dbg_Update_0 <= '0';
Dbg_Clk_1 <= '0';
Dbg_TDI_1 <= '0';
Dbg_TDO_I(1) <= '0';
Dbg_Reg_En_1 <= (others => '0');
Dbg_Capture_1 <= '0';
Dbg_Shift_1 <= '0';
Dbg_Update_1 <= '0';
Dbg_Clk_2 <= '0';
Dbg_TDI_2 <= '0';
Dbg_TDO_I(2) <= '0';
Dbg_Reg_En_2 <= (others => '0');
Dbg_Capture_2 <= '0';
Dbg_Shift_2 <= '0';
Dbg_Update_2 <= '0';
Dbg_Clk_3 <= '0';
Dbg_TDI_3 <= '0';
Dbg_TDO_I(3) <= '0';
Dbg_Reg_En_3 <= (others => '0');
Dbg_Capture_3 <= '0';
Dbg_Shift_3 <= '0';
Dbg_Update_3 <= '0';
Dbg_Clk_4 <= '0';
Dbg_TDI_4 <= '0';
Dbg_TDO_I(4) <= '0';
Dbg_Reg_En_4 <= (others => '0');
Dbg_Capture_4 <= '0';
Dbg_Shift_4 <= '0';
Dbg_Update_4 <= '0';
Dbg_Clk_5 <= '0';
Dbg_TDI_5 <= '0';
Dbg_TDO_I(5) <= '0';
Dbg_Reg_En_5 <= (others => '0');
Dbg_Capture_5 <= '0';
Dbg_Shift_5 <= '0';
Dbg_Update_5 <= '0';
Dbg_Clk_6 <= '0';
Dbg_TDI_6 <= '0';
Dbg_TDO_I(6) <= '0';
Dbg_Reg_En_6 <= (others => '0');
Dbg_Capture_6 <= '0';
Dbg_Shift_6 <= '0';
Dbg_Update_6 <= '0';
Dbg_Clk_7 <= '0';
Dbg_TDI_7 <= '0';
Dbg_TDO_I(7) <= '0';
Dbg_Reg_En_7 <= (others => '0');
Dbg_Capture_7 <= '0';
Dbg_Shift_7 <= '0';
Dbg_Update_7 <= '0';
Dbg_Clk_8 <= '0';
Dbg_TDI_8 <= '0';
Dbg_TDO_I(8) <= '0';
Dbg_Reg_En_8 <= (others => '0');
Dbg_Capture_8 <= '0';
Dbg_Shift_8 <= '0';
Dbg_Update_8 <= '0';
Dbg_Clk_9 <= '0';
Dbg_TDI_9 <= '0';
Dbg_TDO_I(9) <= '0';
Dbg_Reg_En_9 <= (others => '0');
Dbg_Capture_9 <= '0';
Dbg_Shift_9 <= '0';
Dbg_Update_9 <= '0';
Dbg_Clk_10 <= '0';
Dbg_TDI_10 <= '0';
Dbg_TDO_I(10) <= '0';
Dbg_Reg_En_10 <= (others => '0');
Dbg_Capture_10 <= '0';
Dbg_Shift_10 <= '0';
Dbg_Update_10 <= '0';
Dbg_Clk_11 <= '0';
Dbg_TDI_11 <= '0';
Dbg_TDO_I(11) <= '0';
Dbg_Reg_En_11 <= (others => '0');
Dbg_Capture_11 <= '0';
Dbg_Shift_11 <= '0';
Dbg_Update_11 <= '0';
Dbg_Clk_12 <= '0';
Dbg_TDI_12 <= '0';
Dbg_TDO_I(12) <= '0';
Dbg_Reg_En_12 <= (others => '0');
Dbg_Capture_12 <= '0';
Dbg_Shift_12 <= '0';
Dbg_Update_12 <= '0';
Dbg_Clk_13 <= '0';
Dbg_TDI_13 <= '0';
Dbg_TDO_I(13) <= '0';
Dbg_Reg_En_13 <= (others => '0');
Dbg_Capture_13 <= '0';
Dbg_Shift_13 <= '0';
Dbg_Update_13 <= '0';
Dbg_Clk_14 <= '0';
Dbg_TDI_14 <= '0';
Dbg_TDO_I(14) <= '0';
Dbg_Reg_En_14 <= (others => '0');
Dbg_Capture_14 <= '0';
Dbg_Shift_14 <= '0';
Dbg_Update_14 <= '0';
Dbg_Clk_15 <= '0';
Dbg_TDI_15 <= '0';
Dbg_TDO_I(15) <= '0';
Dbg_Reg_En_15 <= (others => '0');
Dbg_Capture_15 <= '0';
Dbg_Shift_15 <= '0';
Dbg_Update_15 <= '0';
Dbg_Clk_16 <= '0';
Dbg_TDI_16 <= '0';
Dbg_TDO_I(16) <= '0';
Dbg_Reg_En_16 <= (others => '0');
Dbg_Capture_16 <= '0';
Dbg_Shift_16 <= '0';
Dbg_Update_16 <= '0';
Dbg_Clk_17 <= '0';
Dbg_TDI_17 <= '0';
Dbg_TDO_I(17) <= '0';
Dbg_Reg_En_17 <= (others => '0');
Dbg_Capture_17 <= '0';
Dbg_Shift_17 <= '0';
Dbg_Update_17 <= '0';
Dbg_Clk_18 <= '0';
Dbg_TDI_18 <= '0';
Dbg_TDO_I(18) <= '0';
Dbg_Reg_En_18 <= (others => '0');
Dbg_Capture_18 <= '0';
Dbg_Shift_18 <= '0';
Dbg_Update_18 <= '0';
Dbg_Clk_19 <= '0';
Dbg_TDI_19 <= '0';
Dbg_TDO_I(19) <= '0';
Dbg_Reg_En_19 <= (others => '0');
Dbg_Capture_19 <= '0';
Dbg_Shift_19 <= '0';
Dbg_Update_19 <= '0';
Dbg_Clk_20 <= '0';
Dbg_TDI_20 <= '0';
Dbg_TDO_I(20) <= '0';
Dbg_Reg_En_20 <= (others => '0');
Dbg_Capture_20 <= '0';
Dbg_Shift_20 <= '0';
Dbg_Update_20 <= '0';
Dbg_Clk_21 <= '0';
Dbg_TDI_21 <= '0';
Dbg_TDO_I(21) <= '0';
Dbg_Reg_En_21 <= (others => '0');
Dbg_Capture_21 <= '0';
Dbg_Shift_21 <= '0';
Dbg_Update_21 <= '0';
Dbg_Clk_22 <= '0';
Dbg_TDI_22 <= '0';
Dbg_TDO_I(22) <= '0';
Dbg_Reg_En_22 <= (others => '0');
Dbg_Capture_22 <= '0';
Dbg_Shift_22 <= '0';
Dbg_Update_22 <= '0';
Dbg_Clk_23 <= '0';
Dbg_TDI_23 <= '0';
Dbg_TDO_I(23) <= '0';
Dbg_Reg_En_23 <= (others => '0');
Dbg_Capture_23 <= '0';
Dbg_Shift_23 <= '0';
Dbg_Update_23 <= '0';
Dbg_Clk_24 <= '0';
Dbg_TDI_24 <= '0';
Dbg_TDO_I(24) <= '0';
Dbg_Reg_En_24 <= (others => '0');
Dbg_Capture_24 <= '0';
Dbg_Shift_24 <= '0';
Dbg_Update_24 <= '0';
Dbg_Clk_25 <= '0';
Dbg_TDI_25 <= '0';
Dbg_TDO_I(25) <= '0';
Dbg_Reg_En_25 <= (others => '0');
Dbg_Capture_25 <= '0';
Dbg_Shift_25 <= '0';
Dbg_Update_25 <= '0';
Dbg_Clk_26 <= '0';
Dbg_TDI_26 <= '0';
Dbg_TDO_I(26) <= '0';
Dbg_Reg_En_26 <= (others => '0');
Dbg_Capture_26 <= '0';
Dbg_Shift_26 <= '0';
Dbg_Update_26 <= '0';
Dbg_Clk_27 <= '0';
Dbg_TDI_27 <= '0';
Dbg_TDO_I(27) <= '0';
Dbg_Reg_En_27 <= (others => '0');
Dbg_Capture_27 <= '0';
Dbg_Shift_27 <= '0';
Dbg_Update_27 <= '0';
Dbg_Clk_28 <= '0';
Dbg_TDI_28 <= '0';
Dbg_TDO_I(28) <= '0';
Dbg_Reg_En_28 <= (others => '0');
Dbg_Capture_28 <= '0';
Dbg_Shift_28 <= '0';
Dbg_Update_28 <= '0';
Dbg_Clk_29 <= '0';
Dbg_TDI_29 <= '0';
Dbg_TDO_I(29) <= '0';
Dbg_Reg_En_29 <= (others => '0');
Dbg_Capture_29 <= '0';
Dbg_Shift_29 <= '0';
Dbg_Update_29 <= '0';
Dbg_Clk_30 <= '0';
Dbg_TDI_30 <= '0';
Dbg_TDO_I(30) <= '0';
Dbg_Reg_En_30 <= (others => '0');
Dbg_Capture_30 <= '0';
Dbg_Shift_30 <= '0';
Dbg_Update_30 <= '0';
Dbg_Clk_31 <= '0';
Dbg_TDI_31 <= '0';
Dbg_TDO_I(31) <= '0';
Dbg_Reg_En_31 <= (others => '0');
Dbg_Capture_31 <= '0';
Dbg_Shift_31 <= '0';
Dbg_Update_31 <= '0';
end generate Use_Parallel;
end architecture IMP;
-------------------------------------------------------------------------------
-- mdm.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2014,2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2006-10-27 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2012-12-14 Removed legacy interfaces
-- stefana 2013-11-01 Added extended debug: debug register access, debug
-- memory access, cross trigger support
-- stefana 2014-04-30 Added external trace support
-- stefana 2016-04-25 Added parallel synchronous debug interface
-- stefana 2016-06-01 Added wrappers for unisim primitives
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library mdm_v3_2_8;
use mdm_v3_2_8.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
entity MDM is
generic (
C_FAMILY : string := "virtex7";
C_JTAG_CHAIN : integer := 2;
C_USE_BSCAN : integer := 0;
C_USE_CONFIG_RESET : integer := 0;
C_INTERCONNECT : integer := 0;
C_DEBUG_INTERFACE : integer := 0;
C_MB_DBG_PORTS : integer := 1;
C_DBG_REG_ACCESS : integer := 0;
C_DBG_MEM_ACCESS : integer := 0;
C_USE_UART : integer := 1;
C_USE_CROSS_TRIGGER : integer := 0;
C_TRACE_OUTPUT : integer := 0;
C_TRACE_DATA_WIDTH : integer range 2 to 32 := 32;
C_TRACE_CLK_FREQ_HZ : integer := 200000000;
C_TRACE_CLK_OUT_PHASE : integer range 0 to 360 := 90;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_S_AXI_ADDR_WIDTH : integer range 4 to 16 := 4;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_DATA_SIZE : integer range 32 to 32 := 32;
C_M_AXIS_DATA_WIDTH : integer range 32 to 32 := 32;
C_M_AXIS_ID_WIDTH : integer range 1 to 7 := 7
);
port (
-- Global signals
Config_Reset : in std_logic := '0';
Scan_Reset_Sel : in std_logic := '0';
Scan_Reset : in std_logic := '0';
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- External cross trigger signals
Trig_In_0 : in std_logic;
Trig_Ack_In_0 : out std_logic;
Trig_Out_0 : out std_logic;
Trig_Ack_Out_0 : in std_logic;
Trig_In_1 : in std_logic;
Trig_Ack_In_1 : out std_logic;
Trig_Out_1 : out std_logic;
Trig_Ack_Out_1 : in std_logic;
Trig_In_2 : in std_logic;
Trig_Ack_In_2 : out std_logic;
Trig_Out_2 : out std_logic;
Trig_Ack_Out_2 : in std_logic;
Trig_In_3 : in std_logic;
Trig_Ack_In_3 : out std_logic;
Trig_Out_3 : out std_logic;
Trig_Ack_Out_3 : in std_logic;
-- AXI slave signals
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Bus master signals
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
LMB_Data_Addr_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_0 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_0 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_0 : out std_logic;
LMB_Read_Strobe_0 : out std_logic;
LMB_Write_Strobe_0 : out std_logic;
LMB_Ready_0 : in std_logic;
LMB_Wait_0 : in std_logic;
LMB_CE_0 : in std_logic;
LMB_UE_0 : in std_logic;
LMB_Byte_Enable_0 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_1 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_1 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_1 : out std_logic;
LMB_Read_Strobe_1 : out std_logic;
LMB_Write_Strobe_1 : out std_logic;
LMB_Ready_1 : in std_logic;
LMB_Wait_1 : in std_logic;
LMB_CE_1 : in std_logic;
LMB_UE_1 : in std_logic;
LMB_Byte_Enable_1 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_2 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_2 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_2 : out std_logic;
LMB_Read_Strobe_2 : out std_logic;
LMB_Write_Strobe_2 : out std_logic;
LMB_Ready_2 : in std_logic;
LMB_Wait_2 : in std_logic;
LMB_CE_2 : in std_logic;
LMB_UE_2 : in std_logic;
LMB_Byte_Enable_2 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_3 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_3 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_3 : out std_logic;
LMB_Read_Strobe_3 : out std_logic;
LMB_Write_Strobe_3 : out std_logic;
LMB_Ready_3 : in std_logic;
LMB_Wait_3 : in std_logic;
LMB_CE_3 : in std_logic;
LMB_UE_3 : in std_logic;
LMB_Byte_Enable_3 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_4 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_4 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_4 : out std_logic;
LMB_Read_Strobe_4 : out std_logic;
LMB_Write_Strobe_4 : out std_logic;
LMB_Ready_4 : in std_logic;
LMB_Wait_4 : in std_logic;
LMB_CE_4 : in std_logic;
LMB_UE_4 : in std_logic;
LMB_Byte_Enable_4 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_5 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_5 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_5 : out std_logic;
LMB_Read_Strobe_5 : out std_logic;
LMB_Write_Strobe_5 : out std_logic;
LMB_Ready_5 : in std_logic;
LMB_Wait_5 : in std_logic;
LMB_CE_5 : in std_logic;
LMB_UE_5 : in std_logic;
LMB_Byte_Enable_5 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_6 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_6 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_6 : out std_logic;
LMB_Read_Strobe_6 : out std_logic;
LMB_Write_Strobe_6 : out std_logic;
LMB_Ready_6 : in std_logic;
LMB_Wait_6 : in std_logic;
LMB_CE_6 : in std_logic;
LMB_UE_6 : in std_logic;
LMB_Byte_Enable_6 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_7 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_7 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_7 : out std_logic;
LMB_Read_Strobe_7 : out std_logic;
LMB_Write_Strobe_7 : out std_logic;
LMB_Ready_7 : in std_logic;
LMB_Wait_7 : in std_logic;
LMB_CE_7 : in std_logic;
LMB_UE_7 : in std_logic;
LMB_Byte_Enable_7 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_8 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_8 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_8 : out std_logic;
LMB_Read_Strobe_8 : out std_logic;
LMB_Write_Strobe_8 : out std_logic;
LMB_Ready_8 : in std_logic;
LMB_Wait_8 : in std_logic;
LMB_CE_8 : in std_logic;
LMB_UE_8 : in std_logic;
LMB_Byte_Enable_8 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_9 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_9 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_9 : out std_logic;
LMB_Read_Strobe_9 : out std_logic;
LMB_Write_Strobe_9 : out std_logic;
LMB_Ready_9 : in std_logic;
LMB_Wait_9 : in std_logic;
LMB_CE_9 : in std_logic;
LMB_UE_9 : in std_logic;
LMB_Byte_Enable_9 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_10 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_10 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_10 : out std_logic;
LMB_Read_Strobe_10 : out std_logic;
LMB_Write_Strobe_10 : out std_logic;
LMB_Ready_10 : in std_logic;
LMB_Wait_10 : in std_logic;
LMB_CE_10 : in std_logic;
LMB_UE_10 : in std_logic;
LMB_Byte_Enable_10 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_11 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_11 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_11 : out std_logic;
LMB_Read_Strobe_11 : out std_logic;
LMB_Write_Strobe_11 : out std_logic;
LMB_Ready_11 : in std_logic;
LMB_Wait_11 : in std_logic;
LMB_CE_11 : in std_logic;
LMB_UE_11 : in std_logic;
LMB_Byte_Enable_11 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_12 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_12 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_12 : out std_logic;
LMB_Read_Strobe_12 : out std_logic;
LMB_Write_Strobe_12 : out std_logic;
LMB_Ready_12 : in std_logic;
LMB_Wait_12 : in std_logic;
LMB_CE_12 : in std_logic;
LMB_UE_12 : in std_logic;
LMB_Byte_Enable_12 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_13 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_13 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_13 : out std_logic;
LMB_Read_Strobe_13 : out std_logic;
LMB_Write_Strobe_13 : out std_logic;
LMB_Ready_13 : in std_logic;
LMB_Wait_13 : in std_logic;
LMB_CE_13 : in std_logic;
LMB_UE_13 : in std_logic;
LMB_Byte_Enable_13 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_14 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_14 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_14 : out std_logic;
LMB_Read_Strobe_14 : out std_logic;
LMB_Write_Strobe_14 : out std_logic;
LMB_Ready_14 : in std_logic;
LMB_Wait_14 : in std_logic;
LMB_CE_14 : in std_logic;
LMB_UE_14 : in std_logic;
LMB_Byte_Enable_14 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_15 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_15 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_15 : out std_logic;
LMB_Read_Strobe_15 : out std_logic;
LMB_Write_Strobe_15 : out std_logic;
LMB_Ready_15 : in std_logic;
LMB_Wait_15 : in std_logic;
LMB_CE_15 : in std_logic;
LMB_UE_15 : in std_logic;
LMB_Byte_Enable_15 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_16 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_16 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_16 : out std_logic;
LMB_Read_Strobe_16 : out std_logic;
LMB_Write_Strobe_16 : out std_logic;
LMB_Ready_16 : in std_logic;
LMB_Wait_16 : in std_logic;
LMB_CE_16 : in std_logic;
LMB_UE_16 : in std_logic;
LMB_Byte_Enable_16 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_17 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_17 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_17 : out std_logic;
LMB_Read_Strobe_17 : out std_logic;
LMB_Write_Strobe_17 : out std_logic;
LMB_Ready_17 : in std_logic;
LMB_Wait_17 : in std_logic;
LMB_CE_17 : in std_logic;
LMB_UE_17 : in std_logic;
LMB_Byte_Enable_17 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_18 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_18 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_18 : out std_logic;
LMB_Read_Strobe_18 : out std_logic;
LMB_Write_Strobe_18 : out std_logic;
LMB_Ready_18 : in std_logic;
LMB_Wait_18 : in std_logic;
LMB_CE_18 : in std_logic;
LMB_UE_18 : in std_logic;
LMB_Byte_Enable_18 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_19 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_19 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_19 : out std_logic;
LMB_Read_Strobe_19 : out std_logic;
LMB_Write_Strobe_19 : out std_logic;
LMB_Ready_19 : in std_logic;
LMB_Wait_19 : in std_logic;
LMB_CE_19 : in std_logic;
LMB_UE_19 : in std_logic;
LMB_Byte_Enable_19 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_20 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_20 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_20 : out std_logic;
LMB_Read_Strobe_20 : out std_logic;
LMB_Write_Strobe_20 : out std_logic;
LMB_Ready_20 : in std_logic;
LMB_Wait_20 : in std_logic;
LMB_CE_20 : in std_logic;
LMB_UE_20 : in std_logic;
LMB_Byte_Enable_20 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_21 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_21 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_21 : out std_logic;
LMB_Read_Strobe_21 : out std_logic;
LMB_Write_Strobe_21 : out std_logic;
LMB_Ready_21 : in std_logic;
LMB_Wait_21 : in std_logic;
LMB_CE_21 : in std_logic;
LMB_UE_21 : in std_logic;
LMB_Byte_Enable_21 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_22 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_22 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_22 : out std_logic;
LMB_Read_Strobe_22 : out std_logic;
LMB_Write_Strobe_22 : out std_logic;
LMB_Ready_22 : in std_logic;
LMB_Wait_22 : in std_logic;
LMB_CE_22 : in std_logic;
LMB_UE_22 : in std_logic;
LMB_Byte_Enable_22 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_23 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_23 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_23 : out std_logic;
LMB_Read_Strobe_23 : out std_logic;
LMB_Write_Strobe_23 : out std_logic;
LMB_Ready_23 : in std_logic;
LMB_Wait_23 : in std_logic;
LMB_CE_23 : in std_logic;
LMB_UE_23 : in std_logic;
LMB_Byte_Enable_23 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_24 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_24 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_24 : out std_logic;
LMB_Read_Strobe_24 : out std_logic;
LMB_Write_Strobe_24 : out std_logic;
LMB_Ready_24 : in std_logic;
LMB_Wait_24 : in std_logic;
LMB_CE_24 : in std_logic;
LMB_UE_24 : in std_logic;
LMB_Byte_Enable_24 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_25 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_25 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_25 : out std_logic;
LMB_Read_Strobe_25 : out std_logic;
LMB_Write_Strobe_25 : out std_logic;
LMB_Ready_25 : in std_logic;
LMB_Wait_25 : in std_logic;
LMB_CE_25 : in std_logic;
LMB_UE_25 : in std_logic;
LMB_Byte_Enable_25 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_26 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_26 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_26 : out std_logic;
LMB_Read_Strobe_26 : out std_logic;
LMB_Write_Strobe_26 : out std_logic;
LMB_Ready_26 : in std_logic;
LMB_Wait_26 : in std_logic;
LMB_CE_26 : in std_logic;
LMB_UE_26 : in std_logic;
LMB_Byte_Enable_26 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_27 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_27 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_27 : out std_logic;
LMB_Read_Strobe_27 : out std_logic;
LMB_Write_Strobe_27 : out std_logic;
LMB_Ready_27 : in std_logic;
LMB_Wait_27 : in std_logic;
LMB_CE_27 : in std_logic;
LMB_UE_27 : in std_logic;
LMB_Byte_Enable_27 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_28 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_28 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_28 : out std_logic;
LMB_Read_Strobe_28 : out std_logic;
LMB_Write_Strobe_28 : out std_logic;
LMB_Ready_28 : in std_logic;
LMB_Wait_28 : in std_logic;
LMB_CE_28 : in std_logic;
LMB_UE_28 : in std_logic;
LMB_Byte_Enable_28 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_29 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_29 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_29 : out std_logic;
LMB_Read_Strobe_29 : out std_logic;
LMB_Write_Strobe_29 : out std_logic;
LMB_Ready_29 : in std_logic;
LMB_Wait_29 : in std_logic;
LMB_CE_29 : in std_logic;
LMB_UE_29 : in std_logic;
LMB_Byte_Enable_29 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_30 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_30 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_30 : out std_logic;
LMB_Read_Strobe_30 : out std_logic;
LMB_Write_Strobe_30 : out std_logic;
LMB_Ready_30 : in std_logic;
LMB_Wait_30 : in std_logic;
LMB_CE_30 : in std_logic;
LMB_UE_30 : in std_logic;
LMB_Byte_Enable_30 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
LMB_Data_Addr_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read_31 : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write_31 : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe_31 : out std_logic;
LMB_Read_Strobe_31 : out std_logic;
LMB_Write_Strobe_31 : out std_logic;
LMB_Ready_31 : in std_logic;
LMB_Wait_31 : in std_logic;
LMB_CE_31 : in std_logic;
LMB_UE_31 : in std_logic;
LMB_Byte_Enable_31 : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Disable_0 : out std_logic;
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_AWADDR_0 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_0 : out std_logic;
Dbg_AWREADY_0 : in std_logic;
Dbg_WDATA_0 : out std_logic_vector(31 downto 0);
Dbg_WVALID_0 : out std_logic;
Dbg_WREADY_0 : in std_logic;
Dbg_BRESP_0 : in std_logic_vector(1 downto 0);
Dbg_BVALID_0 : in std_logic;
Dbg_BREADY_0 : out std_logic;
Dbg_ARADDR_0 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_0 : out std_logic;
Dbg_ARREADY_0 : in std_logic;
Dbg_RDATA_0 : in std_logic_vector(31 downto 0);
Dbg_RRESP_0 : in std_logic_vector(1 downto 0);
Dbg_RVALID_0 : in std_logic;
Dbg_RREADY_0 : out std_logic;
Dbg_Disable_1 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_AWADDR_1 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_1 : out std_logic;
Dbg_AWREADY_1 : in std_logic;
Dbg_WDATA_1 : out std_logic_vector(31 downto 0);
Dbg_WVALID_1 : out std_logic;
Dbg_WREADY_1 : in std_logic;
Dbg_BRESP_1 : in std_logic_vector(1 downto 0);
Dbg_BVALID_1 : in std_logic;
Dbg_BREADY_1 : out std_logic;
Dbg_ARADDR_1 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_1 : out std_logic;
Dbg_ARREADY_1 : in std_logic;
Dbg_RDATA_1 : in std_logic_vector(31 downto 0);
Dbg_RRESP_1 : in std_logic_vector(1 downto 0);
Dbg_RVALID_1 : in std_logic;
Dbg_RREADY_1 : out std_logic;
Dbg_Disable_2 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_AWADDR_2 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_2 : out std_logic;
Dbg_AWREADY_2 : in std_logic;
Dbg_WDATA_2 : out std_logic_vector(31 downto 0);
Dbg_WVALID_2 : out std_logic;
Dbg_WREADY_2 : in std_logic;
Dbg_BRESP_2 : in std_logic_vector(1 downto 0);
Dbg_BVALID_2 : in std_logic;
Dbg_BREADY_2 : out std_logic;
Dbg_ARADDR_2 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_2 : out std_logic;
Dbg_ARREADY_2 : in std_logic;
Dbg_RDATA_2 : in std_logic_vector(31 downto 0);
Dbg_RRESP_2 : in std_logic_vector(1 downto 0);
Dbg_RVALID_2 : in std_logic;
Dbg_RREADY_2 : out std_logic;
Dbg_Disable_3 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_AWADDR_3 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_3 : out std_logic;
Dbg_AWREADY_3 : in std_logic;
Dbg_WDATA_3 : out std_logic_vector(31 downto 0);
Dbg_WVALID_3 : out std_logic;
Dbg_WREADY_3 : in std_logic;
Dbg_BRESP_3 : in std_logic_vector(1 downto 0);
Dbg_BVALID_3 : in std_logic;
Dbg_BREADY_3 : out std_logic;
Dbg_ARADDR_3 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_3 : out std_logic;
Dbg_ARREADY_3 : in std_logic;
Dbg_RDATA_3 : in std_logic_vector(31 downto 0);
Dbg_RRESP_3 : in std_logic_vector(1 downto 0);
Dbg_RVALID_3 : in std_logic;
Dbg_RREADY_3 : out std_logic;
Dbg_Disable_4 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_AWADDR_4 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_4 : out std_logic;
Dbg_AWREADY_4 : in std_logic;
Dbg_WDATA_4 : out std_logic_vector(31 downto 0);
Dbg_WVALID_4 : out std_logic;
Dbg_WREADY_4 : in std_logic;
Dbg_BRESP_4 : in std_logic_vector(1 downto 0);
Dbg_BVALID_4 : in std_logic;
Dbg_BREADY_4 : out std_logic;
Dbg_ARADDR_4 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_4 : out std_logic;
Dbg_ARREADY_4 : in std_logic;
Dbg_RDATA_4 : in std_logic_vector(31 downto 0);
Dbg_RRESP_4 : in std_logic_vector(1 downto 0);
Dbg_RVALID_4 : in std_logic;
Dbg_RREADY_4 : out std_logic;
Dbg_Disable_5 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_AWADDR_5 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_5 : out std_logic;
Dbg_AWREADY_5 : in std_logic;
Dbg_WDATA_5 : out std_logic_vector(31 downto 0);
Dbg_WVALID_5 : out std_logic;
Dbg_WREADY_5 : in std_logic;
Dbg_BRESP_5 : in std_logic_vector(1 downto 0);
Dbg_BVALID_5 : in std_logic;
Dbg_BREADY_5 : out std_logic;
Dbg_ARADDR_5 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_5 : out std_logic;
Dbg_ARREADY_5 : in std_logic;
Dbg_RDATA_5 : in std_logic_vector(31 downto 0);
Dbg_RRESP_5 : in std_logic_vector(1 downto 0);
Dbg_RVALID_5 : in std_logic;
Dbg_RREADY_5 : out std_logic;
Dbg_Disable_6 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_AWADDR_6 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_6 : out std_logic;
Dbg_AWREADY_6 : in std_logic;
Dbg_WDATA_6 : out std_logic_vector(31 downto 0);
Dbg_WVALID_6 : out std_logic;
Dbg_WREADY_6 : in std_logic;
Dbg_BRESP_6 : in std_logic_vector(1 downto 0);
Dbg_BVALID_6 : in std_logic;
Dbg_BREADY_6 : out std_logic;
Dbg_ARADDR_6 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_6 : out std_logic;
Dbg_ARREADY_6 : in std_logic;
Dbg_RDATA_6 : in std_logic_vector(31 downto 0);
Dbg_RRESP_6 : in std_logic_vector(1 downto 0);
Dbg_RVALID_6 : in std_logic;
Dbg_RREADY_6 : out std_logic;
Dbg_Disable_7 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_AWADDR_7 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_7 : out std_logic;
Dbg_AWREADY_7 : in std_logic;
Dbg_WDATA_7 : out std_logic_vector(31 downto 0);
Dbg_WVALID_7 : out std_logic;
Dbg_WREADY_7 : in std_logic;
Dbg_BRESP_7 : in std_logic_vector(1 downto 0);
Dbg_BVALID_7 : in std_logic;
Dbg_BREADY_7 : out std_logic;
Dbg_ARADDR_7 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_7 : out std_logic;
Dbg_ARREADY_7 : in std_logic;
Dbg_RDATA_7 : in std_logic_vector(31 downto 0);
Dbg_RRESP_7 : in std_logic_vector(1 downto 0);
Dbg_RVALID_7 : in std_logic;
Dbg_RREADY_7 : out std_logic;
Dbg_Disable_8 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_AWADDR_8 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_8 : out std_logic;
Dbg_AWREADY_8 : in std_logic;
Dbg_WDATA_8 : out std_logic_vector(31 downto 0);
Dbg_WVALID_8 : out std_logic;
Dbg_WREADY_8 : in std_logic;
Dbg_BRESP_8 : in std_logic_vector(1 downto 0);
Dbg_BVALID_8 : in std_logic;
Dbg_BREADY_8 : out std_logic;
Dbg_ARADDR_8 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_8 : out std_logic;
Dbg_ARREADY_8 : in std_logic;
Dbg_RDATA_8 : in std_logic_vector(31 downto 0);
Dbg_RRESP_8 : in std_logic_vector(1 downto 0);
Dbg_RVALID_8 : in std_logic;
Dbg_RREADY_8 : out std_logic;
Dbg_Disable_9 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_AWADDR_9 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_9 : out std_logic;
Dbg_AWREADY_9 : in std_logic;
Dbg_WDATA_9 : out std_logic_vector(31 downto 0);
Dbg_WVALID_9 : out std_logic;
Dbg_WREADY_9 : in std_logic;
Dbg_BRESP_9 : in std_logic_vector(1 downto 0);
Dbg_BVALID_9 : in std_logic;
Dbg_BREADY_9 : out std_logic;
Dbg_ARADDR_9 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_9 : out std_logic;
Dbg_ARREADY_9 : in std_logic;
Dbg_RDATA_9 : in std_logic_vector(31 downto 0);
Dbg_RRESP_9 : in std_logic_vector(1 downto 0);
Dbg_RVALID_9 : in std_logic;
Dbg_RREADY_9 : out std_logic;
Dbg_Disable_10 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_AWADDR_10 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_10 : out std_logic;
Dbg_AWREADY_10 : in std_logic;
Dbg_WDATA_10 : out std_logic_vector(31 downto 0);
Dbg_WVALID_10 : out std_logic;
Dbg_WREADY_10 : in std_logic;
Dbg_BRESP_10 : in std_logic_vector(1 downto 0);
Dbg_BVALID_10 : in std_logic;
Dbg_BREADY_10 : out std_logic;
Dbg_ARADDR_10 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_10 : out std_logic;
Dbg_ARREADY_10 : in std_logic;
Dbg_RDATA_10 : in std_logic_vector(31 downto 0);
Dbg_RRESP_10 : in std_logic_vector(1 downto 0);
Dbg_RVALID_10 : in std_logic;
Dbg_RREADY_10 : out std_logic;
Dbg_Disable_11 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_AWADDR_11 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_11 : out std_logic;
Dbg_AWREADY_11 : in std_logic;
Dbg_WDATA_11 : out std_logic_vector(31 downto 0);
Dbg_WVALID_11 : out std_logic;
Dbg_WREADY_11 : in std_logic;
Dbg_BRESP_11 : in std_logic_vector(1 downto 0);
Dbg_BVALID_11 : in std_logic;
Dbg_BREADY_11 : out std_logic;
Dbg_ARADDR_11 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_11 : out std_logic;
Dbg_ARREADY_11 : in std_logic;
Dbg_RDATA_11 : in std_logic_vector(31 downto 0);
Dbg_RRESP_11 : in std_logic_vector(1 downto 0);
Dbg_RVALID_11 : in std_logic;
Dbg_RREADY_11 : out std_logic;
Dbg_Disable_12 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_AWADDR_12 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_12 : out std_logic;
Dbg_AWREADY_12 : in std_logic;
Dbg_WDATA_12 : out std_logic_vector(31 downto 0);
Dbg_WVALID_12 : out std_logic;
Dbg_WREADY_12 : in std_logic;
Dbg_BRESP_12 : in std_logic_vector(1 downto 0);
Dbg_BVALID_12 : in std_logic;
Dbg_BREADY_12 : out std_logic;
Dbg_ARADDR_12 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_12 : out std_logic;
Dbg_ARREADY_12 : in std_logic;
Dbg_RDATA_12 : in std_logic_vector(31 downto 0);
Dbg_RRESP_12 : in std_logic_vector(1 downto 0);
Dbg_RVALID_12 : in std_logic;
Dbg_RREADY_12 : out std_logic;
Dbg_Disable_13 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_AWADDR_13 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_13 : out std_logic;
Dbg_AWREADY_13 : in std_logic;
Dbg_WDATA_13 : out std_logic_vector(31 downto 0);
Dbg_WVALID_13 : out std_logic;
Dbg_WREADY_13 : in std_logic;
Dbg_BRESP_13 : in std_logic_vector(1 downto 0);
Dbg_BVALID_13 : in std_logic;
Dbg_BREADY_13 : out std_logic;
Dbg_ARADDR_13 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_13 : out std_logic;
Dbg_ARREADY_13 : in std_logic;
Dbg_RDATA_13 : in std_logic_vector(31 downto 0);
Dbg_RRESP_13 : in std_logic_vector(1 downto 0);
Dbg_RVALID_13 : in std_logic;
Dbg_RREADY_13 : out std_logic;
Dbg_Disable_14 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_AWADDR_14 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_14 : out std_logic;
Dbg_AWREADY_14 : in std_logic;
Dbg_WDATA_14 : out std_logic_vector(31 downto 0);
Dbg_WVALID_14 : out std_logic;
Dbg_WREADY_14 : in std_logic;
Dbg_BRESP_14 : in std_logic_vector(1 downto 0);
Dbg_BVALID_14 : in std_logic;
Dbg_BREADY_14 : out std_logic;
Dbg_ARADDR_14 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_14 : out std_logic;
Dbg_ARREADY_14 : in std_logic;
Dbg_RDATA_14 : in std_logic_vector(31 downto 0);
Dbg_RRESP_14 : in std_logic_vector(1 downto 0);
Dbg_RVALID_14 : in std_logic;
Dbg_RREADY_14 : out std_logic;
Dbg_Disable_15 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_AWADDR_15 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_15 : out std_logic;
Dbg_AWREADY_15 : in std_logic;
Dbg_WDATA_15 : out std_logic_vector(31 downto 0);
Dbg_WVALID_15 : out std_logic;
Dbg_WREADY_15 : in std_logic;
Dbg_BRESP_15 : in std_logic_vector(1 downto 0);
Dbg_BVALID_15 : in std_logic;
Dbg_BREADY_15 : out std_logic;
Dbg_ARADDR_15 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_15 : out std_logic;
Dbg_ARREADY_15 : in std_logic;
Dbg_RDATA_15 : in std_logic_vector(31 downto 0);
Dbg_RRESP_15 : in std_logic_vector(1 downto 0);
Dbg_RVALID_15 : in std_logic;
Dbg_RREADY_15 : out std_logic;
Dbg_Disable_16 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_AWADDR_16 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_16 : out std_logic;
Dbg_AWREADY_16 : in std_logic;
Dbg_WDATA_16 : out std_logic_vector(31 downto 0);
Dbg_WVALID_16 : out std_logic;
Dbg_WREADY_16 : in std_logic;
Dbg_BRESP_16 : in std_logic_vector(1 downto 0);
Dbg_BVALID_16 : in std_logic;
Dbg_BREADY_16 : out std_logic;
Dbg_ARADDR_16 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_16 : out std_logic;
Dbg_ARREADY_16 : in std_logic;
Dbg_RDATA_16 : in std_logic_vector(31 downto 0);
Dbg_RRESP_16 : in std_logic_vector(1 downto 0);
Dbg_RVALID_16 : in std_logic;
Dbg_RREADY_16 : out std_logic;
Dbg_Disable_17 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_AWADDR_17 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_17 : out std_logic;
Dbg_AWREADY_17 : in std_logic;
Dbg_WDATA_17 : out std_logic_vector(31 downto 0);
Dbg_WVALID_17 : out std_logic;
Dbg_WREADY_17 : in std_logic;
Dbg_BRESP_17 : in std_logic_vector(1 downto 0);
Dbg_BVALID_17 : in std_logic;
Dbg_BREADY_17 : out std_logic;
Dbg_ARADDR_17 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_17 : out std_logic;
Dbg_ARREADY_17 : in std_logic;
Dbg_RDATA_17 : in std_logic_vector(31 downto 0);
Dbg_RRESP_17 : in std_logic_vector(1 downto 0);
Dbg_RVALID_17 : in std_logic;
Dbg_RREADY_17 : out std_logic;
Dbg_Disable_18 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_AWADDR_18 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_18 : out std_logic;
Dbg_AWREADY_18 : in std_logic;
Dbg_WDATA_18 : out std_logic_vector(31 downto 0);
Dbg_WVALID_18 : out std_logic;
Dbg_WREADY_18 : in std_logic;
Dbg_BRESP_18 : in std_logic_vector(1 downto 0);
Dbg_BVALID_18 : in std_logic;
Dbg_BREADY_18 : out std_logic;
Dbg_ARADDR_18 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_18 : out std_logic;
Dbg_ARREADY_18 : in std_logic;
Dbg_RDATA_18 : in std_logic_vector(31 downto 0);
Dbg_RRESP_18 : in std_logic_vector(1 downto 0);
Dbg_RVALID_18 : in std_logic;
Dbg_RREADY_18 : out std_logic;
Dbg_Disable_19 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_AWADDR_19 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_19 : out std_logic;
Dbg_AWREADY_19 : in std_logic;
Dbg_WDATA_19 : out std_logic_vector(31 downto 0);
Dbg_WVALID_19 : out std_logic;
Dbg_WREADY_19 : in std_logic;
Dbg_BRESP_19 : in std_logic_vector(1 downto 0);
Dbg_BVALID_19 : in std_logic;
Dbg_BREADY_19 : out std_logic;
Dbg_ARADDR_19 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_19 : out std_logic;
Dbg_ARREADY_19 : in std_logic;
Dbg_RDATA_19 : in std_logic_vector(31 downto 0);
Dbg_RRESP_19 : in std_logic_vector(1 downto 0);
Dbg_RVALID_19 : in std_logic;
Dbg_RREADY_19 : out std_logic;
Dbg_Disable_20 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_AWADDR_20 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_20 : out std_logic;
Dbg_AWREADY_20 : in std_logic;
Dbg_WDATA_20 : out std_logic_vector(31 downto 0);
Dbg_WVALID_20 : out std_logic;
Dbg_WREADY_20 : in std_logic;
Dbg_BRESP_20 : in std_logic_vector(1 downto 0);
Dbg_BVALID_20 : in std_logic;
Dbg_BREADY_20 : out std_logic;
Dbg_ARADDR_20 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_20 : out std_logic;
Dbg_ARREADY_20 : in std_logic;
Dbg_RDATA_20 : in std_logic_vector(31 downto 0);
Dbg_RRESP_20 : in std_logic_vector(1 downto 0);
Dbg_RVALID_20 : in std_logic;
Dbg_RREADY_20 : out std_logic;
Dbg_Disable_21 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_AWADDR_21 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_21 : out std_logic;
Dbg_AWREADY_21 : in std_logic;
Dbg_WDATA_21 : out std_logic_vector(31 downto 0);
Dbg_WVALID_21 : out std_logic;
Dbg_WREADY_21 : in std_logic;
Dbg_BRESP_21 : in std_logic_vector(1 downto 0);
Dbg_BVALID_21 : in std_logic;
Dbg_BREADY_21 : out std_logic;
Dbg_ARADDR_21 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_21 : out std_logic;
Dbg_ARREADY_21 : in std_logic;
Dbg_RDATA_21 : in std_logic_vector(31 downto 0);
Dbg_RRESP_21 : in std_logic_vector(1 downto 0);
Dbg_RVALID_21 : in std_logic;
Dbg_RREADY_21 : out std_logic;
Dbg_Disable_22 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_AWADDR_22 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_22 : out std_logic;
Dbg_AWREADY_22 : in std_logic;
Dbg_WDATA_22 : out std_logic_vector(31 downto 0);
Dbg_WVALID_22 : out std_logic;
Dbg_WREADY_22 : in std_logic;
Dbg_BRESP_22 : in std_logic_vector(1 downto 0);
Dbg_BVALID_22 : in std_logic;
Dbg_BREADY_22 : out std_logic;
Dbg_ARADDR_22 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_22 : out std_logic;
Dbg_ARREADY_22 : in std_logic;
Dbg_RDATA_22 : in std_logic_vector(31 downto 0);
Dbg_RRESP_22 : in std_logic_vector(1 downto 0);
Dbg_RVALID_22 : in std_logic;
Dbg_RREADY_22 : out std_logic;
Dbg_Disable_23 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_AWADDR_23 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_23 : out std_logic;
Dbg_AWREADY_23 : in std_logic;
Dbg_WDATA_23 : out std_logic_vector(31 downto 0);
Dbg_WVALID_23 : out std_logic;
Dbg_WREADY_23 : in std_logic;
Dbg_BRESP_23 : in std_logic_vector(1 downto 0);
Dbg_BVALID_23 : in std_logic;
Dbg_BREADY_23 : out std_logic;
Dbg_ARADDR_23 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_23 : out std_logic;
Dbg_ARREADY_23 : in std_logic;
Dbg_RDATA_23 : in std_logic_vector(31 downto 0);
Dbg_RRESP_23 : in std_logic_vector(1 downto 0);
Dbg_RVALID_23 : in std_logic;
Dbg_RREADY_23 : out std_logic;
Dbg_Disable_24 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_AWADDR_24 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_24 : out std_logic;
Dbg_AWREADY_24 : in std_logic;
Dbg_WDATA_24 : out std_logic_vector(31 downto 0);
Dbg_WVALID_24 : out std_logic;
Dbg_WREADY_24 : in std_logic;
Dbg_BRESP_24 : in std_logic_vector(1 downto 0);
Dbg_BVALID_24 : in std_logic;
Dbg_BREADY_24 : out std_logic;
Dbg_ARADDR_24 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_24 : out std_logic;
Dbg_ARREADY_24 : in std_logic;
Dbg_RDATA_24 : in std_logic_vector(31 downto 0);
Dbg_RRESP_24 : in std_logic_vector(1 downto 0);
Dbg_RVALID_24 : in std_logic;
Dbg_RREADY_24 : out std_logic;
Dbg_Disable_25 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_AWADDR_25 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_25 : out std_logic;
Dbg_AWREADY_25 : in std_logic;
Dbg_WDATA_25 : out std_logic_vector(31 downto 0);
Dbg_WVALID_25 : out std_logic;
Dbg_WREADY_25 : in std_logic;
Dbg_BRESP_25 : in std_logic_vector(1 downto 0);
Dbg_BVALID_25 : in std_logic;
Dbg_BREADY_25 : out std_logic;
Dbg_ARADDR_25 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_25 : out std_logic;
Dbg_ARREADY_25 : in std_logic;
Dbg_RDATA_25 : in std_logic_vector(31 downto 0);
Dbg_RRESP_25 : in std_logic_vector(1 downto 0);
Dbg_RVALID_25 : in std_logic;
Dbg_RREADY_25 : out std_logic;
Dbg_Disable_26 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_AWADDR_26 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_26 : out std_logic;
Dbg_AWREADY_26 : in std_logic;
Dbg_WDATA_26 : out std_logic_vector(31 downto 0);
Dbg_WVALID_26 : out std_logic;
Dbg_WREADY_26 : in std_logic;
Dbg_BRESP_26 : in std_logic_vector(1 downto 0);
Dbg_BVALID_26 : in std_logic;
Dbg_BREADY_26 : out std_logic;
Dbg_ARADDR_26 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_26 : out std_logic;
Dbg_ARREADY_26 : in std_logic;
Dbg_RDATA_26 : in std_logic_vector(31 downto 0);
Dbg_RRESP_26 : in std_logic_vector(1 downto 0);
Dbg_RVALID_26 : in std_logic;
Dbg_RREADY_26 : out std_logic;
Dbg_Disable_27 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_AWADDR_27 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_27 : out std_logic;
Dbg_AWREADY_27 : in std_logic;
Dbg_WDATA_27 : out std_logic_vector(31 downto 0);
Dbg_WVALID_27 : out std_logic;
Dbg_WREADY_27 : in std_logic;
Dbg_BRESP_27 : in std_logic_vector(1 downto 0);
Dbg_BVALID_27 : in std_logic;
Dbg_BREADY_27 : out std_logic;
Dbg_ARADDR_27 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_27 : out std_logic;
Dbg_ARREADY_27 : in std_logic;
Dbg_RDATA_27 : in std_logic_vector(31 downto 0);
Dbg_RRESP_27 : in std_logic_vector(1 downto 0);
Dbg_RVALID_27 : in std_logic;
Dbg_RREADY_27 : out std_logic;
Dbg_Disable_28 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_AWADDR_28 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_28 : out std_logic;
Dbg_AWREADY_28 : in std_logic;
Dbg_WDATA_28 : out std_logic_vector(31 downto 0);
Dbg_WVALID_28 : out std_logic;
Dbg_WREADY_28 : in std_logic;
Dbg_BRESP_28 : in std_logic_vector(1 downto 0);
Dbg_BVALID_28 : in std_logic;
Dbg_BREADY_28 : out std_logic;
Dbg_ARADDR_28 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_28 : out std_logic;
Dbg_ARREADY_28 : in std_logic;
Dbg_RDATA_28 : in std_logic_vector(31 downto 0);
Dbg_RRESP_28 : in std_logic_vector(1 downto 0);
Dbg_RVALID_28 : in std_logic;
Dbg_RREADY_28 : out std_logic;
Dbg_Disable_29 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_AWADDR_29 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_29 : out std_logic;
Dbg_AWREADY_29 : in std_logic;
Dbg_WDATA_29 : out std_logic_vector(31 downto 0);
Dbg_WVALID_29 : out std_logic;
Dbg_WREADY_29 : in std_logic;
Dbg_BRESP_29 : in std_logic_vector(1 downto 0);
Dbg_BVALID_29 : in std_logic;
Dbg_BREADY_29 : out std_logic;
Dbg_ARADDR_29 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_29 : out std_logic;
Dbg_ARREADY_29 : in std_logic;
Dbg_RDATA_29 : in std_logic_vector(31 downto 0);
Dbg_RRESP_29 : in std_logic_vector(1 downto 0);
Dbg_RVALID_29 : in std_logic;
Dbg_RREADY_29 : out std_logic;
Dbg_Disable_30 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_AWADDR_30 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_30 : out std_logic;
Dbg_AWREADY_30 : in std_logic;
Dbg_WDATA_30 : out std_logic_vector(31 downto 0);
Dbg_WVALID_30 : out std_logic;
Dbg_WREADY_30 : in std_logic;
Dbg_BRESP_30 : in std_logic_vector(1 downto 0);
Dbg_BVALID_30 : in std_logic;
Dbg_BREADY_30 : out std_logic;
Dbg_ARADDR_30 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_30 : out std_logic;
Dbg_ARREADY_30 : in std_logic;
Dbg_RDATA_30 : in std_logic_vector(31 downto 0);
Dbg_RRESP_30 : in std_logic_vector(1 downto 0);
Dbg_RVALID_30 : in std_logic;
Dbg_RREADY_30 : out std_logic;
Dbg_Disable_31 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
Dbg_AWADDR_31 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_31 : out std_logic;
Dbg_AWREADY_31 : in std_logic;
Dbg_WDATA_31 : out std_logic_vector(31 downto 0);
Dbg_WVALID_31 : out std_logic;
Dbg_WREADY_31 : in std_logic;
Dbg_BRESP_31 : in std_logic_vector(1 downto 0);
Dbg_BVALID_31 : in std_logic;
Dbg_BREADY_31 : out std_logic;
Dbg_ARADDR_31 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_31 : out std_logic;
Dbg_ARREADY_31 : in std_logic;
Dbg_RDATA_31 : in std_logic_vector(31 downto 0);
Dbg_RRESP_31 : in std_logic_vector(1 downto 0);
Dbg_RVALID_31 : in std_logic;
Dbg_RREADY_31 : out std_logic;
-- External BSCAN inputs
-- These signals are used when C_USE_BSCAN = 2 (EXTERNAL)
bscan_ext_tdi : in std_logic;
bscan_ext_reset : in std_logic;
bscan_ext_shift : in std_logic;
bscan_ext_update : in std_logic;
bscan_ext_capture : in std_logic;
bscan_ext_sel : in std_logic;
bscan_ext_drck : in std_logic;
bscan_ext_tdo : out std_logic;
-- External JTAG ports
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end entity MDM;
library mdm_v3_2_8;
use mdm_v3_2_8.mdm_funcs.all;
architecture IMP of MDM is
function bool2std (val : boolean) return std_logic is
begin -- function bool2std
if val then
return '1';
else
return '0';
end if;
end function bool2std;
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant C_TARGET : TARGET_FAMILY_TYPE := String_To_Family(C_FAMILY, false);
constant ZEROES : std_logic_vector(31 downto 0) := X"00000000";
constant C_REG_NUM_CE : integer := 4 + 4 * C_DBG_REG_ACCESS;
constant C_REG_DATA_WIDTH : integer := 8 + 24 * C_DBG_REG_ACCESS;
constant C_ARD_RANGES : integer := 1 + C_DEBUG_INTERFACE;
type S_AXI_MIN_SIZE_T is array(0 to 2) of std_logic_vector(31 downto 0);
constant C_S_AXI_MIN_SIZE_VEC : S_AXI_MIN_SIZE_T := ((X"0000000F", X"0000001F", X"00007FFF"));
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) :=
C_S_AXI_MIN_SIZE_VEC(boolean'pos(C_DBG_REG_ACCESS = 1));
constant C_S_AXI_MIN_SIZE_2 : std_logic_vector(31 downto 0) :=
C_S_AXI_MIN_SIZE_VEC(boolean'pos(C_DBG_REG_ACCESS = 1) +
boolean'pos(C_DBG_REG_ACCESS = 1 and C_DEBUG_INTERFACE = 1));
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
ZEROES & X"00000000",
ZEROES & C_S_AXI_MIN_SIZE,
ZEROES & X"00004000",
ZEROES & (X"00004000" or C_S_AXI_MIN_SIZE_2)
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
0 => C_REG_NUM_CE,
1 => 1
);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
constant C_TRACE_AXI_MASTER : boolean := C_TRACE_OUTPUT = 3;
--------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------
component MDM_Core
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_JTAG_CHAIN : integer;
C_USE_BSCAN : integer;
C_USE_CONFIG_RESET : integer := 0;
C_DEBUG_INTERFACE : integer;
C_MB_DBG_PORTS : integer;
C_EN_WIDTH : integer;
C_DBG_REG_ACCESS : integer;
C_REG_NUM_CE : integer;
C_REG_DATA_WIDTH : integer;
C_DBG_MEM_ACCESS : integer;
C_S_AXI_ADDR_WIDTH : integer;
C_S_AXI_ACLK_FREQ_HZ : integer;
C_M_AXI_ADDR_WIDTH : integer;
C_M_AXI_DATA_WIDTH : integer;
C_USE_CROSS_TRIGGER : integer;
C_USE_UART : integer;
C_UART_WIDTH : integer := 8;
C_TRACE_OUTPUT : integer;
C_TRACE_DATA_WIDTH : integer;
C_TRACE_CLK_FREQ_HZ : integer;
C_TRACE_CLK_OUT_PHASE : integer;
C_M_AXIS_DATA_WIDTH : integer;
C_M_AXIS_ID_WIDTH : integer);
port (
-- Global signals
Config_Reset : in std_logic;
Scan_Reset_Sel : in std_logic;
Scan_Reset : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
Interrupt : out std_logic;
Ext_BRK : out std_logic;
Ext_NM_BRK : out std_logic;
Debug_SYS_Rst : out std_logic;
-- Debug Register Access signals
DbgReg_DRCK : out std_logic;
DbgReg_UPDATE : out std_logic;
DbgReg_Select : out std_logic;
JTAG_Busy : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- AXI IPIC signals
bus2ip_clk : in std_logic;
bus2ip_resetn : in std_logic;
bus2ip_data : in std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
bus2ip_rdce : in std_logic_vector(0 to C_REG_NUM_CE+C_DEBUG_INTERFACE-1);
bus2ip_wrce : in std_logic_vector(0 to C_REG_NUM_CE+C_DEBUG_INTERFACE-1);
bus2ip_cs : in std_logic_vector(0 to C_DEBUG_INTERFACE);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
ip2bus_data : out std_logic_vector(C_REG_DATA_WIDTH-1 downto 0);
-- Bus Master signals
MB_Debug_Enabled : out std_logic_vector(C_EN_WIDTH-1 downto 0);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
Master_rd_start : out std_logic;
Master_rd_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_rd_len : out std_logic_vector(4 downto 0);
Master_rd_size : out std_logic_vector(1 downto 0);
Master_rd_excl : out std_logic;
Master_rd_idle : in std_logic;
Master_rd_resp : in std_logic_vector(1 downto 0);
Master_wr_start : out std_logic;
Master_wr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_wr_len : out std_logic_vector(4 downto 0);
Master_wr_size : out std_logic_vector(1 downto 0);
Master_wr_excl : out std_logic;
Master_wr_idle : in std_logic;
Master_wr_resp : in std_logic_vector(1 downto 0);
Master_data_rd : out std_logic;
Master_data_out : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_exists : in std_logic;
Master_data_wr : out std_logic;
Master_data_in : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_data_empty : in std_logic;
Master_dwr_addr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Master_dwr_len : out std_logic_vector(4 downto 0);
Master_dwr_data : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Master_dwr_start : out std_logic;
Master_dwr_next : in std_logic;
Master_dwr_done : in std_logic;
Master_dwr_resp : in std_logic_vector(1 downto 0);
-- JTAG signals
JTAG_TDI : in std_logic;
JTAG_RESET : in std_logic;
UPDATE : in std_logic;
JTAG_SHIFT : in std_logic;
JTAG_CAPTURE : in std_logic;
SEL : in std_logic;
DRCK : in std_logic;
JTAG_TDO : out std_logic;
-- External Trace AXI Stream output
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0);
M_AXIS_TID : out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0);
M_AXIS_TREADY : in std_logic;
M_AXIS_TVALID : out std_logic;
-- External Trace output
TRACE_CLK_OUT : out std_logic;
TRACE_CLK : in std_logic;
TRACE_CTL : out std_logic;
TRACE_DATA : out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0);
-- MicroBlaze Debug Signals
Dbg_Disable_0 : out std_logic;
Dbg_Clk_0 : out std_logic;
Dbg_TDI_0 : out std_logic;
Dbg_TDO_0 : in std_logic;
Dbg_Reg_En_0 : out std_logic_vector(0 to 7);
Dbg_Capture_0 : out std_logic;
Dbg_Shift_0 : out std_logic;
Dbg_Update_0 : out std_logic;
Dbg_Rst_0 : out std_logic;
Dbg_Trig_In_0 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_0 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_0 : in std_logic_vector(0 to 7);
Dbg_TrClk_0 : out std_logic;
Dbg_TrData_0 : in std_logic_vector(0 to 35);
Dbg_TrReady_0 : out std_logic;
Dbg_TrValid_0 : in std_logic;
Dbg_AWADDR_0 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_0 : out std_logic;
Dbg_AWREADY_0 : in std_logic;
Dbg_WDATA_0 : out std_logic_vector(31 downto 0);
Dbg_WVALID_0 : out std_logic;
Dbg_WREADY_0 : in std_logic;
Dbg_BRESP_0 : in std_logic_vector(1 downto 0);
Dbg_BVALID_0 : in std_logic;
Dbg_BREADY_0 : out std_logic;
Dbg_ARADDR_0 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_0 : out std_logic;
Dbg_ARREADY_0 : in std_logic;
Dbg_RDATA_0 : in std_logic_vector(31 downto 0);
Dbg_RRESP_0 : in std_logic_vector(1 downto 0);
Dbg_RVALID_0 : in std_logic;
Dbg_RREADY_0 : out std_logic;
Dbg_Disable_1 : out std_logic;
Dbg_Clk_1 : out std_logic;
Dbg_TDI_1 : out std_logic;
Dbg_TDO_1 : in std_logic;
Dbg_Reg_En_1 : out std_logic_vector(0 to 7);
Dbg_Capture_1 : out std_logic;
Dbg_Shift_1 : out std_logic;
Dbg_Update_1 : out std_logic;
Dbg_Rst_1 : out std_logic;
Dbg_Trig_In_1 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_1 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_1 : in std_logic_vector(0 to 7);
Dbg_TrClk_1 : out std_logic;
Dbg_TrData_1 : in std_logic_vector(0 to 35);
Dbg_TrReady_1 : out std_logic;
Dbg_TrValid_1 : in std_logic;
Dbg_AWADDR_1 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_1 : out std_logic;
Dbg_AWREADY_1 : in std_logic;
Dbg_WDATA_1 : out std_logic_vector(31 downto 0);
Dbg_WVALID_1 : out std_logic;
Dbg_WREADY_1 : in std_logic;
Dbg_BRESP_1 : in std_logic_vector(1 downto 0);
Dbg_BVALID_1 : in std_logic;
Dbg_BREADY_1 : out std_logic;
Dbg_ARADDR_1 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_1 : out std_logic;
Dbg_ARREADY_1 : in std_logic;
Dbg_RDATA_1 : in std_logic_vector(31 downto 0);
Dbg_RRESP_1 : in std_logic_vector(1 downto 0);
Dbg_RVALID_1 : in std_logic;
Dbg_RREADY_1 : out std_logic;
Dbg_Disable_2 : out std_logic;
Dbg_Clk_2 : out std_logic;
Dbg_TDI_2 : out std_logic;
Dbg_TDO_2 : in std_logic;
Dbg_Reg_En_2 : out std_logic_vector(0 to 7);
Dbg_Capture_2 : out std_logic;
Dbg_Shift_2 : out std_logic;
Dbg_Update_2 : out std_logic;
Dbg_Rst_2 : out std_logic;
Dbg_Trig_In_2 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_2 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_2 : in std_logic_vector(0 to 7);
Dbg_TrClk_2 : out std_logic;
Dbg_TrData_2 : in std_logic_vector(0 to 35);
Dbg_TrReady_2 : out std_logic;
Dbg_TrValid_2 : in std_logic;
Dbg_AWADDR_2 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_2 : out std_logic;
Dbg_AWREADY_2 : in std_logic;
Dbg_WDATA_2 : out std_logic_vector(31 downto 0);
Dbg_WVALID_2 : out std_logic;
Dbg_WREADY_2 : in std_logic;
Dbg_BRESP_2 : in std_logic_vector(1 downto 0);
Dbg_BVALID_2 : in std_logic;
Dbg_BREADY_2 : out std_logic;
Dbg_ARADDR_2 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_2 : out std_logic;
Dbg_ARREADY_2 : in std_logic;
Dbg_RDATA_2 : in std_logic_vector(31 downto 0);
Dbg_RRESP_2 : in std_logic_vector(1 downto 0);
Dbg_RVALID_2 : in std_logic;
Dbg_RREADY_2 : out std_logic;
Dbg_Disable_3 : out std_logic;
Dbg_Clk_3 : out std_logic;
Dbg_TDI_3 : out std_logic;
Dbg_TDO_3 : in std_logic;
Dbg_Reg_En_3 : out std_logic_vector(0 to 7);
Dbg_Capture_3 : out std_logic;
Dbg_Shift_3 : out std_logic;
Dbg_Update_3 : out std_logic;
Dbg_Rst_3 : out std_logic;
Dbg_Trig_In_3 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_3 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_3 : in std_logic_vector(0 to 7);
Dbg_TrClk_3 : out std_logic;
Dbg_TrData_3 : in std_logic_vector(0 to 35);
Dbg_TrReady_3 : out std_logic;
Dbg_TrValid_3 : in std_logic;
Dbg_AWADDR_3 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_3 : out std_logic;
Dbg_AWREADY_3 : in std_logic;
Dbg_WDATA_3 : out std_logic_vector(31 downto 0);
Dbg_WVALID_3 : out std_logic;
Dbg_WREADY_3 : in std_logic;
Dbg_BRESP_3 : in std_logic_vector(1 downto 0);
Dbg_BVALID_3 : in std_logic;
Dbg_BREADY_3 : out std_logic;
Dbg_ARADDR_3 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_3 : out std_logic;
Dbg_ARREADY_3 : in std_logic;
Dbg_RDATA_3 : in std_logic_vector(31 downto 0);
Dbg_RRESP_3 : in std_logic_vector(1 downto 0);
Dbg_RVALID_3 : in std_logic;
Dbg_RREADY_3 : out std_logic;
Dbg_Disable_4 : out std_logic;
Dbg_Clk_4 : out std_logic;
Dbg_TDI_4 : out std_logic;
Dbg_TDO_4 : in std_logic;
Dbg_Reg_En_4 : out std_logic_vector(0 to 7);
Dbg_Capture_4 : out std_logic;
Dbg_Shift_4 : out std_logic;
Dbg_Update_4 : out std_logic;
Dbg_Rst_4 : out std_logic;
Dbg_Trig_In_4 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_4 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_4 : in std_logic_vector(0 to 7);
Dbg_TrClk_4 : out std_logic;
Dbg_TrData_4 : in std_logic_vector(0 to 35);
Dbg_TrReady_4 : out std_logic;
Dbg_TrValid_4 : in std_logic;
Dbg_AWADDR_4 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_4 : out std_logic;
Dbg_AWREADY_4 : in std_logic;
Dbg_WDATA_4 : out std_logic_vector(31 downto 0);
Dbg_WVALID_4 : out std_logic;
Dbg_WREADY_4 : in std_logic;
Dbg_BRESP_4 : in std_logic_vector(1 downto 0);
Dbg_BVALID_4 : in std_logic;
Dbg_BREADY_4 : out std_logic;
Dbg_ARADDR_4 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_4 : out std_logic;
Dbg_ARREADY_4 : in std_logic;
Dbg_RDATA_4 : in std_logic_vector(31 downto 0);
Dbg_RRESP_4 : in std_logic_vector(1 downto 0);
Dbg_RVALID_4 : in std_logic;
Dbg_RREADY_4 : out std_logic;
Dbg_Disable_5 : out std_logic;
Dbg_Clk_5 : out std_logic;
Dbg_TDI_5 : out std_logic;
Dbg_TDO_5 : in std_logic;
Dbg_Reg_En_5 : out std_logic_vector(0 to 7);
Dbg_Capture_5 : out std_logic;
Dbg_Shift_5 : out std_logic;
Dbg_Update_5 : out std_logic;
Dbg_Rst_5 : out std_logic;
Dbg_Trig_In_5 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_5 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_5 : in std_logic_vector(0 to 7);
Dbg_TrClk_5 : out std_logic;
Dbg_TrData_5 : in std_logic_vector(0 to 35);
Dbg_TrReady_5 : out std_logic;
Dbg_TrValid_5 : in std_logic;
Dbg_AWADDR_5 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_5 : out std_logic;
Dbg_AWREADY_5 : in std_logic;
Dbg_WDATA_5 : out std_logic_vector(31 downto 0);
Dbg_WVALID_5 : out std_logic;
Dbg_WREADY_5 : in std_logic;
Dbg_BRESP_5 : in std_logic_vector(1 downto 0);
Dbg_BVALID_5 : in std_logic;
Dbg_BREADY_5 : out std_logic;
Dbg_ARADDR_5 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_5 : out std_logic;
Dbg_ARREADY_5 : in std_logic;
Dbg_RDATA_5 : in std_logic_vector(31 downto 0);
Dbg_RRESP_5 : in std_logic_vector(1 downto 0);
Dbg_RVALID_5 : in std_logic;
Dbg_RREADY_5 : out std_logic;
Dbg_Disable_6 : out std_logic;
Dbg_Clk_6 : out std_logic;
Dbg_TDI_6 : out std_logic;
Dbg_TDO_6 : in std_logic;
Dbg_Reg_En_6 : out std_logic_vector(0 to 7);
Dbg_Capture_6 : out std_logic;
Dbg_Shift_6 : out std_logic;
Dbg_Update_6 : out std_logic;
Dbg_Rst_6 : out std_logic;
Dbg_Trig_In_6 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_6 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_6 : in std_logic_vector(0 to 7);
Dbg_TrClk_6 : out std_logic;
Dbg_TrData_6 : in std_logic_vector(0 to 35);
Dbg_TrReady_6 : out std_logic;
Dbg_TrValid_6 : in std_logic;
Dbg_AWADDR_6 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_6 : out std_logic;
Dbg_AWREADY_6 : in std_logic;
Dbg_WDATA_6 : out std_logic_vector(31 downto 0);
Dbg_WVALID_6 : out std_logic;
Dbg_WREADY_6 : in std_logic;
Dbg_BRESP_6 : in std_logic_vector(1 downto 0);
Dbg_BVALID_6 : in std_logic;
Dbg_BREADY_6 : out std_logic;
Dbg_ARADDR_6 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_6 : out std_logic;
Dbg_ARREADY_6 : in std_logic;
Dbg_RDATA_6 : in std_logic_vector(31 downto 0);
Dbg_RRESP_6 : in std_logic_vector(1 downto 0);
Dbg_RVALID_6 : in std_logic;
Dbg_RREADY_6 : out std_logic;
Dbg_Disable_7 : out std_logic;
Dbg_Clk_7 : out std_logic;
Dbg_TDI_7 : out std_logic;
Dbg_TDO_7 : in std_logic;
Dbg_Reg_En_7 : out std_logic_vector(0 to 7);
Dbg_Capture_7 : out std_logic;
Dbg_Shift_7 : out std_logic;
Dbg_Update_7 : out std_logic;
Dbg_Rst_7 : out std_logic;
Dbg_Trig_In_7 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_7 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_7 : in std_logic_vector(0 to 7);
Dbg_TrClk_7 : out std_logic;
Dbg_TrData_7 : in std_logic_vector(0 to 35);
Dbg_TrReady_7 : out std_logic;
Dbg_TrValid_7 : in std_logic;
Dbg_AWADDR_7 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_7 : out std_logic;
Dbg_AWREADY_7 : in std_logic;
Dbg_WDATA_7 : out std_logic_vector(31 downto 0);
Dbg_WVALID_7 : out std_logic;
Dbg_WREADY_7 : in std_logic;
Dbg_BRESP_7 : in std_logic_vector(1 downto 0);
Dbg_BVALID_7 : in std_logic;
Dbg_BREADY_7 : out std_logic;
Dbg_ARADDR_7 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_7 : out std_logic;
Dbg_ARREADY_7 : in std_logic;
Dbg_RDATA_7 : in std_logic_vector(31 downto 0);
Dbg_RRESP_7 : in std_logic_vector(1 downto 0);
Dbg_RVALID_7 : in std_logic;
Dbg_RREADY_7 : out std_logic;
Dbg_Disable_8 : out std_logic;
Dbg_Clk_8 : out std_logic;
Dbg_TDI_8 : out std_logic;
Dbg_TDO_8 : in std_logic;
Dbg_Reg_En_8 : out std_logic_vector(0 to 7);
Dbg_Capture_8 : out std_logic;
Dbg_Shift_8 : out std_logic;
Dbg_Update_8 : out std_logic;
Dbg_Rst_8 : out std_logic;
Dbg_Trig_In_8 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_8 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_8 : in std_logic_vector(0 to 7);
Dbg_TrClk_8 : out std_logic;
Dbg_TrData_8 : in std_logic_vector(0 to 35);
Dbg_TrReady_8 : out std_logic;
Dbg_TrValid_8 : in std_logic;
Dbg_AWADDR_8 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_8 : out std_logic;
Dbg_AWREADY_8 : in std_logic;
Dbg_WDATA_8 : out std_logic_vector(31 downto 0);
Dbg_WVALID_8 : out std_logic;
Dbg_WREADY_8 : in std_logic;
Dbg_BRESP_8 : in std_logic_vector(1 downto 0);
Dbg_BVALID_8 : in std_logic;
Dbg_BREADY_8 : out std_logic;
Dbg_ARADDR_8 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_8 : out std_logic;
Dbg_ARREADY_8 : in std_logic;
Dbg_RDATA_8 : in std_logic_vector(31 downto 0);
Dbg_RRESP_8 : in std_logic_vector(1 downto 0);
Dbg_RVALID_8 : in std_logic;
Dbg_RREADY_8 : out std_logic;
Dbg_Disable_9 : out std_logic;
Dbg_Clk_9 : out std_logic;
Dbg_TDI_9 : out std_logic;
Dbg_TDO_9 : in std_logic;
Dbg_Reg_En_9 : out std_logic_vector(0 to 7);
Dbg_Capture_9 : out std_logic;
Dbg_Shift_9 : out std_logic;
Dbg_Update_9 : out std_logic;
Dbg_Rst_9 : out std_logic;
Dbg_Trig_In_9 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_9 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_9 : in std_logic_vector(0 to 7);
Dbg_TrClk_9 : out std_logic;
Dbg_TrData_9 : in std_logic_vector(0 to 35);
Dbg_TrReady_9 : out std_logic;
Dbg_TrValid_9 : in std_logic;
Dbg_AWADDR_9 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_9 : out std_logic;
Dbg_AWREADY_9 : in std_logic;
Dbg_WDATA_9 : out std_logic_vector(31 downto 0);
Dbg_WVALID_9 : out std_logic;
Dbg_WREADY_9 : in std_logic;
Dbg_BRESP_9 : in std_logic_vector(1 downto 0);
Dbg_BVALID_9 : in std_logic;
Dbg_BREADY_9 : out std_logic;
Dbg_ARADDR_9 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_9 : out std_logic;
Dbg_ARREADY_9 : in std_logic;
Dbg_RDATA_9 : in std_logic_vector(31 downto 0);
Dbg_RRESP_9 : in std_logic_vector(1 downto 0);
Dbg_RVALID_9 : in std_logic;
Dbg_RREADY_9 : out std_logic;
Dbg_Disable_10 : out std_logic;
Dbg_Clk_10 : out std_logic;
Dbg_TDI_10 : out std_logic;
Dbg_TDO_10 : in std_logic;
Dbg_Reg_En_10 : out std_logic_vector(0 to 7);
Dbg_Capture_10 : out std_logic;
Dbg_Shift_10 : out std_logic;
Dbg_Update_10 : out std_logic;
Dbg_Rst_10 : out std_logic;
Dbg_Trig_In_10 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_10 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_10 : in std_logic_vector(0 to 7);
Dbg_TrClk_10 : out std_logic;
Dbg_TrData_10 : in std_logic_vector(0 to 35);
Dbg_TrReady_10 : out std_logic;
Dbg_TrValid_10 : in std_logic;
Dbg_AWADDR_10 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_10 : out std_logic;
Dbg_AWREADY_10 : in std_logic;
Dbg_WDATA_10 : out std_logic_vector(31 downto 0);
Dbg_WVALID_10 : out std_logic;
Dbg_WREADY_10 : in std_logic;
Dbg_BRESP_10 : in std_logic_vector(1 downto 0);
Dbg_BVALID_10 : in std_logic;
Dbg_BREADY_10 : out std_logic;
Dbg_ARADDR_10 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_10 : out std_logic;
Dbg_ARREADY_10 : in std_logic;
Dbg_RDATA_10 : in std_logic_vector(31 downto 0);
Dbg_RRESP_10 : in std_logic_vector(1 downto 0);
Dbg_RVALID_10 : in std_logic;
Dbg_RREADY_10 : out std_logic;
Dbg_Disable_11 : out std_logic;
Dbg_Clk_11 : out std_logic;
Dbg_TDI_11 : out std_logic;
Dbg_TDO_11 : in std_logic;
Dbg_Reg_En_11 : out std_logic_vector(0 to 7);
Dbg_Capture_11 : out std_logic;
Dbg_Shift_11 : out std_logic;
Dbg_Update_11 : out std_logic;
Dbg_Rst_11 : out std_logic;
Dbg_Trig_In_11 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_11 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_11 : in std_logic_vector(0 to 7);
Dbg_TrClk_11 : out std_logic;
Dbg_TrData_11 : in std_logic_vector(0 to 35);
Dbg_TrReady_11 : out std_logic;
Dbg_TrValid_11 : in std_logic;
Dbg_AWADDR_11 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_11 : out std_logic;
Dbg_AWREADY_11 : in std_logic;
Dbg_WDATA_11 : out std_logic_vector(31 downto 0);
Dbg_WVALID_11 : out std_logic;
Dbg_WREADY_11 : in std_logic;
Dbg_BRESP_11 : in std_logic_vector(1 downto 0);
Dbg_BVALID_11 : in std_logic;
Dbg_BREADY_11 : out std_logic;
Dbg_ARADDR_11 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_11 : out std_logic;
Dbg_ARREADY_11 : in std_logic;
Dbg_RDATA_11 : in std_logic_vector(31 downto 0);
Dbg_RRESP_11 : in std_logic_vector(1 downto 0);
Dbg_RVALID_11 : in std_logic;
Dbg_RREADY_11 : out std_logic;
Dbg_Disable_12 : out std_logic;
Dbg_Clk_12 : out std_logic;
Dbg_TDI_12 : out std_logic;
Dbg_TDO_12 : in std_logic;
Dbg_Reg_En_12 : out std_logic_vector(0 to 7);
Dbg_Capture_12 : out std_logic;
Dbg_Shift_12 : out std_logic;
Dbg_Update_12 : out std_logic;
Dbg_Rst_12 : out std_logic;
Dbg_Trig_In_12 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_12 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_12 : in std_logic_vector(0 to 7);
Dbg_TrClk_12 : out std_logic;
Dbg_TrData_12 : in std_logic_vector(0 to 35);
Dbg_TrReady_12 : out std_logic;
Dbg_TrValid_12 : in std_logic;
Dbg_AWADDR_12 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_12 : out std_logic;
Dbg_AWREADY_12 : in std_logic;
Dbg_WDATA_12 : out std_logic_vector(31 downto 0);
Dbg_WVALID_12 : out std_logic;
Dbg_WREADY_12 : in std_logic;
Dbg_BRESP_12 : in std_logic_vector(1 downto 0);
Dbg_BVALID_12 : in std_logic;
Dbg_BREADY_12 : out std_logic;
Dbg_ARADDR_12 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_12 : out std_logic;
Dbg_ARREADY_12 : in std_logic;
Dbg_RDATA_12 : in std_logic_vector(31 downto 0);
Dbg_RRESP_12 : in std_logic_vector(1 downto 0);
Dbg_RVALID_12 : in std_logic;
Dbg_RREADY_12 : out std_logic;
Dbg_Disable_13 : out std_logic;
Dbg_Clk_13 : out std_logic;
Dbg_TDI_13 : out std_logic;
Dbg_TDO_13 : in std_logic;
Dbg_Reg_En_13 : out std_logic_vector(0 to 7);
Dbg_Capture_13 : out std_logic;
Dbg_Shift_13 : out std_logic;
Dbg_Update_13 : out std_logic;
Dbg_Rst_13 : out std_logic;
Dbg_Trig_In_13 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_13 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_13 : in std_logic_vector(0 to 7);
Dbg_TrClk_13 : out std_logic;
Dbg_TrData_13 : in std_logic_vector(0 to 35);
Dbg_TrReady_13 : out std_logic;
Dbg_TrValid_13 : in std_logic;
Dbg_AWADDR_13 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_13 : out std_logic;
Dbg_AWREADY_13 : in std_logic;
Dbg_WDATA_13 : out std_logic_vector(31 downto 0);
Dbg_WVALID_13 : out std_logic;
Dbg_WREADY_13 : in std_logic;
Dbg_BRESP_13 : in std_logic_vector(1 downto 0);
Dbg_BVALID_13 : in std_logic;
Dbg_BREADY_13 : out std_logic;
Dbg_ARADDR_13 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_13 : out std_logic;
Dbg_ARREADY_13 : in std_logic;
Dbg_RDATA_13 : in std_logic_vector(31 downto 0);
Dbg_RRESP_13 : in std_logic_vector(1 downto 0);
Dbg_RVALID_13 : in std_logic;
Dbg_RREADY_13 : out std_logic;
Dbg_Disable_14 : out std_logic;
Dbg_Clk_14 : out std_logic;
Dbg_TDI_14 : out std_logic;
Dbg_TDO_14 : in std_logic;
Dbg_Reg_En_14 : out std_logic_vector(0 to 7);
Dbg_Capture_14 : out std_logic;
Dbg_Shift_14 : out std_logic;
Dbg_Update_14 : out std_logic;
Dbg_Rst_14 : out std_logic;
Dbg_Trig_In_14 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_14 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_14 : in std_logic_vector(0 to 7);
Dbg_TrClk_14 : out std_logic;
Dbg_TrData_14 : in std_logic_vector(0 to 35);
Dbg_TrReady_14 : out std_logic;
Dbg_TrValid_14 : in std_logic;
Dbg_AWADDR_14 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_14 : out std_logic;
Dbg_AWREADY_14 : in std_logic;
Dbg_WDATA_14 : out std_logic_vector(31 downto 0);
Dbg_WVALID_14 : out std_logic;
Dbg_WREADY_14 : in std_logic;
Dbg_BRESP_14 : in std_logic_vector(1 downto 0);
Dbg_BVALID_14 : in std_logic;
Dbg_BREADY_14 : out std_logic;
Dbg_ARADDR_14 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_14 : out std_logic;
Dbg_ARREADY_14 : in std_logic;
Dbg_RDATA_14 : in std_logic_vector(31 downto 0);
Dbg_RRESP_14 : in std_logic_vector(1 downto 0);
Dbg_RVALID_14 : in std_logic;
Dbg_RREADY_14 : out std_logic;
Dbg_Disable_15 : out std_logic;
Dbg_Clk_15 : out std_logic;
Dbg_TDI_15 : out std_logic;
Dbg_TDO_15 : in std_logic;
Dbg_Reg_En_15 : out std_logic_vector(0 to 7);
Dbg_Capture_15 : out std_logic;
Dbg_Shift_15 : out std_logic;
Dbg_Update_15 : out std_logic;
Dbg_Rst_15 : out std_logic;
Dbg_Trig_In_15 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_15 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_15 : in std_logic_vector(0 to 7);
Dbg_TrClk_15 : out std_logic;
Dbg_TrData_15 : in std_logic_vector(0 to 35);
Dbg_TrReady_15 : out std_logic;
Dbg_TrValid_15 : in std_logic;
Dbg_AWADDR_15 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_15 : out std_logic;
Dbg_AWREADY_15 : in std_logic;
Dbg_WDATA_15 : out std_logic_vector(31 downto 0);
Dbg_WVALID_15 : out std_logic;
Dbg_WREADY_15 : in std_logic;
Dbg_BRESP_15 : in std_logic_vector(1 downto 0);
Dbg_BVALID_15 : in std_logic;
Dbg_BREADY_15 : out std_logic;
Dbg_ARADDR_15 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_15 : out std_logic;
Dbg_ARREADY_15 : in std_logic;
Dbg_RDATA_15 : in std_logic_vector(31 downto 0);
Dbg_RRESP_15 : in std_logic_vector(1 downto 0);
Dbg_RVALID_15 : in std_logic;
Dbg_RREADY_15 : out std_logic;
Dbg_Disable_16 : out std_logic;
Dbg_Clk_16 : out std_logic;
Dbg_TDI_16 : out std_logic;
Dbg_TDO_16 : in std_logic;
Dbg_Reg_En_16 : out std_logic_vector(0 to 7);
Dbg_Capture_16 : out std_logic;
Dbg_Shift_16 : out std_logic;
Dbg_Update_16 : out std_logic;
Dbg_Rst_16 : out std_logic;
Dbg_Trig_In_16 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_16 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_16 : in std_logic_vector(0 to 7);
Dbg_TrClk_16 : out std_logic;
Dbg_TrData_16 : in std_logic_vector(0 to 35);
Dbg_TrReady_16 : out std_logic;
Dbg_TrValid_16 : in std_logic;
Dbg_AWADDR_16 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_16 : out std_logic;
Dbg_AWREADY_16 : in std_logic;
Dbg_WDATA_16 : out std_logic_vector(31 downto 0);
Dbg_WVALID_16 : out std_logic;
Dbg_WREADY_16 : in std_logic;
Dbg_BRESP_16 : in std_logic_vector(1 downto 0);
Dbg_BVALID_16 : in std_logic;
Dbg_BREADY_16 : out std_logic;
Dbg_ARADDR_16 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_16 : out std_logic;
Dbg_ARREADY_16 : in std_logic;
Dbg_RDATA_16 : in std_logic_vector(31 downto 0);
Dbg_RRESP_16 : in std_logic_vector(1 downto 0);
Dbg_RVALID_16 : in std_logic;
Dbg_RREADY_16 : out std_logic;
Dbg_Disable_17 : out std_logic;
Dbg_Clk_17 : out std_logic;
Dbg_TDI_17 : out std_logic;
Dbg_TDO_17 : in std_logic;
Dbg_Reg_En_17 : out std_logic_vector(0 to 7);
Dbg_Capture_17 : out std_logic;
Dbg_Shift_17 : out std_logic;
Dbg_Update_17 : out std_logic;
Dbg_Rst_17 : out std_logic;
Dbg_Trig_In_17 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_17 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_17 : in std_logic_vector(0 to 7);
Dbg_TrClk_17 : out std_logic;
Dbg_TrData_17 : in std_logic_vector(0 to 35);
Dbg_TrReady_17 : out std_logic;
Dbg_TrValid_17 : in std_logic;
Dbg_AWADDR_17 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_17 : out std_logic;
Dbg_AWREADY_17 : in std_logic;
Dbg_WDATA_17 : out std_logic_vector(31 downto 0);
Dbg_WVALID_17 : out std_logic;
Dbg_WREADY_17 : in std_logic;
Dbg_BRESP_17 : in std_logic_vector(1 downto 0);
Dbg_BVALID_17 : in std_logic;
Dbg_BREADY_17 : out std_logic;
Dbg_ARADDR_17 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_17 : out std_logic;
Dbg_ARREADY_17 : in std_logic;
Dbg_RDATA_17 : in std_logic_vector(31 downto 0);
Dbg_RRESP_17 : in std_logic_vector(1 downto 0);
Dbg_RVALID_17 : in std_logic;
Dbg_RREADY_17 : out std_logic;
Dbg_Disable_18 : out std_logic;
Dbg_Clk_18 : out std_logic;
Dbg_TDI_18 : out std_logic;
Dbg_TDO_18 : in std_logic;
Dbg_Reg_En_18 : out std_logic_vector(0 to 7);
Dbg_Capture_18 : out std_logic;
Dbg_Shift_18 : out std_logic;
Dbg_Update_18 : out std_logic;
Dbg_Rst_18 : out std_logic;
Dbg_Trig_In_18 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_18 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_18 : in std_logic_vector(0 to 7);
Dbg_TrClk_18 : out std_logic;
Dbg_TrData_18 : in std_logic_vector(0 to 35);
Dbg_TrReady_18 : out std_logic;
Dbg_TrValid_18 : in std_logic;
Dbg_AWADDR_18 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_18 : out std_logic;
Dbg_AWREADY_18 : in std_logic;
Dbg_WDATA_18 : out std_logic_vector(31 downto 0);
Dbg_WVALID_18 : out std_logic;
Dbg_WREADY_18 : in std_logic;
Dbg_BRESP_18 : in std_logic_vector(1 downto 0);
Dbg_BVALID_18 : in std_logic;
Dbg_BREADY_18 : out std_logic;
Dbg_ARADDR_18 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_18 : out std_logic;
Dbg_ARREADY_18 : in std_logic;
Dbg_RDATA_18 : in std_logic_vector(31 downto 0);
Dbg_RRESP_18 : in std_logic_vector(1 downto 0);
Dbg_RVALID_18 : in std_logic;
Dbg_RREADY_18 : out std_logic;
Dbg_Disable_19 : out std_logic;
Dbg_Clk_19 : out std_logic;
Dbg_TDI_19 : out std_logic;
Dbg_TDO_19 : in std_logic;
Dbg_Reg_En_19 : out std_logic_vector(0 to 7);
Dbg_Capture_19 : out std_logic;
Dbg_Shift_19 : out std_logic;
Dbg_Update_19 : out std_logic;
Dbg_Rst_19 : out std_logic;
Dbg_Trig_In_19 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_19 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_19 : in std_logic_vector(0 to 7);
Dbg_TrClk_19 : out std_logic;
Dbg_TrData_19 : in std_logic_vector(0 to 35);
Dbg_TrReady_19 : out std_logic;
Dbg_TrValid_19 : in std_logic;
Dbg_AWADDR_19 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_19 : out std_logic;
Dbg_AWREADY_19 : in std_logic;
Dbg_WDATA_19 : out std_logic_vector(31 downto 0);
Dbg_WVALID_19 : out std_logic;
Dbg_WREADY_19 : in std_logic;
Dbg_BRESP_19 : in std_logic_vector(1 downto 0);
Dbg_BVALID_19 : in std_logic;
Dbg_BREADY_19 : out std_logic;
Dbg_ARADDR_19 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_19 : out std_logic;
Dbg_ARREADY_19 : in std_logic;
Dbg_RDATA_19 : in std_logic_vector(31 downto 0);
Dbg_RRESP_19 : in std_logic_vector(1 downto 0);
Dbg_RVALID_19 : in std_logic;
Dbg_RREADY_19 : out std_logic;
Dbg_Disable_20 : out std_logic;
Dbg_Clk_20 : out std_logic;
Dbg_TDI_20 : out std_logic;
Dbg_TDO_20 : in std_logic;
Dbg_Reg_En_20 : out std_logic_vector(0 to 7);
Dbg_Capture_20 : out std_logic;
Dbg_Shift_20 : out std_logic;
Dbg_Update_20 : out std_logic;
Dbg_Rst_20 : out std_logic;
Dbg_Trig_In_20 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_20 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_20 : in std_logic_vector(0 to 7);
Dbg_TrClk_20 : out std_logic;
Dbg_TrData_20 : in std_logic_vector(0 to 35);
Dbg_TrReady_20 : out std_logic;
Dbg_TrValid_20 : in std_logic;
Dbg_AWADDR_20 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_20 : out std_logic;
Dbg_AWREADY_20 : in std_logic;
Dbg_WDATA_20 : out std_logic_vector(31 downto 0);
Dbg_WVALID_20 : out std_logic;
Dbg_WREADY_20 : in std_logic;
Dbg_BRESP_20 : in std_logic_vector(1 downto 0);
Dbg_BVALID_20 : in std_logic;
Dbg_BREADY_20 : out std_logic;
Dbg_ARADDR_20 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_20 : out std_logic;
Dbg_ARREADY_20 : in std_logic;
Dbg_RDATA_20 : in std_logic_vector(31 downto 0);
Dbg_RRESP_20 : in std_logic_vector(1 downto 0);
Dbg_RVALID_20 : in std_logic;
Dbg_RREADY_20 : out std_logic;
Dbg_Disable_21 : out std_logic;
Dbg_Clk_21 : out std_logic;
Dbg_TDI_21 : out std_logic;
Dbg_TDO_21 : in std_logic;
Dbg_Reg_En_21 : out std_logic_vector(0 to 7);
Dbg_Capture_21 : out std_logic;
Dbg_Shift_21 : out std_logic;
Dbg_Update_21 : out std_logic;
Dbg_Rst_21 : out std_logic;
Dbg_Trig_In_21 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_21 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_21 : in std_logic_vector(0 to 7);
Dbg_TrClk_21 : out std_logic;
Dbg_TrData_21 : in std_logic_vector(0 to 35);
Dbg_TrReady_21 : out std_logic;
Dbg_TrValid_21 : in std_logic;
Dbg_AWADDR_21 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_21 : out std_logic;
Dbg_AWREADY_21 : in std_logic;
Dbg_WDATA_21 : out std_logic_vector(31 downto 0);
Dbg_WVALID_21 : out std_logic;
Dbg_WREADY_21 : in std_logic;
Dbg_BRESP_21 : in std_logic_vector(1 downto 0);
Dbg_BVALID_21 : in std_logic;
Dbg_BREADY_21 : out std_logic;
Dbg_ARADDR_21 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_21 : out std_logic;
Dbg_ARREADY_21 : in std_logic;
Dbg_RDATA_21 : in std_logic_vector(31 downto 0);
Dbg_RRESP_21 : in std_logic_vector(1 downto 0);
Dbg_RVALID_21 : in std_logic;
Dbg_RREADY_21 : out std_logic;
Dbg_Disable_22 : out std_logic;
Dbg_Clk_22 : out std_logic;
Dbg_TDI_22 : out std_logic;
Dbg_TDO_22 : in std_logic;
Dbg_Reg_En_22 : out std_logic_vector(0 to 7);
Dbg_Capture_22 : out std_logic;
Dbg_Shift_22 : out std_logic;
Dbg_Update_22 : out std_logic;
Dbg_Rst_22 : out std_logic;
Dbg_Trig_In_22 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_22 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_22 : in std_logic_vector(0 to 7);
Dbg_TrClk_22 : out std_logic;
Dbg_TrData_22 : in std_logic_vector(0 to 35);
Dbg_TrReady_22 : out std_logic;
Dbg_TrValid_22 : in std_logic;
Dbg_AWADDR_22 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_22 : out std_logic;
Dbg_AWREADY_22 : in std_logic;
Dbg_WDATA_22 : out std_logic_vector(31 downto 0);
Dbg_WVALID_22 : out std_logic;
Dbg_WREADY_22 : in std_logic;
Dbg_BRESP_22 : in std_logic_vector(1 downto 0);
Dbg_BVALID_22 : in std_logic;
Dbg_BREADY_22 : out std_logic;
Dbg_ARADDR_22 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_22 : out std_logic;
Dbg_ARREADY_22 : in std_logic;
Dbg_RDATA_22 : in std_logic_vector(31 downto 0);
Dbg_RRESP_22 : in std_logic_vector(1 downto 0);
Dbg_RVALID_22 : in std_logic;
Dbg_RREADY_22 : out std_logic;
Dbg_Disable_23 : out std_logic;
Dbg_Clk_23 : out std_logic;
Dbg_TDI_23 : out std_logic;
Dbg_TDO_23 : in std_logic;
Dbg_Reg_En_23 : out std_logic_vector(0 to 7);
Dbg_Capture_23 : out std_logic;
Dbg_Shift_23 : out std_logic;
Dbg_Update_23 : out std_logic;
Dbg_Rst_23 : out std_logic;
Dbg_Trig_In_23 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_23 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_23 : in std_logic_vector(0 to 7);
Dbg_TrClk_23 : out std_logic;
Dbg_TrData_23 : in std_logic_vector(0 to 35);
Dbg_TrReady_23 : out std_logic;
Dbg_TrValid_23 : in std_logic;
Dbg_AWADDR_23 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_23 : out std_logic;
Dbg_AWREADY_23 : in std_logic;
Dbg_WDATA_23 : out std_logic_vector(31 downto 0);
Dbg_WVALID_23 : out std_logic;
Dbg_WREADY_23 : in std_logic;
Dbg_BRESP_23 : in std_logic_vector(1 downto 0);
Dbg_BVALID_23 : in std_logic;
Dbg_BREADY_23 : out std_logic;
Dbg_ARADDR_23 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_23 : out std_logic;
Dbg_ARREADY_23 : in std_logic;
Dbg_RDATA_23 : in std_logic_vector(31 downto 0);
Dbg_RRESP_23 : in std_logic_vector(1 downto 0);
Dbg_RVALID_23 : in std_logic;
Dbg_RREADY_23 : out std_logic;
Dbg_Disable_24 : out std_logic;
Dbg_Clk_24 : out std_logic;
Dbg_TDI_24 : out std_logic;
Dbg_TDO_24 : in std_logic;
Dbg_Reg_En_24 : out std_logic_vector(0 to 7);
Dbg_Capture_24 : out std_logic;
Dbg_Shift_24 : out std_logic;
Dbg_Update_24 : out std_logic;
Dbg_Rst_24 : out std_logic;
Dbg_Trig_In_24 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_24 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_24 : in std_logic_vector(0 to 7);
Dbg_TrClk_24 : out std_logic;
Dbg_TrData_24 : in std_logic_vector(0 to 35);
Dbg_TrReady_24 : out std_logic;
Dbg_TrValid_24 : in std_logic;
Dbg_AWADDR_24 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_24 : out std_logic;
Dbg_AWREADY_24 : in std_logic;
Dbg_WDATA_24 : out std_logic_vector(31 downto 0);
Dbg_WVALID_24 : out std_logic;
Dbg_WREADY_24 : in std_logic;
Dbg_BRESP_24 : in std_logic_vector(1 downto 0);
Dbg_BVALID_24 : in std_logic;
Dbg_BREADY_24 : out std_logic;
Dbg_ARADDR_24 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_24 : out std_logic;
Dbg_ARREADY_24 : in std_logic;
Dbg_RDATA_24 : in std_logic_vector(31 downto 0);
Dbg_RRESP_24 : in std_logic_vector(1 downto 0);
Dbg_RVALID_24 : in std_logic;
Dbg_RREADY_24 : out std_logic;
Dbg_Disable_25 : out std_logic;
Dbg_Clk_25 : out std_logic;
Dbg_TDI_25 : out std_logic;
Dbg_TDO_25 : in std_logic;
Dbg_Reg_En_25 : out std_logic_vector(0 to 7);
Dbg_Capture_25 : out std_logic;
Dbg_Shift_25 : out std_logic;
Dbg_Update_25 : out std_logic;
Dbg_Rst_25 : out std_logic;
Dbg_Trig_In_25 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_25 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_25 : in std_logic_vector(0 to 7);
Dbg_TrClk_25 : out std_logic;
Dbg_TrData_25 : in std_logic_vector(0 to 35);
Dbg_TrReady_25 : out std_logic;
Dbg_TrValid_25 : in std_logic;
Dbg_AWADDR_25 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_25 : out std_logic;
Dbg_AWREADY_25 : in std_logic;
Dbg_WDATA_25 : out std_logic_vector(31 downto 0);
Dbg_WVALID_25 : out std_logic;
Dbg_WREADY_25 : in std_logic;
Dbg_BRESP_25 : in std_logic_vector(1 downto 0);
Dbg_BVALID_25 : in std_logic;
Dbg_BREADY_25 : out std_logic;
Dbg_ARADDR_25 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_25 : out std_logic;
Dbg_ARREADY_25 : in std_logic;
Dbg_RDATA_25 : in std_logic_vector(31 downto 0);
Dbg_RRESP_25 : in std_logic_vector(1 downto 0);
Dbg_RVALID_25 : in std_logic;
Dbg_RREADY_25 : out std_logic;
Dbg_Disable_26 : out std_logic;
Dbg_Clk_26 : out std_logic;
Dbg_TDI_26 : out std_logic;
Dbg_TDO_26 : in std_logic;
Dbg_Reg_En_26 : out std_logic_vector(0 to 7);
Dbg_Capture_26 : out std_logic;
Dbg_Shift_26 : out std_logic;
Dbg_Update_26 : out std_logic;
Dbg_Rst_26 : out std_logic;
Dbg_Trig_In_26 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_26 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_26 : in std_logic_vector(0 to 7);
Dbg_TrClk_26 : out std_logic;
Dbg_TrData_26 : in std_logic_vector(0 to 35);
Dbg_TrReady_26 : out std_logic;
Dbg_TrValid_26 : in std_logic;
Dbg_AWADDR_26 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_26 : out std_logic;
Dbg_AWREADY_26 : in std_logic;
Dbg_WDATA_26 : out std_logic_vector(31 downto 0);
Dbg_WVALID_26 : out std_logic;
Dbg_WREADY_26 : in std_logic;
Dbg_BRESP_26 : in std_logic_vector(1 downto 0);
Dbg_BVALID_26 : in std_logic;
Dbg_BREADY_26 : out std_logic;
Dbg_ARADDR_26 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_26 : out std_logic;
Dbg_ARREADY_26 : in std_logic;
Dbg_RDATA_26 : in std_logic_vector(31 downto 0);
Dbg_RRESP_26 : in std_logic_vector(1 downto 0);
Dbg_RVALID_26 : in std_logic;
Dbg_RREADY_26 : out std_logic;
Dbg_Disable_27 : out std_logic;
Dbg_Clk_27 : out std_logic;
Dbg_TDI_27 : out std_logic;
Dbg_TDO_27 : in std_logic;
Dbg_Reg_En_27 : out std_logic_vector(0 to 7);
Dbg_Capture_27 : out std_logic;
Dbg_Shift_27 : out std_logic;
Dbg_Update_27 : out std_logic;
Dbg_Rst_27 : out std_logic;
Dbg_Trig_In_27 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_27 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_27 : in std_logic_vector(0 to 7);
Dbg_TrClk_27 : out std_logic;
Dbg_TrData_27 : in std_logic_vector(0 to 35);
Dbg_TrReady_27 : out std_logic;
Dbg_TrValid_27 : in std_logic;
Dbg_AWADDR_27 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_27 : out std_logic;
Dbg_AWREADY_27 : in std_logic;
Dbg_WDATA_27 : out std_logic_vector(31 downto 0);
Dbg_WVALID_27 : out std_logic;
Dbg_WREADY_27 : in std_logic;
Dbg_BRESP_27 : in std_logic_vector(1 downto 0);
Dbg_BVALID_27 : in std_logic;
Dbg_BREADY_27 : out std_logic;
Dbg_ARADDR_27 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_27 : out std_logic;
Dbg_ARREADY_27 : in std_logic;
Dbg_RDATA_27 : in std_logic_vector(31 downto 0);
Dbg_RRESP_27 : in std_logic_vector(1 downto 0);
Dbg_RVALID_27 : in std_logic;
Dbg_RREADY_27 : out std_logic;
Dbg_Disable_28 : out std_logic;
Dbg_Clk_28 : out std_logic;
Dbg_TDI_28 : out std_logic;
Dbg_TDO_28 : in std_logic;
Dbg_Reg_En_28 : out std_logic_vector(0 to 7);
Dbg_Capture_28 : out std_logic;
Dbg_Shift_28 : out std_logic;
Dbg_Update_28 : out std_logic;
Dbg_Rst_28 : out std_logic;
Dbg_Trig_In_28 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_28 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_28 : in std_logic_vector(0 to 7);
Dbg_TrClk_28 : out std_logic;
Dbg_TrData_28 : in std_logic_vector(0 to 35);
Dbg_TrReady_28 : out std_logic;
Dbg_TrValid_28 : in std_logic;
Dbg_AWADDR_28 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_28 : out std_logic;
Dbg_AWREADY_28 : in std_logic;
Dbg_WDATA_28 : out std_logic_vector(31 downto 0);
Dbg_WVALID_28 : out std_logic;
Dbg_WREADY_28 : in std_logic;
Dbg_BRESP_28 : in std_logic_vector(1 downto 0);
Dbg_BVALID_28 : in std_logic;
Dbg_BREADY_28 : out std_logic;
Dbg_ARADDR_28 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_28 : out std_logic;
Dbg_ARREADY_28 : in std_logic;
Dbg_RDATA_28 : in std_logic_vector(31 downto 0);
Dbg_RRESP_28 : in std_logic_vector(1 downto 0);
Dbg_RVALID_28 : in std_logic;
Dbg_RREADY_28 : out std_logic;
Dbg_Disable_29 : out std_logic;
Dbg_Clk_29 : out std_logic;
Dbg_TDI_29 : out std_logic;
Dbg_TDO_29 : in std_logic;
Dbg_Reg_En_29 : out std_logic_vector(0 to 7);
Dbg_Capture_29 : out std_logic;
Dbg_Shift_29 : out std_logic;
Dbg_Update_29 : out std_logic;
Dbg_Rst_29 : out std_logic;
Dbg_Trig_In_29 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_29 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_29 : in std_logic_vector(0 to 7);
Dbg_TrClk_29 : out std_logic;
Dbg_TrData_29 : in std_logic_vector(0 to 35);
Dbg_TrReady_29 : out std_logic;
Dbg_TrValid_29 : in std_logic;
Dbg_AWADDR_29 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_29 : out std_logic;
Dbg_AWREADY_29 : in std_logic;
Dbg_WDATA_29 : out std_logic_vector(31 downto 0);
Dbg_WVALID_29 : out std_logic;
Dbg_WREADY_29 : in std_logic;
Dbg_BRESP_29 : in std_logic_vector(1 downto 0);
Dbg_BVALID_29 : in std_logic;
Dbg_BREADY_29 : out std_logic;
Dbg_ARADDR_29 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_29 : out std_logic;
Dbg_ARREADY_29 : in std_logic;
Dbg_RDATA_29 : in std_logic_vector(31 downto 0);
Dbg_RRESP_29 : in std_logic_vector(1 downto 0);
Dbg_RVALID_29 : in std_logic;
Dbg_RREADY_29 : out std_logic;
Dbg_Disable_30 : out std_logic;
Dbg_Clk_30 : out std_logic;
Dbg_TDI_30 : out std_logic;
Dbg_TDO_30 : in std_logic;
Dbg_Reg_En_30 : out std_logic_vector(0 to 7);
Dbg_Capture_30 : out std_logic;
Dbg_Shift_30 : out std_logic;
Dbg_Update_30 : out std_logic;
Dbg_Rst_30 : out std_logic;
Dbg_Trig_In_30 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_30 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_30 : in std_logic_vector(0 to 7);
Dbg_TrClk_30 : out std_logic;
Dbg_TrData_30 : in std_logic_vector(0 to 35);
Dbg_TrReady_30 : out std_logic;
Dbg_TrValid_30 : in std_logic;
Dbg_AWADDR_30 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_30 : out std_logic;
Dbg_AWREADY_30 : in std_logic;
Dbg_WDATA_30 : out std_logic_vector(31 downto 0);
Dbg_WVALID_30 : out std_logic;
Dbg_WREADY_30 : in std_logic;
Dbg_BRESP_30 : in std_logic_vector(1 downto 0);
Dbg_BVALID_30 : in std_logic;
Dbg_BREADY_30 : out std_logic;
Dbg_ARADDR_30 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_30 : out std_logic;
Dbg_ARREADY_30 : in std_logic;
Dbg_RDATA_30 : in std_logic_vector(31 downto 0);
Dbg_RRESP_30 : in std_logic_vector(1 downto 0);
Dbg_RVALID_30 : in std_logic;
Dbg_RREADY_30 : out std_logic;
Dbg_Disable_31 : out std_logic;
Dbg_Clk_31 : out std_logic;
Dbg_TDI_31 : out std_logic;
Dbg_TDO_31 : in std_logic;
Dbg_Reg_En_31 : out std_logic_vector(0 to 7);
Dbg_Capture_31 : out std_logic;
Dbg_Shift_31 : out std_logic;
Dbg_Update_31 : out std_logic;
Dbg_Rst_31 : out std_logic;
Dbg_Trig_In_31 : in std_logic_vector(0 to 7);
Dbg_Trig_Ack_In_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Out_31 : out std_logic_vector(0 to 7);
Dbg_Trig_Ack_Out_31 : in std_logic_vector(0 to 7);
Dbg_TrClk_31 : out std_logic;
Dbg_TrData_31 : in std_logic_vector(0 to 35);
Dbg_TrReady_31 : out std_logic;
Dbg_TrValid_31 : in std_logic;
Dbg_AWADDR_31 : out std_logic_vector(14 downto 2);
Dbg_AWVALID_31 : out std_logic;
Dbg_AWREADY_31 : in std_logic;
Dbg_WDATA_31 : out std_logic_vector(31 downto 0);
Dbg_WVALID_31 : out std_logic;
Dbg_WREADY_31 : in std_logic;
Dbg_BRESP_31 : in std_logic_vector(1 downto 0);
Dbg_BVALID_31 : in std_logic;
Dbg_BREADY_31 : out std_logic;
Dbg_ARADDR_31 : out std_logic_vector(14 downto 2);
Dbg_ARVALID_31 : out std_logic;
Dbg_ARREADY_31 : in std_logic;
Dbg_RDATA_31 : in std_logic_vector(31 downto 0);
Dbg_RRESP_31 : in std_logic_vector(1 downto 0);
Dbg_RVALID_31 : in std_logic;
Dbg_RREADY_31 : out std_logic;
-- External Trigger Signals
Ext_Trig_In : in std_logic_vector(0 to 3);
Ext_Trig_Ack_In : out std_logic_vector(0 to 3);
Ext_Trig_Out : out std_logic_vector(0 to 3);
Ext_Trig_Ack_Out : in std_logic_vector(0 to 3);
-- External JTAG
Ext_JTAG_DRCK : out std_logic;
Ext_JTAG_RESET : out std_logic;
Ext_JTAG_SEL : out std_logic;
Ext_JTAG_CAPTURE : out std_logic;
Ext_JTAG_SHIFT : out std_logic;
Ext_JTAG_UPDATE : out std_logic;
Ext_JTAG_TDI : out std_logic;
Ext_JTAG_TDO : in std_logic
);
end component MDM_Core;
component bus_master is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_M_AXI_DATA_WIDTH : natural;
C_M_AXI_THREAD_ID_WIDTH : natural;
C_M_AXI_ADDR_WIDTH : natural;
C_DATA_SIZE : natural;
C_HAS_FIFO_PORTS : boolean;
C_HAS_DIRECT_PORT : boolean
);
port (
Rd_Start : in std_logic;
Rd_Addr : in std_logic_vector(31 downto 0);
Rd_Len : in std_logic_vector(4 downto 0);
Rd_Size : in std_logic_vector(1 downto 0);
Rd_Exclusive : in std_logic;
Rd_Idle : out std_logic;
Rd_Response : out std_logic_vector(1 downto 0);
Wr_Start : in std_logic;
Wr_Addr : in std_logic_vector(31 downto 0);
Wr_Len : in std_logic_vector(4 downto 0);
Wr_Size : in std_logic_vector(1 downto 0);
Wr_Exclusive : in std_logic;
Wr_Idle : out std_logic;
Wr_Response : out std_logic_vector(1 downto 0);
Data_Rd : in std_logic;
Data_Out : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Exists : out std_logic;
Data_Wr : in std_logic;
Data_In : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Data_Empty : out std_logic;
Direct_Wr_Addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
Direct_Wr_Len : in std_logic_vector(4 downto 0);
Direct_Wr_Data : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
Direct_Wr_Start : in std_logic;
Direct_Wr_Next : out std_logic;
Direct_Wr_Done : out std_logic;
Direct_Wr_Resp : out std_logic_vector(1 downto 0);
LMB_Data_Addr : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Read : in std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Data_Write : out std_logic_vector(0 to C_DATA_SIZE-1);
LMB_Addr_Strobe : out std_logic;
LMB_Read_Strobe : out std_logic;
LMB_Write_Strobe : out std_logic;
LMB_Ready : in std_logic;
LMB_Wait : in std_logic;
LMB_UE : in std_logic;
LMB_Byte_Enable : out std_logic_vector(0 to (C_DATA_SIZE-1)/8);
M_AXI_ACLK : in std_logic;
M_AXI_ARESETn : in std_logic;
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_WLAST : out std_logic;
M_AXI_WDATA : out std_logic_vector(31 downto 0);
M_AXI_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARLOCK : out std_logic;
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_RLAST : in std_logic;
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(31 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic
);
end component bus_master;
component MB_BSCANE2
generic (
C_TARGET : TARGET_FAMILY_TYPE;
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_logic := 'H';
DRCK : out std_logic := 'H';
RESET : out std_logic := 'H';
RUNTEST : out std_logic := 'L';
SEL : out std_logic := 'L';
SHIFT : out std_logic := 'L';
TCK : out std_logic := 'L';
TDI : out std_logic := 'L';
TMS : out std_logic := 'L';
UPDATE : out std_logic := 'L';
TDO : in std_logic := 'X'
);
end component;
component MB_BUFG
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I : in std_logic
);
end component;
component MB_BUFGCTRL
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT_OUT : integer := 0;
IS_CE0_INVERTED : bit := '0';
IS_CE1_INVERTED : bit := '0';
IS_I0_INVERTED : bit := '0';
IS_I1_INVERTED : bit := '0';
IS_IGNORE0_INVERTED : bit := '0';
IS_IGNORE1_INVERTED : bit := '0';
IS_S0_INVERTED : bit := '0';
IS_S1_INVERTED : bit := '0';
PRESELECT_I0 : boolean := false;
PRESELECT_I1 : boolean := false
);
port (
O : out std_logic;
CE0 : in std_logic;
CE1 : in std_logic;
I0 : in std_logic;
I1 : in std_logic;
IGNORE0 : in std_logic;
IGNORE1 : in std_logic;
S0 : in std_logic;
S1 : in std_logic
);
end component;
--------------------------------------------------------------------------
-- Functions
--------------------------------------------------------------------------
-- Returns at least 1
function MakePos (a : integer) return integer is
begin
if a < 1 then
return 1;
else
return a;
end if;
end function MakePos;
constant C_EN_WIDTH : integer := MakePos(C_MB_DBG_PORTS);
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal tdi : std_logic;
signal reset : std_logic;
signal update : std_logic;
signal capture : std_logic;
signal shift : std_logic;
signal sel : std_logic;
signal drck : std_logic;
signal tdo : std_logic;
signal drck_i : std_logic;
signal update_i : std_logic;
signal dbgreg_drck : std_logic;
signal dbgreg_update : std_logic;
signal dbgreg_select : std_logic;
signal jtag_busy : std_logic := '0';
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0) := (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
signal bus2ip_cs : std_logic_vector((C_ARD_RANGES-1) downto 0);
signal bus2ip_rdce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY(0 to C_ARD_RANGES-1))-1 downto 0);
signal bus2ip_wrce : std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY(0 to C_ARD_RANGES-1))-1 downto 0);
signal mb_debug_enabled : std_logic_vector(C_EN_WIDTH-1 downto 0);
signal master_rd_start : std_logic;
signal master_rd_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_rd_len : std_logic_vector(4 downto 0);
signal master_rd_size : std_logic_vector(1 downto 0);
signal master_rd_excl : std_logic;
signal master_rd_idle : std_logic;
signal master_rd_resp : std_logic_vector(1 downto 0);
signal master_wr_start : std_logic;
signal master_wr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_wr_len : std_logic_vector(4 downto 0);
signal master_wr_size : std_logic_vector(1 downto 0);
signal master_wr_excl : std_logic;
signal master_wr_idle : std_logic;
signal master_wr_resp : std_logic_vector(1 downto 0);
signal master_data_rd : std_logic;
signal master_data_out : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_exists : std_logic;
signal master_data_wr : std_logic;
signal master_data_in : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_data_empty : std_logic;
signal master_dwr_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal master_dwr_len : std_logic_vector(4 downto 0);
signal master_dwr_data : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
signal master_dwr_start : std_logic;
signal master_dwr_next : std_logic;
signal master_dwr_done : std_logic;
signal master_dwr_resp : std_logic_vector(1 downto 0);
signal ext_trig_in : std_logic_vector(0 to 3);
signal ext_trig_Ack_In : std_logic_vector(0 to 3);
signal ext_trig_out : std_logic_vector(0 to 3);
signal ext_trig_Ack_Out : std_logic_vector(0 to 3);
--------------------------------------------------------------------------
-- Attibute declarations
--------------------------------------------------------------------------
attribute period : string;
attribute period of update : signal is "200 ns";
attribute buffer_type : string;
attribute buffer_type of update_i : signal is "none";
attribute buffer_type of MDM_Core_I1 : label is "none";
begin -- architecture IMP
Use_E2 : if C_USE_BSCAN /= 2 and C_USE_BSCAN /= 3 generate
begin
BSCAN_I : MB_BSCANE2
generic map (
C_TARGET => C_TARGET,
DISABLE_JTAG => "FALSE",
JTAG_CHAIN => C_JTAG_CHAIN)
port map (
CAPTURE => capture, -- [out std_logic]
DRCK => drck_i, -- [out std_logic]
RESET => reset, -- [out std_logic]
RUNTEST => open, -- [out std_logic]
SEL => sel, -- [out std_logic]
SHIFT => shift, -- [out std_logic]
TCK => open, -- [out std_logic]
TDI => tdi, -- [out std_logic]
TMS => open, -- [out std_logic]
UPDATE => update_i, -- [out std_logic]
TDO => tdo); -- [in std_logic]
end generate Use_E2;
Use_External : if C_USE_BSCAN = 2 and C_USE_BSCAN /= 3 generate
begin
capture <= bscan_ext_capture;
drck_i <= bscan_ext_drck;
reset <= bscan_ext_reset;
sel <= bscan_ext_sel;
shift <= bscan_ext_shift;
tdi <= bscan_ext_tdi;
update_i <= bscan_ext_update;
bscan_ext_tdo <= tdo;
end generate Use_External;
No_External : if C_USE_BSCAN /= 2 generate
begin
bscan_ext_tdo <= '0';
end generate No_External;
Use_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 1 and C_USE_BSCAN /= 3 generate
signal dbgreg_select_n : std_logic;
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
signal update_set : std_logic;
signal update_reset : std_logic;
begin
dbgreg_select_n <= not dbgreg_select;
-- drck <= dbgreg_drck when dbgreg_select = '1' else drck_i;
dbgreg_drck_i <= dbgreg_drck;
BUFGCTRL_DRCK : MB_BUFGCTRL
generic map (
C_TARGET => C_TARGET,
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => drck,
CE0 => '1',
CE1 => '1',
I0 => drck_i,
I1 => dbgreg_drck_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
-- update <= dbgreg_update when dbgreg_select = '1' else update_i;
dbgreg_update_i <= dbgreg_update;
BUFGCTRL_UPDATE : MB_BUFGCTRL
generic map (
C_TARGET => C_TARGET,
INIT_OUT => 0,
PRESELECT_I0 => true,
PRESELECT_I1 => false
)
port map (
O => update,
CE0 => '1',
CE1 => '1',
I0 => update_i,
I1 => dbgreg_update_i,
IGNORE0 => '1',
IGNORE1 => '1',
S0 => dbgreg_select_n,
S1 => dbgreg_select
);
JTAG_Busy_Detect : process (drck_i, sel, update_set, Config_Reset)
begin
if sel = '0' or update_set = '1' or Config_Reset = '1' then
jtag_busy <= '0';
update_reset <= '1';
elsif drck_i'event and drck_i = '1' then
if sel = '1' and capture = '1' then
jtag_busy <= '1';
end if;
update_reset <= '0';
end if;
end process JTAG_Busy_Detect;
JTAG_Update_Detect : process (update_i, update_reset, Config_Reset)
begin
if update_reset = '1' or Config_Reset = '1' then
update_set <= '0';
elsif update_i'event and update_i = '1' then
update_set <= '1';
end if;
end process JTAG_Update_Detect;
end generate Use_Dbg_Reg_Access;
No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 and C_USE_BSCAN /= 3 generate
begin
BUFG_DRCK : MB_BUFG
generic map (
C_TARGET => C_TARGET
)
port map (
O => drck,
I => drck_i
);
update <= update_i;
jtag_busy <= '0';
end generate No_Dbg_Reg_Access;
Use_Dbg_Reg_Access_No_BSCAN : if C_DBG_REG_ACCESS = 1 and C_USE_BSCAN = 3 generate
signal dbgreg_drck_i : std_logic;
signal dbgreg_update_i : std_logic;
begin
BUFG_DRCK : MB_BUFG
generic map (
C_TARGET => C_TARGET
)
port map (
O => dbgreg_drck_i,
I => dbgreg_drck
);
BUFG_UPDATE : MB_BUFG
generic map (
C_TARGET => C_TARGET
)
port map (
O => dbgreg_update_i,
I => dbgreg_update
);
drck <= dbgreg_drck_i;
update <= dbgreg_update_i;
jtag_busy <= '0';
-- Unused
tdi <= '0';
reset <= '0';
capture <= '0';
shift <= '0';
sel <= '0';
drck_i <= '0';
update_i <= '0';
end generate Use_Dbg_Reg_Access_No_BSCAN;
No_BSCAN_No_Dbg_Reg_Access : if C_DBG_REG_ACCESS = 0 and C_USE_BSCAN = 3 generate
begin
drck <= '0';
update <= '0';
jtag_busy <= '0';
tdi <= '0';
reset <= '0';
capture <= '0';
shift <= '0';
sel <= '0';
drck_i <= '0';
update_i <= '0';
end generate No_BSCAN_No_Dbg_Reg_Access;
---------------------------------------------------------------------------
-- MDM core
---------------------------------------------------------------------------
MDM_Core_I1 : MDM_Core
generic map (
C_TARGET => C_TARGET, -- [TARGET_FAMILY_TYPE]
C_JTAG_CHAIN => C_JTAG_CHAIN, -- [integer]
C_USE_BSCAN => C_USE_BSCAN, -- [integer]
C_USE_CONFIG_RESET => C_USE_CONFIG_RESET, -- [integer = 0]
C_DEBUG_INTERFACE => C_DEBUG_INTERFACE, -- [integer]
C_MB_DBG_PORTS => C_MB_DBG_PORTS, -- [integer]
C_EN_WIDTH => C_EN_WIDTH, -- [integer]
C_DBG_REG_ACCESS => C_DBG_REG_ACCESS, -- [integer]
C_REG_NUM_CE => C_REG_NUM_CE, -- [integer]
C_REG_DATA_WIDTH => C_REG_DATA_WIDTH, -- [integer]
C_DBG_MEM_ACCESS => C_DBG_MEM_ACCESS, -- [integer]
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, -- [integer]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ, -- [integer]
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH, -- [integer]
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH, -- [integer]
C_USE_CROSS_TRIGGER => C_USE_CROSS_TRIGGER, -- [integer]
C_USE_UART => C_USE_UART, -- [integer]
C_UART_WIDTH => 8, -- [integer]
C_TRACE_OUTPUT => C_TRACE_OUTPUT, -- [integer]
C_TRACE_DATA_WIDTH => C_TRACE_DATA_WIDTH, -- [integer]
C_TRACE_CLK_FREQ_HZ => C_TRACE_CLK_FREQ_HZ, -- [integer]
C_TRACE_CLK_OUT_PHASE => C_TRACE_CLK_OUT_PHASE, -- [integer]
C_M_AXIS_DATA_WIDTH => C_M_AXIS_DATA_WIDTH, -- [integer]
C_M_AXIS_ID_WIDTH => C_M_AXIS_ID_WIDTH -- [integer]
)
port map (
-- Global signals
Config_Reset => Config_Reset, -- [in std_logic]
Scan_Reset_Sel => Scan_Reset_Sel, -- [in std_logic]
Scan_Reset => Scan_Reset, -- [in std_logic]
M_AXIS_ACLK => M_AXIS_ACLK, -- [in std_logic]
M_AXIS_ARESETN => M_AXIS_ARESETN, -- [in std_logic]
Interrupt => Interrupt, -- [out std_logic]
Ext_BRK => Ext_BRK, -- [out std_logic]
Ext_NM_BRK => Ext_NM_BRK, -- [out std_logic]
Debug_SYS_Rst => Debug_SYS_Rst, -- [out std_logic]
-- Debug Register Access signals
DbgReg_DRCK => dbgreg_drck, -- [out std_logic]
DbgReg_UPDATE => dbgreg_update, -- [out std_logic]
DbgReg_Select => dbgreg_select, -- [out std_logic]
JTAG_Busy => jtag_busy, -- [in std_logic]
S_AXI_AWADDR => S_AXI_AWADDR, -- [in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0)]
S_AXI_ARADDR => S_AXI_ARADDR, -- [in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0)]
-- AXI IPIC signals
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data(C_REG_DATA_WIDTH-1 downto 0),
bus2ip_rdce => bus2ip_rdce(C_REG_NUM_CE+C_DEBUG_INTERFACE-1 downto 0),
bus2ip_wrce => bus2ip_wrce(C_REG_NUM_CE+C_DEBUG_INTERFACE-1 downto 0),
bus2ip_cs => bus2ip_cs,
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
ip2bus_data => ip2bus_data(C_REG_DATA_WIDTH-1 downto 0),
-- Bus Master signals
MB_Debug_Enabled => mb_debug_enabled,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
Master_rd_start => master_rd_start,
Master_rd_addr => master_rd_addr,
Master_rd_len => master_rd_len,
Master_rd_size => master_rd_size,
Master_rd_excl => master_rd_excl,
Master_rd_idle => master_rd_idle,
Master_rd_resp => master_rd_resp,
Master_wr_start => master_wr_start,
Master_wr_addr => master_wr_addr,
Master_wr_len => master_wr_len,
Master_wr_size => master_wr_size,
Master_wr_excl => master_wr_excl,
Master_wr_idle => master_wr_idle,
Master_wr_resp => master_wr_resp,
Master_data_rd => master_data_rd,
Master_data_out => master_data_out,
Master_data_exists => master_data_exists,
Master_data_wr => master_data_wr,
Master_data_in => master_data_in,
Master_data_empty => master_data_empty,
Master_dwr_addr => master_dwr_addr,
Master_dwr_len => master_dwr_len,
Master_dwr_data => master_dwr_data,
Master_dwr_start => master_dwr_start,
Master_dwr_next => master_dwr_next,
Master_dwr_done => master_dwr_done,
Master_dwr_resp => master_dwr_resp,
-- JTAG signals
JTAG_TDI => tdi, -- [in std_logic]
JTAG_RESET => reset, -- [in std_logic]
UPDATE => update, -- [in std_logic]
JTAG_SHIFT => shift, -- [in std_logic]
JTAG_CAPTURE => capture, -- [in std_logic]
SEL => sel, -- [in std_logic]
DRCK => drck, -- [in std_logic]
JTAG_TDO => tdo, -- [out std_logic]
-- External Trace AXI Stream output
M_AXIS_TDATA => M_AXIS_TDATA, -- [out std_logic_vector(C_M_AXIS_DATA_WIDTH-1 downto 0)]
M_AXIS_TID => M_AXIS_TID, -- [out std_logic_vector(C_M_AXIS_ID_WIDTH-1 downto 0)]
M_AXIS_TREADY => M_AXIS_TREADY, -- [in std_logic]
M_AXIS_TVALID => M_AXIS_TVALID, -- [out std_logic]
-- External Trace output
TRACE_CLK_OUT => TRACE_CLK_OUT, -- [out std_logic]
TRACE_CLK => TRACE_CLK, -- [in std_logic]
TRACE_CTL => TRACE_CTL, -- [out std_logic]
TRACE_DATA => TRACE_DATA, -- [out std_logic_vector(C_TRACE_DATA_WIDTH-1 downto 0)]
-- MicroBlaze Debug Signals
Dbg_Disable_0 => Dbg_Disable_0, -- [out std_logic]
Dbg_Clk_0 => Dbg_Clk_0, -- [out std_logic]
Dbg_TDI_0 => Dbg_TDI_0, -- [out std_logic]
Dbg_TDO_0 => Dbg_TDO_0, -- [in std_logic]
Dbg_Reg_En_0 => Dbg_Reg_En_0, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_0 => Dbg_Capture_0, -- [out std_logic]
Dbg_Shift_0 => Dbg_Shift_0, -- [out std_logic]
Dbg_Update_0 => Dbg_Update_0, -- [out std_logic]
Dbg_Rst_0 => Dbg_Rst_0, -- [out std_logic]
Dbg_Trig_In_0 => Dbg_Trig_In_0, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_0 => Dbg_Trig_Ack_In_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_0 => Dbg_Trig_Out_0, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_0 => Dbg_Trig_Ack_Out_0, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_0 => Dbg_TrClk_0, -- [out std_logic]
Dbg_TrData_0 => Dbg_TrData_0, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_0 => Dbg_TrReady_0, -- [out std_logic]
Dbg_TrValid_0 => Dbg_TrValid_0, -- [in std_logic]
Dbg_AWADDR_0 => Dbg_AWADDR_0, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_0 => Dbg_AWVALID_0, -- [out std_logic]
Dbg_AWREADY_0 => Dbg_AWREADY_0, -- [in std_logic]
Dbg_WDATA_0 => Dbg_WDATA_0, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_0 => Dbg_WVALID_0, -- [out std_logic]
Dbg_WREADY_0 => Dbg_WREADY_0, -- [in std_logic]
Dbg_BRESP_0 => Dbg_BRESP_0, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_0 => Dbg_BVALID_0, -- [in std_logic]
Dbg_BREADY_0 => Dbg_BREADY_0, -- [out std_logic]
Dbg_ARADDR_0 => Dbg_ARADDR_0, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_0 => Dbg_ARVALID_0, -- [out std_logic]
Dbg_ARREADY_0 => Dbg_ARREADY_0, -- [in std_logic]
Dbg_RDATA_0 => Dbg_RDATA_0, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_0 => Dbg_RRESP_0, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_0 => Dbg_RVALID_0, -- [in std_logic]
Dbg_RREADY_0 => Dbg_RREADY_0, -- [out std_logic]
Dbg_Disable_1 => Dbg_Disable_1, -- [out std_logic]
Dbg_Clk_1 => Dbg_Clk_1, -- [out std_logic]
Dbg_TDI_1 => Dbg_TDI_1, -- [out std_logic]
Dbg_TDO_1 => Dbg_TDO_1, -- [in std_logic]
Dbg_Reg_En_1 => Dbg_Reg_En_1, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_1 => Dbg_Capture_1, -- [out std_logic]
Dbg_Shift_1 => Dbg_Shift_1, -- [out std_logic]
Dbg_Update_1 => Dbg_Update_1, -- [out std_logic]
Dbg_Rst_1 => Dbg_Rst_1, -- [out std_logic]
Dbg_Trig_In_1 => Dbg_Trig_In_1, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_1 => Dbg_Trig_Ack_In_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_1 => Dbg_Trig_Out_1, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_1 => Dbg_Trig_Ack_Out_1, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_1 => Dbg_TrClk_1, -- [out std_logic]
Dbg_TrData_1 => Dbg_TrData_1, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_1 => Dbg_TrReady_1, -- [out std_logic]
Dbg_TrValid_1 => Dbg_TrValid_1, -- [in std_logic]
Dbg_AWADDR_1 => Dbg_AWADDR_1, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_1 => Dbg_AWVALID_1, -- [out std_logic]
Dbg_AWREADY_1 => Dbg_AWREADY_1, -- [in std_logic]
Dbg_WDATA_1 => Dbg_WDATA_1, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_1 => Dbg_WVALID_1, -- [out std_logic]
Dbg_WREADY_1 => Dbg_WREADY_1, -- [in std_logic]
Dbg_BRESP_1 => Dbg_BRESP_1, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_1 => Dbg_BVALID_1, -- [in std_logic]
Dbg_BREADY_1 => Dbg_BREADY_1, -- [out std_logic]
Dbg_ARADDR_1 => Dbg_ARADDR_1, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_1 => Dbg_ARVALID_1, -- [out std_logic]
Dbg_ARREADY_1 => Dbg_ARREADY_1, -- [in std_logic]
Dbg_RDATA_1 => Dbg_RDATA_1, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_1 => Dbg_RRESP_1, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_1 => Dbg_RVALID_1, -- [in std_logic]
Dbg_RREADY_1 => Dbg_RREADY_1, -- [out std_logic]
Dbg_Disable_2 => Dbg_Disable_2, -- [out std_logic]
Dbg_Clk_2 => Dbg_Clk_2, -- [out std_logic]
Dbg_TDI_2 => Dbg_TDI_2, -- [out std_logic]
Dbg_TDO_2 => Dbg_TDO_2, -- [in std_logic]
Dbg_Reg_En_2 => Dbg_Reg_En_2, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_2 => Dbg_Capture_2, -- [out std_logic]
Dbg_Shift_2 => Dbg_Shift_2, -- [out std_logic]
Dbg_Update_2 => Dbg_Update_2, -- [out std_logic]
Dbg_Rst_2 => Dbg_Rst_2, -- [out std_logic]
Dbg_Trig_In_2 => Dbg_Trig_In_2, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_2 => Dbg_Trig_Ack_In_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_2 => Dbg_Trig_Out_2, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_2 => Dbg_Trig_Ack_Out_2, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_2 => Dbg_TrClk_2, -- [out std_logic]
Dbg_TrData_2 => Dbg_TrData_2, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_2 => Dbg_TrReady_2, -- [out std_logic]
Dbg_TrValid_2 => Dbg_TrValid_2, -- [in std_logic]
Dbg_AWADDR_2 => Dbg_AWADDR_2, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_2 => Dbg_AWVALID_2, -- [out std_logic]
Dbg_AWREADY_2 => Dbg_AWREADY_2, -- [in std_logic]
Dbg_WDATA_2 => Dbg_WDATA_2, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_2 => Dbg_WVALID_2, -- [out std_logic]
Dbg_WREADY_2 => Dbg_WREADY_2, -- [in std_logic]
Dbg_BRESP_2 => Dbg_BRESP_2, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_2 => Dbg_BVALID_2, -- [in std_logic]
Dbg_BREADY_2 => Dbg_BREADY_2, -- [out std_logic]
Dbg_ARADDR_2 => Dbg_ARADDR_2, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_2 => Dbg_ARVALID_2, -- [out std_logic]
Dbg_ARREADY_2 => Dbg_ARREADY_2, -- [in std_logic]
Dbg_RDATA_2 => Dbg_RDATA_2, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_2 => Dbg_RRESP_2, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_2 => Dbg_RVALID_2, -- [in std_logic]
Dbg_RREADY_2 => Dbg_RREADY_2, -- [out std_logic]
Dbg_Disable_3 => Dbg_Disable_3, -- [out std_logic]
Dbg_Clk_3 => Dbg_Clk_3, -- [out std_logic]
Dbg_TDI_3 => Dbg_TDI_3, -- [out std_logic]
Dbg_TDO_3 => Dbg_TDO_3, -- [in std_logic]
Dbg_Reg_En_3 => Dbg_Reg_En_3, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_3 => Dbg_Capture_3, -- [out std_logic]
Dbg_Shift_3 => Dbg_Shift_3, -- [out std_logic]
Dbg_Update_3 => Dbg_Update_3, -- [out std_logic]
Dbg_Rst_3 => Dbg_Rst_3, -- [out std_logic]
Dbg_Trig_In_3 => Dbg_Trig_In_3, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_3 => Dbg_Trig_Ack_In_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_3 => Dbg_Trig_Out_3, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_3 => Dbg_Trig_Ack_Out_3, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_3 => Dbg_TrClk_3, -- [out std_logic]
Dbg_TrData_3 => Dbg_TrData_3, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_3 => Dbg_TrReady_3, -- [out std_logic]
Dbg_TrValid_3 => Dbg_TrValid_3, -- [in std_logic]
Dbg_AWADDR_3 => Dbg_AWADDR_3, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_3 => Dbg_AWVALID_3, -- [out std_logic]
Dbg_AWREADY_3 => Dbg_AWREADY_3, -- [in std_logic]
Dbg_WDATA_3 => Dbg_WDATA_3, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_3 => Dbg_WVALID_3, -- [out std_logic]
Dbg_WREADY_3 => Dbg_WREADY_3, -- [in std_logic]
Dbg_BRESP_3 => Dbg_BRESP_3, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_3 => Dbg_BVALID_3, -- [in std_logic]
Dbg_BREADY_3 => Dbg_BREADY_3, -- [out std_logic]
Dbg_ARADDR_3 => Dbg_ARADDR_3, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_3 => Dbg_ARVALID_3, -- [out std_logic]
Dbg_ARREADY_3 => Dbg_ARREADY_3, -- [in std_logic]
Dbg_RDATA_3 => Dbg_RDATA_3, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_3 => Dbg_RRESP_3, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_3 => Dbg_RVALID_3, -- [in std_logic]
Dbg_RREADY_3 => Dbg_RREADY_3, -- [out std_logic]
Dbg_Disable_4 => Dbg_Disable_4, -- [out std_logic]
Dbg_Clk_4 => Dbg_Clk_4, -- [out std_logic]
Dbg_TDI_4 => Dbg_TDI_4, -- [out std_logic]
Dbg_TDO_4 => Dbg_TDO_4, -- [in std_logic]
Dbg_Reg_En_4 => Dbg_Reg_En_4, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_4 => Dbg_Capture_4, -- [out std_logic]
Dbg_Shift_4 => Dbg_Shift_4, -- [out std_logic]
Dbg_Update_4 => Dbg_Update_4, -- [out std_logic]
Dbg_Rst_4 => Dbg_Rst_4, -- [out std_logic]
Dbg_Trig_In_4 => Dbg_Trig_In_4, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_4 => Dbg_Trig_Ack_In_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_4 => Dbg_Trig_Out_4, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_4 => Dbg_Trig_Ack_Out_4, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_4 => Dbg_TrClk_4, -- [out std_logic]
Dbg_TrData_4 => Dbg_TrData_4, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_4 => Dbg_TrReady_4, -- [out std_logic]
Dbg_TrValid_4 => Dbg_TrValid_4, -- [in std_logic]
Dbg_AWADDR_4 => Dbg_AWADDR_4, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_4 => Dbg_AWVALID_4, -- [out std_logic]
Dbg_AWREADY_4 => Dbg_AWREADY_4, -- [in std_logic]
Dbg_WDATA_4 => Dbg_WDATA_4, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_4 => Dbg_WVALID_4, -- [out std_logic]
Dbg_WREADY_4 => Dbg_WREADY_4, -- [in std_logic]
Dbg_BRESP_4 => Dbg_BRESP_4, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_4 => Dbg_BVALID_4, -- [in std_logic]
Dbg_BREADY_4 => Dbg_BREADY_4, -- [out std_logic]
Dbg_ARADDR_4 => Dbg_ARADDR_4, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_4 => Dbg_ARVALID_4, -- [out std_logic]
Dbg_ARREADY_4 => Dbg_ARREADY_4, -- [in std_logic]
Dbg_RDATA_4 => Dbg_RDATA_4, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_4 => Dbg_RRESP_4, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_4 => Dbg_RVALID_4, -- [in std_logic]
Dbg_RREADY_4 => Dbg_RREADY_4, -- [out std_logic]
Dbg_Disable_5 => Dbg_Disable_5, -- [out std_logic]
Dbg_Clk_5 => Dbg_Clk_5, -- [out std_logic]
Dbg_TDI_5 => Dbg_TDI_5, -- [out std_logic]
Dbg_TDO_5 => Dbg_TDO_5, -- [in std_logic]
Dbg_Reg_En_5 => Dbg_Reg_En_5, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_5 => Dbg_Capture_5, -- [out std_logic]
Dbg_Shift_5 => Dbg_Shift_5, -- [out std_logic]
Dbg_Update_5 => Dbg_Update_5, -- [out std_logic]
Dbg_Rst_5 => Dbg_Rst_5, -- [out std_logic]
Dbg_Trig_In_5 => Dbg_Trig_In_5, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_5 => Dbg_Trig_Ack_In_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_5 => Dbg_Trig_Out_5, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_5 => Dbg_Trig_Ack_Out_5, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_5 => Dbg_TrClk_5, -- [out std_logic]
Dbg_TrData_5 => Dbg_TrData_5, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_5 => Dbg_TrReady_5, -- [out std_logic]
Dbg_TrValid_5 => Dbg_TrValid_5, -- [in std_logic]
Dbg_AWADDR_5 => Dbg_AWADDR_5, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_5 => Dbg_AWVALID_5, -- [out std_logic]
Dbg_AWREADY_5 => Dbg_AWREADY_5, -- [in std_logic]
Dbg_WDATA_5 => Dbg_WDATA_5, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_5 => Dbg_WVALID_5, -- [out std_logic]
Dbg_WREADY_5 => Dbg_WREADY_5, -- [in std_logic]
Dbg_BRESP_5 => Dbg_BRESP_5, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_5 => Dbg_BVALID_5, -- [in std_logic]
Dbg_BREADY_5 => Dbg_BREADY_5, -- [out std_logic]
Dbg_ARADDR_5 => Dbg_ARADDR_5, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_5 => Dbg_ARVALID_5, -- [out std_logic]
Dbg_ARREADY_5 => Dbg_ARREADY_5, -- [in std_logic]
Dbg_RDATA_5 => Dbg_RDATA_5, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_5 => Dbg_RRESP_5, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_5 => Dbg_RVALID_5, -- [in std_logic]
Dbg_RREADY_5 => Dbg_RREADY_5, -- [out std_logic]
Dbg_Disable_6 => Dbg_Disable_6, -- [out std_logic]
Dbg_Clk_6 => Dbg_Clk_6, -- [out std_logic]
Dbg_TDI_6 => Dbg_TDI_6, -- [out std_logic]
Dbg_TDO_6 => Dbg_TDO_6, -- [in std_logic]
Dbg_Reg_En_6 => Dbg_Reg_En_6, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_6 => Dbg_Capture_6, -- [out std_logic]
Dbg_Shift_6 => Dbg_Shift_6, -- [out std_logic]
Dbg_Update_6 => Dbg_Update_6, -- [out std_logic]
Dbg_Rst_6 => Dbg_Rst_6, -- [out std_logic]
Dbg_Trig_In_6 => Dbg_Trig_In_6, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_6 => Dbg_Trig_Ack_In_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_6 => Dbg_Trig_Out_6, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_6 => Dbg_Trig_Ack_Out_6, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_6 => Dbg_TrClk_6, -- [out std_logic]
Dbg_TrData_6 => Dbg_TrData_6, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_6 => Dbg_TrReady_6, -- [out std_logic]
Dbg_TrValid_6 => Dbg_TrValid_6, -- [in std_logic]
Dbg_AWADDR_6 => Dbg_AWADDR_6, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_6 => Dbg_AWVALID_6, -- [out std_logic]
Dbg_AWREADY_6 => Dbg_AWREADY_6, -- [in std_logic]
Dbg_WDATA_6 => Dbg_WDATA_6, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_6 => Dbg_WVALID_6, -- [out std_logic]
Dbg_WREADY_6 => Dbg_WREADY_6, -- [in std_logic]
Dbg_BRESP_6 => Dbg_BRESP_6, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_6 => Dbg_BVALID_6, -- [in std_logic]
Dbg_BREADY_6 => Dbg_BREADY_6, -- [out std_logic]
Dbg_ARADDR_6 => Dbg_ARADDR_6, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_6 => Dbg_ARVALID_6, -- [out std_logic]
Dbg_ARREADY_6 => Dbg_ARREADY_6, -- [in std_logic]
Dbg_RDATA_6 => Dbg_RDATA_6, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_6 => Dbg_RRESP_6, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_6 => Dbg_RVALID_6, -- [in std_logic]
Dbg_RREADY_6 => Dbg_RREADY_6, -- [out std_logic]
Dbg_Disable_7 => Dbg_Disable_7, -- [out std_logic]
Dbg_Clk_7 => Dbg_Clk_7, -- [out std_logic]
Dbg_TDI_7 => Dbg_TDI_7, -- [out std_logic]
Dbg_TDO_7 => Dbg_TDO_7, -- [in std_logic]
Dbg_Reg_En_7 => Dbg_Reg_En_7, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_7 => Dbg_Capture_7, -- [out std_logic]
Dbg_Shift_7 => Dbg_Shift_7, -- [out std_logic]
Dbg_Update_7 => Dbg_Update_7, -- [out std_logic]
Dbg_Rst_7 => Dbg_Rst_7, -- [out std_logic]
Dbg_Trig_In_7 => Dbg_Trig_In_7, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_7 => Dbg_Trig_Ack_In_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_7 => Dbg_Trig_Out_7, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_7 => Dbg_Trig_Ack_Out_7, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_7 => Dbg_TrClk_7, -- [out std_logic]
Dbg_TrData_7 => Dbg_TrData_7, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_7 => Dbg_TrReady_7, -- [out std_logic]
Dbg_TrValid_7 => Dbg_TrValid_7, -- [in std_logic]
Dbg_AWADDR_7 => Dbg_AWADDR_7, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_7 => Dbg_AWVALID_7, -- [out std_logic]
Dbg_AWREADY_7 => Dbg_AWREADY_7, -- [in std_logic]
Dbg_WDATA_7 => Dbg_WDATA_7, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_7 => Dbg_WVALID_7, -- [out std_logic]
Dbg_WREADY_7 => Dbg_WREADY_7, -- [in std_logic]
Dbg_BRESP_7 => Dbg_BRESP_7, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_7 => Dbg_BVALID_7, -- [in std_logic]
Dbg_BREADY_7 => Dbg_BREADY_7, -- [out std_logic]
Dbg_ARADDR_7 => Dbg_ARADDR_7, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_7 => Dbg_ARVALID_7, -- [out std_logic]
Dbg_ARREADY_7 => Dbg_ARREADY_7, -- [in std_logic]
Dbg_RDATA_7 => Dbg_RDATA_7, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_7 => Dbg_RRESP_7, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_7 => Dbg_RVALID_7, -- [in std_logic]
Dbg_RREADY_7 => Dbg_RREADY_7, -- [out std_logic]
Dbg_Disable_8 => Dbg_Disable_8, -- [out std_logic]
Dbg_Clk_8 => Dbg_Clk_8, -- [out std_logic]
Dbg_TDI_8 => Dbg_TDI_8, -- [out std_logic]
Dbg_TDO_8 => Dbg_TDO_8, -- [in std_logic]
Dbg_Reg_En_8 => Dbg_Reg_En_8, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_8 => Dbg_Capture_8, -- [out std_logic]
Dbg_Shift_8 => Dbg_Shift_8, -- [out std_logic]
Dbg_Update_8 => Dbg_Update_8, -- [out std_logic]
Dbg_Rst_8 => Dbg_Rst_8, -- [out std_logic]
Dbg_Trig_In_8 => Dbg_Trig_In_8, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_8 => Dbg_Trig_Ack_In_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_8 => Dbg_Trig_Out_8, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_8 => Dbg_Trig_Ack_Out_8, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_8 => Dbg_TrClk_8, -- [out std_logic]
Dbg_TrData_8 => Dbg_TrData_8, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_8 => Dbg_TrReady_8, -- [out std_logic]
Dbg_TrValid_8 => Dbg_TrValid_8, -- [in std_logic]
Dbg_AWADDR_8 => Dbg_AWADDR_8, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_8 => Dbg_AWVALID_8, -- [out std_logic]
Dbg_AWREADY_8 => Dbg_AWREADY_8, -- [in std_logic]
Dbg_WDATA_8 => Dbg_WDATA_8, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_8 => Dbg_WVALID_8, -- [out std_logic]
Dbg_WREADY_8 => Dbg_WREADY_8, -- [in std_logic]
Dbg_BRESP_8 => Dbg_BRESP_8, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_8 => Dbg_BVALID_8, -- [in std_logic]
Dbg_BREADY_8 => Dbg_BREADY_8, -- [out std_logic]
Dbg_ARADDR_8 => Dbg_ARADDR_8, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_8 => Dbg_ARVALID_8, -- [out std_logic]
Dbg_ARREADY_8 => Dbg_ARREADY_8, -- [in std_logic]
Dbg_RDATA_8 => Dbg_RDATA_8, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_8 => Dbg_RRESP_8, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_8 => Dbg_RVALID_8, -- [in std_logic]
Dbg_RREADY_8 => Dbg_RREADY_8, -- [out std_logic]
Dbg_Disable_9 => Dbg_Disable_9, -- [out std_logic]
Dbg_Clk_9 => Dbg_Clk_9, -- [out std_logic]
Dbg_TDI_9 => Dbg_TDI_9, -- [out std_logic]
Dbg_TDO_9 => Dbg_TDO_9, -- [in std_logic]
Dbg_Reg_En_9 => Dbg_Reg_En_9, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_9 => Dbg_Capture_9, -- [out std_logic]
Dbg_Shift_9 => Dbg_Shift_9, -- [out std_logic]
Dbg_Update_9 => Dbg_Update_9, -- [out std_logic]
Dbg_Rst_9 => Dbg_Rst_9, -- [out std_logic]
Dbg_Trig_In_9 => Dbg_Trig_In_9, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_9 => Dbg_Trig_Ack_In_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_9 => Dbg_Trig_Out_9, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_9 => Dbg_Trig_Ack_Out_9, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_9 => Dbg_TrClk_9, -- [out std_logic]
Dbg_TrData_9 => Dbg_TrData_9, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_9 => Dbg_TrReady_9, -- [out std_logic]
Dbg_TrValid_9 => Dbg_TrValid_9, -- [in std_logic]
Dbg_AWADDR_9 => Dbg_AWADDR_9, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_9 => Dbg_AWVALID_9, -- [out std_logic]
Dbg_AWREADY_9 => Dbg_AWREADY_9, -- [in std_logic]
Dbg_WDATA_9 => Dbg_WDATA_9, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_9 => Dbg_WVALID_9, -- [out std_logic]
Dbg_WREADY_9 => Dbg_WREADY_9, -- [in std_logic]
Dbg_BRESP_9 => Dbg_BRESP_9, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_9 => Dbg_BVALID_9, -- [in std_logic]
Dbg_BREADY_9 => Dbg_BREADY_9, -- [out std_logic]
Dbg_ARADDR_9 => Dbg_ARADDR_9, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_9 => Dbg_ARVALID_9, -- [out std_logic]
Dbg_ARREADY_9 => Dbg_ARREADY_9, -- [in std_logic]
Dbg_RDATA_9 => Dbg_RDATA_9, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_9 => Dbg_RRESP_9, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_9 => Dbg_RVALID_9, -- [in std_logic]
Dbg_RREADY_9 => Dbg_RREADY_9, -- [out std_logic]
Dbg_Disable_10 => Dbg_Disable_10, -- [out std_logic]
Dbg_Clk_10 => Dbg_Clk_10, -- [out std_logic]
Dbg_TDI_10 => Dbg_TDI_10, -- [out std_logic]
Dbg_TDO_10 => Dbg_TDO_10, -- [in std_logic]
Dbg_Reg_En_10 => Dbg_Reg_En_10, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_10 => Dbg_Capture_10, -- [out std_logic]
Dbg_Shift_10 => Dbg_Shift_10, -- [out std_logic]
Dbg_Update_10 => Dbg_Update_10, -- [out std_logic]
Dbg_Rst_10 => Dbg_Rst_10, -- [out std_logic]
Dbg_Trig_In_10 => Dbg_Trig_In_10, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_10 => Dbg_Trig_Ack_In_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_10 => Dbg_Trig_Out_10, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_10 => Dbg_Trig_Ack_Out_10, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_10 => Dbg_TrClk_10, -- [out std_logic]
Dbg_TrData_10 => Dbg_TrData_10, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_10 => Dbg_TrReady_10, -- [out std_logic]
Dbg_TrValid_10 => Dbg_TrValid_10, -- [in std_logic]
Dbg_AWADDR_10 => Dbg_AWADDR_10, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_10 => Dbg_AWVALID_10, -- [out std_logic]
Dbg_AWREADY_10 => Dbg_AWREADY_10, -- [in std_logic]
Dbg_WDATA_10 => Dbg_WDATA_10, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_10 => Dbg_WVALID_10, -- [out std_logic]
Dbg_WREADY_10 => Dbg_WREADY_10, -- [in std_logic]
Dbg_BRESP_10 => Dbg_BRESP_10, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_10 => Dbg_BVALID_10, -- [in std_logic]
Dbg_BREADY_10 => Dbg_BREADY_10, -- [out std_logic]
Dbg_ARADDR_10 => Dbg_ARADDR_10, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_10 => Dbg_ARVALID_10, -- [out std_logic]
Dbg_ARREADY_10 => Dbg_ARREADY_10, -- [in std_logic]
Dbg_RDATA_10 => Dbg_RDATA_10, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_10 => Dbg_RRESP_10, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_10 => Dbg_RVALID_10, -- [in std_logic]
Dbg_RREADY_10 => Dbg_RREADY_10, -- [out std_logic]
Dbg_Disable_11 => Dbg_Disable_11, -- [out std_logic]
Dbg_Clk_11 => Dbg_Clk_11, -- [out std_logic]
Dbg_TDI_11 => Dbg_TDI_11, -- [out std_logic]
Dbg_TDO_11 => Dbg_TDO_11, -- [in std_logic]
Dbg_Reg_En_11 => Dbg_Reg_En_11, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_11 => Dbg_Capture_11, -- [out std_logic]
Dbg_Shift_11 => Dbg_Shift_11, -- [out std_logic]
Dbg_Update_11 => Dbg_Update_11, -- [out std_logic]
Dbg_Rst_11 => Dbg_Rst_11, -- [out std_logic]
Dbg_Trig_In_11 => Dbg_Trig_In_11, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_11 => Dbg_Trig_Ack_In_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_11 => Dbg_Trig_Out_11, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_11 => Dbg_Trig_Ack_Out_11, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_11 => Dbg_TrClk_11, -- [out std_logic]
Dbg_TrData_11 => Dbg_TrData_11, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_11 => Dbg_TrReady_11, -- [out std_logic]
Dbg_TrValid_11 => Dbg_TrValid_11, -- [in std_logic]
Dbg_AWADDR_11 => Dbg_AWADDR_11, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_11 => Dbg_AWVALID_11, -- [out std_logic]
Dbg_AWREADY_11 => Dbg_AWREADY_11, -- [in std_logic]
Dbg_WDATA_11 => Dbg_WDATA_11, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_11 => Dbg_WVALID_11, -- [out std_logic]
Dbg_WREADY_11 => Dbg_WREADY_11, -- [in std_logic]
Dbg_BRESP_11 => Dbg_BRESP_11, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_11 => Dbg_BVALID_11, -- [in std_logic]
Dbg_BREADY_11 => Dbg_BREADY_11, -- [out std_logic]
Dbg_ARADDR_11 => Dbg_ARADDR_11, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_11 => Dbg_ARVALID_11, -- [out std_logic]
Dbg_ARREADY_11 => Dbg_ARREADY_11, -- [in std_logic]
Dbg_RDATA_11 => Dbg_RDATA_11, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_11 => Dbg_RRESP_11, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_11 => Dbg_RVALID_11, -- [in std_logic]
Dbg_RREADY_11 => Dbg_RREADY_11, -- [out std_logic]
Dbg_Disable_12 => Dbg_Disable_12, -- [out std_logic]
Dbg_Clk_12 => Dbg_Clk_12, -- [out std_logic]
Dbg_TDI_12 => Dbg_TDI_12, -- [out std_logic]
Dbg_TDO_12 => Dbg_TDO_12, -- [in std_logic]
Dbg_Reg_En_12 => Dbg_Reg_En_12, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_12 => Dbg_Capture_12, -- [out std_logic]
Dbg_Shift_12 => Dbg_Shift_12, -- [out std_logic]
Dbg_Update_12 => Dbg_Update_12, -- [out std_logic]
Dbg_Rst_12 => Dbg_Rst_12, -- [out std_logic]
Dbg_Trig_In_12 => Dbg_Trig_In_12, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_12 => Dbg_Trig_Ack_In_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_12 => Dbg_Trig_Out_12, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_12 => Dbg_Trig_Ack_Out_12, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_12 => Dbg_TrClk_12, -- [out std_logic]
Dbg_TrData_12 => Dbg_TrData_12, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_12 => Dbg_TrReady_12, -- [out std_logic]
Dbg_TrValid_12 => Dbg_TrValid_12, -- [in std_logic]
Dbg_AWADDR_12 => Dbg_AWADDR_12, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_12 => Dbg_AWVALID_12, -- [out std_logic]
Dbg_AWREADY_12 => Dbg_AWREADY_12, -- [in std_logic]
Dbg_WDATA_12 => Dbg_WDATA_12, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_12 => Dbg_WVALID_12, -- [out std_logic]
Dbg_WREADY_12 => Dbg_WREADY_12, -- [in std_logic]
Dbg_BRESP_12 => Dbg_BRESP_12, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_12 => Dbg_BVALID_12, -- [in std_logic]
Dbg_BREADY_12 => Dbg_BREADY_12, -- [out std_logic]
Dbg_ARADDR_12 => Dbg_ARADDR_12, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_12 => Dbg_ARVALID_12, -- [out std_logic]
Dbg_ARREADY_12 => Dbg_ARREADY_12, -- [in std_logic]
Dbg_RDATA_12 => Dbg_RDATA_12, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_12 => Dbg_RRESP_12, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_12 => Dbg_RVALID_12, -- [in std_logic]
Dbg_RREADY_12 => Dbg_RREADY_12, -- [out std_logic]
Dbg_Disable_13 => Dbg_Disable_13, -- [out std_logic]
Dbg_Clk_13 => Dbg_Clk_13, -- [out std_logic]
Dbg_TDI_13 => Dbg_TDI_13, -- [out std_logic]
Dbg_TDO_13 => Dbg_TDO_13, -- [in std_logic]
Dbg_Reg_En_13 => Dbg_Reg_En_13, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_13 => Dbg_Capture_13, -- [out std_logic]
Dbg_Shift_13 => Dbg_Shift_13, -- [out std_logic]
Dbg_Update_13 => Dbg_Update_13, -- [out std_logic]
Dbg_Rst_13 => Dbg_Rst_13, -- [out std_logic]
Dbg_Trig_In_13 => Dbg_Trig_In_13, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_13 => Dbg_Trig_Ack_In_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_13 => Dbg_Trig_Out_13, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_13 => Dbg_Trig_Ack_Out_13, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_13 => Dbg_TrClk_13, -- [out std_logic]
Dbg_TrData_13 => Dbg_TrData_13, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_13 => Dbg_TrReady_13, -- [out std_logic]
Dbg_TrValid_13 => Dbg_TrValid_13, -- [in std_logic]
Dbg_AWADDR_13 => Dbg_AWADDR_13, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_13 => Dbg_AWVALID_13, -- [out std_logic]
Dbg_AWREADY_13 => Dbg_AWREADY_13, -- [in std_logic]
Dbg_WDATA_13 => Dbg_WDATA_13, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_13 => Dbg_WVALID_13, -- [out std_logic]
Dbg_WREADY_13 => Dbg_WREADY_13, -- [in std_logic]
Dbg_BRESP_13 => Dbg_BRESP_13, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_13 => Dbg_BVALID_13, -- [in std_logic]
Dbg_BREADY_13 => Dbg_BREADY_13, -- [out std_logic]
Dbg_ARADDR_13 => Dbg_ARADDR_13, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_13 => Dbg_ARVALID_13, -- [out std_logic]
Dbg_ARREADY_13 => Dbg_ARREADY_13, -- [in std_logic]
Dbg_RDATA_13 => Dbg_RDATA_13, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_13 => Dbg_RRESP_13, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_13 => Dbg_RVALID_13, -- [in std_logic]
Dbg_RREADY_13 => Dbg_RREADY_13, -- [out std_logic]
Dbg_Disable_14 => Dbg_Disable_14, -- [out std_logic]
Dbg_Clk_14 => Dbg_Clk_14, -- [out std_logic]
Dbg_TDI_14 => Dbg_TDI_14, -- [out std_logic]
Dbg_TDO_14 => Dbg_TDO_14, -- [in std_logic]
Dbg_Reg_En_14 => Dbg_Reg_En_14, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_14 => Dbg_Capture_14, -- [out std_logic]
Dbg_Shift_14 => Dbg_Shift_14, -- [out std_logic]
Dbg_Update_14 => Dbg_Update_14, -- [out std_logic]
Dbg_Rst_14 => Dbg_Rst_14, -- [out std_logic]
Dbg_Trig_In_14 => Dbg_Trig_In_14, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_14 => Dbg_Trig_Ack_In_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_14 => Dbg_Trig_Out_14, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_14 => Dbg_Trig_Ack_Out_14, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_14 => Dbg_TrClk_14, -- [out std_logic]
Dbg_TrData_14 => Dbg_TrData_14, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_14 => Dbg_TrReady_14, -- [out std_logic]
Dbg_TrValid_14 => Dbg_TrValid_14, -- [in std_logic]
Dbg_AWADDR_14 => Dbg_AWADDR_14, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_14 => Dbg_AWVALID_14, -- [out std_logic]
Dbg_AWREADY_14 => Dbg_AWREADY_14, -- [in std_logic]
Dbg_WDATA_14 => Dbg_WDATA_14, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_14 => Dbg_WVALID_14, -- [out std_logic]
Dbg_WREADY_14 => Dbg_WREADY_14, -- [in std_logic]
Dbg_BRESP_14 => Dbg_BRESP_14, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_14 => Dbg_BVALID_14, -- [in std_logic]
Dbg_BREADY_14 => Dbg_BREADY_14, -- [out std_logic]
Dbg_ARADDR_14 => Dbg_ARADDR_14, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_14 => Dbg_ARVALID_14, -- [out std_logic]
Dbg_ARREADY_14 => Dbg_ARREADY_14, -- [in std_logic]
Dbg_RDATA_14 => Dbg_RDATA_14, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_14 => Dbg_RRESP_14, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_14 => Dbg_RVALID_14, -- [in std_logic]
Dbg_RREADY_14 => Dbg_RREADY_14, -- [out std_logic]
Dbg_Disable_15 => Dbg_Disable_15, -- [out std_logic]
Dbg_Clk_15 => Dbg_Clk_15, -- [out std_logic]
Dbg_TDI_15 => Dbg_TDI_15, -- [out std_logic]
Dbg_TDO_15 => Dbg_TDO_15, -- [in std_logic]
Dbg_Reg_En_15 => Dbg_Reg_En_15, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_15 => Dbg_Capture_15, -- [out std_logic]
Dbg_Shift_15 => Dbg_Shift_15, -- [out std_logic]
Dbg_Update_15 => Dbg_Update_15, -- [out std_logic]
Dbg_Rst_15 => Dbg_Rst_15, -- [out std_logic]
Dbg_Trig_In_15 => Dbg_Trig_In_15, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_15 => Dbg_Trig_Ack_In_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_15 => Dbg_Trig_Out_15, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_15 => Dbg_Trig_Ack_Out_15, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_15 => Dbg_TrClk_15, -- [out std_logic]
Dbg_TrData_15 => Dbg_TrData_15, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_15 => Dbg_TrReady_15, -- [out std_logic]
Dbg_TrValid_15 => Dbg_TrValid_15, -- [in std_logic]
Dbg_AWADDR_15 => Dbg_AWADDR_15, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_15 => Dbg_AWVALID_15, -- [out std_logic]
Dbg_AWREADY_15 => Dbg_AWREADY_15, -- [in std_logic]
Dbg_WDATA_15 => Dbg_WDATA_15, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_15 => Dbg_WVALID_15, -- [out std_logic]
Dbg_WREADY_15 => Dbg_WREADY_15, -- [in std_logic]
Dbg_BRESP_15 => Dbg_BRESP_15, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_15 => Dbg_BVALID_15, -- [in std_logic]
Dbg_BREADY_15 => Dbg_BREADY_15, -- [out std_logic]
Dbg_ARADDR_15 => Dbg_ARADDR_15, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_15 => Dbg_ARVALID_15, -- [out std_logic]
Dbg_ARREADY_15 => Dbg_ARREADY_15, -- [in std_logic]
Dbg_RDATA_15 => Dbg_RDATA_15, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_15 => Dbg_RRESP_15, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_15 => Dbg_RVALID_15, -- [in std_logic]
Dbg_RREADY_15 => Dbg_RREADY_15, -- [out std_logic]
Dbg_Disable_16 => Dbg_Disable_16, -- [out std_logic]
Dbg_Clk_16 => Dbg_Clk_16, -- [out std_logic]
Dbg_TDI_16 => Dbg_TDI_16, -- [out std_logic]
Dbg_TDO_16 => Dbg_TDO_16, -- [in std_logic]
Dbg_Reg_En_16 => Dbg_Reg_En_16, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_16 => Dbg_Capture_16, -- [out std_logic]
Dbg_Shift_16 => Dbg_Shift_16, -- [out std_logic]
Dbg_Update_16 => Dbg_Update_16, -- [out std_logic]
Dbg_Rst_16 => Dbg_Rst_16, -- [out std_logic]
Dbg_Trig_In_16 => Dbg_Trig_In_16, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_16 => Dbg_Trig_Ack_In_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_16 => Dbg_Trig_Out_16, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_16 => Dbg_Trig_Ack_Out_16, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_16 => Dbg_TrClk_16, -- [out std_logic]
Dbg_TrData_16 => Dbg_TrData_16, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_16 => Dbg_TrReady_16, -- [out std_logic]
Dbg_TrValid_16 => Dbg_TrValid_16, -- [in std_logic]
Dbg_AWADDR_16 => Dbg_AWADDR_16, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_16 => Dbg_AWVALID_16, -- [out std_logic]
Dbg_AWREADY_16 => Dbg_AWREADY_16, -- [in std_logic]
Dbg_WDATA_16 => Dbg_WDATA_16, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_16 => Dbg_WVALID_16, -- [out std_logic]
Dbg_WREADY_16 => Dbg_WREADY_16, -- [in std_logic]
Dbg_BRESP_16 => Dbg_BRESP_16, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_16 => Dbg_BVALID_16, -- [in std_logic]
Dbg_BREADY_16 => Dbg_BREADY_16, -- [out std_logic]
Dbg_ARADDR_16 => Dbg_ARADDR_16, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_16 => Dbg_ARVALID_16, -- [out std_logic]
Dbg_ARREADY_16 => Dbg_ARREADY_16, -- [in std_logic]
Dbg_RDATA_16 => Dbg_RDATA_16, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_16 => Dbg_RRESP_16, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_16 => Dbg_RVALID_16, -- [in std_logic]
Dbg_RREADY_16 => Dbg_RREADY_16, -- [out std_logic]
Dbg_Disable_17 => Dbg_Disable_17, -- [out std_logic]
Dbg_Clk_17 => Dbg_Clk_17, -- [out std_logic]
Dbg_TDI_17 => Dbg_TDI_17, -- [out std_logic]
Dbg_TDO_17 => Dbg_TDO_17, -- [in std_logic]
Dbg_Reg_En_17 => Dbg_Reg_En_17, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_17 => Dbg_Capture_17, -- [out std_logic]
Dbg_Shift_17 => Dbg_Shift_17, -- [out std_logic]
Dbg_Update_17 => Dbg_Update_17, -- [out std_logic]
Dbg_Rst_17 => Dbg_Rst_17, -- [out std_logic]
Dbg_Trig_In_17 => Dbg_Trig_In_17, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_17 => Dbg_Trig_Ack_In_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_17 => Dbg_Trig_Out_17, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_17 => Dbg_Trig_Ack_Out_17, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_17 => Dbg_TrClk_17, -- [out std_logic]
Dbg_TrData_17 => Dbg_TrData_17, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_17 => Dbg_TrReady_17, -- [out std_logic]
Dbg_TrValid_17 => Dbg_TrValid_17, -- [in std_logic]
Dbg_AWADDR_17 => Dbg_AWADDR_17, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_17 => Dbg_AWVALID_17, -- [out std_logic]
Dbg_AWREADY_17 => Dbg_AWREADY_17, -- [in std_logic]
Dbg_WDATA_17 => Dbg_WDATA_17, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_17 => Dbg_WVALID_17, -- [out std_logic]
Dbg_WREADY_17 => Dbg_WREADY_17, -- [in std_logic]
Dbg_BRESP_17 => Dbg_BRESP_17, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_17 => Dbg_BVALID_17, -- [in std_logic]
Dbg_BREADY_17 => Dbg_BREADY_17, -- [out std_logic]
Dbg_ARADDR_17 => Dbg_ARADDR_17, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_17 => Dbg_ARVALID_17, -- [out std_logic]
Dbg_ARREADY_17 => Dbg_ARREADY_17, -- [in std_logic]
Dbg_RDATA_17 => Dbg_RDATA_17, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_17 => Dbg_RRESP_17, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_17 => Dbg_RVALID_17, -- [in std_logic]
Dbg_RREADY_17 => Dbg_RREADY_17, -- [out std_logic]
Dbg_Disable_18 => Dbg_Disable_18, -- [out std_logic]
Dbg_Clk_18 => Dbg_Clk_18, -- [out std_logic]
Dbg_TDI_18 => Dbg_TDI_18, -- [out std_logic]
Dbg_TDO_18 => Dbg_TDO_18, -- [in std_logic]
Dbg_Reg_En_18 => Dbg_Reg_En_18, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_18 => Dbg_Capture_18, -- [out std_logic]
Dbg_Shift_18 => Dbg_Shift_18, -- [out std_logic]
Dbg_Update_18 => Dbg_Update_18, -- [out std_logic]
Dbg_Rst_18 => Dbg_Rst_18, -- [out std_logic]
Dbg_Trig_In_18 => Dbg_Trig_In_18, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_18 => Dbg_Trig_Ack_In_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_18 => Dbg_Trig_Out_18, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_18 => Dbg_Trig_Ack_Out_18, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_18 => Dbg_TrClk_18, -- [out std_logic]
Dbg_TrData_18 => Dbg_TrData_18, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_18 => Dbg_TrReady_18, -- [out std_logic]
Dbg_TrValid_18 => Dbg_TrValid_18, -- [in std_logic]
Dbg_AWADDR_18 => Dbg_AWADDR_18, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_18 => Dbg_AWVALID_18, -- [out std_logic]
Dbg_AWREADY_18 => Dbg_AWREADY_18, -- [in std_logic]
Dbg_WDATA_18 => Dbg_WDATA_18, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_18 => Dbg_WVALID_18, -- [out std_logic]
Dbg_WREADY_18 => Dbg_WREADY_18, -- [in std_logic]
Dbg_BRESP_18 => Dbg_BRESP_18, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_18 => Dbg_BVALID_18, -- [in std_logic]
Dbg_BREADY_18 => Dbg_BREADY_18, -- [out std_logic]
Dbg_ARADDR_18 => Dbg_ARADDR_18, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_18 => Dbg_ARVALID_18, -- [out std_logic]
Dbg_ARREADY_18 => Dbg_ARREADY_18, -- [in std_logic]
Dbg_RDATA_18 => Dbg_RDATA_18, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_18 => Dbg_RRESP_18, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_18 => Dbg_RVALID_18, -- [in std_logic]
Dbg_RREADY_18 => Dbg_RREADY_18, -- [out std_logic]
Dbg_Disable_19 => Dbg_Disable_19, -- [out std_logic]
Dbg_Clk_19 => Dbg_Clk_19, -- [out std_logic]
Dbg_TDI_19 => Dbg_TDI_19, -- [out std_logic]
Dbg_TDO_19 => Dbg_TDO_19, -- [in std_logic]
Dbg_Reg_En_19 => Dbg_Reg_En_19, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_19 => Dbg_Capture_19, -- [out std_logic]
Dbg_Shift_19 => Dbg_Shift_19, -- [out std_logic]
Dbg_Update_19 => Dbg_Update_19, -- [out std_logic]
Dbg_Rst_19 => Dbg_Rst_19, -- [out std_logic]
Dbg_Trig_In_19 => Dbg_Trig_In_19, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_19 => Dbg_Trig_Ack_In_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_19 => Dbg_Trig_Out_19, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_19 => Dbg_Trig_Ack_Out_19, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_19 => Dbg_TrClk_19, -- [out std_logic]
Dbg_TrData_19 => Dbg_TrData_19, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_19 => Dbg_TrReady_19, -- [out std_logic]
Dbg_TrValid_19 => Dbg_TrValid_19, -- [in std_logic]
Dbg_AWADDR_19 => Dbg_AWADDR_19, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_19 => Dbg_AWVALID_19, -- [out std_logic]
Dbg_AWREADY_19 => Dbg_AWREADY_19, -- [in std_logic]
Dbg_WDATA_19 => Dbg_WDATA_19, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_19 => Dbg_WVALID_19, -- [out std_logic]
Dbg_WREADY_19 => Dbg_WREADY_19, -- [in std_logic]
Dbg_BRESP_19 => Dbg_BRESP_19, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_19 => Dbg_BVALID_19, -- [in std_logic]
Dbg_BREADY_19 => Dbg_BREADY_19, -- [out std_logic]
Dbg_ARADDR_19 => Dbg_ARADDR_19, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_19 => Dbg_ARVALID_19, -- [out std_logic]
Dbg_ARREADY_19 => Dbg_ARREADY_19, -- [in std_logic]
Dbg_RDATA_19 => Dbg_RDATA_19, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_19 => Dbg_RRESP_19, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_19 => Dbg_RVALID_19, -- [in std_logic]
Dbg_RREADY_19 => Dbg_RREADY_19, -- [out std_logic]
Dbg_Disable_20 => Dbg_Disable_20, -- [out std_logic]
Dbg_Clk_20 => Dbg_Clk_20, -- [out std_logic]
Dbg_TDI_20 => Dbg_TDI_20, -- [out std_logic]
Dbg_TDO_20 => Dbg_TDO_20, -- [in std_logic]
Dbg_Reg_En_20 => Dbg_Reg_En_20, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_20 => Dbg_Capture_20, -- [out std_logic]
Dbg_Shift_20 => Dbg_Shift_20, -- [out std_logic]
Dbg_Update_20 => Dbg_Update_20, -- [out std_logic]
Dbg_Rst_20 => Dbg_Rst_20, -- [out std_logic]
Dbg_Trig_In_20 => Dbg_Trig_In_20, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_20 => Dbg_Trig_Ack_In_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_20 => Dbg_Trig_Out_20, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_20 => Dbg_Trig_Ack_Out_20, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_20 => Dbg_TrClk_20, -- [out std_logic]
Dbg_TrData_20 => Dbg_TrData_20, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_20 => Dbg_TrReady_20, -- [out std_logic]
Dbg_TrValid_20 => Dbg_TrValid_20, -- [in std_logic]
Dbg_AWADDR_20 => Dbg_AWADDR_20, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_20 => Dbg_AWVALID_20, -- [out std_logic]
Dbg_AWREADY_20 => Dbg_AWREADY_20, -- [in std_logic]
Dbg_WDATA_20 => Dbg_WDATA_20, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_20 => Dbg_WVALID_20, -- [out std_logic]
Dbg_WREADY_20 => Dbg_WREADY_20, -- [in std_logic]
Dbg_BRESP_20 => Dbg_BRESP_20, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_20 => Dbg_BVALID_20, -- [in std_logic]
Dbg_BREADY_20 => Dbg_BREADY_20, -- [out std_logic]
Dbg_ARADDR_20 => Dbg_ARADDR_20, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_20 => Dbg_ARVALID_20, -- [out std_logic]
Dbg_ARREADY_20 => Dbg_ARREADY_20, -- [in std_logic]
Dbg_RDATA_20 => Dbg_RDATA_20, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_20 => Dbg_RRESP_20, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_20 => Dbg_RVALID_20, -- [in std_logic]
Dbg_RREADY_20 => Dbg_RREADY_20, -- [out std_logic]
Dbg_Disable_21 => Dbg_Disable_21, -- [out std_logic]
Dbg_Clk_21 => Dbg_Clk_21, -- [out std_logic]
Dbg_TDI_21 => Dbg_TDI_21, -- [out std_logic]
Dbg_TDO_21 => Dbg_TDO_21, -- [in std_logic]
Dbg_Reg_En_21 => Dbg_Reg_En_21, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_21 => Dbg_Capture_21, -- [out std_logic]
Dbg_Shift_21 => Dbg_Shift_21, -- [out std_logic]
Dbg_Update_21 => Dbg_Update_21, -- [out std_logic]
Dbg_Rst_21 => Dbg_Rst_21, -- [out std_logic]
Dbg_Trig_In_21 => Dbg_Trig_In_21, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_21 => Dbg_Trig_Ack_In_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_21 => Dbg_Trig_Out_21, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_21 => Dbg_Trig_Ack_Out_21, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_21 => Dbg_TrClk_21, -- [out std_logic]
Dbg_TrData_21 => Dbg_TrData_21, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_21 => Dbg_TrReady_21, -- [out std_logic]
Dbg_TrValid_21 => Dbg_TrValid_21, -- [in std_logic]
Dbg_AWADDR_21 => Dbg_AWADDR_21, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_21 => Dbg_AWVALID_21, -- [out std_logic]
Dbg_AWREADY_21 => Dbg_AWREADY_21, -- [in std_logic]
Dbg_WDATA_21 => Dbg_WDATA_21, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_21 => Dbg_WVALID_21, -- [out std_logic]
Dbg_WREADY_21 => Dbg_WREADY_21, -- [in std_logic]
Dbg_BRESP_21 => Dbg_BRESP_21, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_21 => Dbg_BVALID_21, -- [in std_logic]
Dbg_BREADY_21 => Dbg_BREADY_21, -- [out std_logic]
Dbg_ARADDR_21 => Dbg_ARADDR_21, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_21 => Dbg_ARVALID_21, -- [out std_logic]
Dbg_ARREADY_21 => Dbg_ARREADY_21, -- [in std_logic]
Dbg_RDATA_21 => Dbg_RDATA_21, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_21 => Dbg_RRESP_21, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_21 => Dbg_RVALID_21, -- [in std_logic]
Dbg_RREADY_21 => Dbg_RREADY_21, -- [out std_logic]
Dbg_Disable_22 => Dbg_Disable_22, -- [out std_logic]
Dbg_Clk_22 => Dbg_Clk_22, -- [out std_logic]
Dbg_TDI_22 => Dbg_TDI_22, -- [out std_logic]
Dbg_TDO_22 => Dbg_TDO_22, -- [in std_logic]
Dbg_Reg_En_22 => Dbg_Reg_En_22, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_22 => Dbg_Capture_22, -- [out std_logic]
Dbg_Shift_22 => Dbg_Shift_22, -- [out std_logic]
Dbg_Update_22 => Dbg_Update_22, -- [out std_logic]
Dbg_Rst_22 => Dbg_Rst_22, -- [out std_logic]
Dbg_Trig_In_22 => Dbg_Trig_In_22, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_22 => Dbg_Trig_Ack_In_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_22 => Dbg_Trig_Out_22, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_22 => Dbg_Trig_Ack_Out_22, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_22 => Dbg_TrClk_22, -- [out std_logic]
Dbg_TrData_22 => Dbg_TrData_22, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_22 => Dbg_TrReady_22, -- [out std_logic]
Dbg_TrValid_22 => Dbg_TrValid_22, -- [in std_logic]
Dbg_AWADDR_22 => Dbg_AWADDR_22, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_22 => Dbg_AWVALID_22, -- [out std_logic]
Dbg_AWREADY_22 => Dbg_AWREADY_22, -- [in std_logic]
Dbg_WDATA_22 => Dbg_WDATA_22, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_22 => Dbg_WVALID_22, -- [out std_logic]
Dbg_WREADY_22 => Dbg_WREADY_22, -- [in std_logic]
Dbg_BRESP_22 => Dbg_BRESP_22, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_22 => Dbg_BVALID_22, -- [in std_logic]
Dbg_BREADY_22 => Dbg_BREADY_22, -- [out std_logic]
Dbg_ARADDR_22 => Dbg_ARADDR_22, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_22 => Dbg_ARVALID_22, -- [out std_logic]
Dbg_ARREADY_22 => Dbg_ARREADY_22, -- [in std_logic]
Dbg_RDATA_22 => Dbg_RDATA_22, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_22 => Dbg_RRESP_22, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_22 => Dbg_RVALID_22, -- [in std_logic]
Dbg_RREADY_22 => Dbg_RREADY_22, -- [out std_logic]
Dbg_Disable_23 => Dbg_Disable_23, -- [out std_logic]
Dbg_Clk_23 => Dbg_Clk_23, -- [out std_logic]
Dbg_TDI_23 => Dbg_TDI_23, -- [out std_logic]
Dbg_TDO_23 => Dbg_TDO_23, -- [in std_logic]
Dbg_Reg_En_23 => Dbg_Reg_En_23, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_23 => Dbg_Capture_23, -- [out std_logic]
Dbg_Shift_23 => Dbg_Shift_23, -- [out std_logic]
Dbg_Update_23 => Dbg_Update_23, -- [out std_logic]
Dbg_Rst_23 => Dbg_Rst_23, -- [out std_logic]
Dbg_Trig_In_23 => Dbg_Trig_In_23, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_23 => Dbg_Trig_Ack_In_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_23 => Dbg_Trig_Out_23, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_23 => Dbg_Trig_Ack_Out_23, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_23 => Dbg_TrClk_23, -- [out std_logic]
Dbg_TrData_23 => Dbg_TrData_23, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_23 => Dbg_TrReady_23, -- [out std_logic]
Dbg_TrValid_23 => Dbg_TrValid_23, -- [in std_logic]
Dbg_AWADDR_23 => Dbg_AWADDR_23, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_23 => Dbg_AWVALID_23, -- [out std_logic]
Dbg_AWREADY_23 => Dbg_AWREADY_23, -- [in std_logic]
Dbg_WDATA_23 => Dbg_WDATA_23, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_23 => Dbg_WVALID_23, -- [out std_logic]
Dbg_WREADY_23 => Dbg_WREADY_23, -- [in std_logic]
Dbg_BRESP_23 => Dbg_BRESP_23, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_23 => Dbg_BVALID_23, -- [in std_logic]
Dbg_BREADY_23 => Dbg_BREADY_23, -- [out std_logic]
Dbg_ARADDR_23 => Dbg_ARADDR_23, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_23 => Dbg_ARVALID_23, -- [out std_logic]
Dbg_ARREADY_23 => Dbg_ARREADY_23, -- [in std_logic]
Dbg_RDATA_23 => Dbg_RDATA_23, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_23 => Dbg_RRESP_23, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_23 => Dbg_RVALID_23, -- [in std_logic]
Dbg_RREADY_23 => Dbg_RREADY_23, -- [out std_logic]
Dbg_Disable_24 => Dbg_Disable_24, -- [out std_logic]
Dbg_Clk_24 => Dbg_Clk_24, -- [out std_logic]
Dbg_TDI_24 => Dbg_TDI_24, -- [out std_logic]
Dbg_TDO_24 => Dbg_TDO_24, -- [in std_logic]
Dbg_Reg_En_24 => Dbg_Reg_En_24, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_24 => Dbg_Capture_24, -- [out std_logic]
Dbg_Shift_24 => Dbg_Shift_24, -- [out std_logic]
Dbg_Update_24 => Dbg_Update_24, -- [out std_logic]
Dbg_Rst_24 => Dbg_Rst_24, -- [out std_logic]
Dbg_Trig_In_24 => Dbg_Trig_In_24, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_24 => Dbg_Trig_Ack_In_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_24 => Dbg_Trig_Out_24, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_24 => Dbg_Trig_Ack_Out_24, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_24 => Dbg_TrClk_24, -- [out std_logic]
Dbg_TrData_24 => Dbg_TrData_24, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_24 => Dbg_TrReady_24, -- [out std_logic]
Dbg_TrValid_24 => Dbg_TrValid_24, -- [in std_logic]
Dbg_AWADDR_24 => Dbg_AWADDR_24, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_24 => Dbg_AWVALID_24, -- [out std_logic]
Dbg_AWREADY_24 => Dbg_AWREADY_24, -- [in std_logic]
Dbg_WDATA_24 => Dbg_WDATA_24, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_24 => Dbg_WVALID_24, -- [out std_logic]
Dbg_WREADY_24 => Dbg_WREADY_24, -- [in std_logic]
Dbg_BRESP_24 => Dbg_BRESP_24, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_24 => Dbg_BVALID_24, -- [in std_logic]
Dbg_BREADY_24 => Dbg_BREADY_24, -- [out std_logic]
Dbg_ARADDR_24 => Dbg_ARADDR_24, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_24 => Dbg_ARVALID_24, -- [out std_logic]
Dbg_ARREADY_24 => Dbg_ARREADY_24, -- [in std_logic]
Dbg_RDATA_24 => Dbg_RDATA_24, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_24 => Dbg_RRESP_24, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_24 => Dbg_RVALID_24, -- [in std_logic]
Dbg_RREADY_24 => Dbg_RREADY_24, -- [out std_logic]
Dbg_Disable_25 => Dbg_Disable_25, -- [out std_logic]
Dbg_Clk_25 => Dbg_Clk_25, -- [out std_logic]
Dbg_TDI_25 => Dbg_TDI_25, -- [out std_logic]
Dbg_TDO_25 => Dbg_TDO_25, -- [in std_logic]
Dbg_Reg_En_25 => Dbg_Reg_En_25, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_25 => Dbg_Capture_25, -- [out std_logic]
Dbg_Shift_25 => Dbg_Shift_25, -- [out std_logic]
Dbg_Update_25 => Dbg_Update_25, -- [out std_logic]
Dbg_Rst_25 => Dbg_Rst_25, -- [out std_logic]
Dbg_Trig_In_25 => Dbg_Trig_In_25, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_25 => Dbg_Trig_Ack_In_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_25 => Dbg_Trig_Out_25, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_25 => Dbg_Trig_Ack_Out_25, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_25 => Dbg_TrClk_25, -- [out std_logic]
Dbg_TrData_25 => Dbg_TrData_25, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_25 => Dbg_TrReady_25, -- [out std_logic]
Dbg_TrValid_25 => Dbg_TrValid_25, -- [in std_logic]
Dbg_AWADDR_25 => Dbg_AWADDR_25, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_25 => Dbg_AWVALID_25, -- [out std_logic]
Dbg_AWREADY_25 => Dbg_AWREADY_25, -- [in std_logic]
Dbg_WDATA_25 => Dbg_WDATA_25, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_25 => Dbg_WVALID_25, -- [out std_logic]
Dbg_WREADY_25 => Dbg_WREADY_25, -- [in std_logic]
Dbg_BRESP_25 => Dbg_BRESP_25, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_25 => Dbg_BVALID_25, -- [in std_logic]
Dbg_BREADY_25 => Dbg_BREADY_25, -- [out std_logic]
Dbg_ARADDR_25 => Dbg_ARADDR_25, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_25 => Dbg_ARVALID_25, -- [out std_logic]
Dbg_ARREADY_25 => Dbg_ARREADY_25, -- [in std_logic]
Dbg_RDATA_25 => Dbg_RDATA_25, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_25 => Dbg_RRESP_25, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_25 => Dbg_RVALID_25, -- [in std_logic]
Dbg_RREADY_25 => Dbg_RREADY_25, -- [out std_logic]
Dbg_Disable_26 => Dbg_Disable_26, -- [out std_logic]
Dbg_Clk_26 => Dbg_Clk_26, -- [out std_logic]
Dbg_TDI_26 => Dbg_TDI_26, -- [out std_logic]
Dbg_TDO_26 => Dbg_TDO_26, -- [in std_logic]
Dbg_Reg_En_26 => Dbg_Reg_En_26, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_26 => Dbg_Capture_26, -- [out std_logic]
Dbg_Shift_26 => Dbg_Shift_26, -- [out std_logic]
Dbg_Update_26 => Dbg_Update_26, -- [out std_logic]
Dbg_Rst_26 => Dbg_Rst_26, -- [out std_logic]
Dbg_Trig_In_26 => Dbg_Trig_In_26, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_26 => Dbg_Trig_Ack_In_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_26 => Dbg_Trig_Out_26, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_26 => Dbg_Trig_Ack_Out_26, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_26 => Dbg_TrClk_26, -- [out std_logic]
Dbg_TrData_26 => Dbg_TrData_26, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_26 => Dbg_TrReady_26, -- [out std_logic]
Dbg_TrValid_26 => Dbg_TrValid_26, -- [in std_logic]
Dbg_AWADDR_26 => Dbg_AWADDR_26, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_26 => Dbg_AWVALID_26, -- [out std_logic]
Dbg_AWREADY_26 => Dbg_AWREADY_26, -- [in std_logic]
Dbg_WDATA_26 => Dbg_WDATA_26, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_26 => Dbg_WVALID_26, -- [out std_logic]
Dbg_WREADY_26 => Dbg_WREADY_26, -- [in std_logic]
Dbg_BRESP_26 => Dbg_BRESP_26, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_26 => Dbg_BVALID_26, -- [in std_logic]
Dbg_BREADY_26 => Dbg_BREADY_26, -- [out std_logic]
Dbg_ARADDR_26 => Dbg_ARADDR_26, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_26 => Dbg_ARVALID_26, -- [out std_logic]
Dbg_ARREADY_26 => Dbg_ARREADY_26, -- [in std_logic]
Dbg_RDATA_26 => Dbg_RDATA_26, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_26 => Dbg_RRESP_26, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_26 => Dbg_RVALID_26, -- [in std_logic]
Dbg_RREADY_26 => Dbg_RREADY_26, -- [out std_logic]
Dbg_Disable_27 => Dbg_Disable_27, -- [out std_logic]
Dbg_Clk_27 => Dbg_Clk_27, -- [out std_logic]
Dbg_TDI_27 => Dbg_TDI_27, -- [out std_logic]
Dbg_TDO_27 => Dbg_TDO_27, -- [in std_logic]
Dbg_Reg_En_27 => Dbg_Reg_En_27, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_27 => Dbg_Capture_27, -- [out std_logic]
Dbg_Shift_27 => Dbg_Shift_27, -- [out std_logic]
Dbg_Update_27 => Dbg_Update_27, -- [out std_logic]
Dbg_Rst_27 => Dbg_Rst_27, -- [out std_logic]
Dbg_Trig_In_27 => Dbg_Trig_In_27, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_27 => Dbg_Trig_Ack_In_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_27 => Dbg_Trig_Out_27, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_27 => Dbg_Trig_Ack_Out_27, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_27 => Dbg_TrClk_27, -- [out std_logic]
Dbg_TrData_27 => Dbg_TrData_27, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_27 => Dbg_TrReady_27, -- [out std_logic]
Dbg_TrValid_27 => Dbg_TrValid_27, -- [in std_logic]
Dbg_AWADDR_27 => Dbg_AWADDR_27, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_27 => Dbg_AWVALID_27, -- [out std_logic]
Dbg_AWREADY_27 => Dbg_AWREADY_27, -- [in std_logic]
Dbg_WDATA_27 => Dbg_WDATA_27, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_27 => Dbg_WVALID_27, -- [out std_logic]
Dbg_WREADY_27 => Dbg_WREADY_27, -- [in std_logic]
Dbg_BRESP_27 => Dbg_BRESP_27, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_27 => Dbg_BVALID_27, -- [in std_logic]
Dbg_BREADY_27 => Dbg_BREADY_27, -- [out std_logic]
Dbg_ARADDR_27 => Dbg_ARADDR_27, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_27 => Dbg_ARVALID_27, -- [out std_logic]
Dbg_ARREADY_27 => Dbg_ARREADY_27, -- [in std_logic]
Dbg_RDATA_27 => Dbg_RDATA_27, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_27 => Dbg_RRESP_27, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_27 => Dbg_RVALID_27, -- [in std_logic]
Dbg_RREADY_27 => Dbg_RREADY_27, -- [out std_logic]
Dbg_Disable_28 => Dbg_Disable_28, -- [out std_logic]
Dbg_Clk_28 => Dbg_Clk_28, -- [out std_logic]
Dbg_TDI_28 => Dbg_TDI_28, -- [out std_logic]
Dbg_TDO_28 => Dbg_TDO_28, -- [in std_logic]
Dbg_Reg_En_28 => Dbg_Reg_En_28, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_28 => Dbg_Capture_28, -- [out std_logic]
Dbg_Shift_28 => Dbg_Shift_28, -- [out std_logic]
Dbg_Update_28 => Dbg_Update_28, -- [out std_logic]
Dbg_Rst_28 => Dbg_Rst_28, -- [out std_logic]
Dbg_Trig_In_28 => Dbg_Trig_In_28, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_28 => Dbg_Trig_Ack_In_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_28 => Dbg_Trig_Out_28, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_28 => Dbg_Trig_Ack_Out_28, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_28 => Dbg_TrClk_28, -- [out std_logic]
Dbg_TrData_28 => Dbg_TrData_28, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_28 => Dbg_TrReady_28, -- [out std_logic]
Dbg_TrValid_28 => Dbg_TrValid_28, -- [in std_logic]
Dbg_AWADDR_28 => Dbg_AWADDR_28, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_28 => Dbg_AWVALID_28, -- [out std_logic]
Dbg_AWREADY_28 => Dbg_AWREADY_28, -- [in std_logic]
Dbg_WDATA_28 => Dbg_WDATA_28, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_28 => Dbg_WVALID_28, -- [out std_logic]
Dbg_WREADY_28 => Dbg_WREADY_28, -- [in std_logic]
Dbg_BRESP_28 => Dbg_BRESP_28, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_28 => Dbg_BVALID_28, -- [in std_logic]
Dbg_BREADY_28 => Dbg_BREADY_28, -- [out std_logic]
Dbg_ARADDR_28 => Dbg_ARADDR_28, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_28 => Dbg_ARVALID_28, -- [out std_logic]
Dbg_ARREADY_28 => Dbg_ARREADY_28, -- [in std_logic]
Dbg_RDATA_28 => Dbg_RDATA_28, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_28 => Dbg_RRESP_28, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_28 => Dbg_RVALID_28, -- [in std_logic]
Dbg_RREADY_28 => Dbg_RREADY_28, -- [out std_logic]
Dbg_Disable_29 => Dbg_Disable_29, -- [out std_logic]
Dbg_Clk_29 => Dbg_Clk_29, -- [out std_logic]
Dbg_TDI_29 => Dbg_TDI_29, -- [out std_logic]
Dbg_TDO_29 => Dbg_TDO_29, -- [in std_logic]
Dbg_Reg_En_29 => Dbg_Reg_En_29, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_29 => Dbg_Capture_29, -- [out std_logic]
Dbg_Shift_29 => Dbg_Shift_29, -- [out std_logic]
Dbg_Update_29 => Dbg_Update_29, -- [out std_logic]
Dbg_Rst_29 => Dbg_Rst_29, -- [out std_logic]
Dbg_Trig_In_29 => Dbg_Trig_In_29, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_29 => Dbg_Trig_Ack_In_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_29 => Dbg_Trig_Out_29, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_29 => Dbg_Trig_Ack_Out_29, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_29 => Dbg_TrClk_29, -- [out std_logic]
Dbg_TrData_29 => Dbg_TrData_29, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_29 => Dbg_TrReady_29, -- [out std_logic]
Dbg_TrValid_29 => Dbg_TrValid_29, -- [in std_logic]
Dbg_AWADDR_29 => Dbg_AWADDR_29, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_29 => Dbg_AWVALID_29, -- [out std_logic]
Dbg_AWREADY_29 => Dbg_AWREADY_29, -- [in std_logic]
Dbg_WDATA_29 => Dbg_WDATA_29, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_29 => Dbg_WVALID_29, -- [out std_logic]
Dbg_WREADY_29 => Dbg_WREADY_29, -- [in std_logic]
Dbg_BRESP_29 => Dbg_BRESP_29, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_29 => Dbg_BVALID_29, -- [in std_logic]
Dbg_BREADY_29 => Dbg_BREADY_29, -- [out std_logic]
Dbg_ARADDR_29 => Dbg_ARADDR_29, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_29 => Dbg_ARVALID_29, -- [out std_logic]
Dbg_ARREADY_29 => Dbg_ARREADY_29, -- [in std_logic]
Dbg_RDATA_29 => Dbg_RDATA_29, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_29 => Dbg_RRESP_29, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_29 => Dbg_RVALID_29, -- [in std_logic]
Dbg_RREADY_29 => Dbg_RREADY_29, -- [out std_logic]
Dbg_Disable_30 => Dbg_Disable_30, -- [out std_logic]
Dbg_Clk_30 => Dbg_Clk_30, -- [out std_logic]
Dbg_TDI_30 => Dbg_TDI_30, -- [out std_logic]
Dbg_TDO_30 => Dbg_TDO_30, -- [in std_logic]
Dbg_Reg_En_30 => Dbg_Reg_En_30, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_30 => Dbg_Capture_30, -- [out std_logic]
Dbg_Shift_30 => Dbg_Shift_30, -- [out std_logic]
Dbg_Update_30 => Dbg_Update_30, -- [out std_logic]
Dbg_Rst_30 => Dbg_Rst_30, -- [out std_logic]
Dbg_Trig_In_30 => Dbg_Trig_In_30, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_30 => Dbg_Trig_Ack_In_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_30 => Dbg_Trig_Out_30, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_30 => Dbg_Trig_Ack_Out_30, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_30 => Dbg_TrClk_30, -- [out std_logic]
Dbg_TrData_30 => Dbg_TrData_30, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_30 => Dbg_TrReady_30, -- [out std_logic]
Dbg_TrValid_30 => Dbg_TrValid_30, -- [in std_logic]
Dbg_AWADDR_30 => Dbg_AWADDR_30, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_30 => Dbg_AWVALID_30, -- [out std_logic]
Dbg_AWREADY_30 => Dbg_AWREADY_30, -- [in std_logic]
Dbg_WDATA_30 => Dbg_WDATA_30, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_30 => Dbg_WVALID_30, -- [out std_logic]
Dbg_WREADY_30 => Dbg_WREADY_30, -- [in std_logic]
Dbg_BRESP_30 => Dbg_BRESP_30, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_30 => Dbg_BVALID_30, -- [in std_logic]
Dbg_BREADY_30 => Dbg_BREADY_30, -- [out std_logic]
Dbg_ARADDR_30 => Dbg_ARADDR_30, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_30 => Dbg_ARVALID_30, -- [out std_logic]
Dbg_ARREADY_30 => Dbg_ARREADY_30, -- [in std_logic]
Dbg_RDATA_30 => Dbg_RDATA_30, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_30 => Dbg_RRESP_30, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_30 => Dbg_RVALID_30, -- [in std_logic]
Dbg_RREADY_30 => Dbg_RREADY_30, -- [out std_logic]
Dbg_Disable_31 => Dbg_Disable_31, -- [out std_logic]
Dbg_Clk_31 => Dbg_Clk_31, -- [out std_logic]
Dbg_TDI_31 => Dbg_TDI_31, -- [out std_logic]
Dbg_TDO_31 => Dbg_TDO_31, -- [in std_logic]
Dbg_Reg_En_31 => Dbg_Reg_En_31, -- [out std_logic_vector(0 to 7)]
Dbg_Capture_31 => Dbg_Capture_31, -- [out std_logic]
Dbg_Shift_31 => Dbg_Shift_31, -- [out std_logic]
Dbg_Update_31 => Dbg_Update_31, -- [out std_logic]
Dbg_Rst_31 => Dbg_Rst_31, -- [out std_logic]
Dbg_Trig_In_31 => Dbg_Trig_In_31, -- [in std_logic_vector(0 to 7)]
Dbg_Trig_Ack_In_31 => Dbg_Trig_Ack_In_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Out_31 => Dbg_Trig_Out_31, -- [out std_logic_vector(0 to 7)]
Dbg_Trig_Ack_Out_31 => Dbg_Trig_Ack_Out_31, -- [in std_logic_vector(0 to 7)]
Dbg_TrClk_31 => Dbg_TrClk_31, -- [out std_logic]
Dbg_TrData_31 => Dbg_TrData_31, -- [in std_logic_vector(0 to 35)]
Dbg_TrReady_31 => Dbg_TrReady_31, -- [out std_logic]
Dbg_TrValid_31 => Dbg_TrValid_31, -- [in std_logic]
Dbg_AWADDR_31 => Dbg_AWADDR_31, -- [out std_logic_vector(14 downto 2]
Dbg_AWVALID_31 => Dbg_AWVALID_31, -- [out std_logic]
Dbg_AWREADY_31 => Dbg_AWREADY_31, -- [in std_logic]
Dbg_WDATA_31 => Dbg_WDATA_31, -- [out std_logic_vector(31 downto 0)]
Dbg_WVALID_31 => Dbg_WVALID_31, -- [out std_logic]
Dbg_WREADY_31 => Dbg_WREADY_31, -- [in std_logic]
Dbg_BRESP_31 => Dbg_BRESP_31, -- [in std_logic_vector(1 downto 0)]
Dbg_BVALID_31 => Dbg_BVALID_31, -- [in std_logic]
Dbg_BREADY_31 => Dbg_BREADY_31, -- [out std_logic]
Dbg_ARADDR_31 => Dbg_ARADDR_31, -- [out std_logic_vector(14 downto 2)]
Dbg_ARVALID_31 => Dbg_ARVALID_31, -- [out std_logic]
Dbg_ARREADY_31 => Dbg_ARREADY_31, -- [in std_logic]
Dbg_RDATA_31 => Dbg_RDATA_31, -- [in std_logic_vector(31 downto 0)]
Dbg_RRESP_31 => Dbg_RRESP_31, -- [in std_logic_vector(1 downto 0)]
Dbg_RVALID_31 => Dbg_RVALID_31, -- [in std_logic]
Dbg_RREADY_31 => Dbg_RREADY_31, -- [out std_logic]
Ext_Trig_In => ext_trig_in, -- [in std_logic_vector(0 to 3)]
Ext_Trig_Ack_In => ext_trig_ack_in, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Out => ext_trig_out, -- [out std_logic_vector(0 to 3)]
Ext_Trig_Ack_Out => ext_trig_ack_out, -- [in std_logic_vector(0 to 3)]
Ext_JTAG_DRCK => Ext_JTAG_DRCK,
Ext_JTAG_RESET => Ext_JTAG_RESET,
Ext_JTAG_SEL => Ext_JTAG_SEL,
Ext_JTAG_CAPTURE => Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT => Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE => Ext_JTAG_UPDATE,
Ext_JTAG_TDI => Ext_JTAG_TDI,
Ext_JTAG_TDO => Ext_JTAG_TDO
);
ext_trig_in <= Trig_In_0 & Trig_In_1 & Trig_In_2 & Trig_In_3;
ext_trig_ack_out <= Trig_Ack_Out_0 & Trig_Ack_Out_1 & Trig_Ack_Out_2 & Trig_Ack_Out_3;
Trig_Ack_In_0 <= ext_trig_ack_in(0);
Trig_Ack_In_1 <= ext_trig_ack_in(1);
Trig_Ack_In_2 <= ext_trig_ack_in(2);
Trig_Ack_In_3 <= ext_trig_ack_in(3);
Trig_Out_0 <= ext_trig_out(0);
Trig_Out_1 <= ext_trig_out(1);
Trig_Out_2 <= ext_trig_out(2);
Trig_Out_3 <= ext_trig_out(3);
-- Bus Master port
Use_Bus_MASTER : if (C_DBG_MEM_ACCESS = 1) generate
type LMB_vec_type is array (natural range <>) of std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_addr : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_data_write : std_logic_vector(0 to C_DATA_SIZE - 1);
signal lmb_addr_strobe : std_logic;
signal lmb_read_strobe : std_logic;
signal lmb_write_strobe : std_logic;
signal lmb_ready : std_logic;
signal lmb_wait : std_logic;
signal lmb_ue : std_logic;
signal lmb_byte_enable : std_logic_vector(0 to C_DATA_SIZE / 8 - 1);
signal lmb_addr_strobe_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec : LMB_vec_type(0 to 31);
signal lmb_ready_vec : std_logic_vector(0 to 31);
signal lmb_wait_vec : std_logic_vector(0 to 31);
signal lmb_ue_vec : std_logic_vector(0 to 31);
signal lmb_data_read_vec_q : LMB_vec_type(0 to C_EN_WIDTH - 1);
signal lmb_ready_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_wait_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
signal lmb_ue_vec_q : std_logic_vector(0 to C_EN_WIDTH - 1);
begin
bus_master_I : bus_master
generic map (
C_TARGET => C_TARGET,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => true,
C_HAS_DIRECT_PORT => C_TRACE_AXI_MASTER
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => lmb_data_addr,
LMB_Data_Read => lmb_data_read,
LMB_Data_Write => lmb_data_write,
LMB_Addr_Strobe => lmb_addr_strobe,
LMB_Read_Strobe => lmb_read_strobe,
LMB_Write_Strobe => lmb_write_strobe,
LMB_Ready => lmb_ready,
LMB_Wait => lmb_wait,
LMB_UE => lmb_ue,
LMB_Byte_Enable => lmb_byte_enable,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
Generate_LMB_Outputs : process (mb_debug_enabled, lmb_addr_strobe)
begin -- process Generate_LMB_Outputs
lmb_addr_strobe_vec <= (others => '0');
for I in 0 to C_EN_WIDTH - 1 loop
lmb_addr_strobe_vec(I) <= lmb_addr_strobe and mb_debug_enabled(I);
end loop;
end process Generate_LMB_Outputs;
LMB_Addr_Strobe_0 <= lmb_addr_strobe_vec(0);
LMB_Addr_Strobe_1 <= lmb_addr_strobe_vec(1);
LMB_Addr_Strobe_2 <= lmb_addr_strobe_vec(2);
LMB_Addr_Strobe_3 <= lmb_addr_strobe_vec(3);
LMB_Addr_Strobe_4 <= lmb_addr_strobe_vec(4);
LMB_Addr_Strobe_5 <= lmb_addr_strobe_vec(5);
LMB_Addr_Strobe_6 <= lmb_addr_strobe_vec(6);
LMB_Addr_Strobe_7 <= lmb_addr_strobe_vec(7);
LMB_Addr_Strobe_8 <= lmb_addr_strobe_vec(8);
LMB_Addr_Strobe_9 <= lmb_addr_strobe_vec(9);
LMB_Addr_Strobe_10 <= lmb_addr_strobe_vec(10);
LMB_Addr_Strobe_11 <= lmb_addr_strobe_vec(11);
LMB_Addr_Strobe_12 <= lmb_addr_strobe_vec(12);
LMB_Addr_Strobe_13 <= lmb_addr_strobe_vec(13);
LMB_Addr_Strobe_14 <= lmb_addr_strobe_vec(14);
LMB_Addr_Strobe_15 <= lmb_addr_strobe_vec(15);
LMB_Addr_Strobe_16 <= lmb_addr_strobe_vec(16);
LMB_Addr_Strobe_17 <= lmb_addr_strobe_vec(17);
LMB_Addr_Strobe_18 <= lmb_addr_strobe_vec(18);
LMB_Addr_Strobe_19 <= lmb_addr_strobe_vec(19);
LMB_Addr_Strobe_20 <= lmb_addr_strobe_vec(20);
LMB_Addr_Strobe_21 <= lmb_addr_strobe_vec(21);
LMB_Addr_Strobe_22 <= lmb_addr_strobe_vec(22);
LMB_Addr_Strobe_23 <= lmb_addr_strobe_vec(23);
LMB_Addr_Strobe_24 <= lmb_addr_strobe_vec(24);
LMB_Addr_Strobe_25 <= lmb_addr_strobe_vec(25);
LMB_Addr_Strobe_26 <= lmb_addr_strobe_vec(26);
LMB_Addr_Strobe_27 <= lmb_addr_strobe_vec(27);
LMB_Addr_Strobe_28 <= lmb_addr_strobe_vec(28);
LMB_Addr_Strobe_29 <= lmb_addr_strobe_vec(29);
LMB_Addr_Strobe_30 <= lmb_addr_strobe_vec(30);
LMB_Addr_Strobe_31 <= lmb_addr_strobe_vec(31);
LMB_Data_Addr_0 <= lmb_data_addr;
LMB_Data_Addr_1 <= lmb_data_addr;
LMB_Data_Addr_2 <= lmb_data_addr;
LMB_Data_Addr_3 <= lmb_data_addr;
LMB_Data_Addr_4 <= lmb_data_addr;
LMB_Data_Addr_5 <= lmb_data_addr;
LMB_Data_Addr_6 <= lmb_data_addr;
LMB_Data_Addr_7 <= lmb_data_addr;
LMB_Data_Addr_8 <= lmb_data_addr;
LMB_Data_Addr_9 <= lmb_data_addr;
LMB_Data_Addr_10 <= lmb_data_addr;
LMB_Data_Addr_11 <= lmb_data_addr;
LMB_Data_Addr_12 <= lmb_data_addr;
LMB_Data_Addr_13 <= lmb_data_addr;
LMB_Data_Addr_14 <= lmb_data_addr;
LMB_Data_Addr_15 <= lmb_data_addr;
LMB_Data_Addr_16 <= lmb_data_addr;
LMB_Data_Addr_17 <= lmb_data_addr;
LMB_Data_Addr_18 <= lmb_data_addr;
LMB_Data_Addr_19 <= lmb_data_addr;
LMB_Data_Addr_20 <= lmb_data_addr;
LMB_Data_Addr_21 <= lmb_data_addr;
LMB_Data_Addr_22 <= lmb_data_addr;
LMB_Data_Addr_23 <= lmb_data_addr;
LMB_Data_Addr_24 <= lmb_data_addr;
LMB_Data_Addr_25 <= lmb_data_addr;
LMB_Data_Addr_26 <= lmb_data_addr;
LMB_Data_Addr_27 <= lmb_data_addr;
LMB_Data_Addr_28 <= lmb_data_addr;
LMB_Data_Addr_29 <= lmb_data_addr;
LMB_Data_Addr_30 <= lmb_data_addr;
LMB_Data_Addr_31 <= lmb_data_addr;
LMB_Data_write_0 <= lmb_data_write;
LMB_Data_write_1 <= lmb_data_write;
LMB_Data_write_2 <= lmb_data_write;
LMB_Data_write_3 <= lmb_data_write;
LMB_Data_write_4 <= lmb_data_write;
LMB_Data_write_5 <= lmb_data_write;
LMB_Data_write_6 <= lmb_data_write;
LMB_Data_write_7 <= lmb_data_write;
LMB_Data_write_8 <= lmb_data_write;
LMB_Data_write_9 <= lmb_data_write;
LMB_Data_write_10 <= lmb_data_write;
LMB_Data_write_11 <= lmb_data_write;
LMB_Data_write_12 <= lmb_data_write;
LMB_Data_write_13 <= lmb_data_write;
LMB_Data_write_14 <= lmb_data_write;
LMB_Data_write_15 <= lmb_data_write;
LMB_Data_write_16 <= lmb_data_write;
LMB_Data_write_17 <= lmb_data_write;
LMB_Data_write_18 <= lmb_data_write;
LMB_Data_write_19 <= lmb_data_write;
LMB_Data_write_20 <= lmb_data_write;
LMB_Data_write_21 <= lmb_data_write;
LMB_Data_write_22 <= lmb_data_write;
LMB_Data_write_23 <= lmb_data_write;
LMB_Data_write_24 <= lmb_data_write;
LMB_Data_write_25 <= lmb_data_write;
LMB_Data_write_26 <= lmb_data_write;
LMB_Data_write_27 <= lmb_data_write;
LMB_Data_write_28 <= lmb_data_write;
LMB_Data_write_29 <= lmb_data_write;
LMB_Data_write_30 <= lmb_data_write;
LMB_Data_write_31 <= lmb_data_write;
LMB_Read_strobe_0 <= lmb_read_strobe;
LMB_Read_strobe_1 <= lmb_read_strobe;
LMB_Read_strobe_2 <= lmb_read_strobe;
LMB_Read_strobe_3 <= lmb_read_strobe;
LMB_Read_strobe_4 <= lmb_read_strobe;
LMB_Read_strobe_5 <= lmb_read_strobe;
LMB_Read_strobe_6 <= lmb_read_strobe;
LMB_Read_strobe_7 <= lmb_read_strobe;
LMB_Read_strobe_8 <= lmb_read_strobe;
LMB_Read_strobe_9 <= lmb_read_strobe;
LMB_Read_strobe_10 <= lmb_read_strobe;
LMB_Read_strobe_11 <= lmb_read_strobe;
LMB_Read_strobe_12 <= lmb_read_strobe;
LMB_Read_strobe_13 <= lmb_read_strobe;
LMB_Read_strobe_14 <= lmb_read_strobe;
LMB_Read_strobe_15 <= lmb_read_strobe;
LMB_Read_strobe_16 <= lmb_read_strobe;
LMB_Read_strobe_17 <= lmb_read_strobe;
LMB_Read_strobe_18 <= lmb_read_strobe;
LMB_Read_strobe_19 <= lmb_read_strobe;
LMB_Read_strobe_20 <= lmb_read_strobe;
LMB_Read_strobe_21 <= lmb_read_strobe;
LMB_Read_strobe_22 <= lmb_read_strobe;
LMB_Read_strobe_23 <= lmb_read_strobe;
LMB_Read_strobe_24 <= lmb_read_strobe;
LMB_Read_strobe_25 <= lmb_read_strobe;
LMB_Read_strobe_26 <= lmb_read_strobe;
LMB_Read_strobe_27 <= lmb_read_strobe;
LMB_Read_strobe_28 <= lmb_read_strobe;
LMB_Read_strobe_29 <= lmb_read_strobe;
LMB_Read_strobe_30 <= lmb_read_strobe;
LMB_Read_strobe_31 <= lmb_read_strobe;
LMB_Write_strobe_0 <= lmb_write_strobe;
LMB_Write_strobe_1 <= lmb_write_strobe;
LMB_Write_strobe_2 <= lmb_write_strobe;
LMB_Write_strobe_3 <= lmb_write_strobe;
LMB_Write_strobe_4 <= lmb_write_strobe;
LMB_Write_strobe_5 <= lmb_write_strobe;
LMB_Write_strobe_6 <= lmb_write_strobe;
LMB_Write_strobe_7 <= lmb_write_strobe;
LMB_Write_strobe_8 <= lmb_write_strobe;
LMB_Write_strobe_9 <= lmb_write_strobe;
LMB_Write_strobe_10 <= lmb_write_strobe;
LMB_Write_strobe_11 <= lmb_write_strobe;
LMB_Write_strobe_12 <= lmb_write_strobe;
LMB_Write_strobe_13 <= lmb_write_strobe;
LMB_Write_strobe_14 <= lmb_write_strobe;
LMB_Write_strobe_15 <= lmb_write_strobe;
LMB_Write_strobe_16 <= lmb_write_strobe;
LMB_Write_strobe_17 <= lmb_write_strobe;
LMB_Write_strobe_18 <= lmb_write_strobe;
LMB_Write_strobe_19 <= lmb_write_strobe;
LMB_Write_strobe_20 <= lmb_write_strobe;
LMB_Write_strobe_21 <= lmb_write_strobe;
LMB_Write_strobe_22 <= lmb_write_strobe;
LMB_Write_strobe_23 <= lmb_write_strobe;
LMB_Write_strobe_24 <= lmb_write_strobe;
LMB_Write_strobe_25 <= lmb_write_strobe;
LMB_Write_strobe_26 <= lmb_write_strobe;
LMB_Write_strobe_27 <= lmb_write_strobe;
LMB_Write_strobe_28 <= lmb_write_strobe;
LMB_Write_strobe_29 <= lmb_write_strobe;
LMB_Write_strobe_30 <= lmb_write_strobe;
LMB_Write_strobe_31 <= lmb_write_strobe;
LMB_Byte_enable_0 <= lmb_byte_enable;
LMB_Byte_enable_1 <= lmb_byte_enable;
LMB_Byte_enable_2 <= lmb_byte_enable;
LMB_Byte_enable_3 <= lmb_byte_enable;
LMB_Byte_enable_4 <= lmb_byte_enable;
LMB_Byte_enable_5 <= lmb_byte_enable;
LMB_Byte_enable_6 <= lmb_byte_enable;
LMB_Byte_enable_7 <= lmb_byte_enable;
LMB_Byte_enable_8 <= lmb_byte_enable;
LMB_Byte_enable_9 <= lmb_byte_enable;
LMB_Byte_enable_10 <= lmb_byte_enable;
LMB_Byte_enable_11 <= lmb_byte_enable;
LMB_Byte_enable_12 <= lmb_byte_enable;
LMB_Byte_enable_13 <= lmb_byte_enable;
LMB_Byte_enable_14 <= lmb_byte_enable;
LMB_Byte_enable_15 <= lmb_byte_enable;
LMB_Byte_enable_16 <= lmb_byte_enable;
LMB_Byte_enable_17 <= lmb_byte_enable;
LMB_Byte_enable_18 <= lmb_byte_enable;
LMB_Byte_enable_19 <= lmb_byte_enable;
LMB_Byte_enable_20 <= lmb_byte_enable;
LMB_Byte_enable_21 <= lmb_byte_enable;
LMB_Byte_enable_22 <= lmb_byte_enable;
LMB_Byte_enable_23 <= lmb_byte_enable;
LMB_Byte_enable_24 <= lmb_byte_enable;
LMB_Byte_enable_25 <= lmb_byte_enable;
LMB_Byte_enable_26 <= lmb_byte_enable;
LMB_Byte_enable_27 <= lmb_byte_enable;
LMB_Byte_enable_28 <= lmb_byte_enable;
LMB_Byte_enable_29 <= lmb_byte_enable;
LMB_Byte_enable_30 <= lmb_byte_enable;
LMB_Byte_enable_31 <= lmb_byte_enable;
Generate_LMB_Inputs : process (mb_debug_enabled, lmb_data_read_vec_q, lmb_ready_vec_q, lmb_wait_vec_q, lmb_ue_vec_q)
variable data_mask : std_logic_vector(0 to C_DATA_SIZE - 1);
variable data_read : std_logic_vector(0 to C_DATA_SIZE - 1);
variable ready : std_logic;
variable wait_i : std_logic;
variable ue : std_logic;
begin -- process Generate_LMB_Inputs
data_read := (others => '0');
ready := '0';
wait_i := '0';
ue := '0';
for I in 0 to C_EN_WIDTH - 1 loop
data_mask := (0 to C_DATA_SIZE - 1 => mb_debug_enabled(I));
data_read := data_read or (lmb_data_read_vec_q(I) and data_mask);
ready := ready or (lmb_ready_vec_q(I) and mb_debug_enabled(I));
wait_i := wait_i or (lmb_wait_vec_q(I) and mb_debug_enabled(I));
ue := ue or (lmb_ue_vec_q(I) and mb_debug_enabled(I));
end loop;
lmb_data_read <= data_read;
lmb_ready <= ready;
lmb_wait <= wait_i;
lmb_ue <= ue;
end process Generate_LMB_Inputs;
Clock_LMB_Inputs : process (M_AXI_ACLK)
begin
if M_AXI_ACLK'event and M_AXI_ACLK = '1' then -- rising clock edge
for I in 0 to C_EN_WIDTH - 1 loop
lmb_data_read_vec_q(I) <= lmb_data_read_vec(I);
lmb_ready_vec_q(I) <= lmb_ready_vec(I);
lmb_wait_vec_q(I) <= lmb_wait_vec(I);
lmb_ue_vec_q(I) <= lmb_ue_vec(I);
end loop;
end if;
end process Clock_LMB_Inputs;
lmb_data_read_vec(0) <= LMB_Data_Read_0;
lmb_data_read_vec(1) <= LMB_Data_Read_1;
lmb_data_read_vec(2) <= LMB_Data_Read_2;
lmb_data_read_vec(3) <= LMB_Data_Read_3;
lmb_data_read_vec(4) <= LMB_Data_Read_4;
lmb_data_read_vec(5) <= LMB_Data_Read_5;
lmb_data_read_vec(6) <= LMB_Data_Read_6;
lmb_data_read_vec(7) <= LMB_Data_Read_7;
lmb_data_read_vec(8) <= LMB_Data_Read_8;
lmb_data_read_vec(9) <= LMB_Data_Read_9;
lmb_data_read_vec(10) <= LMB_Data_Read_10;
lmb_data_read_vec(11) <= LMB_Data_Read_11;
lmb_data_read_vec(12) <= LMB_Data_Read_12;
lmb_data_read_vec(13) <= LMB_Data_Read_13;
lmb_data_read_vec(14) <= LMB_Data_Read_14;
lmb_data_read_vec(15) <= LMB_Data_Read_15;
lmb_data_read_vec(16) <= LMB_Data_Read_16;
lmb_data_read_vec(17) <= LMB_Data_Read_17;
lmb_data_read_vec(18) <= LMB_Data_Read_18;
lmb_data_read_vec(19) <= LMB_Data_Read_19;
lmb_data_read_vec(20) <= LMB_Data_Read_20;
lmb_data_read_vec(21) <= LMB_Data_Read_21;
lmb_data_read_vec(22) <= LMB_Data_Read_22;
lmb_data_read_vec(23) <= LMB_Data_Read_23;
lmb_data_read_vec(24) <= LMB_Data_Read_24;
lmb_data_read_vec(25) <= LMB_Data_Read_25;
lmb_data_read_vec(26) <= LMB_Data_Read_26;
lmb_data_read_vec(27) <= LMB_Data_Read_27;
lmb_data_read_vec(28) <= LMB_Data_Read_28;
lmb_data_read_vec(29) <= LMB_Data_Read_29;
lmb_data_read_vec(30) <= LMB_Data_Read_30;
lmb_data_read_vec(31) <= LMB_Data_Read_31;
lmb_ready_vec(0) <= LMB_Ready_0;
lmb_ready_vec(1) <= LMB_Ready_1;
lmb_ready_vec(2) <= LMB_Ready_2;
lmb_ready_vec(3) <= LMB_Ready_3;
lmb_ready_vec(4) <= LMB_Ready_4;
lmb_ready_vec(5) <= LMB_Ready_5;
lmb_ready_vec(6) <= LMB_Ready_6;
lmb_ready_vec(7) <= LMB_Ready_7;
lmb_ready_vec(8) <= LMB_Ready_8;
lmb_ready_vec(9) <= LMB_Ready_9;
lmb_ready_vec(10) <= LMB_Ready_10;
lmb_ready_vec(11) <= LMB_Ready_11;
lmb_ready_vec(12) <= LMB_Ready_12;
lmb_ready_vec(13) <= LMB_Ready_13;
lmb_ready_vec(14) <= LMB_Ready_14;
lmb_ready_vec(15) <= LMB_Ready_15;
lmb_ready_vec(16) <= LMB_Ready_16;
lmb_ready_vec(17) <= LMB_Ready_17;
lmb_ready_vec(18) <= LMB_Ready_18;
lmb_ready_vec(19) <= LMB_Ready_19;
lmb_ready_vec(20) <= LMB_Ready_20;
lmb_ready_vec(21) <= LMB_Ready_21;
lmb_ready_vec(22) <= LMB_Ready_22;
lmb_ready_vec(23) <= LMB_Ready_23;
lmb_ready_vec(24) <= LMB_Ready_24;
lmb_ready_vec(25) <= LMB_Ready_25;
lmb_ready_vec(26) <= LMB_Ready_26;
lmb_ready_vec(27) <= LMB_Ready_27;
lmb_ready_vec(28) <= LMB_Ready_28;
lmb_ready_vec(29) <= LMB_Ready_29;
lmb_ready_vec(30) <= LMB_Ready_30;
lmb_ready_vec(31) <= LMB_Ready_31;
lmb_wait_vec(0) <= LMB_Wait_0;
lmb_wait_vec(1) <= LMB_Wait_1;
lmb_wait_vec(2) <= LMB_Wait_2;
lmb_wait_vec(3) <= LMB_Wait_3;
lmb_wait_vec(4) <= LMB_Wait_4;
lmb_wait_vec(5) <= LMB_Wait_5;
lmb_wait_vec(6) <= LMB_Wait_6;
lmb_wait_vec(7) <= LMB_Wait_7;
lmb_wait_vec(8) <= LMB_Wait_8;
lmb_wait_vec(9) <= LMB_Wait_9;
lmb_wait_vec(10) <= LMB_Wait_10;
lmb_wait_vec(11) <= LMB_Wait_11;
lmb_wait_vec(12) <= LMB_Wait_12;
lmb_wait_vec(13) <= LMB_Wait_13;
lmb_wait_vec(14) <= LMB_Wait_14;
lmb_wait_vec(15) <= LMB_Wait_15;
lmb_wait_vec(16) <= LMB_Wait_16;
lmb_wait_vec(17) <= LMB_Wait_17;
lmb_wait_vec(18) <= LMB_Wait_18;
lmb_wait_vec(19) <= LMB_Wait_19;
lmb_wait_vec(20) <= LMB_Wait_20;
lmb_wait_vec(21) <= LMB_Wait_21;
lmb_wait_vec(22) <= LMB_Wait_22;
lmb_wait_vec(23) <= LMB_Wait_23;
lmb_wait_vec(24) <= LMB_Wait_24;
lmb_wait_vec(25) <= LMB_Wait_25;
lmb_wait_vec(26) <= LMB_Wait_26;
lmb_wait_vec(27) <= LMB_Wait_27;
lmb_wait_vec(28) <= LMB_Wait_28;
lmb_wait_vec(29) <= LMB_Wait_29;
lmb_wait_vec(30) <= LMB_Wait_30;
lmb_wait_vec(31) <= LMB_Wait_31;
lmb_ue_vec(0) <= LMB_UE_0;
lmb_ue_vec(1) <= LMB_UE_1;
lmb_ue_vec(2) <= LMB_UE_2;
lmb_ue_vec(3) <= LMB_UE_3;
lmb_ue_vec(4) <= LMB_UE_4;
lmb_ue_vec(5) <= LMB_UE_5;
lmb_ue_vec(6) <= LMB_UE_6;
lmb_ue_vec(7) <= LMB_UE_7;
lmb_ue_vec(8) <= LMB_UE_8;
lmb_ue_vec(9) <= LMB_UE_9;
lmb_ue_vec(10) <= LMB_UE_10;
lmb_ue_vec(11) <= LMB_UE_11;
lmb_ue_vec(12) <= LMB_UE_12;
lmb_ue_vec(13) <= LMB_UE_13;
lmb_ue_vec(14) <= LMB_UE_14;
lmb_ue_vec(15) <= LMB_UE_15;
lmb_ue_vec(16) <= LMB_UE_16;
lmb_ue_vec(17) <= LMB_UE_17;
lmb_ue_vec(18) <= LMB_UE_18;
lmb_ue_vec(19) <= LMB_UE_19;
lmb_ue_vec(20) <= LMB_UE_20;
lmb_ue_vec(21) <= LMB_UE_21;
lmb_ue_vec(22) <= LMB_UE_22;
lmb_ue_vec(23) <= LMB_UE_23;
lmb_ue_vec(24) <= LMB_UE_24;
lmb_ue_vec(25) <= LMB_UE_25;
lmb_ue_vec(26) <= LMB_UE_26;
lmb_ue_vec(27) <= LMB_UE_27;
lmb_ue_vec(28) <= LMB_UE_28;
lmb_ue_vec(29) <= LMB_UE_29;
lmb_ue_vec(30) <= LMB_UE_30;
lmb_ue_vec(31) <= LMB_UE_31;
end generate Use_Bus_MASTER;
Use_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and C_TRACE_AXI_MASTER) generate
begin
bus_master_I : bus_master
generic map (
C_TARGET => C_TARGET,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_THREAD_ID_WIDTH => C_M_AXI_THREAD_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_DATA_SIZE => C_DATA_SIZE,
C_HAS_FIFO_PORTS => false,
C_HAS_DIRECT_PORT => true
)
port map (
Rd_Start => master_rd_start,
Rd_Addr => master_rd_addr,
Rd_Len => master_rd_len,
Rd_Size => master_rd_size,
Rd_Exclusive => master_rd_excl,
Rd_Idle => master_rd_idle,
Rd_Response => master_rd_resp,
Wr_Start => master_wr_start,
Wr_Addr => master_wr_addr,
Wr_Len => master_wr_len,
Wr_Size => master_wr_size,
Wr_Exclusive => master_wr_excl,
Wr_Idle => master_wr_idle,
Wr_Response => master_wr_resp,
Data_Rd => master_data_rd,
Data_Out => master_data_out,
Data_Exists => master_data_exists,
Data_Wr => master_data_wr,
Data_In => master_data_in,
Data_Empty => master_data_empty,
Direct_Wr_Addr => master_dwr_addr,
Direct_Wr_Len => master_dwr_len,
Direct_Wr_Data => master_dwr_data,
Direct_Wr_Start => master_dwr_start,
Direct_Wr_Next => master_dwr_next,
Direct_Wr_Done => master_dwr_done,
Direct_Wr_Resp => master_dwr_resp,
LMB_Data_Addr => open,
LMB_Data_Read => (others => '0'),
LMB_Data_Write => open,
LMB_Addr_Strobe => open,
LMB_Read_Strobe => open,
LMB_Write_Strobe => open,
LMB_Ready => '0',
LMB_Wait => '0',
LMB_UE => '0',
LMB_Byte_Enable => open,
M_AXI_ACLK => M_AXI_ACLK,
M_AXI_ARESETn => M_AXI_ARESETn,
M_AXI_AWID => M_AXI_AWID,
M_AXI_AWADDR => M_AXI_AWADDR,
M_AXI_AWLEN => M_AXI_AWLEN,
M_AXI_AWSIZE => M_AXI_AWSIZE,
M_AXI_AWBURST => M_AXI_AWBURST,
M_AXI_AWLOCK => M_AXI_AWLOCK,
M_AXI_AWCACHE => M_AXI_AWCACHE,
M_AXI_AWPROT => M_AXI_AWPROT,
M_AXI_AWQOS => M_AXI_AWQOS,
M_AXI_AWVALID => M_AXI_AWVALID,
M_AXI_AWREADY => M_AXI_AWREADY,
M_AXI_WLAST => M_AXI_WLAST,
M_AXI_WDATA => M_AXI_WDATA,
M_AXI_WSTRB => M_AXI_WSTRB,
M_AXI_WVALID => M_AXI_WVALID,
M_AXI_WREADY => M_AXI_WREADY,
M_AXI_BRESP => M_AXI_BRESP,
M_AXI_BID => M_AXI_BID,
M_AXI_BVALID => M_AXI_BVALID,
M_AXI_BREADY => M_AXI_BREADY,
M_AXI_ARADDR => M_AXI_ARADDR,
M_AXI_ARID => M_AXI_ARID,
M_AXI_ARLEN => M_AXI_ARLEN,
M_AXI_ARSIZE => M_AXI_ARSIZE,
M_AXI_ARBURST => M_AXI_ARBURST,
M_AXI_ARLOCK => M_AXI_ARLOCK,
M_AXI_ARCACHE => M_AXI_ARCACHE,
M_AXI_ARPROT => M_AXI_ARPROT,
M_AXI_ARQOS => M_AXI_ARQOS,
M_AXI_ARVALID => M_AXI_ARVALID,
M_AXI_ARREADY => M_AXI_ARREADY,
M_AXI_RLAST => M_AXI_RLAST,
M_AXI_RID => M_AXI_RID,
M_AXI_RDATA => M_AXI_RDATA,
M_AXI_RRESP => M_AXI_RRESP,
M_AXI_RVALID => M_AXI_RVALID,
M_AXI_RREADY => M_AXI_RREADY
);
end generate Use_Bus_MASTER_AXI;
No_Bus_MASTER_AXI : if (C_DBG_MEM_ACCESS = 0 and not C_TRACE_AXI_MASTER) generate
begin
master_rd_idle <= '1';
master_rd_resp <= "00";
master_wr_idle <= '1';
master_wr_resp <= "00";
master_data_out <= (others => '0');
master_data_exists <= '0';
master_data_empty <= '1';
master_dwr_next <= '0';
master_dwr_done <= '0';
master_dwr_resp <= (others => '0');
M_AXI_AWID <= (others => '0');
M_AXI_AWADDR <= (others => '0');
M_AXI_AWLEN <= (others => '0');
M_AXI_AWSIZE <= (others => '0');
M_AXI_AWBURST <= (others => '0');
M_AXI_AWLOCK <= '0';
M_AXI_AWCACHE <= (others => '0');
M_AXI_AWPROT <= (others => '0');
M_AXI_AWQOS <= (others => '0');
M_AXI_AWVALID <= '0';
M_AXI_WDATA <= (others => '0');
M_AXI_WSTRB <= (others => '0');
M_AXI_WLAST <= '0';
M_AXI_WVALID <= '0';
M_AXI_BREADY <= '0';
M_AXI_ARID <= (others => '0');
M_AXI_ARADDR <= (others => '0');
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= (others => '0');
M_AXI_ARBURST <= (others => '0');
M_AXI_ARLOCK <= '0';
M_AXI_ARCACHE <= (others => '0');
M_AXI_ARPROT <= (others => '0');
M_AXI_ARQOS <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end generate No_Bus_MASTER_AXI;
No_Bus_MASTER_LMB : if (C_DBG_MEM_ACCESS = 0) generate
begin
LMB_Data_Addr_0 <= (others => '0');
LMB_Data_Write_0 <= (others => '0');
LMB_Addr_Strobe_0 <= '0';
LMB_Read_Strobe_0 <= '0';
LMB_Write_Strobe_0 <= '0';
LMB_Byte_Enable_0 <= (others => '0');
LMB_Data_Addr_1 <= (others => '0');
LMB_Data_Write_1 <= (others => '0');
LMB_Addr_Strobe_1 <= '0';
LMB_Read_Strobe_1 <= '0';
LMB_Write_Strobe_1 <= '0';
LMB_Byte_Enable_1 <= (others => '0');
LMB_Data_Addr_2 <= (others => '0');
LMB_Data_Write_2 <= (others => '0');
LMB_Addr_Strobe_2 <= '0';
LMB_Read_Strobe_2 <= '0';
LMB_Write_Strobe_2 <= '0';
LMB_Byte_Enable_2 <= (others => '0');
LMB_Data_Addr_3 <= (others => '0');
LMB_Data_Write_3 <= (others => '0');
LMB_Addr_Strobe_3 <= '0';
LMB_Read_Strobe_3 <= '0';
LMB_Write_Strobe_3 <= '0';
LMB_Byte_Enable_3 <= (others => '0');
LMB_Data_Addr_4 <= (others => '0');
LMB_Data_Write_4 <= (others => '0');
LMB_Addr_Strobe_4 <= '0';
LMB_Read_Strobe_4 <= '0';
LMB_Write_Strobe_4 <= '0';
LMB_Byte_Enable_4 <= (others => '0');
LMB_Data_Addr_5 <= (others => '0');
LMB_Data_Write_5 <= (others => '0');
LMB_Addr_Strobe_5 <= '0';
LMB_Read_Strobe_5 <= '0';
LMB_Write_Strobe_5 <= '0';
LMB_Byte_Enable_5 <= (others => '0');
LMB_Data_Addr_6 <= (others => '0');
LMB_Data_Write_6 <= (others => '0');
LMB_Addr_Strobe_6 <= '0';
LMB_Read_Strobe_6 <= '0';
LMB_Write_Strobe_6 <= '0';
LMB_Byte_Enable_6 <= (others => '0');
LMB_Data_Addr_7 <= (others => '0');
LMB_Data_Write_7 <= (others => '0');
LMB_Addr_Strobe_7 <= '0';
LMB_Read_Strobe_7 <= '0';
LMB_Write_Strobe_7 <= '0';
LMB_Byte_Enable_7 <= (others => '0');
LMB_Data_Addr_8 <= (others => '0');
LMB_Data_Write_8 <= (others => '0');
LMB_Addr_Strobe_8 <= '0';
LMB_Read_Strobe_8 <= '0';
LMB_Write_Strobe_8 <= '0';
LMB_Byte_Enable_8 <= (others => '0');
LMB_Data_Addr_9 <= (others => '0');
LMB_Data_Write_9 <= (others => '0');
LMB_Addr_Strobe_9 <= '0';
LMB_Read_Strobe_9 <= '0';
LMB_Write_Strobe_9 <= '0';
LMB_Byte_Enable_9 <= (others => '0');
LMB_Data_Addr_10 <= (others => '0');
LMB_Data_Write_10 <= (others => '0');
LMB_Addr_Strobe_10 <= '0';
LMB_Read_Strobe_10 <= '0';
LMB_Write_Strobe_10 <= '0';
LMB_Byte_Enable_10 <= (others => '0');
LMB_Data_Addr_11 <= (others => '0');
LMB_Data_Write_11 <= (others => '0');
LMB_Addr_Strobe_11 <= '0';
LMB_Read_Strobe_11 <= '0';
LMB_Write_Strobe_11 <= '0';
LMB_Byte_Enable_11 <= (others => '0');
LMB_Data_Addr_12 <= (others => '0');
LMB_Data_Write_12 <= (others => '0');
LMB_Addr_Strobe_12 <= '0';
LMB_Read_Strobe_12 <= '0';
LMB_Write_Strobe_12 <= '0';
LMB_Byte_Enable_12 <= (others => '0');
LMB_Data_Addr_13 <= (others => '0');
LMB_Data_Write_13 <= (others => '0');
LMB_Addr_Strobe_13 <= '0';
LMB_Read_Strobe_13 <= '0';
LMB_Write_Strobe_13 <= '0';
LMB_Byte_Enable_13 <= (others => '0');
LMB_Data_Addr_14 <= (others => '0');
LMB_Data_Write_14 <= (others => '0');
LMB_Addr_Strobe_14 <= '0';
LMB_Read_Strobe_14 <= '0';
LMB_Write_Strobe_14 <= '0';
LMB_Byte_Enable_14 <= (others => '0');
LMB_Data_Addr_15 <= (others => '0');
LMB_Data_Write_15 <= (others => '0');
LMB_Addr_Strobe_15 <= '0';
LMB_Read_Strobe_15 <= '0';
LMB_Write_Strobe_15 <= '0';
LMB_Byte_Enable_15 <= (others => '0');
LMB_Data_Addr_16 <= (others => '0');
LMB_Data_Write_16 <= (others => '0');
LMB_Addr_Strobe_16 <= '0';
LMB_Read_Strobe_16 <= '0';
LMB_Write_Strobe_16 <= '0';
LMB_Byte_Enable_16 <= (others => '0');
LMB_Data_Addr_17 <= (others => '0');
LMB_Data_Write_17 <= (others => '0');
LMB_Addr_Strobe_17 <= '0';
LMB_Read_Strobe_17 <= '0';
LMB_Write_Strobe_17 <= '0';
LMB_Byte_Enable_17 <= (others => '0');
LMB_Data_Addr_18 <= (others => '0');
LMB_Data_Write_18 <= (others => '0');
LMB_Addr_Strobe_18 <= '0';
LMB_Read_Strobe_18 <= '0';
LMB_Write_Strobe_18 <= '0';
LMB_Byte_Enable_18 <= (others => '0');
LMB_Data_Addr_19 <= (others => '0');
LMB_Data_Write_19 <= (others => '0');
LMB_Addr_Strobe_19 <= '0';
LMB_Read_Strobe_19 <= '0';
LMB_Write_Strobe_19 <= '0';
LMB_Byte_Enable_19 <= (others => '0');
LMB_Data_Addr_20 <= (others => '0');
LMB_Data_Write_20 <= (others => '0');
LMB_Addr_Strobe_20 <= '0';
LMB_Read_Strobe_20 <= '0';
LMB_Write_Strobe_20 <= '0';
LMB_Byte_Enable_20 <= (others => '0');
LMB_Data_Addr_21 <= (others => '0');
LMB_Data_Write_21 <= (others => '0');
LMB_Addr_Strobe_21 <= '0';
LMB_Read_Strobe_21 <= '0';
LMB_Write_Strobe_21 <= '0';
LMB_Byte_Enable_21 <= (others => '0');
LMB_Data_Addr_22 <= (others => '0');
LMB_Data_Write_22 <= (others => '0');
LMB_Addr_Strobe_22 <= '0';
LMB_Read_Strobe_22 <= '0';
LMB_Write_Strobe_22 <= '0';
LMB_Byte_Enable_22 <= (others => '0');
LMB_Data_Addr_23 <= (others => '0');
LMB_Data_Write_23 <= (others => '0');
LMB_Addr_Strobe_23 <= '0';
LMB_Read_Strobe_23 <= '0';
LMB_Write_Strobe_23 <= '0';
LMB_Byte_Enable_23 <= (others => '0');
LMB_Data_Addr_24 <= (others => '0');
LMB_Data_Write_24 <= (others => '0');
LMB_Addr_Strobe_24 <= '0';
LMB_Read_Strobe_24 <= '0';
LMB_Write_Strobe_24 <= '0';
LMB_Byte_Enable_24 <= (others => '0');
LMB_Data_Addr_25 <= (others => '0');
LMB_Data_Write_25 <= (others => '0');
LMB_Addr_Strobe_25 <= '0';
LMB_Read_Strobe_25 <= '0';
LMB_Write_Strobe_25 <= '0';
LMB_Byte_Enable_25 <= (others => '0');
LMB_Data_Addr_26 <= (others => '0');
LMB_Data_Write_26 <= (others => '0');
LMB_Addr_Strobe_26 <= '0';
LMB_Read_Strobe_26 <= '0';
LMB_Write_Strobe_26 <= '0';
LMB_Byte_Enable_26 <= (others => '0');
LMB_Data_Addr_27 <= (others => '0');
LMB_Data_Write_27 <= (others => '0');
LMB_Addr_Strobe_27 <= '0';
LMB_Read_Strobe_27 <= '0';
LMB_Write_Strobe_27 <= '0';
LMB_Byte_Enable_27 <= (others => '0');
LMB_Data_Addr_28 <= (others => '0');
LMB_Data_Write_28 <= (others => '0');
LMB_Addr_Strobe_28 <= '0';
LMB_Read_Strobe_28 <= '0';
LMB_Write_Strobe_28 <= '0';
LMB_Byte_Enable_28 <= (others => '0');
LMB_Data_Addr_29 <= (others => '0');
LMB_Data_Write_29 <= (others => '0');
LMB_Addr_Strobe_29 <= '0';
LMB_Read_Strobe_29 <= '0';
LMB_Write_Strobe_29 <= '0';
LMB_Byte_Enable_29 <= (others => '0');
LMB_Data_Addr_30 <= (others => '0');
LMB_Data_Write_30 <= (others => '0');
LMB_Addr_Strobe_30 <= '0';
LMB_Read_Strobe_30 <= '0';
LMB_Write_Strobe_30 <= '0';
LMB_Byte_Enable_30 <= (others => '0');
LMB_Data_Addr_31 <= (others => '0');
LMB_Data_Write_31 <= (others => '0');
LMB_Addr_Strobe_31 <= '0';
LMB_Read_Strobe_31 <= '0';
LMB_Write_Strobe_31 <= '0';
LMB_Byte_Enable_31 <= (others => '0');
end generate No_Bus_MASTER_LMB;
Use_AXI_IPIF : if (C_USE_UART = 1) or (C_DBG_REG_ACCESS = 1) generate
begin
-- ip2bus_data assignment - as core may use less than 32 bits
--ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
-- Work around spyglass bug report on <null> range to the left but not to the right
spy_g: if C_S_AXI_DATA_WIDTH > C_REG_DATA_WIDTH generate
begin
ip2bus_data(C_S_AXI_DATA_WIDTH-1 downto C_REG_DATA_WIDTH) <= (others => '0');
end generate spy_g;
---------------------------------------------------------------------------
-- AXI lite IPIF
---------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map (
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE_2,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY(0 to C_ARD_RANGES * 2 - 1),
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY(0 to C_ARD_RANGES - 1)
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end generate Use_AXI_IPIF;
No_AXI_IPIF : if (C_USE_UART = 0) and (C_DBG_REG_ACCESS = 0) generate
begin
S_AXI_AWREADY <= '0';
S_AXI_WREADY <= '0';
S_AXI_BRESP <= (others => '0');
S_AXI_BVALID <= '0';
S_AXI_ARREADY <= '0';
S_AXI_RDATA <= (others => '0');
S_AXI_RRESP <= (others => '0');
S_AXI_RVALID <= '0';
bus2ip_clk <= '0';
bus2ip_resetn <= '0';
bus2ip_data <= (others => '0');
bus2ip_rdce <= (others => '0');
bus2ip_wrce <= (others => '0');
bus2ip_cs <= (others => '0');
end generate No_AXI_IPIF;
end architecture IMP;
|
apache-2.0
|
e2860a1a480e149da8d8d6d43242020b
| 0.514834 | 3.144668 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/6039/hdl/lib_srl_fifo_v1_0_rfs.vhd
| 5 | 46,739 |
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cntr_incr_decr_addn_f.vhd
--
-- Description: This counter can increment, decrement or skip ahead
-- by an arbitrary amount.
--
-- If Reset is active, the value Cnt synchronously resets
-- to all ones. (This reset value, different than the
-- customary reset value of zero, caters to the original
-- application of cntr_incr_decr_addn_f as the address
-- counter for srl_fifo_rbu_f.)
--
-- Otherwise, on each Clk, one is added to Cnt if Incr is
-- asserted and one is subtracted if Decr is asserted. (If
-- both are asserted, then there is no change to Cnt.)
--
-- If Decr is not asserted, then the input value,
-- Nm_to_add, is added. (Simultaneous assertion of Incr
-- would add one more.) If Decr is asserted, then
-- N_to_add, is ignored, i.e., it is possible to decrement
-- by one or add N, but not both, and Decr overrides.
--
-- The value that Cnt will take on at the next clock
-- is available as Cnt_p1.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
--
-- History:
-- FLO 12/30/05 First Version.
--
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity cntr_incr_decr_addn_f is
generic (
C_SIZE : natural;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic; -- Note: the counter resets to all ones!
Incr : in std_logic;
Decr : in std_logic;
N_to_add : in std_logic_vector(C_SIZE-1 downto 0);
Cnt : out std_logic_vector(C_SIZE-1 downto 0);
Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0)
);
end entity cntr_incr_decr_addn_f;
---(
library lib_srl_fifo_v1_0_2;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture imp of cntr_incr_decr_addn_f is
-- constant COUNTER_PRIMS_AVAIL : boolean :=
-- supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS));
constant COUNTER_PRIMS_AVAIL : boolean := false;
signal cnt_i : std_logic_vector(Cnt'range);
signal cnt_i_p1 : std_logic_vector(Cnt'range);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
begin -- architecture imp
---(
INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate
--
CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr
) is
--
function qual_n_to_add(N_to_add : std_logic_vector;
Decr : std_logic
) return UNSIGNED is
variable r: UNSIGNED(N_to_add'range);
begin
for i in r'range loop
r(i) := N_to_add(i) or Decr;
end loop;
return r;
end;
--
function to_singleton_unsigned(s : std_logic) return unsigned is
variable r : unsigned(0 to 0) := (others => s);
begin
return r;
end;
--
begin
cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i)
+ qual_n_to_add(N_to_add, Decr)
+ to_singleton_unsigned(Incr)
);
end process;
--
CNT_I_PROC : process(Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
cnt_i <= (others => '1');
else
cnt_i <= cnt_i_p1;
end if;
end if;
end process;
--
end generate INFERRED_GEN;
---)
Cnt <= cnt_i;
Cnt_p1 <= cnt_i_p1;
end architecture imp;
---)
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
-- constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
-- constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
-- (C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
-- constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
constant W32 : boolean := (C_DEPTH > 16);
constant W16 : boolean := (not W32);
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
-- constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
-- and ( (W16 and C_DEPTH >= 16)
-- or (W32 and C_DEPTH >= 32)
-- )
-- )
-- or (not W32 and not W16);
constant USE_INFERRED : boolean := true;
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed lib library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity lib_srl_fifo_v1_0_2.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity lib_srl_fifo_v1_0_2.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
apache-2.0
|
1e1ccc28c23ee1a34efe121d2968b0ed
| 0.452534 | 4.913171 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/ALU_tb.vhd
| 1 | 4,811 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
ALUOP => ALUOP,
ALURESULT => ALURESULT
);
-- Stimulus process
stim_proc: process
begin
------------------SUB-------------------------------
ALUOP<="000111";
-- 5 - 28
Oper1<="00000000000000000000000000000101"; -- +5
Oper2<="00000000000000000000000000011100"; -- +28
wait for 20 ns;
-- 32 - 20
Oper1<="00000000000000000000000000100000";-- +32
Oper2<="00000000000000000000000000010100";-- +20
wait for 20 ns;
-- -45 - (+33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000100001";-- +33
wait for 20 ns;
-- -45 - (+63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000111111";-- +63
wait for 20 ns;
-- -45 - (-33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
-- -45 - (-63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-63)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-33)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
----------------SUMA----------------
ALUOP<="000110";-- 75 + 25
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- 75 + (-25)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- 75 + (-100)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-- -75 + 25
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- -75 + 100
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000001100100";-- +100
wait for 20 ns;
-- -75 + (-25)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- -75 + (-100)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-------------------OR--------------------
ALUOP<="000010";
Oper1<="11111111111111111100011110110101";
Oper2<="00000011101010001001010000001100";
wait for 20 ns;
-----------------orn---------------------
ALUOP<="000011";
wait for 20 ns;
-----------------xor-------------------
ALUOP<="000100";
wait for 20 ns;
-----------------xnor-------------------
ALUOP<="000101";
wait for 20 ns;
-----------------and-------------------
ALUOP<="000000";
wait for 20 ns;
-----------------andn-------------------
ALUOP<="000001";
wait for 20 ns;
------------------------Instrucciones aritmetico logicas no definidas-----------------------
-----------------SLL------------------
ALUOP<="001000";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRL-------------------
ALUOP<="001001";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRA----------------------
ALUOP<="001010";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
---------------Instrucciones no definidas--------------------------
ALUOP<="111111";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000011111111";
wait;
end process;
END;
|
mit
|
1ca81372a281a7ba449dcb0060a73e08
| 0.560798 | 4.496262 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/FlipFlop1Bit.vhd
| 1 | 1,571 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/18/2015 02:08:31 PM
-- Design Name:
-- Module Name: FlipFlop1Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FlipFlop1Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT; -- Input Data
Output : out BIT; -- Output Data
State : out BIT -- Current state of the Flip Flop
);
end FlipFlop1Bit;
architecture Behavioral of FlipFlop1Bit is
signal Nand1 : BIT;
signal Nand2 : BIT;
signal Not1 : BIT;
signal F1 : BIT;
signal F2 : BIT;
begin
Nand1 <= not(Load and Input);
Not1 <= not Input;
Nand2 <= not(Not1 and Load);
F1 <= not (F2 and Nand1);
F2 <= not (Nand2 and F1) after 1 ns;
-- Return the internal state for debugging/monitoring purposes
State <= F1;
Output <= F1 and Sel;
end Behavioral;
|
mit
|
3879452834150919e25d0101300269ff
| 0.562699 | 3.997455 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/principal_tb.vhd
| 1 | 1,155 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY principal_tb IS
END principal_tb;
ARCHITECTURE behavior OF principal_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MODULOPRINCIPAL
PORT(
rst : IN std_logic;
CLK : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MODULOPRINCIPAL PORT MAP (
rst => rst,
CLK => CLK,
ALURESULT => ALURESULT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
wait for 700 ns;
rst<='1';
wait;
end process;
END;
|
mit
|
0354abf702fcac83df98d4fc6b1afff3
| 0.554113 | 3.955479 | false | false | false | false |
daniw/add
|
floppy/mcu/cpu.vhd
| 2 | 2,550 |
-------------------------------------------------------------------------------
-- Entity: cpu
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Top-level of CPU for simple von-Neumann MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu is
port(rst : in std_logic;
clk : in std_logic;
-- CPU bus signals
bus_in : in t_bus2cpu;
bus_out : out t_cpu2bus
);
end cpu;
architecture rtl of cpu is
signal ctr2prc : t_ctr2prc;
signal prc2ctr : t_prc2ctr;
signal ctr2alu : t_ctr2alu;
signal alu2ctr : t_alu2ctr;
signal ctr2reg : t_ctr2reg;
signal reg2ctr : t_reg2ctr;
signal alu_res, alu_op1, alu_op2 : std_logic_vector(DW-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Instantiation of top-level components (assumed to be in library work)
-----------------------------------------------------------------------------
-- Control Unit--------------------------------------------------------------
i_ctrl: entity work.cpu_ctrl
port map(
rst => rst,
clk => clk,
data_in => bus_in.data,
addr => bus_out.addr,
data_out => bus_out.data,
r_wb => bus_out.r_wb,
reg_in => reg2ctr,
reg_out => ctr2reg,
prc_in => prc2ctr,
prc_out => ctr2prc,
alu_in => alu2ctr,
alu_out => ctr2alu
);
-- Address Generation -------------------------------------------------------
i_prc: entity work.cpu_prc
port map(
rst => rst,
clk => clk,
ctr_in => ctr2prc,
ctr_out => prc2ctr
);
-- ALU ----------------------------------------------------------------------
i_alu: entity work.cpu_alu
port map(
clk => clk,
alu_in => ctr2alu,
alu_out => alu2ctr,
oper1 => alu_op1,
oper2 => alu_op2,
result => alu_res
);
-- Register Block -----------------------------------------------------------
i_reg: entity work.cpu_reg
port map(
rst => rst,
clk => clk,
reg_in => ctr2reg,
reg_out => reg2ctr,
alu_res => alu_res,
alu_op1 => alu_op1,
alu_op2 => alu_op2
);
end rtl;
|
gpl-2.0
|
d6dfa8b81d3207984aedf8c79b9cbbd0
| 0.381961 | 4.022082 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/ip/altera/pll/pll.vhd
| 1 | 15,921 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.1.0 Build 590 10/25/2017 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
clkswitch : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
inclk1 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
inclk1_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
primary_clock : STRING;
self_reset_on_loss_lock : STRING;
switch_over_type : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clkswitch : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5 <= inclk1;
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5 & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 22727,
inclk1_input_frequency => 20833,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_USED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_USED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
primary_clock => "inclk0",
self_reset_on_loss_lock => "OFF",
switch_over_type => "MANUAL",
width_clock => 5
)
PORT MAP (
areset => areset,
clkswitch => clkswitch,
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "44.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "44.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "48.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "22727"
-- Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "20833"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_syn.v TRUE
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
8f8e616ac8f8b74898ffd7685c7153e3
| 0.69782 | 3.350379 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/Counter4Bit.vhd
| 1 | 1,395 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 10:16:50 PM
-- Design Name:
-- Module Name: Counter4Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Counter4Bit is
port
(
Clock : in BIT;
Reset : in BIT;
Output: out STD_LOGIC_VECTOR(3 downto 0)
);
end Counter4Bit;
architecture Behavioral of Counter4Bit is
signal temp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
main: process (Clock, Reset)
begin
if (Reset = '1') then
temp <= "0000";
else if (Clock'event and Clock = '1') then
temp <= UNSIGNED(temp) + 1;
end if;
end if;
Output <= temp;
end process;
end Behavioral;
|
mit
|
5e85090b760237ce16016650909d9dd0
| 0.555556 | 4.055233 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/CounterTest/counter_toplevel.vhd
| 1 | 1,851 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2014
-- Module Name: counter
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Clock toplevel
-- Top level design of the clock counter
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity clock_toplevel is
Port ( CLK : in STD_LOGIC; -- 50 MHz Oscillator
BTN : in STD_LOGIC; -- Reset Button
SW : in STD_LOGIC_VECTOR (1 downto 0); -- Switch 0:add/sub, 1: clk speed
LED : out STD_LOGIC_VECTOR (7 downto 0));
end clock_toplevel;
architecture Structural of clock_toplevel is
signal CLOCK_DIVIDER : STD_LOGIC := '0'; -- Divided Clock Output
signal CLK2 : STD_LOGIC := '0'; -- 2 HZ line
signal CLK4 : STD_LOGIC := '0'; -- 4 HZ line
begin
----- Structural Components: -----
clk2Hz: entity work.clk2Hz
port map( CLK_IN => CLK,
RST => BTN,
CLK_OUT => CLK2);
clk4Hz: entity work.clk4Hz
port map( CLK_IN => CLK,
RST => BTN,
CLK_OUT => CLK4);
mux1: entity work.mux_2to1
port map( SEL => SW(1),
IN_1 => CLK2,
IN_2 => CLK4,
MOUT => CLOCK_DIVIDER);
counter: entity work.counter
port map( CLK => CLOCK_DIVIDER,
DIRECTION => SW(0),
RST => BTN,
COUNT_OUT => LED);
----- End Structural Components -----
end Structural;
|
mit
|
c8d2bad563dc43a0c8121328a6c7eea4
| 0.52134 | 4.068132 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/5ab6/hdl/lib_fifo_v1_0_rfs.vhd
| 3 | 195,893 |
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- - Update to use fifo_generator_v13_0_5 (New parameter C_EN_SAFETY_CKT is added with default value as 0 or disabled)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
library fifo_generator_v13_1_3;
use fifo_generator_v13_1_3.all;
--library lib_fifo_v1_0_7;
--use lib_fifo_v1_0_7.lib_fifo_pkg.all;
--use lib_fifo_v1_0_7.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_EN_SAFETY_CKT : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
Constant C_DEFAULT_VALUE : String := "BlankString"; -- new for FIFO Gen
Constant C_PRIM_FIFO_TYPE : String := "512x36"; -- new for FIFO Gen
Constant RST_VAL : String := "0"; -- new for FIFO Gen
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
Constant C_HAS_RST_INT : integer := 1;--if_then_else(C_EN_SAFETY_CKT = 1,0,1);
Constant C_HAS_SRST_INT : integer := 0;--if_then_else(C_EN_SAFETY_CKT = 1,1,0);
--Constant C_HAS_SRST_INT : integer := 0 when (C_EN_SAFETY_CKT = 1) else 1;
Constant C_EN_SAFETY_CKT_1 : integer := if_then_else(C_USE_BLOCKMEM = 1,C_EN_SAFETY_CKT,0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
signal Full_int : std_logic;
signal Almost_full_int : std_logic;
begin --(architecture implementation)
full_gen: if (C_EN_SAFETY_CKT_1 = 1) generate
begin
Full <= Full_int or WR_RST_BUSY;
Almost_full <= Almost_full_int or WR_RST_BUSY;
end generate full_gen;
full_gen1: if (C_EN_SAFETY_CKT_1 = 0) generate
begin
Full <= Full_int;
Almost_full <= Almost_full_int;
end generate full_gen1;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => RST_VAL,--"0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full_int,
almost_full => Almost_full_int,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT_1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full_int, -- : OUT std_logic;
almost_full => Almost_full_int, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_3
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_3;
use fifo_generator_v13_1_3.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq" and FAMILY_TO_USE /= "spartan7") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq" or FAMILY_TO_USE = "spartan7") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_3.fifo_generator_v13_1_3
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
apache-2.0
|
e1658a577333356a93842817cbb446b1
| 0.411531 | 3.897825 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/ALUwithInput/SevenSeg.vhd
| 1 | 4,018 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: SevenSeg
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description: 7-segment display controller
-- Will power the 4 7-seg displays on the Nexys 2
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SSegDriver is
port (
CLK : in STD_LOGIC; -- 50 MHz input
RST : in STD_LOGIC;
EN : in STD_LOGIC;
SEG_0 : in STD_LOGIC_VECTOR (3 downto 0);
SEG_1 : in STD_LOGIC_VECTOR (3 downto 0);
SEG_2 : in STD_LOGIC_VECTOR (3 downto 0);
SEG_3 : in STD_LOGIC_VECTOR (3 downto 0);
DP_CTRL : in STD_LOGIC_VECTOR (3 downto 0);
COL_EN : in STD_LOGIC;
SEG_OUT : out STD_LOGIC_VECTOR (6 downto 0);
DP_OUT : out STD_LOGIC;
AN_OUT : out STD_LOGIC_VECTOR (3 downto 0)
);
end SSegDriver;
architecture Behavioral of SSegDriver is
signal hexnum : STD_LOGIC_VECTOR (3 downto 0);
signal segnum : STD_LOGIC_VECTOR (6 downto 0);
signal clk240hz : STD_LOGIC :='0'; -- 240Hz clock line ~= 4ms
CONSTANT wait240hz : integer := 104166; -- (50E6/240)/2 = 104166.66
signal count240hz : integer range 0 to wait240hz := 0;
signal pos : STD_LOGIC_VECTOR (1 downto 0);
begin
SEG_OUT <= segnum;
--convert current hex to the segment display
with hexnum select
segnum <=
"1000000" when "0000", -- 0
"1111001" when "0001", -- 1
"0100100" when "0010", -- 2
"0110000" when "0011", -- 3
"0011001" when "0100", -- 4
"0010010" when "0101", -- 5
"0000010" when "0110", -- 6
"1111000" when "0111", -- 7
"0000000" when "1000", -- 8
"0010000" when "1001", -- 9
"0001000" when "1010", -- A
"0000011" when "1011", -- B
"1000110" when "1100", -- C
"0100001" when "1101", -- D
"0000110" when "1110", -- E
"0001110" when "1111", -- F
"1111111" when others; -- Invalid number
clk_div_240hz: process (RST, CLK, EN) begin
if (RST = '1') then
clk240hz <= '0';
count240hz <= 0;
elsif (rising_edge(CLK) and EN = '1') then
if (count240hz = wait240hz) then
if(clk240hz='0') then
clk240hz <= '1';
else
clk240hz <= '0';
end if;
count240hz <= 0;
else
count240hz <= count240hz + 1;
end if;
end if;
end process;
disp_driver: process (RST, CLK) begin
if (RST = '1') then
pos <= "00";
hexnum <= (others => '0');
DP_OUT <= '1';
AN_OUT <= (others => '0');
elsif rising_edge(clk240hz) then
pos <= pos + 1;
if (pos = "11") then
pos <= "00";
end if;
case (pos) is
when "00" =>
hexnum <= SEG_0;
AN_OUT <= "0111";
DP_OUT <= DP_CTRL(0);
when "01" =>
hexnum <= SEG_1;
AN_OUT <= "1011";
DP_OUT <= DP_CTRL(1);
when "10" =>
hexnum <= SEG_2;
AN_OUT <= "1101";
DP_OUT <= DP_CTRL(2);
when "11" =>
hexnum <= SEG_3;
AN_OUT <= "1110";
DP_OUT <= DP_CTRL(3);
when others =>
hexnum <= (others => '0');
AN_OUT <= (others => '0');
end case;
end if;
end process;
end Behavioral;
|
mit
|
510998028628cf4ffb3006d79c8c38b0
| 0.463912 | 3.837631 | false | false | false | false |
KPU-RISC/KPU
|
VHDL/RCL8Bit.vhd
| 1 | 1,411 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 12:51:34 PM
-- Design Name:
-- Module Name: RCL8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RCL8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end RCL8Bit;
architecture Behavioral of RCL8Bit is
begin
Cout <= Input(7);
Output(0) <= Cin;
Output(1) <= Input(0);
Output(2) <= Input(1);
Output(3) <= Input(2);
Output(4) <= Input(3);
Output(5) <= Input(4);
Output(6) <= Input(5);
Output(7) <= Input(6);
end Behavioral;
|
mit
|
1a4709f09dcf6d6270ba22eff901f99f
| 0.537208 | 3.813514 | false | false | false | false |
daniw/add
|
lab1/Ex2/FIR_1x5_load_coeff/vhd/fir_1d_trn_load_tb.vhd
| 1 | 6,840 |
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 19-May-11
-- Project : RT Video Lab 1: Exercise 2
-- Description: Testbench for 5-tap FIR filter with loadable coefficients
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std; use std.textio.all;
entity fir_1d_load_tb IS
end fir_1d_load_tb;
architecture behavior of fir_1d_load_tb is
-- Component Declaration for the Unit Under Test (UUT)
component fir_1d_trn_load is
generic
(IN_DW, OUT_DW, COEF_DW, TAPS, DELAY : integer);
port
(ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector; -- coefficients
din : in std_logic_vector; -- data input
out_data : out std_logic_vector -- filtered output data
);
end component;
-- clock frequency definition
constant clk_freq : real := 100.0; -- 100 MHz
constant t_clk : time := 1000.0/clk_freq * 1 ns; -- one clock period
-- define delays for timing-simulation
constant t_stim : time := 0.25*t_clk; -- delay time for stimuli application
constant t_prop : time := 0.25*t_clk; -- propagation delay for UUT mimic
-- design parameters
constant IN_DW : integer := 8;
constant OUT_DW : integer := 19;
constant COEF_DW: integer := 7;
constant TAPS : integer := 5;
constant DELAY : integer := 8; -- adapt to adjust filter latency!!!
-- inputs signals
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal coef : std_logic_vector(COEF_DW-1 downto 0) := (others => '0');
signal din : std_logic_vector(IN_DW-1 downto 0) := (others => '0');
-- outputs signals
signal out_data : std_logic_vector(OUT_DW-1 downto 0) := (others => '0');
-- local testbench control signals
signal load_done : boolean := false;
signal err_cnt : natural := 0;
-- I/O files
-- Expeceted responses are generated for the middle row of the corresponding
-- filter mask, which correspnds to the following coefficients:
-- Filter : b0 b1 b2 b3 b4
------------------------------------------
-- 1_Identity : 0 0 1 0 0
-- 2_Edge : 0 -1 8 -1 0
-- 3_SobelX : 0 2 0 -2 0
-- 4_SobelY : 0 0 0 0 0
-- 5_SobelXY : 0 -1 0 1 0
-- 6_Blur : 1 0 0 0 1
-- 7_Smooth : 1 5 44 5 1
-- 8_Sharpen : 0 -2 32 -2 0
-- 9_Gaussian : 2 4 8 4 2
------------------------------------------
constant mask_type : string := "7_Smooth";
file f_stimuli_d : text is in "..\1x5_Filter\" & mask_type & "\FIR_IN.txt";
file f_stimuli_c : text is in "..\1x5_Filter\" & mask_type & "\COEF_SEQ.txt";
file f_exp_resp : text is in "..\1x5_Filter\" & mask_type & "\FIR_OUT.txt";
file f_act_resp : text is out "..\1x5_Filter\" & mask_type & "\FIR_VHDL_OUT.txt";
begin
-- Instantiate the Unit Under Test
uut : fir_1d_trn_load
generic map (
IN_DW => IN_DW,
OUT_DW => OUT_DW,
COEF_DW => COEF_DW,
TAPS => TAPS,
DELAY => DELAY
)
port map (
ce_1 => '1',
clk_1 => clk,
load => load,
coef => coef,
din => din,
out_data => out_data
);
-- Clock generation
p_clk :process
begin
wait for t_clk/2;
clk <= not clk;
end process;
-- apply coeff_load stimuli to UUT
p_stim_c:process(clk)
variable inline : line;
variable char : character;
variable cnt_load : natural := 0;
begin
if clk'event and clk = '1' then
cnt_load := cnt_load + 1;
-- generate load-pulse 5 cycles long
if cnt_load = 100 then
load <= '1' after t_stim;
elsif cnt_load = 105 then
load <= '0' after t_stim;
end if;
-- apply coefficients 1 cycle too early and one cycle too long in order
-- to check correct load sequence (see COEF_SEQ.txt)
if cnt_load >= 100 then
if not endfile(f_stimuli_c) then
readline(f_stimuli_c,inline);
for k in COEF_DW-1 downto 0 loop
read(inline,char);
if char = '0' then
coef(k) <= '0' after t_stim;
else
coef(k) <= '1' after t_stim;
end if;
end loop;
else
-- start data_in application
load_done <= true;
end if;
end if;
end if;
end process;
-- apply data_in stimuli to UUT
p_stim_d:process(clk)
variable inline : line;
variable char : character;
begin
if clk'event and clk = '1' then
if load_done and (not endfile(f_stimuli_d)) then
readline(f_stimuli_d,inline);
for k in IN_DW-1 downto 0 loop
read(inline,char);
if char = '0' then
din(k) <= '0' after t_stim;
else
din(k) <= '1' after t_stim;
end if;
end loop;
elsif endfile(f_stimuli_d) then
-- end of simulation
assert false report "******** End of simulation : " &
"Total Number of Mismatches detected = " &
integer'image(err_cnt) &
" ********"
severity failure;
end if;
end if;
end process;
-- compare expected with actual responses and write output file
p_check: process(clk)
variable line_exp, line_act : line;
variable str_exp, str_act : string(OUT_DW downto 1);
begin
if clk'event and clk = '1' then
if load_done then
-- read expected value from file
readline(f_exp_resp, line_exp);
for k in OUT_DW-1 downto 0 loop
-- get all bits in actual output
if out_data(k) = '0' then
str_act(k+1) := '0';
elsif out_data(k) = '1' then
str_act(k+1) := '1';
end if;
write(line_act, str_act(k+1));
-- get all bits in expected output
read(line_exp, str_exp(k+1));
end loop;
-- write actual value to file
writeline(f_act_resp, line_act);
-- compare actual and expected output vector
if not (str_exp = str_act) then
assert false
report "expected: " & str_exp & " actual: " & str_act severity note;
err_cnt <= err_cnt + 1;
end if;
end if;
end if;
end process;
end;
|
gpl-2.0
|
48cc0bc6115493160603c515c1bda1c6
| 0.50848 | 3.624801 | false | false | false | false |
daniw/add
|
rot_enc/cpu_prc.vhd
| 3 | 2,652 |
-------------------------------------------------------------------------------
-- Entity: cpu_prc
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Program Counter unit for the RISC-CPU of the von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: 8 + 2
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_prc is
port(rst : in std_logic;
clk : in std_logic;
-- CPU internal interfaces
ctr_in : in t_ctr2prc;
ctr_out : out t_prc2ctr
);
end cpu_prc;
architecture rtl of cpu_prc is
-- program counter and exception signals
signal pc : std_logic_vector(AW-1 downto 0);
signal exc : t_addr_exc;
begin
-- assign outputs
ctr_out.pc <= pc;
ctr_out.exc <= exc;
-----------------------------------------------------------------------------
-- Program Counter
-----------------------------------------------------------------------------
P_pc: process(clk, rst)
variable v_pc : std_logic_vector(AW-1 downto 0);
variable v_addr : std_logic_vector(AW downto 0);
begin
if rst = '1' then
pc <= (others => '0');
exc <= no_err;
elsif rising_edge(clk) then
if ctr_in.enb = '1' then
exc <= no_err; -- default assignment
case ctr_in.mode is
when linear =>
-- PC := PC + 1
v_pc := std_logic_vector(unsigned(pc) + 1);
if v_pc(AW-1) /= BA(ROM)(AW-1) then -- NOT NICE! Find better solution!!!!!!!!!!!!!!!!!!!!!!!
-- PC would leave ROM address space
-- do not increment and issue error
exc <= lin_err;
else
pc <= v_pc;
end if;
when abs_jump =>
-- PC := addr
pc <= ctr_in.addr;
when rel_offset =>
-- PC := PC + addr
v_addr := std_logic_vector(unsigned('0' & pc) + unsigned(ctr_in.addr));
pc <= v_addr(AW-1 downto 0);
if v_addr(AW) = '1' and ctr_in.addr(AW-1) = '0' then
-- overflow with addition of positive relative offset
exc <= rel_err;
elsif v_addr(AW) = '0' and ctr_in.addr(AW-1) = '1' then
-- underflow with addition of negative relative offset
exc <= rel_err;
end if;
when others => null;
end case;
end if;
end if;
end process;
end rtl;
|
gpl-2.0
|
bae4ec076034f63889aadf8dc8fa103d
| 0.423831 | 4.202853 | false | false | false | false |
jeffmagina/ECE368
|
Lab1/CounterTest/clk8Hz.vhd
| 1 | 1,419 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: CLK4Hz
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Clock Divider
-- Lower the Clock frequency from
-- 50 Mhz to 4 hz
-- 50Mhz = 50,000,000/12,500,000 = 2 Hz
-- 4Hz ~= 1/2 second
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk4Hz is
Port ( CLK_IN : in STD_LOGIC;
RST : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end clk4Hz;
architecture Behavioral of clk4Hz is
signal clkdv: STD_LOGIC:='0';
signal counter : integer range 0 to 6250000 := 0;
begin
frequency_divider: process (RST, CLK_IN) begin
if (RST = '1') then
clkdv <= '0';
counter <= 0;
elsif rising_edge(CLK_IN) then
if (counter = 6250000) then
if(clkdv='0') then
clkdv <= '1';
else
clkdv <= '0';
end if;
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
CLK_OUT <= clkdv;
end Behavioral;
|
mit
|
0e818c40c1b8d3cc188729d17a0b7d7d
| 0.497533 | 4.113043 | false | false | false | false |
jeffmagina/ECE368
|
Lab2/Keyboard Debug Unit/DEBUG_CONTROLLER.vhd
| 1 | 2,196 |
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Jeffrey Magina and Jon Leidhold
--
-- Create Date: SPRING 2015
-- Module Name: DEBUG CONTROLLER
-- Project Name: DEBUG CONTROLLER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debug Unit for part 4 of Lab 1
-- Takes in a 0 - F on the ASCII_DATA line
-- and outputs it to the BUFFER concatenated
-- together to form the Instruction
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEBUG_CONTROLLER is
Port( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0));
end DEBUG_CONTROLLER;
architecture Structural of DEBUG_CONTROLLER is
signal RD : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal KEY_DATA : STD_LOGIC_VECTOR (7 downto 0);
signal TO_SEG : STD_LOGIC_VECTOR(15 downto 0);
signal cen : STD_LOGIC := '0';
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
U1: entity work.KEYBOARD_CONTROLLER
Port MAP ( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
ASCII_OUT => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE);
U2: entity work.ASCII_BUFFER
port MAP(
ASCII_DATA => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE,
CLK => CLK,
RST => RST,
ASCII_BUFF => TO_SEG);
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => '0',
EN => enl,
SEG_0 => TO_SEG(15 downto 12),
SEG_1 => TO_SEG(11 downto 8),
SEG_2 => TO_SEG(7 downto 4),
SEG_3 => TO_SEG(3 downto 0),
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
end Structural;
|
mit
|
60b979b30e8b0c510de9a5624643cb9b
| 0.549636 | 3.458268 | false | false | false | false |
aggroskater/ee4321-vhdl-digital-design
|
Project-5-Sequence-Detector-Moore-Machine/sequence_detector.vhd
| 1 | 3,107 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
--NOTE: The following link is a very helpful reference:
--http://cseweb.ucsd.edu/~tweng/cse143/VHDLReference/aa.pdf
entity moore_seq_detect is
port (
x : IN STD_LOGIC;
clock : IN STD_LOGIC;
z : OUT STD_LOGIC
);
end;
architecture Behavioural of moore_seq_detect is
--declare state vars (this is basically enumerating
--a list of the possible values that a type of
--"state_type" may hold)
type state_type is (sr, s0, s1, s2, s3, s4, s5, s6);
--declare internal signals and their type. At any
--given time, each state could be defined as any of
--the states enumerated above (sr, s0, ... , s6).
--current state defaults to sr
signal current_state: state_type := sr;
signal next_state: state_type;
--count tells us how many times the sequence has been
--detected
signal count : std_logic_vector(3 downto 0) := "0000";
--z_internal serves as a snooper for the output z. let's us
--check value of z during clock process to appropriately
--update count variable.
signal z_internal : std_logic;
BEGIN
--be sure to map z_internal back to the actual output z.
z <= z_internal;
--combinatorial portion
proc_cruncher: process(current_state, x)
begin
case current_state is
when sr =>
z_internal <= '0';
if x = '0' then
next_state <= sr;
else
next_state <= s0;
end if;
when s0 =>
z_internal <= '0';
if x = '0' then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
z_internal <= '0';
if x = '0' then
next_state <= sr;
else
next_state <= s2;
end if;
when s2 =>
z_internal <= '0';
if x = '0' then
next_state <= s1;
else
next_state <= s3;
end if;
when s3 =>
z_internal <= '0';
if x = '0' then
next_state <= s4;
else
next_state <= s0;
end if;
when s4 =>
z_internal <= '0';
if x = '0' then
next_state <= s5;
else
next_state <= s2;
end if;
when s5 =>
z_internal <= '0';
if x = '0' then
next_state <= sr;
else
next_state <= s6;
end if;
when s6 =>
z_internal <= '1';
if x = '0' then
next_state <= s1;
else
next_state <= s0;
end if;
when others =>
next_state <= sr;
end case;
end process;
--sync'd portion
--using wait directive precludes need to pass clock to process directly.
--(I think)
proc_clock: process
begin
wait until clock'event and clock = '1';
--I tried simply updating count within the combinatorial block,
--but it always double counted. Here, we only ever increment
--on the positive edge of the clock, so there's no chance for
--double counting the same z=1 signal (the z=1 signal drops
--by the next clock cycle).
if ( z_internal = '1' ) then
count <= std_logic_vector(unsigned(count) + 1);
end if;
current_state <= next_state;
end process;
end Behavioural;
|
agpl-3.0
|
edfc8b64f6a625467843c594b1040941
| 0.594786 | 3.351672 | false | false | false | false |
gustavogarciautp/Procesador
|
Entrega 1/CU.vhd
| 1 | 975 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CU is
Port ( OP : in STD_LOGIC_VECTOR (1 downto 0);
OP3 : in STD_LOGIC_VECTOR (5 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0));
end CU;
architecture Behavioral of CU is
begin
process(OP,OP3)
begin
case OP is
when "10"=>
case OP3 is --Instrucciones aritmetico logicas
when "000001"=>ALUOP<="000000"; --0. AND
when "000101"=>ALUOP<="000001"; --1. ANDN
when "000010"=>ALUOP<="000010"; --2. OR
when "000110"=>ALUOP<="000011"; --3. ORN
when "000011"=>ALUOP<="000100"; --4. XOR
when "000111"=>ALUOP<="000101"; --5. XNOR
when "000000"=>ALUOP<="000110"; --6. ADD
when "000100"=>ALUOP<="000111"; --7. SUB
when others =>ALUOP<="111111"; --Otras instrucciones aritmetico logicas aun no definidas
end case;
when others=>ALUOP<="111111";--Otras instrucciones aun no definidas
end case;
end process;
end Behavioral;
|
mit
|
20c8f2acc60db3c4c35910ba06ef41c4
| 0.614359 | 3.293919 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_ilmb_bram_if_cntlr_0/sim/system_ilmb_bram_if_cntlr_0.vhd
| 1 | 12,257 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0_10;
USE lmb_bram_if_cntlr_v4_0_10.lmb_bram_if_cntlr;
ENTITY system_ilmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END system_ilmb_bram_if_cntlr_0;
ARCHITECTURE system_ilmb_bram_if_cntlr_0_arch OF system_ilmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR;
C_BASEADDR : STD_LOGIC_VECTOR;
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR;
C_MASK1 : STD_LOGIC_VECTOR;
C_MASK2 : STD_LOGIC_VECTOR;
C_MASK3 : STD_LOGIC_VECTOR;
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_BRAM_AWIDTH : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"0000000000007FFF",
C_BASEADDR => X"0000000000000000",
C_NUM_LMB => 1,
C_MASK => X"0000000080000000",
C_MASK1 => X"0000000000800000",
C_MASK2 => X"0000000000800000",
C_MASK3 => X"0000000000800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_BRAM_AWIDTH => 32,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END system_ilmb_bram_if_cntlr_0_arch;
|
apache-2.0
|
152afbec28135c9986455e3c973f3f65
| 0.652607 | 3.23489 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ip/system_axi_timer_0_0/synth/system_axi_timer_0_0.vhd
| 1 | 9,191 |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END system_axi_timer_0_0;
ARCHITECTURE system_axi_timer_0_0_arch OF system_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_timer_0_0_arch : ARCHITECTURE IS "system_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_timer_0_0_arch: ARCHITECTURE IS "system_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "artix7",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END system_axi_timer_0_0_arch;
|
apache-2.0
|
5db1deef2df6ca1c8739324f3ea1b2f3
| 0.691546 | 3.307305 | false | false | false | false |
alextrem/red-diamond
|
fpga/vhdl/spdif_pkg.vhd
| 1 | 7,217 |
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 02/26/2015
-- Design Name:
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This AES3/EBU and SPDIF receiver is compliant with
-- IEC61937, IEC60958-3 and IEC60958-4
-- This package contains constants and type definitions
-- for the receiver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Changed indentation
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package spdif_pkg is
-- statemachine type
type t_aes3_state is (UNLOCKED, CONFIRMING, LOCKED);
type t_aes_in is record
data : std_logic;
--rx_full : std_ulogic;
--rx_fifo_de : std_ulogic;
end record;
type t_aes_out is record
lock : std_logic;
frame_clock : std_logic;
--i2s_out : std_ulogic;
--rx_de : std_ulogic;
--rx_fifo_full : std_ulogic;
--rx_data : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant X_PREAMBLE : std_logic_vector(7 downto 0) := "01000111";
constant Y_PREAMBLE : std_logic_vector(7 downto 0) := "00100111";
constant Z_PREAMBLE : std_logic_vector(7 downto 0) := "00010111";
-- AES3/EBU or SPDIF stream constants
constant FRAMES : integer := 192;
subtype FRAME_WIDTH is integer range FRAMES-1 downto 0;
constant CHANNELS : integer := 2;
constant SUBFRAME : integer := 32;
-- channel status description
type t_byte_0 is record
channel_use : std_logic; -- professional or consumer
pcm : std_logic; -- PCM indication
preemphasis : std_logic_vector(2 downto 0); -- signal pre-emphasis
lock : std_logic; -- lock indication
sample_frequency : std_logic_vector(1 downto 0); -- encoded sampling freq.
end record t_byte_0;
type t_byte_1 is record
channel_mode : std_logic_vector(3 downto 0);
user_bit : std_logic_vector(3 downto 0);
end record t_byte_1;
type t_byte_2 is record
aux_sample_bits : std_logic_vector(2 downto 0);
sample_word_length : std_logic_vector(2 downto 0);
alignment_level : std_logic_vector(1 downto 0);
end record t_byte_2;
type t_byte_3 is record
multichannel_mode : std_logic_vector(6 downto 0);
channel_number : std_logic;
end record t_byte_3;
type t_byte_4 is record
reference_signal : std_logic_vector(1 downto 0);
reserved : std_logic;
sampling_frequency : std_logic_vector(3 downto 0);
frequency_scaling : std_logic;
end record t_byte_4;
type t_byte_5 is record
reserved : std_logic_vector(7 downto 0);
end record;
type t_byte_6_to_9 is record
channel_origin_1 : std_logic_vector(7 downto 0);
channel_origin_2 : std_logic_vector(7 downto 0);
channel_origin_3 : std_logic_vector(7 downto 0);
end record t_byte_6_to_9;
type t_byte_10_to_13 is record
channel_destination_1 : std_logic_vector(7 downto 0);
channel_destination_2 : std_logic_vector(7 downto 0);
channel_destination_3 : std_logic_vector(7 downto 0);
end record t_byte_10_to_13;
type t_byte_14_to_17 is record
lsac_0 : std_logic_vector(7 downto 0); -- local sample address code
lsac_1 : std_logic_vector(7 downto 0); -- local sample address code
lsac_2 : std_logic_vector(7 downto 0); -- local sample address code
lsac_3 : std_logic_vector(7 downto 0); -- local sample address code
end record t_byte_14_to_17;
type t_byte_18_to_21 is record
tsc_0 : std_logic_vector(7 downto 0); -- time of day sample code
tsc_1 : std_logic_vector(7 downto 0); -- time of day sample code
tsc_2 : std_logic_vector(7 downto 0); -- time of day sample code
tsc_3 : std_logic_vector(7 downto 0); -- time of day sample code
end record t_byte_18_to_21;
type channel_status is record
reg_0 : t_byte_0;
reg_1 : t_byte_1;
reg_2 : t_byte_2;
reg_3 : t_byte_3;
reg_4 : t_byte_4;
reg_5 : t_byte_5;
origin : t_byte_6_to_9;
destination : t_byte_10_to_13;
sample_address : t_byte_14_to_17;
time_of_day : t_byte_18_to_21;
reliability : std_logic_vector(7 downto 0);
crc : std_logic_vector(7 downto 0);
end record channel_status;
-- RX data will be 8 times oversampled
-- 192000 Hz : 24,576 MHz
-- 176400 Hz : 22,5792 MHz
-- 96000 Hz : 12,288 MHz
-- 88200 Hz : 11,2896 MHz
-- 48000 Hz : 6,144 MHz
-- 44100 Hz : 5,6448 MHz
-- 32000 Hz : 4,096 MHz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function preamble_detection (
data : std_logic_vector(7 downto 0);
const : std_logic_vector(7 downto 0) )
return std_logic;
function crcc (
data : std_logic_vector(7 downto 0);
crc : std_logic_vector(7 downto 0) )
return std_logic_vector;
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component aes3rx
port (
clk : in std_ulogic;
reset : in std_ulogic;
-- aes/ebu interface definition
aes_in : in t_aes_in;
aes_out : out t_aes_out
);
end component;
end spdif_pkg;
package body spdif_pkg is
function preamble_detection (
data : std_logic_vector(7 downto 0);
const : std_logic_vector(7 downto 0))
return std_logic is
variable v : std_logic := '0';
begin
if data = const or data = not const then
v := '1';
else
v := '0';
end if;
return v;
end preamble_detection;
function crcc (
data : std_logic_vector(7 downto 0);
crc : std_logic_vector(7 downto 0))
return std_logic_vector is
variable d : std_logic_vector(7 downto 0);
variable c : std_logic_vector(7 downto 0);
variable n : std_logic_Vector(7 downto 0);
begin
d := data;
c := crc;
n(0) := d(0) xor d(4) xor d(5) xor d(6) xor c(0) xor c(4) xor c(5) xor c(6);
n(1) := d(1) xor d(5) xor d(6) xor d(7) xor c(1) xor c(5) xor c(6) xor c(7);
n(2) := d(0) xor d(2) xor d(4) xor d(5) xor d(7) xor c(0) xor c(2) xor c(4) xor c(5) xor c(7);
n(3) := d(0) xor d(1) xor d(3) xor d(4) xor c(0) xor c(1) xor c(3) xor c(4);
n(4) := d(0) xor d(1) xor d(2) xor d(6) xor c(0) xor c(1) xor c(2) xor c(6);
n(5) := d(1) xor d(2) xor d(3) xor d(7) xor c(1) xor c(2) xor c(3) xor c(7);
n(6) := d(2) xor d(3) xor d(4) xor c(2) xor c(3) xor c(4);
n(7) := d(3) xor d(4) xor d(5) xor c(3) xor c(4) xor c(5);
return n;
end crcc;
end;
|
gpl-3.0
|
e92c7acc374d51fb59918c981de8de69
| 0.54815 | 3.31359 | false | false | false | false |
nishtahir/arty-blaze
|
src/bd/system/ipshared/4f16/hdl/axi_gpio_v2_0_vh_rfs.vhd
| 2 | 68,745 |
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_13 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_13 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_4;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_13 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_13;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_13.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
|
apache-2.0
|
9b1a5923184eb9b038d2ab8d2bd6b36a
| 0.440454 | 4.141515 | false | false | false | false |
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