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vinodpa/openPowerlink-FPGA
|
Examples/ipcore/common/pdi/src/pdi_par.vhd
| 3 | 14,711 |
-------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
papBigEnd_g : boolean := false; --deprecated
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
signal ap_address_write, ap_address_write_l : std_logic_vector(ap_address'range);
signal ap_byteenable_write, ap_byteenable_write_l : std_logic_vector(ap_byteenable'range);
signal ap_address_read : std_logic_vector(ap_address'range);
signal ap_byteenable_read : std_logic_vector(ap_byteenable'range);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- store addr and be for write access
-- note: this reduces the address hold time to zero
--
addrStore : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
ap_address_write_l <= (others => '0');
ap_byteenable_write_l <= (others => '0');
ap_address_write <= (others => '0');
ap_byteenable_write <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
if pap_cs_s = '1' then
ap_address_write_l <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_write_l <= ap_byteenable_s;
end if;
ap_address_write <= ap_address_write_l;
ap_byteenable_write <= ap_byteenable_write_l;
end if;
end process;
ap_address_read <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_read <= ap_byteenable_s;
ap_address <= ap_address_write when ap_write_s = '1' else
ap_address_read;
ap_byteenable <= ap_byteenable_write when ap_write_s = '1' else
ap_byteenable_read;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s and not ap_write_s;
ap_chipselect <= (pap_cs_s and pap_rd_s) or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 0) = "00" else
"0010" when pap_addr_s(1 downto 0) = "01" else
"0100" when pap_addr_s(1 downto 0) = "10" else
"1000" when pap_addr_s(1 downto 0) = "11" else
(others => '0');
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" else
(others => '0');
-- ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s;
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss;
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
|
gpl-2.0
|
3c01608689b56352ff78c08219144007
| 0.461559 | 4.281432 | false | false | false | false |
spoorcc/realtimestagram
|
src/test_bench_driver_color.vhd
| 2 | 8,650 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
--! use standard library
library ieee;
--! use std_logic_vector
use ieee.std_logic_1164.all;
--! needed for colorscheme calculations
use ieee.numeric_std.all;
--! used for writing and reading images
use std.textio.all;
--! used only for calculation of constants
use ieee.math_real.all;
use work.image_io_pkg.all;
use work.config_const_pkg.all;
entity test_bench_driver_color is
generic (
wordsize: integer; --! size of input pixel value in bits
input_file: string;
output_file: string;
clk_period_ns: time := 2 ns;
rst_after: time := 10 ns;
rst_duration: time := 10 ns;
--! Number of clk pulses of delay of a Device Under Test between input and output
dut_delay: integer := 1;
h_count_size: integer := integer(ceil(log2(real(const_imagewidth))));
v_count_size: integer := integer(ceil(log2(real(const_imageheight))))
);
port (
clk: out std_logic; --! completely clocked process
rst: out std_logic; --! asynchronous reset
enable: out std_logic;
h_count: out std_logic_vector(h_count_size-1 downto 0) := (others => '0');
v_count: out std_logic_vector(v_count_size-1 downto 0) := (others => '0');
red_pixel_from_file: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
green_pixel_from_file: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
blue_pixel_from_file: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
red_pixel_to_file: in std_logic_vector((wordsize-1) downto 0); --! the output pixel
green_pixel_to_file: in std_logic_vector((wordsize-1) downto 0); --! the output pixel
blue_pixel_to_file: in std_logic_vector((wordsize-1) downto 0) --! the output pixel
);
end entity;
architecture behavioural of test_bench_driver_color is
--===================signal declaration===================--
signal tb_clk: std_logic := '0';
signal tb_rst: std_logic := '0';
signal tb_enable: std_logic := '0';
signal tb_done: std_logic := '0';
signal dut_data_valid: std_logic := '0';
signal end_of_file: std_logic := '0';
signal red_pixel_tmp: std_logic_vector(wordsize-1 downto 0) := (others => '0');
signal green_pixel_tmp: std_logic_vector(wordsize-1 downto 0) := (others => '0');
signal blue_pixel_tmp: std_logic_vector(wordsize-1 downto 0) := (others => '0');
--===================file declaration===================--
--! File containing pixels for input of the testbench
file file_input_pixel: text open read_mode is input_file;
--! File used as output for the tesbench
file file_output_pixel: text open write_mode is output_file;
begin
--===================rst===================--
tb_rst <= '0', '1' after rst_after, '0' after rst_after+rst_duration when (tb_done = '0');
rst <= tb_rst;
--===================clock===================--
tb_clk <= not tb_clk after clk_period_ns when (tb_done = '0');
clk <= tb_clk;
--=================== enable ===============--
enable <= tb_enable;
--=================== release ===============--
release_process: process(tb_clk, tb_rst, end_of_file)
variable pre_delay_count : integer := dut_delay;
variable post_delay_count : integer := dut_delay - 1;
begin
if rising_edge(tb_clk) then
if tb_rst = '1' then
tb_enable <= '1'; -- enable tb
end if;
if tb_enable = '1' and tb_rst = '0' then
if pre_delay_count > 0 then
pre_delay_count := pre_delay_count - 1;
else
dut_data_valid <= '1';
end if;
end if;
if end_of_file = '1' or post_delay_count < dut_delay-1 then
if post_delay_count > 0 then
post_delay_count := post_delay_count - 1;
else
tb_enable <= '0';
tb_done <= '1';
end if;
end if;
end if;
end process;
--===================process for reading input_pixels ===============--
reading_input_pixels: process(tb_clk)
constant pgm_width : integer := const_imagewidth;
constant pgm_height : integer := const_imageheight;
constant max_pixel_value : integer := 2**wordsize-1;
variable readheader: std_logic := '1';
begin
red_pixel_from_file <= red_pixel_tmp;
green_pixel_from_file <= green_pixel_tmp;
blue_pixel_from_file <= blue_pixel_tmp;
if rising_edge(tb_clk) then
if readheader = '1' then
read_pbmplus_header( pgm_width, pgm_height, max_pixel_value, ppm, file_input_pixel );
readheader := '0';
end if;
if tb_rst = '0' then
if tb_enable = '1' and end_of_file = '0' then
read_rgb_pixel(file_input_pixel, red_pixel_tmp, green_pixel_tmp, blue_pixel_tmp, end_of_file);
end if;
end if;
end if;
end process;
--===================process for writing output ===================================--
writing_output_file: process( tb_clk )
constant pgm_width : integer := const_imagewidth;
constant pgm_height : integer := const_imageheight;
constant max_pixel_value : integer := 2**wordsize-1;
variable writeheader: std_logic := '1';
variable r_val: integer := 0;
variable g_val: integer := 0;
variable b_val: integer := 0;
begin
if rising_edge(tb_clk) then
if writeheader = '1' then
write_pbmplus_header( pgm_width, pgm_height, max_pixel_value, ppm, file_output_pixel );
writeheader := '0';
end if;
if tb_enable = '1' and tb_rst = '0' and dut_data_valid = '1' then
-- write output image
r_val := to_integer(unsigned(red_pixel_to_file));
g_val := to_integer(unsigned(green_pixel_to_file));
b_val := to_integer(unsigned(blue_pixel_to_file));
write_rgb_pixel( r_val, g_val, b_val, file_output_pixel);
end if;
end if;
end process;
--=================== process for pixel counts ===================================--
h_and_v_counters: process( tb_clk )
constant pgm_width : integer := const_imagewidth;
constant pgm_height : integer := const_imageheight;
variable h_count_var : integer range 0 to const_imagewidth := 0;
variable v_count_var : integer range 0 to const_imageheight := 0;
begin
if rising_edge(tb_clk) then
if tb_enable = '1' and tb_rst = '0' then
if h_count_var < const_imagewidth-1 then
h_count_var := h_count_var + 1;
else
h_count_var := 0;
if v_count_var < const_imageheight-1 then
v_count_var := v_count_var + 1;
else
v_count_var := 0;
end if;
end if;
h_count <= std_logic_vector(to_unsigned(h_count_var, h_count_size));
v_count <= std_logic_vector(to_unsigned(v_count_var, v_count_size));
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
82c507701c8308331cc69ca6ffc1ed85
| 0.520231 | 4.036398 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 5/Parte 2 (TPC)/CombShiftUnit.vhd
| 1 | 1,225 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CombShiftUnit is
port( dataIn : in std_logic_vector(7 downto 0);
rotate : in std_logic;
dirLeft : in std_logic;
shArith : in std_logic;
shAmount : in std_logic_vector(2 downto 0);
dataOut : out std_logic_vector(7 downto 0));
end CombShiftUnit;
architecture Behavioral of CombShiftUnit is
signal s_shAmount : natural;
signal s_dataOut : std_logic_vector(7 downto 0);
begin
s_shAmount <= to_integer(unsigned(shAmount));
process(rotate, dirLeft, shAmount, shArith)
begin
if(rotate='1') then
s_dataOut <= dataIn;
if(dirLeft='1') then
dataOut <= s_dataOut(6 downto 0) & s_dataOut(7);
else
dataOut <= s_dataOut(0) & s_dataOut(7 downto 1);
end if;
elsif(shArith='1') then
if(dirLeft='1') then
dataOut <= std_logic_vector(shift_left(signed(dataIn), s_shAmount));
else
dataOut <= std_logic_vector(shift_right(signed(dataIn), s_shAmount));
end if;
else
if(dirLeft='1') then
dataOut <= std_logic_vector(shift_left(unsigned(dataIn), s_shAmount));
else
dataOut <= std_logic_vector(shift_right(unsigned(dataIn), s_shAmount));
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
c01b93e00b76c0b7cc75029feaffcfcb
| 0.68 | 2.951807 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/Alu4.vhd
| 1 | 821 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ALU4 is
port( a, b : in std_logic_vector(3 downto 0);
op : in std_logic_vector(2 downto 0);
r, m : out std_logic_vector(3 downto 0));
end ALU4;
architecture Behavioral of ALU4 is
signal s_a, s_b, s_r : unsigned(3 downto 0);
signal s_m : unsigned(7 downto 0);
begin
s_a <= unsigned(a);
s_b <= unsigned(b);
s_m <= s_a * s_b;
with op select
s_r <= (s_a + s_b) when "000",
(s_a - s_b) when "001",
s_m(3 downto 0) when "010",
(s_a / s_b) when "011",
s_a rem s_b when "100",
s_a and s_b when "101",
s_a or s_b when "110",
s_a xor s_b when "111";
r <= std_logic_vector(s_r);
m <= std_logic_vector(s_m(7 downto 4)) when (op = "010") else
(others => '0');
end Behavioral;
|
gpl-2.0
|
44db518f0c2312b744ace21e82daf037
| 0.565164 | 2.365994 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/Cozinha/CozinhaFSM.vhd
| 1 | 1,316 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity CozinhaFSM is
port( BS : in std_logic;
BC : in std_logic;
C : in std_logic;
S : in std_logic;
U : out std_logic;
D : out std_logic;
clk: in std_logic);
end CozinhaFSM;
architecture Behavioral of CozinhaFSM is
type Tstate is (S0, S1, S2);
signal pState, nState: Tstate;
signal s_u, s_d : std_logic;
begin
U <= s_u;
D <= s_d;
clk_process:process(clk)
begin
if(rising_edge(clk)) then
nState <= pState;
end if;
end process;
com_proc: process(pState, C, S, BC, BS)
begin
case pState is
when S0 =>
s_u<='1';
s_d<='0';
if(BS='1' and BS='1' and s_U/='1' and s_D/='1') then
nState <= S1;
elsif(C='1' or S='1') then
nState <= S2;
else
nState <= S0;
end if;
when S1 =>
s_u<='0';
s_d<='1';
if(BC='1' and C='1' and s_U/='1' and s_D/='1') then
nState <= S0;
elsif(C='1' or S='1') then
nState <= S2;
else
nState <= S1;
end if;
when S2 =>
s_u<='0';
s_d<='0';
if(BC='1' and C='1' and s_U/='1' and s_D/='1') then
nState <= S0;
elsif(BS='1' and BS='1' and s_U/='1' and s_D/='1') then
nState <= S1;
else
nState <= S2;
end if;
when others =>
s_u<='0';
s_d<='0';
nState <= S2;
end case;
end process;
end Behavioral;
|
gpl-2.0
|
16f3fa8c6fb6234644dca60f896357c0
| 0.531915 | 2.276817 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/RandomNumberw_counter_Tb.vhd
| 1 | 1,319 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RandomNumberw_counter_Tb is
end RandomNumberw_counter_Tb;
-- Testes unitários para a sincronização das entidade RandomNumber e counter9999
architecture Stimulus of RandomNumberw_counter_Tb is
signal s_reset, s_stop, s_clock, s_count, s_resetOut : std_logic;
signal s_random0, s_random3,s_random2,s_random1 : std_logic_vector(3 downto 0);
begin
uutrandom: entity work.RandomNumber(Behavioral)
port map(clock => s_clock,
stop_signal => s_stop,
reset => s_reset,
count => s_count,
resetOut => s_resetOut);
uutcounter: entity work.Counter9999(Behavioral)
port map(clk => s_clock,
reset => s_resetOut,
enable => s_count,
count0 => s_random0,
count1 => s_random1,
count2 => s_random2,
count3 => s_random3);
clk_proc:process
begin
s_clock <= '1';
wait for 13 ns;
s_clock <= '0';
wait for 13 ns;
end process;
comb_process:process
begin
s_stop <= '0';
s_reset <= '0';
wait for 50 ns;
s_stop <= '1';
wait for 25 ns;
s_stop <= '0';
wait for 25 ns;
s_reset <= '1';
wait for 25 ns;
end process;
end Stimulus;
|
gpl-2.0
|
18bebce1641e2bde3922615a9d19b916
| 0.614742 | 2.924444 | false | false | false | false |
spoorcc/realtimestagram
|
src/rgb2hsv.vhd
| 2 | 11,407 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
--============================================================================--
--! \class rgb2hsv
--! \brief Creates seperate Hue Saturation Value channels from rgb signal
--!
--! Hue
--! ---------------
--! The Hue indicates the degrees on the color circle. Starting at 0 degrees with red,
--! 120 degrees for green and 240 degrees for blue.
--! Because 360 degrees does map not correctly on the 8 bits of a byte everything is normalised
--! to the full range of a byte
--! Hue is calculated following the function:
--! \f[H =\left\{\begin{matrix} 0, & R=G=B\\
--! \frac{(G-B)*60^{\circ}}{max(R,G,B)-min(R,G,B)}\textup{mod}\:360^{\circ}, & R \geq G,B\\
--! \frac{(B-R)*60^{\circ}}{max(R,G,B)-min(R,G,B)}+120^{\circ}, & G \geq R,B\\
--! \frac{(R-G)*60^{\circ}}{max(R,G,B)-min(R,G,B)}+240^{\circ} & B \geq R,G \\
--! \end{matrix}\right.\f]
--!
--! Saturation
--! ----------------------
--! The saturation indicates the strength of the color.
--! Saturation is calculated following the function:
--! \f[S =\left\{\begin{matrix} 0, & max(R,G,B)=0 \\
--! \frac{max(R,G,B)-min(R,G,B)}{max(R,G,B)}, & otherwise\\
--! \end{matrix}\right.\f]
--!
--! Value
--! ----------------------
--! The value indicates the intensity of the pixel.
--! Value is calculated using the following function:
--! \f[ V = max(R,G,B)\f]
--!
entity rgb2hsv is
generic (
wordsize: integer := 8 --! input image wordsize in bits
);
port (
-- inputs
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
pixel_red_i: in std_logic_vector((wordsize-1) downto 0); --! red input pixel
pixel_green_i: in std_logic_vector((wordsize-1) downto 0); --! green input pixel
pixel_blue_i: in std_logic_vector((wordsize-1) downto 0); --! blue input pixel
-- outputs
pixel_hue_o: out std_logic_vector((wordsize-1) downto 0); --! hue value of pixel
pixel_sat_o: out std_logic_vector((wordsize-1) downto 0); --! saturation of pixel
pixel_val_o: out std_logic_vector((wordsize-1) downto 0) --! value of pixel
);
type mux_select_delay is array(0 to 4) of integer range 0 to 2;
type max_delay is array(0 to 2) of integer range 0 to 2**wordsize;
constant c_60_degrees : integer := integer(round(real( 60)/real(360) * real(2**wordsize)));
constant c_120_degrees : integer := integer(round(real(120)/real(360) * real(2**wordsize)));
constant c_240_degrees : integer := integer(round(real(240)/real(360) * real(2**wordsize)));
end entity;
--============================================================================--
architecture behavioural of rgb2hsv is
-- signal declarations
signal rgdiff: integer range -2**wordsize to 2**wordsize; --! Difference between Red and Green input pixel
signal brdiff: integer range -2**wordsize to 2**wordsize; --! Difference between Blue and Red input pixel
signal gbdiff: integer range -2**wordsize to 2**wordsize; --! Difference between Green and Blue input pixel
signal c_rgdiff: integer range -2**wordsize * c_60_degrees to 2**wordsize * c_60_degrees; --! rg_diff * 60 degrees
signal c_brdiff: integer range -2**wordsize * c_60_degrees to 2**wordsize * c_60_degrees; --! br_diff * 60 degrees
signal c_gbdiff: integer range -2**wordsize * c_60_degrees to 2**wordsize * c_60_degrees; --! gb_diff * 60 degrees
signal c_rgdiff_d0: integer range -2**wordsize * c_60_degrees to 2**wordsize * c_60_degrees; --! delayed c_rgdiff
signal c_brdiff_d0: integer range -2**wordsize * c_60_degrees to 2**wordsize * c_60_degrees; --! delayed c_brdiff
signal c_gbdiff_d0: integer range -2**wordsize * c_60_degrees to 2**wordsize * c_60_degrees; --! delayed c_gbdiff
signal c_rgdiff_div_max: integer range -2**wordsize to 2**wordsize; --! delayed c_rgdiff divided by max
signal c_brdiff_div_max: integer range -2**wordsize to 2**wordsize; --! delayed c_brdiff divided by max
signal c_gbdiff_div_max: integer range -2**wordsize to 2**wordsize; --! delayed c_gbdiff divided by max
signal rg_mux_in: integer range -2**wordsize to 2**wordsize;
signal br_mux_in: integer range -2**wordsize to 2**wordsize;
signal gb_mux_in: integer range -2**wordsize to 2**wordsize;
signal mux_select: mux_select_delay;
-- comparator
signal r_versus_g_max: integer range 0 to 2**wordsize;
signal r_versus_g_min: integer range 0 to 2**wordsize;
signal blue_pix_delay: integer range 0 to 2**wordsize;
signal b_versus_max: integer range 0 to 2**wordsize;
signal b_versus_min: integer range 0 to 2**wordsize;
signal max_min_min: integer range 0 to 2**wordsize;
signal range_times_255: integer range 0 to 2**wordsize * 255;
signal range_255_div_by_max: integer range 0 to 2**wordsize;
signal comp_max: max_delay;
begin
hsv2rgb : process(clk, rst)
variable red_i_int : integer range 0 to 2**wordsize := 0;
variable green_i_int : integer range 0 to 2**wordsize := 0;
variable blue_i_int : integer range 0 to 2**wordsize := 0;
variable sat_out : std_logic_vector(wordsize-1 downto 0) := (others => '0');
variable mux_out : std_logic_vector(wordsize-1 downto 0) := (others => '0');
begin
if rst = '1' then
rgdiff <= 0;
brdiff <= 0;
gbdiff <= 0;
c_rgdiff <= 0;
c_brdiff <= 0;
c_gbdiff <= 0;
c_rgdiff_d0 <= 0;
c_brdiff_d0 <= 0;
c_gbdiff_d0 <= 0;
c_rgdiff_div_max <= 0;
c_brdiff_div_max <= 0;
c_gbdiff_div_max <= 0;
rg_mux_in <= 0;
br_mux_in <= 0;
gb_mux_in <= 0;
mux_select <= (others => 0);
r_versus_g_max <= 0;
r_versus_g_min <= 0;
b_versus_max <= 0;
b_versus_min <= 0;
range_times_255 <= 0;
range_255_div_by_max <= 0;
comp_max <= (others => 0);
elsif rising_edge(clk) then
if enable = '1' then
red_i_int := to_integer(unsigned(pixel_red_i));
green_i_int := to_integer(unsigned(pixel_green_i));
blue_i_int := to_integer(unsigned(pixel_blue_i));
-- First stage of comparison
if red_i_int >= green_i_int then
r_versus_g_max <= red_i_int;
r_versus_g_min <= green_i_int;
mux_select(0) <= 0;
else
r_versus_g_max <= green_i_int;
r_versus_g_min <= red_i_int;
mux_select(0) <= 1;
end if;
blue_pix_delay <= blue_i_int;
-- Second stage of comparison
if r_versus_g_max < blue_pix_delay then
b_versus_max <= blue_pix_delay;
mux_select(1) <= 2;
else
b_versus_max <= r_versus_g_max;
mux_select(1) <= mux_select(0);
end if;
if r_versus_g_min > blue_pix_delay then
b_versus_min <= blue_pix_delay;
else
b_versus_min <= r_versus_g_min;
end if;
comp_max(0) <= b_versus_max;
comp_max(1 to 2) <= comp_max(0 to 1);
max_min_min <= b_versus_max - b_versus_min;
-- Hue calculation
gbdiff <= (green_i_int - blue_i_int);
brdiff <= (blue_i_int - red_i_int);
rgdiff <= (red_i_int - green_i_int);
c_gbdiff <= c_60_degrees * gbdiff;
c_brdiff <= c_60_degrees * brdiff;
c_rgdiff <= c_60_degrees * rgdiff;
c_gbdiff_d0 <= c_gbdiff;
c_brdiff_d0 <= c_brdiff;
c_rgdiff_d0 <= c_rgdiff;
if max_min_min /= 0 then
c_gbdiff_div_max <= (c_gbdiff_d0 / max_min_min) mod 2**wordsize;
c_brdiff_div_max <= (c_brdiff_d0 / max_min_min);
c_rgdiff_div_max <= (c_rgdiff_d0 / max_min_min);
else
c_gbdiff_div_max <= 0;
c_brdiff_div_max <= 0;
c_rgdiff_div_max <= 0;
end if;
gb_mux_in <= c_gbdiff_div_max;
br_mux_in <= (c_120_degrees + c_brdiff_div_max);
rg_mux_in <= (c_240_degrees + c_rgdiff_div_max);
-- mux delay
mux_select(2 to 4) <= mux_select(1 to 3);
-- mux
if mux_select(4) = 0 then
mux_out := std_logic_vector(to_unsigned(gb_mux_in, wordsize));
elsif mux_select(4) = 1 then
mux_out := std_logic_vector(to_unsigned(br_mux_in, wordsize));
else
mux_out := std_logic_vector(to_unsigned(rg_mux_in, wordsize));
end if;
pixel_hue_o <= mux_out(wordsize-1 downto 0);
-- Saturation calculation
range_times_255 <= max_min_min * 255;
if comp_max(1) /= 0 then
range_255_div_by_max <= ((range_times_255 / comp_max(1)) mod 2**wordsize);
else
range_255_div_by_max <= 0;
end if;
sat_out := std_logic_vector(to_unsigned(range_255_div_by_max, wordsize));
pixel_sat_o <= sat_out;
-- Value calculation
pixel_val_o <= std_logic_vector(to_unsigned(comp_max(2), wordsize));
else
pixel_hue_o <= (others => '0');
pixel_sat_o <= (others => '0');
pixel_val_o <= (others => '0');
end if; -- end if enable = '1'
end if; -- end if rst = '1'
end process;
end architecture;
--============================================================================--
|
gpl-2.0
|
1d0b6e96b6b91f01b78f4b467df9ee30
| 0.518015 | 3.709593 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 3/blink.vhd
| 1 | 1,317 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity blink is
port( binIn : in std_logic_vector(6 downto 0);
binOut: out std_logic_vector(6 downto 0);
clk : in std_logic;
reset : in std_logic;
outLed: out std_logic);
end blink;
architecture Behavioral of blink is
signal last_binIn : std_logic_vector(6 downto 0);
signal counter : natural;
begin
process(clk, reset)
begin
if(reset='1') then
counter <= 0;
last_binIn <= "0000000";
elsif(rising_edge(clk)) then
outLed <= '1';
if(last_binIn= "1100011" and not (binIn="1100011"))then
outLed <= '0';
if(counter=8 or counter=10 or counter=12) then
binOut <=(others => '1');
counter <= counter+1;
elsif(counter=7 or counter=9 or counter=11 or counter=13) then
binOut <= "1111110";
counter <= counter+1;
else
binOut <=(others => '1');
counter <= 0;
end if;
else
if(not(last_binIn = binIn)) then
last_binIn <= binIn;
counter <=0;
end if;
if(counter=1 or counter=3 or counter=5) then
binOut <=(others => '1');
counter <= counter+1;
elsif(counter=0 or counter=2 or counter=4 or counter=6) then
binOut <= binIn;
counter <= counter+1;
else
binOut <=(others => '1');
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
a97c099535d7c39df7266f5814f8500c
| 0.609719 | 2.946309 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
VGA-PS2_Cursor/dcm_40mhz.vhd
| 1 | 2,809 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm_40mhz.vhd
-- /___/ /\ Timestamp : 04/07/2013 16:27:16
-- \ \ / \
-- \___\/\___\
--
-- Design Name: dcm_40mhz
-- Device: xc3s100e-5cp132
--
-- Module dcm_40mhz
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dcm_40mhz is
port (
CLKIN_IN : in std_logic;
CLKDV_OUT : out std_logic;
-- CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic
);
end dcm_40mhz;
architecture behavioral of dcm_40mhz is
signal CLKDV_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
-- CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKDV_BUFG_INST : BUFG
port map (
I=>CLKDV_BUF,
O=>CLKDV_OUT
);
CLKIN_IBUFG_INST : IBUFG
port map (
I=>CLKIN_IN,
O=>CLKIN_IBUFG
);
CLK0_BUFG_INST : BUFG
port map (
I=>CLK0_BUF,
O=>CLKFB_IN
);
DCM_SP_INST : DCM_SP
generic map (
CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.5,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (
CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>CLKDV_BUF,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open
);
end behavioral;
|
gpl-3.0
|
b6bd16cf8e19f30c0627401c872d4f62
| 0.442862 | 3.806233 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 3/Bin2BCDDecoder.vhd
| 1 | 1,279 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin2BCDDecoder is
port( inBin : in std_logic_vector (6 downto 0);
outBCD: out std_logic_vector(3 downto 0);
outBCD2:out std_logic_vector(3 downto 0));
end Bin2BCDDecoder;
architecture Behavioral of Bin2BCDDecoder is
signal n,l,m : natural;
begin
n <= to_integer(unsigned(inBin));
outBCD2 <= "1110" when (inBin="1111110") else
"0000" when n<10 else
"0001" when n<20 else
"0010" when n<30 else
"0011" when n<40 else
"0100" when n<50 else
"0101" when n<60 else
"0110" when n<70 else
"0111" when n<80 else
"1000" when n<90 else
"1001" when n<100 else
"1111";
l <= 0 when n<10 else
10 when n<20 else
20 when n<30 else
30 when n<40 else
40 when n<50 else
50 when n<60 else
60 when n<70 else
70 when n<80 else
80 when n<90 else
90;
m <= n-l;
outBCD <= "1110" when (inBin="1111110") else
"0000" when m=0 else
"0001" when m=1 else
"0010" when m=2 else
"0011" when m=3 else
"0100" when m=4 else
"0101" when m=5 else
"0110" when m=6 else
"0111" when m=7 else
"1000" when m=8 else
"1001" when m=9 else
"1111";
end Behavioral;
|
gpl-2.0
|
91ee68252c8edca2633507d4c5be626f
| 0.599687 | 2.768398 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 8/Parte 1/SeqDetFSM.vhd
| 1 | 1,912 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqDetFSM is
port( xin : in std_logic;
yout : out std_logic;
clk : in std_logic
);
end SeqDetFSM;
architecture MealyArch of SeqDetFSM is
type Tstate is (S0, S1, S2, S3);
signal pState, nState : Tstate;
begin
clkproc: process(clk)
begin
if(rising_edge(clk)) then
pState <= nState;
end if;
end process;
combProcess: process(xin, pState)
begin
yout <= '0';
case pState is
when S0=>
if(xin='1') then
nState <= S1;
else
nState <= S0;
end if;
when S1=>
if(xin='1') then
nState <= S1;
else
nState <= S2;
end if;
when S2=>
if(xin='1') then
nState <= S3;
else
nState <= S0;
end if;
when S3=>
if(xin='1') then
nState <= S1;
yout <= '1';
else
nState <= S2;
end if;
when others =>
nState <= S0;
end case;
end process;
end MealyArch;
architecture MooreArch of SeqDetFSM is
type Tstate is (S0, S1, S2, S3, S4, S5);
signal pState, nState : Tstate;
begin
clkproc: process(clk)
begin
if(rising_edge(clk)) then
pState <= nState;
end if;
end process;
combProcess: process(xin, pState)
begin
yout <= '0';
case pState is
when S0=>
if(Xin='1') then
nState <= S1;
else
nState <= S5;
end if;
when S1 =>
if(Xin='1') then
nState <= S1;
else
nState <= S2;
end if;
when S2 =>
if(Xin='1') then
nState <= S3;
else
nState <= S5;
end if;
when S3 =>
if(Xin='1') then
nState <= S4;
else
nState <= S2;
end if;
when S4 =>
yout <= '1';
if(Xin='1') then
nState <= S1;
else
nState <= S2;
end if;
when S5 =>
if(Xin='1') then
nState <= S1;
else
nState <= S5;
end if;
when others =>
nState <= S0;
end case;
end process;
end MooreArch;
|
gpl-2.0
|
0e1ee6c2884d6782430c6f8883791f91
| 0.536088 | 2.637241 | false | false | false | false |
tejainece/VHDLExperiments
|
Multiply16Booth4/BoothPartProdGen.vhd
| 3 | 1,465 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:00:36 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity BoothPartProdGen is
PORT (
bin3: in STD_LOGIC_VECTOR(2 downto 0);
a: in STD_LOGIC_VECTOR(15 downto 0);
product: out STD_LOGIC_VECTOR(16 downto 0)
);
end BoothPartProdGen;
architecture Behavioral of BoothPartProdGen is
constant ONE17: STD_LOGIC_VECTOR(16 downto 0) := "00000000000000001";
begin
PROCESS(bin3, a)
BEGIN
if bin3 = "001" or bin3 = "010" then -- * 1
product <= "0" & a;
elsif bin3 = "011" then -- * 2
product <= a & '0';
elsif bin3 = "101" or bin3 = "110" then -- * -1
product <= std_logic_vector(unsigned(not('0' & a)) + unsigned(ONE17));
elsif bin3 = "100" then -- * -2
product <= std_logic_vector(unsigned(not(a & '0')) + unsigned(ONE17));
else
product <= "00000000000000000";
end if;
END PROCESS;
end Behavioral;
|
gpl-3.0
|
8736df7df6cb95845f0efdea948fbefe
| 0.585666 | 3.547215 | false | false | false | false |
vinodpa/openPowerlink-FPGA
|
Examples/ipcore/common/powerlink/src/powerlink.vhd
| 3 | 45,374 |
-------------------------------------------------------------------------------
-- POWERLINK IP-Core
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.global.all;
entity powerlink is
generic(
-- GENERAL GENERICS --
endian_g : string := "little";
genOnePdiClkDomain_g : integer := 0;
genPdi_g : integer := 1;
genInternalAp_g : integer := 1;
genSimpleIO_g : integer := 0;
genSpiAp_g : integer := 0;
-- OPENMAC GENERICS
Simulate : integer := 0;
iBufSize_g : integer := 1024;
iBufSizeLOG2_g : integer := 10;
useRmii_g : integer := 1; --use Rmii
useIntPacketBuf_g : integer := 1; --internal packet buffer
useRxIntPacketBuf_g : integer := 1; --rx buffer located in internal packet buffer
use2ndCmpTimer_g : integer := 1; --use second cmp timer (used in PDI)
usePulse2ndCmpTimer_g : integer := 1; --use second cmp timer with pulse support
pulseWidth2ndCmpTimer_g : integer := 9;
use2ndPhy_g : integer := 1; --use second phy (introduces openHUB)
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : integer := 1; --hold burst value during transfer
m_tx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g
m_rx_burst_size_g : integer := 16; --0 < x =< 2**m_burstcount_width_g
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_data_width_g : integer := 16;
gen_dma_observer_g : integer := 1;
genSmiIO : integer := 1; --drive SMI IO if true
gNumSmi : integer range 1 to 2 := 2; --number of SMI used
-- PDI GENERICS
iRpdos_g : integer := 3;
iTpdos_g : integer := 1;
genABuf1_g : integer := 1; --if 0 iABuf1_g must be set to 0!
genABuf2_g : integer := 1; --if 0 iABuf2_g must be set to 0!
genLedGadget_g : integer := 0;
genTimeSync_g : integer := 0;
genEvent_g : integer := 0;
--PDO buffer size *3
iTpdoBufSize_g : integer := 100;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
--asynchronous buffer size
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iPdiRev_g : integer := 16#55AA#;
pcpSysId : integer := 1;
-- 8/16bit PARALLEL PDI GENERICS
papDataWidth_g : integer := 8;
papLowAct_g : integer := 0;
papBigEnd_g : integer := 0;
-- SPI GENERICS
spiCPOL_g : integer := 0;
spiCPHA_g : integer := 0;
spiBigEnd_g : integer := 0;
-- PORTIO
pioValLen_g : integer := 50; --clock ticks of pcp_clk
-- GENERAL TARGET DEPENDINGS
genIoBuf_g : integer := 1 --generates IO buffers
);
port(
-- CLOCK / RESET PORTS
clk50 : in std_logic; --RMII clk
rst : in std_logic; --general reset
clkEth : in std_logic; --Tx Reg clk
m_clk : in std_logic; --openMAC DMA master clock
pkt_clk : in std_logic; --openMAC packet buffer clock (don't use pcp..)
clkPcp : in std_logic; --pcp clk
clkAp : in std_logic; --ap clk
rstPcp : in std_logic; --rst from pcp side
rstAp : in std_logic; --rst ap
-- OPENMAC
--- OPENMAC PORTS
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_byteenable : in std_logic_vector(1 downto 0);
mac_address : in std_logic_vector(11 downto 0);
mac_writedata : in std_logic_vector(15 downto 0);
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mac_irq : out std_logic := '0';
--- TIMER COMPARE PORTS
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_address : in std_logic_vector(1 downto 0);
tcp_writedata : in std_logic_vector(31 downto 0);
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
tcp_irq : out std_logic := '0';
--- MAC BUFFER PORTS
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_writedata : in std_logic_vector(31 downto 0);
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
--- OPENMAC DMA PORTS
m_read : OUT STD_LOGIC := '0';
m_write : OUT STD_LOGIC := '0';
m_byteenable : OUT STD_LOGIC_VECTOR(m_data_width_g/8-1 DOWNTO 0) := (others => '0');
m_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
m_writedata : OUT STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0');
m_readdata : IN STD_LOGIC_VECTOR(m_data_width_g-1 DOWNTO 0) := (others => '0');
m_waitrequest : IN STD_LOGIC;
m_readdatavalid : in STD_LOGIC := '0';
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
-- PDI
--- PCP PORTS
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_address : in std_logic_vector(12 downto 0);
pcp_writedata : in std_logic_vector(31 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
--- AP PORTS
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
---- AVALON
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_byteenable : in std_logic_vector(3 downto 0);
ap_address : in std_logic_vector(12 downto 0);
ap_writedata : in std_logic_vector(31 downto 0);
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_waitrequest : out std_logic;
---- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs_n : in std_logic;
pap_rd_n : in std_logic;
pap_wr_n : in std_logic;
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
---- SPI
spi_clk : in std_logic;
spi_sel_n : in std_logic;
spi_mosi : in std_logic;
spi_miso : out std_logic := '0';
---- simple I/O
smp_address : in std_logic;
smp_read : in std_logic;
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
smp_byteenable : in std_logic_vector(3 downto 0);
smp_waitrequest : out std_logic;
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0');
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
pio_operational : out std_logic := '0';
-- EXTERNAL
--- PHY MANAGEMENT
---- shared (valid if gNumSmi = 1)
phy_SMIClk : out std_logic := '0';
phy_SMIDat : inout std_logic := '1';
phy_SMIDat_I : in std_logic := '1';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
phy_Rst_n : out std_logic := '1';
---- PHY0 (valid if gNumSmi = 2)
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat : inout std_logic := '1';
phy0_SMIDat_I : in std_logic := '1';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_link : in std_logic := '0';
---- PHY1 (valid if gNumSmi = 2)
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat : inout std_logic := '1';
phy1_SMIDat_I : in std_logic := '1';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_Rst_n : out std_logic := '1';
phy1_link : in std_logic := '0';
--- RMII PORTS
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
--- MII PORTS
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
--- LEDs
led_error : out std_logic := '0';
led_status : out std_logic := '0';
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_gpo : out std_logic_vector(7 downto 0) := (others => '0')
);
end powerlink;
architecture rtl of powerlink is
signal smi_Clk : std_logic := '0';
signal smi_Di : std_logic := '0';
signal smi_Do : std_logic := '0';
signal smi_Doe : std_logic := '0';
signal phy_nResetOut : std_logic := '0';
signal irqToggle : std_logic := '0';
signal ap_chipselect_s : std_logic := '0';
signal ap_read_s : std_logic := '0';
signal ap_write_s : std_logic := '0';
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range) := (others => '0');
signal ap_address_s : std_logic_vector(ap_address'range) := (others => '0');
signal ap_writedata_s : std_logic_vector(ap_writedata'range):= (others => '0');
signal ap_readdata_s : std_logic_vector(ap_readdata'range) := (others => '0');
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic;
signal pap_wr_s : std_logic;
signal pap_be_s : std_logic_vector(pap_be'range);
signal pap_ack_s : std_logic;
signal ap_irq_s : std_logic;
signal ap_asyncIrq_s : std_logic;
signal spi_sel_s : std_logic;
signal spi_sel_s1 : std_logic;
signal spi_sel_s2 : std_logic;
signal spi_clk_s : std_logic;
signal spi_clk_s1 : std_logic;
signal spi_clk_s2 : std_logic;
signal spi_mosi_s : std_logic;
signal spi_mosi_s1 : std_logic;
signal spi_mosi_s2 : std_logic;
signal phyLink, phyAct : std_logic_vector(1 downto 0);
signal led_s : std_logic_vector(15 downto 0);
signal clkAp_s, rstAp_s : std_logic;
--PDI change buffer triggers for hw acc to pdi
signal rpdo_change_tog : std_logic_vector(2 downto 0);
signal tpdo_change_tog : std_logic;
begin
--general signals
clkAp_s <= clkAp when integerToBoolean(genOnePdiClkDomain_g) = false else clkPcp;
rstAp_s <= rstAp when integerToBoolean(genOnePdiClkDomain_g) = false else rstPcp;
phyLink <= phy1_link & phy0_link;
--LEDs: GPO7, ..., GPO0, O1, O0, PA1, PL1, PA0, PL0, E, S
led_error <= led_s(1);
led_status <= led_s(0);
led_phyLink <= led_s(4) & led_s(2);
led_phyAct <= led_s(5) & led_s(3);
led_opt <= led_s(7) & led_s(6);
led_gpo <= led_s(15 downto 8);
------------------------------------------------------------------------------------------------------------------------
--PCP + AP
genPdi : if integerToBoolean(genPdi_g) and integerToBoolean(genInternalAp_g) and not integerToBoolean(genSpiAp_g) generate
--sync and async interrupt are driven by only one line
-- this gives some effort for Nios II AP ;)
ap_irq <= ap_irq_s or ap_asyncIrq_s;
-- added by mairt (2.3.2012)
-- microblaze can handle 2 interrupts
ap_syncIrq <= ap_irq_s;
ap_syncIrq_n <= not ap_irq_s;
ap_asyncIrq <= ap_asyncIrq_s;
ap_asyncIrq_n <= not ap_asyncIrq_s;
theAvalonPdi : entity work.pdi
generic map (
genOnePdiClkDomain_g => integerToBoolean(genOnePdiClkDomain_g),
iPdiRev_g => iPdiRev_g,
pcpSysId => pcpSysId,
iRpdos_g => iRpdos_g,
iTpdos_g => iTpdos_g,
genABuf1_g => integerToBoolean(genABuf1_g),
genABuf2_g => integerToBoolean(genABuf2_g),
genLedGadget_g => integerToBoolean(genLedGadget_g),
genTimeSync_g => integerToBoolean(genTimeSync_g),
genEvent_g => integerToBoolean(genEvent_g),
--PDO buffer size *3
iTpdoBufSize_g => iTpdoBufSize_g,
iRpdo0BufSize_g => iRpdo0BufSize_g,
iRpdo1BufSize_g => iRpdo1BufSize_g,
iRpdo2BufSize_g => iRpdo2BufSize_g,
--asynchronous buffer size
iABuf1_g => iAsyBuf1Size_g,
iABuf2_g => iAsyBuf2Size_g
)
port map (
pcp_reset => rstPcp,
pcp_clk => clkPcp,
ap_reset => rstAp_s,
ap_clk => clkAp_s,
-- Avalon Slave Interface for PCP
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_write => pcp_write,
pcp_byteenable => pcp_byteenable,
pcp_address => pcp_address,
pcp_writedata => pcp_writedata,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_irq => irqToggle,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect,
ap_read => ap_read,
ap_write => ap_write,
ap_byteenable => ap_byteenable,
ap_address => ap_address,
ap_writedata => ap_writedata,
ap_readdata => ap_readdata,
ap_waitrequest => ap_waitrequest,
ap_irq => ap_irq_s,
-- async interrupt
ap_asyncIrq => ap_asyncIrq_s,
-- LED
ledsOut => led_s,
phyLink => phyLink,
phyAct => phyAct,
--PDI change buffer triggers
rpdo_change_tog => rpdo_change_tog,
tpdo_change_tog => tpdo_change_tog
);
end generate genPdi;
--AP is external connected via parallel interface
genPdiPar : if integerToBoolean(genPdi_g) and not integerToBoolean(genInternalAp_g) and not integerToBoolean(genSpiAp_g) generate
--only 8 or 16bit data width is allowed
ASSERT ( papDataWidth_g = 8 or papDataWidth_g = 16 )
REPORT "External parallel port only allows 8 or 16bit data width!"
severity failure;
-------------------------------------------------------------------------------------
--convert active low signals to active high - respectively assign active high signals
theActiveLowGen : if integerToBoolean(papLowAct_g) generate
pap_wr_s <= not pap_wr_n;
pap_rd_s <= not pap_rd_n;
pap_cs_s <= not pap_cs_n;
pap_be_s <= not pap_be_n;
end generate;
theActiveHighGen : if not integerToBoolean(papLowAct_g) generate
pap_wr_s <= pap_wr;
pap_rd_s <= pap_rd;
pap_cs_s <= pap_cs;
pap_be_s <= pap_be;
end generate;
ap_syncIrq <= ap_irq_s;
ap_syncIrq_n <= not ap_irq_s;
ap_asyncIrq <= ap_asyncIrq_s;
ap_asyncIrq_n <= not ap_asyncIrq_s;
pap_ack <= pap_ack_s;
pap_ack_n <= not pap_ack_s;
--
-------------------------------------------------------------------------------------
theParPort : entity work.pdi_par
generic map (
papDataWidth_g => papDataWidth_g,
papBigEnd_g => integerToBoolean(papBigEnd_g),
papGenIoBuf_g => integerToBoolean(genIoBuf_g)
)
port map (
-- 8/16bit parallel
pap_cs => pap_cs_s,
pap_rd => pap_rd_s,
pap_wr => pap_wr_s,
pap_be => pap_be_s,
pap_addr => pap_addr,
pap_data => pap_data,
pap_data_I => pap_data_I,
pap_data_O => pap_data_O,
pap_data_T => pap_data_T,
pap_ack => pap_ack_s,
pap_gpio => pap_gpio,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
-- clock for AP side
ap_reset => rstPcp,
ap_clk => clk50,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect_s,
ap_read => ap_read_s,
ap_write => ap_write_s,
ap_byteenable => ap_byteenable_s,
ap_address => ap_address_s,
ap_writedata => ap_writedata_s,
ap_readdata => ap_readdata_s
);
thePdi : entity work.pdi
generic map (
genOnePdiClkDomain_g => integerToBoolean(genOnePdiClkDomain_g),
iPdiRev_g => iPdiRev_g,
pcpSysId => pcpSysId,
iRpdos_g => iRpdos_g,
iTpdos_g => iTpdos_g,
genABuf1_g => integerToBoolean(genABuf1_g),
genABuf2_g => integerToBoolean(genABuf2_g),
genLedGadget_g => integerToBoolean(genLedGadget_g),
genTimeSync_g => integerToBoolean(genTimeSync_g),
genEvent_g => integerToBoolean(genEvent_g),
--PDO buffer size *3
iTpdoBufSize_g => iTpdoBufSize_g,
iRpdo0BufSize_g => iRpdo0BufSize_g,
iRpdo1BufSize_g => iRpdo1BufSize_g,
iRpdo2BufSize_g => iRpdo2BufSize_g,
--asynchronous buffer size
iABuf1_g => iAsyBuf1Size_g,
iABuf2_g => iAsyBuf2Size_g
)
port map (
pcp_reset => rstPcp,
pcp_clk => clkPcp,
ap_reset => rst,
ap_clk => clk50,
-- Avalon Slave Interface for PCP
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_write => pcp_write,
pcp_byteenable => pcp_byteenable,
pcp_address => pcp_address,
pcp_writedata => pcp_writedata,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_irq => irqToggle,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect_s,
ap_read => ap_read_s,
ap_write => ap_write_s,
ap_byteenable => ap_byteenable_s,
ap_address => ap_address_s,
ap_writedata => ap_writedata_s,
ap_readdata => ap_readdata_s,
ap_waitrequest => open,
ap_irq => ap_irq_s,
-- async interrupt
ap_asyncIrq => ap_asyncIrq_s,
-- LED
ledsOut => led_s,
phyLink => phyLink,
phyAct => phyAct,
--PDI change buffer triggers
rpdo_change_tog => rpdo_change_tog,
tpdo_change_tog => tpdo_change_tog
);
end generate genPdiPar;
--AP is extern connected via SPI
genPdiSpi : if integerToBoolean(genPdi_g) and integerToBoolean(genSpiAp_g) generate
ap_syncIrq <= ap_irq_s;
ap_syncIrq_n <= not ap_irq_s;
ap_asyncIrq <= ap_asyncIrq_s;
ap_asyncIrq_n <= not ap_asyncIrq_s;
spi_clk_s <= spi_clk;
spi_sel_s <= not spi_sel_n;
spi_mosi_s <= spi_mosi;
theSyncProc : process(clk50, rst)
begin
if rst = '1' then
spi_sel_s1 <= '0';
spi_sel_s2 <= '0';
spi_clk_s1 <= '0';
spi_clk_s2 <= '0';
spi_mosi_s1 <= '0';
spi_mosi_s2 <= '0';
elsif clk50 = '1' and clk50'event then
spi_sel_s1 <= spi_sel_s;
spi_sel_s2 <= spi_sel_s1;
spi_clk_s1 <= spi_clk_s;
spi_clk_s2 <= spi_clk_s1;
spi_mosi_s1 <= spi_mosi_s;
spi_mosi_s2 <= spi_mosi_s1;
end if;
end process;
------------------------------------------------------------------------------------------------------------------------
thePdiSpi : entity work.pdi_spi
generic map (
spiSize_g => 8, --fixed value!
cpol_g => integerToBoolean(spiCPOL_g),
cpha_g => integerToBoolean(spiCPHA_g),
spiBigEnd_g => integerToBoolean(spiBigEnd_g)
)
port map (
-- SPI
spi_clk => spi_clk_s2,
spi_sel => spi_sel_s2,
spi_miso => spi_miso,
spi_mosi => spi_mosi_s2,
-- clock for AP side
ap_reset => rstPcp,
ap_clk => clk50,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect_s,
ap_read => ap_read_s,
ap_write => ap_write_s,
ap_byteenable => ap_byteenable_s,
ap_address => ap_address_s,
ap_writedata => ap_writedata_s,
ap_readdata => ap_readdata_s
);
thePdi : entity work.pdi
generic map (
genOnePdiClkDomain_g => integerToBoolean(genOnePdiClkDomain_g),
iPdiRev_g => iPdiRev_g,
pcpSysId => pcpSysId,
iRpdos_g => iRpdos_g,
iTpdos_g => iTpdos_g,
genABuf1_g => integerToBoolean(genABuf1_g),
genABuf2_g => integerToBoolean(genABuf2_g),
genLedGadget_g => integerToBoolean(genLedGadget_g),
genTimeSync_g => integerToBoolean(genTimeSync_g),
genEvent_g => integerToBoolean(genEvent_g),
--PDO buffer size *3
iTpdoBufSize_g => iTpdoBufSize_g,
iRpdo0BufSize_g => iRpdo0BufSize_g,
iRpdo1BufSize_g => iRpdo1BufSize_g,
iRpdo2BufSize_g => iRpdo2BufSize_g,
--asynchronous buffer size
iABuf1_g => iAsyBuf1Size_g,
iABuf2_g => iAsyBuf2Size_g
)
port map (
pcp_reset => rstPcp,
pcp_clk => clkPcp,
ap_reset => rst,
ap_clk => clk50,
-- Avalon Slave Interface for PCP
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_write => pcp_write,
pcp_byteenable => pcp_byteenable,
pcp_address => pcp_address,
pcp_writedata => pcp_writedata,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_irq => irqToggle,
-- Avalon Slave Interface for AP
ap_chipselect => ap_chipselect_s,
ap_read => ap_read_s,
ap_write => ap_write_s,
ap_byteenable => ap_byteenable_s,
ap_address => ap_address_s,
ap_writedata => ap_writedata_s,
ap_readdata => ap_readdata_s,
ap_waitrequest => open,
ap_irq => ap_irq_s,
-- async interrupt
ap_asyncIrq => ap_asyncIrq_s,
-- LED
ledsOut => led_s,
phyLink => phyLink,
phyAct => phyAct,
--PDI change buffer triggers
rpdo_change_tog => rpdo_change_tog,
tpdo_change_tog => tpdo_change_tog
);
end generate genPdiSpi;
--PDI is disabled (either simple I/O or openMAC only)
genNotPdi : if not integerToBoolean(genPdi_g) generate
-- directly forward toggle signal from 2nd CMP timer
ap_syncIrq <= irqToggle;
ap_syncIrq_n <= not irqToggle;
end generate genNotPdi;
--
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
--SIMPLE I/O CN
genSimpleIO : if integerToBoolean(genSimpleIO_g) generate
thePortIO : entity work.portio
generic map (
pioValLen_g => pioValLen_g,
pioGenIoBuf_g => integerToBoolean(genIoBuf_g)
)
port map (
s0_address => smp_address,
s0_read => smp_read,
s0_readdata => smp_readdata,
s0_write => smp_write,
s0_writedata => smp_writedata,
s0_byteenable => smp_byteenable,
s0_waitrequest => smp_waitrequest,
clk => clkPcp,
reset => rstPcp,
x_pconfig => pio_pconfig,
x_portInLatch => pio_portInLatch,
x_portOutValid => pio_portOutValid,
x_portio => pio_portio,
x_portio_I => pio_portio_I,
x_portio_O => pio_portio_O,
x_portio_T => pio_portio_T,
x_operational => pio_operational
);
end generate genSimpleIO;
--
------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------
--OPENMAC (OPENHUB, OPENFILTER, PHY MANAGEMENT)
theOpenMac : entity work.openMAC_Ethernet
generic map (
endian_g => endian_g,
dma_highadr_g => m_address'high,
gen2ndCmpTimer_g => integerToBoolean(use2ndCmpTimer_g),
genPulse2ndCmpTimer_g => integerToBoolean(usePulse2ndCmpTimer_g),
pulseWidth2ndCmpTimer_g => pulseWidth2ndCmpTimer_g,
genHub_g => integerToBoolean(use2ndPhy_g),
iPktBufSizeLog2_g => iBufSizeLOG2_g,
iPktBufSize_g => iBufSize_g,
simulate => integerToBoolean(simulate),
useIntPktBuf_g => integerToBoolean(useIntPacketBuf_g),
useRmii_g => integerToBoolean(useRmii_g),
useRxIntPktBuf_g => integerToBoolean(useRxIntPacketBuf_g),
m_burstcount_width_g => m_burstcount_width_g,
m_burstcount_const_g => integerToBoolean(m_burstcount_const_g),
m_data_width_g => m_data_width_g,
m_tx_fifo_size_g => m_tx_fifo_size_g,
m_rx_fifo_size_g => m_rx_fifo_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
m_rx_burst_size_g => m_rx_burst_size_g,
genSmiIO => integerToBoolean(genSmiIO),
gNumSmi => gNumSmi,
genPhyActLed_g => integerToBoolean(genLedGadget_g),
gen_dma_observer_g => integerToBoolean(gen_dma_observer_g)
)
port map(
clk => clk50,
clkx2 => clkEth,
pkt_clk => pkt_clk,
m_clk => m_clk,
rst => rst,
m_address => m_address,
m_burstcount => m_burstcount,
m_burstcounter => m_burstcounter,
m_byteenable => m_byteenable,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_write => m_write,
m_writedata => m_writedata,
m_waitrequest => m_waitrequest,
mac_rx_irq => open,
mac_tx_irq => open,
act_led => phyAct(0),
phy0_rst_n => phy0_Rst_n,
phy0_rx_dat => phy0_RxDat,
phy0_rx_dv => phy0_RxDv,
phy0_rx_err => phy0_RxErr,
phy0_smi_clk => phy0_SMICLK,
phy0_smi_dio => phy0_SMIDat,
phy0_smi_dio_I => phy0_SMIDat_I,
phy0_smi_dio_O => phy0_SMIDat_O,
phy0_smi_dio_T => phy0_SMIDat_T,
phy0_tx_dat => phy0_TxDat,
phy0_tx_en => phy0_TxEn,
phy1_rst_n => phy1_Rst_n,
phy1_rx_dat => phy1_RxDat,
phy1_rx_dv => phy1_RxDv,
phy1_rx_err => phy1_RxErr,
phy1_smi_clk => phy1_SMICLK,
phy1_smi_dio => phy1_SMIDat,
phy1_smi_dio_I => phy1_SMIDat_I,
phy1_smi_dio_O => phy1_SMIDat_O,
phy1_smi_dio_T => phy1_SMIDat_T,
phy1_tx_dat => phy1_TxDat,
phy1_tx_en => phy1_TxEn,
phyMii0_rx_clk => phyMii0_RxClk,
phyMii0_rx_dat => phyMii0_RxDat,
phyMii0_rx_dv => phyMii0_RxDv,
phyMii0_rx_err => phyMii0_RxEr,
phyMii0_tx_clk => phyMii0_TxClk,
phyMii0_tx_dat => phyMii0_TxDat,
phyMii0_tx_en => phyMii0_TxEn,
phyMii1_rx_clk => phyMii1_RxClk,
phyMii1_rx_dat => phyMii1_RxDat,
phyMii1_rx_dv => phyMii1_RxDv,
phyMii1_rx_err => phyMii1_RxEr,
phyMii1_tx_clk => phyMii1_TxClk,
phyMii1_tx_dat => phyMii1_TxDat,
phyMii1_tx_en => phyMii1_TxEn,
phy_rst_n => phy_Rst_n,
phy_smi_clk => phy_SMIClk,
phy_smi_dio_I => phy_SMIDat_I,
phy_smi_dio_O => phy_SMIDat_O,
phy_smi_dio_T => phy_SMIDat_T,
phy_smi_dio => phy_SMIDat,
pkt_address => mbf_address,
pkt_byteenable => mbf_byteenable,
pkt_chipselect => mbf_chipselect,
pkt_read => mbf_read,
pkt_readdata => mbf_readdata,
pkt_waitrequest => mbf_waitrequest,
pkt_write => mbf_write,
pkt_writedata => mbf_writedata,
s_address => mac_address,
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_irq => mac_irq,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata,
t_address => tcp_address,
t_byteenable => tcp_byteenable,
t_chipselect => tcp_chipselect,
t_irq => tcp_irq,
t_read => tcp_read,
t_readdata => tcp_readdata,
t_tog => irqToggle,
t_waitrequest => tcp_waitrequest,
t_write => tcp_write,
t_writedata => tcp_writedata
);
phyAct(1) <= phyAct(0);
--
------------------------------------------------------------------------------------------------------------------------
end rtl;
|
gpl-2.0
|
2dcc1a8675c9cc1e7de5258b49350aee
| 0.396438 | 4.707335 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/interruptgen/interruptgen.vhd
| 1 | 888 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interruptgen is
port(
I_clk: in std_logic := '0';
I_interrupt: in std_logic := '0';
O_interrupt: out std_logic := '0'
);
end interruptgen;
architecture Behavioral of interruptgen is
constant CYCLELENGTH: integer := 3000000;
signal act: boolean := false;
begin
-- generate interrupt signals if active
process(I_clk)
variable clockcnt: integer range 0 to CYCLELENGTH;
begin
if rising_edge(I_clk) then
O_interrupt <= '0';
if(clockcnt < (CYCLELENGTH / 30) and act) then
O_interrupt <= '1';
end if;
clockcnt := clockcnt + 1;
if(clockcnt >= CYCLELENGTH) then
clockcnt := 0;
end if;
end if;
end process;
-- toggle activity
process(I_interrupt)
begin
if rising_edge(I_interrupt) then
act <= not act;
end if;
end process;
end Behavioral;
|
mit
|
170c10e382423512e660e315fe30b183
| 0.661036 | 3.030717 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 1/LogicDemo.vhd
| 1 | 503 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LogicDemo is
port(LEDR : out std_logic_vector(5 downto 0);
SW : in std_logic_vector(1 downto 0));
end LogicDemo;
architecture Structural of LogicDemo is
begin
system_core : entity work.LogicUnit(Behavioral)
port map(input0 => SW(0),
input1 => SW(1),
invOut => LEDR(0),
andOut => LEDR(1),
orOut => LEDR(2),
xorOut => LEDR(3),
nandOut => LEDR(4),
norOut => LEDR(5));
end Structural;
|
gpl-2.0
|
0a2a39f730a7d4a0fb4a691c54fc1d87
| 0.604374 | 3.08589 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 4/Parte III/CounterUpDownN.vhd
| 1 | 650 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterUpDownN is
generic(N : positive :=4);
port( clk : in std_logic;
updown: in std_logic;
reset : in std_logic;
count : out std_logic_vector(n-1 downto 0));
end CounterUpDownN;
architecture Behavioral of CounterUpDownN is
signal s_count : unsigned (n-1 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset='1') then
s_count <= (others => '0');
elsif (updown = '1') then
s_count <= s_count + 1;
else
s_count <= s_count - 1;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;
|
gpl-2.0
|
f9108ea48f08dcd029ead18fa38f5597
| 0.653846 | 2.68595 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/attic/cpu_toplevel.vhd
| 1 | 6,645 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity cpu_toplevel is
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_reset: in std_logic;
I_memdata: in std_logic_vector(XLEN-1 downto 0);
I_membusy: in std_logic;
O_memdata: out std_logic_vector(XLEN-1 downto 0);
O_memaddr: out std_logic_vector(XLEN-1 downto 0);
O_memen: out std_logic := '0';
O_memwrite: out std_logic := '0'
);
end cpu_toplevel;
architecture Behavioral of cpu_toplevel is
component alu
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_fop: in std_logic_vector(7 downto 0);
I_imm: in std_logic_vector(XLEN-1 downto 0);
I_dataS1: in std_logic_vector(XLEN-1 downto 0);
I_dataS2: in std_logic_vector(XLEN-1 downto 0);
I_reset: in std_logic := '0';
O_alumemop: out std_logic_vector(2 downto 0);
O_busy: out std_logic;
O_data: out std_logic_vector(XLEN-1 downto 0);
O_PC: out std_logic_vector(XLEN-1 downto 0)
);
end component;
component control
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_reset: in std_logic;
I_memop: in std_logic;
I_regwrite: in std_logic;
I_alubusy: in std_logic;
I_membusy: in std_logic;
I_alumemop: in std_logic_vector(2 downto 0); -- from ALU
-- enable signals for components
O_decen: out std_logic;
O_aluen: out std_logic;
O_memen: out std_logic;
O_regen: out std_logic;
-- op selection for devices
O_regop: out std_logic_vector(1 downto 0);
O_memop: out std_logic_vector(2 downto 0);
O_mem_imem: out std_logic -- 1: operation on instruction memory, 0: on data memory
);
end component;
component decoder
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_instr: in std_logic_vector(31 downto 0);
O_rs1: out std_logic_vector(4 downto 0);
O_rs2: out std_logic_vector(4 downto 0);
O_rd: out std_logic_vector(4 downto 0);
O_imm: out std_logic_vector(31 downto 0);
O_fop: out std_logic_vector(7 downto 0);
O_regwrite : out std_logic;
O_memop: out std_logic
);
end component;
component mem
Port(
-- wired to CPU core
I_clk: in std_logic;
I_en: in std_logic;
I_op: in std_logic_vector(2 downto 0); -- memory opcodes
I_iaddr: in std_logic_vector(31 downto 0); -- instruction address, provided by PCU
I_daddr: in std_logic_vector(31 downto 0); -- data address, provided by ALU
I_data: in std_logic_vector(31 downto 0); -- data to be stored on write ops
I_mem_imem: in std_logic := '0'; -- denotes if instruction memory is accessed (signal from control unit)
O_data : out std_logic_vector(31 downto 0);
O_busy: out std_logic;
-- wired to outside world, RAM, devices etc.
O_memen: out std_logic := '0';
O_memaddr: out std_logic_vector(31 downto 0);
O_memdata: out std_logic_vector(31 downto 0);
I_memdata: in std_logic_vector(31 downto 0);
O_memwrite: out std_logic := '0';
I_membusy: in std_logic := '0'
);
end component;
component registers
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_op: in std_logic_vector(1 downto 0);
I_selS1: in std_logic_vector(4 downto 0);
I_selS2: in std_logic_vector(4 downto 0);
I_selD: in std_logic_vector(4 downto 0);
I_dataAlu: in std_logic_vector(XLEN-1 downto 0);
I_dataMem: in std_logic_vector(XLEN-1 downto 0);
O_dataS1: out std_logic_vector(XLEN-1 downto 0);
O_dataS2: out std_logic_vector(XLEN-1 downto 0)
);
end component;
signal alu_out: std_logic_vector(XLEN-1 downto 0);
signal alu_memop: std_logic_vector(2 downto 0) := MEMOP_READW;
signal alu_busy: std_logic := '0';
signal alu_pc: std_logic_vector(XLEN-1 downto 0);
signal ctrl_pcuen: std_logic := '0';
signal ctrl_decen: std_logic := '0';
signal ctrl_aluen: std_logic := '0';
signal ctrl_memen: std_logic := '0';
signal ctrl_regen: std_logic := '0';
signal ctrl_regop: std_logic_vector(1 downto 0) := REGOP_READ;
signal ctrl_pcuop: std_logic := '0';
signal ctrl_memop: std_logic_vector(2 downto 0) := MEMOP_READW;
signal ctrl_mem_imem: std_logic := '0';
signal ctrl_reset: std_logic := '0';
signal dec_fop: std_logic_vector(7 downto 0);
signal dec_memop: std_logic := '0';
signal dec_rs1: std_logic_vector(4 downto 0);
signal dec_rs2: std_logic_vector(4 downto 0);
signal dec_rd: std_logic_vector(4 downto 0);
signal dec_regwrite: std_logic := '0';
signal dec_imm: std_logic_vector(XLEN-1 downto 0);
signal inv_clk: std_logic;
signal mem_busy: std_logic := '0';
signal mem_data: std_logic_vector(XLEN-1 downto 0);
signal reg_dataS1: std_logic_vector(XLEN-1 downto 0);
signal reg_dataS2: std_logic_vector(XLEN-1 downto 0);
begin
-- inverted clock for control unit to ensure that all control
-- signals arive in time for the controlled units. Effectively
-- makes control unit work on falling edge, all other units on
-- rising edge
inv_clk <= not I_clk;
alu_instance: alu port map(
I_clk => I_clk,
I_en => ctrl_aluen,
I_fop => dec_fop,
I_imm => dec_imm,
I_reset => I_reset,
I_dataS1 => reg_dataS1,
I_dataS2 => reg_dataS2,
O_alumemop => alu_memop,
O_busy => alu_busy,
O_data => alu_out,
O_PC => alu_pc
);
ctrl_instance: control port map(
I_clk => inv_clk, -- control runs on inverted clock!
I_en => I_en,
I_reset => I_reset,
I_memop => dec_memop,
I_regwrite => dec_regwrite,
I_alubusy => alu_busy,
I_membusy => mem_busy,
I_alumemop => alu_memop,
O_decen => ctrl_decen,
O_aluen => ctrl_aluen,
O_memen => ctrl_memen,
O_regen => ctrl_regen,
O_regop => ctrl_regop,
O_memop => ctrl_memop,
O_mem_imem => ctrl_mem_imem
);
dec_instance: decoder port map(
I_clk => I_clk,
I_en => ctrl_decen,
I_instr => mem_data,
O_rs1 => dec_rs1,
O_rs2 => dec_rs2,
O_rd => dec_rd,
O_imm => dec_imm,
O_fop => dec_fop,
O_regwrite => dec_regwrite,
O_memop => dec_memop
);
mem_instance: mem port map(
I_clk => I_clk,
I_en => ctrl_memen,
I_op => ctrl_memop,
I_iaddr => alu_pc,
I_daddr => alu_out,
I_data => reg_dataS2,
I_mem_imem => ctrl_mem_imem,
O_data => mem_data,
O_busy => mem_busy,
-- wired to outside world, RAM, devices etc.
O_memen => O_memen,
O_memaddr => O_memaddr,
O_memdata => O_memdata,
I_memdata => I_memdata,
O_memwrite => O_memwrite,
I_membusy => I_membusy
);
reg_instance: registers port map(
I_clk => I_clk,
I_en => ctrl_regen,
I_op => ctrl_regop,
I_selS1 => dec_rs1,
I_selS2 => dec_rs2,
I_selD => dec_rd,
I_dataAlu => alu_out,
I_dataMem => mem_data,
O_dataS1 => reg_dataS1,
O_dataS2 => reg_dataS2
);
process(I_clk)
begin
end process;
end Behavioral;
|
mit
|
22fb7a0a8a1762c061023e91d1310efa
| 0.647254 | 2.640048 | false | false | false | false |
sahandKashani/TRDB-D5M
|
DE0-Nano/hw/hdl/DE0_Nano_TRDB_D5M_top_level.vhd
| 2 | 5,936 |
-- #############################################################################
-- DE0_Nano_TRDB_D5M_top_level.vhd
--
-- BOARD : DE0-Nano from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.3
-- Creation date : 21/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_TRDB_D5M_top_level is
port(
-- CLOCK
CLOCK_50 : in std_logic;
-- LED
-- LED : out std_logic_vector(7 downto 0);
-- KEY_N
-- KEY_N : in std_logic_vector(1 downto 0);
-- SW
-- SW : in std_logic_vector(3 downto 0);
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_DQM : out std_logic_vector(1 downto 0);
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- EPCS
-- EPCS_ASDO : out std_logic;
-- EPCS_DATA0 : in std_logic;
-- EPCS_DCLK : out std_logic;
-- EPCS_NCSO : out std_logic;
-- Accelerometer and EEPROM
-- G_SENSOR_CS_N : out std_logic;
-- G_SENSOR_INT : in std_logic;
-- I2C_SCLK : out std_logic;
-- I2C_SDAT : inout std_logic;
-- ADC
-- ADC_CS_N : out std_logic;
-- ADC_SADDR : out std_logic;
-- ADC_SCLK : out std_logic;
-- ADC_SDAT : in std_logic;
-- 2x13 GPIO Header
-- GPIO_2 : inout std_logic_vector(12 downto 0);
-- GPIO_2_IN : in std_logic_vector(2 downto 0);
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic
-- GPIO_1
-- GPIO_1 : inout std_logic_vector(33 downto 0);
-- GPIO_1_IN : in std_logic_vector(1 downto 0)
);
end entity DE0_Nano_TRDB_D5M_top_level;
architecture rtl of DE0_Nano_TRDB_D5M_top_level is
component system is
port(
clk_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
sdram_clk_clk : out std_logic;
sdram_controller_addr : out std_logic_vector(12 downto 0);
sdram_controller_ba : out std_logic_vector(1 downto 0);
sdram_controller_cas_n : out std_logic;
sdram_controller_cke : out std_logic;
sdram_controller_cs_n : out std_logic;
sdram_controller_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
sdram_controller_dqm : out std_logic_vector(1 downto 0);
sdram_controller_ras_n : out std_logic;
sdram_controller_we_n : out std_logic;
trdb_d5m_xclkin_clk : out std_logic;
trdb_d5m_cmos_sensor_frame_valid : in std_logic := 'X';
trdb_d5m_cmos_sensor_line_valid : in std_logic := 'X';
trdb_d5m_cmos_sensor_data : in std_logic_vector(11 downto 0) := (others => 'X');
trdb_d5m_i2c_scl : inout std_logic := 'X';
trdb_d5m_i2c_sda : inout std_logic := 'X';
trdb_d5m_pixclk_clk : in std_logic := 'X'
);
end component system;
begin
GPIO_0_D5M_RESET_N <= '1';
GPIO_0_D5M_TRIGGER <= '0';
system_inst : component system
port map(
clk_clk => CLOCK_50,
reset_reset_n => '1',
sdram_clk_clk => DRAM_CLK,
sdram_controller_addr => DRAM_ADDR,
sdram_controller_ba => DRAM_BA,
sdram_controller_cas_n => DRAM_CAS_N,
sdram_controller_cke => DRAM_CKE,
sdram_controller_cs_n => DRAM_CS_N,
sdram_controller_dq => DRAM_DQ,
sdram_controller_dqm => DRAM_DQM,
sdram_controller_ras_n => DRAM_RAS_N,
sdram_controller_we_n => DRAM_WE_N,
trdb_d5m_xclkin_clk => GPIO_0_D5M_XCLKIN,
trdb_d5m_cmos_sensor_frame_valid => GPIO_0_D5M_FVAL,
trdb_d5m_cmos_sensor_line_valid => GPIO_0_D5M_LVAL,
trdb_d5m_cmos_sensor_data => GPIO_0_D5M_D,
trdb_d5m_i2c_scl => GPIO_0_D5M_SCLK,
trdb_d5m_i2c_sda => GPIO_0_D5M_SDATA,
trdb_d5m_pixclk_clk => GPIO_0_D5M_PIXCLK
);
end;
|
unlicense
|
dd43efb5cf08e078b87444fb491503fb
| 0.443733 | 3.550239 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/BlinkTb.vhd
| 1 | 825 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BlinkTb is
end BlinkTb;
-- Testes funcionais à entidade Blink.
architecture Stimulus of BlinkTb is
signal s_clock, s_load, s_enable : std_logic;
signal s_numberIn, s_numberOut : std_logic_vector(3 downto 0);
begin
uut: entity work.Blink(Behavioral)
port map(clock => s_clock,
enable => s_enable,
numberIn => s_numberIn,
numberOut => s_numberOut,
load => s_load);
clk_proc:process
begin
s_clock <= '1';
wait for 10 ns;
s_clock <= '0';
wait for 10 ns;
end process;
comb_proc:process
begin
s_load <= '1';
s_numberIn <= "1010";
s_enable <= '1';
wait for 100 ns;
s_enable <= '0';
wait for 35 ns;
end process;
end Stimulus;
|
gpl-2.0
|
8a38da08fb0c75a3dc93ab7e2bc2ee50
| 0.643204 | 2.851211 | false | false | false | false |
rbaummer/UART
|
baud_clock_gen.vhd
| 1 | 2,964 |
--------------------------------------------------------------------------------
--
-- File: Baud Clock Gen
-- Author: Rob Baummer
--
-- Description: Generates the baud rate tick from 9600 to 57600 baud.
--------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
entity baud_clock_gen is
generic (
--Frequency of System Clock in Hz
clock_frequency : integer);
port (
reset : in std_logic;
sys_clk : in std_logic;
--Baud rate selection
--000 - 57.6
--001 - 38.4
--010 - 19.2
--011 - 14.4
--100 - 9.6
baud_rate_sel : in std_logic_vector(2 downto 0);
--Baud rate enable
baud_enable : out std_logic
);
end baud_clock_gen;
architecture behavorial of baud_clock_gen is
--Calculate rollover value for 115.2k baud rate using specified clock frequency
--The baud rates 9.6k to 56.6k are all evenly divisible from 115.2
constant baud_rollover : integer := integer(real(clock_frequency)/(115200.0*8.0));
constant counter_size : integer := integer(round(log2(real(baud_rollover))));
--counter for 115.2k baud rate
signal fast_baud_counter : std_logic_vector(counter_size-1 downto 0);
--counter for selectable baud rate
signal slow_baud_counter : std_logic_vector(3 downto 0);
signal slow_baud_rollover : std_logic_vector(3 downto 0);
signal fast_baud_en : std_logic;
signal slow_baud_en : std_logic;
begin
--Counter for 115.2 baud rate
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or fast_baud_en = '1' then
fast_baud_counter <= (others => '0');
else
fast_baud_counter <= fast_baud_counter + 1;
end if;
end if;
end process;
--Enable is high at 115.2 KHz rate
fast_baud_en <= '1' when fast_baud_counter = std_logic_vector(to_unsigned(baud_rollover-1, counter_size)) else '0';
--Counter for selectable baud rate
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or slow_baud_en = '1' then
slow_baud_counter <= (others => '0');
elsif fast_baud_en = '1' then
slow_baud_counter <= slow_baud_counter + 1;
end if;
end if;
end process;
--Enable is high at selectable rate 9.6, 14.4, 19.1, 38.4 or 57.6 KHz
slow_baud_en <= fast_baud_en when slow_baud_counter = slow_baud_rollover else '0';
process (baud_rate_sel)
begin
case baud_rate_sel is
--57.6 KHz
when "000" => slow_baud_rollover <= X"1";
--38.4 KHz
when "001" => slow_baud_rollover <= X"2";
--19.2 KHz
when "010" => slow_baud_rollover <= X"5";
--14.4 KHz
when "011" => slow_baud_rollover <= X"7";
--9.6 KHz
when "100" => slow_baud_rollover <= X"B";
--others defaults to 57.6 KHz
when others => slow_baud_rollover <= X"1";
end case;
end process;
--Output Enable for selected Baud rate
baud_enable <= slow_baud_en;
end behavorial;
|
mit
|
a86ffa45d23fd0ce4095c2a9adbc73ad
| 0.625506 | 3.02449 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2/Hex2SSegController.vhd
| 1 | 874 |
----------------------------------------------
-- Module Name: ClockController - switch --
----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity ClockController is
port ( clock : in std_logic;
sw0 : in std_logic;
clk : out std_logic);
end ClockController;
architecture switch of ClockController is
constant TC5Hz : integer := 56; -- TC for 5 Hz clock
constant TC1KHz : integer := 15; -- TC for 1 KHz clock
signal clk5Hz : std_logic := '0'; -- 5 Hz clock
signal clk1KHz : std_logic := '0'; -- 1 KHz clock
begin
c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
c1KHz: CDiv port map (clock, TC1KHz, clk1KHz);
-- use switch to select fast or slow clk
clk <= clk1KHz when (sw0 = '0') else
clk5Hz;
end switch;
|
gpl-3.0
|
ef0129b9bcabdf47635982edf8067198
| 0.557208 | 3.641667 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 1/NOR2Gate.vhd
| 1 | 511 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOR2Gate is
port(inPort0 : in std_logic;
inPort1 : in std_logic;
outPort : out std_logic);
end NOR2Gate;
architecture Structural of NOR2Gate is
signal s_orOut : std_logic;
begin
or_gate : entity work.OR2Gate(Behavioral)
port map(inPort0 => inPort0,
inPort1 => inPort1,
outPort => s_orOut);
not_gate : entity work.NotGate(Behavioral)
port map(inPort => s_orOut,
outPort => outPort);
end Structural;
|
gpl-2.0
|
391620406e1f32a0d354ebd17222ccee
| 0.657534 | 3.078313 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
VGA-PS2_Cursor/mousecomp.vhd
| 1 | 3,609 |
----------------------------------------------------------------------------------
-- Company: Digilent RO
-- Engineer: Mircea Dabacan
--
-- Create Date: 12:57:12 03/01/2008
-- Design Name:
-- Module Name: MouseRefComp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is the structural VHDL code of the
-- Digilent Mouse Reference Component.
-- It instantiates three components:
-- - ps2interface
-- - mouse_controller
-- - resolution_mouse_informer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.vga_mouse_pkg.all;
entity mousecomp is
port (
clk : in std_logic;
resolution : in std_logic;
rst : in std_logic;
switch : in std_logic;
left : out std_logic;
middle : out std_logic;
new_event : out std_logic;
right : out std_logic;
busy : out std_logic;
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end mousecomp;
architecture structural of mousecomp is
signal TX_DATA : std_logic_vector(7 downto 0);
signal bitSetMaxX : std_logic;
signal vecValue : std_logic_vector(9 downto 0);
signal bitRead : std_logic;
signal bitWrite : std_logic;
signal bitErr : std_logic;
signal bitSetX : std_logic;
signal bitSetY : std_logic;
signal bitSetMaxY : std_logic;
signal vecRxData : std_logic_vector(7 downto 0);
begin
MouseCtrlInst : mouse_controller
port map (
clk => clk,
rst => rst,
read => bitRead,
write => bitWrite,
err => bitErr,
setmax_x => bitSetMaxX,
setmax_y => bitSetMaxY,
setx => bitSetX,
sety => bitSetY,
value(9 downto 0) => vecValue(9 downto 0),
rx_data(7 downto 0) => vecRxData(7 downto 0),
tx_data(7 downto 0) => TX_DATA(7 downto 0),
left => left,
middle => middle,
right => right,
xpos(9 downto 0) => xpos(9 downto 0),
ypos(9 downto 0) => ypos(9 downto 0),
zpos(3 downto 0) => zpos(3 downto 0),
new_event => new_event
);
ResMouseInfInst : resolution_mouse_informer
port map (
clk => clk,
resolution => resolution,
rst => rst,
switch => switch,
setmax_x => bitSetMaxX,
setmax_y => bitSetMaxY,
setx => bitSetX,
sety => bitSetY,
value(9 downto 0) => vecValue(9 downto 0)
);
Pss2Inst : ps2interface
port map (
clk => clk,
rst => rst,
tx_data(7 downto 0) => TX_DATA(7 downto 0),
read => bitRead,
write => bitWrite,
busy => busy,
err => bitErr,
rx_data(7 downto 0) => vecRxData(7 downto 0),
ps2_clk => ps2_clk,
ps2_data => ps2_data
);
end structural;
|
gpl-3.0
|
90311947285953a5b49ca33384bc551d
| 0.48767 | 4.055056 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/FreqDivider.vhd
| 1 | 691 |
-- Projeto MasterMind
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
generic(K : natural := 2);
port (clkIn : in std_logic;
clkOut: out std_logic);
end FreqDivider;
-- Divisor de frequência dado fornecido nos guiões da disciplina
architecture Behavioral of FreqDivider is
signal s_counter : natural;
constant halfWay : natural := K/2-1;
begin
process(clkIn)
begin
if(rising_edge(clkIn)) then
if(s_counter = halfWay) then
clkOut <= '1';
s_counter <= s_counter+1;
elsif(s_counter=K-1) then
clkOut <= '0';
s_counter<=0;
else
s_counter <= s_counter+1;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
eb5474aa2277ecb52e222e3024cc4f85
| 0.679245 | 2.82377 | false | false | false | false |
tejainece/VHDLExperiments
|
Multiply16Booth4/Counter4_2.vhd
| 4 | 1,489 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:15:39 12/15/2013
-- Design Name:
-- Module Name: Counter4_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
end Counter4_2;
architecture Behavioral of Counter4_2 is
COMPONENT FAdder
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
signal sINT1: STD_LOGIC;
begin
fa1: FAdder port map(
c => a,
a => b,
b => c,
s => sINT1,
co => tout
);
fa2: FAdder port map(
c => tin,
a => sINT1,
b => d,
s => s,
co => co
);
end Behavioral;
|
gpl-3.0
|
7ba55cb1edd8e2b0b550aed730749e72
| 0.541974 | 3.353604 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/BasicWatchWithBugs/Resolução/Counter4Bits.vhd
| 2 | 889 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter4Bits is
generic(MAX : natural);
port(reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
valOut : out std_logic_vector(3 downto 0);
termCnt : out std_logic);
end Counter4Bits;
architecture RTL of Counter4Bits is
signal s_value : unsigned(3 downto 0);
begin
process(reset, clk)
begin
if (rising_edge(clk)) then
if (reset = '1') then
s_value <= (others => '0');
termCnt <= '0';
elsif (enable = '1') then
if (to_integer(s_value) = MAX) then
s_value <= (others => '0');
termCnt <= '0';
else
s_value <= s_value + 1;
if (to_integer(s_value) = MAX - 1) then
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end if;
end if;
end process;
valOut <= std_logic_vector(s_value);
end RTL;
|
gpl-2.0
|
b1a13ecd0c1341bd4fd8cff6e7ca2e3b
| 0.588301 | 2.710366 | false | false | false | false |
tejainece/VHDLExperiments
|
FloatingPointMul23/SelectorLSB.vhd
| 1 | 1,481 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:14:26 11/21/2013
-- Design Name:
-- Module Name: SelectorLSB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.MyTypes.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SelectorLSB is
generic (
num_sum: integer := 0
);
Port ( cIn : in PairT;
cSel : in std_logic;
cOut : out std_logic;
sumIn : in PairArr(num_sum downto 0);
sumOut : out std_logic_vector(num_sum downto 0)
);
end SelectorLSB;
architecture Behavioral of SelectorLSB is
begin
process (cIn, cSel, sumIn)
begin
if (cSel = '0') then
for index in 0 to num_sum loop
sumOut(index) <= sumIn(index)(0);
end loop;
cOut <= cIn(0);
else
for index in 0 to num_sum loop
sumOut(index) <= sumIn(index)(1);
end loop;
cOut <= cIn(1);
end if;
end process;
end Behavioral;
|
gpl-3.0
|
01b1690a849ce16a87d365644445460f
| 0.585415 | 3.543062 | false | false | false | false |
rbaummer/UART
|
testbench/mixed_clock_fifo_regbased_TB.vhd
| 1 | 3,352 |
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mixed_clock_fifo_regbased_tb is
end mixed_clock_fifo_regbased_tb;
architecture TB_ARCHITECTURE of mixed_clock_fifo_regbased_tb is
-- Component declaration of the tested unit
component mixed_clock_fifo_regbased
generic(
N : INTEGER;
L : INTEGER );
port(
reset : in STD_LOGIC;
read_clk : in STD_LOGIC;
read : in STD_LOGIC;
valid : out STD_LOGIC;
empty : out STD_LOGIC;
read_data : out STD_LOGIC_VECTOR(N-1 downto 0);
write_clk : in STD_LOGIC;
write : in STD_LOGIC;
full : out STD_LOGIC;
write_data : in STD_LOGIC_VECTOR(N-1 downto 0) );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal reset : STD_LOGIC := '0';
signal read_clk : STD_LOGIC := '0';
signal read : STD_LOGIC := '0';
signal write_clk : STD_LOGIC := '0';
signal write : STD_LOGIC := '0';
signal write_data : STD_LOGIC_VECTOR(15 downto 0) := X"0000";
-- Observed signals - signals mapped to the output ports of tested entity
signal valid : STD_LOGIC := '0';
signal empty : STD_LOGIC := '0';
signal read_data : STD_LOGIC_VECTOR(15 downto 0) := X"0000";
signal full : STD_LOGIC := '0';
-- Add your code here ...
constant clk1_period : time := 8 ns;
constant clk2_period : time := 15 ns;
begin
-- Unit Under Test port map
UUT : mixed_clock_fifo_regbased
generic map (
N => 16,
L => 8
)
port map (
reset => reset,
read_clk => read_clk,
read => read,
valid => valid,
empty => empty,
read_data => read_data,
write_clk => write_clk,
write => write,
full => full,
write_data => write_data
);
--Set read clock to 125 MHz
process
begin
clk1: loop
read_clk <= '1';
wait for clk1_period/2;
read_clk <= '0';
wait for clk1_period/2;
end loop;
end process;
--Set write clock to 66 MHz
process
begin
clk2: loop
write_clk <= '1';
wait for clk2_period/2;
write_clk <= '0';
wait for clk2_period/2;
end loop;
end process;
-- Add your stimulus here ...
process
--procedure to write a data word into the FIFO
procedure put_data(word : in std_logic_vector(15 downto 0)) is
begin
wait until write_clk = '1';
write_data <= word;
write <= '1';
wait until write_clk = '1';
write <= '0';
end procedure;
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
put_data(X"0001");
put_data(X"0002");
put_data(X"0003");
put_data(X"0004");
put_data(X"0005");
put_data(X"0006");
put_data(X"0007");
put_data(X"0008");
wait for 1 ms;
end process;
process
--procedure to read a data word from the FIFO
procedure get_data is
begin
wait until read_clk = '1';
read <= '1';
wait for 8 ns;
read <= '0';
end procedure;
begin
wait for 300 ns;
get_data;
get_data;
wait for 16 ns;
get_data;
get_data;
get_data;
wait for 24 ns;
get_data;
get_data;
get_data;
wait for 1 ms;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mixed_clock_fifo_regbased of mixed_clock_fifo_regbased_tb is
for TB_ARCHITECTURE
for UUT : mixed_clock_fifo_regbased
use entity work.mixed_clock_fifo_regbased(behavioral);
end for;
end for;
end TESTBENCH_FOR_mixed_clock_fifo_regbased;
|
mit
|
727ade8947f01a4cd1965271043bcea0
| 0.639916 | 2.884682 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/sys_toplevel_wb8.vhd
| 1 | 3,857 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
use work.arbiter_types.all;
entity sys_toplevel_wb8 is
Port(
I_clk: in std_logic;
I_reset: in std_logic := '0';
I_serial_rx: in std_logic;
I_interrupt: in std_logic;
I_spi_miso: in std_logic;
O_leds: out std_logic_vector(7 downto 0) := X"00";
O_serial_tx: out std_logic;
O_vga_vsync, O_vga_hsync, O_vga_r, O_vga_g, O_vga_b: out std_logic := '0';
O_spi_sel, O_spi_clk, O_spi_mosi: out std_logic := '0'
);
end sys_toplevel_wb8;
architecture Behavioral of sys_toplevel_wb8 is
signal arb_ACK_O: std_logic := '0';
signal arb_DAT_O: std_logic_vector(7 downto 0) := X"00";
signal arb_ACK_I: arb_ACK_I_t;
signal arb_DAT_I: arb_DAT_I_t;
signal arb_STB_O: arb_STB_O_t;
signal cpu_DAT_O: std_logic_vector(7 downto 0);
signal cpu_ADR_O: std_logic_vector(XLEN-1 downto 0);
signal cpu_STB_O, cpu_CYC_O, cpu_WE_O: std_logic := '0';
signal interruptgen_interrupt: std_logic := '0';
signal pll_clk, pll_vga_clk: std_logic;
signal reset_ctrl_reset_O: std_logic;
signal inv_reset: std_logic := '0';
signal inv_interrupt: std_logic := '0';
begin
-- interrupt button is inverted
inv_interrupt <= not I_interrupt;
arbiter_instance: entity work.arbiter_wb8 port map(
ADR_I => cpu_ADR_O,
ACK_I => arb_ACK_I,
DAT_I => arb_DAT_I,
STB_I => cpu_STB_O,
ACK_O => arb_ACK_O,
DAT_O => arb_DAT_O,
STB_O => arb_STB_O
);
cpu_instance: entity work.cpu_toplevel_wb8 port map(
CLK_I => pll_clk,
ACK_I => arb_ACK_O,
DAT_I => arb_DAT_O,
RST_I => reset_ctrl_reset_O,
ADR_O => cpu_ADR_O,
DAT_O => cpu_DAT_O,
CYC_O => cpu_CYC_O,
STB_O => cpu_STB_O,
WE_O => cpu_WE_O,
I_interrupt => interruptgen_interrupt
);
interruptgen_instance: entity work.interruptgen port map(
I_clk => pll_clk,
I_interrupt => inv_interrupt,
O_interrupt => interruptgen_interrupt
);
leds_instance: entity work.leds_wb8 port map(
ADR_I => cpu_ADR_O,
CLK_I => pll_clk,
DAT_I => cpu_DAT_O,
STB_I => arb_STB_O(1),
WE_I => cpu_WE_O,
ACK_O => arb_ACK_I(1),
DAT_O => arb_DAT_I(1),
-- control signal for onboard LEDs
O_leds => O_leds
);
reset_ctrl_instance: entity work.reset_ctrl port map(
I_clk => pll_clk,
I_reset => '0',
I_reset_inv => I_reset,
O_reset => reset_ctrl_reset_O
);
serial_instance: entity work.serial_wb8
generic map(
CLOCKFREQ => 50000000,
BAUDRATE => 115200
)
port map(
ADR_I => cpu_ADR_O,
CLK_I => pll_clk,
DAT_I => cpu_DAT_O,
STB_I => arb_STB_O(2),
WE_I => cpu_WE_O,
ACK_O => arb_ACK_I(2),
DAT_O => arb_DAT_I(2),
I_rx => I_serial_rx,
O_tx => O_serial_tx
);
spiromram_instance: entity work.spiromram_wb8 port map(
CLK_I => pll_clk,
STB_I => arb_STB_O(4),
WE_I => cpu_WE_O,
ADR_I => cpu_ADR_O,
DAT_I => cpu_DAT_O,
RST_I => reset_ctrl_reset_O,
DAT_O => arb_DAT_I(4),
ACK_O => arb_ACK_I(4),
-- SPI signal lines
I_spi_miso => I_spi_miso,
O_spi_sel => O_spi_sel,
O_spi_clk => O_spi_clk,
O_spi_mosi => O_spi_mosi
);
vga_instance: entity work.vga_wb8 port map(
ADR_I => cpu_ADR_O,
CLK_I => pll_clk,
DAT_I => cpu_DAT_O,
STB_I => arb_STB_O(3),
WE_I => cpu_WE_O,
ACK_O => arb_ACK_I(3),
DAT_O => arb_DAT_I(3),
I_vga_clk => pll_vga_clk,
O_vga_vsync => O_vga_vsync,
O_vga_hsync => O_vga_hsync,
O_vga_r => O_vga_r,
O_vga_g => O_vga_g,
O_vga_b => O_vga_b
);
-- I/O device 0
ram_instance: entity work.ram_wb8 port map(
CLK_I => pll_clk,
STB_I => arb_STB_O(0),
WE_I => cpu_WE_O,
ADR_I => cpu_ADR_O,
DAT_I => cpu_DAT_O,
DAT_O => arb_DAT_I(0),
ACK_O => arb_ACK_I(0)
);
pll_instance: entity work.wizpll port map(
inclk0 => I_clk,
c0 => pll_clk
);
pll_vga_instance: entity work.wizpll_vga port map(
inclk0 => I_clk,
c0 => pll_vga_clk
);
end Behavioral;
|
mit
|
3e4c7c396170314b4f0b0bb22f9a9567
| 0.604096 | 2.263498 | false | false | false | false |
jpcofr/PDUAMaude
|
PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/MDR.vhdl
| 1 | 1,457 |
-- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: MDR (Registro de datos) **
-- ** Creacion: Julio 07 **
-- ** Revisión: Marzo 08 **
-- ** Por: MGH-CMUA-UNIANDES **
-- ***********************************************
-- Descripcion:
-- Registro de Datos
-- HMDR (habilitador)
-- _____|_
-- RD_WR -->| |
-- DATA_EX_in -->| |<-- DATA_ALU
-- DATA_EX_out <--| |--> DATA_C
-- |_______|
--
-- ***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MDR is
Port ( DATA_EX_in : in std_logic_vector(7 downto 0);
DATA_EX_out : out std_logic_vector(7 downto 0);
DATA_ALU : in std_logic_vector(7 downto 0);
DATA_C : out std_logic_vector(7 downto 0);
HMDR : in std_logic;
RD_WR : in std_logic);
end MDR;
architecture Behavioral of MDR is
begin
process(DATA_EX_in,DATA_ALU,HMDR,RD_WR)
begin
if HMDR = '0' then -- no acceso a memoria
DATA_EX_out <= (others => 'Z');
DATA_C <= DATA_ALU;
elsif RD_WR = '0' then --lectura
--DATA_EX_out <= (others => 'Z');
DATA_C <= DATA_EX_in;
else
DATA_EX_out <= DATA_ALU;
DATA_C <= DATA_ALU;
end if;
end process;
end Behavioral;
|
mit
|
c4797914b00d48017276a7f9067b7f89
| 0.446122 | 3.167391 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/with screen/MIPSconPantallaME/Instruction.vhd
| 1 | 11,570 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:40:15 01/09/2013
-- Design Name:
-- Module Name: Instruction - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Instruction is
port ( hcnt: in std_logic_vector(8 downto 0); -- horizontal pixel counter
vcnt: in std_logic_vector(9 downto 0);
funct: in std_logic_vector(5 downto 0);
op: in std_logic_vector(5 downto 0);
pintar: out std_logic;
pos_x:in std_logic_vector (8 downto 0);
pos_y: in std_logic_vector(9 downto 0)
);
end Instruction;
architecture Behavioral of Instruction is
signal Px: std_logic_vector(2 downto 0);
signal Py: std_logic_vector(3 downto 0);
begin
Px<=hcnt(2 downto 0);
Py<=vcnt(3 downto 0);
process(hcnt, vcnt)
begin
pintar<='0';
--primero
if hcnt >= pos_x and hcnt < pos_x + 8 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if op = "000000" then --tipo R
if funct ="000000" then --nop
if(N(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100000" then --add
if(A(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100010" then --sub
if(S(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100100" then --and
if(A(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100101" then --or
if(O(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if; --nop
elsif op = "100011" then--lw
if(L(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "101011" then--sw
if(S(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000100" then--beq
if(B(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000110" then--bgt
if(B(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000111" then--blt
if(B(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000101" then--bne
if(B(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010010" then--andi
if(A(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010011" then--ori
if(O(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010000" then--addi
if(A(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010001" then--subi
if(S(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "111111" then--J
if(J(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;-- tipo R
end if;
end if;
--segundo
if hcnt >= pos_x+8 and hcnt < pos_x + 16 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if op = "000000" then --tipo R
if funct ="000000" then --nop
if(O(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100000" then --add
if(D(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100010" then --sub
if(U(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100100" then --and
if(N(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100101" then --or
if(R(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if; --nop
elsif op = "100011" then--lw
if(W(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "101011" then--sw
if(W(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000100" then--beq
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000110" then--bgt
if(G(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000111" then--blt
if(L(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000101" then--bne
if(N(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010010" then--andi
if(N(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010011" then--ori
if(R(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010000" then--addi
if(D(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010001" then--subi
if(U(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "111111" then--J
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;-- tipo R
end if;
end if;
--tercero
if hcnt >= pos_x+16 and hcnt < pos_x + 24 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if op = "000000" then --tipo R
if funct ="000000" then --nop
if(p(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100000" then --add
if(D(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100010" then --sub
if(B(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100100" then --and
if(D(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100101" then --or
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if; --nop
elsif op = "100011" then--lw
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "101011" then--sw
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000100" then--beq
if(Q(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000110" then--bgt
if(t(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000111" then--blt
if(T(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000101" then--bne
if(E(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010010" then--andi
if(D(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010011" then--ori
if(I(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010000" then--addi
if(D(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010001" then--subi
if(B(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "111111" then--J
if(VACIO(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;-- tipo R
end if;
end if;
if hcnt >= pos_x+24 and hcnt < pos_x + 32 then
if vcnt >= pos_y and vcnt < pos_y + 16 then
if op = "000000" then --tipo R
if funct ="000000" then --nop
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100000" then --add
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100010" then --sub
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100100" then --and
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif funct ="100101" then --or
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if; --nop
elsif op = "100011" then--lw
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "101011" then--sw
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000100" then--beq
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000110" then--bgt
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000111" then--blt
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "000101" then--bne
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010010" then--andi
if(I(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010011" then--ori
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010000" then--addi
if(I(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "010001" then--subi
if(I(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
elsif op = "111111" then--J
if(vacio(conv_integer(Py))(conv_integer(Px))='1') then pintar<='1';
else pintar<='0';
end if;
end if;-- tipo R
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
a927c78569ff3d7e77f4e352a5efe997
| 0.553673 | 3.045538 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 8/Parte 1/SeqDetector.vhd
| 1 | 668 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqDetector is
port( CLOCK_50 : in std_logic;
SW : in std_logic_vector(0 downto 0);
LEDR : out std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(0 downto 0));
end SeqDetector;
architecture Shell of SeqDetector is
signal s_clk : std_logic;
begin
LEDG(0) <= s_clk;
clk_div: entity Work.ClkDividerN(Behavioral)
generic map(divFactor => 200000000)
port map(reset => '0',
clkIn => CLOCK_50,
clkOut=> s_clk);
seqdetFSM_mealy: entity Work.SeqDetFSM(MealyArch)
port map(xin => SW(0),
yout => LEDR(0),
clk => s_clk);
end Shell;
|
gpl-2.0
|
aeec0ef502fa387f3dad05887135fd68
| 0.61976 | 2.866953 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/attic/shifter.vhd
| 1 | 1,414 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity shifter is
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_op: in std_logic_vector(1 downto 0);
I_input: in std_logic_vector(XLEN-1 downto 0);
I_count: in std_logic_vector(4 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0)
);
end shifter;
architecture Behavioral of shifter is
begin
--process(I_clk)
process(I_clk, I_en, I_op, I_input, I_count)
begin
if rising_edge(I_clk) and I_en = '1' then
case I_op is
when SHIFTER_SLL =>
O_data <= std_logic_vector(shift_left(unsigned(I_input),to_integer(unsigned(I_count))));
when SHIFTER_SRL =>
O_data <= std_logic_vector(shift_right(unsigned(I_input),to_integer(unsigned(I_count))));
when SHIFTER_SRA =>
O_data <= std_logic_vector(shift_right(signed(I_input),to_integer(unsigned(I_count))));
when others =>
null;
end case;
-- if I_op = SHIFTER_SLL then
-- O_data <= std_logic_vector(shift_left(unsigned(I_input),to_integer(unsigned(I_count))));
-- elsif I_op = SHIFTER_SRL then
-- O_data <= std_logic_vector(shift_right(unsigned(I_input),to_integer(unsigned(I_count))));
-- else -- SHIFTER_SRA
-- O_data <= std_logic_vector(shift_right(signed(I_input),to_integer(unsigned(I_count))));
-- end if;
end if;
end process;
end Behavioral;
|
mit
|
8d0648cf771f2407811b2ccfeeec977b
| 0.653465 | 2.772549 | false | false | false | false |
ncareol/nidas
|
src/firmware/anythingIO/anythingIO_260x.vhd
| 1 | 10,669 |
--LIBRARY ieee;
--USE ieee.std_logic_1164.ALL;
--PACKAGE data_memory is
-- constant memsize: integer := 61;
-- type word is std_logic_vector(15 downto 0);
-- type memory is array(5 downto 0) of word;
-- type memory is array(5 downto 0) of std_logic_vector(15 downto 0);
--END data_memory;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
--USE data__memory.ALL;
entity PC104 is port
(
-- bus interface signals --
-- BALE: in STD_LOGIC;
-- TC: in STD_LOGIC;
-- BOSC: in STD_LOGIC;
-- RSTDRV: in STD_LOGIC; --System reset
-- REFRES: in STD_LOGIC;
-- SBHE: in STD_LOGIC;
-- MASTER: in STD_LOGIC;
-- SMEMR: in STD_LOGIC;
-- SMEMW: in STD_LOGIC;
-- IOCHRDY: inout STD_LOGIC;
-- MEMCS16: inout STD_LOGIC;
IOCS16: inout STD_LOGIC;
-- IRQ: out STD_LOGIC_VECTOR (15 downto 3); -- interrupts
-- DACK: in STD_LOGIC_VECTOR (7 downto 6); -- dma acknowledges
-- DRQ: out STD_LOGIC_VECTOR (7 downto 6); -- dma requests
LBE: out STD_LOGIC;
LBDIR: out STD_LOGIC;
-- SYSCLK: in STD_LOGIC; --PC104 bus clock PIN 185 GCK3
SynClk: in STD_LOGIC; --50 MHz local clock PIN 80 GCK0
DIS: out STD_LOGIC;
AEN: in STD_LOGIC;
IORD: in STD_LOGIC;
IOWR: in STD_LOGIC;
SA: in STD_LOGIC_VECTOR (9 downto 0); -- address bus
SD: out STD_LOGIC_VECTOR (15 downto 0); -- data bus
-- led bits
LEDS: out STD_LOGIC_VECTOR(5 downto 0);
strobe: in std_logic;
Hadvance: out STD_LOGIC;
Hreset: out STD_LOGIC;
Hdata: in STD_LOGIC;
HistBits: in std_logic_vector(5 downto 0);
pulse0: in std_logic;
pulse1: in std_logic;
latch_count: in std_logic;
alt_clock: in std_logic;
radar_alt: in std_logic;
-- ckout: out std_logic;
ldebug: out std_logic;
pdebug: out std_logic;
ndebug: out std_logic;
cdebug: out std_logic
);
end PC104;
Architecture behavior of PC104 is
-- 0x220 hex
constant Decode : STD_LOGIC_VECTOR (5 downto 0) := "100010";
-- misc global signals --
-- type memory is array(63 downto 0) of std_logic_vector(15 downto 0);
type ram_type is array(63 downto 0) of std_logic_vector(15 downto 0);
-- signal Histogram: memory; --:=
signal Histogram: ram_type:=
(X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",
X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000",X"0000");
signal index: integer:=0;
signal CardSelect: STD_LOGIC:='0';
signal HistAdd: std_logic_vector (15 downto 0):=X"0000";
signal strobes: std_logic_vector (15 downto 0):=X"0000";
signal count0: std_logic_vector(15 downto 0):=X"0000";
signal count1: std_logic_vector(15 downto 0):=X"0000";
signal count0_latch: std_logic_vector(15 downto 0):=X"0000";
signal count1_latch: std_logic_vector(15 downto 0):=X"0000";
signal count_clear: std_logic:='0';
signal altitude: std_logic_vector(23 downto 0):=X"000000";
signal clear_hist: std_logic:='0';
signal house_data: std_logic_vector(15 downto 0):=X"0000";
signal house_adv: std_logic:='0';
signal alt_clock_old1: std_logic:='0';
signal alt_clock_old2: std_logic:='0';
signal read_data: std_logic:='0';
signal read_data_old1: std_logic:='0';
signal read_data_old2: std_logic:='0';
signal pulse0_old1: std_logic:='0';
signal pulse1_old1: std_logic:='0';
signal pulse0_old2: std_logic:='0';
signal pulse1_old2: std_logic:='0';
signal latch_count_old1: std_logic:='0';
signal latch_count_old2: std_logic:='0';
signal strobe_old1: std_logic:='0';
signal strobe_old2: std_logic:='0';
signal Hdata_old1: std_logic:='0';
signal Hdata_old2: std_logic:='0';
signal ledcount: STD_LOGIC_VECTOR (28 downto 0);
--Components:
-- component ledblink is
-- port (
-- clk: in STD_LOGIC;
-- ledx: out STD_LOGIC_VECTOR (5 downto 0)
-- );
-- end component ledblink;
begin
-- gledblink: ledblink port map (
-- clk => SynClk,
-- ledx => LEDS
-- );
-- DRQ <= "ZZ";
-- IRQ <= "ZZZZZZZZZZZZZ";
DIS <= '0'; -- uncomment to leave configuration decode on
-- DIS <= '1'; -- uncomment to disable configuration decode
-- MEMCS16 <= 'Z';
-- IOCHRDY <= 'Z';
-- ckout <= SynClk;
HistAdd(15 downto 6) <= "0000000000";
HistAdd(5 downto 0) <= HistBits(5 downto 0);
-- leds(0) <= not ledcount(23);
leds(0) <= not(HistBits(0) and HistBits(1) and HistBits(2) and HistBits(3)
and HistBits(4) and HistBits(5));
leds(1) <= not ledcount(24);
leds(2) <= not ledcount(25);
leds(3) <= not ledcount(26);
leds(4) <= not ledcount(27);
leds(5) <= not ledcount(28);
ledblinker: process (SynClk)
begin
if rising_edge(SynClk) then
ledcount <= ledcount + 1;
end if;
end process ledblinker;
RadarAltimeter: process (SynClk)
begin
if rising_edge(SynClk) then
alt_clock_old2 <= alt_clock_old1;
alt_clock_old1 <= alt_clock;
if alt_clock_old2 = '0' and alt_clock_old1 = '1' then
-- altitude <= altitude(1 to 23) & radar_alt; --bit into msb
-- altitude <= radar_alt & altitude(0 to 22); --bit into lsb
-- altitude <= altitude(22 downto 0) & radar_alt; --bit into lsb
altitude <= radar_alt & altitude(23 downto 1) ; --bit into msb
ndebug <= radar_alt;
pdebug <= altitude(23);
end if;
end if;
end process RadarAltimeter;
PulseCounters: process (SynClk)
begin
if rising_edge(SynClk) then
pulse0_old1 <= pulse0;
pulse0_old2 <= pulse0_old1;
pulse1_old1 <= pulse1;
pulse1_old2 <= pulse1_old1;
if count_clear = '1' then
count0 <= X"0000";
count1 <= X"0000";
end if;
if pulse0_old2 = '0' and pulse0_old1 = '1' then
count0 <= count0 + 1;
end if;
if pulse1_old2 = '0' and pulse1_old1 = '1' then
count1 <= count1 + 1;
end if;
end if;
end process PulseCounters;
LatchCounts: process (SynCLk)
begin
if rising_edge(SynClk) then
latch_count_old1 <= latch_count;
latch_count_old2 <= latch_count_old1;
if latch_count_old2 = '0' and latch_count_old1 = '1' then
count_clear <= '1';
count0_latch <= count0;
count1_latch <= count1;
else
count_clear <= '0';
end if;
end if;
end process LatchCounts;
HouseCounter: process (SynClk,house_adv)
begin
if (house_adv = '1') then
house_data <= X"0000";
elsif rising_edge(SynClk) then
Hdata_old2 <= Hdata_old1;
Hdata_old1 <= Hdata;
if Hdata_old2 = '0' and Hdata_old1 = '1' then
house_data <= house_data + 1;
end if;
end if;
end process HouseCounter;
CSelect: process (AEN)
begin
if SA(9 downto 4) = Decode and AEN = '0' then
CardSelect <= '1';
LBE <= '0';
else
LBE <= '1';
CardSelect <= '0';
end if;
end process CSelect;
Localbuffer: process (CardSelect, IORD)
begin
if (CardSelect = '1') and (IORD = '0') then
LBDIR <= '0';
else
LBDIR <= '1';
end if;
end process Localbuffer;
AddDecode: process (SA, AEN, IORD)
-- variable i: integer;
begin
clear_hist <= '0';
read_data <= '0';
if SA(3 downto 0) = "0010" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD(15 downto 0) <= strobes(15 downto 0);
end if;
elsif SA(3 downto 0) = "0011" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= 'Z';
if IORD = '0' then
ldebug <= '1';
clear_hist <= '1';
end if;
elsif SA(3 downto 0) = "0100" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
ldebug <= '0';
SD(15 downto 0) <= Histogram(index);
read_data <= '1';
end if;
elsif SA(3 downto 0) = "0101" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= 'Z';
Hadvance <= '1';
house_adv <= '1';
elsif SA(3 downto 0) = "0110" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD <= house_data;
end if;
elsif SA(3 downto 0) = "0111" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= 'Z';
Hreset <= '1';
elsif SA(3 downto 0) = "1000" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD(15 downto 0) <= count0_latch(15 downto 0);
-- cdebug <='0';
end if;
elsif SA(3 downto 0) = "1010" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD(15 downto 0) <= count1_latch(15 downto 0);
end if;
elsif SA(3 downto 0) = "1100" and SA(9 downto 4) = Decode and AEN = '0' then
IOCS16 <= '0';
if IORD = '0' then
SD(15 downto 8) <= altitude(21 downto 14);
SD(7 downto 1) <= altitude(13 downto 7);
SD(0) <= altitude(1) or altitude(2) or altitude (4);
end if;
else
Hadvance <= '0';
house_adv <= '0';
Hreset <= '0';
SD(15 downto 0) <= "ZZZZZZZZZZZZZZZZ";
IOCS16 <= 'Z';
-- cdebug <= '1';
end if;
end process AddDecode;
histo: process(SynClk,clear_hist)
variable i: integer;
variable j: integer;
variable k: integer;
variable n: integer;
begin
if clear_hist = '1' then
i := 0;
cdebug <= '1';
strobes <= X"0000";
for k in 0 to 63 loop
Histogram(k) <= X"0000";
end loop;
-- i := 63;
-- while i>=0 loop
-- Histogram(i) <= X"0000";
-- i := i - 1;
-- end loop;
-- i := 31;
-- while i>=0 loop
-- Histogram(i) <= X"0000";
-- i := i - 1;
-- end loop;
elsif rising_edge(SynClk) then
j := conv_integer(HistAdd);
n := j;
cdebug <= '0';
strobe_old2 <= strobe_old1;
strobe_old1 <= strobe;
read_data_old2 <= read_data_old1;
read_data_old1 <= read_data;
if read_data_old2 = '0' and read_data_old1 = '1' then
index <= i;
i := i + 1;
elsif strobe_old2 = '0' and strobe_old1 = '1' then
strobes <= strobes + 1;
Histogram(n) <= Histogram(n) + 1;
end if;
end if;
end process histo;
end behavior;
|
gpl-2.0
|
fd12293fce609e7ea3deb726d9786c46
| 0.577655 | 2.994387 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/MemoriaDeDatos.vhd
| 1 | 3,077 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:34 11/21/2012
-- Design Name:
-- Module Name: MemoriaDeInstrucciones - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemoriaDeDatos is
--generic( P: integer:=32; -- ancho de palabra 32 bits
-- N: integer:=32; -- nº de palabras 32 de 32
--M: integer:= 64; -- grupos de 4 palabras (2^32 / 4)=1073741824
--tam_addr: integer:=5); -- ancho dirección 2^5=32
port( Clock: in std_logic;
ADDR, write_addr: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0);
DW: in std_logic_vector(31 downto 0);
R, W: in std_logic
);
end MemoriaDeDatos;
architecture Behavioral of MemoriaDeDatos is
type mem_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal tmp_mem: mem_type:=(
"00000000000000010000000000100000",--suma
"00000000010000110000000000100000",
"00000000100001010000000000100000",
"00000000110001110000000000100000",
"00000001000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100010",--resta
"00000000000000010000000000100010",
"00000000000000010000000000100010",
"00000000000000010000000000100101",--or
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100100",--and
"00010000000000000000000000000011",--beq
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000",
"00000000000000010000000000100000");
begin
-- Lectura
process(Clock)
begin
if (Clock'event and Clock='1') then
if(R = '1') then
DR <= tmp_mem(conv_integer(ADDR));
else
DR <= (DR' range => 'Z');
end if;
end if;
end process;
-- Escritura
process(Clock)
begin
if (Clock'event and Clock='1') then
if(W = '1') then
tmp_mem(conv_integer(write_addr))<= DW;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
0817e79cd9ccb06e95a4f181aeff3996
| 0.714332 | 4.364539 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/MasterMind_Str.vhd
| 1 | 8,234 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MasterMind_Str is
port( Key0 : in std_logic;
Key1 : in std_logic;
Key2 : in std_logic;
Key3 : in std_logic;
SW0 : in std_logic;
clock : in std_logic;
Hex7 : out std_logic_vector(6 downto 0);
Hex6 : out std_logic_vector(6 downto 0);
Hex5 : out std_logic_vector(6 downto 0);
Hex4 : out std_logic_vector(6 downto 0);
Hex3 : out std_logic_vector(6 downto 0);
Hex2 : out std_logic_vector(6 downto 0);
Hex1 : out std_logic_vector(6 downto 0);
Hex0 : out std_logic_vector(6 downto 0));
end MasterMind_Str;
architecture Structural of MasterMind_Str is
signal clk_2hz, clk_100hz : std_logic;
signal confirm, set, dim, inc : std_logic;
signal s_count, s_resetOut : std_logic;
signal s_ran0, s_ran1, s_ran2, s_ran3 : std_logic_vector(3 downto 0);
signal sel : std_logic_vector(1 downto 0);
signal s_out0, s_out1, s_out2, s_out3 : std_logic;
signal s_up0, s_up1, s_up2, s_up3 : std_logic;
signal s_down0, s_down1, s_down2, s_down3 : std_logic;
signal c0, c1, c2, c3 : std_logic_vector(3 downto 0);
signal reg_Out0, reg_Out1, reg_Out2, reg_Out3 : std_logic_vector(3 downto 0);
signal tent0, tent1 : std_logic_vector(3 downto 0);
signal s_com0, s_com1, s_com2, s_com3 : std_logic;
signal s_blink : std_logic;
signal s_t0, s_t1, s_p, s_n : std_logic_vector(3 downto 0);
signal s_c0, s_c1, s_c2, s_c3 : std_logic_vector(3 downto 0);
signal s_isend : std_logic;
signal s_isblink0, s_isblink1, s_isblink2, s_isblink3 : std_logic;
signal s_cert, s_erra : std_logic_vector(3 downto 0);
signal s_state : std_logic_vector(1 downto 0);
signal s_load : std_logic;
begin
freq_div1: entity work.FreqDivider(Behavioral)
generic map(K => 25000000)
port map(clkIn =>clock,
clkOut=> clk_2hz);
freq_div2: entity work.FreqDivider(Behavioral)
generic map(K => 5000000)
port map(clkIn => clock,
clkOut=> clk_100hz);
deb_0: entity work.Debouncer(Behavioral)
generic map(N => 5)
port map(clk => clk_100hz,
dirty_In => Key0,
cleanOut => set);
deb_1: entity work.Debouncer(Behavioral)
generic map(N => 5)
port map(clk => clk_100hz,
dirty_In => Key1,
cleanOut => inc);
deb_2: entity work.Debouncer(Behavioral)
generic map(N => 5)
port map(clk => clk_100hz,
dirty_In => Key2,
cleanOut => dim);
deb_3: entity work.Debouncer(Behavioral)
generic map(N => 5)
port map(clk => clk_100hz,
dirty_In => Key3,
cleanOut => confirm);
Rand_Num: entity work.RandomNumber(Behavioral)
port map(clock => clock,
stop_signal => Key3,
reset => SW0,
count => s_count,
resetOut => s_resetOut);
Counter9999: entity work.Counter9999(Behavioral)
port map(clk => clock,
enable => s_count,
reset => s_resetOut,
count0 => s_ran0,
count1 => s_ran1,
count2 => s_ran2,
count3 => s_ran3);
Counter4: entity work.Counter4(Behavioral)
port map(clk => clk_100hz,
enable=> set,
reset => SW0,
count => sel);
Demultiplexer: entity work.Demultiplexer(Behavioral)
port map(S => sel,
out1 => s_out0,
out2 => s_out1,
out3 => s_out2,
out4 => s_out3);
s_up0 <= s_out0 and inc;
s_down0 <= s_out0 and dim;
s_up1 <= s_out1 and inc;
s_down1 <= s_out1 and dim;
s_up2 <= s_out2 and inc;
s_down2 <= s_out2 and dim;
s_up3 <= s_out3 and inc;
s_down3 <= s_out3 and dim;
Counter9_0: entity work.Counter9(Behavioral)
port map(clk => clk_100hz,
up => s_up0,
down => s_down0,
reset => SW0,
count => c0);
Counter9_1: entity work.Counter9(Behavioral)
port map(clk => clk_100hz,
up => s_up1,
down => s_down1,
reset => SW0,
count => c1);
Counter9_2: entity work.Counter9(Behavioral)
port map(clk => clk_100hz,
up => s_up2,
down => s_down2,
reset => SW0,
count => c2);
Counter9_3: entity work.Counter9(Behavioral)
port map(clk => clk_100hz,
up => s_up3,
down => s_down3,
reset => SW0,
count => c3);
register_c: entity work.register4(Behavioral)
port map(dataIn0 => c0,
dataIn1 => c1,
dataIn2 => c2,
dataIn3 => c3,
clk => confirm,
reset => SW0,
dataOut0 => reg_Out0,
dataOut1 => reg_Out1,
dataOut2 => reg_Out2,
dataOut3 => reg_Out3);
counter99: entity work.Counter99(Behavioral)
port map(clk => clk_100hz,
enable => confirm,
reset => SW0,
count0 => tent0,
count1 => tent1);
compare: entity work.Compare2(Behavioral)
port map(randomnum0 => s_ran0,
randomnum1 => s_ran1,
randomnum2 => s_ran2,
randomnum3 => s_ran3,
usernum0 => reg_Out0,
usernum1 => reg_Out1,
usernum2 => reg_Out2,
usernum3 => reg_Out3,
cert => s_cert,
erra => s_erra,
clock => clock,
reset => confirm or SW0);
checkEnd: entity work.checkEnd(Behavioral)
port map(try0 => tent0,
try1 => tent1,
clock => confirm,
reset => SW0,
isBlink => s_blink,
p => s_p,
n => s_n,
t1 => s_t1,
t0 => s_t0,
isend => s_isend,
cert => s_cert,
erra => s_erra,
b_load => s_load);
s_isblink0 <= s_blink or s_out0;
s_isblink1 <= s_blink or s_out1;
s_isblink2 <= s_blink or s_out2;
s_isblink3 <= s_blink or s_out3;
blink0: entity work.Blink(Behavioral)
port map(enable => s_isblink0,
numberIn => c0,
numberOut=> s_c0,
clock => clk_2hz,
load => s_load);
blink1: entity work.Blink(Behavioral)
port map(enable => s_isblink1,
numberIn => c1,
numberOut=> s_c1,
clock => clk_2hz,
load => s_load);
blink2: entity work.Blink(Behavioral)
port map(enable => s_isblink2,
numberIn => c2,
numberOut=> s_c2,
clock => clk_2hz,
load => s_load);
blink3: entity work.Blink(Behavioral)
port map(enable => s_isblink3,
numberIn => c3,
numberOut=> s_c3,
clock => clk_2hz,
load => s_load);
bin7segdec0: entity work.Bin7SegDecoder(Behavioral)
port map(enable => '1',
binInput => s_t0,
decOut_n => Hex4);
bin7segdec1: entity work.Bin7SegDecoder(Behavioral)
port map(enable => '1',
binInput => s_t1,
decOut_n => Hex5);
bin7segdec2: entity work.Bin7SegDecoder(Behavioral)
port map(enable => '1',
binInput => s_p,
decOut_n => Hex7);
bin7segdec3: entity work.Bin7SegDecoder(Behavioral)
port map(enable => '1',
binInput => s_n,
decOut_n => Hex6);
bin7segdec4: entity work.Bin7SegDecoder(Behavioral)
port map(enable => not s_isend,
binInput => s_c0,
decOut_n => Hex0);
bin7segdec5: entity work.Bin7SegDecoder(Behavioral)
port map(enable => not s_isend,
binInput => s_c1,
decOut_n => Hex1);
bin7segdec6: entity work.Bin7SegDecoder(Behavioral)
port map(enable => not s_isend,
binInput => s_c2,
decOut_n => Hex2);
bin7segdec7: entity work.Bin7SegDecoder(Behavioral)
port map(enable => not s_isend,
binInput => s_c3,
decOut_n => Hex3);
end Structural;
|
gpl-2.0
|
c1f3658573c6b8cd68a4b414f3b14ae0
| 0.528662 | 2.821796 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/cpuPipeline.vhd
| 1 | 11,261 |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cpuPipeline is
port
(
clk : in std_logic;
reset : in std_logic;
four : INTEGER;
writeToRegisterFile : in std_logic := '0';
writeToMemoryFile : in std_logic := '0'
);
end cpuPipeline;
architecture cpuPipeline_arch of cpuPipeline is
component instructionFetchStage IS
port(
clk : in std_logic;
muxInput0 : in std_logic_vector(31 downto 0);
selectInputs : in std_logic;
four : in INTEGER;
structuralStall : IN STD_LOGIC;
pcStall : IN STD_LOGIC;
selectOutput : out std_logic_vector(31 downto 0);
instructionMemoryOutput : out std_logic_vector(31 downto 0)
);
end component;
component controller is
port(clk : in std_logic;
opcode : in std_logic_vector(5 downto 0);
funct : in std_logic_vector(5 downto 0);
branch: in std_logic;
oldBranch: in std_logic;
ALU1src : out STD_LOGIC;
ALU2src : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemToReg : out STD_LOGIC;
RType : out std_logic;
JType : out std_logic;
Shift : out std_logic;
structuralStall : out std_logic;
ALUOp : out STD_LOGIC_VECTOR(4 downto 0)
);
end component;
component register_file is
PORT(
clock: IN STD_LOGIC;
rs: IN STD_LOGIC_VECTOR (4 downto 0);
rt: IN STD_LOGIC_VECTOR (4 downto 0);
write_enable: IN STD_LOGIC;
rd: IN STD_LOGIC_VECTOR (4 downto 0);
rd_data: IN STD_LOGIC_VECTOR (31 downto 0);
writeToText : IN STD_LOGIC := '0';
ra_data: OUT STD_LOGIC_VECTOR (31 downto 0);
rb_data: OUT STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component signextender is
PORT (
immediate_in: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
immediate_out: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component mux is
port(
input0 : in std_logic_vector(31 downto 0);
input1 : in std_logic_vector(31 downto 0);
selectInput : in std_logic;
selectOutput : out std_logic_vector(31 downto 0)
);
end component;
component alu is
Port ( input_a : in STD_LOGIC_VECTOR (31 downto 0);
input_b : in STD_LOGIC_VECTOR (31 downto 0);
SEL : in STD_LOGIC_VECTOR (4 downto 0);
out_alu : out STD_LOGIC_VECTOR(31 downto 0));
end component;
component zero is
port (input_a : in std_logic_vector (31 downto 0);
input_b : in std_logic_vector (31 downto 0);
optype : in std_logic_vector (4 downto 0);
result: out std_logic
);
end component;
--MEMORY OBJ FOR MEM STAGE
COMPONENT memory IS
GENERIC(
ram_size : INTEGER := 8192;
mem_delay : time := 10 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC := '0';
memread: IN STD_LOGIC := '0';
writeToText : IN STD_LOGIC := '0';
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END COMPONENT;
--MEM STAGE
component mem is
port (clk: in std_logic;
-- Control lines
ctrl_write : in std_logic;
ctrl_read: in std_logic;
ctrl_memtoreg_in: in std_logic;
ctrl_memtoreg_out: out std_logic;
ctrl_regwrite_in: in std_logic;
ctrl_regwrite_out: out std_logic;
ctrl_jal: in std_logic;
--Ports of stage
alu_in : in std_logic_vector (31 downto 0);
alu_out : out std_logic_vector (31 downto 0);
mem_data_in: in std_logic_vector (31 downto 0);
mem_data_out: out std_logic_vector (31 downto 0);
write_addr_in: in std_logic_vector (4 downto 0);
write_addr_out: out std_logic_vector (4 downto 0);
--Memory signals
writedata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
address: OUT INTEGER RANGE 0 TO 32768 -1;
memwrite: OUT STD_LOGIC := '0';
memread: OUT STD_LOGIC := '0';
readdata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: IN STD_LOGIC
);
end component;
component wb is
port (ctrl_memtoreg_in: in std_logic;
ctrl_regwrite_in: in std_logic;
ctrl_regwrite_out: out std_logic;
alu_in : in std_logic_vector (31 downto 0);
mem_in: in std_logic_vector (31 downto 0);
mux_out : out std_logic_vector (31 downto 0);
write_addr_in: in std_logic_vector (4 downto 0);
write_addr_out: out std_logic_vector (4 downto 0)
);
end component;
-- STALL SIGNALS
signal IDEXStructuralStall : std_logic;
signal EXMEMStructuralStall : std_logic;
signal structuralStall : std_logic;
signal pcStall : std_logic;
-- TEST SIGNALS
signal muxInput : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
signal selectInput : std_logic := '1';
signal fourInt : INTEGER := 4;
-- PIPELINE IFID
--address goes to both IFID and IDEX
signal address : std_logic_vector(31 downto 0);
signal instruction : std_logic_vector(31 downto 0);
signal IFIDaddress : std_logic_vector(31 downto 0);
signal IFIDinstruction : std_logic_vector(31 downto 0);
--PIPELINE IDEX
signal IDEXaddress : std_logic_vector(31 downto 0);
signal IDEXra : std_logic_vector(31 downto 0);
signal IDEXrb : std_logic_vector(31 downto 0);
signal IDEXimmediate : std_logic_vector(31 downto 0);
signal IDEXrd : std_logic_vector (4 downto 0);
signal IDEXALU1srcO, IDEXALU2srcO, IDEXMemReadO, IDEXMeMWriteO, IDEXRegWriteO, IDEXMemToRegO: std_logic;
signal IDEXAluOp : std_logic_vector (4 downto 0);
-- SIGNALS FOR CONTROLLER
signal opcodeInput,functInput : std_logic_vector(5 downto 0);
signal ALU1srcO,ALU2srcO,MemReadO,MemWriteO,RegWriteO,MemToRegO,RType,Jtype,Shift: std_logic;
signal ALUOp : std_logic_vector(4 downto 0);
-- SIGNALS FOR REGISTERS
signal rs,rt,rd,WBrd : std_logic_vector (4 downto 0);
signal rd_data: std_logic_vector(31 downto 0);
signal write_enable : std_logic;
signal ra,rb : std_logic_vector(31 downto 0);
signal shamnt : std_logic_vector(4 downto 0);
signal immediate : std_logic_vector(15 downto 0);
signal immediate_out : std_logic_vector(31 downto 0);
-- SIGNALS FOR EXECUTE STAGE
signal muxOutput1 : std_logic_vector(31 downto 0);
signal muxOutput2 : std_logic_vector(31 downto 0);
signal aluOutput : std_logic_vector(31 downto 0);
signal zeroOutput : std_logic;
-- SIGNALS FOR EXMEM
signal EXMEMBranch : std_logic; -- need the zero variable
signal ctrl_jal : std_logic;
signal EXMEMaluOutput : std_logic_vector(31 downto 0);
signal EXMEMregisterOutput : std_logic_vector(31 downto 0);
signal EXMEMrd : std_logic_vector(4 downto 0);
signal EXMEMMemReadO, EXMEMMeMWriteO, EXMEMRegWriteO, EXMEMMemToRegO: std_logic;
-- MEM SIGNALS
signal MEMWBmemOutput : std_logic_vector(31 downto 0);
signal MEMWBaluOutput : std_logic_vector(31 downto 0);
signal MEMWBrd : std_logic_vector(4 downto 0);
signal memtoReg : std_logic;
signal regWrite : std_logic;
signal MEMwritedata : std_logic_vector(31 downto 0);
signal MEMaddress : INTEGER;
signal MEMmemwrite : STD_LOGIC;
signal MEMmemread : STD_LOGIC;
signal MEMreaddata : std_logic_vector(31 downto 0);
signal MEMwaitrequest : STD_LOGIC;
begin
IFS : instructionFetchStage
port map(
clk => clk,
muxInput0 => EXMEMaluOutput,
selectInputs => EXMEMBranch,
four => fourInt,
structuralStall => structuralStall,
pcStall => pcStall,
selectOutput => address,
instructionMemoryOutput => instruction
);
-- DECODE STAGE
CT : controller
port map(
clk => clk,
opcode => opcodeInput,
funct => functInput,
branch => zeroOutput,
oldBranch => EXMEMBranch,
ALU1src => ALU1srcO,
ALU2src => ALU2srcO,
MemRead => MemReadO,
MemWrite => MemWriteO,
RegWrite => RegWriteO,
MemToReg => MemToRegO,
structuralStall => IDEXStructuralStall,
ALUOp => ALUOp,
Shift => Shift,
RType => RType,
JType => JType
);
RegisterFile : register_file
port map (
clock => clk,
rs => rs,
rt => rt,
write_enable => write_enable,
rd => WBrd,
rd_data => rd_data,
writeToText => writeToRegisterFile,
ra_data => ra,
rb_data => rb
);
se : signextender
port map(
immediate_in => immediate,
immediate_out => immediate_out
);
-- EXECUTE STAGE
exMux1 : mux
port map (
input0 => IDEXra,
input1 => IDEXaddress,
selectInput => IDEXALU1srcO,
selectOutput => muxOutput1
);
exMux2 : mux
port map (
input0 => IDEXimmediate,
input1 => IDEXrb,
selectInput => IDEXALU2srcO,
selectOutput => muxOutput2
);
operator : alu
port map(
input_a => muxOutput1,
input_b => muxOutput2,
SEL => IDEXAluOp,
out_alu => aluOutput
);
zr : zero
port map (
input_a => IDEXra,
input_b => IDEXrb,
optype => IDEXAluOp,
result => zeroOutput
);
memStage : mem
port map (
clk =>clk,
-- Control lines
ctrl_write => EXMEMMemWriteO,
ctrl_read => EXMEMMemReadO,
ctrl_memtoreg_in => EXMEMMemToRegO,
ctrl_memtoreg_out => memtoReg,
ctrl_regwrite_in => EXMEMRegWriteO,
ctrl_regwrite_out => regWrite,
ctrl_jal => ctrl_jal,
--Ports of stage
alu_in => EXMEMaluOutput,
alu_out=> MEMWBaluOutput,
mem_data_in => EXMEMregisterOutput,
mem_data_out => MEMWBmemOutput,
write_addr_in => EXMEMrd,
write_addr_out => MEMWBrd,
--Memory signals
writedata => MEMwritedata,
address => MEMaddress,
memwrite => MEMmemwrite,
memread => MEMmemread,
readdata => MEMreaddata,
waitrequest => MEMwaitrequest
);
memMemory: memory
port map (
clock => clk,
writedata => MEMwritedata,
address => MEMaddress,
memwrite => MEMmemwrite,
memread => MEMmemread,
writeToText => writeToMemoryFile,
readdata => MEMreaddata,
waitrequest => MEMwaitrequest
);
wbStage: wb
port map (ctrl_memtoreg_in => memtoReg,
ctrl_regwrite_in => regWrite,
ctrl_regwrite_out => write_enable,
alu_in => MEMWBaluOutput,
mem_in => MEMWBmemOutput,
mux_out => rd_data,
write_addr_in => MEMWBrd,
write_addr_out => WBrd
);
process(EXMEMStructuralStall)
begin
if EXMEMStructuralStall = '1' then
pcStall <= '1';
else
pcStall <= '0';
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
--PIPELINED VALUE
--IFID
IFIDaddress <= address;
IFIDinstruction <= instruction;
-- IDEX
IDEXaddress <= IFIDaddress;
IDEXrb <= rb;
--FOR IMMEDIATE VALUES
if RType = '1' then
IDEXrd <= rd;
-- FOR JAL
elsif ALUOP = "11010" then
IDEXrd <= "11111";
else
IDEXrd <= rt;
end if;
--FOR SHIFT INSTRUCTIONS
if Shift = '1' then
IDEXra <= rb;
else
IDEXra <= ra;
end if;
--FOR JUMP INSTRUCTIONS
if JType = '1' then
IDEXimmediate <= "000000" & IFIDinstruction(25 downto 0);
else
IDEXimmediate <= immediate_out;
end if;
IDEXALU1srcO <= ALU1srcO;
IDEXALU2srcO <= ALU2srcO;
IDEXMemReadO <= MemReadO;
IDEXMeMWriteO <= MemWriteO;
IDEXRegWriteO <= RegWriteO;
IDEXMemToRegO <= MemToRegO;
IDEXAluOp <= ALUOp;
--EXMEM
EXMEMBranch <= zeroOutput;
EXMEMrd <= IDEXrd;
EXMEMMemReadO <= IDEXMemReadO;
EXMEMMeMWriteO <= IDEXMeMWriteO;
EXMEMRegWriteO <= IDEXRegWriteO;
EXMEMMemToRegO <= IDEXMemToRegO;
EXMEMaluOutput <= aluOutput;
EXMEMStructuralStall <= IDEXStructuralStall;
structuralStall <= EXMEMStructuralStall;
--FOR JAL
if IDEXAluOp = "11010" then
EXMEMregisterOutput <= IDEXaddress;
ctrl_jal <= '1';
else
EXMEMregisterOutput <= IDEXrb;
ctrl_jal <= '0';
end if;
end if ;
end process;
-- controller values
opcodeInput <= IFIDinstruction(31 downto 26);
functInput <= IFIDinstruction(5 downto 0);
-- register values
rs <= IFIDinstruction(25 downto 21);
rt <= IFIDinstruction(20 downto 16);
rd <= IFIDinstruction(15 downto 11);
shamnt <= IFIDinstruction(10 downto 6);
-- EXTENDED
immediate <= IFIDinstruction(15 downto 0);
-- MIGHT NEED TO PUT WRITE ENABLE HERE LATER
-- AND JUMP ADDRESS HERE
end cpuPipeline_arch;
|
gpl-3.0
|
46b275b41321905eb8afa49ad983d239
| 0.710061 | 3.138517 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/mem.vhd
| 1 | 2,174 |
library ieee;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem is
GENERIC(
ram_size : INTEGER := 8192;
mem_delay : time := 10 ns;
clock_period : time := 1 ns
);
port (clk: in std_logic;
-- Control lines
ctrl_write : in std_logic;
ctrl_read: in std_logic;
ctrl_memtoreg_in: in std_logic;
ctrl_memtoreg_out: out std_logic;
ctrl_regwrite_in: in std_logic;
ctrl_regwrite_out: out std_logic;
ctrl_jal: in std_logic;
--Ports of stage
alu_in : in std_logic_vector (31 downto 0);
alu_out : out std_logic_vector (31 downto 0);
mem_data_in: in std_logic_vector (31 downto 0);
mem_data_out: out std_logic_vector (31 downto 0);
write_addr_in: in std_logic_vector (4 downto 0);
write_addr_out: out std_logic_vector (4 downto 0);
--Memory signals
writedata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
address: OUT INTEGER RANGE 0 TO ram_size-1;
memwrite: OUT STD_LOGIC := '0';
memread: OUT STD_LOGIC := '0';
readdata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: IN STD_LOGIC
);
end mem;
architecture behavioral of mem is
signal mem_data_next, alu_next, address_next: std_logic_vector (31 downto 0);
signal write_addr_next: std_logic_vector (4 downto 0);
signal ctrl_memtoreg_next, ctrl_regwrite_next: std_logic;
begin
process (clk)
begin
if (clk'event and clk = '1') then
write_addr_out <= write_addr_next;
mem_data_out <= mem_data_next;
alu_out <= alu_next;
ctrl_regwrite_out <= ctrl_regwrite_next;
ctrl_memtoreg_out <= ctrl_memtoreg_next;
end if;
end process;
process (write_addr_in , ctrl_memtoreg_in, ctrl_regwrite_in, alu_in)
begin
memwrite <= '0';
memread <= '0';
--Propogate signals
write_addr_next <= write_addr_in;
ctrl_memtoreg_next <= ctrl_memtoreg_in;
ctrl_regwrite_next <= ctrl_regwrite_in;
--FOR JAL
if ctrl_jal = '1' then
alu_next <= mem_data_in;
else
alu_next <= alu_in;
end if;
--Access memory
if ctrl_write = '1' then
address <= to_integer(unsigned(alu_in));
memwrite <= '1';
writedata <= mem_data_in;
elsif ctrl_read = '1' then
address <= to_integer(unsigned(alu_in));
memread <= '1';
end if;
end process;
mem_data_next <= readdata;
end behavioral;
|
gpl-3.0
|
e60bb1b4aeb567fe2475c75c776cbb88
| 0.675713 | 2.794344 | false | false | false | false |
universal-ctags/ctags
|
Units/review-needed.r/test.vhd.t/input.vhd
| 2 | 192,382 |
package body badger is
end package body;
package body badger2 is
end package body badger2;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity accumulator is port (
a: in std_logic_vector(3 downto 0);
clk, reset: in std_logic;
accum: out std_logic_vector(3 downto 0)
);
end accumulator;
architecture simple of accumulator is
signal accumL: unsigned(3 downto 0);
begin
accumulate: process (clk, reset) begin
if (reset = '1') then
accumL <= "0000";
elsif (clk'event and clk= '1') then
accumL <= accumL + to_unsigned(a);
end if;
end process;
accum <= std_logic_vector(accumL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is port (
a,b : in std_logic_vector (15 downto 0);
sum: out std_logic_vector (15 downto 0)
);
end adder;
architecture dataflow of adder is
begin
sum <= a + b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity pAdderAttr is
generic(n : integer := 8);
port (a : in std_logic_vector(n - 1 downto 0);
b : in std_logic_vector(n - 1 downto 0);
cin : in std_logic;
sum : out std_logic_vector(n - 1 downto 0);
cout : out std_logic);
end pAdderAttr;
architecture loopDemo of pAdderAttr is
begin
process(a, b, cin)
variable carry: std_logic_vector(sum'length downto 0);
variable localSum: std_logic_vector(sum'high downto 0);
begin
carry(0) := cin;
for i in sum'reverse_range loop
localSum(i) := (a(i) xor b(i)) xor carry(i);
carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
end loop;
sum <= localSum;
cout <= carry(carry'high - 1);
end process;
end loopDemo;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in unsigned(3 downto 0);
sum: out unsigned(3 downto 0)
);
end adder;
architecture simple of adder is
begin
sum <= a + b;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity asyncLoad is port (
loadVal, d: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLoad;
architecture rtl of asyncLoad is
begin
process (clk, load, loadVal) begin
if (load = '1') then
q <= loadVal;
elsif (clk'event and clk = '1' ) then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BidirBuf is port (
OE: in std_logic;
input: in std_logic_vector;
output: out std_logic_vector
);
end BidirBuf;
architecture behavioral of BidirBuf is
begin
bidirBuf: process (OE, input) begin
if (OE = '1') then
output <= input;
else
output <= (others => 'Z');
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BidirCnt is port (
OE: in std_logic;
CntEnable: in std_logic;
LdCnt: in std_logic;
Clk: in std_logic;
Rst: in std_logic;
Cnt: inout std_logic_vector(3 downto 0)
);
end BidirCnt;
architecture behavioral of BidirCnt is
component LoadCnt port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end component;
component BidirBuf port (
OE: in std_logic;
input: in std_logic_vector;
output: inout std_logic_vector
);
end component;
signal CntVal: std_logic_vector(3 downto 0);
signal LoadVal: std_logic_vector(3 downto 0);
begin
u1: loadcnt port map (CntEn => CntEnable,
LdCnt => LdCnt,
LdData => LoadVal,
Clk => Clk,
Rst => Rst,
CntVal => CntVal
);
u2: bidirbuf port map (OE => oe,
input => CntVal,
output => Cnt
);
LoadVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity bidirbuffer is port (
input: in std_logic;
enable: in std_logic;
feedback: out std_logic;
output: inout std_logic
);
end bidirbuffer;
architecture structural of bidirbuffer is
begin
u1: bidir port map (ip => input,
oe => enable,
op_fb => feedback,
op => output
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity clkGen is port (
clk: in std_logic;
reset: in std_logic;
ClkDiv2, ClkDiv4,
ClkDiv6,ClkDiv8: out std_logic
);
end clkGen;
architecture behav of clkGen is
subtype numClks is std_logic_vector(1 to 4);
subtype numPatterns is integer range 0 to 11;
type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
constant clkTable: clkTableType := clkTableType'(
-- ClkDiv8______
-- ClkDiv6_____ |
-- ClkDiv4____ ||
-- ClkDiv2 __ |||
-- ||||
"1111",
"0111",
"1011",
"0001",
"1100",
"0100",
"1010",
"0010",
"1111",
"0001",
"1001",
"0101");
signal index: numPatterns;
begin
lookupTable: process (clk, reset) begin
if reset = '1' then
index <= 0;
elsif (clk'event and clk = '1') then
if index = numPatterns'high then
index <= numPatterns'low;
else
index <= index + 1;
end if;
end if;
end process;
(ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
end behav;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
enable: in std_logic;
reset: in std_logic;
count: buffer unsigned(3 downto 0)
);
end counter;
architecture simple of counter is
begin
increment: process (clk, reset) begin
if reset = '1' then
count <= "0000";
elsif(clk'event and clk = '1') then
if enable = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.scaleable.all;
entity count8 is port (
clk: in std_logic;
rst: in std_logic;
count: out std_logic_vector(7 downto 0)
);
end count8;
architecture structural of count8 is
begin
u1: scaleUpCnt port map (clk => clk,
reset => rst,
cnt => count
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 9)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 9);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(3,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(9 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(9 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= to_unsigned(0,10);
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
enable: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
elsif (enable = '1') then
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
load: in std_logic;
data: in std_logic_vector(3 downto 0);
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
if (load = '1') then
countL <= to_unsigned(data);
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Cnt4Term is port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic
);
end Cnt4Term;
architecture behavioral of Cnt4Term is
signal CntL: unsigned(3 downto 0);
begin
increment: process begin
wait until clk = '1';
CntL <= CntL + 1;
end process;
Cnt <= to_stdlogicvector(CntL);
TermCnt <= '1' when CntL = "1111" else '0';
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity Counter is port (
clock: in std_logic;
Count: out std_logic_vector(3 downto 0)
);
end Counter;
architecture structural of Counter is
component Cnt4Term port (
clk: in std_logic;
Cnt: out std_logic_vector(3 downto 0);
TermCnt: out std_logic);
end component;
begin
u1: Cnt4Term port map (clk => clock,
Cnt => Count,
TermCnt => open
);
end structural;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if(clk'event and clk = '1') then
if (reset = '1') then
countL <= "0000";
else
countL <= countL + 1;
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convertArith is port (
truncate: out unsigned(3 downto 0);
extend: out unsigned(15 downto 0);
direction: out unsigned(0 to 7)
);
end convertArith;
architecture simple of convertArith is
constant Const: unsigned(7 downto 0) := "00111010";
begin
truncate <= resize(Const, truncate'length);
extend <= resize(Const, extend'length);
direction <= resize(Const, direction'length);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
constant THREE: std_logic_vector(1 downto 0) := "11";
begin
y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
end concurrent;
-- incorporates Errata 12.1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity typeConvert is port (
a: out unsigned(7 downto 0)
);
end typeConvert;
architecture simple of typeConvert is
constant Const: natural := 43;
begin
a <= To_unsigned(Const,8);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk) begin
if (clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(0 to 3)
);
end counter;
architecture simple of counter is
signal countL: unsigned(0 to 3);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "0000";
elsif(clk'event and clk = '1') then
countL <= countL + "001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if reset = '1' then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + 1;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture simple of counter is
signal countL: unsigned(3 downto 0);
begin
increment: process (clk, reset) begin
if (reset = '1') then
countL <= "1001";
elsif(clk'event and clk = '1') then
countL <= countL + "0001";
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
use work.decProcs.all;
entity decoder is port (
decIn: in std_logic_vector(1 downto 0);
decOut: out std_logic_vector(3 downto 0)
);
end decoder;
architecture simple of decoder is
begin
DEC2x4(decIn,decOut);
end simple;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
decOut_n: out std_logic_vector(5 downto 0)
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
alias sio_dec_n: std_logic is decOut_n(5);
alias rst_ctrl_rd_n: std_logic is decOut_n(4);
alias atc_stat_rd_n: std_logic is decOut_n(3);
alias mgmt_stat_rd_n: std_logic is decOut_n(2);
alias io_int_stat_rd_n: std_logic is decOut_n(1);
alias int_ctrl_rd_n: std_logic is decOut_n(0);
alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
begin
decoder: process (upper, CtrlBits)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case upper is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case CtrlBits is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process (dev_adr, cs0_n)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
case dev_adr(19 downto 17) is
when SuperIoRange =>
sio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
int_ctrl_rd_n <= '0';
when IoIntStatReg =>
io_int_stat_rd_n <= '0';
when RstCtrlReg =>
rst_ctrl_rd_n <= '0';
when AtcStatusReg =>
atc_stat_rd_n <= '0';
when MgmtStatusReg =>
mgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
else
null;
end if;
end process decoder;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
cs0_n: in std_logic;
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
signal Lsio_dec_n: std_logic;
signal Lrst_ctrl_rd_n: std_logic;
signal Latc_stat_rd_n: std_logic;
signal Lmgmt_stat_rd_n: std_logic;
signal Lio_int_stat_rd_n: std_logic;
signal Lint_ctrl_rd_n: std_logic;
begin
decoder: process (dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
Lsio_dec_n <= '1';
Lint_ctrl_rd_n <= '1';
Lio_int_stat_rd_n <= '1';
Lrst_ctrl_rd_n <= '1';
Latc_stat_rd_n <= '1';
Lmgmt_stat_rd_n <= '1';
case dev_adr(19 downto 17) is
when SuperIoRange =>
Lsio_dec_n <= '0';
when CtrlRegRange =>
case dev_adr(16 downto 0) is
when IntCtrlReg =>
Lint_ctrl_rd_n <= '0';
when IoIntStatReg =>
Lio_int_stat_rd_n <= '0';
when RstCtrlReg =>
Lrst_ctrl_rd_n <= '0';
when AtcStatusReg =>
Latc_stat_rd_n <= '0';
when MgmtStatusReg =>
Lmgmt_stat_rd_n <= '0';
when others =>
null;
end case;
when others =>
null;
end case;
end process decoder;
qualify: process (cs0_n) begin
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if (cs0_n = '0') then
sio_dec_n <= Lsio_dec_n;
int_ctrl_rd_n <= Lint_ctrl_rd_n;
io_int_stat_rd_n <= Lio_int_stat_rd_n;
rst_ctrl_rd_n <= Lrst_ctrl_rd_n;
atc_stat_rd_n <= Latc_stat_rd_n;
mgmt_stat_rd_n <= Lmgmt_stat_rd_n;
else
null;
end if;
end process qualify;
end synthesis;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n: out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
decoder: process ( dev_adr)
begin
-- Set defaults for outputs - for synthesis reasons.
sio_dec_n <= '1';
int_ctrl_rd_n <= '1';
io_int_stat_rd_n <= '1';
rst_ctrl_rd_n <= '1';
atc_stat_rd_n <= '1';
mgmt_stat_rd_n <= '1';
if dev_adr(19 downto 17) = SuperIOrange then
sio_dec_n <= '0';
elsif dev_adr(19 downto 17) = CtrlRegrange then
if dev_adr(16 downto 0) = IntCtrlReg then
int_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0)= IoIntStatReg then
io_int_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = RstCtrlReg then
rst_ctrl_rd_n <= '0';
elsif dev_adr(16 downto 0) = AtcStatusReg then
atc_stat_rd_n <= '0';
elsif dev_adr(16 downto 0) = MgmtStatusReg then
mgmt_stat_rd_n <= '0';
else
null;
end if;
else
null;
end if;
end process decoder;
end synthesis;
library IEEE;
use IEEE.std_logic_1164.all;
package decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
);
end decProcs;
package body decProcs is
procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
decode: out std_logic_vector(3 downto 0)
) is
begin
case inputs is
when "11" =>
decode := "1000";
when "10" =>
decode := "0100";
when "01" =>
decode := "0010";
when "00" =>
decode := "0001";
when others =>
decode := "0001";
end case;
end DEC2x4;
end decProcs;
library ieee;
use ieee.std_logic_1164.all;
entity isa_dec is port
(
dev_adr: in std_logic_vector(19 downto 0);
sio_dec_n: out std_logic;
rst_ctrl_rd_n: out std_logic;
atc_stat_rd_n: out std_logic;
mgmt_stat_rd_n: out std_logic;
io_int_stat_rd_n:out std_logic;
int_ctrl_rd_n: out std_logic
);
end isa_dec;
architecture synthesis of isa_dec is
constant CtrlRegRange: std_logic_vector(2 downto 0) := "100";
constant SuperIoRange: std_logic_vector(2 downto 0) := "010";
constant IntCtrlReg: std_logic_vector(16 downto 0) := "00000000000000000";
constant IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
constant RstCtrlReg: std_logic_vector(16 downto 0) := "00000000000000010";
constant AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
constant MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
begin
with dev_adr(19 downto 17) select
sio_dec_n <= '0' when SuperIORange,
'1' when others;
with dev_adr(19 downto 0) select
int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
'1' when others;
with dev_adr(19 downto 0) select
rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
'1' when others;
with dev_adr(19 downto 0) select
atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
'1' when others;
with dev_adr(19 downto 0) select
mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
'1' when others;
end synthesis;
-- Incorporates Errata 5.1 and 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal delayCnt, pulseCnt: unsigned(7 downto 0);
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
begin
delayReg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
pulseCntVal <= unsigned(data);
end if;
end if;
end process;
pulseDelay: process (clk, reset) begin
if (reset = '1') then
delayCnt <= "11111111";
elsif(clk'event and clk = '1') then
if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
delayCnt <= delayCntVal;
elsif endPulse = '1' then
delayCnt <= delayCnt - 1;
end if;
end if;
end process;
startPulse <= '1' when delayCnt = "00000000" else '0';
pulseLength: process (clk, reset) begin
if (reset = '1') then
pulseCnt <= "11111111";
elsif (clk'event and clk = '1') then
if (loadLength = '1') then
pulseCnt <= pulseCntVal;
elsif (startPulse = '1' and endPulse = '1') then
pulseCnt <= pulseCntVal;
elsif (endPulse = '1') then
pulseCnt <= pulseCnt;
else
pulseCnt <= pulseCnt - 1;
end if;
end if;
end process;
endPulse <= '1' when pulseCnt = "00000000" else '0';
pulseOutput: process (clk, reset) begin
if (reset = '1') then
pulse <= '0';
elsif (clk'event and clk = '1') then
if (startPulse = '1') then
pulse <= '1';
elsif (endPulse = '1') then
pulse <= '0';
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst : in std_logic;
q: out std_logic;
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, a,b,c) begin
if ((a = '1' and b = '1') or c = '1') then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
a,b,c : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
signal localRst: std_logic;
begin
localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
process (clk, localRst) begin
if localRst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
arst: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
aset : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, aset) begin
if aset = '1' then
q <= '1';
elsif clk'event and clk = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
arst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk, arst) begin
if arst = '1' then
q1 <= '0';
q2 <= '1';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
wait on clk;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
envector: in std_logic_vector(7 downto 0);
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if envector = "10010111" then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if en = '1' then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (prst = '1') then
q <= '1';
elsif (rst = '1') then
q <= '0';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity flipFlop is port (
clock, input: in std_logic;
ffOut: out std_logic
);
end flipFlop;
architecture simple of flipFlop is
procedure dff (signal clk: in std_logic;
signal d: in std_logic;
signal q: out std_logic
) is
begin
if clk'event and clk = '1' then
q <= d;
end if;
end procedure dff;
begin
dff(clock, input, ffOut);
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
end: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until rising_edge(clk);
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1, d2: in std_logic;
clk: in std_logic;
srst : in std_logic;
q1, q2: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q1 <= '0';
q2 <= '1';
else
q1 <= d1;
q2 <= d2;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe_sr is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
rst,prst: in std_logic;
q: out std_logic
);
end struct_dffe_sr;
use work.primitive.all;
architecture instance of struct_dffe_sr is
begin
ff: dffe_sr port map (
d => d,
clk => clk,
en => en,
rst => rst,
prst => prst,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
srst : in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
if clk'event and clk = '1' then
if srst = '1' then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dffe is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dffe;
use work.primitive.all;
architecture instance of struct_dffe is
begin
ff: dffe port map (
d => d,
clk => clk,
en => en,
q => q
);
end instance;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity dffTri is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end dffTri;
architecture parameterize of dffTri is
type tribufType is record
ip: std_logic;
oe: std_logic;
op: std_logic;
end record;
type tribufArrayType is array (integer range <>) of tribufType;
signal tri: tribufArrayType(size - 1 downto 0);
begin
g0: for i in 0 to size - 1 generate
u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
end generate;
g1: for i in 0 to size - 1 generate
u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
tri(i).oe <= op_enable;
qout(i) <= tri(i).op;
end generate;
end parameterize;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
en: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic bus
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
signal qLocal: std_logic;
begin
qLocal <= d when en = '1' else qLocal;
q <= qLocal;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en, d) begin
if en = '1' then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity struct_dlatch is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end struct_dlatch;
use work.primitive.all;
architecture instance of struct_dlatch is
begin
latch: dlatchh port map (
d => d,
en => en,
q => q
);
end instance;
-- Incorporates Errata 5.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity downCounter is port (
clk: in std_logic;
reset: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end downCounter;
architecture simple of downCounter is
signal countL: unsigned(3 downto 0);
signal termCnt: std_logic;
begin
decrement: process (clk, reset) begin
if (reset = '1') then
countL <= "1011"; -- Reset to 11
termCnt <= '1';
elsif(clk'event and clk = '1') then
if (termCnt = '1') then
countL <= "1011"; -- Count rolls over to 11
else
countL <= countL - 1;
end if;
if (countL = "0001") then -- Terminal count decoded 1 cycle earlier
termCnt <= '1';
else
termCnt <= '0';
end if;
end if;
end process;
count <= std_logic_vector(countL);
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compareDC is port (
addressBus: in std_logic_vector(31 downto 0);
addressHit: out std_logic
);
end compareDC;
architecture wontWork of compareDC is
begin
compare: process(addressBus) begin
if (addressBus = "011110101011--------------------") then
addressHit <= '1';
else
addressHit <= '0';
end if;
end process compare;
end wontWork;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
encode: process (invec) begin
case invec is
when "00000001" =>
enc_out <= "000";
when "00000010" =>
enc_out <= "001";
when "00000100" =>
enc_out <= "010";
when "00001000" =>
enc_out <= "011";
when "00010000" =>
enc_out <= "100";
when "00100000" =>
enc_out <= "101";
when "01000000" =>
enc_out <= "110";
when "10000000" =>
enc_out <= "111";
when others =>
enc_out <= "000";
end case;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec:in std_logic_vector(7 downto 0);
enc_out:out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
process (invec)
begin
if invec(7) = '1' then
enc_out <= "111";
elsif invec(6) = '1' then
enc_out <= "110";
elsif invec(5) = '1' then
enc_out <= "101";
elsif invec(4) = '1' then
enc_out <= "100";
elsif invec(3) = '1' then
enc_out <= "011";
elsif invec(2) = '1' then
enc_out <= "010";
elsif invec(1) = '1' then
enc_out <= "001";
elsif invec(0) = '1' then
enc_out <= "000";
else
enc_out <= "000";
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port (invec: in std_logic_vector(7 downto 0);
enc_out: out std_logic_vector(2 downto 0)
);
end encoder;
architecture rtl of encoder is
begin
enc_out <= "111" when invec(7) = '1' else
"110" when invec(6) = '1' else
"101" when invec(5) = '1' else
"100" when invec(4) = '1' else
"011" when invec(3) = '1' else
"010" when invec(2) = '1' else
"001" when invec(1) = '1' else
"000" when invec(0) = '1' else
"000";
end rtl;
-- includes Errata 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- errata 5.2
entity compare is port (
ina: in std_logic_vector (3 downto 0);
inb: in std_logic_vector (2 downto 0);
equal: out std_logic
);
end compare;
architecture simple of compare is
begin
equalProc: process (ina, inb) begin
if (ina = inb ) then
equal <= '1';
else
equal <= '0';
end if;
end process;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture behavioral of LogicFcn is
begin
fcn: process (A,B,C) begin
if (A = '0' and B = '0') then
Y <= '1';
elsif C = '1' then
Y <= '1';
else
Y <= '0';
end if;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture dataflow of LogicFcn is
begin
Y <= '1' when (A = '0' AND B = '0') OR
(C = '1')
else '0';
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity LogicFcn is port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic
);
end LogicFcn;
architecture structural of LogicFcn is
signal notA, notB, andSignal: std_logic;
begin
i1: inverter port map (i => A,
o => notA);
i2: inverter port map (i => B,
o => notB);
a1: and2 port map (i1 => notA,
i2 => notB,
y => andSignal);
o1: or2 port map (i1 => andSignal,
i2 => C,
y => Y);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is port (
D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
constant tCQ: time := 8 ns;
constant tS: time := 4 ns;
constant tH: time := 3 ns;
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process (clk) begin
wait until clk = '1';
q <= d;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d: in std_logic;
clk: in std_logic;
q: out std_logic
);
end DFF;
architecture rtl of DFF is
begin
process begin
wait until clk = '1';
q <= d;
wait on clk;
end process;
end rtl;
configuration SimpleGatesCfg of FEWGATES is
for structural
for all: AND2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
configuration SimpleGatesCfg of FEWGATES is
for structural
for u1: and2
use entity work.and2(rtl);
end for;
for u2: and2
use entity work.and2(rtl);
end for;
for u3: inverter
use entity work.inverter(rtl);
end for;
for u4: or2
use entity work.or2(rtl);
end for;
end for;
end SimpleGatesCfg;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.and2;
use work.or2;
use work.inverter;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
-- Configution specifications
for all: and2 use entity work.and2(rtl);
for u3: inverter use entity work.inverter(rtl);
for u4: or2 use entity work.or2(rtl);
begin
u1: and2 port map (i1 => a, i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c, i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
use work.GatesPkg.all;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture concurrent of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
a_and_b <= '1' when a = '1' and b = '1' else '0';
c_and_d <= '1' when c = '1' and d = '1' else '0';
not_c_and_d <= not c_and_d;
y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
package GatesPkg is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
end GatesPkg;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 =>c,
i2 => d,
y => c_and_d
);
u3: inverter port map (a => c_and_d,
y => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity FEWGATES is port (
a,b,c,d: in std_logic;
y: out std_logic
);
end FEWGATES;
architecture structural of FEWGATES is
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
signal a_and_b, c_and_d, not_c_and_d: std_logic;
begin
u1: and2 port map (i1 => a ,
i2 => b,
y => a_and_b
);
u2: and2 port map (i1 => c,
i2 => d,
y => c_and_d
);
u3: inverter port map (i => c_and_d,
o => not_c_and_d);
u4: or2 port map (i1 => a_and_b,
i2 => not_c_and_d,
y => y
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.simPrimitives.all;
entity simHierarchy is port (
A, B, Clk: in std_logic;
Y: out std_logic
);
end simHierarchy;
architecture hierarchical of simHierarchy is
signal ADly, BDly, OrGateDly, ClkDly: std_logic;
signal OrGate, FlopOut: std_logic;
begin
ADly <= transport A after 2 ns;
BDly <= transport B after 2 ns;
OrGateDly <= transport OrGate after 1.5 ns;
ClkDly <= transport Clk after 1 ns;
u1: OR2 generic map (tPD => 10 ns)
port map ( I1 => ADly,
I2 => BDly,
Y => OrGate
);
u2: simDFF generic map ( tS => 4 ns,
tH => 3 ns,
tCQ => 8 ns
)
port map ( D => OrGateDly,
Clk => ClkDly,
Q => FlopOut
);
Y <= transport FlopOut after 2 ns;
end hierarchical;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
--------------------------------------------------------------------------------
--| File name : $RCSfile: io1164.vhd $
--| Library : SUPPORT
--| Revision : $Revision: 1.1 $
--| Author(s) : Vantage Analysis Systems, Inc; Des Young
--| Integration : Des Young
--| Creation : Nov 1995
--| Status : $State: Exp $
--|
--| Purpose : IO routines for std_logic_1164.
--| Assumptions : Numbers use radixed character set with no prefix.
--| Limitations : Does not read VHDL pound-radixed numbers.
--| Known Errors: none
--|
--| Description:
--| This is a modified library. The source is basically that donated by
--| Vantage to libutil. Des Young removed std_ulogic_vector support (to
--| conform to synthesizable libraries), and added read_oct/hex to integer.
--|
--| =======================================================================
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
--| reserved. This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package VHDL source
--| Package Name: somelib.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : * Overloads procedures READ and WRITE for STD_LOGIC types
--| in manner consistent with TEXTIO package.
--| * Provides procedures to read and write logic values as
--| binary, octal, or hexadecimal values ('X' as appropriate).
--| These should be particularly useful for models
--| to read in stimulus as 0/1/x or octal or hex.
--| Subprograms :
--| Notes :
--| History : 1. Donated to libutil by Dave Bernstein 15 Jun 94
--| 2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
--| (This is because that type is not supported for synthesis).
--| 3. Added read_oct/hex to integer, Des Young, 20 Nov 95
--|
--| =======================================================================
--| Extra routines by Des Young, [email protected]. 1995. GNU copyright.
--| =======================================================================
--|
--------------------------------------------------------------------------------
library ieee;
package io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- import std_logic package
use ieee.std_logic_1164.all;
-- import textio package
use std.textio.all;
--
-- the READ and WRITE procedures act similarly to the procedures in the
-- STD.TEXTIO package. for each type, there are two read procedures and
-- one write procedure for converting between character and internal
-- representations of values. each value is represented as the string of
-- characters that you would use in VHDL code. (remember that apostrophes
-- and quotation marks are not used.) input is case-insensitive. output
-- is in upper case. see the following LRM sections for more information:
--
-- 2.3 - Subprogram Overloading
-- 3.3 - Access Types (STD.TEXTIO.LINE is an access type)
-- 7.3.6 - Allocators (allocators create access values)
-- 14.3 - Package TEXTIO
--
-- Note that the procedures for std_ulogic will match calls with the value
-- parameter of type std_logic.
--
-- declare READ procedures to overload like in TEXTIO
--
procedure read(l: inout line; value: out std_ulogic ; good: out boolean);
procedure read(l: inout line; value: out std_ulogic );
procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
procedure read(l: inout line; value: out std_logic_vector );
--
-- declare WRITE procedures to overload like in TEXTIO
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 );
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 );
--
-- declare procedures to convert between logic values and octal
-- or hexadecimal ('X' where appropriate).
--
-- octal / std_logic_vector
procedure read_oct (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_oct (l : inout line ;
value : out std_logic_vector );
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- hexadecimal / std_logic_vector
procedure read_hex (l : inout line ;
value : out std_logic_vector ;
good : out boolean );
procedure read_hex (l : inout line ;
value : out std_logic_vector );
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified : in side := right;
field : in width := 0 );
-- read a number into an integer
procedure read_oct(l : inout line;
value : out integer;
good : out boolean);
procedure read_oct(l : inout line;
value : out integer);
procedure read_hex(l : inout line;
value : out integer;
good : out boolean);
procedure read_hex(l : inout line;
value : out integer);
end io1164;
--------------------------------------------------------------------------------
--| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
--| This package is provided by Vantage Analysis Systems.
--| The package may not be sold without the express written consent of
--| Vantage Analysis Systems, Inc.
--|
--| The VHDL for this package may be copied and/or distributed as long as
--| this copyright notice is retained in the source and any modifications
--| are clearly marked in the History: list.
--|
--| Title : IO1164 package body VHDL source
--| Package Name: VANTAGE_LOGIC.IO1164
--| File Name : io1164.vhdl
--| Author(s) : dbb
--| Purpose : source for IO1164 package body
--| Subprograms :
--| Notes : see package declaration
--| History : see package declaration
--------------------------------------------------------------------------------
package body io1164 is
--$ !VANTAGE_METACOMMENTS_ON
--$ !VANTAGE_DNA_ON
-- define lowercase conversion of characters for canonical comparison
type char2char_t is array (character'low to character'high) of character;
constant lowcase: char2char_t := (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del);
-- define conversions between various types
-- logic -> character
type f_logic_to_character_t is
array (std_ulogic'low to std_ulogic'high) of character;
constant f_logic_to_character : f_logic_to_character_t :=
(
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-'
);
-- character, integer, logic
constant x_charcode : integer := -1;
constant maxoct_charcode: integer := 7;
constant maxhex_charcode: integer := 15;
constant bad_charcode : integer := integer'left;
type digit2int_t is
array ( character'low to character'high ) of integer;
constant octdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7,
'X' | 'x' => x_charcode, others => bad_charcode );
constant hexdigit2int: digit2int_t := (
'0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
'5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9,
'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
'X' | 'x' => x_charcode, others => bad_charcode );
constant oct_bits_per_digit: integer := 3;
constant hex_bits_per_digit: integer := 4;
type int2octdigit_t is
array ( 0 to maxoct_charcode ) of character;
constant int2octdigit: int2octdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7' );
type int2hexdigit_t is
array ( 0 to maxhex_charcode ) of character;
constant int2hexdigit: int2hexdigit_t :=
( 0 => '0', 1 => '1', 2 => '2', 3 => '3',
4 => '4', 5 => '5', 6 => '6', 7 => '7',
8 => '8', 9 => '9', 10 => 'A', 11 => 'B',
12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
type oct_logic_vector_t is
array(1 to oct_bits_per_digit) of std_ulogic;
type octint2logic_t is
array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
constant octint2logic : octint2logic_t := (
( 'X', 'X', 'X' ),
( '0', '0', '0' ),
( '0', '0', '1' ),
( '0', '1', '0' ),
( '0', '1', '1' ),
( '1', '0', '0' ),
( '1', '0', '1' ),
( '1', '1', '0' ),
( '1', '1', '1' )
);
type hex_logic_vector_t is
array(1 to hex_bits_per_digit) of std_ulogic;
type hexint2logic_t is
array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
constant hexint2logic : hexint2logic_t := (
( 'X', 'X', 'X', 'X' ),
( '0', '0', '0', '0' ),
( '0', '0', '0', '1' ),
( '0', '0', '1', '0' ),
( '0', '0', '1', '1' ),
( '0', '1', '0', '0' ),
( '0', '1', '0', '1' ),
( '0', '1', '1', '0' ),
( '0', '1', '1', '1' ),
( '1', '0', '0', '0' ),
( '1', '0', '0', '1' ),
( '1', '0', '1', '0' ),
( '1', '0', '1', '1' ),
( '1', '1', '0', '0' ),
( '1', '1', '0', '1' ),
( '1', '1', '1', '0' ),
( '1', '1', '1', '1' )
);
----------------------------------------------------------------------------
-- READ procedure bodies
--
-- The strategy for duplicating TEXTIO's overloading of procedures
-- with and without GOOD parameters is to put all the logic in the
-- version with the GOOD parameter and to have the version without
-- GOOD approximate a runtime error by use of an assertion.
--
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
variable c : character; -- char read while looping
variable m : line; -- safe copy of L
variable success: boolean := false; -- readable version of GOOD
variable done : boolean := false; -- flag to say done reading chars
begin
--
-- algorithm:
--
-- if there are characters in the line
-- save a copy of the line
-- get the next character
-- if got one
-- set value
-- if all ok
-- free temp copy
-- else
-- free passed in line
-- assign copy back to line
-- set GOOD
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- grab the next character
read( l, c, success );
-- if read ok
if success then
--
-- an issue here is whether lower-case values should be accepted or not
--
-- determine the value
case c is
when 'U' | 'u' => value := 'U';
when 'X' | 'x' => value := 'X';
when '0' => value := '0';
when '1' => value := '1';
when 'Z' | 'z' => value := 'Z';
when 'W' | 'w' => value := 'W';
when 'L' | 'l' => value := 'L';
when 'H' | 'h' => value := 'H';
when '-' => value := '-';
when others => success := false;
end case;
end if;
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
end if; -- non null access, non empty string
-- set output parameter
good := success;
end read;
procedure read( l: inout line; value: out std_ulogic ) is
variable success: boolean; -- internal good flag
begin
read( l, value, success ); -- use safe version
assert success
report "IO1164.READ: Unable to read STD_ULOGIC value."
severity error;
end read;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure read(l : inout line ;
value: out std_logic_vector;
good : out boolean ) is
variable m : line ; -- saved copy of L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- value for one array element
variable c : character ; -- read a character
begin
--
-- algorithm:
--
-- this procedure strips off leading whitespace, and then calls the
-- READ procedure for each single logic value element in the output
-- array.
--
-- only operate on lines that contain characters
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save a copy of string in case read fails
m := new string'( l.all );
-- loop for each element in output array
for i in value'range loop
-- prohibit internal blanks
if i /= value'left then
if l.all'length = 0 then
success := false;
exit;
end if;
c := l.all(l.all'left);
if c = ' ' or c = ht then
success := false;
exit;
end if;
end if;
-- read the next logic value
read( l, logic_value, success );
-- stuff the value in if ok, else bail out
if success then
value( i ) := logic_value;
else
exit;
end if;
end loop; -- each element in output array
-- free working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
elsif ( value'length /= 0 ) then
-- string is empty but the return array has 1+ elements
success := false;
end if;
-- set output parameter
good := success;
end read;
procedure read(l: inout line; value: out std_logic_vector ) is
variable success: boolean;
begin
read( l, value, success );
assert success
report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value."
severity error;
end read;
----------------------------------------------------------------------------
-- WRITE procedure bodies
----------------------------------------------------------------------------
--
-- std_ulogic
-- note: compatible with std_logic
--
procedure write(l : inout line ;
value : in std_ulogic ;
justified: in side := right;
field : in width := 0 ) is
begin
--
-- algorithm:
--
-- just write out the string associated with the enumerated
-- value.
--
case value is
when 'U' => write( l, character'('U'), justified, field );
when 'X' => write( l, character'('X'), justified, field );
when '0' => write( l, character'('0'), justified, field );
when '1' => write( l, character'('1'), justified, field );
when 'Z' => write( l, character'('Z'), justified, field );
when 'W' => write( l, character'('W'), justified, field );
when 'L' => write( l, character'('L'), justified, field );
when 'H' => write( l, character'('H'), justified, field );
when '-' => write( l, character'('-'), justified, field );
end case;
end write;
--
-- std_logic_vector
-- note: NOT compatible with std_ulogic_vector
--
procedure write(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m: line; -- build up intermediate string
begin
--
-- algorithm:
--
-- for each value in array
-- add string representing value to intermediate string
-- write intermediate string to line parameter
-- free intermediate string
--
-- for each value in array
for i in value'range loop
-- add string representing value to intermediate string
write( m, value( i ) );
end loop;
-- write intermediate string to line parameter
write( l, m.all, justified, field );
-- free intermediate string
deallocate( m );
end write;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- procedure bodies for octal and hexadecimal read and write
----------------------------------------------------------------------------
--
-- std_logic_vector/octal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_oct(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable oct_logic_vector: oct_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem oct_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := octdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
oct_logic_vector := octint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := oct_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := octdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
oct_logic_vector := octint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_oct;
procedure read_oct(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_oct;
procedure write_oct(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / oct_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = oct_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2octdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_oct;
--
-- std_logic_vector/hexadecimal
-- note: NOT compatible with std_ulogic_vector
--
procedure read_hex(l : inout line ;
value : out std_logic_vector;
good : out boolean ) is
variable m : line ; -- safe L
variable success : boolean := true; -- readable GOOD
variable logic_value : std_logic ; -- elem value
variable c : character ; -- char read
variable charcode : integer ; -- char->int
variable hex_logic_vector: hex_logic_vector_t ; -- for 1 digit
variable bitpos : integer ; -- in state vec.
begin
--
-- algorithm:
--
-- skip over leading blanks, then read a digit
-- and do a conversion into a logic value
-- for each element in array
--
-- make sure logic array is right size to read this base
success := ( ( value'length rem hex_bits_per_digit ) = 0 );
if success then
-- only operate on non-empty strings
if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-- save old copy of string in case read fails
m := new string'( l.all );
-- pick off leading white space and get first significant char
c := ' ';
while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
read( l, c, success );
end loop;
-- turn character into integer
charcode := hexdigit2int( c );
-- not doing any bits yet
bitpos := 0;
-- check for bad first character
if charcode = bad_charcode then
success := false;
else
-- loop through each value in array
hex_logic_vector := hexint2logic( charcode );
for i in value'range loop
-- doing the next bit
bitpos := bitpos + 1;
-- stick the value in
value( i ) := hex_logic_vector( bitpos );
-- read the next character if we're not at array end
if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
read( l, c, success );
if not success then
exit;
end if;
-- turn character into integer
charcode := hexdigit2int( c );
-- check for bad char
if charcode = bad_charcode then
success := false;
exit;
end if;
-- reset bit position
bitpos := 0;
-- turn character code into state array
hex_logic_vector := hexint2logic( charcode );
end if;
end loop; -- each index in return array
end if; -- if bad first character
-- clean up working storage
if success then
deallocate( m );
else
deallocate( l );
l := m;
end if;
-- no characters to read for return array that isn't null slice
elsif ( value'length /= 0 ) then
success := false;
end if; -- non null access, non empty string
end if;
-- set out parameter of success
good := success;
end read_hex;
procedure read_hex(l : inout line ;
value : out std_logic_vector) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value."
severity error;
end read_hex;
procedure write_hex(l : inout line ;
value : in std_logic_vector ;
justified: in side := right;
field : in width := 0 ) is
variable m : line ; -- safe copy of L
variable goodlength : boolean ; -- array is ok len for this base
variable isx : boolean ; -- an X in this digit
variable integer_value: integer ; -- accumulate integer value
variable c : character; -- character read
variable charpos : integer ; -- index string being contructed
variable bitpos : integer ; -- bit index inside digit
begin
--
-- algorithm:
--
-- make sure this array can be written in this base
-- create a string to place intermediate results
-- initialize counters and flags to beginning of string
-- for each item in array
-- note unknown, else accumulate logic into integer
-- if at this digit's last bit
-- stuff digit just computed into intermediate result
-- reset flags and counters except for charpos
-- write intermediate result into line
-- free work storage
--
-- make sure this array can be written in this base
goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
assert goodlength
report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
severity error;
if goodlength then
-- create a string to place intermediate results
m := new string(1 to ( value'length / hex_bits_per_digit ) );
-- initialize counters and flags to beginning of string
charpos := 0;
bitpos := 0;
isx := false;
integer_value := 0;
-- for each item in array
for i in value'range loop
-- note unknown, else accumulate logic into integer
case value(i) is
when '0' | 'L' =>
integer_value := integer_value * 2;
when '1' | 'H' =>
integer_value := ( integer_value * 2 ) + 1;
when others =>
isx := true;
end case;
-- see if we've done this digit's last bit
bitpos := bitpos + 1;
if bitpos = hex_bits_per_digit then
-- stuff the digit just computed into the intermediate result
charpos := charpos + 1;
if isx then
m.all(charpos) := 'X';
else
m.all(charpos) := int2hexdigit( integer_value );
end if;
-- reset flags and counters except for location in string being constructed
bitpos := 0;
isx := false;
integer_value := 0;
end if;
end loop;
-- write intermediate result into line
write( l, m.all, justified, field );
-- free work storage
deallocate( m );
end if;
end write_hex;
------------------------------------------------------------------------------
------------------------------------
-- Read octal/hex numbers to integer
------------------------------------
--
-- Read octal to integer
--
procedure read_oct(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := octdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := octdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 8) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_oct;
-- simple version
procedure read_oct(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_oct( l, value, success ); -- use safe version
assert success
report "IO1164.READ_OCT: Unable to read octal integer value."
severity error;
end read_oct;
--
-- Read hex to integer
--
procedure read_hex(l : inout line;
value : out integer;
good : out boolean) is
variable pos : integer;
variable digit : integer;
variable result : integer := 0;
variable success : boolean := true;
variable c : character;
variable old_l : line := l;
begin
-- algorithm:
--
-- skip leading white space, read digit, convert
-- into integer
--
if (l /= NULL) then
-- set pos to start of actual number by skipping white space
pos := l'LEFT;
c := l(pos);
while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
pos := pos + 1;
c := l(pos);
end loop;
-- check for start of valid number
digit := hexdigit2int(l(pos));
if ((digit = bad_charcode) or (digit = x_charcode)) then
good := FALSE;
return;
else
-- calculate integer value
for i in pos to l'RIGHT loop
digit := hexdigit2int(l(pos));
exit when (digit = bad_charcode) or (digit = x_charcode);
result := (result * 16) + digit;
pos := pos + 1;
end loop;
value := result;
-- shrink line
if (pos > 1) then
l := new string'(old_l(pos to old_l'HIGH));
deallocate(old_l);
end if;
good := TRUE;
return;
end if;
else
good := FALSE;
end if;
end read_hex;
-- simple version
procedure read_hex(l : inout line;
value : out integer) is
variable success: boolean; -- internal good flag
begin
read_hex( l, value, success ); -- use safe version
assert success
report "IO1164.READ_HEX: Unable to read hex integer value."
severity error;
end read_hex;
end io1164;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity asyncLdCnt is port (
loadVal: in std_logic_vector(3 downto 0);
clk, load: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end asyncLdCnt;
architecture rtl of asyncLdCnt is
signal qLocal: unsigned(3 downto 0);
begin
process (clk, load, loadVal) begin
if (load = '1') then
qLocal <= to_unsigned(loadVal);
elsif (clk'event and clk = '1' ) then
qLocal <= qLocal + 1;
end if;
end process;
q <= to_stdlogicvector(qLocal);
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LoadCnt is port (
CntEn: in std_logic;
LdCnt: in std_logic;
LdData: in std_logic_vector(3 downto 0);
Clk: in std_logic;
Rst: in std_logic;
CntVal: out std_logic_vector(3 downto 0)
);
end LoadCnt;
architecture behavioral of LoadCnt is
signal Cnt: std_logic_vector(3 downto 0);
begin
counter: process (Clk, Rst) begin
if Rst = '1' then
Cnt <= (others => '0');
elsif (Clk'event and Clk = '1') then
if (LdCnt = '1') then
Cnt <= LdData;
elsif (CntEn = '1') then
Cnt <= Cnt + 1;
else
Cnt <= Cnt;
end if;
end if;
end process;
CntVal <= Cnt;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
library UTILS;
use UTILS.io1164.all;
use std.textio.all;
entity loadCntTB is
end loadCntTB;
architecture testbench of loadCntTB is
component loadCnt port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end component;
file vectorFile: text is in "vectorfile";
type vectorType is record
data: std_logic_vector(7 downto 0);
load: std_logic;
rst: std_logic;
q: std_logic_vector(7 downto 0);
end record;
signal testVector: vectorType;
signal TestClk: std_logic := '0';
signal Qout: std_logic_vector(7 downto 0);
constant ClkPeriod: time := 100 ns;
for all: loadCnt use entity work.loadcnt(rtl);
begin
-- File reading and stimulus application
readVec: process
variable VectorLine: line;
variable VectorValid: boolean;
variable vRst: std_logic;
variable vLoad: std_logic;
variable vData: std_logic_vector(7 downto 0);
variable vQ: std_logic_vector(7 downto 0);
begin
while not endfile (vectorFile) loop
readline(vectorFile, VectorLine);
read(VectorLine, vRst, good => VectorValid);
next when not VectorValid;
read(VectorLine, vLoad);
read(VectorLine, vData);
read(VectorLine, vQ);
wait for ClkPeriod/4;
testVector.Rst <= vRst;
testVector.Load <= vLoad;
testVector.Data <= vData;
testVector.Q <= vQ;
wait for (ClkPeriod/4) * 3;
end loop;
assert false
report "Simulation complete"
severity note;
wait;
end process;
-- Free running test clock
TestClk <= not TestClk after ClkPeriod/2;
-- Instance of design being tested
u1: loadCnt port map (Data => testVector.Data,
load => testVector.Load,
clk => TestClk,
rst => testVector.Rst,
q => Qout
);
-- Process to verify outputs
verify: process (TestClk)
variable ErrorMsg: line;
begin
if (TestClk'event and TestClk = '0') then
if Qout /= testVector.Q then
write(ErrorMsg, string'("Vector failed "));
write(ErrorMsg, now);
writeline(output, ErrorMsg);
end if;
end if;
end process;
end testbench;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity loadCnt is port (
data: in std_logic_vector (7 downto 0);
load: in std_logic;
clk: in std_logic;
rst: in std_logic;
q: out std_logic_vector (7 downto 0)
);
end loadCnt;
architecture rtl of loadCnt is
signal cnt: std_logic_vector (7 downto 0);
begin
counter: process (clk, rst) begin
if (rst = '1') then
cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (load = '1') then
cnt <= data;
else
cnt <= cnt + 1;
end if;
end if;
end process;
q <= cnt;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity multiplier is port (
a,b : in std_logic_vector (15 downto 0);
product: out std_logic_vector (31 downto 0)
);
end multiplier;
architecture dataflow of multiplier is
begin
product <= a * b;
end dataflow;
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is port (
A, B, Sel: in std_logic;
Y: out std_logic
);
end mux;
architecture simModel of mux is
-- Delay Constants
constant tPD_A: time := 10 ns;
constant tPD_B: time := 15 ns;
constant tPD_Sel: time := 5 ns;
begin
DelayMux: process (A, B, Sel)
variable localY: std_logic; -- Zero delay place holder for Y
begin
-- Zero delay model
case Sel is
when '0' =>
localY := A;
when others =>
localY := B;
end case;
-- Delay calculation
if (B'event) then
Y <= localY after tPD_B;
elsif (A'event) then
Y <= localY after tPD_A;
else
Y <= localY after tPD_Sel;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
begin
if (a + b = "10011010") then
result <= c;
elsif (a + b = "01011001") then
result <= d;
elsif (a + b = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture concurrent of TRIBUF8 is
begin
op <= ip when oe = '1' else (others => 'Z');
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture concurrent of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end concurrent;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF8 is port (
ip: in std_logic_vector(7 downto 0);
oe: in std_logic;
op: out std_logic_vector(7 downto 0)
);
end TRIBUF8;
architecture sequential of TRIBUF8 is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= (others => 'Z');
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in bit;
oe: in bit;
op: out bit
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= null;
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture sequential of TRIBUF is
begin
enable: process (ip,oe) begin
if (oe = '1') then
op <= ip;
else
op <= 'Z';
end if;
end process;
end sequential;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity tribuffer is port (
input: in std_logic;
enable: in std_logic;
output: out std_logic
);
end tribuffer;
architecture structural of tribuffer is
begin
u1: tribuf port map (ip => input,
oe => enable,
op => output
);
end structural;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
begin
genXOR(0) <= '0';
parTree: for i in 1 to ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
entity oddParityLoop is
generic ( width : integer := 8 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityLoop ;
architecture scaleable of oddParityLoop is
begin
process (ad)
variable loopXor: std_logic;
begin
loopXor := '0';
for i in 0 to width -1 loop
loopXor := loopXor xor ad( i ) ;
end loop ;
oddParity <= loopXor ;
end process;
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is port (
I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after 10 ns;
end simple;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is port (
a,b: in std_logic_vector(3 downto 0);
sum: out std_logic_vector(3 downto 0);
overflow: out std_logic
);
end adder;
architecture concat of adder is
signal localSum: std_logic_vector(4 downto 0);
begin
localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
sum <= localSum(3 downto 0);
overflow <= localSum(4);
end concat;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity paramDFF is
generic (size: integer := 8);
port (
data: in std_logic_vector(size - 1 downto 0);
clock: in std_logic;
reset: in std_logic;
ff_enable: in std_logic;
op_enable: in std_logic;
qout: out std_logic_vector(size - 1 downto 0)
);
end paramDFF;
architecture parameterize of paramDFF is
signal reg: std_logic_vector(size - 1 downto 0);
begin
u1: pDFFE generic map (n => size)
port map (d => data,
clk =>clock,
rst => reset,
en => ff_enable,
q => reg
);
u2: pTRIBUF generic map (n => size)
port map (ip => reg,
oe => op_enable,
op => qout
);
end parameterize;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 );
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal genXor: std_logic_vector(ad'range);
signal one: std_logic := '1';
begin
parTree: for i in ad'range generate
g0: if i = 0 generate
x0: xor2 port map (i1 => one,
i2 => one,
y => genXor(0)
);
end generate;
g1: if i > 0 and i <= ad'high generate
x1: xor2 port map (i1 => genXor(i - 1),
i2 => ad(i - 1),
y => genXor(i)
);
end generate;
end generate;
oddParity <= genXor(ad'high) ;
end scaleable ;
library ieee;
use ieee.std_logic_1164.all;
use work.primitive.all;
entity oddParityGen is
generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
port (ad: in std_logic_vector (width - 1 downto 0);
oddParity : out std_logic ) ;
end oddParityGen;
architecture scaleable of oddParityGen is
signal stage0: std_logic_vector(31 downto 0);
signal stage1: std_logic_vector(15 downto 0);
signal stage2: std_logic_vector(7 downto 0);
signal stage3: std_logic_vector(3 downto 0);
signal stage4: std_logic_vector(1 downto 0);
begin
g4: for i in stage4'range generate
g41: if (ad'length > 2) generate
x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
end generate;
end generate;
g3: for i in stage3'range generate
g31: if (ad'length > 4) generate
x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
end generate;
end generate;
g2: for i in stage2'range generate
g21: if (ad'length > 8) generate
x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
end generate;
end generate;
g1: for i in stage1'range generate
g11: if (ad'length > 16) generate
x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
end generate;
end generate;
s1: for i in ad'range generate
s14: if (ad'length = 2) generate
stage4(i) <= ad(i);
end generate;
s13: if (ad'length = 4) generate
stage3(i) <= ad(i);
end generate;
s12: if (ad'length = 8) generate
stage2(i) <= ad(i);
end generate;
s11: if (ad'length = 16) generate
stage1(i) <= ad(i);
end generate;
s10: if (ad'length = 32) generate
stage0(i) <= ad(i);
end generate;
end generate;
genPar: xor2 port map (stage4(0), stage4(1), oddParity);
end scaleable ;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in unsigned(3 downto 0);
power : out unsigned(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
signal inputValInt: integer range 0 to 15;
signal powerL: integer range 0 to 65535;
begin
inputValInt <= to_integer(inputVal);
power <= to_unsigned(powerL,16);
process begin
wait until Clk = '1';
powerL <= Pow(inputValInt,4);
end process;
end behavioral;
package PowerPkg is
component Power port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end component;
end PowerPkg;
use work.bv_math.all;
use work.int_math.all;
use work.PowerPkg.all;
entity Power is port(
Clk : in bit;
inputVal : in bit_vector(0 to 3);
power : out bit_vector(0 to 15) );
end Power;
architecture funky of Power is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
Variable i : integer := 0;
begin
while( i < Exp ) loop
Result := Result * N;
i := i + 1;
end loop;
return( Result );
end Pow;
function RollVal( CntlVal : integer ) return integer is
begin
return( Pow( 2, CntlVal ) + 2 );
end RollVal;
begin
process
begin
wait until Clk = '1';
power <= i2bv(Rollval(bv2I(inputVal)),16);
end process;
end funky;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is port
(interrupts : in std_logic_vector(7 downto 0);
priority : in std_logic_vector(2 downto 0);
result : out std_logic_vector(2 downto 0)
);
end priority_encoder;
architecture behave of priority_encoder is
begin
process (interrupts)
variable selectIn : integer;
variable LoopCount : integer;
begin
LoopCount := 1;
selectIn := to_integer(to_unsigned(priority));
while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
if (selectIn = 0) then
selectIn := 7;
else
selectIn := selectIn - 1;
end if;
LoopCount := LoopCount + 1;
end loop;
result <= std_logic_vector(to_unsigned(selectIn,3));
end process;
end behave;
library IEEE;
use IEEE.std_logic_1164.all;
package primitive is
component DFFE port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end component;
component DFFE_SR port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end component;
component DLATCHH port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end component;
component AND2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component OR2 port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end component;
component INVERTER port (
i: in std_logic;
o: out std_logic
);
end component;
component TRIBUF port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end component;
component BIDIR port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE is port (
d: in std_logic;
q: out std_logic;
en: in std_logic;
clk: in std_logic
);
end DFFE;
architecture rtl of DFFE is
begin
process begin
wait until clk = '1';
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFFE_SR is port (
d: in std_logic;
en: in std_logic;
clk: in std_logic;
rst: in std_logic;
prst: in std_logic;
q: out std_logic
);
end DFFE_SR;
architecture rtl of DFFE_SR is
begin
process (clk, rst, prst) begin
if (rst = '1') then
q <= '0';
elsif (prst = '1') then
q <= '1';
elsif (clk'event and clk = '1') then
if (en = '1') then
q <= d;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity DLATCHH is port (
d: in std_logic;
en: in std_logic;
q: out std_logic
);
end DLATCHH;
architecture rtl of DLATCHH is
begin
process (en) begin
if (en = '1') then
q <= d;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity AND2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end AND2;
architecture rtl of AND2 is
begin
y <= '1' when i1 = '1' and i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity OR2 is port (
i1: in std_logic;
i2: in std_logic;
y: out std_logic
);
end OR2;
architecture rtl of OR2 is
begin
y <= '1' when i1 = '1' or i2 = '1' else '0';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity INVERTER is port (
i: in std_logic;
o: out std_logic
);
end INVERTER;
architecture rtl of INVERTER is
begin
o <= not i;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity TRIBUF is port (
ip: in std_logic;
oe: in std_logic;
op: out std_logic
);
end TRIBUF;
architecture rtl of TRIBUF is
begin
op <= ip when oe = '1' else 'Z';
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity BIDIR is port (
ip: in std_logic;
oe: in std_logic;
op_fb: out std_logic;
op: inout std_logic
);
end BIDIR;
architecture rtl of BIDIR is
begin
op <= ip when oe = '1' else 'Z';
op_fb <= op;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
subtype fsmType is std_logic_vector(1 downto 0);
constant loadDelayCnt : fsmType := "00";
constant waitDelayEnd : fsmType := "10";
constant loadLengthCnt : fsmType := "11";
constant waitLengthEnd : fsmType := "01";
signal currState, nextState: fsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
-- Assign pulse output
pulse <= currState(0);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pulseErr is port
(a: in std_logic;
b: out std_logic
);
end pulseErr;
architecture behavior of pulseErr is
signal c: std_logic;
begin
pulse: process (a,c) begin
b <= c XOR a;
c <= a;
end process;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulse is port (
clk, reset: in std_logic;
loadLength,loadDelay: in std_logic;
data: in std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulse;
architecture rtl of progPulse is
signal downCnt, downCntData: unsigned(7 downto 0);
signal downCntLd, downCntEn: std_logic;
signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
signal startPulse, endPulse: std_logic;
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
begin
delayreg: process (clk, reset) begin
if reset = '1' then
delayCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
delayCntVal <= to_unsigned(data);
end if;
end if;
end process;
lengthReg: process (clk, reset) begin
if reset = '1' then
pulseCntVal <= "11111111";
elsif clk'event and clk = '1' then
if loadDelay = '1' then
pulseCntVal <= to_unsigned(data);
end if;
end if;
end process;
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCnt = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, pulseCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downCntData <= pulseCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downCntData <= pulseCntVal;
pulse <= '0';
end case;
end process outConProc;
downCntr: process (clk,reset) begin
if (reset = '1') then
downCnt <= "00000000";
elsif (clk'event and clk = '1') then
if (downCntLd = '1') then
downCnt <= downCntData;
elsif (downCntEn = '1') then
downCnt <= downCnt - 1;
else
downCnt <= downCnt;
end if;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
type stateVec is array (3 downto 0) of std_logic;
type stateBits is array (progPulseFsmType) of stateVec;
signal loadVal: std_logic;
constant stateTable: stateBits := (
loadDelayCnt => "0010",
waitDelayEnd => "0100",
loadLengthCnt => "0011",
waitLengthEnd => "1101" );
-- ^^^^
-- ||||__ loadVal
-- |||___ downCntLd
-- ||____ downCntEn
-- |_____ pulse
signal currState, nextState: progPulseFsmType;
begin
nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (to_unsigned(downCnt) = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
pulse <= stateTable(currState)(3);
downCntEn <= stateTable(currState)(2);
downCntLd <= stateTable(currState)(1);
loadVal <= stateTable(currState)(0);
downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
end fsm;
-- Incorporates Errata 6.1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progPulseFsm is port (
downCnt: in std_logic_vector(7 downto 0);
delayCntVal: in std_logic_vector(7 downto 0);
lengthCntVal: in std_logic_vector(7 downto 0);
loadLength: in std_logic;
loadDelay: in std_logic;
clk: in std_logic;
reset: in std_logic;
downCntEn: out std_logic;
downCntLd: out std_logic;
downtCntData: out std_logic_vector(7 downto 0);
pulse: out std_logic
);
end progPulseFsm;
architecture fsm of progPulseFsm is
type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
signal currState, nextState: progPulseFsmType;
signal downCntL: unsigned (7 downto 0);
begin
downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
case currState is
when loadDelayCnt =>
nextState <= waitDelayEnd;
when waitDelayEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadLengthCnt;
else
nextState <= waitDelayEnd;
end if;
when loadLengthCnt =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
else
nextState <= waitLengthEnd;
end if;
when waitLengthEnd =>
if (loadDelay = '1' or loadLength = '1') then
nextState <= loadDelayCnt;
elsif (downCntL = 0) then
nextState <= loadDelayCnt;
else
nextState <= waitDelayEnd;
end if;
when others =>
null;
end case;
end process nextStProc;
currStProc: process (clk, reset) begin
if (reset = '1') then
currState <= loadDelayCnt;
elsif (clk'event and clk = '1') then
currState <= nextState;
end if;
end process currStProc;
outConProc: process (currState, delayCntVal, lengthCntVal) begin
case currState is
when loadDelayCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
when waitDelayEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= delayCntVal;
pulse <= '0';
when loadLengthCnt =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= lengthCntVal;
pulse <= '1';
when waitLengthEnd =>
downCntEn <= '1';
downCntLd <= '0';
downtCntData <= lengthCntVal;
pulse <= '1';
when others =>
downCntEn <= '0';
downCntLd <= '1';
downtCntData <= delayCntVal;
pulse <= '0';
end case;
end process outConProc;
end fsm;
-- Incorporates errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.specialFunctions.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
end process;
end behavioral;
-- Incorporate errata 5.4
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity powerOfFour is port(
clk : in std_logic;
inputVal : in std_logic_vector(3 downto 0);
power : out std_logic_vector(15 downto 0)
);
end powerOfFour;
architecture behavioral of powerOfFour is
function Pow( N, Exp : integer ) return integer is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
begin
process begin
wait until Clk = '1';
power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity regFile is port (
clk, rst: in std_logic;
data: in std_logic_vector(31 downto 0);
regSel: in std_logic_vector(1 downto 0);
wrEnable: in std_logic;
regOut: out std_logic_vector(31 downto 0)
);
end regFile;
architecture behavioral of regFile is
subtype reg is std_logic_vector(31 downto 0);
type regArray is array (integer range <>) of reg;
signal registerFile: regArray(0 to 3);
begin
regProc: process (clk, rst)
variable i: integer;
begin
i := 0;
if rst = '1' then
while i <= registerFile'high loop
registerFile(i) <= (others => '0');
i := i + 1;
end loop;
elsif clk'event and clk = '1' then
if (wrEnable = '1') then
case regSel is
when "00" =>
registerFile(0) <= data;
when "01" =>
registerFile(1) <= data;
when "10" =>
registerFile(2) <= data;
when "11" =>
registerFile(3) <= data;
when others =>
null;
end case;
end if;
end if;
end process;
outputs: process(regSel, registerFile) begin
case regSel is
when "00" =>
regOut <= registerFile(0);
when "01" =>
regOut <= registerFile(1);
when "10" =>
regOut <= registerFile(2);
when "11" =>
regOut <= registerFile(3);
when others =>
null;
end case;
end process;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF is port (
d1,d2: in std_logic;
q1,q2: out std_logic;
clk: in std_logic;
rst : in std_logic
);
end DFF;
architecture rtl of DFF is
begin
resetLatch: process (clk, rst) begin
if rst = '1' then
q1 <= '0';
elsif clk'event and clk = '1' then
q1 <= d1;
q2 <= d2;
end if;
end process;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity resFcnDemo is port (
a, b: in std_logic;
oeA,oeB: in std_logic;
result: out std_logic
);
end resFcnDemo;
architecture multiDriver of resFcnDemo is
begin
result <= a when oeA = '1' else 'Z';
result <= b when oeB = '1' else 'Z';
end multiDriver;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleDFF is port (
data: in std_logic_vector(7 downto 0);
clock: in std_logic;
enable: in std_logic;
qout: out std_logic_vector(7 downto 0)
);
end scaleDFF;
architecture scalable of scaleDFF is
begin
u1: sDFFE port map (d => data,
clk =>clock,
en => enable,
q => qout
);
end scalable;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
signal oe: std_logic;
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
la_n <= '1'; lb_n <= '1';
lc_n <= '1'; ld_n <= '1';
le_n <= '1'; lf_n <= '1';
lg_n <= '1';
case bcdInputs is
when "0000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
when "0001" => lb_n <= '0'; lc_n <= '0';
when "0010" => la_n <= '0'; lb_n <= '0';
ld_n <= '0'; le_n <= '0';
lg_n <= '0';
when "0011" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lg_n <= '0';
when "0100" => lb_n <= '0'; lc_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0101" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "0110" => la_n <= '0'; lc_n <= '0';
ld_n <= '0'; le_n <= '0';
lf_n <= '0'; lg_n <= '0';
when "0111" => la_n <= '0'; lb_n <= '0';
lc_n <= '0';
when "1000" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
le_n <= '0'; lf_n <= '0';
lg_n <= '0';
when "1001" => la_n <= '0'; lb_n <= '0';
lc_n <= '0'; ld_n <= '0';
lf_n <= '0'; lg_n <= '0';
-- All other inputs possibilities are "don't care"
when others => la_n <= 'X'; lb_n <= 'X';
lc_n <= 'X'; ld_n <= 'X';
le_n <= 'X'; lf_n <= 'X';
lg_n <= 'X';
end case;
end process bcd2sevSeg;
-- Disable outputs for all invalid input values
oe <= '1' when (bcdInputs < 10) else '0';
a_n <= la_n when oe = '1' else 'Z';
b_n <= lb_n when oe = '1' else 'Z';
c_n <= lc_n when oe = '1' else 'Z';
d_n <= ld_n when oe = '1' else 'Z';
e_n <= le_n when oe = '1' else 'Z';
f_n <= lf_n when oe = '1' else 'Z';
g_n <= lg_n when oe = '1' else 'Z';
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity sevenSegmentTB is
end sevenSegmentTB;
architecture testbench of sevenSegmentTB is
component sevenSegment port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end component;
type vector is record
bcdStimulus: std_logic_vector(3 downto 0);
sevSegOut: std_logic_vector(6 downto 0);
end record;
constant NumVectors: integer:= 17;
constant PropDelay: time := 40 ns;
constant SimLoopDelay: time := 10 ns;
type vectorArray is array (0 to NumVectors - 1) of vector;
constant vectorTable: vectorArray := (
(bcdStimulus => "0000", sevSegOut => "0000001"),
(bcdStimulus => "0001", sevSegOut => "1001111"),
(bcdStimulus => "0010", sevSegOut => "0010010"),
(bcdStimulus => "0011", sevSegOut => "0000110"),
(bcdStimulus => "0100", sevSegOut => "1001100"),
(bcdStimulus => "0101", sevSegOut => "0100100"),
(bcdStimulus => "0110", sevSegOut => "0100000"),
(bcdStimulus => "0111", sevSegOut => "0001111"),
(bcdStimulus => "1000", sevSegOut => "0000000"),
(bcdStimulus => "1001", sevSegOut => "0000100"),
(bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
(bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
);
for all : sevenSegment use entity work.sevenSegment(behavioral);
signal StimInputs: std_logic_vector(3 downto 0);
signal CaptureOutputs: std_logic_vector(6 downto 0);
begin
u1: sevenSegment port map (bcdInputs => StimInputs,
a_n => CaptureOutputs(6),
b_n => CaptureOutputs(5),
c_n => CaptureOutputs(4),
d_n => CaptureOutputs(3),
e_n => CaptureOutputs(2),
f_n => CaptureOutputs(1),
g_n => CaptureOutputs(0));
LoopStim: process
variable FoundError: boolean := false;
variable TempVector: vector;
variable ErrorMsgLine: line;
begin
for i in vectorTable'range loop
TempVector := vectorTable(i);
StimInputs <= TempVector.bcdStimulus;
wait for PropDelay;
if CaptureOutputs /= TempVector.sevSegOut then
write (ErrorMsgLine, string'("Vector failed at "));
write (ErrorMsgLine, now);
writeline (output, ErrorMsgLine);
FoundError := true;
end if;
wait for SimLoopDelay;
end loop;
assert FoundError
report "No errors. All vectors passed."
severity note;
wait;
end process;
end testbench;
library ieee;
use ieee.std_logic_1164.all;
entity sevenSegment is port (
bcdInputs: in std_logic_vector (3 downto 0);
a_n, b_n, c_n, d_n,
e_n, f_n, g_n: out std_logic
);
end sevenSegment;
architecture behavioral of sevenSegment is
begin
bcd2sevSeg: process (bcdInputs) begin
-- Assign default to "off"
a_n <= '1'; b_n <= '1';
c_n <= '1'; d_n <= '1';
e_n <= '1'; f_n <= '1';
g_n <= '1';
case bcdInputs is
when "0000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
when "0001" =>
b_n <= '0'; c_n <= '0';
when "0010" =>
a_n <= '0'; b_n <= '0';
d_n <= '0'; e_n <= '0';
g_n <= '0';
when "0011" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
g_n <= '0';
when "0100" =>
b_n <= '0'; c_n <= '0';
f_n <= '0'; g_n <= '0';
when "0101" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; f_n <= '0';
g_n <= '0';
when "0110" =>
a_n <= '0'; c_n <= '0';
d_n <= '0'; e_n <= '0';
f_n <= '0'; g_n <= '0';
when "0111" =>
a_n <= '0'; b_n <= '0';
c_n <= '0';
when "1000" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
e_n <= '0'; f_n <= '0';
g_n <= '0';
when "1001" =>
a_n <= '0'; b_n <= '0';
c_n <= '0'; d_n <= '0';
f_n <= '0'; g_n <= '0';
when others =>
null;
end case;
end process bcd2sevSeg;
end behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ForceShare is port (
a,b,c,d,e,f: in std_logic_vector (7 downto 0);
result: out std_logic_vector(7 downto 0)
);
end ForceShare;
architecture behaviour of ForceShare is
begin
sum: process (a,c,b,d,e,f)
variable tempSum: std_logic_vector(7 downto 0);
begin
tempSum := a + b; -- temporary node for sum
if (tempSum = "10011010") then
result <= c;
elsif (tempSum = "01011001") then
result <= d;
elsif (tempSum = "10111011") then
result <= e;
else
result <= f;
end if;
end process;
end behaviour;
library IEEE;
use IEEE.std_logic_1164.all;
entity shifter is port (
clk, rst: in std_logic;
shiftEn,shiftIn: std_logic;
q: out std_logic_vector (15 downto 0)
);
end shifter;
architecture behav of shifter is
signal qLocal: std_logic_vector(15 downto 0);
begin
shift: process (clk, rst) begin
if (rst = '1') then
qLocal <= (others => '0');
elsif (clk'event and clk = '1') then
if (shiftEn = '1') then
qLocal <= qLocal(14 downto 0) & shiftIn;
else
qLocal <= qLocal;
end if;
end if;
q <= qLocal;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity lastAssignment is port
(a, b: in std_logic;
selA, selb: in std_logic;
result: out std_logic
);
end lastAssignment;
architecture behavioral of lastAssignment is
begin
demo: process (a,b,selA,selB) begin
if (selA = '1') then
result <= a;
else
result <= '0';
end if;
if (selB = '1') then
result <= b;
else
result <= '0';
end if;
end process demo;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '0' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library ieee;
use ieee.std_logic_1164.all;
entity signalDemo is port (
a: in std_logic;
b: out std_logic
);
end signalDemo;
architecture basic of signalDemo is
signal c: std_logic;
begin
demo: process (a) begin
c <= a;
if c = '1' then
b <= a;
else
b <= '0';
end if;
end process;
end basic;
library IEEE;
USE IEEE.std_logic_1164.all;
package simPrimitives is
component OR2
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end component;
component SimDFF
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end component;
end simPrimitives;
library IEEE;
USE IEEE.std_logic_1164.all;
entity OR2 is
generic (tPD: time := 1 ns);
port (I1, I2: in std_logic;
Y: out std_logic
);
end OR2;
architecture simple of OR2 is
begin
Y <= I1 OR I2 after tPD;
end simple;
library IEEE;
use IEEE.std_logic_1164.all;
entity SimDFF is
generic(tCQ: time := 1 ns;
tS : time := 1 ns;
tH : time := 1 ns
);
port (D, Clk: in std_logic;
Q: out std_logic
);
end SimDff;
architecture SimModel of SimDFF is
begin
reg: process (Clk, D) begin
-- Assign output tCQ after rising clock edge
if (Clk'event and Clk = '1') then
Q <= D after tCQ;
end if;
-- Check setup time
if (Clk'event and Clk = '1') then
assert (D'last_event >= tS)
report "Setup time violation"
severity Warning;
end if;
-- Check hold time
if (D'event and Clk'stable and Clk = '1') then
assert (D'last_event - Clk'last_event > tH)
report "Hold Time Violation"
severity Warning;
end if;
end process;
end simModel;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until rising_edge(clk);
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity SRFF is port (
s,r: in std_logic;
clk: in std_logic;
q: out std_logic
);
end SRFF;
architecture rtl of SRFF is
begin
process begin
wait until clk = '1';
if s = '0' and r = '1' then
q <= '0';
elsif s = '1' and r = '0' then
q <= '1';
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
package scaleable is
component scaleUpCnt port (
clk: in std_logic;
reset: in std_logic;
cnt: in std_logic_vector
);
end component;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
use work.primitive.all;
entity scaleUpCnt is port (
clk: in std_logic;
reset: in std_logic;
cnt: out std_logic_vector
);
end scaleUpCnt;
architecture scaleable of scaleUpCnt is
signal one: std_logic := '1';
signal cntL: std_logic_vector(cnt'range);
signal andTerm: std_logic_vector(cnt'range);
begin
-- Special case is the least significant bit
lsb: tff port map (t => one,
reset => reset,
clk => clk,
q => cntL(cntL'low)
);
andTerm(0) <= cntL(cntL'low);
-- General case for all other bits
genAnd: for i in 1 to cntL'high generate
andTerm(i) <= andTerm(i - 1) and cntL(i);
end generate;
genTFF: for i in 1 to cntL'high generate
t1: tff port map (t => andTerm(i),
clk => clk,
reset => reset,
q => cntl(i)
);
end generate;
cnt <= CntL;
end scaleable;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "010";
constant Turn_Ar: targetFsmType := "110";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(3 downto 0);
constant Idle: targetFsmType := "0000";
constant B_Busy: targetFsmType := "0001";
constant Backoff: targetFsmType := "0011";
constant S_Data: targetFsmType := "1100";
constant Turn_Ar: targetFsmType := "1101";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "101";
constant Backoff: targetFsmType := "010";
constant S_Data: targetFsmType := "011";
constant Turn_Ar: targetFsmType := "110";
constant Dont_Care: targetFsmType := "XXX";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= Dont_Care;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Stop_n: out std_logic; -- PCI Stop#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
signal currState, nextState: targetFsmType;
begin
-- Process to generate next state logic
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
-- Process to register the current state
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
-- Process to generate outputs
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
-- Assign output ports
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
-- Incorporates Errata 10.1 and 10.2
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(4 downto 0);
constant Idle: integer := 0;
constant B_Busy: integer := 1;
constant Backoff: integer := 2;
constant S_Data: integer := 3;
constant Turn_Ar: integer := 4;
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
nextState <= (others => '0');
if currState(Idle) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
if currState(B_Busy) = '1' then
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState(Idle) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState(S_Data) <= '1';
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState(Backoff) <= '1';
else
nextState(B_Busy) <= '1';
end if;
end if;
if currState(S_Data) = '1' then
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState(Backoff) <= '1';
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState(Turn_Ar) <= '1';
else
nextState(S_Data) <= '1';
end if;
end if;
if currState(Backoff) = '1' then
if PCI_Frame_n = '1' then
nextState(Turn_Ar) <= '1';
else
nextState(Backoff) <= '1';
end if;
end if;
if currState(Turn_Ar) = '1' then
if (PCI_Frame_n = '0' and Hit = '0') then
nextState(B_Busy) <= '1';
else
nextState(Idle) <= '1';
end if;
end if;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= (others => '0'); -- per Errata 10.2
currState(Idle) <= '1';
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
OE_Trdy_n <= '0'; OE_Stop_n <= '0'; OE_Devsel_n <= '0'; -- defaults per errata 10.1
OE_AD <= '0'; LPCI_Trdy_n <= '1'; LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
if (currState(S_Data) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Backoff) = '1') then
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
end if;
if (currState(Turn_Ar) = '1') then
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
end if;
if (currState(Idle) = '1' or currState(B_Busy) = '1') then
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end if;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when IDLE =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when B_BUSY =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= IDLE;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= BACKOFF;
else
nextState <= B_BUSY;
end if;
when S_DATA =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= BACKOFF;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= TURN_AR;
else
nextState <= S_DATA;
end if;
when BACKOFF =>
if PCI_Frame_n = '1' then
nextState <= TURN_AR;
else
nextState <= BACKOFF;
end if;
when TURN_AR =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_BUSY;
else
nextState <= IDLE;
end if;
when others =>
nextState <= IDLE;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
-- Set default output assignments
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library IEEE;
use IEEE.std_logic_1164.all;
entity pci_target is port (
PCI_Frame_n: in std_logic; -- PCI Frame#
PCI_Irdy_n: in std_logic; -- PCI Irdy#
Hit: in std_logic; -- Hit on address decode
D_Done: in std_logic; -- Device decode complete
Term: in std_logic; -- Terminate transaction
Ready: in std_logic; -- Ready to transfer data
Cmd_Write: in std_logic; -- Command is Write
Cmd_Read: in std_logic; -- Command is Read
T_Abort: in std_logic; -- Target error - abort transaction
PCI_Clk: in std_logic; -- PCI Clock
PCI_Reset_n: in std_logic; -- PCI Reset#
PCI_Devsel_n: out std_logic; -- PCI Devsel#
PCI_Trdy_n: out std_logic; -- PCI Trdy#
PCI_Stop_n: out std_logic; -- PCI Stop#
OE_AD: out std_logic; -- PCI AD bus enable
OE_Trdy_n: out std_logic; -- PCI Trdy# enable
OE_Stop_n: out std_logic; -- PCI Stop# enable
OE_Devsel_n: out std_logic -- PCI Devsel# enable
);
end pci_target;
architecture fsm of pci_target is
signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
subtype targetFsmType is std_logic_vector(2 downto 0);
constant Idle: targetFsmType := "000";
constant B_Busy: targetFsmType := "001";
constant Backoff: targetFsmType := "011";
constant S_Data: targetFsmType := "110";
constant Turn_Ar: targetFsmType := "100";
signal currState, nextState: targetFsmType;
begin
nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
case currState is
when Idle =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when B_Busy =>
if (PCI_Frame_n ='1' and D_Done = '1') or
(PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
nextState <= Idle;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '0' or (Term = '1' and Ready = '1') ) then
nextState <= S_Data;
elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
(Term = '1' and Ready = '0') then
nextState <= Backoff;
else
nextState <= B_Busy;
end if;
when S_Data =>
if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
(LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
nextState <= Backoff;
elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
nextState <= Turn_Ar;
else
nextState <= S_Data;
end if;
when Backoff =>
if PCI_Frame_n = '1' then
nextState <= Turn_Ar;
else
nextState <= Backoff;
end if;
when Turn_Ar =>
if (PCI_Frame_n = '0' and Hit = '0') then
nextState <= B_Busy;
else
nextState <= Idle;
end if;
when others =>
null;
end case;
end process nxtStProc;
curStProc: process (PCI_Clk, PCI_Reset_n) begin
if (PCI_Reset_n = '0') then
currState <= Idle;
elsif (PCI_Clk'event and PCI_Clk = '1') then
currState <= nextState;
end if;
end process curStProc;
outConProc: process (currState, Ready, T_Abort, Cmd_Write,
Cmd_Read, T_Abort, Term) begin
case currState is
when S_Data =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
LPCI_Trdy_n <= '0';
else
LPCI_Trdy_n <= '1';
end if;
if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1') then
LPCI_Stop_n <= '0';
else
LPCI_Stop_n <= '1';
end if;
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when Backoff =>
if (Cmd_Read = '1') then
OE_AD <= '1';
else
OE_AD <= '0';
end if;
LPCI_Stop_n <= '0';
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
if (T_Abort = '0') then
LPCI_Devsel_n <= '0';
else
LPCI_Devsel_n <= '1';
end if;
when Turn_Ar =>
OE_Trdy_n <= '1';
OE_Stop_n <= '1';
OE_Devsel_n <= '1';
when others =>
OE_Trdy_n <= '0';
OE_Stop_n <= '0';
OE_Devsel_n <= '0';
OE_AD <= '0';
LPCI_Trdy_n <= '1';
LPCI_Stop_n <= '1';
LPCI_Devsel_n <= '1';
end case;
end process outConProc;
PCI_Devsel_n <= LPCI_Devsel_n;
PCI_Trdy_n <= LPCI_Trdy_n;
PCI_Stop_n <= LPCI_Stop_n;
end fsm;
library ieee;
use ieee.std_logic_1164.all;
entity test is port (
a: in std_logic;
z: out std_logic;
en: in std_logic
);
end test;
architecture simple of test is
begin
z <= a when en = '1' else 'z';
end simple;
|
gpl-2.0
|
1b0ed120201a98d732f79479882e87f5
| 0.536542 | 3.497346 | false | false | false | false |
krabo0om/pauloBlaze
|
testbench/test_assembler.vhd
| 2 | 229,063 |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Definition of a program memory for KCPSM6 including generic parameters for the
-- convenient selection of device family, program memory size and the ability to include
-- the JTAG Loader hardware for rapid software development.
--
-- This file is primarily for use during code development and it is recommended that the
-- appropriate simplified program memory definition be used in a final production design.
--
-- Generic Values Comments
-- Parameter Supported
--
-- C_FAMILY "S6" Spartan-6 device
-- "V6" Virtex-6 device
-- "7S" 7-Series device
-- (Artix-7, Kintex-7, Virtex-7 or Zynq)
--
-- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions
--
-- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader
--
-- Notes
--
-- If your design contains MULTIPLE KCPSM6 instances then only one should have the
-- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to
-- '1' on one instance of the program memory). Advanced users may be interested to know
-- that it is possible to connect JTAG Loader to multiple memories and then to use the
-- JTAG Loader utility to specify which memory contents are to be modified. However,
-- this scheme does require some effort to set up and the additional connectivity of the
-- multiple BRAMs can impact the placement, routing and performance of the complete
-- design. Please contact the author at Xilinx for more detailed information.
--
-- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete
-- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified
-- without requiring changes to the fundamental hardware definition. However, when the
-- program memory is 1K then only the lower 10-bits of the address are actually used and
-- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower
-- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex.
--
-- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the
-- size of the program and the device family.
--
-- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program
-- will require 2 BRAMs to be used and a 4K program will require 4 BRAMs to be used. It
-- should be noted that a 4K program is not such a natural fit in a Spartan-6 device and
-- the implementation also requires a small amount of logic resulting in slightly lower
-- performance. A Spartan-6 BRAM can also be split into two 9k-bit memories suggesting
-- that a program containing up to 512 instructions could be implemented. However, there
-- is a silicon errata which makes this unsuitable and therefore it is not supported by
-- this file.
--
-- In a Virtex-6 or any 7-Series device a BRAM is capable of holding 2K instructions so
-- obviously a 2K program requires only a single BRAM. Each BRAM can also be divided into
-- 2 smaller memories supporting programs of 1K in half of a 36k-bit BRAM (generally
-- reported as being an 18k-bit BRAM). For a program of 4K instructions, 2 BRAMs are used.
--
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: 2019-11-17T19:53:04.
--
-- Assembler used ROM_form template: ROM_form_JTAGLoader_14March13.vhd
--
-- Standard IEEE libraries
--
--
package jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer;
end jtag_loader_pkg;
--
package body jtag_loader_pkg is
function addr_width_calc (size_in_k: integer) return integer is
begin
if (size_in_k = 1) then return 10;
elsif (size_in_k = 2) then return 11;
elsif (size_in_k = 4) then return 12;
else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE;
end if;
return 0;
end function addr_width_calc;
end package body;
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.jtag_loader_pkg.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity test_assembler is
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end test_assembler;
--
architecture low_level_definition of test_assembler is
--
signal address_a : std_logic_vector(15 downto 0);
signal pipe_a11 : std_logic;
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal data_out_a_ll : std_logic_vector(35 downto 0);
signal data_out_a_lh : std_logic_vector(35 downto 0);
signal data_out_a_hl : std_logic_vector(35 downto 0);
signal data_out_a_hh : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(15 downto 0);
signal data_in_b : std_logic_vector(35 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_in_b_ll : std_logic_vector(35 downto 0);
signal data_in_b_hl : std_logic_vector(35 downto 0);
signal data_out_b : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_out_b_ll : std_logic_vector(35 downto 0);
signal data_out_b_hl : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_in_b_lh : std_logic_vector(35 downto 0);
signal data_in_b_hh : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal data_out_b_lh : std_logic_vector(35 downto 0);
signal data_out_b_hh : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(7 downto 0);
signal we_b_l : std_logic_vector(3 downto 0);
signal we_b_h : std_logic_vector(3 downto 0);
--
signal jtag_addr : std_logic_vector(11 downto 0);
signal jtag_we : std_logic;
signal jtag_we_l : std_logic;
signal jtag_we_h : std_logic;
signal jtag_clk : std_logic;
signal jtag_din : std_logic_vector(17 downto 0);
signal jtag_dout : std_logic_vector(17 downto 0);
signal jtag_dout_1 : std_logic_vector(17 downto 0);
signal jtag_en : std_logic_vector(0 downto 0);
--
signal picoblaze_reset : std_logic_vector(0 downto 0);
signal rdl_bus : std_logic_vector(0 downto 0);
--
constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS);
--
--
component jtag_loader_6
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
jtag_clk : out std_logic;
jtag_we : out std_logic;
jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end component;
--
begin
--
--
ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "0000";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB16BWER
generic map ( DATA_WIDTH_A => 18,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 18,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0010110C101060DED00510041001700060DED10170016100100120034F808001",
INIT_01 => X"60DED0023001100110FF60DE1000100060DED0011001E0DE10FB100560DED01C",
INIT_02 => X"11A2107BE0DE20DE315EA0DE20DE101A11A2107B60DED00220100010110110FF",
INIT_03 => X"9001100060DED0A08010110B10AB60DE900A100A60DEE0DE315D60DEE0DE1085",
INIT_04 => X"2010111410CA60DED042305310CA60DED0F4A010110A9001100020DEB0FEE0DE",
INIT_05 => X"5001110110FF20DE4010110F10F060DED0DB505310CAA0DE3001110110FF60DE",
INIT_06 => X"121411A2107BA0DE7001110110FF60DE601011F010F060DED099705310CAA0DE",
INIT_07 => X"E0DE20DEF1FFD0FF115210CA20DEE0DEF1B9D07B11A2107B60DEF214F1A2D07B",
INIT_08 => X"D001400060DE4006108060DED0FFA0DE4007107FA0DE60DEF120D004115210CA",
INIT_09 => X"400E100160DED0FFA0DE400F10FE60DED0034004108160DED0224002101160DE",
INIT_0A => X"141E02101102100160DED0C0400A108160DED011400C102260DED080400860DE",
INIT_0B => X"C410B40360DEC030A310F1C3E01012FF110A1012D11081409305B034D103C020",
INIT_0C => X"C0C2468060DED00300C260DED002454014C21500100112071205100120C560DE",
INIT_0D => X"20DF20DE50001DC900DB00DB60DCDDC9610010DF110060DED00380C260DED003",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"000000000000000000000000000000000000000000000000900100C210FF7001",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"F00F50D50313034313034313034351374D434F7D0F7D0D50D534D74D4353DD26",
INITP_01 => X"0000000000000000A8AD837DDDF6021B4D28082A00D4D4D74DD353535D374F00",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"00000000000000000000000000000000000000000000000000000000000000A3",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a(31 downto 0),
DOPA => data_out_a(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b(31 downto 0),
DOPB => data_out_b(35 downto 32),
DIB => data_in_b(31 downto 0),
DIPB => data_in_b(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"0010110C101060DED00510041001700060DED10170016100100120034F808001",
INIT_01 => X"60DED0023001100110FF60DE1000100060DED0011001E0DE10FB100560DED01C",
INIT_02 => X"11A2107BE0DE20DE315EA0DE20DE101A11A2107B60DED00220100010110110FF",
INIT_03 => X"9001100060DED0A08010110B10AB60DE900A100A60DEE0DE315D60DEE0DE1085",
INIT_04 => X"2010111410CA60DED042305310CA60DED0F4A010110A9001100020DEB0FEE0DE",
INIT_05 => X"5001110110FF20DE4010110F10F060DED0DB505310CAA0DE3001110110FF60DE",
INIT_06 => X"121411A2107BA0DE7001110110FF60DE601011F010F060DED099705310CAA0DE",
INIT_07 => X"E0DE20DEF1FFD0FF115210CA20DEE0DEF1B9D07B11A2107B60DEF214F1A2D07B",
INIT_08 => X"D001400060DE4006108060DED0FFA0DE4007107FA0DE60DEF120D004115210CA",
INIT_09 => X"400E100160DED0FFA0DE400F10FE60DED0034004108160DED0224002101160DE",
INIT_0A => X"141E02101102100160DED0C0400A108160DED011400C102260DED080400860DE",
INIT_0B => X"C410B40360DEC030A310F1C3E01012FF110A1012D11081409305B034D103C020",
INIT_0C => X"C0C2468060DED00300C260DED002454014C21500100112071205100120C560DE",
INIT_0D => X"20DF20DE50001DC900DB00DB60DCDDC9610010DF110060DED00380C260DED003",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"000000000000000000000000000000000000000000000000900100C210FF7001",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"F00F50D50313034313034313034351374D434F7D0F7D0D50D534D74D4353DD26",
INITP_01 => X"0000000000000000A8AD837DDDF6021B4D28082A00D4D4D74DD353535D374F00",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"00000000000000000000000000000000000000000000000000000000000000A3",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a(13 downto 0) <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10);
jtag_dout <= data_out_b(17 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b(17 downto 0) <= data_out_b(17 downto 0);
address_b(13 downto 0) <= "11111111111111";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b(17 downto 0) <= jtag_din(17 downto 0);
address_b(13 downto 0) <= jtag_addr(9 downto 0) & "1111";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"0010110C101060DED00510041001700060DED10170016100100120034F808001",
INIT_01 => X"60DED0023001100110FF60DE1000100060DED0011001E0DE10FB100560DED01C",
INIT_02 => X"11A2107BE0DE20DE315EA0DE20DE101A11A2107B60DED00220100010110110FF",
INIT_03 => X"9001100060DED0A08010110B10AB60DE900A100A60DEE0DE315D60DEE0DE1085",
INIT_04 => X"2010111410CA60DED042305310CA60DED0F4A010110A9001100020DEB0FEE0DE",
INIT_05 => X"5001110110FF20DE4010110F10F060DED0DB505310CAA0DE3001110110FF60DE",
INIT_06 => X"121411A2107BA0DE7001110110FF60DE601011F010F060DED099705310CAA0DE",
INIT_07 => X"E0DE20DEF1FFD0FF115210CA20DEE0DEF1B9D07B11A2107B60DEF214F1A2D07B",
INIT_08 => X"D001400060DE4006108060DED0FFA0DE4007107FA0DE60DEF120D004115210CA",
INIT_09 => X"400E100160DED0FFA0DE400F10FE60DED0034004108160DED0224002101160DE",
INIT_0A => X"141E02101102100160DED0C0400A108160DED011400C102260DED080400860DE",
INIT_0B => X"C410B40360DEC030A310F1C3E01012FF110A1012D11081409305B034D103C020",
INIT_0C => X"C0C2468060DED00300C260DED002454014C21500100112071205100120C560DE",
INIT_0D => X"20DF20DE50001DC900DB00DB60DCDDC9610010DF110060DED00380C260DED003",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"000000000000000000000000000000000000000000000000900100C210FF7001",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"F00F50D50313034313034313034351374D434F7D0F7D0D50D534D74D4353DD26",
INITP_01 => X"0000000000000000A8AD837DDDF6021B4D28082A00D4D4D74DD353535D374F00",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"00000000000000000000000000000000000000000000000000000000000000A3",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRARDADDR => address_a(13 downto 0),
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b(13 downto 0),
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b(3 downto 0),
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
end generate akv7;
--
end generate ram_1k_generate;
--
--
--
ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate
--
--
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"DE020101FFDE0000DE0101DEFB05DE1C100C10DE05040100DE01010001038001",
INIT_01 => X"0100DEA0100BABDE0A0ADEDE5DDEDE85A27BDEDE5EDEDE1AA27BDE02101001FF",
INIT_02 => X"0101FFDE100FF0DEDB53CADE0101FFDE1014CADE4253CADEF4100A0100DEFEDE",
INIT_03 => X"DEDEFFFF52CADEDEB97BA27BDE14A27B14A27BDE0101FFDE10F0F0DE9953CADE",
INIT_04 => X"0E01DEFFDE0FFEDE030481DE220211DE0100DE0680DEFFDE077FDEDE200452CA",
INIT_05 => X"1003DE3010C310FF0A121040053403201E100201DEC00A81DE110C22DE8008DE",
INIT_06 => X"DFDE00C9DBDBDCC900DF00DE03C2DE03C280DE03C2DE0240C20001070501C5DE",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000001C2FF01",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000011A001400CBA20000000000A28A24440440440200408888200004052",
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INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"B0E8988808B08808B0E888F08808B0E8800808B0E88808B8B0E8B8B00810A740",
INIT_01 => X"C808B0E8C00808B0C808B0F098B0F0880808F09098D090880808B0E890800808",
INIT_02 => X"28880890200808B0E82808D0188808B0100808B0E81808B0E8D008C80890D8F0",
INIT_03 => X"F0907868080890F0F8E80808B0F9F8E8090808D0388808B0300808B0E83808D0",
INIT_04 => X"A008B0E8D0A008B0E8A008B0E8A008B0E8A0B0A008B0E8D0A008D0B078680808",
INIT_05 => X"E25AB0E05178700908086840495868600A010808B0E8A008B0E8A008B0E8A0B0",
INIT_06 => X"1010280E0000B0EE300808B0E8C0B0E8E0A3B0E880B0E8220A0A0809098810B0",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"00000000000000000000000000000000000000000000000000000000480008B8",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000EE96AD132627088929112530C30811111111110521363620849211A5",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"000000000000000000000000000000000000000000000000000000000000000D",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"0010110C101060DED00510041001700060DED10170016100100120034F808001",
INIT_01 => X"60DED0023001100110FF60DE1000100060DED0011001E0DE10FB100560DED01C",
INIT_02 => X"11A2107BE0DE20DE315EA0DE20DE101A11A2107B60DED00220100010110110FF",
INIT_03 => X"9001100060DED0A08010110B10AB60DE900A100A60DEE0DE315D60DEE0DE1085",
INIT_04 => X"2010111410CA60DED042305310CA60DED0F4A010110A9001100020DEB0FEE0DE",
INIT_05 => X"5001110110FF20DE4010110F10F060DED0DB505310CAA0DE3001110110FF60DE",
INIT_06 => X"121411A2107BA0DE7001110110FF60DE601011F010F060DED099705310CAA0DE",
INIT_07 => X"E0DE20DEF1FFD0FF115210CA20DEE0DEF1B9D07B11A2107B60DEF214F1A2D07B",
INIT_08 => X"D001400060DE4006108060DED0FFA0DE4007107FA0DE60DEF120D004115210CA",
INIT_09 => X"400E100160DED0FFA0DE400F10FE60DED0034004108160DED0224002101160DE",
INIT_0A => X"141E02101102100160DED0C0400A108160DED011400C102260DED080400860DE",
INIT_0B => X"C410B40360DEC030A310F1C3E01012FF110A1012D11081409305B034D103C020",
INIT_0C => X"C0C2468060DED00300C260DED002454014C21500100112071205100120C560DE",
INIT_0D => X"20DF20DE50001DC900DB00DB60DCDDC9610010DF110060DED00380C260DED003",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"F00F50D50313034313034313034351374D434F7D0F7D0D50D534D74D4353DD26",
INITP_01 => X"0000000000000000A8AD837DDDF6021B4D28082A00D4D4D74DD353535D374F00",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(10 downto 0) & "1111";
instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0);
address_b <= '1' & jtag_addr(10 downto 0) & "1111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom: RAMB36E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"0010110C101060DED00510041001700060DED10170016100100120034F808001",
INIT_01 => X"60DED0023001100110FF60DE1000100060DED0011001E0DE10FB100560DED01C",
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INIT_03 => X"9001100060DED0A08010110B10AB60DE900A100A60DEE0DE315D60DEE0DE1085",
INIT_04 => X"2010111410CA60DED042305310CA60DED0F4A010110A9001100020DEB0FEE0DE",
INIT_05 => X"5001110110FF20DE4010110F10F060DED0DB505310CAA0DE3001110110FF60DE",
INIT_06 => X"121411A2107BA0DE7001110110FF60DE601011F010F060DED099705310CAA0DE",
INIT_07 => X"E0DE20DEF1FFD0FF115210CA20DEE0DEF1B9D07B11A2107B60DEF214F1A2D07B",
INIT_08 => X"D001400060DE4006108060DED0FFA0DE4007107FA0DE60DEF120D004115210CA",
INIT_09 => X"400E100160DED0FFA0DE400F10FE60DED0034004108160DED0224002101160DE",
INIT_0A => X"141E02101102100160DED0C0400A108160DED011400C102260DED080400860DE",
INIT_0B => X"C410B40360DEC030A310F1C3E01012FF110A1012D11081409305B034D103C020",
INIT_0C => X"C0C2468060DED00300C260DED002454014C21500100112071205100120C560DE",
INIT_0D => X"20DF20DE50001DC900DB00DB60DCDDC9610010DF110060DED00380C260DED003",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"F00F50D50313034313034313034351374D434F7D0F7D0D50D534D74D4353DD26",
INITP_01 => X"0000000000000000A8AD837DDDF6021B4D28082A00D4D4D74DD353535D374F00",
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INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(31 downto 0),
DOPADOP => data_out_a(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(31 downto 0),
DOPBDOP => data_out_b(35 downto 32),
DIBDI => data_in_b(31 downto 0),
DIPBDIP => data_in_b(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_2k_generate;
--
--
ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate
s6: if (C_FAMILY = "S6") generate
--
address_a(13 downto 0) <= address(10 downto 0) & "000";
data_in_a <= "000000000000000000000000000000000000";
--
s6_a11_flop: FD
port map ( D => address(11),
Q => pipe_a11,
C => clk);
--
s6_4k_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(0),
I1 => data_out_a_hl(0),
I2 => data_out_a_ll(1),
I3 => data_out_a_hl(1),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(0),
O6 => instruction(1));
--
s6_4k_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(2),
I1 => data_out_a_hl(2),
I2 => data_out_a_ll(3),
I3 => data_out_a_hl(3),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(2),
O6 => instruction(3));
--
s6_4k_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(4),
I1 => data_out_a_hl(4),
I2 => data_out_a_ll(5),
I3 => data_out_a_hl(5),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(4),
O6 => instruction(5));
--
s6_4k_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(6),
I1 => data_out_a_hl(6),
I2 => data_out_a_ll(7),
I3 => data_out_a_hl(7),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(6),
O6 => instruction(7));
--
s6_4k_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_ll(32),
I1 => data_out_a_hl(32),
I2 => data_out_a_lh(0),
I3 => data_out_a_hh(0),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(8),
O6 => instruction(9));
--
s6_4k_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(1),
I1 => data_out_a_hh(1),
I2 => data_out_a_lh(2),
I3 => data_out_a_hh(2),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(10),
O6 => instruction(11));
--
s6_4k_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(3),
I1 => data_out_a_hh(3),
I2 => data_out_a_lh(4),
I3 => data_out_a_hh(4),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(12),
O6 => instruction(13));
--
s6_4k_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(5),
I1 => data_out_a_hh(5),
I2 => data_out_a_lh(6),
I3 => data_out_a_hh(6),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(14),
O6 => instruction(15));
--
s6_4k_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_a_lh(7),
I1 => data_out_a_hh(7),
I2 => data_out_a_lh(32),
I3 => data_out_a_hh(32),
I4 => pipe_a11,
I5 => '1',
O5 => instruction(16),
O6 => instruction(17));
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_ll <= "000" & data_out_b_ll(32) & "000000000000000000000000" & data_out_b_ll(7 downto 0);
data_in_b_lh <= "000" & data_out_b_lh(32) & "000000000000000000000000" & data_out_b_lh(7 downto 0);
data_in_b_hl <= "000" & data_out_b_hl(32) & "000000000000000000000000" & data_out_b_hl(7 downto 0);
data_in_b_hh <= "000" & data_out_b_hh(32) & "000000000000000000000000" & data_out_b_hh(7 downto 0);
address_b(13 downto 0) <= "00000000000000";
we_b_l(3 downto 0) <= "0000";
we_b_h(3 downto 0) <= "0000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
jtag_dout <= data_out_b_lh(32) & data_out_b_lh(7 downto 0) & data_out_b_ll(32) & data_out_b_ll(7 downto 0);
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_lh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_ll <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
data_in_b_hh <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_hl <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000";
--
s6_4k_jtag_we_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => jtag_we,
I1 => jtag_addr(11),
I2 => '1',
I3 => '1',
I4 => '1',
I5 => '1',
O5 => jtag_we_l,
O6 => jtag_we_h);
--
we_b_l(3 downto 0) <= jtag_we_l & jtag_we_l & jtag_we_l & jtag_we_l;
we_b_h(3 downto 0) <= jtag_we_h & jtag_we_h & jtag_we_h & jtag_we_h;
--
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
--
s6_4k_jtag_mux0_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(0),
I1 => data_out_b_hl(0),
I2 => data_out_b_ll(1),
I3 => data_out_b_hl(1),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(0),
O6 => jtag_dout(1));
--
s6_4k_jtag_mux2_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(2),
I1 => data_out_b_hl(2),
I2 => data_out_b_ll(3),
I3 => data_out_b_hl(3),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(2),
O6 => jtag_dout(3));
--
s6_4k_jtag_mux4_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(4),
I1 => data_out_b_hl(4),
I2 => data_out_b_ll(5),
I3 => data_out_b_hl(5),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(4),
O6 => jtag_dout(5));
--
s6_4k_jtag_mux6_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(6),
I1 => data_out_b_hl(6),
I2 => data_out_b_ll(7),
I3 => data_out_b_hl(7),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(6),
O6 => jtag_dout(7));
--
s6_4k_jtag_mux8_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_ll(32),
I1 => data_out_b_hl(32),
I2 => data_out_b_lh(0),
I3 => data_out_b_hh(0),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(8),
O6 => jtag_dout(9));
--
s6_4k_jtag_mux10_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(1),
I1 => data_out_b_hh(1),
I2 => data_out_b_lh(2),
I3 => data_out_b_hh(2),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(10),
O6 => jtag_dout(11));
--
s6_4k_jtag_mux12_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(3),
I1 => data_out_b_hh(3),
I2 => data_out_b_lh(4),
I3 => data_out_b_hh(4),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(12),
O6 => jtag_dout(13));
--
s6_4k_jtag_mux14_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(5),
I1 => data_out_b_hh(5),
I2 => data_out_b_lh(6),
I3 => data_out_b_hh(6),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(14),
O6 => jtag_dout(15));
--
s6_4k_jtag_mux16_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data_out_b_lh(7),
I1 => data_out_b_hh(7),
I2 => data_out_b_lh(32),
I3 => data_out_b_hh(32),
I4 => jtag_addr(11),
I5 => '1',
O5 => jtag_dout(16),
O6 => jtag_dout(17));
--
end generate loader;
--
kcpsm6_rom_ll: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"DE020101FFDE0000DE0101DEFB05DE1C100C10DE05040100DE01010001038001",
INIT_01 => X"0100DEA0100BABDE0A0ADEDE5DDEDE85A27BDEDE5EDEDE1AA27BDE02101001FF",
INIT_02 => X"0101FFDE100FF0DEDB53CADE0101FFDE1014CADE4253CADEF4100A0100DEFEDE",
INIT_03 => X"DEDEFFFF52CADEDEB97BA27BDE14A27B14A27BDE0101FFDE10F0F0DE9953CADE",
INIT_04 => X"0E01DEFFDE0FFEDE030481DE220211DE0100DE0680DEFFDE077FDEDE200452CA",
INIT_05 => X"1003DE3010C310FF0A121040053403201E100201DEC00A81DE110C22DE8008DE",
INIT_06 => X"DFDE00C9DBDBDCC900DF00DE03C2DE03C280DE03C2DE0240C20001070501C5DE",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000001C2FF01",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000011A001400CBA20000000000A28A24440440440200408888200004052",
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INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_ll(31 downto 0),
DOPA => data_out_a_ll(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_ll(31 downto 0),
DOPB => data_out_b_ll(35 downto 32),
DIB => data_in_b_ll(31 downto 0),
DIPB => data_in_b_ll(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_lh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"B0E8988808B08808B0E888F08808B0E8800808B0E88808B8B0E8B8B00810A740",
INIT_01 => X"C808B0E8C00808B0C808B0F098B0F0880808F09098D090880808B0E890800808",
INIT_02 => X"28880890200808B0E82808D0188808B0100808B0E81808B0E8D008C80890D8F0",
INIT_03 => X"F0907868080890F0F8E80808B0F9F8E8090808D0388808B0300808B0E83808D0",
INIT_04 => X"A008B0E8D0A008B0E8A008B0E8A008B0E8A0B0A008B0E8D0A008D0B078680808",
INIT_05 => X"E25AB0E05178700908086840495868600A010808B0E8A008B0E8A008B0E8A0B0",
INIT_06 => X"1010280E0000B0EE300808B0E8C0B0E8E0A3B0E880B0E8220A0A0809098810B0",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"00000000000000000000000000000000000000000000000000000000480008B8",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"00000000EE96AD132627088929112530C30811111111110521363620849211A5",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"000000000000000000000000000000000000000000000000000000000000000D",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_lh(31 downto 0),
DOPA => data_out_a_lh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_lh(31 downto 0),
DOPB => data_out_b_lh(35 downto 32),
DIB => data_in_b_lh(31 downto 0),
DIPB => data_in_b_lh(35 downto 32),
WEB => we_b_l(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hl: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hl(31 downto 0),
DOPA => data_out_a_hl(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hl(31 downto 0),
DOPB => data_out_b_hl(35 downto 32),
DIB => data_in_b_hl(31 downto 0),
DIPB => data_in_b_hl(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
kcpsm6_rom_hh: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map( ADDRA => address_a(13 downto 0),
ENA => enable,
CLKA => clk,
DOA => data_out_a_hh(31 downto 0),
DOPA => data_out_a_hh(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b(13 downto 0),
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_hh(31 downto 0),
DOPB => data_out_b_hh(35 downto 32),
DIB => data_in_b_hh(31 downto 0),
DIPB => data_in_b_hh(35 downto 32),
WEB => we_b_h(3 downto 0),
REGCEB => '0',
RSTB => '0');
--
end generate s6;
--
--
v6 : if (C_FAMILY = "V6") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"DE020101FFDE0000DE0101DEFB05DE1C100C10DE05040100DE01010001038001",
INIT_01 => X"0100DEA0100BABDE0A0ADEDE5DDEDE85A27BDEDE5EDEDE1AA27BDE02101001FF",
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INIT_03 => X"DEDEFFFF52CADEDEB97BA27BDE14A27B14A27BDE0101FFDE10F0F0DE9953CADE",
INIT_04 => X"0E01DEFFDE0FFEDE030481DE220211DE0100DE0680DEFFDE077FDEDE200452CA",
INIT_05 => X"1003DE3010C310FF0A121040053403201E100201DEC00A81DE110C22DE8008DE",
INIT_06 => X"DFDE00C9DBDBDCC900DF00DE03C2DE03C280DE03C2DE0240C20001070501C5DE",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"B0E8988808B08808B0E888F08808B0E8800808B0E88808B8B0E8B8B00810A740",
INIT_01 => X"C808B0E8C00808B0C808B0F098B0F0880808F09098D090880808B0E890800808",
INIT_02 => X"28880890200808B0E82808D0188808B0100808B0E81808B0E8D008C80890D8F0",
INIT_03 => X"F0907868080890F0F8E80808B0F9F8E8090808D0388808B0300808B0E83808D0",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate v6;
--
--
akv7 : if (C_FAMILY = "7S") generate
--
address_a <= '1' & address(11 downto 0) & "111";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "000000000000000000000000000000000000";
jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0);
--
no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
address_b <= "1111111111111111";
we_b <= "00000000";
enable_b <= '0';
rdl <= '0';
clk_b <= '0';
end generate no_loader;
--
loader : if (C_JTAG_LOADER_ENABLE = 1) generate
data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9);
data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0);
address_b <= '1' & jtag_addr(11 downto 0) & "111";
we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we;
enable_b <= jtag_en(0);
rdl <= rdl_bus(0);
clk_b <= jtag_clk;
end generate loader;
--
kcpsm6_rom_l: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"DE020101FFDE0000DE0101DEFB05DE1C100C10DE05040100DE01010001038001",
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INIT_03 => X"DEDEFFFF52CADEDEB97BA27BDE14A27B14A27BDE0101FFDE10F0F0DE9953CADE",
INIT_04 => X"0E01DEFFDE0FFEDE030481DE220211DE0100DE0680DEFFDE077FDEDE200452CA",
INIT_05 => X"1003DE3010C310FF0A121040053403201E100201DEC00A81DE110C22DE8008DE",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_l(31 downto 0),
DOPADOP => data_out_a_l(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_l(31 downto 0),
DOPBDOP => data_out_b_l(35 downto 32),
DIBDI => data_in_b_l(31 downto 0),
DIPBDIP => data_in_b_l(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
kcpsm6_rom_h: RAMB36E1
generic map ( READ_WIDTH_A => 9,
WRITE_WIDTH_A => 9,
DOA_REG => 0,
INIT_A => X"000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 9,
WRITE_WIDTH_B => 9,
DOB_REG => 0,
INIT_B => X"000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
SIM_DEVICE => "7SERIES",
INIT_00 => X"B0E8988808B08808B0E888F08808B0E8800808B0E88808B8B0E8B8B00810A740",
INIT_01 => X"C808B0E8C00808B0C808B0F098B0F0880808F09098D090880808B0E890800808",
INIT_02 => X"28880890200808B0E82808D0188808B0100808B0E81808B0E8D008C80890D8F0",
INIT_03 => X"F0907868080890F0F8E80808B0F9F8E8090808D0388808B0300808B0E83808D0",
INIT_04 => X"A008B0E8D0A008B0E8A008B0E8A008B0E8A0B0A008B0E8D0A008D0B078680808",
INIT_05 => X"E25AB0E05178700908086840495868600A010808B0E8A008B0E8A008B0E8A0B0",
INIT_06 => X"1010280E0000B0EE300808B0E8C0B0E8E0A3B0E880B0E8220A0A0809098810B0",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
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port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a_h(31 downto 0),
DOPADOP => data_out_a_h(35 downto 32),
DIADI => data_in_a(31 downto 0),
DIPADIP => data_in_a(35 downto 32),
WEA => "0000",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b_h(31 downto 0),
DOPBDOP => data_out_b_h(35 downto 32),
DIBDI => data_in_b_h(31 downto 0),
DIPBDIP => data_in_b_h(35 downto 32),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0',
CASCADEINA => '0',
CASCADEINB => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0');
--
end generate akv7;
--
end generate ram_4k_generate;
--
--
--
--
-- JTAG Loader
--
instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate
--
jtag_loader_6_inst : jtag_loader_6
generic map( C_FAMILY => C_FAMILY,
C_NUM_PICOBLAZE => 1,
C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE,
C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH,
C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH)
port map( picoblaze_reset => rdl_bus,
jtag_en => jtag_en,
jtag_din => jtag_din,
jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0),
jtag_clk => jtag_clk,
jtag_we => jtag_we,
jtag_dout_0 => jtag_dout,
jtag_dout_1 => jtag_dout, -- ports 1-7 are not used
jtag_dout_2 => jtag_dout, -- in a 1 device debug
jtag_dout_3 => jtag_dout, -- session. However, Synplify
jtag_dout_4 => jtag_dout, -- etc require all ports to
jtag_dout_5 => jtag_dout, -- be connected
jtag_dout_6 => jtag_dout,
jtag_dout_7 => jtag_dout);
--
end generate instantiate_loader;
--
end low_level_definition;
--
--
-------------------------------------------------------------------------------------------
--
-- JTAG Loader
--
-------------------------------------------------------------------------------------------
--
--
-- JTAG Loader 6 - Version 6.00
-- Kris Chaplin 4 February 2010
-- Ken Chapman 15 August 2011 - Revised coding style
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
library unisim;
use unisim.vcomponents.all;
--
entity jtag_loader_6 is
generic( C_JTAG_LOADER_ENABLE : integer := 1;
C_FAMILY : string := "V6";
C_NUM_PICOBLAZE : integer := 1;
C_BRAM_MAX_ADDR_WIDTH : integer := 10;
C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18;
C_JTAG_CHAIN : integer := 2;
C_ADDR_WIDTH_0 : integer := 10;
C_ADDR_WIDTH_1 : integer := 10;
C_ADDR_WIDTH_2 : integer := 10;
C_ADDR_WIDTH_3 : integer := 10;
C_ADDR_WIDTH_4 : integer := 10;
C_ADDR_WIDTH_5 : integer := 10;
C_ADDR_WIDTH_6 : integer := 10;
C_ADDR_WIDTH_7 : integer := 10);
port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0');
jtag_clk : out std_logic := '0';
jtag_we : out std_logic := '0';
jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0));
end jtag_loader_6;
--
architecture Behavioral of jtag_loader_6 is
--
signal num_picoblaze : std_logic_vector(2 downto 0);
signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0);
--
signal drck : std_logic;
signal shift_clk : std_logic;
signal shift_din : std_logic;
signal shift_dout : std_logic;
signal shift : std_logic;
signal capture : std_logic;
--
signal control_reg_ce : std_logic;
signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0);
signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0');
signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0);
signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0');
signal control_dout_int : std_logic_vector(7 downto 0):= (others => '0');
signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0');
signal jtag_we_int : std_logic;
signal jtag_clk_int : std_logic;
signal bram_ce_valid : std_logic;
signal din_load : std_logic;
--
signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0);
signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0');
--
begin
bus_zero <= (others => '0');
--
jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate
--
-- Insert BSCAN primitive for target device architecture.
--
BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate
begin
BSCAN_BLOCK_inst : BSCAN_SPARTAN6
generic map ( JTAG_CHAIN => C_JTAG_CHAIN)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_SPARTAN6_gen;
--
BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate
begin
BSCAN_BLOCK_inst: BSCAN_VIRTEX6
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => FALSE)
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_VIRTEX6_gen;
--
BSCAN_7SERIES_gen: if (C_FAMILY="7S") generate
begin
BSCAN_BLOCK_inst: BSCANE2
generic map( JTAG_CHAIN => C_JTAG_CHAIN,
DISABLE_JTAG => "FALSE")
port map( CAPTURE => capture,
DRCK => drck,
RESET => open,
RUNTEST => open,
SEL => bram_ce_valid,
SHIFT => shift,
TCK => open,
TDI => shift_din,
TMS => open,
UPDATE => jtag_clk_int,
TDO => shift_dout);
end generate BSCAN_7SERIES_gen;
--
--
-- Insert clock buffer to ensure reliable shift operations.
--
upload_clock: BUFG
port map( I => drck,
O => shift_clk);
--
--
-- Shift Register
--
--
control_reg_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk = '1' then
if (shift = '1') then
control_reg_ce <= shift_din;
end if;
end if;
end process control_reg_ce_shift;
--
bram_ce_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
if(C_NUM_PICOBLAZE > 1) then
for i in 0 to C_NUM_PICOBLAZE-2 loop
bram_ce(i+1) <= bram_ce(i);
end loop;
end if;
bram_ce(0) <= control_reg_ce;
end if;
end if;
end process bram_ce_shift;
--
bram_we_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
jtag_we_int <= bram_ce(C_NUM_PICOBLAZE-1);
end if;
end if;
end process bram_we_shift;
--
bram_a_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (shift = '1') then
for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop
jtag_addr_int(i+1) <= jtag_addr_int(i);
end loop;
jtag_addr_int(0) <= jtag_we_int;
end if;
end if;
end process bram_a_shift;
--
bram_d_shift: process (shift_clk)
begin
if shift_clk'event and shift_clk='1' then
if (din_load = '1') then
jtag_din_int <= bram_dout_int;
elsif (shift = '1') then
for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop
jtag_din_int(i+1) <= jtag_din_int(i);
end loop;
jtag_din_int(0) <= jtag_addr_int(C_BRAM_MAX_ADDR_WIDTH-1);
end if;
end if;
end process bram_d_shift;
--
shift_dout <= jtag_din_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1);
--
--
din_load_select:process (bram_ce, din_load, capture, bus_zero, control_reg_ce)
begin
if ( bram_ce = bus_zero ) then
din_load <= capture and control_reg_ce;
else
din_load <= capture;
end if;
end process din_load_select;
--
--
-- Control Registers
--
num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3);
picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5);
--
control_registers: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '0') and (control_reg_ce = '1') then
case (jtag_addr_int(3 downto 0)) is
when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB
-- and (3 downto 0) picoblaze instruction data width
control_dout_int <= num_picoblaze & picoblaze_instruction_data_width;
when "0001" => -- 1 = PicoBlaze 0 reset / status
if (C_NUM_PICOBLAZE >= 1) then
control_dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0010" => -- 2 = PicoBlaze 1 reset / status
if (C_NUM_PICOBLAZE >= 2) then
control_dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0011" => -- 3 = PicoBlaze 2 reset / status
if (C_NUM_PICOBLAZE >= 3) then
control_dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0100" => -- 4 = PicoBlaze 3 reset / status
if (C_NUM_PICOBLAZE >= 4) then
control_dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0101" => -- 5 = PicoBlaze 4 reset / status
if (C_NUM_PICOBLAZE >= 5) then
control_dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0110" => -- 6 = PicoBlaze 5 reset / status
if (C_NUM_PICOBLAZE >= 6) then
control_dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "0111" => -- 7 = PicoBlaze 6 reset / status
if (C_NUM_PICOBLAZE >= 7) then
control_dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1000" => -- 8 = PicoBlaze 7 reset / status
if (C_NUM_PICOBLAZE >= 8) then
control_dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) );
else
control_dout_int <= (others => '0');
end if;
when "1111" => control_dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8);
when others => control_dout_int <= (others => '1');
end case;
else
control_dout_int <= (others => '0');
end if;
end if;
end process control_registers;
--
control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8) <= control_dout_int;
--
pb_reset: process(jtag_clk_int)
begin
if (jtag_clk_int'event and jtag_clk_int = '1') then
if (bram_ce_valid = '1') and (jtag_we_int = '1') and (control_reg_ce = '1') then
picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= control_din(C_NUM_PICOBLAZE-1 downto 0);
end if;
end if;
end process pb_reset;
--
--
-- Assignments
--
control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8);
--
-- Qualify the blockram CS signal with bscan select output
jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0');
--
jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int;
jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8);
--
bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked;
--
control_din <= jtag_din_int;
--
jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0');
jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0');
jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0');
jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0');
jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0');
jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0');
jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0');
jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0');
--
jtag_en <= jtag_en_int;
jtag_din <= jtag_din_int;
jtag_addr <= jtag_addr_int;
jtag_clk <= jtag_clk_int;
jtag_we <= jtag_we_int;
picoblaze_reset <= picoblaze_reset_int;
--
end generate jtag_loader_gen;
--
end Behavioral;
--
--
------------------------------------------------------------------------------------
--
-- END OF FILE test_assembler.vhd
--
------------------------------------------------------------------------------------
|
apache-2.0
|
917d4663a628d0ddc89425feb8ac39b4
| 0.626343 | 5.990768 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/instructionMemory_tb.vhd
| 1 | 1,813 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY instructionMemory_tb IS
END instructionMemory_tb;
ARCHITECTURE behaviour OF instructionMemory_tb IS
--Declare the component that you are testing:
COMPONENT instructionMemory IS
GENERIC(
ram_size : INTEGER := 1024;
mem_delay : time := 1 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC := '0';
memread: IN STD_LOGIC := '0';
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END COMPONENT;
--all the input signals with initial values
signal clk : std_logic := '0';
constant clk_period : time := 1 ns;
signal writedata: std_logic_vector(31 downto 0);
signal address: INTEGER RANGE 0 TO 1024-1;
signal memwrite: STD_LOGIC := '0';
signal memread: STD_LOGIC := '0';
signal readdata: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal waitrequest: STD_LOGIC;
BEGIN
--dut => Device Under Test
dut: instructionMemory GENERIC MAP(
ram_size => 1024
)
PORT MAP(
clk,
writedata,
address,
memwrite,
memread,
readdata,
waitrequest
);
clk_process : process
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
BEGIN
wait for clk_period;
wait;
END PROCESS;
END;
|
gpl-3.0
|
3913307901bf6ebd3bcda922bf351c47
| 0.53337 | 4.498759 | false | false | false | false |
FearlessJojo/COPproject
|
project/ALUMUX2.vhd
| 1 | 1,564 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:31:19 11/21/2016
-- Design Name:
-- Module Name: ALUMUX2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALUMUX2 is
Port ( B : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
ALUctrl2 : in STD_LOGIC_VECTOR (1 downto 0);
ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0));
end ALUMUX2;
architecture Behavioral of ALUMUX2 is
begin
process(B, ALUOUT, MEMOUT, ALUctrl2)
begin
case ALUctrl2 is
when "00" | "01" => ALUIN2 <= B;
when "10" => ALUIN2 <= ALUOUT;
when "11" => ALUIN2 <= MEMOUT;
when others => ALUIN2 <= "0000000000000000";
end case;
end process;
end Behavioral;
|
mit
|
3331d79aff326726e5ab33cbd869730e
| 0.571611 | 3.6974 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/controller_tb.vhd
| 1 | 2,699 |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity controller_tb is
end controller_tb;
architecture controller_tb_arch of controller_tb is
component controller is
port(clk : in std_logic;
opcode : in std_logic_vector(5 downto 0);
funct : in std_logic_vector(5 downto 0);
ALU1src : out STD_LOGIC;
ALU2src : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemToReg : out STD_LOGIC;
ALUOp : out STD_LOGIC_VECTOR(4 downto 0)
);
end component;
constant clk_period : time := 1 ns;
signal clk : std_logic := '0';
signal opcodeInput,functInput : std_logic_vector(5 downto 0);
signal ALU1srcO,ALU2srcO,MemReadO,MemWriteO,RegWriteO,MemToRegO : std_logic;
signal output : std_logic_vector(4 downto 0);
begin
controllerTest : controller
port map(
clk => clk,
opcode => opcodeInput,
funct => functInput,
ALU1src => ALU1srcO,
ALU2src => ALU2srcO,
MemRead => MemReadO,
MemWrite => MemWriteO,
RegWrite => RegWriteO,
MemToReg => MemToRegO,
ALUOp => output
);
clk_process : process
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
BEGIN
wait for clk_period;
report "STARTING SIMULATION \n";
opcodeInput <= "100000";
functInput <= "000000";
wait for clk_period;
opcodeInput <= "100010";
wait for clk_period;
opcodeInput <= "001000";
wait for clk_period;
opcodeInput <= "101010";
wait for clk_period;
opcodeInput <= "001010";
wait for clk_period;
opcodeInput <= "100100";
wait for clk_period;
opcodeInput <= "100101";
wait for clk_period;
opcodeInput <= "100111";
wait for clk_period;
opcodeInput <= "100110";
wait for clk_period;
opcodeInput <= "001100";
wait for clk_period;
opcodeInput <= "001101";
wait for clk_period;
opcodeInput <= "001110";
wait for clk_period;
opcodeInput <= "001111";
wait for clk_period;
opcodeInput <= "000010";
wait for clk_period;
opcodeInput <= "100011";
wait for clk_period;
opcodeInput <= "101011";
wait for clk_period;
opcodeInput <= "000100";
wait for clk_period;
opcodeInput <= "000101";
wait for clk_period;
opcodeInput <= "000011";
wait for clk_period;
--OPCODE WITH FUNCT
opcodeInput <= "000000";
wait for clk_period;
functInput <= "011010";
wait for clk_period;
functInput <= "011000";
wait for clk_period;
functInput <= "000011";
wait for clk_period;
functInput <= "001010";
wait for clk_period;
functInput <= "001100";
wait;
end process;
end controller_tb_arch;
|
gpl-3.0
|
68573c3b035b02f2e70e2290ccc19501
| 0.651723 | 3.420786 | false | false | false | false |
GHackAnonymous/SimonGameVHDL
|
LFSR.srcs/sim_1/new/Testbench.vhd
| 1 | 2,883 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Testbench is
end Testbench;
architecture Behavioral of Testbench is
component Main
Port (Led: out STD_LOGIC_VECTOR(3 downto 0);
Display: out STD_LOGIC_VECTOR(6 downto 0);
Botones: in STD_LOGIC_VECTOR(3 downto 0);
switch: in STD_LOGIC;
clock: in STD_LOGIC);
end component;
signal sigBotones : STD_LOGIC_VECTOR(3 downto 0);
signal sigLed : STD_LOGIC_VECTOR(3 downto 0);
signal sigclock : STD_LOGIC;
signal sigswitch : STD_LOGIC;
signal sigDisplay : STD_LOGIC_VECTOR(6 downto 0);
begin
UUT: Main
Port map ( clock => sigclock,
Led => sigLed,
Botones => sigBotones,
switch => sigswitch,
Display => sigDisplay);
--component LFSR
-- Port ( clk : in std_logic ;
-- value32 : out std_logic_vector ( 31 downto 0 );
-- value16 : out std_logic_vector ( 15 downto 0 );
-- value8 : out std_logic_vector ( 7 downto 0 );
-- value4 : out std_logic_vector ( 3 downto 0 );
-- value2 : out std_logic_vector ( 1 downto 0 );
-- value2_2 : out std_logic_vector ( 1 downto 0 );
-- value2_3 : out std_logic_vector ( 1 downto 0 );
-- value2_4 : out std_logic_vector ( 1 downto 0 ));
--end component;
--signal sigvalue32 : std_logic_vector ( 31 downto 0 );
--signal sigvalue16 : std_logic_vector ( 15 downto 0 );
--signal sigvalue8 : std_logic_vector ( 7 downto 0 );
--signal sigvalue4 : std_logic_vector ( 3 downto 0 );
--signal sigvalue2 : std_logic_vector ( 1 downto 0 );
--signal sigvalue2_2 : std_logic_vector ( 1 downto 0 );
--signal sigvalue2_3 : std_logic_vector ( 1 downto 0 );
--signal sigvalue2_4 : std_logic_vector ( 1 downto 0 );
--signal sigclk : STD_LOGIC;
--begin
--UUT: LFSR
-- Port map ( clk => sigclk,
-- value32 => sigvalue32,
-- value16 => sigvalue16,
-- value8 => sigvalue8,
-- value4 => sigvalue4,
-- value2 => sigvalue2,
-- value2_2 => sigvalue2_2,
-- value2_3 => sigvalue2_3,
-- value2_4 => sigvalue2_4);
--Process del clock, 100KHz 1S/50MHz*2 = 10ns
process
begin
sigclock <= '0';
wait for 5ns;
sigclock <= '1';
wait for 5ns;
end process;
process
begin
sigswitch <= '0';
wait for 567ns;
sigswitch <= '1';
wait;
end process;
process
begin
sigBotones <= "0000"; --Antes de empezar
wait for 51ms;
sigBotones <= "0100"; --Primer turno y segundo turno comienzo
wait for 151000 ns;
sigBotones <= "1000"; --Segundo turno led 2
wait for 299000ns;
sigBotones <= "0100"; --Tercer turno comienzo
wait for 20000ns;
sigBotones <= "1000"; --Tercer turno led 2 y 3
wait for 430001 ns;
sigBotones <= "0100";
wait for 20000ns;
sigBotones <= "1000";
wait for 100000ns;
sigBotones <= "0100";
wait;
end process;
end Behavioral;
|
gpl-3.0
|
5c26e5f0f5612beb5d54697d637bc1f1
| 0.613944 | 3.157722 | false | false | false | false |
FearlessJojo/COPproject
|
project/ALUMUX1.vhd
| 1 | 1,564 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:25:14 11/21/2016
-- Design Name:
-- Module Name: ALUMUX1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALUMUX1 is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
ALUctrl1 : in STD_LOGIC_VECTOR (1 downto 0);
ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0));
end ALUMUX1;
architecture Behavioral of ALUMUX1 is
begin
process(A, ALUOUT, MEMOUT, ALUctrl1)
begin
case ALUctrl1 is
when "00" | "01" => ALUIN1 <= A;
when "10" => ALUIN1 <= ALUOUT;
when "11" => ALUIN1 <= MEMOUT;
when others => ALUIN1 <= "0000000000000000";
end case;
end process;
end Behavioral;
|
mit
|
74c2c1f07f348cc53d5a5adab2fcd4b4
| 0.571611 | 3.6974 | false | false | false | false |
FearlessJojo/COPproject
|
project/ALU.vhd
| 1 | 2,153 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:21 11/20/2016
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ALUIN1 : in STD_LOGIC_VECTOR (15 downto 0);
ALUIN2 : in STD_LOGIC_VECTOR (15 downto 0);
ALUOUT : out STD_LOGIC_VECTOR (15 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(OP, ALUIN1, ALUIN2)
variable num : integer range 0 to 15;
begin
case OP is
when "0000" => ALUOUT <= ALUIN1 + ALUIN2;
when "0001" => ALUOUT <= ALUIN1 - ALUIN2;
when "0010" => ALUOUT <= ALUIN1 and ALUIN2;
when "0011" => ALUOUT <= ALUIN1 or ALUIN2;
when "0100" => ALUOUT <= ALUIN1 xor ALUIN2;
when "0101" => ALUOUT <= not ALUIN1;
when "0110" => ALUOUT <= to_stdlogicvector(to_bitvector(ALUIN1) sll conv_integer(ALUIN2));
when "0111" => ALUOUT <= to_stdlogicvector(to_bitvector(ALUIN1) srl conv_integer(ALUIN2));
when "1000" =>
num := conv_integer(ALUIN2);
ALUOUT <= SXT(ALUIN1(15 downto num), ALUOUT'length);
when "1001" => ALUOUT <= to_stdlogicvector(to_bitvector(ALUIN1) rol conv_integer(ALUIN2));
when "1010" => ALUOUT <= ALUIN1;
when "1011" => ALUOUT <= ALUIN2;
when others => ALUOUT <= "0000000000000000";
end case;
end process;
end Behavioral;
|
mit
|
094278c5fcce7cdba9d325294ec95165
| 0.59359 | 3.570481 | false | false | false | false |
jviki/mem_swapping
|
mem_swapping.vhd
| 1 | 6,400 |
-- mem_swapping.vhd
-- Jan Viktorin <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.log2;
---
-- Provides BRAM memory model that swaps
-- its contents to filesystem. This can
-- solve the issue with ISIM to not allocate
-- very huge amount of memory.
---
entity mem_swapping is
generic (
MEM_CAP : integer := 640 * 480;
MEM_LINE : integer := 19200;
DWIDTH : integer := 8;
PREFIX : string := "mem"
);
port (
CLK : in std_logic;
RST : in std_logic;
MEM_A0 : in std_logic_vector(log2(MEM_CAP) - 1 downto 0);
MEM_DIN0 : in std_logic_vector(DWIDTH - 1 downto 0);
MEM_DOUT0 : out std_logic_vector(DWIDTH - 1 downto 0);
MEM_WE0 : in std_logic_vector(DWIDTH / 8 - 1 downto 0);
MEM_RE0 : in std_logic;
MEM_DRDY0 : out std_logic;
MEM_A1 : in std_logic_vector(log2(MEM_CAP) - 1 downto 0);
MEM_DIN1 : in std_logic_vector(DWIDTH - 1 downto 0);
MEM_DOUT1 : out std_logic_vector(DWIDTH - 1 downto 0);
MEM_WE1 : in std_logic_vector(DWIDTH / 8 - 1 downto 0);
MEM_RE1 : in std_logic;
MEM_DRDY1 : out std_logic
);
end entity;
architecture full of mem_swapping is
constant ADDRW : integer := log2(MEM_CAP);
subtype memaddr_t is std_logic_vector(ADDRW - 1 downto 0);
subtype memcell_t is std_logic_vector(DWIDTH - 1 downto 0);
subtype membe_t is std_logic_vector(DWIDTH / 8 - 1 downto 0);
type mempart_t is array(0 to MEM_LINE - 1) of memcell_t;
type memfile_t is file of memcell_t;
--------------------------------------------------------
function get_memname(base : in integer) return string is
begin
assert base >= 0
report "[MEM] Invalid base for access memory: " & integer'image(base)
severity failure;
return PREFIX & "/mem_" & integer'image(base);
end function;
function to_base(addr : in memaddr_t) return integer is
begin
return (conv_integer(addr) / MEM_LINE) * MEM_LINE;
end function;
--------------------------------------------------------
procedure mem_load(base : in integer; mem : out mempart_t; dirty : out boolean) is
file fd : memfile_t;
variable fstat : file_open_status;
begin
file_open(fstat, fd, get_memname(base), READ_MODE);
if fstat /= OPEN_OK then
report "[MEM] Can not open file " & get_memname(base) & ", init to X";
for i in mem'range loop
mem(i) := (others => 'X');
end loop;
else
for i in mem'range loop
if endfile(fd) then
report "[MEM] File is shorter then memory, finished at " & integer'image(i);
exit;
end if;
read(fd, mem(i));
end loop;
-- report "[MEM] Memory reloaded";
dirty := false;
file_close(fd);
end if;
end procedure;
procedure mem_save(base : in integer; mem : in mempart_t; dirty : in boolean) is
file fd : memfile_t;
variable fstat : file_open_status;
begin
if base = -1 or dirty = false then
return;
end if;
file_open(fstat, fd, get_memname(base), WRITE_MODE);
assert fstat = OPEN_OK
report "[MEM] Can not open file " & get_memname(base)
severity failure;
for i in mem'range loop
write(fd, mem(i));
end loop;
end procedure;
procedure mem_access(mem : inout mempart_t; base : inout integer;
addr : in memaddr_t; dirty : inout boolean) is
variable newbase : integer;
begin
newbase := to_base(addr);
if newbase /= base then
report "[MEM] Reloading memory block "
& integer'image(base)
& " => "
& integer'image(newbase)
& " ("
& integer'image(conv_integer(addr))
& ")";
mem_save(base, mem, dirty);
mem_load(newbase, mem, dirty);
base := newbase;
end if;
end procedure;
--------------------------------------------------------
procedure mem_read(mem : inout mempart_t; base : inout integer;
addr : in memaddr_t; data : out memcell_t;
dirty : inout boolean) is
variable addrbase : integer;
variable addroff : integer;
begin
addrbase := to_base(addr);
addroff := conv_integer(addr) - addrbase;
mem_access(mem, base, addr, dirty);
data := mem(addroff);
end procedure;
procedure mem_write(mem : inout mempart_t; base : inout integer;
addr : in memaddr_t; data : in memcell_t;
be : in membe_t; dirty : inout boolean) is
variable addrbase : integer;
variable addroff : integer;
variable val : memcell_t;
begin
addrbase := to_base(addr);
addroff := conv_integer(addr) - addrbase;
mem_access(mem, base, addr, dirty);
val := mem(addroff);
for i in val'range loop
if be(i / 8) = '1' then
val(i) := data(i);
end if;
end loop;
if mem(addroff) /= val then
mem(addroff) := val;
dirty := true;
end if;
end procedure;
--------------------------------------------------------
shared variable mem : mempart_t;
shared variable dirty: boolean := false;
shared variable base : integer := -1;
begin
assert (MEM_CAP mod MEM_LINE) = 0
report "MEM_LINE must be multiple of MEM_CAP"
severity failure;
--------------------------------------------------------
mem_writep : process(CLK, MEM_WE0, MEM_A0, MEM_DIN0, MEM_WE1, MEM_A1, MEM_DIN1)
variable addr : memaddr_t;
variable din : memcell_t;
begin
if rising_edge(CLK) then
if MEM_WE0 /= (MEM_WE0'range => '0') then
addr := MEM_A0;
din := MEM_DIN0;
mem_write(mem, base, addr, din, MEM_WE0, dirty);
end if;
if MEM_WE1 /= (MEM_WE1'range => '0') then
addr := MEM_A1;
din := MEM_DIN1;
mem_write(mem, base, addr, din, MEM_WE1, dirty);
end if;
end if;
end process;
mem_readp : process(CLK, MEM_RE0, MEM_A0, MEM_RE1, MEM_A1)
variable addr : memaddr_t;
variable dout : memcell_t;
begin
if rising_edge(CLK) then
if MEM_RE0 = '1' then
addr := MEM_A0;
mem_read(mem, base, addr, dout, dirty);
MEM_DOUT0 <= dout;
end if;
if MEM_RE1 = '1' then
addr := MEM_A1;
mem_read(mem, base, addr, dout, dirty);
MEM_DOUT1 <= dout;
end if;
end if;
end process;
mem_drdyp : process(CLK, MEM_RE0, MEM_RE1)
begin
if rising_edge(CLK) then
if RST = '1' then
MEM_DRDY0 <= '0';
MEM_DRDY1 <= '0';
else
MEM_DRDY0 <= MEM_RE0;
MEM_DRDY1 <= MEM_RE1;
end if;
end if;
end process;
end architecture;
|
gpl-2.0
|
739797119e6b803762cb7fdcf9a82940
| 0.596875 | 2.95203 | false | false | false | false |
GHackAnonymous/SimonGameVHDL
|
LFSR.srcs/sources_1/new/LFSR.vhd
| 1 | 2,461 |
library IEEE ;
use IEEE . Std_logic_1164 . ALL ;
use IEEE . NUMERIC_STD . ALL ;
entity LFSR is
Port ( clk : in std_logic ;
value32 : out std_logic_vector ( 31 downto 0 );
value16 : out std_logic_vector ( 15 downto 0 );
value8 : out std_logic_vector ( 7 downto 0 );
value4 : out std_logic_vector ( 3 downto 0 );
value2 : out std_logic_vector ( 1 downto 0 );
value2_2 : out std_logic_vector ( 1 downto 0 );
value2_3 : out std_logic_vector ( 1 downto 0 );
value2_4 : out std_logic_vector ( 1 downto 0 ));
end LFSR ;
architecture Behavioral of LFSR is
signal rnd32 : std_logic_vector ( 31 downto 0 ):= ( others => '0' );
signal rnd16 : std_logic_vector ( 15 downto 0 ):= ( others => '0' );
signal rnd8 : std_logic_vector ( 7 downto 0 ):= ( others => '0' );
signal rnd4 : std_logic_vector ( 3 downto 0 ):= ( others => '0' );
signal rnd2 : std_logic_vector ( 1 downto 0 ):= ( others => '0' );
signal rnd2_2 : std_logic_vector ( 1 downto 0 ):= ( others => '0' );
signal rnd2_3 : std_logic_vector ( 1 downto 0 ):= ( others => '0' );
signal rnd2_4 : std_logic_vector ( 1 downto 0 ):= ( others => '0' );
begin
process begin
wait until rising_edge ( CLK );
rnd2 (1) <= rnd2 (0);
rnd2 (0) <= not rnd8(3) XOR rnd8(1);
rnd2_2 (1) <= rnd2 (0);
rnd2_2 (0) <= not rnd8(4) XOR rnd8(2);
rnd2_3 (1) <= rnd2 (0);
rnd2_3 (0) <= not rnd8(5) XOR rnd8(3);
rnd2_4 (1) <= rnd2 (0);
rnd2_4 (0) <= not rnd8(6) XOR rnd8(0);
rnd4 ( 3 downto 1 ) <= rnd4 ( 2 downto 0 );
rnd4 ( 0 ) <= not ( rnd4 ( 3 ) XOR rnd8 ( 2 ) XOR rnd8 ( 1 ));
rnd8 ( 7 downto 1 ) <= rnd8 ( 6 downto 0 );
rnd8 ( 0 ) <= not ( rnd8 ( 7 ) XOR rnd8 ( 6 ) XOR rnd8 ( 4 ));
rnd16 ( 15 downto 1 ) <= rnd16 ( 14 downto 0 );
rnd16 ( 0 ) <= not ( rnd16 ( 15 ) XOR rnd16 ( 14 ) XOR rnd16 ( 13 ) XOR rnd16 ( 4 ));
rnd32 ( 31 downto 1 ) <= rnd32 ( 30 downto 0 );
rnd32 ( 0 ) <= not ( rnd32 ( 31 ) XOR rnd32 ( 22 ) XOR rnd32 ( 2 ) XOR rnd32 ( 1 ));
end process ;
value32 <= rnd32 ;
value16 <= rnd16 ;
value8 <= rnd8 ;
value4 <= rnd4 ;
value2 <= rnd2;
value2_2 <= rnd2_2;
value2_3 <= rnd2_3;
value2_4 <= rnd2_4;
end Behavioral ;
|
gpl-3.0
|
07fb27bd94fd13eb3de0d750aad26a2b
| 0.498171 | 2.793417 | false | false | false | false |
corywalker/vhdl_fft
|
spi_master_slave/rtl/spi_master_slave/grp_debouncer.vhd
| 5 | 13,007 |
-----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 09:56:30 07/06/2011
-- Module Name: grp_debouncer - RTL
-- Project Name: basic functions
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is a generic multiple input debouncing circuit.
-- It handles multiple inputs, like mechanical switch inputs, and outputs a debounced, stable registered version of the inputs.
-- A 'new_data' one-cycle strobe is also available, to sync downstream logic.
--
-- CONCEPTUAL CIRCUIT
-- ==================
--
-- W
-- /----------------/----------------\
-- | |
-- | |
-- | ______ ______ | _____
-- | W | | W |fdr | W | W |cmp \
-- \----/---| +1 |---/----| |--/--+----/----| \
-- | | | | | \
-- ------ | | \ |
-- | | | = |-----\
-- |> R | / | |
-- ---+-- | / |
-- | CNT_VAL---| / |
-- | |____/ |
-- | |
-- \------------\ |
-- | |
-- N ____ | |
-- /-------/---)) \ ____ | |
-- | ))XOR |-----) \ | |
-- | /------))___/ )OR |-----/ |
-- | | /---)___/ |
-- | | | |
-- | | \----------\ |
-- | | N | |
-- | \--------/-----------\ +----------------------+---------\
-- | | | |
-- \---\ | | |
-- ______ | ______ | | ______ |
-- | fd | | | fd | | | |fde | |
-- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o]
-- N | | N N | | N | | | | N | N |
-- | | | | | \---|CE | | |
-- | | | | | | | | |
-- [clk_i]----> |> | |> | | |> | | | ____ ______
-- ------ ------ | ------ | N ____ \---| \ | fd |
-- | \---/---)) \ |AND |-----| |----[strb_o]
-- | ))XOR |-----|___/ | |
-- \-------------------------/---))___/ | |
-- N | |
-- |> |
-- ------
--
--
-- PIPELINE LOGIC
-- ==============
--
-- This debouncer circuit detects edges in an input signal, and waits the signal to stabilize for the designated time
-- before transferring the stable signal to the registered output.
-- A one-clock-cyle strobe is pulsed at the output to signalize a new data available.
-- The core clock should be the system clock, to optimize use of global clock resources.
--
-- GROUP DEBOUNCING
-- ================
--
-- A change in state in any bit in the input word causes reload of the delay counter, and the output word is updated only
-- when all bits are stable for the specified period. Therefore, the grouping of signals and delay selection should match
-- behaviour of the selected signals.
--
-- RESOURCES USED
-- ==============
--
-- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers.
-- The number of LUTs inferred is roughly: ((4*N+2)/6)+2.
-- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r.
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
-- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock.
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference.
-- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45).
-- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output.
-- 2011/09/19 v1.01.0030 [JD] changed range for internal counter (cnt_reg, cnt_next) to avoid adder flipover (Altera/ModelSim).
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-- The circuit can easily be extended to have a signature of which inputs changed at the data out port.
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity grp_debouncer is
Generic (
N : positive := 8; -- input bus width
CNT_VAL : positive := 10000); -- clock counts for debounce period
Port (
clk_i : in std_logic := 'X'; -- system clock
data_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- noisy input data
data_o : out std_logic_vector (N-1 downto 0); -- registered stable output data
strb_o : out std_logic -- strobe for new data available
);
end grp_debouncer;
architecture rtl of grp_debouncer is
-- datapath pipeline
signal reg_A, reg_B : std_logic_vector (N-1 downto 0) := (others => '0'); -- debounce edge detectors
signal reg_out : std_logic_vector (N-1 downto 0) := (others => '0'); -- registered output
signal dat_strb : std_logic := '0'; -- data transfer strobe
signal strb_reg : std_logic := '0'; -- registered strobe
signal strb_next : std_logic := '0'; -- lookahead strobe
signal dat_diff : std_logic := '0'; -- edge detector
-- debounce counter
signal cnt_reg : integer range CNT_VAL + 1 downto 0 := 0; -- debounce period counter
signal cnt_next : integer range CNT_VAL + 1 downto 0 := 0; -- combinatorial signal
begin
--=============================================================================================
-- DEBOUNCE COUNTER LOGIC
--=============================================================================================
-- This counter is implemented as a up-counter with reset and final count detection via compare,
-- instead of a down-counter with preset and final count detection via nonzero detection.
-- This is better for Spartan-6 and Virtex-6 CLB architecture, because it uses less control sets.
--
-- cnt_reg register transfer logic
cnt_reg_proc: process (clk_i) is
begin
if clk_i'event and clk_i = '1' then
cnt_reg <= cnt_next;
end if;
end process cnt_reg_proc;
-- cnt_next combinatorial logic
cnt_next_proc: cnt_next <= 0 when dat_diff = '1' or dat_strb = '1' else cnt_reg + 1;
-- final count combinatorial logic
final_cnt_proc: dat_strb <= '1' when cnt_reg = CNT_VAL else '0';
--=============================================================================================
-- DATAPATH SIGNAL PIPELINE
--=============================================================================================
-- input pipeline logic
pipeline_proc: process (clk_i) is
begin
if clk_i'event and clk_i = '1' then
-- edge detection pipeline
reg_A <= data_i;
reg_B <= reg_A;
-- new data strobe pipeline delay
strb_reg <= strb_next;
end if;
-- output data pipeline
if clk_i'event and clk_i = '1' then
if dat_strb = '1' then
reg_out <= reg_B;
end if;
end if;
end process pipeline_proc;
-- edge detector
edge_detector_proc: dat_diff <= '1' when reg_A /= reg_B else '0';
-- lookahead new data strobe
next_strobe_proc: strb_next <= '1' when ((reg_out /= reg_B) and dat_strb = '1') else '0';
--=============================================================================================
-- OUTPUT LOGIC
--=============================================================================================
-- connect output ports
data_o_proc: data_o <= reg_out;
strb_o_proc: strb_o <= strb_reg;
end rtl;
|
mit
|
28fc828b52f5fbaf6513d54d9ef54fd6
| 0.340125 | 5.399336 | false | false | false | false |
corywalker/vhdl_fft
|
counter.vhd
| 3 | 1,144 |
----------------------------------------------------
-- VHDL code for n-bit counter (ESD figure 2.6)
-- by Weijun Zhang, 04/2001
--
-- this is the behavior description of n-bit counter
-- another way can be used is FSM model.
----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------------------
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0) := (others => '0');
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= (Pre_Q'range => '0');
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;
-----------------------------------------------------
|
mit
|
4df7da30c87839d7bbaaa89f3cd0dcc5
| 0.488636 | 3.726384 | false | false | false | false |
kumasento/zedboard-thesis
|
examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/sim/system_axi_gpio_0_0.vhd
| 1 | 8,743 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY system_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_axi_gpio_0_0;
ARCHITECTURE system_axi_gpio_0_0_arch OF system_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_0_arch;
|
apache-2.0
|
9209bc611eef5ac4bde3de419ca4f995
| 0.679744 | 3.251395 | false | false | false | false |
corywalker/vhdl_fft
|
outbuf_interp.vhd
| 3 | 3,778 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity outbuf_interp is
generic (
N : positive := 16;
ADDRWIDTH : positive := 12
);
port(
CLK1, spi_sck_i, addr_rst: in std_logic;
spi_miso_o: out std_logic;
addr : OUT STD_LOGIC_VECTOR(ADDRWIDTH-1 DOWNTO 0) := "0000000000";
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
end outbuf_interp;
---------------------------------------------------
architecture Behavioral of outbuf_interp is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
signal di_i: std_logic_vector (N-1 downto 0) := "0000000000000000";
signal di_req_o: std_logic;
signal wren_i: std_logic := '0';
signal spi_ssel_i: std_logic := '1';
signal cnt1_clear: std_logic;
signal cnt1_Q: unsigned (31 downto 0);
signal cnt1_Q_v: std_logic_vector (31 downto 0);
signal slower_spi_clock: std_logic := '0';
signal s_read_state: unsigned (3 downto 0) := "0000";
signal next_s_read_state: unsigned (3 downto 0) := "0010";
begin
ss1: entity work.spi_slave
generic map (N => N)
port map (
clk_i => slower_spi_clock,
spi_sck_i => spi_sck_i,
spi_ssel_i => spi_ssel_i,
di_i => di_i,
di_req_o => di_req_o,
wren_i => wren_i,
spi_miso_o => spi_miso_o
);
cnt1: entity work.counter
generic map (n => 32)
port map (
clock => CLK1,
clear => cnt1_clear,
count => '1',
Q => cnt1_Q_v
);
process(CLK1)
begin
s_read_state <= next_s_read_state;
if rising_edge(CLK1) then
slower_spi_clock <= not slower_spi_clock;
end if;
end process;
process(s_read_state, CLK1)
variable currcount: unsigned (ADDRWIDTH-1 downto 0) := (OTHERS => '0');
begin
if(addr_rst = '1') then
currcount := (OTHERS => '0');
addr <= std_logic_vector(currcount);
next_s_read_state <= "0001";
spi_ssel_i <= '1';
elsif rising_edge(CLK1) then
case s_read_state is
when "0000" =>
if di_req_o = '1' then
next_s_read_state <= "0001";
end if;
when "0001" =>
next_s_read_state <= "0010";
when "0010" =>
next_s_read_state <= "0011";
di_i <= din;
currcount := currcount + 1;
addr <= std_logic_vector(currcount);
-- We toggle ssel like this because it resets the position
-- if we change our mind about di_i.
spi_ssel_i <= '0';
when "0011" =>
next_s_read_state <= "0100";
when "0100" =>
next_s_read_state <= "0101";
when "0101" =>
next_s_read_state <= "0110";
wren_i <= '1';
when "0110" =>
next_s_read_state <= "0111";
when "0111" =>
next_s_read_state <= "1000";
when "1000" =>
next_s_read_state <= "0000";
wren_i <= '0';
when others =>
next_s_read_state <= "0000";
end case;
end if;
end process;
cnt1_clear <= di_req_o;
cnt1_Q <= unsigned(cnt1_Q_v);
end Behavioral;
|
mit
|
6ea778e55d1cb2795280b1f807516583
| 0.451032 | 3.816162 | false | false | false | false |
Speccery/fpga99
|
toplevel.vhd
| 1 | 11,932 |
-- toplevel.vhd
-- TMS9995 project for Mini Spartan 6 board with FTDI UART
-- XC6SLX9-2TQG144
--
-- toplevel.vhd
--
-- Started 2016-03-23 (C) Erik Piehl
-- Continued after a long pause 2018-05-01 to include Paul's TMS9902.
-- Fix for windows 10, reminder how to get ISE 14.7 working on win 10.
-- https://www.youtube.com/watch?v=jBJlW40kAAU
--Fixing Project Navigator, iMPACT and License Manager
--1. Open the following directory: C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64
--2. Find and rename libPortability.dll to libPortability.dll.orig
--3. Make a copy of libPortabilityNOSH.dll (copy and paste it to the same directory) and rename it libPortability.dll
--4. Copy libPortabilityNOSH.dll again, but this time navigate to C:\Xilinx\14.7\ISE_DS\common\lib\nt64 and paste it there
--5. in C:\Xilinx\14.7\ISE_DS\common\lib\nt64 Find and rename libPortability.dll to libPortability.dll.orig
--6. Rename libPortabilityNOSH.dll to libPortability.dll
--OK, I have fixed this, you can try in your windows.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.vcomponents.all; -- get xilinx ram
entity toplevel is
generic (
real9902 : boolean := false;
awidth : integer := 8;
aregs : integer := 16
);
Port(
-- MINI XC6SLX9
CLK50M : in std_logic;
SW1 : in std_logic; -- switch pushed -> high level
SW2 : in std_logic;
LED : out std_logic_vector(7 downto 0); -- high value -> LED is lit
TX : out std_logic; -- to FTDI CHIP
RX : in std_logic; -- to FTDI CHIP
-- Connections to TMS9995 board
n_RAMCE : out std_logic;
n_ROMCE : out std_logic;
CRUCLK_OUT : out std_logic;
n_CRU1 : out std_logic;
n_CRU2 : out std_logic;
n_MEMEN : in std_logic;
n_WE : in std_logic;
n_DBIN : in std_logic;
ABUS : in std_logic_vector(15 downto 0);
DBUS : inout std_logic_vector(7 downto 0);
CRUIN : out STD_LOGIC; -- output from PNR's TMS9902
-- UART routing to FTDI chip
RX02 : out std_logic;
TX02 : in std_logic;
-- NMI signals to enable single stepping
n_NMI : out std_logic;
IAQ : in std_logic;
-- SD card interface. DI and DO are from the viewpoint of the SD card interface.
n_SD_CS : out std_logic := '1';
SD_DI : out std_logic;
SD_CLK : out std_logic;
SD_DO : in std_logic;
-- MMU & other signals
n_RESET_OUT : out std_logic;
RA : out std_logic_vector(18 downto 12); -- 7 bits, let's not bring out the MSB A19
READY : out std_logic
);
end toplevel;
ARCHITECTURE toplevel_architecture OF toplevel IS
constant mmubase : std_logic_vector(15 downto 0) := x"FF40"; -- MMU's base address (memory mapped peripheral)
constant testbas : std_logic_vector(15 downto 0) := x"FF50"; -- test reg base address (memory mapped peripheral)
constant flagbas : std_logic_vector(15 downto 0) := x"0140"; -- Flagsel register in CRU address space
constant sel9902 : std_logic_vector(15 downto 0) := x"0000"; -- TMS9902 start in CRU address space
constant sel9901 : std_logic_vector(15 downto 0) := x"0040";
constant spibase : std_logic_vector(15 downto 0) := x"FF30"; -- SPI controller
signal reset : std_logic;
signal reset_delay : std_logic_vector(15 downto 0) := x"0000";
signal protect : std_logic;
signal mapen : std_logic;
signal n_romen : std_logic;
signal selmmu : std_logic := '0';
signal seltest : std_logic := '0';
signal selflag : std_logic := '0';
signal selspi : std_logic;
signal n_romce1 : std_logic;
signal ckon : std_logic;
signal ckoff : std_logic;
signal lrex : std_logic;
signal nmi_sync : std_logic_vector(2 downto 0);
signal iaq_sync : std_logic_vector(3 downto 0); -- Delay line to find rising edges of IAQ
signal spi_clk_div : unsigned(2 downto 0); -- Clock divider for SPI, div 50MHz by 8
signal spi_bit_count : unsigned(3 downto 0); -- SPI bit counter, 8 bits are always transferred
signal spi_shift_out : std_logic_vector(7 downto 0); -- outgoing SPI data, changed before rising edge, MSB out
signal spi_shift_in : std_logic_vector(7 downto 0); -- incoming SPI data, sampled on "rising edge"
signal spi_state : std_logic := '0'; -- 0 = idle, 1 = busy
signal spi_cs : std_logic := '1';
-- flag_reg:
-- bit 0 : n_romen - when zero, the first 32K of ROM overlay bottom 32K of address space
-- bit 1 : mapen - when one, the MMU is enabled
signal flag_reg : std_logic_vector(7 downto 0);
type abank is array (natural range 0 to (2**aregs)-1) of std_logic_vector(awidth-1 downto 0);
signal regs : abank;
signal translated_addr : std_logic_vector(awidth-1 downto 0);
signal we_sync : std_logic_vector(3 downto 0); -- Delay line to sample and synchronize n_WE/n_CRUCLK
signal debug : std_logic_vector(7 downto 0);
signal CRUCLK : std_logic;
-- TMS9902 by pnr
component tms9902 is
port (
CLK : in std_logic;
nRTS : out std_logic;
nDSR : in std_logic;
nCTS : in std_logic;
nINT : out std_logic;
nCE : in std_logic;
CRUOUT : in std_logic;
CRUIN : out std_logic;
CRUCLK : in std_logic;
XOUT : out std_logic;
RIN : in std_logic;
S : in std_logic_vector(4 downto 0)
);
end component;
signal tms9902_cruin : std_logic;
signal tms9902_nCE : std_logic;
signal tms9902_rts_cts : std_logic;
signal pnr9902_tx : std_logic;
signal pnr9902_rx : std_logic;
signal n_CRU1_internal : std_logic;
begin
RX02 <= RX;
pnr9902_rx <= RX;
process(TX02, pnr9902_tx)
begin
if real9902 then
TX <= TX02;
else
TX <= pnr9902_tx;
end if;
end process;
LED(0) <= not TX02;
LED(1) <= not RX;
LED(2) <= SW1;
LED(3) <= SW2;
LED(7 DOWNTO 4) <= flag_reg(3 downto 0);
-- External instruction decoding
CRUCLK_OUT <= CRUCLK;
CRUCLK <= '1' when n_memen = '1' and n_we = '0' and dbus(7 downto 5) = "000" else '0';
lrex <= '1' when n_memen = '1' and n_we = '0' and dbus(7 downto 5) = "111" else '0';
ckon <= '1' when n_memen = '1' and n_we = '0' and dbus(7 downto 5) = "101" else '0';
ckoff <= '1' when n_memen = '1' and n_we = '0' and dbus(7 downto 5) = "110" else '0';
-- Chip selects
-- RAM is enabled whenever ROM is not enabled and memory mapped registers are not accessed
n_RAMCE <= '0' when n_memen = '0' and n_romce1 = '1'
and abus(15 downto 4) /= mmubase(15 downto 4) and abus(15 downto 4) /= testbas(15 downto 4)
else '1';
-- and ((abus(15) = '1' and mapen = '0') or (ra(19) = '0' and mapen = '1'))
-- ROM is enabled if A15=0 when n_romen=0.
-- In addition, when MMU is enabled and CPU is accessing high 512K.
n_romce1 <= '0' when n_memen = '0'
and ((abus(15) = '0' and n_romen = '0') or (translated_addr(7)='1' and mapen = '1'))
else '1';
n_ROMCE <= n_romce1;
-- CRU bus: S4=A5 S3=A4 S2=A3 S1=A2 S0=A1 CRUOUT=A0
n_cru1_internal <= '0' when n_memen = '1' and abus(15 downto 6) = sel9902(15 downto 6) else '1';
n_cru2 <= '0' when n_memen = '1' and abus(15 downto 6) = sel9901(15 downto 6) else '1';
mapen <= flag_reg(1);
n_romen <= flag_reg(0);
-- NMI output
n_NMI <= nmi_sync(2);
-- Memory mapped peripherals inside FPGA
-- selmmu is high when the FPGA's MMU is being accessed
selmmu <= '1' when abus(15 downto 4) = mmubase(15 downto 4) and n_memen = '0' else '0';
seltest <= '1' when abus(15 downto 4) = testbas(15 downto 4) and n_memen = '0' else '0';
selspi <= '1' when abus(15 downto 4) = spibase(15 downto 4) and n_memen = '0' else '0';
-- CRU peripherals inside the FPGA
selflag <= '1' when abus(15 downto 4) = flagbas(15 downto 4) and n_memen = '1' else '0';
-- Driving of SPI out of the FPGA
SD_DI <= spi_shift_out(7);
SD_CLK <= spi_clk_div(2); -- MSB of the divider
n_SD_CS <= spi_cs;
-- put the MMU design here.
process (CLK50M, SW1)
begin
if SW1 = '1' then
-- Process reset here.
n_reset_out <= '0';
ready <= '0';
reset_delay <= (others => '0');
flag_reg <= x"00";
we_sync <= (others => '0');
nmi_sync <= (others => '1');
iaq_sync <= (others => '0');
spi_state <= '0';
spi_cs <= '1';
elsif rising_edge(CLK50M) then
-- take care of reset, enable zero wait states
n_reset_out <= reset_delay(8);
ready <= reset_delay(15);
reset_delay <= reset_delay(14 downto 0) & '1';
-- write to MMU
if selmmu = '1' and n_we = '0' then
regs(to_integer(unsigned(abus(3 downto 0)))) <= dbus(awidth-1 downto 0);
end if;
-- write to CRU registers
we_sync <= we_sync(2 downto 0) & not n_we; -- sample the INVERSE of n_we
if selflag = '1' and we_sync = "0011" then
flag_reg(to_integer(unsigned(abus(3 downto 1)))) <= abus(0);
end if;
-- Work on NMI generation
if lrex = '1' then
nmi_sync(0) <= '0';
end if;
iaq_sync <= iaq_sync(2 downto 0) & IAQ; -- sample IAQ
if iaq_sync = "0011" then
-- Let's see if this simple logic works. On each rising edge
-- of IAQ nmi_sync shift register advances.
-- The bit shifted in is the pending lrex (actually it's inverse).
nmi_sync <= nmi_sync(1 downto 0) & '1';
end if;
---------------------------------
-- SPI interface
---------------------------------
if spi_state = '1' then
spi_clk_div <= unsigned(spi_clk_div) + 1;
if spi_clk_div = "011" then
-- On next 50MHz clock the SPI clock becomes high, i.e. when the following
-- asignments occur
spi_shift_in <= spi_shift_in(6 downto 0) & SD_DO;
spi_bit_count <= spi_bit_count + 1;
end if;
if spi_clk_div = "111" then
spi_shift_out <= spi_shift_out(6 downto 0) & '1';
if spi_bit_count = x"8" then
-- Transfer is done! Yippee!
spi_state <= '0'; -- No more busy
spi_clk_div <= "000"; -- This may be redundant, but ensures SPI clock out is low.
end if;
end if;
end if;
-- Write to SPI port.
if selspi = '1' and we_sync = "0011" and spi_state = '0' and abus(3 downto 0) = "0000" then
spi_state <= '1';
spi_clk_div <= "000";
spi_bit_count <= (others => '0');
spi_shift_out <= dbus(7 downto 0);
end if;
if selspi = '1' and we_sync = "0011" and abus(3 downto 0) = "0010" then
-- setup chip select
spi_cs <= dbus(0);
end if;
end if;
end process;
translated_addr <=
regs(to_integer(unsigned(abus(15 downto 12)))) when mapen = '1' and selmmu = '0'
else "0000" & abus(15 downto 12);
ra(18 downto 12) <= translated_addr(6 downto 0);
debug <= std_logic_vector(spi_bit_count & '0' & spi_clk_div);
dbus <=
regs(to_integer(unsigned(abus(3 downto 0)))) when n_DBIN = '0' and selmmu = '1'
else spi_shift_in when n_DBIN = '0' and selspi = '1' and abus(3 downto 0) = "0000"
-- spi status register
else "000000" & spi_state & spi_cs when n_DBIN = '0' and selspi = '1' and abus(3 downto 0) = "0010"
-- spi debug register
else debug when n_DBIN = '0' and selspi = '1' and abus(3 downto 0) = "0100"
else x"5A" when n_DBIN = '0' and seltest = '1'
else "ZZZZZZZZ";
tms9902_nCE <= '1' when real9902 = True else n_CRU1_internal;
n_CRU1 <= '1' when real9902 = False else n_CRU1_internal;
pnr_tms9902 : tms9902 PORT MAP (
CLK => CLK50M,
nRTS => tms9902_rts_cts, -- out
nDSR => '0', -- in
nCTS => tms9902_rts_cts, -- in, driven by nRTS above
nINT => open, -- out
nCE => tms9902_nCE, -- in
CRUOUT => abus(0), -- in
CRUIN => CRUIN, -- out
CRUCLK => CRUCLK, -- in
XOUT => pnr9902_tx, -- out
RIN => pnr9902_rx, -- in
S => abus(5 downto 1)
);
end toplevel_architecture;
|
lgpl-3.0
|
1478e201d8dcbbadd366b3643df54c8f
| 0.60476 | 2.803571 | false | false | false | false |
krabo0om/pauloBlaze
|
sources/alu.vhd
| 2 | 8,026 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.op_codes.all;
entity ALU is
generic (
debug : boolean := false;
hwbuild : unsigned(7 downto 0) := X"41"
);
port (
clk : in STD_LOGIC;
clk2 : in STD_LOGIC;
reset : in STD_LOGIC;
sleep_int : in STD_LOGIC;
opcode : in unsigned (5 downto 0);
opB : in unsigned (7 downto 0);
preserve_flags : in std_logic;
restore_flags : in std_logic;
carry : out STD_LOGIC;
zero : out STD_LOGIC;
reg_value : out unsigned (7 downto 0);
reg_we : out std_logic;
reg_reg0 : in unsigned (7 downto 0);
reg_reg1 : in unsigned (7 downto 0)
);
end ALU;
architecture Behavioral of ALU is
signal result : unsigned(7 downto 0);
signal res_valid : std_logic; -- result should be written to register
signal inter_flank : std_logic;
signal carry_c : std_logic;
signal carry_o : std_logic;
signal carry_i : std_logic; -- saved during interrupt
signal zero_i : std_logic; -- same
signal zero_c : std_logic;
signal zero_o : std_logic;
signal debug_opA_value : unsigned(7 downto 0);
signal debug_opB_value : unsigned(7 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
reg_value <= result;
reg_we <= not clk2 and res_valid and not sleep_int;
end if;
end process;
carry <= carry_o;
zero <= zero_o;
op : process (reset, opcode, opB, carry_o, zero_o, reg_reg0, reg_reg1, clk2)
variable opB_value : unsigned(7 downto 0);
variable opA_value : unsigned(7 downto 0);
variable result_v : unsigned(8 downto 0);
variable parity_v : std_logic;
variable padding : std_logic;
variable tmp : std_logic;
begin
opA_value := reg_reg0;
if (opcode (0) = '0') then -- LSB 0 = op_x sx, sy
opB_value := reg_reg1;
else -- LSB 1 = op_x sx, kk
opB_value := opB;
end if;
if (debug) then
padding := '0'; --looks better during simulation
debug_opA_value <= opA_value;
debug_opB_value <= opB_value;
else
padding := '-';
end if;
res_valid <= '0';
carry_c <= carry_o;
zero_c <= zero_o;
result_v := (others => padding);
parity_v := '0';
if (reset = '0') then
case opcode is
--register loading
when OP_LOAD_SX_SY | OP_LOAD_SX_KK | OP_LOADRETURN_SX_KK =>
result_v := padding & opB_value;
res_valid <= '1';
when OP_STAR_SX_SY =>
--Logical
when OP_AND_SX_SY | OP_AND_SX_KK =>
result_v := padding & (opA_value and opB_value);
res_valid <= '1';
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
carry_c <= '0';
when OP_OR_SX_SY | OP_OR_SX_KK =>
result_v := padding & (opA_value or opB_value);
res_valid <= '1';
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
carry_c <= '0';
when OP_XOR_SX_SY | OP_XOR_SX_KK =>
result_v := padding & (opA_value xor opB_value);
res_valid <= '1';
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
carry_c <= '0';
--Arithmetic
when OP_ADD_SX_SY | OP_ADD_SX_KK | OP_SUB_SX_SY | OP_SUB_SX_KK |
OP_ADDCY_SX_SY | OP_ADDCY_SX_KK | OP_SUBCY_SX_SY | OP_SUBCY_SX_KK =>
if (opcode(3) = '0') then
result_v := ('0' & opA_value) + ('0' & opB_value) + ("" & (carry_o and opCode(1)));
else
result_v := ('0' & opA_value) - ('0' & opB_value) - ("" & (carry_o and opCode(1)));
end if;
if (result_v(7 downto 0) = "00000000") then
if (opcode = OP_ADDCY_SX_SY or opcode = OP_ADDCY_SX_KK or opcode = OP_SUBCY_SX_SY or opcode = OP_SUBCY_SX_KK) then
zero_c <= zero_o;
else
zero_c <= '1';
end if;
else
zero_c <= '0';
end if;
carry_c <= result_v(8);
res_valid <= '1';
--Test and Compare
when OP_TEST_SX_SY | OP_TEST_SX_KK | OP_TESTCY_SX_SY | OP_TESTCY_SX_KK =>
result_v := (padding & (opA_value and opB_value));
-- opCode(1) == 0 : TEST
-- opCode(1) == 1 : TESTCY
if (result_v(7 downto 0) = "00000000") then
if (opCode(1) = '0') then
zero_c <= '1';
else
zero_c <= zero_o;
end if;
else
zero_c <= '0';
end if;
for i in 0 to 7 loop
parity_v := parity_v xor result_v(i);
end loop;
if (opCode(1) = '0') then
-- TEST
carry_c <= parity_v;
else
-- TESTCY
carry_c <= parity_v xor carry_o;
end if;
when OP_COMPARE_SX_SY | OP_COMPARE_SX_KK | OP_COMPARECY_SX_SY | OP_COMPARECY_SX_KK =>
-- opCode(1) == 0 : COMAPRE
-- opCode(1) == 1 : COMAPRECY
-- mask carry with it
result_v := ('0' & opA_value) - ('0' & opB_value) - ("" & (opCode(1) and carry_o));
if (result_v(7 downto 0) = "00000000") then
if (opCode(1) = '0') then
zero_c <= '1';
else
zero_c <= zero_o;
end if;
else
zero_c <= '0';
end if;
carry_c <= result_v(8);
--Shift and Rotate ... and hwbuild OP_HWBUILD_SX
when OP_SL0_SX =>
if (opB(7) = '1') then -- hw build op
result_v := padding & hwbuild;
res_valid <= '1';
carry_c <= '1';
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
else
-- shift and rotate
case opB(2 downto 0) is
when "110" | "111" =>
tmp := opB(0);
when "010" => -- RL
tmp := opA_value(7);
when "100" => -- RR
tmp := opA_value(0);
when "000" =>
tmp := carry_o;
when others =>
tmp := '0';
end case;
if (opB(3) = '1') then
result_v := opA_value(0) & tmp & opA_value(7 downto 1);
else -- concat the carry value into the result and shift
result_v := opA_value(7) & opA_value(6 downto 0) & tmp;
end if;
carry_c <= result_v(8);
if (result_v(7 downto 0) = "00000000") then
zero_c <= '1';
else
zero_c <= '0';
end if;
res_valid <= '1';
end if;
when others =>
result_v := (others => padding);
end case;
end if;
result <= result_v(7 downto 0);
end process;
flags : process (clk) begin
if (rising_edge(clk)) then
if (reset = '1') then
carry_o <= '0';
zero_o <= '0';
carry_i <= '0';
zero_i <= '0';
else
if (preserve_flags = '1') then
-- preserve flags
carry_i <= carry_o;
zero_i <= zero_o;
end if;
if (restore_flags = '1') then
-- restore flags
carry_o <= carry_i;
zero_o <= zero_i;
elsif (clk2 = '1') then
carry_o <= carry_c;
zero_o <= zero_c;
else
carry_o <= carry_o;
zero_o <= zero_o;
end if;
end if;
end if;
end process flags;
end Behavioral;
|
apache-2.0
|
875cf0b1dbc6cd0cb72a4397f7a465b3
| 0.529404 | 2.939927 | false | false | false | false |
krabo0om/pauloBlaze
|
testbench/tb_pauloB.vhd
| 2 | 4,337 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.math_real.all;
use work.op_codes.all;
ENTITY tb_pauloB IS
END tb_pauloB;
ARCHITECTURE behavior OF tb_pauloB IS
--Inputs
signal clk : std_logic := '0';
signal clk_5ns_delayed : std_logic := '0';
signal clk_5ns_enable : std_logic := '0';
signal reset : std_logic := '0';
signal sleep : std_logic := '0';
signal instruction : std_logic_vector(17 downto 0) := (others => '0');
signal in_port : std_logic_vector(7 downto 0) := (others => '0');
signal in_port_del : std_logic_vector(7 downto 0) := (others => '0');
signal interrupt : std_logic := '0';
--Outputs
signal address : std_logic_vector(11 downto 0);
signal bram_enable : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt_ack : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
type io_data is array (0 to 4) of unsigned(7 downto 0);
signal data : io_data := (x"00", x"AB", x"CD", x"12", x"00");
signal prog_mem_en : std_logic;
signal done : std_logic;
signal sleep_en : std_logic := '0';
signal inter_en : std_logic := '0';
signal reset_en : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.pauloBlaze
generic map (
debug => true,
interrupt_vector => x"300",
hwbuild => x"41",
scratch_pad_memory_size => 64 )
PORT MAP (
-- clk => clk_5ns_delayed,
clk => clk,
reset => reset,
sleep => sleep,
address => address,
instruction => instruction,
bram_enable => bram_enable,
in_port => in_port,
out_port => out_port,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
read_strobe => read_strobe,
interrupt => interrupt,
interrupt_ack => interrupt_ack );
-- end port map
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
sleeping : process begin
if (sleep_en = '1') then
wait for 475 ns;
sleep <= '1';
wait for 137 ns;
sleep <= '0';
end if;
wait;
end process sleeping;
inter_static : process
begin
if (inter_en = '1') then
wait for 499 ns;
interrupt <= '1';
wait until interrupt_ack = '1';
interrupt <= '0';
end if;
wait;
end process inter_static;
prog_mem : entity work.code_loader
Port map (
address => address,
instruction => instruction,
enable => bram_enable,
done => done,
rdl => open,
clk => clk);
reset_proc: process
begin
reset <= '1';
wait for clk_period*10;
wait until done = '1';
wait until clk = '1';
reset <= '0';
if (reset_en = '1') then
wait for 465 ns;
reset <= '1';
wait for 86 ns;
reset <= '0';
end if;
wait;
end process;
process begin
wait for 20 ns;
in_port <= in_port_del;
end process;
data_in_proc : process (port_id) begin
case (port_id) is
when x"05" =>
in_port_del <= x"F3";
when others =>
in_port_del <= port_id;
end case;
end process data_in_proc;
END;
|
apache-2.0
|
b67a03d4f60b6da00aa8f83d11bd9f00
| 0.602029 | 3.181952 | false | false | false | false |
kumasento/zedboard-thesis
|
examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_gpio_0_1/synth/system_axi_gpio_0_1.vhd
| 1 | 9,636 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY system_axi_gpio_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END system_axi_gpio_0_1;
ARCHITECTURE system_axi_gpio_0_1_arch OF system_axi_gpio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_0_1_arch : ARCHITECTURE IS "system_axi_gpio_0_1,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_0_1_arch: ARCHITECTURE IS "system_axi_gpio_0_1,axi_gpio,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=5,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_1_arch;
|
apache-2.0
|
8335a8afb9a10fb33992b56cefa0d349
| 0.687837 | 3.187562 | false | false | false | false |
kumasento/zedboard-thesis
|
examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/synth/system_axi_gpio_0_0.vhd
| 1 | 9,636 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY system_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END system_axi_gpio_0_0;
ARCHITECTURE system_axi_gpio_0_0_arch OF system_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_0_0_arch : ARCHITECTURE IS "system_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "system_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_0_arch;
|
apache-2.0
|
2be59a1906a8426c71b5c77f642ce6a2
| 0.687837 | 3.187562 | false | false | false | false |
corywalker/vhdl_fft
|
ft_controller.vhd
| 3 | 9,158 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ft_controller is
generic (
N : positive := 16;
-- We have 4096 words in the RAM
--ADDRWIDTH : positive := 12;
ADDRWIDTH : positive := 10; -- 512 words on input, 512 on output
-- DELAY:
-- Time to wait in between capture sessions
-- This will be irrelevant once we have output SPI
-- INT_EXT_SEL:
-- '0' for determ_adc, '1' for external.
SIZE : positive := 512;
SIZELOG : positive := 9;
DELAY : positive := 10000;
INT_EXT_SEL: std_logic := '1';
SPI_2X_CLK_DIV: positive := 40;
DA_RESET_DELAY: positive := 10000
);
port(
CLK1: in std_logic;
adc_conv: out std_logic;
adc_sck: out std_logic;
adc_miso: in std_logic;
start_i: in std_logic; -- high when arduino is reading data
busy_o: out std_logic; -- high when performing fft
sck_i: in std_logic; -- to arduino
miso_o: out std_logic; -- to arduino
Led : out std_logic_vector(7 downto 0) := "10001000";
rst : in std_logic
);
end ft_controller;
architecture Behavioral of ft_controller is
COMPONENT xfft_v7_1
PORT (
clk : IN STD_LOGIC;
start : IN STD_LOGIC;
unload : IN STD_LOGIC;
xn_re : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
xn_im : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
fwd_inv : IN STD_LOGIC;
fwd_inv_we : IN STD_LOGIC;
scale_sch : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
scale_sch_we : IN STD_LOGIC;
rfd : OUT STD_LOGIC;
xn_index : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
busy : OUT STD_LOGIC;
edone : OUT STD_LOGIC;
done : OUT STD_LOGIC;
dv : OUT STD_LOGIC;
xk_index : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
xk_re : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xk_im : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
type state_type is (idle, cc_write, fft_read, wait_for_valid, fft_write, oi_read);
signal curr_state, next_state : state_type := idle;
signal start, unload, wnr : std_logic := '0';
signal xn_re, xn_im : std_logic_vector(7 downto 0) := (others => '0');
signal rfd, fftbusy, edone, done, dv : std_logic := '0';
signal xn_index : std_logic_vector(8 downto 0) := (others => '0');
signal xk_re, xk_im : std_logic_vector(7 downto 0) := (others => '0');
signal xk_index : std_logic_vector(8 downto 0) := (others => '0');
signal fft_en : std_logic;
signal cc_out : std_logic_vector(N-1 downto 0);
signal oi_in : std_logic_vector(N-1 downto 0);
signal cc_start: std_logic := '1';
signal addr_rst: std_logic := '1';
signal cc_busy: std_logic;
signal br_wea : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal br_addra : STD_LOGIC_VECTOR(ADDRWIDTH-1 DOWNTO 0);
signal oi_addr_o : STD_LOGIC_VECTOR(ADDRWIDTH-1 DOWNTO 0);
signal theaddr : STD_LOGIC_VECTOR(ADDRWIDTH-1 DOWNTO 0);
signal br_dina : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
signal br_douta : STD_LOGIC_VECTOR(N-1 DOWNTO 0);
begin
cc1: entity work.cap_controller
generic map (
N => N,
SIZE => SIZE,
SIZELOG => SIZELOG,
ADDRWIDTH => ADDRWIDTH,
INT_EXT_SEL => INT_EXT_SEL,
SPI_2X_CLK_DIV => SPI_2X_CLK_DIV,
DA_RESET_DELAY => DA_RESET_DELAY
)
port map (
CLK1 => CLK1,
start => start_i,
busy => cc_busy,
wea => br_wea,
addr => br_addra,
dout => cc_out,
adc_conv => adc_conv,
adc_sck => adc_sck,
adc_miso => adc_miso,
rst => rst
);
br1 : RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Output value upon SSR assertion
WRITE_MODE => "WRITE_FIRST") -- WRITE_FIRST, READ_FIRST or NO_CHANGE
port map (
DO => br_douta, -- 16-bit Data Output
DOP => open, -- 2-bit parity Output
ADDR => theaddr, -- 10-bit Address Input
CLK => CLK1, -- Clock
DI => br_dina, -- 16-bit Data Input
DIP => (others => '0'), -- 2-bit parity Input
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => wnr -- Write Enable Input
);
fft_block : xfft_v7_1
PORT MAP (
clk => CLK1,
start => start,
unload => unload,
xn_re => xn_re,
xn_im => xn_im,
fwd_inv => '1',
fwd_inv_we => '1',
scale_sch => "000000000000110110",
scale_sch_we => '1',
rfd => rfd,
xn_index => xn_index,
busy => fftbusy,
edone => edone,
done => done,
dv => dv,
xk_index => xk_index,
xk_re => xk_re,
xk_im => xk_im
);
oi1: entity work.outbuf_interp
generic map (
N => N,
ADDRWIDTH => ADDRWIDTH
)
port map (
CLK1 => CLK1,
spi_sck_i => sck_i,
addr_rst => addr_rst,
spi_miso_o => miso_o,
din => oi_in,
addr => oi_addr_o
);
addr_rst <= cc_busy;
curr_logic : process (CLK1, rst)
begin
if rising_edge(CLK1) then
if rst = '1' then
curr_state <= idle;
else
curr_state <= next_state;
end if;
end if;
end process;
next_logic : process (CLK1, curr_state)
variable index : integer := 0;
variable mbase : integer := 512;
begin
if rising_edge(CLK1) then
Led <= br_douta(14 downto 7);
case curr_state is
when idle =>
if cc_busy = '1' then
next_state <= cc_write;
end if;
when cc_write =>
busy_o <= '1';
wnr <= '1';
br_dina <= cc_out;
theaddr <= br_addra;
start <= '0';
index := 0;
if cc_busy = '0' then
next_state <= fft_read;
end if;
when fft_read =>
busy_o <= '1';
wnr <= '0';
theaddr <= std_logic_vector(to_unsigned(index, theaddr'length));
xn_re <= br_douta(15 downto 8);
xn_im <= br_douta(7 downto 0);
start <= '1';
index := index + 1;
if done = '1' then
start <= '0';
index := 0;
next_state <= wait_for_valid;
end if;
when wait_for_valid =>
unload <= '1';
start <= '0';
if dv = '1' then
unload <= '0';
next_state <= fft_write;
end if;
when fft_write =>
busy_o <= '1';
wnr <= '1';
start <= '0';
index := mbase + to_integer(unsigned(xk_index));
br_dina <= xk_re & xk_im;
theaddr <= std_logic_vector(to_unsigned(index, theaddr'length));
if dv = '0' then
busy_o <= '0';
unload <= '0';
index := 0;
next_state <= oi_read;
end if;
when oi_read =>
busy_o <= '0';
wnr <= '0';
start <= '0';
theaddr <= std_logic_vector(to_unsigned(mbase + to_integer(unsigned(oi_addr_o)), theaddr'length));
oi_in <= br_douta;
if cc_busy = '1' then
next_state <= cc_write;
end if;
end case;
end if;
end process;
end Behavioral;
|
mit
|
19c04b657595fb29b3fd7ef8b0322235
| 0.415156 | 4.311676 | false | false | false | false |
FearlessJojo/COPproject
|
project/MEMMUX.vhd
| 1 | 1,619 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:38:55 11/21/2016
-- Design Name:
-- Module Name: MEMMUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEMMUX is
Port ( ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
DataOUT : in STD_LOGIC_VECTOR (15 downto 0);
ACCMEM : in STD_LOGIC;
MEMOUT : out STD_LOGIC_VECTOR (15 downto 0);
IMOUT: in STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2:in STD_LOGIC);
end MEMMUX;
architecture Behavioral of MEMMUX is
begin
process (ALUOUT, DataOUT, ACCMEM,MEM_RAM2,IMOUT)
begin
case ACCMEM is
when '0' => MEMOUT <= ALUOUT;
when '1' =>
if (MEM_RAM2 = '1')then
MEMOUT <= IMOUT;
else
MEMOUT <= DataOUT;
end if;
when others => MEMOUT <= "0000000000000000";
end case;
end process;
end Behavioral;
|
mit
|
038faadc0b69a8ad4254266123b26d04
| 0.569487 | 3.613839 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/alu_tb.vhd
| 1 | 2,454 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY alu_tb IS
END alu_tb;
ARCHITECTURE behav of alu_tb IS
COMPONENT alu IS
PORT(
input_a : in STD_LOGIC_VECTOR (31 downto 0);
input_b : in STD_LOGIC_VECTOR (31 downto 0);
SEL : in STD_LOGIC_VECTOR (4 downto 0);
out_alu : out STD_LOGIC_VECTOR(31 downto 0)
);
END COMPONENT;
SIGNAL clock: STD_LOGIC := '0';
CONSTANT clock_period : time := 1 ns;
SIGNAL input_a : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL input_b : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL sel : STD_LOGIC_VECTOR(4 downto 0);
SIGNAL out_alu : STD_LOGIC_VECTOR (31 downto 0);
BEGIN
alutest : alu
PORT MAP(
input_a => input_a,
input_b => input_b,
SEL => sel,
out_alu => out_alu
);
clock_process : PROCESS
BEGIN
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
END PROCESS;
test_process : PROCESS
BEGIN
wait for clock_period;
-- ADD
input_a <= "00000000000000000000000000000000";
input_b <= "00000000000000000000000000000001";
sel <= "00000";
wait for clock_period;
--SUBTRACT
input_a <= "00000000000000000000000000000001";
input_b <= "00000000000000000000000000000001";
sel <= "00001";
wait for clock_period;
--SLL
input_a <= "00000000000000000000000000000010";
input_b <= "00000000000000000000000100000000";
sel <= "10001";
wait for clock_period;
--MUL1
input_a <= "00000000000000000000000000000100";
input_b <= "00000000000000000000001000000000";
sel <= "00011";
wait for clock_period;
--MFHI
sel <= "01110";
wait for clock_period;
--MFLO
sel <= "01111";
wait for clock_period;
--MUL2
input_a <= "10000000000000000000000000000000";
input_b <= "00000000010000000000000000000000";
sel <= "00011";
wait for clock_period;
--MFHI
sel <= "01110";
wait for clock_period;
--MFLO
sel <= "01111";
wait for clock_period;
--DIV1
input_a <= "00000000000000000000000000001000";
input_b <= "00000000000000000000000000000010";
sel <= "00100";
wait for clock_period;
--MFHI
sel <= "01110";
wait for clock_period;
--MFLO
sel <= "01111";
wait for clock_period;
--DIV2
input_a <= "00000000000000000000000000001000";
input_a <= "00000000000000000000000000000011";
sel <= "00100";
wait for clock_period;
--MFHI
sel <= "01110";
wait for clock_period;
--MFLO
sel <= "01111";
wait for clock_period;
WAIT;
END PROCESS;
END behav;
|
gpl-3.0
|
00669a3121b00fee3a6db6a68683b629
| 0.663407 | 3.195313 | false | false | false | false |
corywalker/vhdl_fft
|
determ_adc.vhd
| 3 | 3,567 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------
entity determ_adc is
generic (
N : positive := 16;
DA_RESET_DELAY: positive
);
port(
CLK1, spi_sck_i, conv_i: in std_logic;
spi_miso_o: out std_logic
);
end determ_adc;
---------------------------------------------------
architecture Behavioral of determ_adc is
type state_type is (s0,s1,s2,s3,s4); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.
signal di_i: std_logic_vector (N-1 downto 0) := "0000000000000000";
signal di_req_o: std_logic;
signal wren_i: std_logic := '0';
signal spi_ssel_i: std_logic := '1';
signal cnt1_clear: std_logic;
signal cnt1_Q: unsigned (31 downto 0);
signal cnt1_Q_v: std_logic_vector (31 downto 0);
signal slower_spi_clock: std_logic := '0';
signal s_read_state: unsigned (3 downto 0) := "0000";
signal next_s_read_state: unsigned (3 downto 0) := "0010";
begin
ss1: entity work.spi_slave
generic map (N => N)
port map (
clk_i => slower_spi_clock,
spi_sck_i => spi_sck_i,
spi_ssel_i => spi_ssel_i,
di_i => di_i,
di_req_o => di_req_o,
wren_i => wren_i,
spi_miso_o => spi_miso_o
);
cnt1: entity work.counter
generic map (n => 32)
port map (
clock => CLK1,
clear => cnt1_clear,
count => '1',
Q => cnt1_Q_v
);
process(CLK1)
begin
s_read_state <= next_s_read_state;
if rising_edge(CLK1) then
slower_spi_clock <= not slower_spi_clock;
end if;
end process;
process(s_read_state, CLK1)
variable currcount: unsigned (3 downto 0) := "0000";
begin
if(cnt1_Q = DA_RESET_DELAY) then
currcount := "0000";
next_s_read_state <= "0001";
spi_ssel_i <= '1';
elsif rising_edge(CLK1) then
case s_read_state is
when "0000" =>
if di_req_o = '1' then
next_s_read_state <= "0001";
end if;
when "0001" =>
next_s_read_state <= "0010";
di_i <= "0" & std_logic_vector(currcount) & "00000000" & "111";
when "0010" =>
next_s_read_state <= "0011";
currcount := currcount + 1;
-- We toggle ssel like this because it resets the position
-- if we change our mind about di_i.
spi_ssel_i <= '0';
when "0011" =>
next_s_read_state <= "0100";
when "0100" =>
next_s_read_state <= "0101";
when "0101" =>
next_s_read_state <= "0110";
wren_i <= '1';
when "0110" =>
next_s_read_state <= "0111";
when "0111" =>
next_s_read_state <= "1000";
when "1000" =>
next_s_read_state <= "0000";
wren_i <= '0';
when others =>
next_s_read_state <= "0000";
end case;
end if;
end process;
cnt1_clear <= di_req_o;
cnt1_Q <= unsigned(cnt1_Q_v);
end Behavioral;
|
mit
|
049843eac5fb79fc7d1432b321c62ff4
| 0.445753 | 3.770613 | false | false | false | false |
FearlessJojo/COPproject
|
project/EXE_MEM.vhd
| 1 | 2,346 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: EXE_MEM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EXE_MEM is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
EXE_ALUOUT : in STD_LOGIC_VECTOR (15 downto 0);
EXE_Rd : in STD_LOGIC_VECTOR (3 downto 0);
EXE_AccMEM : in STD_LOGIC;
EXE_memWE : in STD_LOGIC;
EXE_regWE : in STD_LOGIC;
EXE_DataIN : in STD_LOGIC_VECTOR (15 downto 0);
MEM_ALUOUT : out STD_LOGIC_VECTOR (15 downto 0);
MEM_Rd : out STD_LOGIC_VECTOR (3 downto 0);
MEM_AccMEM : out STD_LOGIC;
MEM_memWE : out STD_LOGIC;
MEM_regWE : out STD_LOGIC;
MEM_DataIN : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC
);
end EXE_MEM;
architecture Behavioral of EXE_MEM is
begin
process(clk, rst)
begin
if (rst = '0') then
MEM_AccMEM <= '0';
MEM_memWE <= '0';
MEM_regWE <= '0';
else
if (clk'event and clk = '1') then
if (enable = '1')and(MEM_RAM2 = '0') then
MEM_ALUOUT <= EXE_ALUOUT;
MEM_Rd <= EXE_Rd;
MEM_AccMEM <= EXE_AccMEM;
MEM_memWE <= EXE_memWE;
MEM_regWE <= EXE_regWE;
MEM_DataIN <= EXE_DataIN;
else
if (MEM_RAM2 = '1') then
MEM_AccMEM <= '0';
MEM_memWE <= '0';
MEM_regWE <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
4d3c520cb1e4025732d5ae52b01404d8
| 0.52728 | 3.581679 | false | false | false | false |
krabo0om/pauloBlaze
|
sources/op_codes.vhd
| 2 | 5,423 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package op_codes is
constant OP_LOAD_SX_SY : unsigned(5 downto 0) := "000000";
constant OP_LOAD_SX_KK : unsigned(5 downto 0) := "000001";
constant OP_STAR_SX_SY : unsigned(5 downto 0) := "010110";
constant OP_AND_SX_SY : unsigned(5 downto 0) := "000010";
constant OP_AND_SX_KK : unsigned(5 downto 0) := "000011";
constant OP_OR_SX_SY : unsigned(5 downto 0) := "000100";
constant OP_OR_SX_KK : unsigned(5 downto 0) := "000101";
constant OP_XOR_SX_SY : unsigned(5 downto 0) := "000110";
constant OP_XOR_SX_KK : unsigned(5 downto 0) := "000111";
constant OP_ADD_SX_SY : unsigned(5 downto 0) := "010000";
constant OP_ADD_SX_KK : unsigned(5 downto 0) := "010001";
constant OP_ADDCY_SX_SY : unsigned(5 downto 0) := "010010";
constant OP_ADDCY_SX_KK : unsigned(5 downto 0) := "010011";
constant OP_SUB_SX_SY : unsigned(5 downto 0) := "011000";
constant OP_SUB_SX_KK : unsigned(5 downto 0) := "011001";
constant OP_SUBCY_SX_SY : unsigned(5 downto 0) := "011010";
constant OP_SUBCY_SX_KK : unsigned(5 downto 0) := "011011";
constant OP_TEST_SX_SY : unsigned(5 downto 0) := "001100";
constant OP_TEST_SX_KK : unsigned(5 downto 0) := "001101";
constant OP_TESTCY_SX_SY : unsigned(5 downto 0) := "001110";
constant OP_TESTCY_SX_KK : unsigned(5 downto 0) := "001111";
constant OP_COMPARE_SX_SY : unsigned(5 downto 0) := "011100";
constant OP_COMPARE_SX_KK : unsigned(5 downto 0) := "011101";
constant OP_COMPARECY_SX_SY : unsigned(5 downto 0) := "011110";
constant OP_COMPARECY_SX_KK : unsigned(5 downto 0) := "011111";
constant OP_SL0_SX : unsigned(5 downto 0) := "010100";
constant OP_SL1_SX : unsigned(5 downto 0) := "010100";
constant OP_SLX_SX : unsigned(5 downto 0) := "010100";
constant OP_SLA_SX : unsigned(5 downto 0) := "010100";
constant OP_RL_SX : unsigned(5 downto 0) := "010100";
constant OP_SR0_SX : unsigned(5 downto 0) := "010100";
constant OP_SR1_SX : unsigned(5 downto 0) := "010100";
constant OP_SRX_SX : unsigned(5 downto 0) := "010100";
constant OP_SRA_SX : unsigned(5 downto 0) := "010100";
constant OP_RR_SX : unsigned(5 downto 0) := "010100";
constant OP_REGBANK_A : unsigned(5 downto 0) := "110111";
constant OP_REGBANK_B : unsigned(5 downto 0) := "110111";
constant OP_INPUT_SX_SY : unsigned(5 downto 0) := "001000";
constant OP_INPUT_SX_PP : unsigned(5 downto 0) := "001001";
constant OP_OUTPUT_SX_SY : unsigned(5 downto 0) := "101100";
constant OP_OUTPUT_SX_PP : unsigned(5 downto 0) := "101101";
constant OP_OUTPUTK_KK_P : unsigned(5 downto 0) := "101011";
constant OP_STORE_SX_SY : unsigned(5 downto 0) := "101110";
constant OP_STORE_SX_SS : unsigned(5 downto 0) := "101111";
constant OP_FETCH_SX_SY : unsigned(5 downto 0) := "001010";
constant OP_FETCH_SX_SS : unsigned(5 downto 0) := "001011";
constant OP_DISABLE_INTERRUPT : unsigned(5 downto 0) := "101000";
constant OP_ENABLE_INTERRUPT : unsigned(5 downto 0) := "101000";
constant OP_RETURNI_DISABLE : unsigned(5 downto 0) := "101001";
constant OP_RETURNI_ENABLE : unsigned(5 downto 0) := "101001";
constant OP_JUMP_AAA : unsigned(5 downto 0) := "100010";
constant OP_JUMP_Z_AAA : unsigned(5 downto 0) := "110010";
constant OP_JUMP_NZ_AAA : unsigned(5 downto 0) := "110110";
constant OP_JUMP_C_AAA : unsigned(5 downto 0) := "111010";
constant OP_JUMP_NC_AAA : unsigned(5 downto 0) := "111110";
constant OP_JUMP_SX_SY : unsigned(5 downto 0) := "100110";
constant OP_CALL_AAA : unsigned(5 downto 0) := "100000";
constant OP_CALL_Z_AAA : unsigned(5 downto 0) := "110000";
constant OP_CALL_NZ_AAA : unsigned(5 downto 0) := "110100";
constant OP_CALL_C_AAA : unsigned(5 downto 0) := "111000";
constant OP_CALL_NC_AAA : unsigned(5 downto 0) := "111100";
constant OP_CALL_SX_SY : unsigned(5 downto 0) := "100100";
constant OP_RETURN : unsigned(5 downto 0) := "100101";
constant OP_RETURN_Z : unsigned(5 downto 0) := "110001";
constant OP_RETURN_NZ : unsigned(5 downto 0) := "110101";
constant OP_RETURN_C : unsigned(5 downto 0) := "111001";
constant OP_RETURN_NC : unsigned(5 downto 0) := "111101";
constant OP_LOADRETURN_SX_KK : unsigned(5 downto 0) := "100001";
constant OP_HWBUILD_SX : unsigned(5 downto 0) := "010100";
end op_codes;
package body op_codes is
end op_codes;
|
apache-2.0
|
c401c67ef74a66827ca003967f42efc0
| 0.645584 | 3.184381 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/instructionMemory.vhd
| 1 | 2,292 |
--Adapted from Example 12-15 of Quartus Design and Synthesis handbook
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY instructionMemory IS
GENERIC(
-- might need to change it
ram_size : INTEGER := 1024;
mem_delay : time := 1 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC;
memread: IN STD_LOGIC;
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END instructionMemory;
ARCHITECTURE rtl OF instructionMemory IS
TYPE MEM IS ARRAY(ram_size-1 downto 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg: INTEGER RANGE 0 to ram_size-1;
SIGNAL write_waitreq_reg: STD_LOGIC := '1';
SIGNAL read_waitreq_reg: STD_LOGIC := '1';
BEGIN
--This is the main section of the SRAM model
mem_process: PROCESS (clock)
FILE f : text;
variable row : line;
variable rowData : std_logic_vector(31 downto 0);
variable rowCounter : integer:=0;
BEGIN
--This is a cheap trick to initialize the SRAM in simulation
IF(now < 1 ps)THEN
file_open(f,"program.txt.",READ_MODE);
while (not endfile(f)) loop
readline(f,row);
read(row,rowData);
ram_block(rowCounter) <= rowData;
rowCounter := rowCounter + 1;
end loop;
end if;
file_close(f);
--This is the actual synthesizable SRAM block
IF (clock'event AND clock = '1') THEN
IF (memwrite = '1') THEN
ram_block(address) <= writedata;
END IF;
read_address_reg <= address;
END IF;
END PROCESS;
readdata <= ram_block(read_address_reg);
--The waitrequest signal is used to vary response time in simulation
--Read and write should never happen at the same time.
waitreq_w_proc: PROCESS (memwrite)
BEGIN
IF(memwrite'event AND memwrite = '1')THEN
write_waitreq_reg <= '0' after mem_delay, '1' after mem_delay + clock_period;
END IF;
END PROCESS;
waitreq_r_proc: PROCESS (memread)
BEGIN
IF(memread'event AND memread = '1')THEN
read_waitreq_reg <= '0' after mem_delay, '1' after mem_delay + clock_period;
END IF;
END PROCESS;
waitrequest <= write_waitreq_reg and read_waitreq_reg;
END rtl;
|
gpl-3.0
|
605d5e864f89862e4ba0b24e3fc35121
| 0.693717 | 3.097297 | false | false | false | false |
FearlessJojo/COPproject
|
project/ID_EXE.vhd
| 1 | 2,583 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: ID_EXE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ID_EXE is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
bubble : in STD_LOGIC;
ID_ALUIN1 : in STD_LOGIC_VECTOR (15 downto 0);
ID_ALUIN2 : in STD_LOGIC_VECTOR (15 downto 0);
ID_OP : in STD_LOGIC_VECTOR (3 downto 0);
ID_Rd : in STD_LOGIC_VECTOR (3 downto 0);
ID_AccMEM : in STD_LOGIC;
ID_memWE : in STD_LOGIC;
ID_regWE : in STD_LOGIC;
ID_DataIN : in STD_LOGIC_VECTOR (15 downto 0);
EXE_ALUIN1 : out STD_LOGIC_VECTOR (15 downto 0);
EXE_ALUIN2 : out STD_LOGIC_VECTOR (15 downto 0);
EXE_OP : out STD_LOGIC_VECTOR (3 downto 0);
EXE_Rd : out STD_LOGIC_VECTOR (3 downto 0);
EXE_AccMEM : out STD_LOGIC;
EXE_memWE : out STD_LOGIC;
EXE_regWE : out STD_LOGIC;
EXE_DataIN : out STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2 : in STD_LOGIC
);
end ID_EXE;
architecture Behavioral of ID_EXE is
begin
process(clk, rst)
begin
if (rst = '0') then
EXE_AccMEM <= '0';
EXE_memWE <= '0';
EXE_regWE <= '0';
else
if (clk'event and clk = '1') then
if (enable = '1')and(MEM_RAM2 = '0') then
EXE_ALUIN1 <= ID_ALUIN1;
EXE_ALUIN2 <= ID_ALUIN2;
EXE_OP <= ID_OP;
EXE_Rd <= ID_Rd;
EXE_AccMEM <= ID_AccMEM;
EXE_memWE <= ID_memWE;
EXE_regWE <= ID_regWE;
EXE_DataIN <= ID_DataIN;
else
if (bubble = '1')and(MEM_RAM2 = '0') then
EXE_AccMEM <= '0';
EXE_memWE <= '0';
EXE_regWE <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
6cf2ce46b33521a6cbc1d6405053b7d6
| 0.541618 | 3.307298 | false | false | false | false |
gustavowl/ProjetoOAC
|
Multiplicador64Bit.vhd
| 1 | 18,822 |
-----------------------------------------------------------------------
-----------------------------DESLOCADOR--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador is
port (
a: in std_logic_vector(63 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end deslocador;
architecture deslocador of deslocador is
begin
c <= a(63 downto 0) when desl = '0' else
'0' & a(63 downto 1) when lado = '0' else
a(62 downto 0) & '0';
cout <= a(62) when lado = '1' and desl = '1' else '0';
end deslocador;
-----------------------------------------------------------------------
--------------------------------MUX A----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1A is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end Mux8x1A;
architecture Mux8x1A of Mux8x1A is
component deslocador
port (
a: in std_logic_vector(63 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end component;
signal temp: std_logic_vector (63 downto 0);
signal tdesl, tz: std_logic;
begin
--seleciona o valor de saída baseado na escolha de entrada XYZ
--as primeiras condições são para operações em lógica booleana
--receberá o valor de A caso seja feita alguma operação algébrica
--ou deslocamento de bits
temp <= a and b when x = '0' and y = '1' and z = '0' else
a nor b when x = '0' and y = '1' and z = '1' else
a or b when x = '1' and y = '0' and z = '0' else a;
--só irá efetuar deslocamento de bits caso xyz = 101 ou 110
tdesl <= '1' when x = '1' and ( ( y = '0' and z = '1') or ( y = '1' and z = '0' ) ) else '0';
--tz armazena o lado para qual será efetuado o deslocamento
tz <= z;
desloc: deslocador port map (temp, tdesl, tz, c, cout);
end Mux8x1A;
-----------------------------------------------------------------------
--------------------------------MUX B----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1B is
port (
a: in std_logic_vector(63 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(63 downto 0)
);
end Mux8x1B;
architecture Mux8x1B of Mux8x1B is
begin
c <= "0000000000000000000000000000000000000000000000000000000000000000" when (x = '1' or y = '1') else
a when z = '0' else not a;
end Mux8x1B;
-----------------------------------------------------------------------
--------------------------------MUX C----------------------------------
---------------------------comparador----------------------------------
--Identifica se está fazendo subtração para CIN p/ conversão em complemento de 2
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1C is
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end Mux8x1C;
architecture Mux8x1C of Mux8x1C is
begin
c <= '1' when (x = '0' and y = '0' and z = '1') else '0';-- or
-- (x = '1' and y = '1' and z = '0') else '0';
end Mux8x1C;
-----------------------------------------------------------------------
---------------------------COMPONENTE LÓGICO---------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity CompLog is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector(63 downto 0);
ib: out std_logic_vector(63 downto 0);
Cin: out std_logic; --p/ conversão em complemento de 2
Cout: out std_logic --p/ identificar overflow na multiplicação
);
end CompLog;
architecture CompLog of CompLog is
component Mux8x1A
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end component;
component Mux8x1B
port (
a: in std_logic_vector(63 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(63 downto 0)
);
end component;
component Mux8x1C
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end component;
begin
mux8x1a0: Mux8x1A port map (a, b, x, y, z, ia, Cout);
-- ia <= "01001001";
mux8x1b0: Mux8x1B port map (b, x, y, z, ib);
mux8x1c0: Mux8x1C port map (x, y, z, Cin);
end CompLog;
-----------------------------------------------------------------------
--------------------------SOMADOR 1 BIT--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador1bit is
port (
a: in std_logic;
b: in std_logic;
cin: in std_logic;
s: out std_logic;
cout: out std_logic
);
end somador1bit;
architecture somador1bit of somador1bit is
begin
cout <= (cin and a) or (cin and b) or (a and b);
s <= (not cin and not a and b) or (not cin and a and not b)
or (cin and not a and not b) or (cin and a and b);
end somador1bit;
-----------------------------------------------------------------------
--------------------------SOMADOR 16 BITS-------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador16bits is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
cin: in std_logic;
s: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end somador16bits;
architecture somador16bits of somador16bits is
component somador1bit
port (
a, b, cin: in std_logic;
s, cout: out std_logic
);
end component;
signal ta, tb, ts: std_logic_vector(63 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16,
c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31,
c32, c33, c34, c35, c36, c37, c38, c39, c40, c41, c42, c43, c44, c45, c46, c47, c48,
c49, c50, c51, c52, c53, c54, c55, c56, c57, c58, c59, c60, c61, c62, c63: std_logic;
begin
ta <= a;
tb <= b;
s8b0: somador1bit port map (a(0), b(0), cin, ts(0), c0);
s8v1: somador1bit port map (a(1), b(1), c0, ts(1), c1);
s8v2: somador1bit port map (a(2), b(2), c1, ts(2), c2);
s8v3: somador1bit port map (a(3), b(3), c2, ts(3), c3);
s8v4: somador1bit port map (a(4), b(4), c3, ts(4), c4);
s8v5: somador1bit port map (a(5), b(5), c4, ts(5), c5);
s8v6: somador1bit port map (a(6), b(6), c5, ts(6), c6);
s8v7: somador1bit port map (a(7), b(7), c6, ts(7), c7);
s8b8: somador1bit port map (a(8), b(8), c7, ts(8), c8);
s8v9: somador1bit port map (a(9), b(9), c8, ts(9), c9);
s8v10: somador1bit port map (a(10), b(10), c9, ts(10), c10);
s8v11: somador1bit port map (a(11), b(11), c10, ts(11), c11);
s8v12: somador1bit port map (a(12), b(12), c11, ts(12), c12);
s8v13: somador1bit port map (a(13), b(13), c12, ts(13), c13);
s8v14: somador1bit port map (a(14), b(14), c13, ts(14), c14);
s8v15: somador1bit port map (a(15), b(15), c14, ts(15), c15);
s8v16: somador1bit port map (a(16), b(16), c15, ts(16), c16);
s8v17: somador1bit port map (a(17), b(17), c16, ts(17), c17);
s8v18: somador1bit port map (a(18), b(18), c17, ts(18), c18);
s8v19: somador1bit port map (a(19), b(19), c18, ts(19), c19);
s8v20: somador1bit port map (a(20), b(20), c19, ts(20), c20);
s8v21: somador1bit port map (a(21), b(21), c20, ts(21), c21);
s8v22: somador1bit port map (a(22), b(22), c21, ts(22), c22);
s8v23: somador1bit port map (a(23), b(23), c22, ts(23), c23);
s8v24: somador1bit port map (a(24), b(24), c23, ts(24), c24);
s8v25: somador1bit port map (a(25), b(25), c24, ts(25), c25);
s8v26: somador1bit port map (a(26), b(26), c25, ts(26), c26);
s8v27: somador1bit port map (a(27), b(27), c26, ts(27), c27);
s8v28: somador1bit port map (a(28), b(28), c27, ts(28), c28);
s8v29: somador1bit port map (a(29), b(29), c28, ts(29), c29);
s8v30: somador1bit port map (a(30), b(30), c29, ts(30), c30);
s8v31: somador1bit port map (a(31), b(31), c30, ts(31), c31);
s8v32: somador1bit port map (a(32), b(32), c31, ts(32), c32);
s8v33: somador1bit port map (a(33), b(33), c32, ts(33), c33);
s8v34: somador1bit port map (a(34), b(34), c33, ts(34), c34);
s8v35: somador1bit port map (a(35), b(35), c34, ts(35), c35);
s8v36: somador1bit port map (a(36), b(36), c35, ts(36), c36);
s8v37: somador1bit port map (a(37), b(37), c36, ts(37), c37);
s8v38: somador1bit port map (a(38), b(38), c37, ts(38), c38);
s8v39: somador1bit port map (a(39), b(39), c38, ts(39), c39);
s8v40: somador1bit port map (a(40), b(40), c39, ts(40), c40);
s8v41: somador1bit port map (a(41), b(41), c40, ts(41), c41);
s8v42: somador1bit port map (a(42), b(42), c41, ts(42), c42);
s8v43: somador1bit port map (a(43), b(43), c42, ts(43), c43);
s8v44: somador1bit port map (a(44), b(44), c43, ts(44), c44);
s8v45: somador1bit port map (a(45), b(45), c44, ts(45), c45);
s8v46: somador1bit port map (a(46), b(46), c45, ts(46), c46);
s8v47: somador1bit port map (a(47), b(47), c46, ts(47), c47);
s8v48: somador1bit port map (a(48), b(48), c47, ts(48), c48);
s8v49: somador1bit port map (a(49), b(49), c48, ts(49), c49);
s8v50: somador1bit port map (a(50), b(50), c49, ts(50), c50);
s8v51: somador1bit port map (a(51), b(51), c50, ts(51), c51);
s8v52: somador1bit port map (a(52), b(52), c51, ts(52), c52);
s8v53: somador1bit port map (a(53), b(53), c52, ts(53), c53);
s8v54: somador1bit port map (a(54), b(54), c53, ts(54), c54);
s8v55: somador1bit port map (a(55), b(55), c54, ts(55), c55);
s8v56: somador1bit port map (a(56), b(56), c55, ts(56), c56);
s8v57: somador1bit port map (a(57), b(57), c56, ts(57), c57);
s8v58: somador1bit port map (a(58), b(58), c57, ts(58), c58);
s8v59: somador1bit port map (a(59), b(59), c58, ts(59), c59);
s8v60: somador1bit port map (a(60), b(60), c59, ts(60), c60);
s8v61: somador1bit port map (a(61), b(61), c60, ts(61), c61);
s8v62: somador1bit port map (a(62), b(62), c61, ts(62), c62);
s8v63: somador1bit port map (a(63), b(63), c62, ts(63), c63);
--verifica overflow e underflow
cout <= (not a(63) and not b(63) and ts(63)) or (a(63) and b(63) and not ts(63));
s <= ts;
end somador16bits;
-----------------------------------------------------------------------
-----------------------------ULA-PO------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_po is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(63 downto 0);
couterro: out std_logic
);
end ula_po;
architecture ula_po of ula_po is
component CompLog
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector (63 downto 0);
ib: out std_logic_vector(63 downto 0);
Cin: out std_logic;
Cout: out std_logic
);
end component;
component somador16bits
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
cin: in std_logic;
s: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end component;
signal ia, ib: std_logic_vector(63 downto 0);
signal cin, cout, cout2: std_logic;
begin
complog0: CompLog port map (a, b, x, y, z, ia, ib, cin, cout);
somador8b0: somador16bits port map (ia, ib, cin, s, cout2);
couterro <= cout or cout2;
end ula_po;
-----------------------------------------------------------------------
-----------------------------ULA-PC------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_pc IS
port ( clk, do_op : in std_logic;
done, state: out std_logic
);
end ula_pc;
architecture ula_pc of ula_pc is
constant STDOINGOP: std_logic := '0';
constant STOPDONE: std_logic := '1';
signal st: std_logic;
begin
--espera um ciclo de clock para ter certeza que as operações
--se estabilizaram
PROCESS (clk)
BEGIN
if (clk'event and clk = '1') then
case st is
when STOPDONE =>
if (do_op = '1') then
st <= STDOINGOP;
end if;
when others =>
st <= STOPDONE;
end case;
end if;
end process;
done <= '1' when st = STOPDONE else '0';
state <= st;
end ula_pc;
-----------------------------------------------------------------------
-------------------------------ULA-------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z, clk, do_op: in std_logic;
s: out std_logic_vector(63 downto 0);
couterro, done, state: out std_logic
);
end ula;
architecture ula of ula is
component ula_po
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(63 downto 0);
couterro: out std_logic
);
end component;
component ula_pc
port (
clk, do_op : in std_logic;
done, state: out std_logic
);
end component;
begin
ulapo: ula_po port map (a, b, x, y, z, s, couterro);
ulapc: ula_pc port map (clk, do_op, done, state);
end ula;
-----------------------------------------------------------------------
-----------------------------DESLOCADOR--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador32 is
port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end deslocador32;
architecture deslocador32 of deslocador32 is
begin
c <= a(31 downto 0) when desl = '0' else
'0' & a(31 downto 1) when lado = '0' else
a(30 downto 0) & '0';
cout <= a(30) when lado = '1' and desl = '1' else '0';
end deslocador32;
--REGISTRADOR 32 BIT
library ieee;
use ieee.std_logic_1164.all;
entity reg_paraleload32 is
port ( i: in std_logic_vector (31 downto 0);
clk, ld, rst: in std_logic; --load: 1: escrita, 0: leitura
q: out std_logic_vector (31 downto 0)
);
end;
architecture reg_paraleload32 of reg_paraleload32 is
begin
q <= "00000000000000000000000000000000" when (clk'event and clk = '1' and rst = '1') else
i when ( clk'event and clk = '1' and ld = '1' );
end reg_paraleload32;
--REGISTRADOR 64 BIT
library ieee;
use ieee.std_logic_1164.all;
entity reg_paraleload64 is
port ( i: in std_logic_vector (63 downto 0);
clk, ld, rst: in std_logic; --load: 1: escrita, 0: leitura
q: out std_logic_vector (63 downto 0)
);
end;
architecture reg_paraleload64 of reg_paraleload64 is
begin
q <= "0000000000000000000000000000000000000000000000000000000000000000" when (clk'event and clk = '1' and rst = '1') else
i when ( clk'event and clk = '1' and ld = '1' );
end reg_paraleload64;
--MULTIPLICADOR
library ieee;
use ieee.std_logic_1164.all;
entity mult64 is
port ( multiplicando: in std_logic_vector (63 downto 0);
multiplicador: in std_logic_vector (31 downto 0);
clk, start: in std_logic; --load: 1: escrita, 0: leitura
produto: out std_logic_vector (63 downto 0);
done: out std_logic
);
end;
architecture mult64 of mult64 is
component reg_paraleload32 port (
i: in std_logic_vector (31 downto 0);
clk, ld, rst: in std_logic; --load: 1: escrita, 0: leitura
q: out std_logic_vector (31 downto 0)
);
end component;
component reg_paraleload64 port (
i: in std_logic_vector (63 downto 0);
clk, ld, rst: in std_logic; --load: 1: escrita, 0: leitura
q: out std_logic_vector (63 downto 0)
);
end component;
component deslocador32 port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
component deslocador port (
a: in std_logic_vector(63 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end component;
component ula port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z, clk, do_op: in std_logic;
s: out std_logic_vector(63 downto 0);
couterro, done, state: out std_logic
);
end component;
signal st, reset, over, cout, cout2, sum, cout3, useless1, useless2, resetaux, overwriteresult: std_logic; --st[0: reset | 1: doing operation]
signal desl64in, desl64out, ulain, ulaout, reg64m_in, ulain_mult: std_logic_vector(63 downto 0);
signal desl32in, desl32out, reg32_in: std_logic_vector(31 downto 0);
begin
PROCESS (clk)
BEGIN
if (clk'event and clk = '1') then
if (start = '1' and not(st = '1')) then
st <= '1';
--over <= '0';
elsif (st = '1' and over = '1') then
st <= '0';
end if;
end if;
END PROCESS;
reset <= '1' when st = '0' or st = 'U' else '0';
reg64m_in <= multiplicando when reset = '1' else desl64out;
reg64m: reg_paraleload64 port map (reg64m_in, clk, '1', '0', desl64in);
desl64: deslocador port map(desl64in, '1', '1', desl64out, cout);
resetaux <= '1' when reset = '1' or ulaout = "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" else '0';
overwriteresult <= '1' when over = '0' else '0';
reg64p: reg_paraleload64 port map (ulaout, clk, overwriteresult, resetaux, ulain);
reg32_in <= multiplicador when reset = '1' else desl32out;
--reg32_in <= "01110111011101110111011101110111" when reset = '0' else multiplicador;
reg32: reg_paraleload32 port map(reg32_in, clk, '1', '0', desl32in);
desl32: deslocador32 port map (desl32in, '1', '0', desl32out, cout2);
sum <= desl32in(0);
ulain_mult <= desl64in when sum = '1' else "0000000000000000000000000000000000000000000000000000000000000000";
alu: ula port map (ulain_mult, ulain, '0', '0', '0', clk, sum, ulaout, cout3, useless1, useless2);
over <= '1' when desl32in = "00000000000000000000000000000000" else '0';
produto <= ulaout;
--produto <= "00000000000000000000000000000000" & desl32in;
done <= over;
--done <= sum;
--done <= '1' when desl32in = "00000000000000000000000000000000" else '0';
end mult64;
|
gpl-2.0
|
e56aeefe1b64439e3f35649bff17e22e
| 0.576444 | 2.775432 | false | false | false | false |
krabo0om/pauloBlaze
|
sources/pauloBlaze.vhd
| 2 | 8,794 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity pauloBlaze is
generic (
debug : boolean := false;
hwbuild : unsigned(7 downto 0) := X"00";
interrupt_vector : unsigned(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64;
stack_depth : positive := 30
);
port (
-- control
clk : in std_logic;
reset : in std_logic;
sleep : in std_logic;
-- instruction memory
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
-- i/o ports
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
-- interrupts
interrupt : in std_logic;
interrupt_ack : out std_logic
);
end pauloBlaze;
architecture Behavioral of pauloBlaze is
signal clk2 : std_logic := '1'; -- high during 2nd clk cycle
-- used for converting from slv to my internal unsigned
signal address_u : unsigned(11 downto 0);
signal instruction_u : unsigned(17 downto 0);
signal in_port_u : unsigned(7 downto 0);
signal out_port_u : unsigned(7 downto 0);
signal port_id_u : unsigned(7 downto 0);
-- signals alu in
signal opcode : unsigned(5 downto 0);
signal opA : unsigned(3 downto 0);
signal opB : unsigned(7 downto 0);
-- signals alu out
signal carry : STD_LOGIC;
signal zero : STD_LOGIC;
-- signals pc in
signal rst_req : STD_LOGIC;
signal ret : STD_LOGIC;
signal call : STD_LOGIC;
signal jump : STD_LOGIC;
signal jmp_addr : unsigned (11 downto 0);
-- signals decoder
signal reset_int : std_logic;
signal reset_bram_en : std_logic;
signal io_op_in : std_logic;
signal io_op_out : std_logic;
signal io_op_out_pp : std_logic;
signal io_kk_en : std_logic;
signal io_kk_port : unsigned (3 downto 0);
signal io_kk_data : unsigned (7 downto 0);
signal spm_addr_ss : unsigned (7 downto 0);
signal spm_ss : std_logic;
signal spm_we : std_logic;
signal spm_rd : std_logic;
signal inter_j : std_logic;
signal sleep_int : std_logic;
signal bram_pause : std_logic;
signal clk2_reset : std_logic;
signal preserve_flags : std_logic;
signal restore_flags : std_logic;
-- general register file signals
signal reg_select : std_logic;
signal reg_star : std_logic;
signal reg_reg0 : unsigned (7 downto 0);
signal reg_reg1 : unsigned (7 downto 0);
signal reg_address : unsigned (7 downto 0);
signal reg_value : unsigned (7 downto 0);
signal reg_we : std_logic;
-- signals register file from alu
signal reg_value_a : unsigned (7 downto 0);
signal reg_we_a : std_logic;
-- signals register file from io
signal reg_value_io : unsigned (7 downto 0);
signal reg_we_io : std_logic;
begin
bram_enable <= clk2 and not bram_pause when reset_int = '0' else reset_bram_en;
-- in case of a reset there is a state where reset_bram_en will be high for one clk cycle, just before
-- the internal reset will be deasserted
clk2_gen : process (clk) begin
if (rising_edge(clk)) then
if (clk2_reset = '1') then
clk2 <= '1';
else
clk2 <= not clk2;
end if;
end if;
end process clk2_gen;
address <= std_logic_vector(address_u);
instruction_u <= unsigned(instruction);
in_port_u <= unsigned(in_port);
out_port <= std_logic_vector(out_port_u);
port_id <= std_logic_vector(port_id_u);
pc : entity work.program_counter
generic map(
interrupt_vector => interrupt_vector,
stack_depth => stack_depth
)
port map(
clk => clk,
reset => reset_int,
rst_req => rst_req,
bram_pause => bram_pause,
call => call,
ret => ret,
inter_j => inter_j,
jump => jump,
jmp_addr => jmp_addr,
address => address_u
);
-- alu
alu_inst : entity work.ALU
generic map(
hwbuild => hwbuild,
debug => debug
)
port map(
clk => clk,
clk2 => clk2,
reset => reset_int,
sleep_int => sleep_int,
opcode => opcode,
-- opA => opA,
opB => opB,
preserve_flags => preserve_flags,
restore_flags => restore_flags,
carry => carry,
zero => zero,
reg_value => reg_value_a,
reg_we => reg_we_a,
reg_reg0 => reg_reg0,
reg_reg1 => reg_reg1
);
decoder_inst : entity work.decoder
generic map(
interrupt_vector => interrupt_vector
)
port map(
clk => clk,
clk2 => clk2,
reset => reset,
reset_int => reset_int,
reset_bram_en => reset_bram_en,
rst_req => rst_req,
sleep => sleep,
sleep_int => sleep_int,
bram_pause => bram_pause,
clk2_reset => clk2_reset,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
instruction => instruction_u,
opcode => opcode,
opA => opA,
opB => opB,
reg0 => reg_reg0,
reg1 => reg_reg1,
carry => carry,
zero => zero,
call => call,
ret => ret,
inter_j => inter_j,
preserve_flags => preserve_flags,
restore_flags => restore_flags,
jmp_addr => jmp_addr,
jump => jump,
io_op_in => io_op_in,
io_op_out => io_op_out,
io_op_out_pp => io_op_out_pp,
io_kk_en => io_kk_en,
io_kk_port => io_kk_port,
io_kk_data => io_kk_data,
reg_address => reg_address,
reg_select => reg_select,
reg_star => reg_star,
spm_addr_ss => spm_addr_ss,
spm_ss => spm_ss,
spm_we => spm_we,
spm_rd => spm_rd
);
reg_value <= reg_value_io when (io_op_in or io_op_out) = '1' else reg_value_a when reg_we_a = '1' else reg_reg0;
reg_we <= reg_we_io or reg_we_a or reg_star or spm_rd;
register_file : entity work.reg_file
generic map(
scratch_pad_memory_size => scratch_pad_memory_size
)
port map(
clk => clk,
reg_address => reg_address,
reg_select => reg_select,
reg_star => reg_star,
value => reg_value,
write_en => reg_we,
reg0 => reg_reg0,
reg1 => reg_reg1,
spm_addr_ss => spm_addr_ss,
spm_ss => spm_ss,
spm_we => spm_we,
spm_rd => spm_rd
);
io_inst : entity work.io_module
port map(
clk => clk,
clk2 => clk2,
reset => reset_int,
reg_value => reg_value_io,
reg_we => reg_we_io,
reg_reg0 => reg_reg0,
reg_reg1 => reg_reg1,
out_data => opB,
io_op_in => io_op_in,
io_op_out => io_op_out,
io_op_out_pp => io_op_out_pp,
io_kk_en => io_kk_en,
io_kk_port => io_kk_port,
io_kk_data => io_kk_data,
-- actual i/o module ports
in_port => in_port_u,
port_id => port_id_u,
out_port => out_port_u,
read_strobe => read_strobe,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe
);
end Behavioral;
|
apache-2.0
|
f7fdef812ce032040f331fcadffe57f3
| 0.538094 | 3.2319 | false | false | false | false |
krabo0om/pauloBlaze
|
sources/decoder.vhd
| 2 | 10,581 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.op_codes.all;
entity decoder is
generic (
interrupt_vector : unsigned(11 downto 0) := X"3FF"
);
Port (
clk : in STD_LOGIC;
clk2 : in STD_LOGIC;
reset : in STD_LOGIC;
reset_int : out STD_LOGIC;
reset_bram_en : out STD_LOGIC;
rst_req : in std_logic;
sleep : in STD_LOGIC;
sleep_int : out STD_LOGIC;
bram_pause : out STD_LOGIC;
clk2_reset : out STD_LOGIC;
interrupt : in STD_LOGIC;
interrupt_ack : out STD_LOGIC;
instruction : in unsigned (17 downto 0);
opCode : out unsigned (5 downto 0);
opA : out unsigned (3 downto 0);
opB : out unsigned (7 downto 0);
reg0 : in unsigned (7 downto 0);
reg1 : in unsigned (7 downto 0);
carry : in STD_LOGIC;
zero : in STD_LOGIC;
call : out STD_LOGIC;
ret : out std_logic;
inter_j : out std_logic;
preserve_flags : out std_logic;
restore_flags : out std_logic;
jump : out STD_LOGIC;
jmp_addr : out unsigned (11 downto 0);
io_op_in : out std_logic;
io_op_out : out std_logic;
io_op_out_pp : out std_logic;
io_kk_en : out std_logic;
io_kk_port : out unsigned (3 downto 0);
io_kk_data : out unsigned (7 downto 0);
reg_address : out unsigned (7 downto 0);
reg_select : out std_logic;
reg_star : out std_logic;
spm_addr_ss : out unsigned (7 downto 0);
spm_ss : out std_logic; -- 0: spm_addr = reg1, 1: spm_addr = spm_addr_ss
spm_we : out std_logic;
spm_rd : out std_logic
);
end decoder;
architecture Behavioral of decoder is
signal clk2_reset_sleep : std_logic;
signal clk2_reset_reset : std_logic;
signal reset_int_o : std_logic;
signal reset_r : std_logic;
signal reg_select_o : std_logic;
signal reg_select_i : std_logic;
signal opCode_o : unsigned (5 downto 0);
signal fetch : std_logic;
signal store : std_logic;
signal inter_en : std_logic;
signal inter_j_o : std_logic;
signal inter_block_regs : std_logic;
signal preserve_flags_o : std_logic;
signal restore_flags_o : std_logic;
signal instr_used : unsigned (17 downto 0);
signal sleep_int_o : std_logic;
signal reg_sel_save : std_logic;
signal sxy_addr : std_logic;
signal bram_pause_sleep : std_logic;
signal bram_pause_reset : std_logic;
type sleep_state_t is (awake, sleeping, dawn, sunrise);
signal sleep_state : sleep_state_t;
type interrupt_state_t is (none, detected, inter_ack, interrupting, int_end);
signal inter_state : interrupt_state_t;
signal inter_state_nxt : interrupt_state_t;
type reset_state_t is (none, detected, finishing, holding, bram_en);
signal reset_state : reset_state_t;
signal reset_state_nxt : reset_state_t;
begin
reset_int <= reset_int_o;
clk2_reset <= clk2_reset_sleep or clk2_reset_reset;
bram_pause <= bram_pause_sleep or bram_pause_reset;
opCode <= opCode_o;
opCode_o <= instr_used(17 downto 12);
opA <= instr_used(11 downto 8);
opB <= instr_used(7 downto 0);
jmp_addr <= instr_used(11 downto 0) when sxy_addr = '0' else reg0(3 downto 0) & reg1;
reg_address <= instr_used(11 downto 4);
reg_select <= reg_select_o;
spm_addr_ss <= instr_used(7 downto 0);
spm_ss <= opCode_o(0);
spm_rd <= fetch;
io_op_out_pp <= instr_used(12); -- constant value (pp) or register as data on the output
io_kk_data <= instr_used(11 downto 4);
io_kk_port <= instr_used(3 downto 0);
sleep_int <= sleep_int_o or inter_block_regs;
inter_j <= inter_j_o;
restore_flags <= restore_flags_o;
decompose : process (instr_used, reset_int_o, zero, carry, opCode_o)
begin
jump <= '0';
sxy_addr <= '0';
call <= '0';
ret <= '0';
io_op_in <= '0';
io_op_out <= '0';
io_kk_en <= '0';
fetch <= '0';
store <= '0';
if (reset_int_o = '0') then
case opCode_o is
when OP_JUMP_AAA =>
jump <= '1';
when OP_JUMP_SX_SY =>
jump <= '1';
sxy_addr <= '1';
when OP_JUMP_Z_AAA | OP_JUMP_NZ_AAA =>
jump <= zero xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> Z; 1 -> NZ
when OP_JUMP_C_AAA | OP_JUMP_NC_AAA =>
jump <= carry xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> C; 1 -> NC
when OP_CALL_AAA =>
call <= '1';
when OP_CALL_SX_SY =>
call <= '1';
sxy_addr <= '1';
when OP_CALL_Z_AAA | OP_CALL_NZ_AAA =>
call <= zero xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> Z; 1 -> NZ
when OP_CALL_C_AAA | OP_CALL_NC_AAA =>
call <= carry xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> C; 1 -> NC
when OP_RETURN | OP_RETURNI_DISABLE | OP_LOADRETURN_SX_KK =>
ret <= '1';
when OP_RETURN_Z | OP_RETURN_NZ =>
ret <= zero xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> Z; 1 -> NZ
when OP_RETURN_C | OP_RETURN_NC =>
ret <= carry xor instr_used(14); -- inst(14) == opCode_o(2): 0 -> C; 1 -> NC
when OP_INPUT_SX_SY | OP_INPUT_SX_PP =>
io_op_in <= '1';
when OP_OUTPUT_SX_SY | OP_OUTPUT_SX_PP =>
io_op_out <= '1';
when OP_OUTPUTK_KK_P =>
io_kk_en <= '1';
when OP_FETCH_SX_SY | OP_FETCH_SX_SS =>
-- spm_rd <= '1';
fetch <= '1';
when OP_STORE_SX_SY | OP_STORE_SX_SS =>
-- spm_we <= '1';
store <= '1';
when others =>
end case;
end if;
end process decompose;
reg_proc : process (clk) begin
if (rising_edge(clk)) then
if (reset_int_o = '1') then
reg_select_o <= '0';
reg_sel_save <= '0';
else
reg_star <= '0';
spm_we <= store and not clk2;
if (preserve_flags_o = '1') then
reg_sel_save <= reg_select_o;
elsif (restore_flags_o = '1') then
reg_select_o <= reg_sel_save;
elsif (opCode_o = OP_REGBANK_A) then
reg_select_o <= instr_used(0);
elsif (opCode_o = OP_STAR_SX_SY) then
reg_select_o <= not reg_select_o;
reg_star <= '1';
end if;
end if;
end if;
end process reg_proc;
inter_en_p : process (clk) begin
if (rising_edge(clk)) then
if (reset_int_o = '1') then
inter_en <= '0';
else
if (opCode_o = OP_ENABLE_INTERRUPT or opCode_o = OP_RETURNI_ENABLE) then
inter_en <= instr_used(0); -- bit 0 contains set/erase
else
inter_en <= inter_en;
end if;
end if;
end if;
end process inter_en_p;
inter_state_com_p : process (inter_state, instruction, interrupt, inter_en, clk2, opCode_o) begin
inter_state_nxt <= inter_state;
instr_used <= instruction;
preserve_flags_o <= '0';
inter_j_o <= '0';
interrupt_ack <= '0';
inter_block_regs <= '0';
restore_flags_o <= '0';
case (inter_state) is
when none =>
if (interrupt = '1') then
inter_state_nxt <= detected;
end if;
when detected =>
if (inter_en = '1' and clk2 = '0') then
inter_block_regs <= '1';
inter_state_nxt <= inter_ack;
end if;
when inter_ack =>
instr_used <= (others => '0');
preserve_flags_o <= '1';
interrupt_ack <= '1';
inter_block_regs <= '1';
inter_j_o <= '1';
inter_state_nxt <= interrupting;
when interrupting =>
if (opCode_o = OP_RETURNI_ENABLE and clk2 = '1') then
inter_state_nxt <= int_end;
restore_flags_o <= '1';
end if;
when int_end =>
inter_state_nxt <= none;
end case;
end process inter_state_com_p;
inter_state_clk_p : process (clk) begin
if (rising_edge(clk)) then
if (reset_int_o = '1') then
inter_state <= none;
else
if (sleep = '0') then
inter_state <= inter_state_nxt;
preserve_flags <= preserve_flags_o;
end if;
end if;
end if;
end process inter_state_clk_p;
sleep_sm : process (clk) begin
if (rising_edge(clk)) then
if (reset_int_o = '1') then
sleep_state <= awake;
bram_pause_sleep <= '0';
sleep_int_o <= '0';
clk2_reset_sleep <= '0';
else
bram_pause_sleep <= '0';
sleep_int_o <= '0';
clk2_reset_sleep <= '0';
case sleep_state is
when awake =>
if (sleep = '1') then
sleep_state <= sleeping;
end if;
when sleeping =>
bram_pause_sleep <= '1';
sleep_int_o <= '1';
if (sleep = '0') then
clk2_reset_sleep <= '1';
sleep_int_o <= '0';
sleep_state <= dawn;
if (clk2 = '1') then
bram_pause_sleep <= '0';
end if;
end if;
when dawn =>
sleep_state <= sunrise;
when sunrise =>
sleep_int_o <= '1';
if (clk2 = '1') then
sleep_int_o <= '0';
sleep_state <= awake;
end if;
end case;
end if;
end if;
end process sleep_sm;
rst_state_com_p : process (reset, rst_req, reset_state) begin
reset_state_nxt <= reset_state;
reset_int_o <= '0';
bram_pause_reset <= '0';
reset_bram_en <= '0';
clk2_reset_reset <= '0';
case (reset_state) is
when none =>
if (reset = '1') then
reset_state_nxt <= detected;
elsif (rst_req = '1') then
reset_state_nxt <= holding;
end if;
when detected =>
bram_pause_reset <= '1';
reset_int_o <= '1';
if (reset = '0') then
reset_state_nxt <= finishing;
end if;
when finishing =>
bram_pause_reset <= '1';
reset_int_o <= '1';
reset_state_nxt <= holding;
when holding =>
bram_pause_reset <= '1';
reset_int_o <= '1';
clk2_reset_reset <= '1';
reset_state_nxt <= bram_en;
when bram_en =>
reset_int_o <= '1';
reset_bram_en <= '1';
reset_state_nxt <= none;
end case;
end process rst_state_com_p;
rst_state_clk_p : process (clk) begin
if (rising_edge(clk)) then
reset_state <= reset_state_nxt;
end if;
end process rst_state_clk_p;
end Behavioral;
|
apache-2.0
|
394ca369d69d99cc11b33199be9f3ea7
| 0.582743 | 2.688945 | false | false | false | false |
universal-ctags/ctags
|
Units/parser-vhdl.r/vhdl-process.d/input-0.vhd
| 2 | 1,493 |
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
-- with modifications.
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer0 is
generic (
abits0 : integer := 5;
dbits0 : integer := 64
);
port (
i_clk0 : in std_logic;
i_raddr0 : in std_logic_vector(abits0-1 downto 0);
o_rdata0 : out std_logic_vector(dbits0-1 downto 0);
i_we0 : in std_logic;
i_waddr0 : in std_logic_vector(abits0-1 downto 0);
i_wdata0 : in std_logic_vector(dbits0-1 downto 0)
);
end;
architecture arch_StackTraceBuffer0 of StackTraceBuffer0 is
type ram_type0 is array ((2**abits0)-1 downto 0) of std_logic_vector (dbits0-1 downto 0);
signal stackbuf0 : ram_type0;
signal raddr0 : std_logic_vector(abits0-1 downto 0);
begin
-- registers:
process(i_clk0) begin
if rising_edge(i_clk0) then
if i_we0 = '1' then
stackbuf0(conv_integer(i_waddr0)) <= i_wdata0;
end if;
raddr0 <= i_raddr0;
end if;
end process;
o_rdata0 <= stackbuf0(conv_integer(raddr0));
end;
|
gpl-2.0
|
e24e4514abc0ce7c4ae83ddcb706803f
| 0.593436 | 3.424312 | false | false | false | false |
corywalker/vhdl_fft
|
spi_slave_tb.vhd
| 3 | 3,954 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:23:24 09/17/2014
-- Design Name:
-- Module Name: C:/Users/John/Downloads/spi_master_slave/trunk/spi_clean/spi_slave_tb.vhd
-- Project Name: spi_clean
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_slave
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY spi_slave_tb IS
END spi_slave_tb;
ARCHITECTURE behavior OF spi_slave_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT spi_slave
PORT(
clk_i : IN std_logic;
spi_ssel_i : IN std_logic;
spi_sck_i : IN std_logic;
spi_mosi_i : IN std_logic;
spi_miso_o : OUT std_logic;
di_req_o : OUT std_logic;
di_i : IN std_logic_vector(31 downto 0);
wren_i : IN std_logic;
wr_ack_o : OUT std_logic;
do_valid_o : OUT std_logic;
do_o : OUT std_logic_vector(31 downto 0);
do_transfer_o : OUT std_logic;
wren_o : OUT std_logic;
rx_bit_next_o : OUT std_logic;
state_dbg_o : OUT std_logic_vector(3 downto 0);
sh_reg_dbg_o : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk_i : std_logic := '0';
signal spi_ssel_i : std_logic := '0';
signal spi_sck_i : std_logic := '0';
signal spi_mosi_i : std_logic := '0';
signal di_i : std_logic_vector(31 downto 0) := (others => '0');
signal wren_i : std_logic := '0';
--Outputs
signal spi_miso_o : std_logic;
signal di_req_o : std_logic;
signal wr_ack_o : std_logic;
signal do_valid_o : std_logic;
signal do_o : std_logic_vector(31 downto 0);
signal do_transfer_o : std_logic;
signal wren_o : std_logic;
signal rx_bit_next_o : std_logic;
signal state_dbg_o : std_logic_vector(3 downto 0);
signal sh_reg_dbg_o : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_i_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: spi_slave PORT MAP (
clk_i => clk_i,
spi_ssel_i => spi_ssel_i,
spi_sck_i => spi_sck_i,
spi_mosi_i => spi_mosi_i,
spi_miso_o => spi_miso_o,
di_req_o => di_req_o,
di_i => di_i,
wren_i => wren_i,
wr_ack_o => wr_ack_o,
do_valid_o => do_valid_o,
do_o => do_o,
do_transfer_o => do_transfer_o,
wren_o => wren_o,
rx_bit_next_o => rx_bit_next_o,
state_dbg_o => state_dbg_o,
sh_reg_dbg_o => sh_reg_dbg_o
);
-- Clock process definitions
clk_i_process :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
spi_sck_i_process :process
begin
spi_sck_i <= '0';
wait for clk_i_period;
spi_sck_i <= '1';
wait for clk_i_period;
end process;
di_i <= X"1234ABCD";
wren_i <= '1';
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_i_period*10;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
fa48c191839512a0666359e53077f7f4
| 0.564492 | 3.235679 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/register_file.vhd
| 1 | 2,351 |
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY register_file IS
GENERIC(
register_size: INTEGER := 32 --MIPS register size is 32 bit
);
PORT(
-- ************** Do we need a standard enable input ? *****************
clock: IN STD_LOGIC;
rs: IN STD_LOGIC_VECTOR (4 downto 0); -- first source register
rt: IN STD_LOGIC_VECTOR (4 downto 0); -- second source register
write_enable: IN STD_LOGIC; -- signals that rd_data may be written into rd **********Unsure if neccessary*************
rd: IN STD_LOGIC_VECTOR (4 downto 0); -- destination register
rd_data: IN STD_LOGIC_VECTOR (31 downto 0); -- destination register data
writeToText: IN STD_LOGIC := '0';
ra_data: OUT STD_LOGIC_VECTOR (31 downto 0); -- data of register a
rb_data: OUT STD_LOGIC_VECTOR (31 downto 0) -- data of register b
);
END register_file;
ARCHITECTURE Behav OF register_file IS
TYPE registers IS ARRAY (0 to 31) OF STD_LOGIC_VECTOR(31 downto 0); -- MIPS has 32 registers. Size of data is 32 bits. => 32x32bits
SIGNAL register_store: registers := (OTHERS=> "00000000000000000000000000000000"); -- initialize all registers to 32 bits of 0.
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event) THEN
ra_data <= register_store(to_integer(unsigned(rs))); -- data of ra is now the data associated with rs's register index in the register_store
rb_data <= register_store(to_integer(unsigned(rt)));
IF (write_enable = '1') THEN -- if write_enable is high, we have permission to update the data of rd
IF (to_integer(unsigned(rd)) = 0) THEN -- if we are trying to write to R0, then deny the write
NULL;
ELSE
register_store(to_integer(unsigned(rd))) <= rd_data; -- access the appropriate register in the register_store, and assign it rd_data
END IF;
END IF;
END IF;
END PROCESS;
process(writeToText)
file register_file : text open write_mode is "register_file.txt";
variable outLine : line;
variable rowLine : integer := 0;
variable test : std_logic_vector(31 downto 0) := "00100000000000010000000000000001";
begin
if writeToText = '1' then
while (rowLine < 32) loop
write(outLine, register_store(rowLine));
writeline(register_file, outLine);
rowLine := rowLine + 1;
end loop;
end if;
end process;
END Behav;
|
gpl-3.0
|
129a98ec27a42c9cce730a2014cebc19
| 0.68439 | 3.392496 | false | false | false | false |
krabo0om/pauloBlaze
|
sources/regFile.vhd
| 2 | 3,984 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.op_codes.all;
entity reg_file is
generic (
debug : boolean := false;
scratch_pad_memory_size : integer := 64
);
port (
clk : in std_logic;
value : in unsigned (7 downto 0);
write_en : in std_logic;
reg0 : out unsigned (7 downto 0);
reg1 : out unsigned (7 downto 0);
reg_address : in unsigned (7 downto 0);
reg_select : in std_logic;
reg_star : in std_logic;
spm_addr_ss : in unsigned (7 downto 0);
spm_ss : in std_logic; -- 0: spm_addr = reg1, 1: spm_addr = spm_addr_ss
spm_we : in std_logic;
spm_rd : in std_logic
);
end reg_file;
architecture Behavioral of reg_file is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type reg_file_t is array (31 downto 0) of unsigned(7 downto 0);
signal reg : reg_file_t := (others=>(others=>'0'));
type scratchpad_t is array(integer range <>) of unsigned(7 downto 0);
signal scratchpad : scratchpad_t((scratch_pad_memory_size-1) downto 0) := (others=>(others=>'0'));
constant spm_addr_width : integer := log2ceil(scratch_pad_memory_size); -- address failsafes into a truncated one
signal spm_addr : unsigned ( spm_addr_width-1 downto 0);
signal spm_read : unsigned (7 downto 0);
signal reg0_buf : unsigned ( 7 downto 0);
signal reg0_o : unsigned ( 7 downto 0);
signal reg1_buf : unsigned ( 7 downto 0);
signal reg1_o : unsigned ( 7 downto 0);
signal reg_wr_data : unsigned ( 7 downto 0);
begin
reg0 <= reg0_o;
reg1 <= reg1_o;
reg_wr_data <= spm_read when spm_rd = '1' else value when reg_star = '0' else reg1_buf;
spm_addr <= spm_addr_ss(spm_addr_width -1 downto 0) when spm_ss = '1' else reg1_buf(spm_addr_width -1 downto 0);
spm_read <= scratchpad(to_integer(spm_addr));
reg0_o <= reg(to_integer(reg_select & reg_address(7 downto 4)));
reg1_o <= reg(to_integer(reg_select & reg_address(3 downto 0)));
write_reg : process (clk) begin
if rising_edge(clk) then
if (write_en = '1') then
reg(to_integer(reg_select & reg_address(7 downto 4))) <= reg_wr_data;
end if;
end if;
end process write_reg;
write_spm : process (clk) begin
if rising_edge(clk) then
if (spm_we = '1') then
scratchpad(to_integer(spm_addr)) <= reg0_buf;
end if;
end if;
end process write_spm;
buf_reg0_p : process (clk) begin
if rising_edge(clk) then
reg0_buf <= reg0_o;
reg1_buf <= reg1_o;
end if;
end process buf_reg0_p;
end Behavioral;
|
apache-2.0
|
e1fa3c6e128e6f9d70401446dc4c0c1e
| 0.605673 | 3.137008 | false | false | false | false |
gustavowl/ProjetoOAC
|
Mult32bit/Multiplicador32Bit_tb.vhd
| 1 | 488 |
library ieee;
use ieee.std_logic_1164.all;
entity mult32_tb is
end mult32_tb;
architecture mult32_tb of mult32_tb is
signal sclk, sstart, sdone: std_logic;
signal res: std_logic_vector(63 downto 0);
signal mtplcnd, mtplcdr: std_logic_vector(31 downto 0);
begin
vector: entity work.mult32
port map (
multiplicando => mtplcnd,
multiplicador => mtplcdr,
clk => sclk,
start => sstart,
produto => res,
done => sdone
);
process
begin
wait;
end process;
end mult32_tb;
|
gpl-2.0
|
1546bd6daff1b09cee36dbbfb7201b5f
| 0.704918 | 2.820809 | false | false | false | false |
FearlessJojo/COPproject
|
project/RAM_UART.vhd
| 1 | 3,881 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAM_UART is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ACCMEM : in STD_LOGIC;
MEM_WE : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (15 downto 0);
data : in STD_LOGIC_VECTOR (15 downto 0);
data_out : out STD_LOGIC_VECTOR (15 downto 0);
Ram1Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram1Data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1OE : out STD_LOGIC;
Ram1WE : out STD_LOGIC;
Ram1EN : out STD_LOGIC;
wrn : out STD_LOGIC;
rdn : out STD_LOGIC;
data_ready : in STD_LOGIC;
tbre : in STD_LOGIC;
tsre : in STD_LOGIC;
MEM_RAM2 :in STD_LOGIC );
end RAM_UART;
architecture Behavioral of RAM_UART is
signal Ram_Uart_ctrl : STD_LOGIC;
signal state_uart : integer range 0 to 2;
signal state : integer range 0 to 1 := 0;
begin
process(CLK, RST, ACCMEM, MEM_WE, addr, data, data_ready, tbre, tsre)
begin
if (addr = "1011111100000000") or (addr = "1011111100000001") then
Ram_Uart_ctrl <= '0';
else
Ram_Uart_ctrl <= '1';
end if;
if (CLK'EVENT) and (CLK = '0') then
if (MEM_WE = '1') and (ACCMEM = '0') and (Ram_Uart_ctrl = '1')and(MEM_RAM2 = '0') then --RAM write
case state is
when 0 => wrn <= '1';
rdn <= '1';
Ram1EN <= '0';
Ram1OE <= '1';
Ram1WE <= '1';
RAM1Addr(17 downto 16) <= "00";
RAM1Addr(15 downto 0) <= addr;
RAM1Data <= data;
state <= 1;
when 1 => Ram1WE <= '0';
state <= 0;
when others => null;
end case;
end if;
if (MEM_WE = '0') and (ACCMEM = '1') and (Ram_Uart_ctrl = '1')and(MEM_RAM2 = '0') then --RAM read
case state is
when 0 => wrn <= '1';
rdn <= '1';
Ram1EN <= '0';
Ram1OE <= '0';
Ram1WE <= '1';
RAM1Data <= (others => 'Z');
RAM1Addr(17 downto 16) <= "00";
RAM1Addr(15 downto 0) <= addr;
state <= 1;
when 1 =>
state <= 0;
when others => null;
end case;
end if;
if (MEM_WE = '0') and (ACCMEM = '0')then
rdn <= '1';
end if;
if (MEM_WE = '0') and (ACCMEM = '1') and (Ram_Uart_ctrl = '0') then --UART read
if (addr /= "1011111100000001") then
case state is
when 0 => rdn <= '0';
RAM1EN <= '1';
RAM1OE <= '1';
RAM1WE <= '1';
RAM1Data <= (others => 'Z');
state <= 1;
when 1 => rdn <= '1';
state <= 0;
when others => null;
end case;
else
rdn <= '1';
end if;
end if;
if (MEM_WE = '1') and (ACCMEM = '0') and (Ram_Uart_ctrl = '0') then --UART write
if (state_uart = 0) then
wrn <= '1';
rdn <= '1';
Ram1EN <= '1';
Ram1OE <= '1';
Ram1WE <= '1';
state_uart <= 1;
RAM1Data <= data;
end if;
if (state_uart = 1) then
wrn <= '0';
state_uart <= 2;
end if;
end if;
if (state_uart = 2) then
wrn <= '1';
if (tsre = '1') and (tbre = '1') then
state_uart <= 0;
end if;
end if;
end if;
-- if (MEM_WE = '1') and (ACCMEM = '0') and (state = 1) then
-- wrn <= not CLK;
-- else
-- wrn <= '1';
-- end if;
if (RST = '0') then
Ram1OE <= '0';
Ram1WE <= '0';
Ram1EN <= '0';
state <= 0;
state_uart <= 0;
end if;
end process;
process(Ram1Data,addr,tsre,tbre,data_ready)
begin
if (addr = "1011111100000001") then
data_out(15 downto 2) <= "00000000000000";
if (tsre = '0') or (tbre = '0') then
data_out(0) <= '0';
else
data_out(0) <= '1';
end if;
if (data_ready = '0') then
data_out(1) <= '0';
else
data_out(1) <= '1';
end if;
else
data_out <= Ram1Data;
end if;
end process;
end Behavioral;
|
mit
|
4942ddc2f366a43dbdf2f3a5fc359c8e
| 0.499871 | 2.695139 | false | false | false | false |
krabo0om/pauloBlaze
|
testbench/tb_lockstep.vhd
| 2 | 7,835 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2019 Paul Genssler - Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.math_real.all;
use work.op_codes.all;
ENTITY tb_lockstep IS
END tb_lockstep;
ARCHITECTURE behavior OF tb_lockstep IS
--Inputs
signal clk : std_logic := '0';
signal clk_5ns_delayed : std_logic := '0';
signal clk_5ns_enable : std_logic := '0';
signal reset : std_logic := '0';
signal sleep : std_logic := '0';
signal instruction : std_logic_vector(17 downto 0) := (others => '0');
signal in_port : std_logic_vector(7 downto 0) := (others => '0');
signal in_port_del : std_logic_vector(7 downto 0) := (others => '0');
signal interrupt : std_logic := '0';
--Outputs
signal address : std_logic_vector(11 downto 0);
signal bram_enable : std_logic;
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt_ack : std_logic;
-- PicoBlaze Outputs
signal pico_address : std_logic_vector(11 downto 0);
signal pico_instruction : std_logic_vector(17 downto 0) := (others => '0');
signal pico_bram_enable : std_logic;
signal pico_out_port : std_logic_vector(7 downto 0);
signal pico_port_id : std_logic_vector(7 downto 0);
signal pico_write_strobe : std_logic;
signal pico_k_write_strobe : std_logic;
signal pico_read_strobe : std_logic;
signal pico_interrupt_ack : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
type io_data is array (0 to 4) of unsigned(7 downto 0);
signal data : io_data := (x"00", x"AB", x"CD", x"12", x"00");
signal prog_mem_en : std_logic;
signal done : std_logic;
signal pico_done : std_logic;
signal sleep_en : std_logic := '1';
signal inter_en : std_logic := '1';
signal reset_en : std_logic := '1';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.pauloBlaze
generic map (
debug => true,
interrupt_vector => x"300",
hwbuild => x"41",
scratch_pad_memory_size => 64 )
PORT MAP (
-- clk => clk_5ns_delayed,
clk => clk,
reset => reset,
sleep => sleep,
address => address,
instruction => instruction,
bram_enable => bram_enable,
in_port => in_port,
out_port => out_port,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
read_strobe => read_strobe,
interrupt => interrupt,
interrupt_ack => interrupt_ack );
-- end port map
picoblaze: entity work.kcpsm6
generic map ( hwbuild => X"41",
interrupt_vector => X"300",
scratch_pad_memory_size => 64)
port map( address => pico_address,
instruction => pico_instruction,
bram_enable => pico_bram_enable,
port_id => pico_port_id,
write_strobe => pico_write_strobe,
k_write_strobe => pico_k_write_strobe,
out_port => pico_out_port,
read_strobe => pico_read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => pico_interrupt_ack,
sleep => sleep,
reset => reset,
clk => clk);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
sleeping : process begin
if (sleep_en = '1') then
wait for 1035 ns;
sleep <= '1';
wait for 1 * clk_period;
sleep <= '0';
wait for 5000 ns;
sleep <= '1';
wait for 7 * clk_period;
sleep <= '0';
end if;
wait;
end process sleeping;
inter_static : process
begin
if (inter_en = '1') then
wait for 490 ns;
interrupt <= '1';
wait for 3 * clk_period;
interrupt <= '0';
wait for 875 ns;
interrupt <= '1';
wait until interrupt_ack = '1';
interrupt <= '0';
end if;
wait;
end process inter_static;
prog_mem : entity work.code_loader
Port map (
address => address,
instruction => instruction,
enable => bram_enable,
done => done,
rdl => open,
clk => clk);
prog_mem_pico : entity work.code_loader
Port map (
address => pico_address,
instruction => pico_instruction,
enable => pico_bram_enable,
done => pico_done,
rdl => open,
clk => clk);
reset_proc: process
begin
reset <= '1';
wait until (done = '1' and pico_done = '1');
wait until clk = '0';
reset <= '0';
if (reset_en = '1') then
wait for 465 ns;
reset <= '1';
wait for 86 ns;
reset <= '0';
end if;
wait for 1337 ns;
wait until rising_edge(clk);
if (reset_en = '1') then
wait for 85 ns;
reset <= '1';
wait for 35 ns;
reset <= '0';
end if;
wait;
end process;
process begin
wait for 20 ns;
in_port <= in_port_del;
end process;
data_in_proc : process (port_id) begin
case (port_id) is
when x"05" =>
in_port_del <= x"F3";
when others =>
in_port_del <= port_id;
end case;
end process data_in_proc;
compare_process: process begin
wait until reset = '0';
loop
wait until rising_edge(clk);
wait until rising_edge(clk);
assert pico_address = address report "address is different" severity error;
assert pico_bram_enable = bram_enable report "bram_enable is different" severity error;
assert pico_write_strobe = write_strobe report "write_strobe is different" severity error;
assert pico_k_write_strobe = k_write_strobe report "k_write_strobe is different" severity error;
if (pico_write_strobe = '1' or write_strobe = '1' or
pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_out_port = out_port report "out_port is different" severity error;
if (pico_k_write_strobe = '1' or k_write_strobe = '1' ) then
assert pico_port_id(3 downto 0) = port_id(3 downto 0) report "port_id is different" severity error;
else
assert pico_port_id = port_id report "port_id is different" severity error;
end if;
end if;
assert pico_read_strobe = read_strobe report "read_strobe is different" severity error;
assert pico_interrupt_ack = interrupt_ack report "interrupt_ack is different" severity error;
end loop;
end process;
END;
|
apache-2.0
|
d3c8311e403f1b567abf07ff44ccdee0
| 0.570645 | 3.575993 | false | false | false | false |
FearlessJojo/COPproject
|
project/PCMUX.vhd
| 1 | 1,537 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:34:57 11/21/2016
-- Design Name:
-- Module Name: PCMUX - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PCMUX is
Port ( NPC : in STD_LOGIC_VECTOR (15 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
adderOUT : in STD_LOGIC_VECTOR (15 downto 0);
PCctrl : in STD_LOGIC_VECTOR (1 downto 0);
PCIN : out STD_LOGIC_VECTOR (15 downto 0));
end PCMUX;
architecture Behavioral of PCMUX is
begin
process(NPC, A, adderOUT, PCctrl)
begin
case PCctrl is
when "00" => PCIN <= NPC;
when "10" | "11" => PCIN <= A;
when "01" => PCIN <= adderOUT;
when others => PCIN <= "0000000000000000";
end case;
end process;
end Behavioral;
|
mit
|
fc03fe2cb7cc0aa64dea7cf0526a9512
| 0.564086 | 3.677033 | false | false | false | false |
kumasento/zedboard-thesis
|
examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/15467f24/hdl/fifo_generator_v12_0.vhd
| 5 | 90,319 |
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`protect end_protected
|
apache-2.0
|
b2b89efdd82bc781810cf8f23b4f51ef
| 0.953111 | 1.837358 | false | false | false | false |
FearlessJojo/COPproject
|
project/Imm.vhd
| 1 | 1,919 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:50:28 11/20/2016
-- Design Name:
-- Module Name: Imm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Imm is
Port ( Immctrl : in STD_LOGIC_VECTOR (3 downto 0);
Inst : in STD_LOGIC_VECTOR (10 downto 0);
Imm : out STD_LOGIC_VECTOR (15 downto 0));
end Imm;
architecture Behavioral of Imm is
begin
process(Immctrl, Inst)
begin
case Immctrl is
when "0001" =>
Imm <= SXT(Inst(7 downto 0), Imm'length);
when "0010" =>
Imm <= SXT(Inst(3 downto 0), Imm'length);
when "0011" =>
Imm <= SXT(Inst(10 downto 0), Imm'length);
when "0100" =>
Imm <= "00000000" & Inst(7 downto 0);
when "0101" =>
Imm <= SXT(Inst(4 downto 0), Imm'length);
when "0110" =>
Imm <= "000000000000" & Inst(3 downto 0);
when "0111" =>
if (Inst(4 downto 2)="000") then
Imm <= "0000000000001000";
else
Imm <= "0000000000000" & Inst(4 downto 2);
end if;
when "1000" =>
Imm <= "0000000000000001";
when others =>
Imm <= "0000000000000000";
end case;
end process;
end Behavioral;
|
mit
|
9b4ffdd8d551ae45b210e7e15541e99c
| 0.557061 | 3.560297 | false | false | false | false |
gustavowl/ProjetoOAC
|
ULA64bit/ula.vhd
| 1 | 13,816 |
-----------------------------------------------------------------------
-----------------------------DESLOCADOR--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador is
port (
a: in std_logic_vector(63 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end deslocador;
architecture deslocador of deslocador is
begin
c <= a(63 downto 0) when desl = '0' else
'0' & a(63 downto 1) when lado = '0' else
a(62 downto 0) & '0';
cout <= a(62) when lado = '1' and desl = '1' else '0';
end deslocador;
-----------------------------------------------------------------------
--------------------------------MUX A----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1A is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end Mux8x1A;
architecture Mux8x1A of Mux8x1A is
component deslocador
port (
a: in std_logic_vector(63 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end component;
signal temp: std_logic_vector (63 downto 0);
signal tdesl, tz: std_logic;
begin
--seleciona o valor de saída baseado na escolha de entrada XYZ
--as primeiras condições são para operações em lógica booleana
--receberá o valor de A caso seja feita alguma operação algébrica
--ou deslocamento de bits
temp <= a and b when x = '0' and y = '1' and z = '0' else
a nor b when x = '0' and y = '1' and z = '1' else
a or b when x = '1' and y = '0' and z = '0' else a;
--só irá efetuar deslocamento de bits caso xyz = 101 ou 110
tdesl <= '1' when x = '1' and ( ( y = '0' and z = '1') or ( y = '1' and z = '0' ) ) else '0';
--tz armazena o lado para qual será efetuado o deslocamento
tz <= z;
desloc: deslocador port map (temp, tdesl, tz, c, cout);
end Mux8x1A;
-----------------------------------------------------------------------
--------------------------------MUX B----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1B is
port (
a: in std_logic_vector(63 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(63 downto 0)
);
end Mux8x1B;
architecture Mux8x1B of Mux8x1B is
begin
c <= "0000000000000000000000000000000000000000000000000000000000000000" when (x = '1' or y = '1') else
a when z = '0' else not a;
end Mux8x1B;
-----------------------------------------------------------------------
--------------------------------MUX C----------------------------------
---------------------------comparador----------------------------------
--Identifica se está fazendo subtração para CIN p/ conversão em complemento de 2
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1C is
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end Mux8x1C;
architecture Mux8x1C of Mux8x1C is
begin
c <= '1' when (x = '0' and y = '0' and z = '1') else '0';-- or
-- (x = '1' and y = '1' and z = '0') else '0';
end Mux8x1C;
-----------------------------------------------------------------------
---------------------------COMPONENTE LÓGICO---------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity CompLog is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector(63 downto 0);
ib: out std_logic_vector(63 downto 0);
Cin: out std_logic; --p/ conversão em complemento de 2
Cout: out std_logic --p/ identificar overflow na multiplicação
);
end CompLog;
architecture CompLog of CompLog is
component Mux8x1A
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end component;
component Mux8x1B
port (
a: in std_logic_vector(63 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(63 downto 0)
);
end component;
component Mux8x1C
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end component;
begin
mux8x1a0: Mux8x1A port map (a, b, x, y, z, ia, Cout);
-- ia <= "01001001";
mux8x1b0: Mux8x1B port map (b, x, y, z, ib);
mux8x1c0: Mux8x1C port map (x, y, z, Cin);
end CompLog;
-----------------------------------------------------------------------
--------------------------SOMADOR 1 BIT--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador1bit is
port (
a: in std_logic;
b: in std_logic;
cin: in std_logic;
s: out std_logic;
cout: out std_logic
);
end somador1bit;
architecture somador1bit of somador1bit is
begin
cout <= (cin and a) or (cin and b) or (a and b);
s <= (not cin and not a and b) or (not cin and a and not b)
or (cin and not a and not b) or (cin and a and b);
end somador1bit;
-----------------------------------------------------------------------
--------------------------SOMADOR 16 BITS-------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador16bits is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
cin: in std_logic;
s: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end somador16bits;
architecture somador16bits of somador16bits is
component somador1bit
port (
a, b, cin: in std_logic;
s, cout: out std_logic
);
end component;
signal ta, tb, ts: std_logic_vector(63 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16,
c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31,
c32, c33, c34, c35, c36, c37, c38, c39, c40, c41, c42, c43, c44, c45, c46, c47, c48,
c49, c50, c51, c52, c53, c54, c55, c56, c57, c58, c59, c60, c61, c62, c63: std_logic;
begin
ta <= a;
tb <= b;
s8b0: somador1bit port map (a(0), b(0), cin, ts(0), c0);
s8v1: somador1bit port map (a(1), b(1), c0, ts(1), c1);
s8v2: somador1bit port map (a(2), b(2), c1, ts(2), c2);
s8v3: somador1bit port map (a(3), b(3), c2, ts(3), c3);
s8v4: somador1bit port map (a(4), b(4), c3, ts(4), c4);
s8v5: somador1bit port map (a(5), b(5), c4, ts(5), c5);
s8v6: somador1bit port map (a(6), b(6), c5, ts(6), c6);
s8v7: somador1bit port map (a(7), b(7), c6, ts(7), c7);
s8b8: somador1bit port map (a(8), b(8), c7, ts(8), c8);
s8v9: somador1bit port map (a(9), b(9), c8, ts(9), c9);
s8v10: somador1bit port map (a(10), b(10), c9, ts(10), c10);
s8v11: somador1bit port map (a(11), b(11), c10, ts(11), c11);
s8v12: somador1bit port map (a(12), b(12), c11, ts(12), c12);
s8v13: somador1bit port map (a(13), b(13), c12, ts(13), c13);
s8v14: somador1bit port map (a(14), b(14), c13, ts(14), c14);
s8v15: somador1bit port map (a(15), b(15), c14, ts(15), c15);
s8v16: somador1bit port map (a(16), b(16), c15, ts(16), c16);
s8v17: somador1bit port map (a(17), b(17), c16, ts(17), c17);
s8v18: somador1bit port map (a(18), b(18), c17, ts(18), c18);
s8v19: somador1bit port map (a(19), b(19), c18, ts(19), c19);
s8v20: somador1bit port map (a(20), b(20), c19, ts(20), c20);
s8v21: somador1bit port map (a(21), b(21), c20, ts(21), c21);
s8v22: somador1bit port map (a(22), b(22), c21, ts(22), c22);
s8v23: somador1bit port map (a(23), b(23), c22, ts(23), c23);
s8v24: somador1bit port map (a(24), b(24), c23, ts(24), c24);
s8v25: somador1bit port map (a(25), b(25), c24, ts(25), c25);
s8v26: somador1bit port map (a(26), b(26), c25, ts(26), c26);
s8v27: somador1bit port map (a(27), b(27), c26, ts(27), c27);
s8v28: somador1bit port map (a(28), b(28), c27, ts(28), c28);
s8v29: somador1bit port map (a(29), b(29), c28, ts(29), c29);
s8v30: somador1bit port map (a(30), b(30), c29, ts(30), c30);
s8v31: somador1bit port map (a(31), b(31), c30, ts(31), c31);
s8v32: somador1bit port map (a(32), b(32), c31, ts(32), c32);
s8v33: somador1bit port map (a(33), b(33), c32, ts(33), c33);
s8v34: somador1bit port map (a(34), b(34), c33, ts(34), c34);
s8v35: somador1bit port map (a(35), b(35), c34, ts(35), c35);
s8v36: somador1bit port map (a(36), b(36), c35, ts(36), c36);
s8v37: somador1bit port map (a(37), b(37), c36, ts(37), c37);
s8v38: somador1bit port map (a(38), b(38), c37, ts(38), c38);
s8v39: somador1bit port map (a(39), b(39), c38, ts(39), c39);
s8v40: somador1bit port map (a(40), b(40), c39, ts(40), c40);
s8v41: somador1bit port map (a(41), b(41), c40, ts(41), c41);
s8v42: somador1bit port map (a(42), b(42), c41, ts(42), c42);
s8v43: somador1bit port map (a(43), b(43), c42, ts(43), c43);
s8v44: somador1bit port map (a(44), b(44), c43, ts(44), c44);
s8v45: somador1bit port map (a(45), b(45), c44, ts(45), c45);
s8v46: somador1bit port map (a(46), b(46), c45, ts(46), c46);
s8v47: somador1bit port map (a(47), b(47), c46, ts(47), c47);
s8v48: somador1bit port map (a(48), b(48), c47, ts(48), c48);
s8v49: somador1bit port map (a(49), b(49), c48, ts(49), c49);
s8v50: somador1bit port map (a(50), b(50), c49, ts(50), c50);
s8v51: somador1bit port map (a(51), b(51), c50, ts(51), c51);
s8v52: somador1bit port map (a(52), b(52), c51, ts(52), c52);
s8v53: somador1bit port map (a(53), b(53), c52, ts(53), c53);
s8v54: somador1bit port map (a(54), b(54), c53, ts(54), c54);
s8v55: somador1bit port map (a(55), b(55), c54, ts(55), c55);
s8v56: somador1bit port map (a(56), b(56), c55, ts(56), c56);
s8v57: somador1bit port map (a(57), b(57), c56, ts(57), c57);
s8v58: somador1bit port map (a(58), b(58), c57, ts(58), c58);
s8v59: somador1bit port map (a(59), b(59), c58, ts(59), c59);
s8v60: somador1bit port map (a(60), b(60), c59, ts(60), c60);
s8v61: somador1bit port map (a(61), b(61), c60, ts(61), c61);
s8v62: somador1bit port map (a(62), b(62), c61, ts(62), c62);
s8v63: somador1bit port map (a(63), b(63), c62, ts(63), c63);
--verifica overflow e underflow
cout <= (not a(63) and not b(63) and ts(63)) or (a(63) and b(63) and not ts(63));
s <= ts;
end somador16bits;
-----------------------------------------------------------------------
-----------------------------ULA-PO------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_po is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(63 downto 0);
couterro: out std_logic
);
end ula_po;
architecture ula_po of ula_po is
component CompLog
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector (63 downto 0);
ib: out std_logic_vector(63 downto 0);
Cin: out std_logic;
Cout: out std_logic
);
end component;
component somador16bits
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
cin: in std_logic;
s: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end component;
signal ia, ib: std_logic_vector(63 downto 0);
signal cin, cout, cout2: std_logic;
begin
complog0: CompLog port map (a, b, x, y, z, ia, ib, cin, cout);
somador8b0: somador16bits port map (ia, ib, cin, s, cout2);
couterro <= cout or cout2;
end ula_po;
-----------------------------------------------------------------------
-----------------------------ULA-PC------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_pc IS
port ( clk, do_op : in std_logic;
done, state: out std_logic
);
end ula_pc;
architecture ula_pc of ula_pc is
constant STDOINGOP: std_logic := '0';
constant STOPDONE: std_logic := '1';
signal st: std_logic;
begin
--espera um ciclo de clock para ter certeza que as operações
--se estabilizaram
PROCESS (clk)
BEGIN
if (clk'event and clk = '1') then
case st is
when STOPDONE =>
if (do_op = '1') then
st <= STDOINGOP;
end if;
when others =>
st <= STOPDONE;
end case;
end if;
end process;
done <= '1' when st = STOPDONE else '0';
state <= st;
end ula_pc;
-----------------------------------------------------------------------
-------------------------------ULA-------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula is
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z, clk, do_op: in std_logic;
s: out std_logic_vector(63 downto 0);
couterro, done, state: out std_logic
);
end ula;
architecture ula of ula is
component ula_po
port (
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(63 downto 0);
couterro: out std_logic
);
end component;
component ula_pc
port (
clk, do_op : in std_logic;
done, state: out std_logic
);
end component;
begin
ulapo: ula_po port map (a, b, x, y, z, s, couterro);
ulapc: ula_pc port map (clk, do_op, done, state);
end ula;
|
gpl-2.0
|
2ae84c3d58081762fb4ed2693533ab15
| 0.547201 | 2.69375 | false | false | false | false |
Speccery/fpga99
|
tms9902.vhd
| 1 | 27,622 |
--
-- TMS9902 component
--
-- Datasheet available at
-- http://ftp.whtech.com/datasheets%20and%20manuals/Datasheets%20-%20TI/TMS9902A.pdf
--
-- This source code is public domain.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tms9902 is
port (
CLK : in std_logic;
nRTS : out std_logic;
nDSR : in std_logic;
nCTS : in std_logic;
nINT : out std_logic;
nCE : in std_logic;
CRUOUT : in std_logic;
CRUIN : out std_logic;
CRUCLK : in std_logic;
XOUT : out std_logic;
RIN : in std_logic;
S : in std_logic_vector(4 downto 0)
);
end;
architecture tms9902_arch of tms9902 is
--
-- CRU / CONTROLLER
--
-- flag register
type cruFLG_type is record
dscenb : std_logic;
timenb : std_logic;
xienb : std_logic;
rienb : std_logic;
brkon : std_logic;
rtson : std_logic;
tstmd : std_logic;
ldctl : std_logic;
ldir : std_logic;
lrdr : std_logic;
lxdr : std_logic;
cruclk : std_logic;
dsch : std_logic;
pdsr : std_logic;
pcts : std_logic;
end record;
signal cruFLG_q, cruFLG_d : cruFLG_type;
-- control register
type ctl_type is record
sbs : std_logic_vector(2 downto 1);
penb : std_logic;
podd : std_logic;
clk4m : std_logic;
rcl : std_logic_vector(1 downto 0);
end record;
signal ctl_q, ctl_d : ctl_type;
-- control signals from CRU controller
signal sig_reset : std_logic; -- device being reset
signal sig_timenb : std_logic; -- timenb being written
signal sig_rienb : std_logic; -- rienb being written
signal sig_ldir : std_logic; -- ldir being reset
--
-- INTERVAL TIMER
--
-- interval register
signal tmr_q, tmr_d : std_logic_vector(7 downto 0) := (others => '1');
-- interval timer counter
signal timctr_q, timctr_d : unsigned(13 downto 0) := (others => '1');
-- control signal from timer counter
signal sig_timctr_iszero : std_logic; -- timer counter is zero
-- interval timer controller
type timFSM_type is record
timelp : std_logic;
timerr : std_logic;
end record;
signal timFSM_q, timFSM_d : timFSM_type;
--
-- TRANSMITTER
--
-- transmit data rate register
signal xdr_q, xdr_d : std_logic_vector(10 downto 0) := (others => '0');
-- transmit half-bit timer counter
signal xhbctr_q, xhbctr_d : unsigned(12 downto 0) := (others => '0');
signal sig_xhbctr_iszero : std_logic;
-- transmit buffer register
signal xbr_q, xbr_d : std_logic_vector(7 downto 0);
signal sig_xbr7 : std_logic;
-- transmit shift register
signal xsr_q, xsr_d : std_logic_vector(7 downto 0);
-- transmit controller
type xmtstat is (IDLE, BREAK, START, BITS, PARITY, STOP);
type xmtFSM_type is record
xbre : std_logic;
xsre : std_logic;
xout : std_logic;
rts : std_logic;
par : std_logic;
bitctr : unsigned(4 downto 0);
state : xmtstat;
end record;
signal xmtFSM_q, xmtFSM_d : xmtFSM_type;
-- control signals from the transmit controller
signal sig_xhb_reset : std_logic;
signal sig_xsr_load : std_logic;
signal sig_xsr_shift : std_logic;
--
-- RECEIVER
--
-- receive data rate register
signal rdr_q, rdr_d : std_logic_vector(10 downto 0) := (others => '0');
-- receive half-bit timer counter
signal rhbctr_q, rhbctr_d : unsigned(12 downto 0) := (others => '0');
signal sig_rhbctr_iszero : std_logic;
-- receive buffer register
signal rbr_q, rbr_d : std_logic_vector(7 downto 0);
-- receive shift register
signal rsr_q, rsr_d : std_logic_vector(7 downto 0);
-- receive controller
type rcvstat is (IDLE, START, START1, BITS, PARITY, STOP);
type rcvFSM_type is record
rbrl : std_logic;
rsbd : std_logic;
rfbd : std_logic;
rover : std_logic;
rper : std_logic;
rfer : std_logic;
par : std_logic;
bitctr : unsigned(4 downto 0);
state : rcvstat;
end record;
signal rcvFSM_q, rcvFSM_d : rcvFSM_type;
-- control signals from the receive controller
signal sig_rhb_reset : std_logic;
signal sig_rbr_load : std_logic;
signal sig_rsr_shift : std_logic;
--
-- MISCELANEOUS
--
signal dscint : std_logic; -- device status change interrupt pending
signal rint : std_logic; -- receive interrupt pending
signal xint : std_logic; -- transmit interrupt pending
signal timint : std_logic; -- timer interrupt pending
signal intr : std_logic; -- any interrupt pending
signal flag : std_logic; -- any register select bit or brkon set
signal rcverr : std_logic; -- any error in last received character
-- Internal versions of RIN, XOUT, nCTS, nDSR and nRTS for the purpose of
-- implementing the 'test mode' feature.
signal rin2 : std_logic;
signal xout2 : std_logic;
signal ncts2 : std_logic;
signal ndsr2 : std_logic;
signal nrts2 : std_logic;
-- clock divider and internal clock
signal bitclk : std_logic;
signal clkctr_q : unsigned(5 downto 0) := "000000";
begin
--
-- OUTPUT SIGNALS
--
nRTS <= nrts2;
nINT <= not intr;
XOUT <= xout2;
-- Convenience signals:
-- xout2 is used both as output and input signal (XOUT is out only)
-- xout2 is merged from xmtFSM (start, parity, etc.) and the xmt shift register
-- nrts2 is merely convenience shorthand
--
xout2 <= xsr_q(0) when xmtFSM_q.state=BITS else xmtFSM_q.xout;
nrts2 <= not xmtFSM_q.rts;
-- Implement TSTMD functionality
--
ncts2 <= nCTS when cruFLG_q.tstmd/='1' else nrts2;
rin2 <= RIN when cruFLG_q.tstmd/='1' else xout2;
ndsr2 <= nDSR when cruFLG_q.tstmd/='1' else '0';
--
-- CLOCK DIVIDER
--
-- Modify as needed to make 'bitclk' run at 1Mhz, being '1' for one period of CLK.
--
clkdiv: process(CLK, clkctr_q, ctl_q)
variable v : unsigned(5 downto 0);
begin
v := clkctr_q;
if rising_edge(CLK) then
v := v + 1;
if v=49 then v:="111111"; end if; -- ERIK: Here CLK is 50MHz.
-- if v="1001" then v:="1111"; end if; -- CLK is 10MHz, div by 10,
clkctr_q <= v;
end if;
end process;
bitclk <= '1' when clkctr_q="000000" else '0';
--
-- CRU CONTROLLER
--
-- Define flag register
--
cruFLG_reg : process(clk)
begin
if rising_edge(clk) then cruFLG_q <= cruFLG_d; end if;
end process;
cruFLG_cmb : process(clk, cruFLG_q, ndsr2, ncts2, nCE, CRUCLK, CRUOUT, S)
variable v : cruFLG_type;
variable rst, timenb, rienb : std_logic;
begin
v := cruFLG_q;
rst := '0'; timenb := '0'; rienb := '0';
-- Monitor and flag device state changes
v.pdsr := ndsr2;
v.pcts := ncts2;
if cruFLG_q.pdsr/=v.pdsr or cruFLG_q.pcts/=v.pcts then
v.dsch := '1';
end if;
if nCE='0' and CRUCLK='1' then
-- handle reset
if S="11111" then
rst := '1'; -- signal to reset other controllers
v.dscenb := '0';
v.timenb := '0';
v.xienb := '0';
v.rienb := '0';
v.brkon := '0';
v.rtson := '0';
v.tstmd := '0';
v.ldctl := '1';
v.ldir := '1';
v.lrdr := '1';
v.lxdr := '1';
v.dsch := '0';
else
case S is
-- Handle controller CRU bits
when "10101" => v.dscenb := CRUOUT; v.dsch := '0'; -- reset device state change flag
when "10100" => v.timenb := CRUOUT; timenb := '1'; -- signal reset timer error flags
when "10011" => v.xienb := CRUOUT;
when "10010" => v.rienb := CRUOUT; rienb := '1'; -- signal reset receiver error flags
when "10001" => v.brkon := CRUOUT;
when "10000" => v.rtson := CRUOUT;
when "01111" => v.tstmd := CRUOUT;
when "01110" => v.ldctl := CRUOUT;
when "01101" => v.ldir := CRUOUT;
when "01100" => v.lrdr := CRUOUT;
when "01011" => v.lxdr := CRUOUT;
when others => null;
end case;
end if;
end if;
-- On falling edge of CRUCLK reset register select bits as needed.
-- (see table 4 datasheet)
v.cruclk := CRUCLK;
if cruFLG_q.cruclk='1' and v.cruclk='0' then
if S="01010" and v.ldctl='0' and v.ldir='0' and v.lrdr='1' then
v.lrdr := '0';
end if;
if S="00111" then
if v.ldctl='1' then
v.ldctl := '0';
elsif v.ldir='1' then
v.ldir:='0';
end if;
end if;
end if;
cruFLG_d <= v;
sig_reset <= rst; -- reset other controllers
sig_timenb <= timenb; -- reset timer controller error flags
sig_rienb <= rienb; -- reset receiver controller error flags
sig_ldir <= (cruFLG_q.ldir and not v.ldir); -- restart timer counter
end process;
-- define control register and its CRU interface
--
ctl_reg : process(clk)
begin
if rising_edge(clk) then ctl_q <= ctl_d; end if;
end process;
ctl_cmb : process(ctl_q, nCE, CRUCLK, cruFLG_q, CRUOUT, S)
variable v : ctl_type;
begin
v := ctl_q;
if nCE='0' and CRUCLK='1' and cruFLG_q.ldctl='1' then
case S is
when "00111" => v.sbs(2) := CRUOUT;
when "00110" => v.sbs(1) := CRUOUT;
when "00101" => v.penb := CRUOUT;
when "00100" => v.podd := CRUOUT;
when "00011" => v.clk4m := CRUOUT;
-- "00010" is not used
when "00001" => v.rcl(1) := CRUOUT;
when "00000" => v.rcl(0) := CRUOUT;
when others => null;
end case;
end if;
ctl_d <= v;
end process;
--
-- INTERVAL TIMER
--
-- define timer interval register and its CRU interface
--
tmr_reg : process(clk)
begin
if rising_edge(clk) then tmr_q <= tmr_d; end if;
end process;
tmr_cmb : process(tmr_q, nCE, CRUCLK, cruFLG_q, CRUOUT, S)
variable v : std_logic_vector(7 downto 0);
begin
v := tmr_q;
if nCE='0' and CRUCLK='1' and cruFLG_q.ldctl='0' and cruFLG_q.ldir='1' then
case S is
when "00111" => v(7) := CRUOUT;
when "00110" => v(6) := CRUOUT;
when "00101" => v(5) := CRUOUT;
when "00100" => v(4) := CRUOUT;
when "00011" => v(3) := CRUOUT;
when "00010" => v(2) := CRUOUT;
when "00001" => v(1) := CRUOUT;
when "00000" => v(0) := CRUOUT;
when others => null;
end case;
end if;
tmr_d <= v;
end process;
-- define timer counter register
--
timctr_reg : process(clk)
begin
if rising_edge(clk) then timctr_q <= timctr_d; end if;
end process;
timctr_cmb : process(timctr_q, tmr_q, cruFLG_q, bitclk, sig_ldir)
variable v : unsigned(13 downto 0);
variable z : std_logic;
variable n : natural;
begin
v := timctr_q;
if v="00000000000000" then z := '1'; else z := '0'; end if;
if cruFLG_q.tstmd='1' then n := 32; else n := 1; end if;
if sig_ldir='1' or z='1' then
v := unsigned(tmr_q&"000000");
elsif bitclk='1' then
v := v - n;
end if;
timctr_d <= v;
sig_timctr_iszero <= z;
end process;
-- define timer controller register
--
timFSM_reg : process(clk)
begin
if rising_edge(clk) then timFSM_q <= timFSM_d; end if;
end process;
timFSM_cmb : process(timFSM_q, sig_reset, sig_timenb, sig_timctr_iszero)
variable v : timFSM_type;
begin
v := timFSM_q;
if sig_reset='1' or sig_timenb='1'then
v.timelp := '0';
v.timerr := '0';
elsif sig_timctr_iszero='1' then
if v.timelp='1' then v.timerr := '1'; end if;
v.timelp := '1';
end if;
timFSM_d <= v;
end process;
--
-- TRANSMITTER
--
-- define transmit data rate register
--
xdr_reg : process(clk)
begin
if rising_edge(clk) then xdr_q <= xdr_d; end if;
end process;
xdr_cmb : process(xdr_q, nCE, CRUCLK, cruFLG_q, CRUOUT, S)
variable v : std_logic_vector(10 downto 0);
begin
v := xdr_q;
if nCE='0' and CRUCLK='1' and cruFLG_q.ldctl='0' and cruFLG_q.ldir='0' and cruFLG_q.lxdr='1' then
case S is
when "01010" => v(10) := CRUOUT;
when "01001" => v(9) := CRUOUT;
when "01000" => v(8) := CRUOUT;
when "00111" => v(7) := CRUOUT;
when "00110" => v(6) := CRUOUT;
when "00101" => v(5) := CRUOUT;
when "00100" => v(4) := CRUOUT;
when "00011" => v(3) := CRUOUT;
when "00010" => v(2) := CRUOUT;
when "00001" => v(1) := CRUOUT;
when "00000" => v(0) := CRUOUT;
when others => null;
end case;
end if;
xdr_d <= v;
end process;
-- define transmit buffer register
--
xbr_reg : process(clk)
begin
if rising_edge(clk) then xbr_q <= xbr_d; end if;
end process;
xbr_cmb : process(xbr_q, nCE, CRUCLK, cruFLG_q, CRUOUT, S)
variable v : std_logic_vector(7 downto 0);
variable xbr7 : std_logic;
begin
v := xbr_q; xbr7 := '0';
if nCE='0' and CRUCLK='1' and cruFLG_q.ldctl='0' and cruFLG_q.ldir='0'
and cruFLG_q.lrdr='0' and cruFLG_q.lxdr='0' then
case S is
when "00111" => v(7) := CRUOUT;
when "00110" => v(6) := CRUOUT;
when "00101" => v(5) := CRUOUT;
when "00100" => v(4) := CRUOUT;
when "00011" => v(3) := CRUOUT;
when "00010" => v(2) := CRUOUT;
when "00001" => v(1) := CRUOUT;
when "00000" => v(0) := CRUOUT;
when others => null;
end case;
-- writing to bit 7 resets the XBRE flag in the controller.
if S="00111" then xbr7 := '1'; end if;
end if;
xbr_d <= v;
sig_xbr7 <= xbr7;
end process;
-- define transmit shift register
--
xsr_reg : process(clk)
begin
if rising_edge(clk) then xsr_q <= xsr_d; end if;
end process;
xsr_cmb : process(xsr_q, xbr_q, sig_xsr_load, sig_xsr_shift)
variable v : std_logic_vector(7 downto 0);
begin
v := xsr_q;
if sig_xsr_load='1' then
v := xbr_q;
elsif sig_xsr_shift='1' then
v := '0'&xsr_q(7 downto 1);
end if;
xsr_d <= v;
end process;
-- define transmit half-bit counter register
--
xhbctr_reg : process(clk)
begin
if rising_edge(clk) then xhbctr_q <= xhbctr_d; end if;
end process;
xhbctr_cmb : process(xhbctr_q, xdr_q, bitclk, sig_xhb_reset)
variable v : unsigned(12 downto 0);
variable z : std_logic;
variable n : natural;
begin
v := xhbctr_q;
if v="0000000000000" then z := '1'; else z := '0'; end if;
if xdr_q(10)='0' then n := 8; else n := 1; end if;
if sig_xhb_reset='1' or z='1' then
v := unsigned(xdr_q(9 downto 0)&"000");
elsif bitclk='1' then
v := v - n;
end if;
xhbctr_d <= v;
sig_xhbctr_iszero <= z;
end process;
-- define xmt controller register
--
xmtFSM_reg : process(clk)
begin
if rising_edge(clk) then xmtFSM_q <= xmtFSM_d; end if;
end process;
xmtFSM_cmb : process(xmtFSM_q, ctl_q, cruFLG_q, xsr_q, ncts2, sig_reset, sig_xbr7, sig_xhbctr_iszero)
variable v : xmtFSM_type;
variable par : std_logic;
variable xsr_load, xsr_shift, xhb_reset : std_logic;
variable xbits : unsigned(4 downto 0);
variable sbits : unsigned(4 downto 0);
begin
v := xmtFSM_q; xsr_load := '0'; xsr_shift := '0'; xhb_reset := '0';
-- prepare half-bit times for data word and stop bits
case ctl_q.rcl is
when "11" => xbits := "10000";
when "10" => xbits := "01110";
when "01" => xbits := "01100";
when others => xbits := "01010";
end case;
case ctl_q.sbs is
when "00" => sbits := "00011";
when "01" => sbits := "00100";
when others => sbits := "00010";
end case;
if sig_xhbctr_iszero='1' then
v.bitctr := v.bitctr - 1;
end if;
if sig_reset='1' then
v.xout := '1';
v.rts := '0';
v.xsre := '1';
v.xbre := '1';
elsif sig_xbr7='1'then
v.xbre := '0';
elsif v.state=BREAK then
v.xout := '0';
if cruFLG_q.brkon='0' then v.state := IDLE; end if;
elsif v.state=IDLE then
v.rts := cruFLG_q.rtson;
if v.rts='1' and ncts2='0' then
if v.xbre='1' then
if cruFLG_q.brkon='1' then v.state := BREAK; end if;
else
v.state := START;
v.xout := '0';
v.bitctr := "00010";
xhb_reset := '1';
end if;
end if;
elsif sig_xhbctr_iszero='1' then
case v.state is
when START =>
if v.bitctr=0 then
xsr_load := '1';
v.xsre := '0';
v.xbre := '1';
v.state := BITS;
v.bitctr := xbits;
v.par := '0';
end if;
when BITS =>
if v.bitctr(0)='0' then
v.par := v.par xor xsr_q(0);
xsr_shift := '1';
end if;
if v.bitctr=0 then
if ctl_q.penb='1' then
v.xout := v.par xor ctl_q.podd;
v.state := PARITY;
v.bitctr := "00010";
else
v.xout := '1';
v.state := STOP;
v.bitctr := sbits;
end if;
end if;
when PARITY =>
if v.bitctr=0 then
v.xout := '1';
v.state := STOP;
v.bitctr := sbits;
end if;
when STOP =>
if v.bitctr=0 then
v.xsre := '1';
v.state := IDLE;
end if;
when others => v.state := IDLE;
end case;
end if;
xmtFSM_d <= v;
sig_xhb_reset <= xhb_reset;
sig_xsr_load <= xsr_load;
sig_xsr_shift <= xsr_shift;
end process;
--
-- RECEIVER
--
-- define receive data rate register and its CRU interface
--
rdr_reg : process(clk)
begin
if rising_edge(clk) then rdr_q <= rdr_d; end if;
end process;
rdr_cmb : process(rdr_q, nCE, CRUCLK, cruFLG_q, CRUOUT, S)
variable v : std_logic_vector(10 downto 0);
begin
v := rdr_q;
if nCE='0' and CRUCLK='1' and cruFLG_q.ldctl='0' and cruFLG_q.ldir='0' and cruFLG_q.lrdr='1' then
case S is
when "01010" => v(10) := CRUOUT;
when "01001" => v(9) := CRUOUT;
when "01000" => v(8) := CRUOUT;
when "00111" => v(7) := CRUOUT;
when "00110" => v(6) := CRUOUT;
when "00101" => v(5) := CRUOUT;
when "00100" => v(4) := CRUOUT;
when "00011" => v(3) := CRUOUT;
when "00010" => v(2) := CRUOUT;
when "00001" => v(1) := CRUOUT;
when "00000" => v(0) := CRUOUT;
when others => null;
end case;
end if;
rdr_d <= v;
end process;
-- define receive buffer register
--
rbr_reg : process(clk)
begin
if rising_edge(clk) then rbr_q <= rbr_d; end if;
end process;
rbr_cmb : process(rbr_q, ctl_q, rsr_q, sig_rbr_load)
variable v : std_logic_vector(7 downto 0);
begin
v := rbr_q;
if sig_rbr_load='1' then
case ctl_q.rcl is
when "11" => v := rsr_q;
when "10" => v := "0" & rsr_q(7 downto 1);
when "01" => v := "00" & rsr_q(7 downto 2);
when others => v := "000" & rsr_q(7 downto 3);
end case;
end if;
rbr_d <= v;
end process;
-- define receive shift register
--
rsr_reg : process(clk)
begin
if rising_edge(clk) then rsr_q <= rsr_d; end if;
end process;
rsr_cmb : process(rsr_q, rbr_q, rin2, sig_rsr_shift)
variable v : std_logic_vector(7 downto 0);
begin
v := rsr_q;
if sig_rsr_shift='1' then
v := rin2 & rsr_q(7 downto 1);
end if;
rsr_d <= v;
end process;
-- define receive half-bit counter register
--
rhbctr_reg : process(clk)
begin
if rising_edge(clk) then rhbctr_q <= rhbctr_d; end if;
end process;
rhbctr_cmb : process(rhbctr_q, rdr_q, bitclk, sig_rhb_reset)
variable v : unsigned(12 downto 0);
variable z : std_logic;
variable n : natural;
begin
v := rhbctr_q;
if v="0000000000000" then z := '1'; else z := '0'; end if;
if rdr_q(10)='0' then n := 8; else n := 1; end if;
if sig_rhb_reset='1' or z='1' then
v := unsigned(rdr_q(9 downto 0)&"000");
elsif bitclk='1' then
v := v - n;
end if;
rhbctr_d <= v;
sig_rhbctr_iszero <= z;
end process;
-- define rcv controller register
--
rcvFSM_reg : process(clk)
begin
if rising_edge(clk) then rcvFSM_q <= rcvFSM_d; end if;
end process;
rcvFSM_cmb : process(rcvFSM_q, ctl_q, rin2, sig_reset, sig_rienb, sig_rhbctr_iszero)
variable v : rcvFSM_type;
variable par : std_logic;
variable rbr_load, rsr_shift, rhb_reset : std_logic;
variable rbits : unsigned(4 downto 0);
begin
v := rcvFSM_q;
rbr_load := '0'; rsr_shift := '0'; rhb_reset := '0';
-- prepare half-bit times for data word and stop bits
case ctl_q.rcl is
when "11" => rbits := "10000";
when "10" => rbits := "01110";
when "01" => rbits := "01100";
when others => rbits := "01010";
end case;
if sig_rhbctr_iszero='1' then
v.bitctr := v.bitctr - 1;
end if;
if sig_reset='1' or sig_rienb='1' then
v.rbrl := '0';
v.rover := '0';
v.rper := '0';
v.rfer := '0';
end if;
if v.state=IDLE then
v.rsbd := '0';
v.rfbd := '0';
if rin2='1' then
v.state := START1;
end if;
elsif v.state=START1 then
if rin2='0' then
v.state := START;
v.bitctr := "00001";
rhb_reset := '1';
end if;
elsif sig_rhbctr_iszero='1' then
case v.state is
when START =>
if v.bitctr=0 then
if rin2='1' then
v.state := IDLE;
else
v.state := BITS;
v.bitctr := rbits;
v.par := '0';
v.rsbd := '1';
end if;
end if;
when BITS =>
if v.bitctr(0)='0' then
v.par := v.par xor rin2;
v.rfbd := '1';
rsr_shift := '1';
end if;
if v.bitctr=0 then
v.bitctr := "00010";
if ctl_q.penb='1' then
v.state := PARITY;
else
v.state := STOP;
end if;
end if;
when PARITY =>
if v.bitctr=0 then
v.par := v.par xor rin2;
v.state := STOP;
v.bitctr := "00010";
end if;
when STOP =>
if v.bitctr=0 then
v.rover := v.rbrl;
v.rper := v.par;
v.rfer := not rin2;
v.rbrl := '1';
rbr_load := '1';
v.state := IDLE;
end if;
when others => v.state := IDLE;
end case;
end if;
rcvFSM_d <= v;
sig_rhb_reset <= rhb_reset;
sig_rbr_load <= rbr_load;
sig_rsr_shift <= rsr_shift;
end process;
--
-- CRU INPUT
--
-- Combinational helper signals (see figure 7 datasheet)
--
dscint <= cruFLG_q.dsch and cruFLG_q.dscenb;
rint <= rcvFSM_q.rbrl and cruFLG_q.rienb;
xint <= xmtFSM_q.xbre and cruFLG_q.xienb;
timint <= timFSM_q.timelp and cruFLG_q.timenb;
intr <= dscint or rint or xint or timint;
rcverr <= rcvFSM_q.rfer or rcvFSM_q.rover or rcvFSM_q.rper;
flag <= cruFLG_q.ldctl or cruFLG_q.ldir or cruFLG_q.lrdr or cruFLG_q.lxdr or cruFLG_q.brkon;
-- the CRUIN signal is essentially a 32-way mux with a tri-state output
--
CRUIN <=
'Z' when nCE='1' else
intr when S="11111" else -- 31, any interrupt pending
flag when S="11110" else -- 30, 'flag' field
cruFLG_q.dsch when S="11101" else -- 29, device status change
not nCTS when S="11100" else -- 28, inverse of nCTS input
not nDSR when S="11011" else -- 27, inverse of nDSR input
not nrts2 when S="11010" else -- 26, inverse of nRTS output
timFSM_q.timelp when S="11001" else -- 25, timer elapsed
timFSM_q.timerr when S="11000" else -- 24, timer elapsed more than once
xmtFSM_q.xsre when S="10111" else -- 23, transmit shift register empty
xmtFSM_q.xbre when S="10110" else -- 22, transmit buffer register empty
rcvFSM_q.rbrl when S="10101" else -- 21, receive buffer register loaded
dscint when S="10100" else -- 20, device status change interrupt pending
timint when S="10011" else -- 19, timer interrupt pending
'0' when S="10010" else -- 18, not used (always 0)
xint when S="10001" else -- 17, transmit interrupt pending
rint when S="10000" else -- 16, receive interrupt pending
RIN when S="01111" else -- 15, direct copy of RIN
rcvFSM_q.rsbd when S="01110" else -- 14, receive start bit detected
rcvFSM_q.rfbd when S="01101" else -- 13, receive first bit detected
rcvFSM_q.rfer when S="01100" else -- 12, receive framing error
rcvFSM_q.rover when S="01011" else -- 11, receive overflow error
rcvFSM_q.rper when S="01010" else -- 10, receive parity error
rcverr when S="01001" else -- 9, any receive error
'0' when S="01000" else -- 8, not used (always 0)
rbr_q(7) when S="00111" else -- 7, receive buffer register, bit 7
rbr_q(6) when S="00110" else
rbr_q(5) when S="00101" else
rbr_q(4) when S="00100" else
rbr_q(3) when S="00011" else
rbr_q(2) when S="00010" else
rbr_q(1) when S="00001" else
rbr_q(0) when S="00000" else -- 0, receive buffer register, bit 0
'0';
end;
|
lgpl-3.0
|
19118ab5d4b33a3c7857d7d6fd61f1e0
| 0.507241 | 3.448439 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/ALU.vhd
| 1 | 4,391 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
Port ( input_a : in STD_LOGIC_VECTOR (31 downto 0);
input_b : in STD_LOGIC_VECTOR (31 downto 0);
SEL : in STD_LOGIC_VECTOR (4 downto 0);
out_alu : out STD_LOGIC_VECTOR(31 downto 0));
end alu;
architecture Behavioral of alu is
signal shift, hi, lo, mul_result, div_result, div_rem : std_logic_vector (31 downto 0);
begin
process(input_a, input_b, SEL)
begin
case SEL is
when "00000" =>
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)), out_alu'length)) ; --ADD
when "00001" =>
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) - to_integer (unsigned(input_b)), out_alu'length)); --SUB
when "00010" =>
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)), out_alu'length)) ; --ADDI
when "00011" =>
hi<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) * to_integer (unsigned(input_b)), 64))(63 downto 32);
lo<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) * to_integer (unsigned(input_b)), 64))(31 downto 0);
mul_result <= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) * to_integer (unsigned(input_b)), 32));
out_alu<= mul_result;
when "00100" =>
div_result <= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) / to_integer (unsigned(input_b)), div_result'length)); --DIV
div_rem <= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) mod to_integer (unsigned(input_b)), div_rem'length));
lo <= div_result;
hi <= div_rem;
out_alu <= div_result;
when "00101" =>
if (unsigned(input_a) < unsigned(input_b)) then --SLT
out_alu <= x"00000001";
else
out_alu <= x"00000000";
end if;
when "00110" =>
if (unsigned(input_a) < unsigned(input_b)) then --SLTI
out_alu <= x"00000001";
else
out_alu <= x"00000000";
end if;
when "00111" =>
out_alu<= input_a and input_b; --AND
when "01000" =>
out_alu<= input_a or input_b; --OR
when "01001" =>
out_alu<= input_a nor input_b; --NOR
when "01010" =>
out_alu<= input_a xor input_b; --XOR
when "01011" =>
out_alu<= input_a and input_b; --ANDI
when "01100" =>
out_alu<= input_a or input_b; --ORI
when "01101" =>
out_alu<= input_a xor input_b; --xORI
when "01110" => --MOVE FROM HIGH
out_alu<= hi;
when "01111" => -- MOVE FROM LOW
out_alu<= lo;
when "10000" => -- LUI
out_alu <= input_b (15 downto 0) & std_logic_vector(to_unsigned(0, 16));
when "10001" => --sll
out_alu <= input_a ((31 - to_integer(unsigned(input_b(10 downto 6)))) downto 0) & std_logic_vector(to_unsigned(0, to_integer(unsigned(input_b(10 downto 6)))));
when "10010" => --srl
out_alu <= std_logic_vector(to_unsigned(0, to_integer(unsigned(input_b(10 downto 6))))) & input_a (31 downto (0 + to_integer(unsigned(input_b(10 downto 6)))));
when "10011" => -- sra
if input_a(31) = '0' then
out_alu <= std_logic_vector(to_unsigned(0, to_integer(unsigned(input_b(10 downto 6))))) & input_a (31 downto (0 + to_integer(unsigned(input_b(10 downto 6)))));
else
out_alu <= std_logic_vector(to_unsigned(1, to_integer(unsigned(input_b(10 downto 6))))) & input_a (31 downto (0 + to_integer(unsigned(input_b(10 downto 6)))));
end if;
when "10100" => -- lw
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)), out_alu'length)) ;
when "10101" => -- sw
out_alu<= std_logic_vector(to_unsigned(to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)), out_alu'length)) ;
when "10110" => -- beq
out_alu<= std_logic_vector(to_unsigned((to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)) * 4), out_alu'length));
when "10111" => -- bne
out_alu<= std_logic_vector(to_unsigned((to_integer (unsigned(input_a)) + to_integer (unsigned(input_b)) * 4), out_alu'length));
when "11000" => -- j ASSUME input b is lower 26 bits 0 padded
out_alu<= input_a(31 downto 28) & input_b(25 downto 0) & "00";
when "11001" => -- jr
out_alu <= input_a;
when "11010" => -- jal
out_alu<= input_a(31 downto 28) & input_b(25 downto 0) & "00";
when others =>
NULL;
end case;
end process;
end Behavioral;
|
gpl-3.0
|
a452aa2f2a0847d8286168976221570e
| 0.625826 | 2.911804 | false | false | false | false |
krabo0om/pauloBlaze
|
sources/program_counter.vhd
| 2 | 4,197 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity program_counter is
generic (
interrupt_vector : unsigned(11 downto 0) := X"3FF";
stack_depth : positive := 30
);
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
rst_req : out std_logic;
bram_pause : in STD_LOGIC;
call : in STD_LOGIC;
ret : in std_logic;
inter_j : in std_logic;
jump : in STD_LOGIC;
jmp_addr : in unsigned (11 downto 0);
address : out unsigned (11 downto 0));
end program_counter;
architecture Behavioral of program_counter is
-- Logarithms: log*ceil*
-- From PoC-Library https://github.com/VLSI-EDA/PoC
-- ==========================================================================
function log2ceil(arg : positive) return natural is
variable tmp : positive := 1;
variable log : natural := 0;
begin
if arg = 1 then return 0; end if;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
type stack_t is array (stack_depth-1 downto 0) of unsigned(11 downto 0);
signal stack : stack_t := (others => (others => '0'));
signal pointer : unsigned (log2ceil(stack_depth+1)-1 downto 0);
signal counter : unsigned (12 downto 0);
signal jmp_int : std_logic;
signal jmp_done : std_logic;
signal addr_o : unsigned (11 downto 0);
begin
jmp_int <= jump or call or inter_j;
address <= interrupt_vector when inter_j = '1' else addr_o ;
clken : process (clk)
variable p : unsigned(pointer'left+1 downto 0);
variable addr_next : unsigned (11 downto 0);
begin
if (rising_edge(clk)) then
if (reset = '1') then
counter <= x"001" & '0';
addr_o <= (others => '0');
jmp_done <= '0';
pointer <= (others => '0');
rst_req <= '0';
else
if (bram_pause = '1') then
-- counter <= addr_o & '1';
jmp_done <= jmp_done;
-- addr_o <= counter(12 downto 1);
elsif (ret = '1' and jmp_done <= '0') then
p := ('0' & pointer) - 1;
if (p = (p'range => '1')) then
rst_req <= '1';
else
pointer <= p(pointer'range);
addr_next := stack(to_integer(p));
counter <= addr_next & '1';
addr_o <= addr_next;
jmp_done <= '1';
end if;
elsif (inter_j = '1') then
p := ('0' & pointer) + 1;
if (p > stack_depth) then
rst_req <= '1';
else
stack(to_integer(pointer)) <= addr_o-1;
pointer <= p(pointer'range);
counter <= (interrupt_vector & '1') + ("" & '1');
addr_o <= interrupt_vector;
jmp_done <= '1';
end if;
elsif (jmp_int = '1' and jmp_done <= '0') then
if (call = '1') then
p := ('0' & pointer) +1;
if (p > stack_depth) then
rst_req <= '1';
else
stack(to_integer(pointer)) <= addr_o+1;
pointer <= p(pointer'range);
end if;
end if;
counter <= jmp_addr & '1';
addr_o <= jmp_addr;
jmp_done <= '1';
else
jmp_done <= '0';
counter <= counter + 1;
addr_o <= counter(12 downto 1);
end if;
end if;
end if;
end process clken;
end Behavioral;
|
apache-2.0
|
391b2c55f6b7dfd91ef5ecbd90b766b8
| 0.549202 | 3.221028 | false | false | false | false |
FearlessJojo/COPproject
|
project/Forwarding.vhd
| 1 | 2,456 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:21 11/20/2016
-- Design Name:
-- Module Name: Forwarding - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Forwarding is
Port ( ID_Rs : in STD_LOGIC_VECTOR (3 downto 0);
ID_Rt : in STD_LOGIC_VECTOR (3 downto 0);
ID_EXE_Rd : in STD_LOGIC_VECTOR (3 downto 0);
ID_EXE_regWE : in STD_LOGIC;
ID_EXE_AccMEM : in STD_LOGIC;
EXE_MEM_Rd : in STD_LOGIC_VECTOR (3 downto 0);
EXE_MEM_regWE : in STD_LOGIC;
PCReg_enable : out STD_LOGIC;
IF_ID_enable : out STD_LOGIC;
ID_EXE_enable : out STD_LOGIC;
ID_EXE_bubble : out STD_LOGIC;
ALUctrl1 : out STD_LOGIC_VECTOR (1 downto 0);
ALUctrl2 : out STD_LOGIC_VECTOR (1 downto 0)
);
end Forwarding;
architecture Behavioral of Forwarding is
begin
process(ID_Rs,ID_Rt,ID_EXE_Rd,ID_EXE_regWE,ID_EXE_AccMEM,EXE_MEM_Rd,EXE_MEM_regWE)
begin
if (((ID_EXE_AccMEM = '1') and (ID_EXE_regWE = '1')) and ((ID_Rs = ID_EXE_Rd) or (ID_Rt = ID_EXE_Rd))) then
PCReg_enable <= '0';
IF_ID_enable <= '0';
ID_EXE_enable <= '0';
ID_EXE_bubble <= '1';
else
PCReg_enable <= '1';
IF_ID_enable <= '1';
ID_EXE_enable <= '1';
ID_EXE_bubble <= '0';
end if;
if ((ID_Rs = ID_EXE_Rd) and ID_EXE_regWE = '1') then
ALUctrl1 <= "10";
else
if ((ID_Rs = EXE_MEM_Rd) and EXE_MEM_regWE = '1') then
ALUctrl1 <= "11";
else
ALUCtrl1 <= "00";
end if;
end if;
if ((ID_Rt = ID_EXE_Rd) and ID_EXE_regWE = '1') then
ALUctrl2 <= "10";
else
if ((ID_Rt = EXE_MEM_Rd) and EXE_MEM_regWE = '1') then
ALUctrl2 <= "11";
else
ALUCtrl2 <= "00";
end if;
end if;
end process;
end Behavioral;
|
mit
|
064884ec402259281ad6041a179214c4
| 0.571661 | 3.043371 | false | false | false | false |
FearlessJojo/COPproject
|
project/UART.vhd
| 1 | 2,479 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:22:35 11/21/2016
-- Design Name:
-- Module Name: UART - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx prAdderitives in this code.
--library UNISAdder;
--use UNISAdder.VComponents.all;
entity UART is
Port (
CLK : in STD_LOGIC;
ACCMEM : in STD_LOGIC;
MEM_WE : in STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1WE : out STD_LOGIC;
RAM1EN : out STD_LOGIC;
data_ready : in STD_LOGIC;
rdn : out STD_LOGIC;
wrn : out STD_LOGIC;
tbre : in STD_LOGIC;
tsre : in STD_LOGIC;
RAM1Data : inout STD_LOGIC_VECTOR (15 downto 0));
end UART;
architecture Behavioral of UART is
signal state_in : integer range 0 to 3 := 0;
signal state_out : integer range 0 to 5 := 0;
begin
process(CLK)
begin
if (CLK'EVENT) and (CLK = '1') then
if (MEM_WE = '1') and (ACCMEM = '0') then
case state_in is
when 0 =>
state_in <= 1;
rdn <= '1';
RAM1OE <= '1';
RAM1WE <= '1';
RAM1EN <= '1';
RAM1Data <= (others => 'Z');
when 1 =>
rdn <= '1';
if (data_ready = '1') then
state_in <= 2;
end if;
when 2 =>
state_in <= 3;
rdn <= '0';
when 3 =>
state_in <= 0;
when others =>
null;
end case;
end if;
if (MEM_WE = '0') and (ACCMEM = '1') then
case state_out is
when 0 =>
state_out <= 1;
rdn <= '1';
wrn <= '1';
when 1 =>
state_out <= 2;
when 2 =>
state_out <= 3;
wrn <= '0';
when 3 =>
state_out <= 4;
wrn <= '1';
when 4 =>
if (tbre = '1') then
state_out <= 5;
end if;
when 5 =>
if (tsre = '1') then
state_out <= 0;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
3c77d3928813614f70fdb122d0f7d152
| 0.518758 | 3.094881 | false | false | false | false |
FearlessJojo/COPproject
|
project/RF.vhd
| 1 | 6,079 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:08:56 11/21/2016
-- Design Name:
-- Module Name: RF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RF is
Port ( regWE : in STD_LOGIC;
RFctrl : in STD_LOGIC_VECTOR (2 downto 0);
MEMOUT : in STD_LOGIC_VECTOR (15 downto 0);
Rd : in STD_LOGIC_VECTOR (3 downto 0);
Inst : in STD_LOGIC_VECTOR (5 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
A : out STD_LOGIC_VECTOR (15 downto 0);
B : out STD_LOGIC_VECTOR (15 downto 0)
);
end RF;
architecture Behavioral of RF is
signal R0 : std_logic_vector (15 downto 0) := "0000000000000000";
signal R1 : std_logic_vector (15 downto 0) := "0000000000000000";
signal R2 : std_logic_vector (15 downto 0) := "0000000000000000";
signal R3 : std_logic_vector (15 downto 0) := "0000000000000000";
signal R4 : std_logic_vector (15 downto 0) := "0000000000000000";
signal R5 : std_logic_vector (15 downto 0) := "0000000000000000";
signal R6 : std_logic_vector (15 downto 0) := "0000000000000000";
signal R7 : std_logic_vector (15 downto 0) := "0000000000000000";
signal IH : std_logic_vector (15 downto 0) := "0000000000000000";
signal SP : std_logic_vector (15 downto 0) := "0000000000000000";
signal RA : std_logic_vector (15 downto 0) := "0000000000000000";
begin
process(RFctrl, Inst, R0, R1, R2, R3, R4, R5, R6, R7, IH, SP, RA, regWE, MEMOUT, Rd)
begin
case RFctrl is
when "000" =>
A <= "0000000000000000";
B <= "0000000000000000";
when "001" =>
if (("0" & Inst(5 downto 3)) = Rd and regWE = '1') then
A <= MEMOUT;
else
case Inst(5 downto 3) is
when "000" => A <= R0;
when "001" => A <= R1;
when "010" => A <= R2;
when "011" => A <= R3;
when "100" => A <= R4;
when "101" => A <= R5;
when "110" => A <= R6;
when "111" => A <= R7;
when others => A <= "0000000000000000";
end case;
end if;
B <= "0000000000000000";
when "010" =>
if (("0" & Inst(5 downto 3)) = Rd and regWE = '1') then
A <= MEMOUT;
else
case Inst(5 downto 3) is
when "000" => A <= R0;
when "001" => A <= R1;
when "010" => A <= R2;
when "011" => A <= R3;
when "100" => A <= R4;
when "101" => A <= R5;
when "110" => A <= R6;
when "111" => A <= R7;
when others => A <= "0000000000000000";
end case;
end if;
if (("0" & Inst(2 downto 0)) = Rd and regWE = '1') then
B <= MEMOUT;
else
case Inst(2 downto 0) is
when "000" => B <= R0;
when "001" => B <= R1;
when "010" => B <= R2;
when "011" => B <= R3;
when "100" => B <= R4;
when "101" => B <= R5;
when "110" => B <= R6;
when "111" => B <= R7;
when others => B <= "0000000000000000";
end case;
end if;
when "011" =>
if (("0" & Inst(2 downto 0)) = Rd and regWE = '1') then
A <= MEMOUT;
else
case Inst(2 downto 0) is
when "000" => A <= R0;
when "001" => A <= R1;
when "010" => A <= R2;
when "011" => A <= R3;
when "100" => A <= R4;
when "101" => A <= R5;
when "110" => A <= R6;
when "111" => A <= R7;
when others => A <= "0000000000000000";
end case;
end if;
B <= "0000000000000000";
when "100" =>
if (Rd = "1000" and regWE = '1') then
A <= MEMOUT;
else
A <= SP;
end if;
B <= "0000000000000000";
when "101" =>
if (Rd = "1010" and regWE = '1') then
A <= MEMOUT;
else
A <= RA;
end if;
B <= "0000000000000000";
when "110" =>
if (Rd = "1001" and regWE = '1') then
A <= MEMOUT;
else
A <= IH;
end if;
B <= "0000000000000000";
when "111" =>
if (Rd = "1000" and regWE = '1') then
A <= MEMOUT;
else
A <= SP;
end if;
if (("0" & Inst(5 downto 3)) = Rd and regWE = '1') then
B <= MEMOUT;
else
case Inst(5 downto 3) is
when "000" => B <= R0;
when "001" => B <= R1;
when "010" => B <= R2;
when "011" => B <= R3;
when "100" => B <= R4;
when "101" => B <= R5;
when "110" => B <= R6;
when "111" => B <= R7;
when others => B <= "0000000000000000";
end case;
end if;
when others =>
A <= "0000000000000001";
B <= "0000000000000001";
end case;
end process;
process(clk, rst)
begin
if (clk'event and clk = '1') then
if (regWE = '1') then
case Rd is
when "0000" => R0 <= MEMOUT;
when "0001" => R1 <= MEMOUT;
when "0010" => R2 <= MEMOUT;
when "0011" => R3 <= MEMOUT;
when "0100" => R4 <= MEMOUT;
when "0101" => R5 <= MEMOUT;
when "0110" => R6 <= MEMOUT;
when "0111" => R7 <= MEMOUT;
when "1000" => SP <= MEMOUT;
when "1001" => IH <= MEMOUT;
when "1010" => RA <= MEMOUT;
when others => null;
end case;
end if;
end if;
if (rst = '0') then
R0 <= "0000000000000000";
R1 <= "0000000000000000";
R2 <= "0000000000000000";
R3 <= "0000000000000000";
R4 <= "0000000000000000";
R5 <= "0000000000000000";
R6 <= "0000000000000000";
R7 <= "0000000000000000";
IH <= "0000000000000000";
RA <= "0000000000000000";
SP <= "0000000000000000";
end if;
end process;
end Behavioral;
|
mit
|
2e14d261296c207c02226c77ebfc8a14
| 0.517519 | 3.057847 | false | false | false | false |
gustavowl/ProjetoOAC
|
ULA32bit/ula.vhd
| 1 | 11,607 |
-----------------------------------------------------------------------
-----------------------------DESLOCADOR--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador is
port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end deslocador;
architecture deslocador of deslocador is
begin
c <= a(31 downto 0) when desl = '0' else
'0' & a(31 downto 1) when lado = '0' else
a(30 downto 0) & '0';
cout <= a(30) when lado = '1' and desl = '1' else '0';
end deslocador;
-----------------------------------------------------------------------
--------------------------------MUX A----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1A is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end Mux8x1A;
architecture Mux8x1A of Mux8x1A is
component deslocador
port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
signal temp: std_logic_vector (31 downto 0);
signal tdesl, tz: std_logic;
begin
--seleciona o valor de saída baseado na escolha de entrada XYZ
--as primeiras condições são para operações em lógica booleana
--receberá o valor de A caso seja feita alguma operação algébrica
--ou deslocamento de bits
temp <= a and b when x = '0' and y = '1' and z = '0' else
a nor b when x = '0' and y = '1' and z = '1' else
a or b when x = '1' and y = '0' and z = '0' else a;
--só irá efetuar deslocamento de bits caso xyz = 101 ou 110
tdesl <= '1' when x = '1' and ( ( y = '0' and z = '1') or ( y = '1' and z = '0' ) ) else '0';
--tz armazena o lado para qual será efetuado o deslocamento
tz <= z;
desloc: deslocador port map (temp, tdesl, tz, c, cout);
end Mux8x1A;
-----------------------------------------------------------------------
--------------------------------MUX B----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1B is
port (
a: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0)
);
end Mux8x1B;
architecture Mux8x1B of Mux8x1B is
begin
c <= "00000000000000000000000000000000" when (x = '1' or y = '1') else
a when z = '0' else not a;
end Mux8x1B;
-----------------------------------------------------------------------
--------------------------------MUX C----------------------------------
---------------------------comparador----------------------------------
--Identifica se está fazendo subtração para CIN p/ conversão em complemento de 2
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1C is
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end Mux8x1C;
architecture Mux8x1C of Mux8x1C is
begin
c <= '1' when (x = '0' and y = '0' and z = '1') else '0';-- or
-- (x = '1' and y = '1' and z = '0') else '0';
end Mux8x1C;
-----------------------------------------------------------------------
---------------------------COMPONENTE LÓGICO---------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity CompLog is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector(31 downto 0);
ib: out std_logic_vector(31 downto 0);
Cin: out std_logic; --p/ conversão em complemento de 2
Cout: out std_logic --p/ identificar overflow na multiplicação
);
end CompLog;
architecture CompLog of CompLog is
component Mux8x1A
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
component Mux8x1B
port (
a: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0)
);
end component;
component Mux8x1C
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end component;
begin
mux8x1a0: Mux8x1A port map (a, b, x, y, z, ia, Cout);
-- ia <= "01001001";
mux8x1b0: Mux8x1B port map (b, x, y, z, ib);
mux8x1c0: Mux8x1C port map (x, y, z, Cin);
end CompLog;
-----------------------------------------------------------------------
--------------------------SOMADOR 1 BIT--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador1bit is
port (
a: in std_logic;
b: in std_logic;
cin: in std_logic;
s: out std_logic;
cout: out std_logic
);
end somador1bit;
architecture somador1bit of somador1bit is
begin
cout <= (cin and a) or (cin and b) or (a and b);
s <= (not cin and not a and b) or (not cin and a and not b)
or (cin and not a and not b) or (cin and a and b);
end somador1bit;
-----------------------------------------------------------------------
--------------------------SOMADOR 16 BITS-------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador16bits is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
cin: in std_logic;
s: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end somador16bits;
architecture somador16bits of somador16bits is
component somador1bit
port (
a, b, cin: in std_logic;
s, cout: out std_logic
);
end component;
signal ta, tb, ts: std_logic_vector(31 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16,
c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31: std_logic;
begin
ta <= a;
tb <= b;
s8b0: somador1bit port map (a(0), b(0), cin, ts(0), c0);
s8v1: somador1bit port map (a(1), b(1), c0, ts(1), c1);
s8v2: somador1bit port map (a(2), b(2), c1, ts(2), c2);
s8v3: somador1bit port map (a(3), b(3), c2, ts(3), c3);
s8v4: somador1bit port map (a(4), b(4), c3, ts(4), c4);
s8v5: somador1bit port map (a(5), b(5), c4, ts(5), c5);
s8v6: somador1bit port map (a(6), b(6), c5, ts(6), c6);
s8v7: somador1bit port map (a(7), b(7), c6, ts(7), c7);
s8b8: somador1bit port map (a(8), b(8), c7, ts(8), c8);
s8v9: somador1bit port map (a(9), b(9), c8, ts(9), c9);
s8v10: somador1bit port map (a(10), b(10), c9, ts(10), c10);
s8v11: somador1bit port map (a(11), b(11), c10, ts(11), c11);
s8v12: somador1bit port map (a(12), b(12), c11, ts(12), c12);
s8v13: somador1bit port map (a(13), b(13), c12, ts(13), c13);
s8v14: somador1bit port map (a(14), b(14), c13, ts(14), c14);
s8v15: somador1bit port map (a(15), b(15), c14, ts(15), c15);
s8v16: somador1bit port map (a(16), b(16), c15, ts(16), c16);
s8v17: somador1bit port map (a(17), b(17), c16, ts(17), c17);
s8v18: somador1bit port map (a(18), b(18), c17, ts(18), c18);
s8v19: somador1bit port map (a(19), b(19), c18, ts(19), c19);
s8v20: somador1bit port map (a(20), b(20), c19, ts(20), c20);
s8v21: somador1bit port map (a(21), b(21), c20, ts(21), c21);
s8v22: somador1bit port map (a(22), b(22), c21, ts(22), c22);
s8v23: somador1bit port map (a(23), b(23), c22, ts(23), c23);
s8v24: somador1bit port map (a(24), b(24), c23, ts(24), c24);
s8v25: somador1bit port map (a(25), b(25), c24, ts(25), c25);
s8v26: somador1bit port map (a(26), b(26), c25, ts(26), c26);
s8v27: somador1bit port map (a(27), b(27), c26, ts(27), c27);
s8v28: somador1bit port map (a(28), b(28), c27, ts(28), c28);
s8v29: somador1bit port map (a(29), b(29), c28, ts(29), c29);
s8v30: somador1bit port map (a(30), b(30), c29, ts(30), c30);
s8v31: somador1bit port map (a(31), b(31), c30, ts(31), c31);
--verifica overflow e underflow
cout <= (not a(31) and not b(31) and ts(31)) or (a(31) and b(31) and not ts(31));
s <= ts;
end somador16bits;
-----------------------------------------------------------------------
-----------------------------ULA-PO------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_po is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro: out std_logic
);
end ula_po;
architecture ula_po of ula_po is
component CompLog
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector (31 downto 0);
ib: out std_logic_vector(31 downto 0);
Cin: out std_logic;
Cout: out std_logic
);
end component;
component somador16bits
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
cin: in std_logic;
s: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
signal ia, ib: std_logic_vector(31 downto 0);
signal cin, cout, cout2: std_logic;
begin
complog0: CompLog port map (a, b, x, y, z, ia, ib, cin, cout);
somador8b0: somador16bits port map (ia, ib, cin, s, cout2);
couterro <= cout or cout2;
end ula_po;
-----------------------------------------------------------------------
-----------------------------ULA-PC------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_pc IS
port ( clk, do_op : in std_logic;
done, state: out std_logic
);
end ula_pc;
architecture ula_pc of ula_pc is
constant STDOINGOP: std_logic := '0';
constant STOPDONE: std_logic := '1';
signal st: std_logic;
begin
--espera um ciclo de clock para ter certeza que as operações
--se estabilizaram
PROCESS (clk)
BEGIN
if (clk'event and clk = '1') then
case st is
when STOPDONE =>
if (do_op = '1') then
st <= STDOINGOP;
end if;
when others =>
st <= STOPDONE;
end case;
end if;
end process;
done <= '1' when st = STOPDONE else '0';
state <= st;
end ula_pc;
-----------------------------------------------------------------------
-------------------------------ULA-------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z, clk, do_op: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro, done, state: out std_logic
);
end ula;
architecture ula of ula is
component ula_po
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro: out std_logic
);
end component;
component ula_pc
port (
clk, do_op : in std_logic;
done, state: out std_logic
);
end component;
begin
ulapo: ula_po port map (a, b, x, y, z, s, couterro);
ulapc: ula_pc port map (clk, do_op, done, state);
end ula;
|
gpl-2.0
|
a686acaff127f90df34f86cf27379375
| 0.532764 | 2.874907 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/Controller.vhd
| 1 | 8,006 |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity controller is
port(clk : in std_logic;
opcode : in std_logic_vector(5 downto 0);
funct : in std_logic_vector(5 downto 0);
branch: in std_logic;
oldBranch: in std_logic;
ALU1src : out STD_LOGIC;
ALU2src : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemToReg : out STD_LOGIC;
RType: out STD_LOGIC;
JType: out STD_LOGIC;
Shift: out STD_LOGIC;
structuralStall : out STD_LOGIC;
ALUOp : out STD_LOGIC_VECTOR(4 downto 0)
);
end controller;
architecture controller_arch of controller is
begin
process (opcode,funct)
begin
--Send empty ctrl insturctions
if (branch = '1') or (oldBranch = '1') then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "00000";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
else
case opcode is
-- SLL PADED BY SIGN EXTEND TO DO OUTPUT 17
when "000000" =>
if funct = "000000" then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "10001";
RType <= '1';
Shift <= '1';
JType <= '0';
structuralStall <= '0';
--SUB OUTPUT 1
elsif funct = "100010" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00001";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--XOR OUTPUT 10
elsif funct = "101000" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01010";
RType <= '1';
Shift <= '0';
structuralStall <= '0';
--AND OUTPUT 7
elsif funct = "100100" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00111";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--ADD OUTPUT 0
elsif funct = "100000" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00000";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--SLT OUTPUT 5
elsif funct = "101010" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00101";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--SRL PADED BY SIGN EXTEND OUTPUT 18
elsif funct = "000010" then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "10010";
RType <= '1';
Shift <= '1';
JType <= '0';
structuralStall <= '0';
--OR OUTPUT 8
elsif funct = "100101" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01000";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--NOR OUTPUT 9
elsif funct = "100111" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01001";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--JUMP REGISTER OUTPUT 25
elsif funct = "001000" then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "11001";
RType <= '1';
Shift <= '0';
JType <= '1';
structuralStall <= '0';
-- DIVIDING OUTPUT 4
elsif funct = "011010" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00100";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
-- MULT OUTPUT 3
elsif funct = "011000" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00011";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--SRA OUTPUT 18
elsif funct = "000011" then
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "10010";
RType <= '1';
JType <= '0';
structuralStall <= '0';
-- TO DO HIGH OUTPUT 14
elsif funct = "001010" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01110";
RType <= '1';
Shift <= '1';
JType <= '0';
structuralStall <= '0';
--TO DO LOW OUTPUT 15
elsif funct = "001100" then
ALU1src <= '0';
ALU2src <= '1';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01111";
RType <= '1';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
end if;
--ADDI OUTPUT 2
when "001000" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00010";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--SLTI OUTPUT 6
when "001010" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "00110";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--ANDI OUTPUT 11
when "001100" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01011";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--ORI OUTPUT 12
when "001101" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01100";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--XORI OUTPUT 13
when "001110" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "01101";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--LUI OUTPUT 16
when "001111" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "10000";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
-- LW OUTPUT 20
when "100011" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '1';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '1';
ALUOp <= "10100";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '1';
-- Store OUTPUT 21
when "101011" =>
ALU1src <= '0';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '1';
RegWrite <= '0';
MemToReg <= '1';
ALUOp <= "10101";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
-- BEQ OUTPUT 22
when "000100" =>
ALU1src <= '1';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "10110";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
--BNE OUTPUT 23
when "000101" =>
ALU1src <= '1';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "10111";
RType <= '0';
Shift <= '0';
JType <= '0';
structuralStall <= '0';
-- JUMP OUTPUT 24
when "000010" =>
ALU1src <= '1';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '0';
MemToReg <= '0';
ALUOp <= "11000";
RType <= '0';
Shift <= '0';
JType <= '1';
structuralStall <= '0';
-- JUMP AND LINK OUTPUT 26
when "000011" =>
ALU1src <= '1';
ALU2src <= '0';
MemRead <= '0';
MemWrite <= '0';
RegWrite <= '1';
MemToReg <= '0';
ALUOp <= "11010";
RType <= '0';
Shift <= '0';
JType <= '1';
structuralStall <= '0';
when others =>
end case;
end if;
end process;
end controller_arch;
|
gpl-3.0
|
6275d3951cd4f4305b2cf3a217a3947f
| 0.503997 | 2.707474 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/zero.vhd
| 1 | 836 |
library ieee;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity zero is
port (input_a : in std_logic_vector (31 downto 0);
input_b : in std_logic_vector (31 downto 0);
optype : in std_logic_vector (4 downto 0);
result: out std_logic := '0'
);
end zero;
architecture behavioral of zero is
begin
process (input_a, input_b, optype)
begin
case optype is
when "10110" => -- beq
if unsigned(input_a) = unsigned(input_b) then
result <= '1';
else
result <= '0';
end if;
when "10111" => -- bne
if unsigned(input_a) = unsigned(input_b) then
result <= '0';
else
result <= '1';
end if;
when "11000" => -- j
result <= '1';
when "11001" => -- jr
result <= '1';
when "11010" => -- jal
result <= '1';
when others =>
result <= '0';
end case;
end process;
end behavioral;
|
gpl-3.0
|
ddb90be31efca96c071722855999bae6
| 0.600478 | 2.786667 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/memory.vhd
| 1 | 2,428 |
--Adapted from Example 12-15 of Quartus Design and Synthesis handbook
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY memory IS
GENERIC(
ram_size : INTEGER := 8192;
mem_delay : time := 0.5 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC;
memread: IN STD_LOGIC;
writeToText : IN STD_LOGIC;
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END memory;
ARCHITECTURE rtl OF memory IS
TYPE MEM IS ARRAY(ram_size-1 downto 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg: INTEGER RANGE 0 to ram_size-1;
SIGNAL write_waitreq_reg: STD_LOGIC := '1';
SIGNAL read_waitreq_reg: STD_LOGIC := '1';
BEGIN
process(writeToText)
file memoryFile : text open write_mode is "memory.txt";
variable outLine : line;
variable rowLine : integer := 0;
begin
if writeToText = '1' then
while (rowLine < 8192) loop
write(outLine, ram_block(rowLine));
writeline(memoryFile, outLine);
rowLine := rowLine + 1;
end loop;
end if;
end process;
--This is the main section of the SRAM model
mem_process: PROCESS (clock)
BEGIN
--This is a cheap trick to initialize the SRAM in simulation
IF(now < 1 ps)THEN
For i in 0 to ram_size-1 LOOP
ram_block(i) <= std_logic_vector(to_unsigned(0,32));
END LOOP;
end if;
--This is the actual synthesizable SRAM block
IF (clock'event AND clock = '1') THEN
IF (memwrite = '1') THEN
ram_block(address) <= writedata;
END IF;
END IF;
END PROCESS;
process (memread)
begin
IF (memread = '1')THEN
readdata <= ram_block(address);
END IF;
end process;
--The waitrequest signal is used to vary response time in simulation
--Read and write should never happen at the same time.
waitreq_w_proc: PROCESS (memwrite)
BEGIN
IF(memwrite'event AND memwrite = '1')THEN
write_waitreq_reg <= '0' after mem_delay, '1' after mem_delay + clock_period;
END IF;
END PROCESS;
waitreq_r_proc: PROCESS (memread)
BEGIN
IF(memread'event AND memread = '1')THEN
read_waitreq_reg <= '0' after mem_delay, '1' after mem_delay + clock_period;
END IF;
END PROCESS;
waitrequest <= write_waitreq_reg and read_waitreq_reg;
END rtl;
|
gpl-3.0
|
e982da336c7f7c47286bf27d14152cc6
| 0.681631 | 3.065657 | false | false | false | false |
krabo0om/pauloBlaze
|
testbench/code_loader.vhd
| 2 | 2,663 |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity code_loader is
Port (
address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
done : out std_logic;
clk : in std_logic);
end code_loader;
architecture Behavioral of code_loader is
type instr_t is array (0 to 1023) of std_logic_vector(17 downto 0);
signal mem : instr_t;
signal instruction_o : std_logic_vector(17 downto 0);
signal clk_sim : std_logic;
signal inst_sim : std_logic_vector(17 downto 0);
signal addr_sim : std_logic_vector(11 downto 0);
begin
instruction <= instruction_o;
rdl <= '0';
read_inst : process (clk)
begin
if (rising_edge(clk)) then
if (enable = '1') then
instruction_o <= mem(to_integer(unsigned(address)));
else
instruction_o <= instruction_o;
end if;
end if;
end process;
load_mem : process
begin
done <= '0';
clk_sim <= '1';
wait for 50 ps;
clk_sim <= '0';
wait for 50 ps;
for i in 0 to 1023 loop
addr_sim <= std_logic_vector(to_unsigned(i+1, 12));
clk_sim <= '1';
wait for 50 ps;
clk_sim <= '0';
wait for 51 ps;
mem(i) <= inst_sim;
end loop;
done <= '1';
wait;
end process load_mem;
prog_mem : entity work.test_assembler generic map (
C_FAMILY => "V6",
C_RAM_SIZE_KWORDS => 1,
C_JTAG_LOADER_ENABLE => 0)
Port map (
address => addr_sim,
instruction => inst_sim,
enable => '1',
rdl => open,
clk => clk_sim);
end Behavioral;
|
apache-2.0
|
7cb7abeb16f8ee58d4c25f2ff8f8ae32
| 0.593316 | 3.332916 | false | false | false | false |
corywalker/vhdl_fft
|
cap_controller.vhd
| 3 | 4,363 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cap_controller is
generic (
N : positive := 16;
ADDRWIDTH : positive := 10;
SIZE : positive := 64;
SIZELOG : positive := 6;
INT_EXT_SEL: std_logic;
SPI_2X_CLK_DIV: positive;
DA_RESET_DELAY: positive
);
port(
CLK1: in std_logic;
start: in std_logic;
busy: out std_logic := '0';
wea : out std_logic_vector(0 DOWNTO 0);
addr : out std_logic_vector(ADDRWIDTH-1 DOWNTO 0);
dout : out std_logic_vector(N-1 DOWNTO 0);
adc_conv: out std_logic;
adc_sck: out std_logic;
adc_miso: in std_logic;
rst: in std_logic
);
end cap_controller;
architecture Behavioral of cap_controller is
signal slower_spi_clock: std_logic := '0';
signal gated_spi_clock: std_logic := '0';
signal determ_spi_sck: std_logic;
signal determ_conv: std_logic;
signal determ_spi_miso: std_logic;
signal spi_sck: std_logic;
signal conv: std_logic;
signal thebusy: std_logic;
signal spi_miso: std_logic;
signal sm_data_buf: std_logic_vector (N-1 downto 0);
signal sm_state_dbg: std_logic_vector (3 downto 0);
signal sm_valid: std_logic;
signal theaddress : integer range SIZE-1 downto 0 := 0;
signal addr_vect : std_logic_vector(ADDRWIDTH-1 DOWNTO 0);
begin
da1: entity work.determ_adc
generic map (
N => N,
DA_RESET_DELAY => DA_RESET_DELAY
)
port map (
CLK1 => CLK1,
spi_sck_i => determ_spi_sck,
conv_i => determ_conv,
spi_miso_o => determ_spi_miso
);
smux1: entity work.spi_mux
port map (
sck_a_o => determ_spi_sck,
sck_b_o => adc_sck,
sck_i => spi_sck,
conv_a_o => determ_conv,
conv_b_o => adc_conv,
conv_i => conv,
miso_a_i => determ_spi_miso,
miso_b_i => adc_miso,
miso_o => spi_miso,
-- '0' for determ_adc, '1' for external.
sel_i => INT_EXT_SEL
);
sm1: entity work.spi_master
generic map (
N => N,
SPI_2X_CLK_DIV => SPI_2X_CLK_DIV
)
port map (
sclk_i => gated_spi_clock,
pclk_i => gated_spi_clock,
rst_i => rst,
wren_i => '1',
do_o => sm_data_buf,
do_valid_o => sm_valid,
spi_sck_o => spi_sck,
spi_miso_i => spi_miso,
state_dbg_o => sm_state_dbg
);
busy <= thebusy;
-- Only write if the SPI master out is valid and we are currently capturing
wea(0) <= sm_valid and thebusy;
conv <= '0' when sm_state_dbg = "0001" else '1';
addr_vect <= std_logic_vector(to_unsigned(theaddress, addr'length));
-- gen: for i in 0 to SIZELOG-1 generate
-- addr(i) <= addr_vect(SIZELOG-i-1);
-- end generate;
addr(SIZELOG-1 downto 0) <= addr_vect(SIZELOG-1 downto 0);
addr(ADDRWIDTH-1 downto SIZELOG) <= (others=>'0');
dout <= "0" & sm_data_buf(14 downto 8) & "00000000";
process(CLK1)
variable address : integer range SIZE-1 downto 0 := 0;
variable is_busy: std_logic := '0';
variable already_stepped : std_logic := '0';
begin
if rising_edge(CLK1) then
slower_spi_clock <= not slower_spi_clock;
if is_busy = '1' then
if sm_valid = '1' and already_stepped = '0' then
already_stepped := '1';
if address = SIZE-1 then
is_busy := '0';
address := 0;
else
address := address + 1;
end if;
elsif sm_valid = '0' then
already_stepped := '0';
end if;
else
if start = '1' then
is_busy := '1';
end if;
end if;
thebusy <= is_busy;
theaddress <= address;
gated_spi_clock <= is_busy and (not slower_spi_clock);
end if;
end process;
end Behavioral;
|
mit
|
a5ae21221c47c9eebde61eac9e9e3b54
| 0.492322 | 3.678752 | false | false | false | false |
kumasento/zedboard-thesis
|
examples/2014_zynq_labs/lab3/lab3.srcs/sources_1/bd/system/ip/system_rst_processing_system7_0_100M_0/sim/system_rst_processing_system7_0_100M_0.vhd
| 1 | 5,923 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY system_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_processing_system7_0_100M_0;
ARCHITECTURE system_rst_processing_system7_0_100M_0_arch OF system_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_processing_system7_0_100M_0_arch;
|
apache-2.0
|
0d06e48fd91c6e0e434b6bab266c5c76
| 0.709438 | 3.594053 | false | false | false | false |
gustavowl/ProjetoOAC
|
Mult32bit/Multiplicador32Bit.vhd
| 1 | 16,581 |
-----------------------------------------------------------------------
-----------------------------DESLOCADOR--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador is
port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end deslocador;
architecture deslocador of deslocador is
begin
c <= a(31 downto 0) when desl = '0' else
'0' & a(31 downto 1) when lado = '0' else
a(30 downto 0) & '0';
cout <= a(30) when lado = '1' and desl = '1' else '0';
end deslocador;
-----------------------------------------------------------------------
--------------------------------MUX A----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1A is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end Mux8x1A;
architecture Mux8x1A of Mux8x1A is
component deslocador
port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
signal temp: std_logic_vector (31 downto 0);
signal tdesl, tz: std_logic;
begin
--seleciona o valor de saída baseado na escolha de entrada XYZ
--as primeiras condições são para operações em lógica booleana
--receberá o valor de A caso seja feita alguma operação algébrica
--ou deslocamento de bits
temp <= a and b when x = '0' and y = '1' and z = '0' else
a nor b when x = '0' and y = '1' and z = '1' else
a or b when x = '1' and y = '0' and z = '0' else a;
--só irá efetuar deslocamento de bits caso xyz = 101 ou 110
tdesl <= '1' when x = '1' and ( ( y = '0' and z = '1') or ( y = '1' and z = '0' ) ) else '0';
--tz armazena o lado para qual será efetuado o deslocamento
tz <= z;
desloc: deslocador port map (temp, tdesl, tz, c, cout);
end Mux8x1A;
-----------------------------------------------------------------------
--------------------------------MUX B----------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1B is
port (
a: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0)
);
end Mux8x1B;
architecture Mux8x1B of Mux8x1B is
begin
c <= "00000000000000000000000000000000" when (x = '1' or y = '1') else
a when z = '0' else not a;
end Mux8x1B;
-----------------------------------------------------------------------
--------------------------------MUX C----------------------------------
---------------------------comparador----------------------------------
--Identifica se está fazendo subtração para CIN p/ conversão em complemento de 2
library ieee;
use ieee.std_logic_1164.all;
entity Mux8x1C is
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end Mux8x1C;
architecture Mux8x1C of Mux8x1C is
begin
c <= '1' when (x = '0' and y = '0' and z = '1') else '0';-- or
-- (x = '1' and y = '1' and z = '0') else '0';
end Mux8x1C;
-----------------------------------------------------------------------
---------------------------COMPONENTE LÓGICO---------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity CompLog is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector(31 downto 0);
ib: out std_logic_vector(31 downto 0);
Cin: out std_logic; --p/ conversão em complemento de 2
Cout: out std_logic --p/ identificar overflow na multiplicação
);
end CompLog;
architecture CompLog of CompLog is
component Mux8x1A
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
component Mux8x1B
port (
a: in std_logic_vector(31 downto 0);
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic_vector(31 downto 0)
);
end component;
component Mux8x1C
port (
x: in std_logic;
y: in std_logic;
z: in std_logic;
c: out std_logic
);
end component;
begin
mux8x1a0: Mux8x1A port map (a, b, x, y, z, ia, Cout);
-- ia <= "01001001";
mux8x1b0: Mux8x1B port map (b, x, y, z, ib);
mux8x1c0: Mux8x1C port map (x, y, z, Cin);
end CompLog;
-----------------------------------------------------------------------
--------------------------SOMADOR 1 BIT--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador1bit is
port (
a: in std_logic;
b: in std_logic;
cin: in std_logic;
s: out std_logic;
cout: out std_logic
);
end somador1bit;
architecture somador1bit of somador1bit is
begin
cout <= (cin and a) or (cin and b) or (a and b);
s <= (not cin and not a and b) or (not cin and a and not b)
or (cin and not a and not b) or (cin and a and b);
end somador1bit;
-----------------------------------------------------------------------
--------------------------SOMADOR 16 BITS-------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity somador16bits is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
cin: in std_logic;
s: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end somador16bits;
architecture somador16bits of somador16bits is
component somador1bit
port (
a, b, cin: in std_logic;
s, cout: out std_logic
);
end component;
signal ta, tb, ts: std_logic_vector(31 downto 0);
signal c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16,
c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31: std_logic;
begin
ta <= a;
tb <= b;
s8b0: somador1bit port map (a(0), b(0), cin, ts(0), c0);
s8v1: somador1bit port map (a(1), b(1), c0, ts(1), c1);
s8v2: somador1bit port map (a(2), b(2), c1, ts(2), c2);
s8v3: somador1bit port map (a(3), b(3), c2, ts(3), c3);
s8v4: somador1bit port map (a(4), b(4), c3, ts(4), c4);
s8v5: somador1bit port map (a(5), b(5), c4, ts(5), c5);
s8v6: somador1bit port map (a(6), b(6), c5, ts(6), c6);
s8v7: somador1bit port map (a(7), b(7), c6, ts(7), c7);
s8b8: somador1bit port map (a(8), b(8), c7, ts(8), c8);
s8v9: somador1bit port map (a(9), b(9), c8, ts(9), c9);
s8v10: somador1bit port map (a(10), b(10), c9, ts(10), c10);
s8v11: somador1bit port map (a(11), b(11), c10, ts(11), c11);
s8v12: somador1bit port map (a(12), b(12), c11, ts(12), c12);
s8v13: somador1bit port map (a(13), b(13), c12, ts(13), c13);
s8v14: somador1bit port map (a(14), b(14), c13, ts(14), c14);
s8v15: somador1bit port map (a(15), b(15), c14, ts(15), c15);
s8v16: somador1bit port map (a(16), b(16), c15, ts(16), c16);
s8v17: somador1bit port map (a(17), b(17), c16, ts(17), c17);
s8v18: somador1bit port map (a(18), b(18), c17, ts(18), c18);
s8v19: somador1bit port map (a(19), b(19), c18, ts(19), c19);
s8v20: somador1bit port map (a(20), b(20), c19, ts(20), c20);
s8v21: somador1bit port map (a(21), b(21), c20, ts(21), c21);
s8v22: somador1bit port map (a(22), b(22), c21, ts(22), c22);
s8v23: somador1bit port map (a(23), b(23), c22, ts(23), c23);
s8v24: somador1bit port map (a(24), b(24), c23, ts(24), c24);
s8v25: somador1bit port map (a(25), b(25), c24, ts(25), c25);
s8v26: somador1bit port map (a(26), b(26), c25, ts(26), c26);
s8v27: somador1bit port map (a(27), b(27), c26, ts(27), c27);
s8v28: somador1bit port map (a(28), b(28), c27, ts(28), c28);
s8v29: somador1bit port map (a(29), b(29), c28, ts(29), c29);
s8v30: somador1bit port map (a(30), b(30), c29, ts(30), c30);
s8v31: somador1bit port map (a(31), b(31), c30, ts(31), c31);
--verifica overflow e underflow
cout <= (not a(31) and not b(31) and ts(31)) or (a(31) and b(31) and not ts(31));
s <= ts;
end somador16bits;
-----------------------------------------------------------------------
-----------------------------ULA-PO------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_po is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro: out std_logic
);
end ula_po;
architecture ula_po of ula_po is
component CompLog
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
ia: out std_logic_vector (31 downto 0);
ib: out std_logic_vector(31 downto 0);
Cin: out std_logic;
Cout: out std_logic
);
end component;
component somador16bits
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
cin: in std_logic;
s: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
signal ia, ib: std_logic_vector(31 downto 0);
signal cin, cout, cout2: std_logic;
begin
complog0: CompLog port map (a, b, x, y, z, ia, ib, cin, cout);
somador8b0: somador16bits port map (ia, ib, cin, s, cout2);
couterro <= cout or cout2;
end ula_po;
-----------------------------------------------------------------------
-----------------------------ULA-PC------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula_pc IS
port ( clk, do_op : in std_logic;
done, state: out std_logic
);
end ula_pc;
architecture ula_pc of ula_pc is
constant STDOINGOP: std_logic := '0';
constant STOPDONE: std_logic := '1';
signal st: std_logic;
begin
--espera um ciclo de clock para ter certeza que as operações
--se estabilizaram
PROCESS (clk)
BEGIN
if (clk'event and clk = '1') then
case st is
when STOPDONE =>
if (do_op = '1') then
st <= STDOINGOP;
end if;
when others =>
st <= STOPDONE;
end case;
end if;
end process;
done <= '1' when st = STOPDONE else '0';
state <= st;
end ula_pc;
-----------------------------------------------------------------------
-------------------------------ULA-------------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ula is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z, clk, do_op: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro, done, state: out std_logic
);
end ula;
architecture ula of ula is
component ula_po
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro: out std_logic
);
end component;
component ula_pc
port (
clk, do_op : in std_logic;
done, state: out std_logic
);
end component;
begin
ulapo: ula_po port map (a, b, x, y, z, s, couterro);
ulapc: ula_pc port map (clk, do_op, done, state);
end ula;
-----------------------------------------------------------------------
-----------------------------DESLOCADOR64--------------------------------
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity deslocador64 is
port (
a: in std_logic_vector(63 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end deslocador64;
architecture deslocador64 of deslocador64 is
begin
c <= a(63 downto 0) when desl = '0' else
'0' & a(63 downto 1) when lado = '0' else
a(62 downto 0) & '0';
cout <= a(62) when lado = '1' and desl = '1' else '0';
end deslocador64;
--REGISTRADOR 32 BIT
library ieee;
use ieee.std_logic_1164.all;
entity reg_paraleload32 is
port ( i: in std_logic_vector (31 downto 0);
clk, ld, rst: in std_logic; --load: 1: escrita, 0: leitura
q: out std_logic_vector (31 downto 0)
);
end;
architecture reg_paraleload32 of reg_paraleload32 is
begin
q <= "00000000000000000000000000000000" when (clk'event and clk = '1' and rst = '1') else
i when ( clk'event and clk = '1' and ld = '1' );
end reg_paraleload32;
--REGISTRADOR 64 BIT
library ieee;
use ieee.std_logic_1164.all;
entity reg_paraleload64 is
port ( i: in std_logic_vector (63 downto 0);
clk, ld, rst: in std_logic; --load: 1: escrita, 0: leitura
q: out std_logic_vector (63 downto 0)
);
end;
architecture reg_paraleload64 of reg_paraleload64 is
begin
q <= "0000000000000000000000000000000000000000000000000000000000000000" when (clk'event and clk = '1' and rst = '1') else
i when ( clk'event and clk = '1' and ld = '1' );
end reg_paraleload64;
--MULTIPLICADOR
library ieee;
use ieee.std_logic_1164.all;
entity mult32 is
port ( multiplicando, multiplicador: in std_logic_vector (31 downto 0);
clk, start: in std_logic; --load: 1: escrita, 0: leitura
produto: out std_logic_vector (63 downto 0);
done: out std_logic
);
end;
architecture mult32 of mult32 is
component reg_paraleload32 port (
i: in std_logic_vector (31 downto 0);
clk, ld, rst: in std_logic; --load: 1: escrita, 0: leitura
q: out std_logic_vector (31 downto 0)
);
end component;
component reg_paraleload64 port (
i: in std_logic_vector (63 downto 0);
clk, ld, rst: in std_logic; --load: 1: escrita, 0: leitura
q: out std_logic_vector (63 downto 0)
);
end component;
component deslocador port (
a: in std_logic_vector(31 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(31 downto 0);
cout: out std_logic
);
end component;
component deslocador64 port (
a: in std_logic_vector(63 downto 0);
desl: in std_logic; --desloca
lado: in std_logic; --0 divide 1 multiplica
c: out std_logic_vector(63 downto 0);
cout: out std_logic
);
end component;
component ula port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
x, y, z, clk, do_op: in std_logic;
s: out std_logic_vector(31 downto 0);
couterro, done, state: out std_logic
);
end component;
signal st, reset, over, cout, cout2, sum, cout3, useless1, useless2, overwriteresult: std_logic; --st[0: reset | 1: doing operation]
signal desl64out, reg64_in, reg64_out: std_logic_vector(63 downto 0);
signal desl32out, mtplcdr_desl, reg32cout, ulain_mult, ulain, ulaout: std_logic_vector(31 downto 0);
begin
PROCESS (clk)
BEGIN
if (clk'event and clk = '1') then
if (start = '1' and not(st = '1')) then
st <= '1';
--over <= '0';
elsif (st = '1' and over = '1') then
st <= '0';
end if;
end if;
END PROCESS;
reset <= '1' when st = '0' or st = 'U' else '0';
reg32: reg_paraleload32 port map (multiplicando, reset, '1', '0', ulain_mult);
reg64_in <= "0000000000000000000000000000000" & multiplicador & '0' when reset = '1'
else ulaout & reg64_out(31 downto 0) when sum = '1' else reg64_out;
overwriteresult <= '1' when over = '0' else '0';
--resetaux <= '1' when reset = '1' or ulaout = "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" else '0';
--reg64: reg_paraleload64 port map (reg64_in, clk, overwriteresult, '0', reg64_out);
--desl64: deslocador64 port map (reg64_out, '1', '0', desl64out, cout2);
desl64: deslocador64 port map (reg64_in, '1', '0', desl64out, cout2);
reg64: reg_paraleload64 port map (desl64out, clk, overwriteresult, '0', reg64_out);
ulain <= reg64_out(63 downto 32);
sum <= reg64_out(0);
alu: ula port map (ulain, ulain_mult, '0', '0', '0', clk, sum, ulaout, cout, useless1, useless2);
produto <= reg64_out;
--produto <= ulain & ulain_mult;
mtplcdr_desl <= "11111111111111111111111111111111" when reset = '1' else desl32out;
reg32c: reg_paraleload32 port map (mtplcdr_desl, clk, '1', '0', reg32cout);
desl32c: deslocador port map (reg32cout, '1', '0', desl32out, cout3);
over <= '1' when reg32cout = "00000000000000000000000000000000" else '0';
done <= over;
--done <= reset;
end mult32;
|
gpl-2.0
|
19914a11d3bf09cfe0d25c6731bcda4d
| 0.567736 | 2.898634 | false | false | false | false |
FearlessJojo/COPproject
|
project/T.vhd
| 1 | 1,351 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:22:35 11/21/2016
-- Design Name:
-- Module Name: T - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISAdder;
--use UNISAdder.VComponents.all;
entity T is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
T_in : in STD_LOGIC;
T_reg : out STD_LOGIC);
end T;
architecture Behavioral of T is
begin
process(clk, rst)
begin
if (rst = '0') then
T_reg <= '0';
else
if (clk'event and clk = '1') then
if (enable = '1') then
T_reg <= T_in;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
278e85f0b62cb80ddff9e19d94ad39c4
| 0.555144 | 3.420253 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/register_file_tb.vhd
| 1 | 2,795 |
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY register_file_tb IS
END register_file_tb;
ARCHITECTURE behav OF register_file_tb IS
COMPONENT register_file IS
GENERIC(
register_size: INTEGER := 32 --MIPS register size is 32 bit
);
PORT(
-- ************** Do we need a standard enable input ? *****************
clock: IN STD_LOGIC;
rs: IN STD_LOGIC_VECTOR (4 downto 0); -- first source register
rt: IN STD_LOGIC_VECTOR (4 downto 0); -- second source register
write_enable: IN STD_LOGIC; -- signals that rd_data may be written into rd **********Unsure if neccessary*************
rd: IN STD_LOGIC_VECTOR (4 downto 0); -- destination register
rd_data: IN STD_LOGIC_VECTOR (31 downto 0); -- destination register data
ra_data: OUT STD_LOGIC_VECTOR (31 downto 0); -- data of register a
rb_data: OUT STD_LOGIC_VECTOR (31 downto 0) -- data of register b
);
END COMPONENT;
SIGNAL clock: STD_LOGIC := '0';
CONSTANT clock_period : time := 1 ns;
SIGNAL rs: STD_LOGIC_VECTOR (4 downto 0);
SIGNAL rt: STD_LOGIC_VECTOR (4 downto 0);
SIGNAL write_enable: STD_LOGIC := '0';
SIGNAL rd: STD_LOGIC_VECTOR (4 downto 0);
SIGNAL rd_data: STD_LOGIC_VECTOR (31 downto 0);
SIGNAL ra_data: STD_LOGIC_VECTOR (31 downto 0);
SIGNAL rb_data: STD_LOGIC_VECTOR (31 downto 0);
BEGIN
-- map component to signals
rfile: register_file
PORT MAP(
clock => clock,
rs => rs,
rt => rt,
write_enable => write_enable,
rd => rd,
rd_data => rd_data,
ra_data => ra_data,
rb_data => rb_data
);
clock_process : PROCESS
BEGIN
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
END PROCESS;
test_process : PROCESS
BEGIN
wait for clock_period;
-- test 1
rs <= "00000";
rt <= "00000";
write_enable <='0';
rd <= "00001";
rd_data <= "00000000000000000000000000000000";
wait for clock_period;
-- test 2
rs <= "00000";
rt <= "00000";
write_enable <='1';
rd <= "00001";
rd_data <= "10000000000000000000000000000001";
wait for clock_period;
-- test 3: write to R0. The write should not happen.
rs <= "11111";
rt <= "11110";
write_enable <='1';
rd <= "00000";
rd_data <= "10000000000000000000000000000001";
wait for clock_period;
-- test 4
rs <= "11111";
rt <= "11110";
write_enable <='0';
rd <= "00011";
rd_data <= "10000000000000000000000000000001";
WAIT;
END PROCESS;
END behav;
|
gpl-3.0
|
54da3d4d6fc55b9d1afb07f8a96600b6
| 0.555277 | 3.865837 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/instructionFetchStage.vhd
| 1 | 3,528 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY instructionFetchStage IS
--MIGHT NEED TO MODIFY IF STAGE TO THE WHOLE CPU PIPELINE
port(
clk : in std_logic;
muxInput0 : in std_logic_vector(31 downto 0);
selectInputs : in std_logic;
four : in INTEGER;
structuralStall : IN STD_LOGIC := '0';
pcStall : IN STD_LOGIC := '0';
selectOutput : out std_logic_vector(31 downto 0);
instructionMemoryOutput : out std_logic_vector(31 downto 0)
);
END instructionFetchStage;
architecture instructionFetchStage_arch of instructionFetchStage is
--INSTRUCTION MEMORY
component instructionMemory IS
GENERIC(
-- might need to change it
ram_size : INTEGER := 1024;
mem_delay : time := 1 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC;
memread: IN STD_LOGIC;
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END component;
--PC
component pc is
port(clk : in std_logic;
reset : in std_logic;
counterOutput : out std_logic_vector(31 downto 0);
counterInput : in std_logic_vector(31 downto 0)
);
end component;
--MUX
component mux is
port(
input0 : in std_logic_vector(31 downto 0);
input1 : in std_logic_vector(31 downto 0);
selectInput : in std_logic;
selectOutput : out std_logic_vector(31 downto 0)
);
end component;
--ADDER
component adder is
port(
plusFour : in integer;
counterOutput : in std_logic_vector(31 downto 0);
adderOutput : out std_logic_vector(31 downto 0)
);
end component;
-- SET SIGNALS
signal rst : std_logic := '0';
signal writedata: std_logic_vector(31 downto 0);
signal address: INTEGER RANGE 0 TO 1024-1;
signal memwrite: STD_LOGIC := '0';
signal memread: STD_LOGIC := '1';
signal readdata: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal waitrequest: STD_LOGIC;
signal pcOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal internal_selectOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal addOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
--SIGNAL FOR STALLS
signal stallValue : STD_LOGIC_VECTOR(31 DOWNTO 0) := "00000000000000000000000000100000";
signal memoryValue : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal pcInput : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
selectOutput <= internal_selectOutput;
address <= to_integer(unsigned(addOutput(9 downto 0)))/4;
pcCounter : pc
port map(
clk => clk,
reset => rst,
counterOutput => pcOutput,
counterInput => pcInput
);
add : adder
port map(
plusFour => four,
counterOutput => pcOutput,
adderOutput => addOutput
);
fetchMux : mux
port map(
input0 => addOutput,
input1 => muxInput0,
selectInput => selectInputs,
selectOutput => internal_selectOutput
);
structuralMux : mux
port map (
input0 => memoryValue,
input1 => stallValue,
selectInput => structuralStall,
selectOutput => instructionMemoryOutput
);
pcMux : mux
port map (
input0 => internal_selectOutput,
input1 => pcOutput,
selectInput => pcStall,
selectOutput => pcInput
);
iMem : instructionMemory
GENERIC MAP(
ram_size => 1024
)
PORT MAP(
clk,
writedata,
address,
memwrite,
memread,
memoryValue,
waitrequest
);
end instructionFetchStage_arch;
|
gpl-3.0
|
db5d58b514c86243d170e2634a67d719
| 0.66695 | 3.55287 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/instructionFetchStage_tb.vhd
| 1 | 1,614 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY instructionFetchStage_tb IS
END instructionFetchStage_tb;
architecture instructionFetchStage_tb_arch of instructionFetchStage_tb is
component instructionFetchStage IS
port(
clk : in std_logic;
muxInput0 : in std_logic_vector(31 downto 0);
selectInputs : in std_logic;
four : in INTEGER;
selectOutput : out std_logic_vector(31 downto 0);
instructionMemoryOutput : out std_logic_vector(31 downto 0)
);
end component;
constant clk_period : time := 1 ns;
signal clk : std_logic := '0';
signal muxValue : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal selection : STD_LOGIC;
signal intFour : INTEGER := 4;
signal muxOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal memoryOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
fetchStage : instructionFetchStage
port map(
clk => clk,
muxInput0 => muxValue,
selectInputs => selection,
four => intFour,
selectOutput => muxOutput,
instructionMemoryOutput => memoryOutput
);
clk_process : process
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
BEGIN
muxValue <= "00000000000000000000000000000000";
selection <= '0';
wait for clk_period;
report "STARTING SIMULATION \n";
selection <= '1';
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait for clk_period;
wait;
end process;
end instructionFetchStage_tb_arch;
|
gpl-3.0
|
50511e891bfcd353bb064ee9d3e5aac0
| 0.677819 | 3.618834 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/mux_tb.vhd
| 1 | 1,340 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY mux_tb IS
END mux_tb;
architecture mux_tb_arch of mux_tb is
component mux is
port(clk : in std_logic;
input0 : in std_logic_vector(31 downto 0);
input1 : in std_logic_vector(31 downto 0);
selectInput : in std_logic;
selectOutput : out std_logic_vector(31 downto 0)
);
end component;
constant clk_period : time := 1 ns;
signal clk : std_logic := '0';
signal muxValue1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal muxValue2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal selection : STD_LOGIC;
signal muxOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
muxFetch : mux
port map(
clk => clk,
input2 => muxValue2,
input1 => muxValue1,
selectInput => selection,
selectOutput => muxOutput
);
clk_process : process
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
BEGIN
wait for clk_period;
report "STARTING SIMULATION \n";
muxValue1 <= "11111111111111111111111111111111";
muxValue2 <= "00000000000000000000000000000000";
selection <= '1';
wait for clk_period;
selection <= '0';
wait;
end process;
end mux_tb_arch;
|
gpl-3.0
|
05506afebde00ee7fe66958e8186d70b
| 0.647761 | 3.333333 | false | false | false | false |
FearlessJojo/COPproject
|
project/PCReg.vhd
| 1 | 1,486 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:35 11/20/2016
-- Design Name:
-- Module Name: PCReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PCReg is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
NPC : in STD_LOGIC_VECTOR (15 downto 0);
PC : BUFFER STD_LOGIC_VECTOR (15 downto 0);
MEM_RAM2: in STD_LOGIC;
l : out STD_LOGIC_VECTOR (15 downto 0));
end PCReg;
architecture Behavioral of PCReg is
begin
L <= pc;
process(clk, rst)
begin
if (rst = '0') then
PC <= "1111111111111111";
else
if (clk'event and clk = '1') then
if (enable = '1')and(MEM_RAM2 = '0') then
PC <= NPC;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
17ac4a2ac4aea596bfb23458ef9b9613
| 0.578735 | 3.513002 | false | false | false | false |
malkolmalburquenque/PipelinedProcessor
|
VHDL/memory_tb.vhd
| 1 | 2,368 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY memory_tb IS
END memory_tb;
ARCHITECTURE behaviour OF memory_tb IS
--Declare the component that you are testing:
COMPONENT memory IS
GENERIC(
ram_size : INTEGER := 32768;
mem_delay : time := 10 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC := '0';
memread: IN STD_LOGIC := '0';
readdata: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END COMPONENT;
--all the input signals with initial values
signal clk : std_logic := '0';
constant clk_period : time := 1 ns;
signal writedata: std_logic_vector(7 downto 0);
signal address: INTEGER RANGE 0 TO 32768-1;
signal memwrite: STD_LOGIC := '0';
signal memread: STD_LOGIC := '0';
signal readdata: STD_LOGIC_VECTOR (7 DOWNTO 0);
signal waitrequest: STD_LOGIC;
BEGIN
--dut => Device Under Test
dut: memory GENERIC MAP(
ram_size => 15
)
PORT MAP(
clk,
writedata,
address,
memwrite,
memread,
readdata,
waitrequest
);
clk_process : process
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
BEGIN
wait for clk_period;
address <= 14;
writedata <= X"12";
memwrite <= '1';
--waits are NOT synthesizable and should not be used in a hardware design
wait until rising_edge(waitrequest);
memwrite <= '0';
memread <= '1';
wait until rising_edge(waitrequest);
assert readdata = x"12" report "write unsuccessful" severity error;
memread <= '0';
wait for clk_period;
address <= 12;memread <= '1';
wait until rising_edge(waitrequest);
assert readdata = x"0c" report "write unsuccessful" severity error;
memread <= '0';
wait;
END PROCESS;
END;
|
gpl-3.0
|
864bc8b807ac5a5b1a5795fd48031437
| 0.532095 | 4.393321 | false | false | false | false |
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