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diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Counter9999Tb.vhd
| 1 | 884 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.std_LOGIC_1164.all;
entity Counter9999Tb is
end Counter9999Tb;
-- Teste unitário para contador de 0 a 9999.
architecture Stimulus of Counter9999Tb is
signal s_clk, s_reset, s_enable : std_logic;
signal s_count0, s_count1, s_count2, s_count3 : std_logic_vector(3 downto 0);
begin
counter_str: entity work.Counter9999(Behavioral)
port map(clk => s_clk,
reset => s_reset,
enable => s_enable,
count0 => s_count0,
count1 => s_count1,
count2 => s_count2,
count3 => s_count3);
clk_proc: process
begin
s_clk <= '0';
wait for 1 ns;
s_clk <= '1';
wait for 1 ns;
end process;
stim_proc: process
begin
s_enable <= '1';
s_reset <= '0';
wait for 100 ns;
end process;
end Stimulus;
|
gpl-2.0
|
ff0252f1ee88a5411889596764068087
| 0.621744 | 2.812102 | false | false | false | false |
JABoye47x/sandbox
|
VHDL/lcd_control.vhd
| 1 | 30,803 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lcd_control is
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
lap : in STD_LOGIC;
mode : in STD_LOGIC;
hundredths : in std_logic_vector (3 downto 0);
tenths : in std_logic_vector (3 downto 0);
ones : in std_logic_vector (3 downto 0);
tens : in std_logic_vector (3 downto 0);
minutes : in std_logic_vector (3 downto 0);
control : out std_logic_vector (2 downto 0); -- LCD_RS, LCD_RW, LCD_E
sf_d: out STD_LOGIC_VECTOR (7 downto 4)
); --LCD data bus
end lcd_control;
architecture lcd_control_arch of lcd_control is
type state_type is (waiting, init1,init2,init3,init4,init5,init6,init7,init8,
word1,word2,word3,word4,word5,alt_word5,word6,word7,word8,word9,word10,
time_display1,time_display2,time_display3,time_display4,time_display5,
time_display6,time_display7,time_display8,time_display9,time_display10,
time_display11,time_display12,time_display13,time_display14,
lap_display1,lap_display2,lap_display3,lap_display4,lap_display5,
lap_display6,lap_display7,lap_display8,lap_display9,lap_display10,
lap_display11,lap_display12,lap_display13,lap_display14,
donestate);
signal state,next_state : state_type;
signal mode_state,next_mode_state : std_logic := '0';
signal sf_d_temp : std_logic_vector (7 downto 0) := "00000000";
signal sf_d_short : std_logic_vector (7 downto 4) := "0000";
signal lap_min,lap_tens,lap_ones,lap_tenths,lap_hundredths : std_logic_vector (3 downto 0) := "0000";
signal count, count_temp : integer := 0;
signal state_flag : std_logic := '0';
signal lap_flag, set_lap_flag : std_logic := '1';
signal set_timer_flag, timer_flag : std_logic := '0';
signal set_clock_flag, clock_flag : std_logic := '1';
signal dual : std_logic := '0'; -- set to 1 if want to do clock out dual nibbles on the lcd DB
signal control_base : std_logic_vector (2 downto 0) := "000"; -- LCD_RS, LCD_RW, LCD_E
constant TIME1 : integer := 750000;
constant TIMED1 : integer := 500;
constant TIMED2 : integer := 1000;
constant TIMED3 : integer := 2000;
constant TIMED4 : integer := 3000;
constant TIME2 : integer := 10000;
constant TIME3 : integer := 210000;
constant TIME4 : integer := 420000;
begin
run : process (clk,state,count,minutes,tens,ones,tenths,hundredths,lap_flag,lap_min,lap_tens,
lap_ones,lap_tenths,lap_hundredths,timer_flag,clock_flag,mode,dual,sf_d_temp,sf_d_short,control_base) is
begin
set_lap_flag <= lap_flag;
set_timer_flag <= timer_flag;
set_clock_flag <= clock_flag;
dual <= '1';
control_base <= "100"; -- default control is RS=1
case state is
-- Initialization Starts --------------------------------
when waiting =>
sf_d_temp <= "00000000";
control <= "000"; -- clear
dual <= '0';
if (count >= TIME1) then
next_state <= init1; state_flag <= '1';
else next_state <= waiting; state_flag <= '0';
end if;
when init1 =>
sf_d_temp <= "00110000"; --reset
dual <= '0';
if (count = TIME4) then
next_state <= init2; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init1; control <= "000"; state_flag <= '0';
else next_state <= init1; control <= "001"; state_flag <= '0';
end if;
when init2 =>
sf_d_temp <= "00110000"; --reset
dual <= '0';
if (count = TIME4) then
next_state <= init3; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init2; control <= "000"; state_flag <= '0';
else next_state <= init2; control <= "001"; state_flag <= '0';
end if;
when init3 =>
sf_d_temp <= "00110000"; --reset
dual <= '0';
if (count = TIME4) then
next_state <= init4; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init3; control <= "000"; state_flag <= '0';
else next_state <= init3; control <= "001"; state_flag <= '0';
end if;
when init4 =>
sf_d_temp <= "00101100"; -- set 4bit interface, 2 lines, 5*10
control_base <= "000";
if (count = TIME3) then
next_state <= init5; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init4; control <= "000"; state_flag <= '0';
else next_state <= init4; control <= "001"; state_flag <= '0';
end if;
when init5 =>
sf_d_temp <= "00001000"; -- display off
control_base <= "000";
if (count = TIME3) then
next_state <= init6; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init5; control <= "000"; state_flag <= '0';
else next_state <= init5; control <= "001"; state_flag <= '0';
end if;
when init6 =>
sf_d_temp <= "00000001"; --Clear Display
control_base <= "000";
set_timer_flag <= '0'; set_clock_flag <= '0'; --reset display flags
if (count = TIME3) then
next_state <= init7; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init6; control <= "000"; state_flag <= '0';
else next_state <= init6; control <= "001"; state_flag <= '0';
end if;
when init7 =>
sf_d_temp <= "00000110"; --Entry Mode set ID=1, S=0
control_base <= "000";
if (count = TIME3) then
next_state <= init8; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init7; control <= "000"; state_flag <= '0';
else next_state <= init7; control <= "001"; state_flag <= '0';
end if;
when init8 =>
sf_d_temp <= "00001100"; --Display: disp on, cursor off, blink off
control_base <= "000";
if (count = TIME3) then
next_state <= word1; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init8; control <= "000"; state_flag <= '0';
else next_state <= init8; control <= "001"; state_flag <= '0';
end if;
-- Initialization Ends -----------------------------------
-------------------------Write out 'Time:'-----------------------
when word1 =>
sf_d_temp <= "01010100"; -- T
if (count = TIME3) then
next_state <= word2; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word1; control <= "100"; state_flag <= '0';
else next_state <= word1; control <= "101"; state_flag <= '0';
end if;
when word2 =>
sf_d_temp <= "01101001"; -- i
if (count = TIME3) then
next_state <= word3; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word2; control <= "100"; state_flag <= '0';
else next_state <= word2; control <= "101"; state_flag <= '0';
end if;
when word3 =>
sf_d_temp <= "01101101"; -- m
if (count = TIME3) then
next_state <= word4; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word3; control <= "100"; state_flag <= '0';
else next_state <= word3; control <= "101"; state_flag <= '0';
end if;
when word4 =>
sf_d_temp <= "01100101"; -- e
if (count = TIME3) then
if (mode = '1') then -- Clock mode
next_state <= word5; control <= "101"; state_flag <= '1';
else -- Timer Mode
next_state <= alt_word5; control <= "101"; state_flag <= '1';
end if;
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word4; control <= "100"; state_flag <= '0';
else next_state <= word4; control <= "101"; state_flag <= '0';
end if;
when alt_word5 =>
sf_d_temp <= "01110010"; -- r written if in timer mode
if (count = TIME3) then
next_state <= time_display1; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= alt_word5; control <= "100"; state_flag <= '0';
else next_state <= alt_word5; control <= "101"; state_flag <= '0';
end if;
when word5 =>
sf_d_temp <= "00111010"; -- [colon]
if (count = TIME3) then
next_state <= word6; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word5; control <= "100"; state_flag <= '0';
else next_state <= word5; control <= "101"; state_flag <= '0';
end if;
-------------------------Write out 'Lap:'-----------------------
when word6 =>
sf_d_temp <= "11000000"; -- Set Address hx40
control_base <= "000";
if (count = TIME3) then
next_state <= word7; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word6; control <= "000"; state_flag <= '0';
else next_state <= word6; control <= "001"; state_flag <= '0';
end if;
when word7 =>
sf_d_temp <= "01001100"; -- L
if (count = TIME3) then
next_state <= word8; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word7; control <= "100"; state_flag <= '0';
else next_state <= word7; control <= "101"; state_flag <= '0';
end if;
when word8 =>
sf_d_temp <= "01100001"; -- a
if (count = TIME3) then
next_state <= word9; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word8; control <= "100"; state_flag <= '0';
else next_state <= word8; control <= "101"; state_flag <= '0';
end if;
when word9 =>
sf_d_temp <= "01110000"; -- p
if (count = TIME3) then
next_state <= word10; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word9; control <= "100"; state_flag <= '0';
else next_state <= word9; control <= "101"; state_flag <= '0';
end if;
when word10 =>
sf_d_temp <= "00111010"; -- [colon]
if (count = TIME3) then
next_state <= time_display1; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word10; control <= "100"; state_flag <= '0';
else next_state <= word10; control <= "101"; state_flag <= '0';
end if;
----------------------- Time Display--------------------------------------
when time_display1 =>
sf_d_temp <= "10000110"; -- Set Address hx06
control_base <= "000";
if (count = TIME3) then
next_state <= time_display2; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display1; control <= "000"; state_flag <= '0';
else next_state <= time_display1; control <= "001"; state_flag <= '0';
end if;
when time_display2=> -- Display minute digit
case minutes is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= time_display3; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display2; control <= "100"; state_flag <= '0';
else next_state <= time_display2; control <= "101"; state_flag <= '0';
end if;
when time_display3 =>
sf_d_temp <= "10000111"; -- Set Address hx07
control_base <= "000";
if (count = TIME3) then
next_state <= time_display4; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display3; control <= "000"; state_flag <= '0';
else next_state <= time_display3; control <= "001"; state_flag <= '0';
end if;
when time_display4 =>
sf_d_temp <= "00111010"; -- [colon]
if (count = TIME3) then
next_state <= time_display5; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display4; control <= "100"; state_flag <= '0';
else next_state <= time_display4; control <= "101"; state_flag <= '0';
end if;
when time_display5 =>
sf_d_temp <= "10001000"; -- Set Address hx08
control_base <= "000";
if (count = TIME3) then
next_state <= time_display6; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display5; control <= "000"; state_flag <= '0';
else next_state <= time_display5; control <= "001"; state_flag <= '0';
end if;
when time_display6=> -- Display tens of seconds digit
case tens is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= time_display7; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display6; control <= "100"; state_flag <= '0';
else next_state <= time_display6; control <= "101"; state_flag <= '0';
end if;
when time_display7 =>
sf_d_temp <= "10001001"; -- Set Address hx09
control_base <= "000";
if (count = TIME3) then
next_state <= time_display8; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display7; control <= "000"; state_flag <= '0';
else next_state <= time_display7; control <= "001"; state_flag <= '0';
end if;
when time_display8 => -- Display seconds digit
case ones is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= time_display9; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display8; control <= "100"; state_flag <= '0';
else next_state <= time_display8; control <= "101"; state_flag <= '0';
end if;
when time_display9 =>
sf_d_temp <= "10001010"; -- Set Address hx0A
control_base <= "000";
if (count = TIME3) then
next_state <= time_display10; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display9; control <= "000"; state_flag <= '0';
else next_state <= time_display9; control <= "001"; state_flag <= '0';
end if;
when time_display10 =>
sf_d_temp <= "00111010"; -- [colon]
if (count = TIME3) then
next_state <= time_display11; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display10; control <= "100"; state_flag <= '0';
else next_state <= time_display10; control <= "101"; state_flag <= '0';
end if;
when time_display11 =>
sf_d_temp <= "10001011"; -- Set Address hx0B
control_base <= "000";
if (count = TIME3) then
next_state <= time_display12; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display11; control <= "000"; state_flag <= '0';
else next_state <= time_display11; control <= "001"; state_flag <= '0';
end if;
when time_display12 => -- Display tenths of second digit
case tenths is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= time_display13; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display12; control <= "100"; state_flag <= '0';
else next_state <= time_display12; control <= "101"; state_flag <= '0';
end if;
when time_display13 =>
sf_d_temp <= "10001100"; -- Set Address hx0C
control_base <= "000";
if (count = TIME3) then
next_state <= time_display14; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display13; control <= "000"; state_flag <= '0';
else next_state <= time_display13; control <= "001"; state_flag <= '0';
end if;
when time_display14 => -- Display hundredths of second digit
case hundredths is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
if ((mode = '1') AND (lap_flag = '1')) then -- Clock mode lap_flag triggered
next_state <= lap_display1; control <= "101"; state_flag <= '1';
elsif ((mode = '1') AND (lap_flag = '0')) then -- Clock mode
if (clock_flag ='1') then
next_state <= init6; control <= "101"; state_flag <= '1'; set_clock_flag <= '0';
else next_state <= lap_display1; control <= "101"; state_flag <= '1';
end if;
elsif (mode = '0') then -- timer mode
if (timer_flag ='1') then
next_state <= init6; control <= "101"; state_flag <= '1'; set_timer_flag <= '0';
else next_state <= time_display1; control <= "101"; state_flag <= '1';
end if;
else
next_state <= time_display1; control <= "101"; state_flag <= '1';
end if;
elsif (count > TIME2 AND count <= TIME3) then
next_state <= time_display14; control <= "100"; state_flag <= '0';
else next_state <= time_display14; control <= "101"; state_flag <= '0';
end if;
----------------------- Lap Time Display--------------------------------------
when lap_display1 =>
sf_d_temp <= "11000110"; -- Set Address hx46
control_base <= "000";
if (count = TIME3) then
next_state <= lap_display2; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display1; control <= "000"; state_flag <= '0';
else next_state <= lap_display1; control <= "001"; state_flag <= '0';
end if;
when lap_display2=> -- Display minute digit
case lap_min is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= lap_display3; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display2; control <= "100"; state_flag <= '0';
else next_state <= lap_display2; control <= "101"; state_flag <= '0';
end if;
when lap_display3 =>
sf_d_temp <= "11000111"; -- Set Address hx47
control_base <= "000";
if (count = TIME3) then
next_state <= lap_display4; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display3; control <= "000"; state_flag <= '0';
else next_state <= lap_display3; control <= "001"; state_flag <= '0';
end if;
when lap_display4 =>
sf_d_temp <= "00111010"; -- [colon]
if (count = TIME3) then
next_state <= lap_display5; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display4; control <= "100"; state_flag <= '0';
else next_state <= lap_display4; control <= "101"; state_flag <= '0';
end if;
when lap_display5 =>
sf_d_temp <= "11001000"; -- Set Address hx48
control_base <= "000";
if (count = TIME3) then
next_state <= lap_display6; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display5; control <= "000"; state_flag <= '0';
else next_state <= lap_display5; control <= "001"; state_flag <= '0';
end if;
when lap_display6=> -- Display tens of seconds digit
case lap_tens is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= lap_display7; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display6; control <= "100"; state_flag <= '0';
else next_state <= lap_display6; control <= "101"; state_flag <= '0';
end if;
when lap_display7 =>
sf_d_temp <= "11001001"; -- Set Address hx49
control_base <= "000";
if (count = TIME3) then
next_state <= lap_display8; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display7; control <= "000"; state_flag <= '0';
else next_state <= lap_display7; control <= "001"; state_flag <= '0';
end if;
when lap_display8 => -- Display seconds digit
case lap_ones is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= lap_display9; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display8; control <= "100"; state_flag <= '0';
else next_state <= lap_display8; control <= "101"; state_flag <= '0';
end if;
when lap_display9 =>
sf_d_temp <= "11001010"; -- Set Address hx4A
control_base <= "000";
if (count = TIME3) then
next_state <= lap_display10; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display9; control <= "000"; state_flag <= '0';
else next_state <= lap_display9; control <= "001"; state_flag <= '0';
end if;
when lap_display10 =>
sf_d_temp <= "00111010"; -- [colon]
if (count = TIME3) then
next_state <= lap_display11; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display10; control <= "100"; state_flag <= '0';
else next_state <= lap_display10; control <= "101"; state_flag <= '0';
end if;
when lap_display11 =>
sf_d_temp <= "11001011"; -- Set Address hx4B
control_base <= "000";
if (count = TIME3) then
next_state <= lap_display12; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display11; control <= "000"; state_flag <= '0';
else next_state <= lap_display11; control <= "001"; state_flag <= '0';
end if;
when lap_display12 => -- Display tenths of second digit
case lap_tenths is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= lap_display13; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display12; control <= "100"; state_flag <= '0';
else next_state <= lap_display12; control <= "101"; state_flag <= '0';
end if;
when lap_display13 =>
sf_d_temp <= "11001100"; -- Set Address hx4C
control_base <= "000";
if (count = TIME3) then
next_state <= lap_display14; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display13; control <= "000"; state_flag <= '0';
else next_state <= lap_display13; control <= "001"; state_flag <= '0';
end if;
when lap_display14 => -- Display hundredths of second digit
case lap_hundredths is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when others => sf_d_temp <= "00101101"; --[-]
end case;
if (count = TIME3) then
next_state <= time_display1; control <= "101"; state_flag <= '1'; set_lap_flag <= '0';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= lap_display14; control <= "100"; state_flag <= '0';
else next_state <= lap_display14; control <= "101"; state_flag <= '0';
end if;
when donestate =>
control <= "100";
sf_d_temp <= "00000000";
if (count = TIME3) then
next_state <= donestate; state_flag <= '1';
else next_state <= donestate; state_flag <= '0';
end if;
end case;
-- if dual mode, then strobe out the high nibble before setting to low nibble, but if not dual, then just put out the high nibble
if (dual = '1') then
if (count <= timeD1) then
sf_d_short <= sf_d_temp(7 downto 4); control<= control_base or "001";
elsif (count > timeD1 and count <= timeD2) then
sf_d_short <= sf_d_temp(7 downto 4); control<= control_base;
elsif (count > timeD2 and count <= timeD3) then
sf_d_short <= sf_d_temp(7 downto 4); control<= control_base or "001";
elsif (count > timeD3 and count <= timeD4) then
sf_d_short <= sf_d_temp(7 downto 4); control<= control_base or "001";
else
sf_d_short <= sf_d_temp(3 downto 0);
end if;
else
sf_d_short <= sf_d_temp(7 downto 4);
end if;
end process run;
lap_time : process (rst, clk, count, lap) is
begin
if (rising_edge(clk)) then
if ((rst = '1') OR (Mode = '0')) then
lap_flag <= '0';
lap_min <= "0000";
lap_tens <= "0000";
lap_ones <= "0000";
lap_tenths <= "0000";
lap_hundredths <= "0000";
elsif ((lap = '1') AND (mode = '1')) then
lap_flag <= '1';
lap_min <= minutes;
lap_tens <= tens;
lap_ones <= ones;
lap_tenths <= tenths;
lap_hundredths <= hundredths;
else
lap_min <= lap_min;
lap_tens <=lap_tens;
lap_ones <= lap_ones;
lap_tenths <= lap_tenths;
lap_hundredths <= lap_hundredths;
lap_flag <= set_lap_flag;
end if;
end if;
end process lap_time;
mode_set : process (rst, clk, mode) is
begin
if (rising_edge(clk)) then
if (rst = '1') then
timer_flag <= '0';
next_mode_state <= '0';
clock_flag <= '0';
elsif (mode_state = '1') then
if (mode = '1') then
next_mode_state <= '1'; clock_flag <= set_clock_flag;
else next_mode_state <= '0'; timer_flag <= '1';
end if;
elsif (mode_state = '0') then
if (mode = '0') then
next_mode_state <= '0'; timer_flag <= set_timer_flag;
else next_mode_state <= '1'; clock_flag <= '1';
end if;
end if;
end if;
end process mode_set;
timing : process (rst, clk, count) is
begin
if (rising_edge(clk)) then
sf_d <= sf_d_short;
count <= count_temp;
if (rst = '1') then
state <= waiting;
mode_state <= '0';
count_temp <= 0;
elsif (state_flag = '1') then
state <= next_state;
mode_state <= next_mode_state;
count_temp <= 0;
else
state <= next_state;
mode_state <= next_mode_state;
count_temp <= count_temp + 1;
end if;
end if;
end process timing;
end lcd_control_arch;
|
unlicense
|
8eb10c2b519ce1578c87f7d50369a89f
| 0.558127 | 2.957277 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/Cozinha/Cozinha_Tb.vhd
| 1 | 741 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Cozinha_Tb is
end Cozinha_Tb;
architecture Stimulus of CozinhaFSM is
signal s_bs, s_bc, s_c, s_s, s_clk, s_u, s_d : std_logic;
begin
uut: entity CozinhaFSM(Behavioral)
port map(BS =>s_bs,
BC =>s_bc,
C =>s_c,
S =>s_s,
clk=>s_clk,
U =>s_u,
D =>s_d);
clk_proc:process
begin
s_clk <= '1';
wait for 20 ns;
s_clk <= '0';
wait for 20 ns;
end process;
stim_proc:process
begin
s_bs <= '0';
s_bc <= '0';
s_c <= '0';
s_S <= '0';
wait for 50 ns;
s_bs <= '1';
s_s <= '1';
wait for 50 ns;
s_bs <= '0';
s_s <= '0';
wait for 50 ns;
s_bc <= '1';
s_c <= '1';
wait for 50 ns;
end process;
end Stimulus;
|
gpl-2.0
|
5d570b3d9725f9da01e77f7b049dd067
| 0.511471 | 2.192308 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/with screen/MIPSconPantallaME/divisor2.vhd
| 1 | 2,027 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:52:22 01/11/2013
-- Design Name:
-- Module Name: divisor2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
entity divisor2 is
port (
reset: in STD_LOGIC;
clk: in STD_LOGIC; -- reloj de entrada de la entity superior
reloj: out STD_LOGIC; -- reloj que se utiliza en los process del programa principal
velocidad0: in std_logic;
velocidad1: in std_logic
);
end divisor2;
architecture divisor_arch of divisor2 is
SIGNAL cuenta: std_logic_vector(24 downto 0);
SIGNAL clk_aux: std_logic;
begin
reloj<=clk_aux;
contador:
PROCESS(reset, clk)
BEGIN
IF (reset='1') THEN
cuenta<= (OTHERS=>'0');
ELSIF(clk'EVENT AND clk='1') THEN
if velocidad0='0' and velocidad1='0' then
IF (cuenta="1111111111111111111111111") THEN
clk_aux <= not clk_aux;
cuenta<= (OTHERS=>'0');
ELSE
cuenta <= cuenta+'1';
END IF;
elsif velocidad0='1' and velocidad1='0' then
IF (cuenta="0111111111111111111111111") THEN
clk_aux <= not clk_aux;
cuenta<= (OTHERS=>'0');
ELSE
cuenta <= cuenta+'1';
END IF;
elsif velocidad0='0' and velocidad1='1' then
IF (cuenta="0011111111111111111111111") THEN
clk_aux <= not clk_aux;
cuenta<= (OTHERS=>'0');
ELSE
cuenta <= cuenta+'1';
END IF;
else
IF (cuenta="0001111111111111111111111") THEN
clk_aux <= not clk_aux;
cuenta<= (OTHERS=>'0');
ELSE
cuenta <= cuenta+'1';
END IF;
end if;
END IF;
END PROCESS contador;
end divisor_arch;
|
gpl-2.0
|
3304e77c9a7bd80e928e2fd4df9aa69b
| 0.550074 | 3.685455 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Bin7SegDecoder.vhd
| 1 | 1,228 |
-- Projeto MasterMind
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port( binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0);
ledOut : out std_logic_vector(3 downto 0);
enable : in std_logic);
end Bin7SegDecoder;
-- Descodificador de BCD para decimal fornecido num guião com algumas alterações.
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111111" when enable='0' else
"1111001" when binInput="0001" else --1
"0100100" when binInput="0010" else --2
"0110000" when binInput="0011" else --3
"0011001" when binInput="0100" else --4
"0010010" when binInput="0101" else --5
"0000010" when binInput="0110" else --6
"1111000" when binInput="0111" else --7
"0000000" when binInput="1000" else --8
"0010000" when binInput="1001" else --9
"0001000" when binInput="1010" else --A
"0000011" when binInput="1011" else --B
"1000110" when binInput="1100" else --C
"0100001" when binInput="1101" else --D
"0000110" when binInput="1110" else --E
"1111111" when binInput="1111" else -- Nulo
"1000000"; --0
ledOut <= binInput;
end Behavioral;
|
gpl-2.0
|
35032e2110bedf31ea1fa1ffc9ae24e4
| 0.65551 | 3.365385 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/Bin7SegDecoder.vhd
| 2 | 1,114 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port( binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0);
ledOut : out std_logic_vector(3 downto 0);
enable : in std_logic);
end Bin7SegDecoder;
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111111" when enable='0' else
"1111001" when binInput="0001" else --1
"0100100" when binInput="0010" else --2
"0110000" when binInput="0011" else --3
"0011001" when binInput="0100" else --4
"0010010" when binInput="0101" else --5
"0000010" when binInput="0110" else --6
"1111000" when binInput="0111" else --7
"0000000" when binInput="1000" else --8
"0010000" when binInput="1001" else --9
"0001000" when binInput="1010" else --A
"0000011" when binInput="1011" else --B
"1000110" when binInput="1100" else --C
"0100001" when binInput="1101" else --D
"0000110" when binInput="1110" else --E
"0001110" when binInput="1111" else --F
"1000000"; --0
ledOut <= binInput;
end Behavioral;
|
gpl-2.0
|
e53ff8f00a61852f9f3f764dcccfd073
| 0.642729 | 3.315476 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
VGA-PS2_Cursor/vgacomp.vhd
| 1 | 5,650 |
------------------------------------------
-- Module Name: vgacomp - behavioral --
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.ALL;
use work.vga_mouse_pkg.all;
entity vgacomp is
port (
clk : in std_logic;
clk_25 : in std_logic;
clk_40 : in std_logic;
rst : in std_logic;
resolution : in std_logic;
click : in std_logic;
bgsw : in std_logic_vector(2 downto 0);
xpos : in std_logic_vector(9 downto 0);
ypos : in std_logic_vector(9 downto 0);
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 1)
);
end vgacomp;
architecture behavioral of vgacomp is
signal bitBlank800_60 : std_logic;
signal bitHS_800_60 : std_logic;
signal bitHS_640_60 : std_logic;
signal bitVS_640_60 : std_logic;
signal bitBlank640_60 : std_logic;
signal bitVS_800_60 : std_logic;
signal vecHcount_640_60 : std_logic_vector(10 downto 0);
signal vecVcount_640_60 : std_logic_vector(10 downto 0);
signal vecHcount_800_60 : std_logic_vector(10 downto 0);
signal vecVcount_800_60 : std_logic_vector(10 downto 0);
signal red_in : std_logic_vector(2 downto 0) := "000";
signal green_in : std_logic_vector(2 downto 0) := "000";
signal blue_in : std_logic_vector(2 downto 1) := "00";
signal red_25 : std_logic_vector(2 downto 0) := "000";
signal green_25 : std_logic_vector(2 downto 0) := "000";
signal blue_25 : std_logic_vector(2 downto 1) := "00";
signal red_40 : std_logic_vector(2 downto 0) := "000";
signal green_40 : std_logic_vector(2 downto 0) := "000";
signal blue_40 : std_logic_vector(2 downto 1) := "00";
begin
process(bgsw)
begin
case bgsw is
when "000" =>
red_in <= "000";
green_in <= "000";
blue_in <= "00";
when "001" =>
red_in <= "000";
green_in <= "000";
blue_in <= "01";
when "010" =>
red_in <= "000";
green_in <= "001";
blue_in <= "00";
when "011" =>
red_in <= "000";
green_in <= "001";
blue_in <= "01";
when "100" =>
red_in <= "001";
green_in <= "000";
blue_in <= "00";
when "101" =>
red_in <= "001";
green_in <= "000";
blue_in <= "01";
when "110" =>
red_in <= "001";
green_in <= "001";
blue_in <= "00";
when others =>
red_in <= "001";
green_in <= "001";
blue_in <= "01";
end case;
end process;
res_sel: vga_res_sel
port map (
resolution => resolution,
HS_640_60 => bitHS_640_60,
HS_800_60 => bitHS_800_60,
VS_640_60 => bitVS_640_60,
VS_800_60 => bitVS_800_60,
red_25 => red_25,
green_25 => green_25,
blue_25 => blue_25,
red_40 => red_40,
green_40 => green_40,
blue_40 => blue_40,
hs => hsync,
vs => vsync,
red => red,
green => green,
blue => blue
);
-- 640 x 480 @ 60 Hz
VgaCtrl640_60 : vga_controller_640_60
port map (
pixel_clk => clk_25,
rst => rst,
blank => bitBlank640_60,
hcount(10 downto 0) => vecHcount_640_60(10 downto 0),
HS => bitHS_640_60,
vcount(10 downto 0) => vecVcount_640_60(10 downto 0),
VS => bitVS_640_60
);
Inst_mouse_disp_25mhz: mouse_displayer
port map (
clk => clk,
pixel_clk => clk_25,
xpos => xpos,
ypos => ypos,
hcount => vecHcount_640_60,
vcount => vecVcount_640_60,
blank => bitBlank640_60,
click => click,
red_in => red_in,
green_in => green_in,
blue_in => blue_in,
red_out => red_25,
green_out => green_25,
blue_out => blue_25
);
-- 800 x 600 @ 60 Hz
VgaCtrl800_60 : vga_controller_800_60
port map (
pixel_clk => clk_40,
rst => rst,
blank => bitBlank800_60,
hcount(10 downto 0) => vecHcount_800_60(10 downto 0),
HS => bitHS_800_60,
vcount(10 downto 0) => vecVcount_800_60(10 downto 0),
VS => bitVS_800_60
);
Inst_mouse_disp_40mhz: mouse_displayer
port map (
clk => clk,
pixel_clk => clk_40,
xpos => xpos,
ypos => ypos,
hcount => vecHcount_800_60,
vcount => vecVcount_800_60,
blank => bitBlank800_60,
click => click,
red_in => red_in,
green_in => green_in,
blue_in => blue_in,
red_out => red_40,
green_out => green_40,
blue_out => blue_40
);
end behavioral;
|
gpl-3.0
|
a410a1508b47ee444f658885d9f51efd
| 0.446549 | 3.709783 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part1/HexDigSSegCntrl.vhd
| 1 | 2,294 |
-----------------------------------------------
-- Module Name: HexDigSSegCntrl - control --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity HexDigSSegCntrl is
port ( clock : in std_logic;
sw0 : in std_logic;
btns : in std_logic_vector (3 downto 0);
anodes : out std_logic_vector (3 downto 0);
cathodes : out std_logic_vector (7 downto 0));
end HexDigSSegCntrl;
architecture control of HexDigSSegCntrl is
begin
-- c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
---- c16Hz: CDiv port map (clock, TC16Hz, clk16Hz);
---- c20Hz: CDiv port map (clock, TC20Hz, clk20Hz);
---- c30Hz: CDiv port map (clock, TC30Hz, clk30Hz);
-- c3Hz: CDiv port map (clock, TC3Hz, clk3Hz);
HexDs: Hex4Digs_2_SSeg port map (clock, sw0, btns, anodes, cathodes);
-- process (sw1, clk5Hz, clk16Hz) -- control clocks
-- process (sw1, clk5Hz, clk20Hz) -- control clocks
-- process (sw1, clk5Hz, clk30Hz) -- control clocks
-- process (sw1, clk5Hz, clk3Hz) -- control clocks
-- begin
-- if (sw1 = '0') then
-- clk <= clk5Hz;
-- else
---- clk <= clk16Hz;
---- clk <= clk20Hz;
---- clk <= clk30Hz;
-- clk <= clk3Hz;
-- end if;
-- end process;
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- en <= not en;
-- end if;
-- end process;
--
-- process (clk)
-- begin
-- if rising_edge(clk) then
-- if en = '1' then
-- c0 <= c0 + 1;
-- cntr(0) <= '1';
-- if (c0 = 15) then
-- c1 <= c1 + 1;
-- cntr(1) <= '1';
-- if (c1 = 15) then
-- c2 <= c2 + 1;
-- cntr(2) <= '1';
-- if (c2 = 15) then
-- c3 <= c3 + 1;
-- cntr(3) <= '1';
-- end if;
-- end if;
-- end if;
-- else
-- cntr <= "0000";
-- end if;
-- end if;
-- end process;
end control;
|
gpl-3.0
|
e2560c5cb501e5836b1924a841e2c037
| 0.435484 | 3.344023 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 1/cliente_seguinte.vhd
| 1 | 648 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity cliente_seguinte is
port( clienseg : in std_logic;
reset : in std_logic;
binOut : out std_logic_vector(6 downto 0));
end cliente_seguinte;
architecture Behavioral of cliente_seguinte is
signal count : unsigned(6 downto 0);
begin
process(clienseg)
begin
if(rising_edge(clienseg)) then
if(reset='1') then
count <= (others => '0');
else
if(count="1100011") then --99
count <= (others=>'0');
else
count <= count+1;
end if;
end if;
end if;
binOut <= std_logic_vector(count);
end process;
end Behavioral;
|
gpl-2.0
|
feb408e1fb4337144a7ceca8e91f6021
| 0.643519 | 3 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/attic/arbiter.vhd
| 1 | 1,318 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity arbiter is
Port(
I_addr: in std_logic_vector(31 downto 0);
I_busy0, I_busy1, I_busy2, I_busy3: in std_logic;
I_data0, I_data1, I_data2, I_data3: in std_logic_vector(31 downto 0);
I_en: in std_logic;
O_busy: out std_logic := '1';
O_data: out std_logic_vector(31 downto 0);
O_en0, O_en1, O_en2, O_en3: out std_logic
);
end arbiter;
architecture Behavioral of arbiter is
begin
process(I_addr, I_en, I_data0, I_data1, I_data2, I_data3, I_busy0, I_busy1, I_busy2, I_busy3)
begin
if I_en = '1' then
O_en0 <= '0';
O_en1 <= '0';
O_en2 <= '0';
O_en3 <= '0';
-- most significant nibble selects device - room for 16 devices
case I_addr(29 downto 28) is
when "00" =>
O_en0 <= '1';
O_data <= I_data0;
O_busy <= I_busy0;
when "01" =>
O_en1 <= '1';
O_data <= I_data1;
O_busy <= I_busy1;
when "10" =>
O_en2 <= '1';
O_data <= I_data2;
O_busy <= I_busy2;
when others => -- "11" presumably
O_en3 <= '1';
O_data <= I_data3;
O_busy <= I_busy3;
end case;
else
O_en0 <= '0';
O_en1 <= '0';
O_en2 <= '0';
O_en3 <= '0';
O_data <= X"00000000";
O_busy <= '0';
end if;
end process;
end Behavioral;
|
mit
|
bc7504c79d75b4811fe790f807e3a729
| 0.544006 | 2.324515 | false | false | false | false |
miree/vhdl_cores
|
fifo/fifo_active_out/fifo.vhd
| 1 | 2,357 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
depth : integer;
bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
push_i, pop_i : in std_logic;
full_o, empty_o : out std_logic;
d_i : in std_logic_vector ( bit_width-1 downto 0 );
q_o : out std_logic_vector ( bit_width-1 downto 0 )
);
end entity;
architecture rtl of fifo is
-- calculate the number of words from
-- the depth (which is like the address width)
constant number_of_words : integer := 2**depth;
-- define data type of the storage array
type fifo_data_array is array ( 0 to number_of_words-1)
of std_logic_vector ( bit_width-1 downto 0);
-- define the storage array
signal fifo_data : fifo_data_array;
-- read and write index pointers
-- give them one bit more then needed to quickly check for overflow
-- by looking at the most significant bit (tip from Mathias Kreider)
signal w_idx : unsigned ( depth downto 0 );
signal r_idx : unsigned ( depth downto 0 );
signal msb_xor : std_logic;
signal empty_or_full : boolean;
signal empty : std_logic;
signal full : std_logic;
signal q : std_logic_vector ( bit_width-1 downto 0 );
begin
main: process
begin
wait until rising_edge(clk_i);
if rst_i = '1' then
w_idx <= (others => '0');
r_idx <= (others => '0');
else
-- write
w_idx <= w_idx;
if push_i = '1' then
fifo_data(to_integer(w_idx(depth-1 downto 0))) <= d_i;
w_idx <= w_idx + 1;
end if;
-- read
r_idx <= r_idx;
q_o <= (others => 'U');
if pop_i = '1' then
q_o <= fifo_data(to_integer(r_idx(depth-1 downto 0)));
r_idx <= r_idx + 1;
end if;
end if;
end process;
-- If read and write index up to (not including) the most significant bit are identical,
-- the fifo is either empty or full.
-- The xor of the most significant bit decides if the fifo is full or empty.
msb_xor <= (r_idx(depth) xor w_idx(depth));
empty_or_full <= r_idx(depth-1 downto 0) = w_idx(depth-1 downto 0);
full_o <= msb_xor when empty_or_full else '0';
empty_o <= not msb_xor when empty_or_full else '0';
end architecture;
|
mit
|
6dd8c39e747d894d2e3f993dda3c0c55
| 0.585066 | 3.310393 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 9/Parte V/Ram2_N_Demo.vhd
| 1 | 605 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram2_N_Demo is
port( KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(3 downto 0));
end Ram2_N_demo;
architecture Structural of Ram2_N_Demo is
begin
ram: entity work.Ram2_n(Behavioral)
generic map(data => 4,
addr => 2)
port map(clk => KEY(0),
writeEnable => SW(0),
writeData => SW(17 downto 14),
writeAddress => SW(2 downto 1),
readAddress => SW(4 downto 3),
dataOut => LEDG(3 downto 0));
end Structural;
|
gpl-2.0
|
dc9a58dcfba91e4d30990087d8761bca
| 0.629752 | 2.894737 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/JpegEnc.vhd
| 2 | 18,960 |
-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project : JPEG_ENC
--
-- Module : JpegEnc
--
-- Content : JPEG Encoder Top Level
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(11 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- FDCT INPUT DATA
fdct_fifo_rd : out std_logic;
fdct_fifo_q : in std_logic_vector(23 downto 0);
fdct_fifo_hf_full : in std_logic;
fdct_fifo_dval_o : out std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0);
outif_almost_full : in std_logic;
--debug signal
frame_size : out std_logic_vector(23 downto 0)
);
end entity JpegEnc;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
signal qdata : std_logic_vector(7 downto 0);
signal qaddr : std_logic_vector(6 downto 0);
signal qwren : std_logic;
signal jpeg_ready : std_logic;
signal jpeg_busy : std_logic;
signal outram_base_addr : std_logic_vector(9 downto 0);
signal num_enc_bytes : std_logic_vector(23 downto 0);
signal img_size_x : std_logic_vector(15 downto 0);
signal img_size_y : std_logic_vector(15 downto 0);
signal sof : std_logic;
signal jpg_iram_rden : std_logic;
signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);
signal jpg_iram_rdata : std_logic_vector(23 downto 0);
signal fdct_start : std_logic;
signal fdct_ready : std_logic;
signal zig_start : std_logic;
signal zig_ready : std_logic;
signal qua_start : std_logic;
signal qua_ready : std_logic;
signal rle_start : std_logic;
signal rle_ready : std_logic;
signal huf_start : std_logic;
signal huf_ready : std_logic;
signal bs_start : std_logic;
signal bs_ready : std_logic;
signal zz_buf_sel : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal zz_data : std_logic_vector(11 downto 0);
signal rle_buf_sel : std_logic;
signal rle_rdaddr : std_logic_vector(5 downto 0);
signal rle_data : std_logic_vector(11 downto 0);
signal qua_buf_sel : std_logic;
signal qua_rdaddr : std_logic_vector(5 downto 0);
signal qua_data : std_logic_vector(11 downto 0);
signal huf_buf_sel : std_logic;
signal huf_rdaddr : std_logic_vector(5 downto 0);
signal huf_rden : std_logic;
signal huf_runlength : std_logic_vector(3 downto 0);
signal huf_size : std_logic_vector(3 downto 0);
signal huf_amplitude : std_logic_vector(11 downto 0);
signal huf_dval : std_logic;
signal bs_buf_sel : std_logic;
signal bs_fifo_empty : std_logic;
signal bs_rd_req : std_logic;
signal bs_packed_byte : std_logic_vector(7 downto 0);
signal huf_fifo_empty : std_logic;
signal zz_rden : std_logic;
signal fdct_sm_settings : T_SM_SETTINGS;
signal zig_sm_settings : T_SM_SETTINGS;
signal qua_sm_settings : T_SM_SETTINGS;
signal rle_sm_settings : T_SM_SETTINGS;
signal huf_sm_settings : T_SM_SETTINGS;
signal bs_sm_settings : T_SM_SETTINGS;
signal image_size_reg : std_logic_vector(31 downto 0);
signal jfif_ram_byte : std_logic_vector(7 downto 0);
signal jfif_ram_wren : std_logic;
signal jfif_ram_wraddr : std_logic_vector(23 downto 0);
signal out_mux_ctrl : std_logic;
signal img_size_wr : std_logic;
signal jfif_start : std_logic;
signal jfif_ready : std_logic;
signal bs_ram_byte : std_logic_vector(7 downto 0);
signal bs_ram_wren : std_logic;
signal bs_ram_wraddr : std_logic_vector(23 downto 0);
signal jfif_eoi : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Host Interface
-------------------------------------------------------------------
U_HostIF : entity work.HostIF
port map
(
CLK => CLK,
RST => RST,
-- OPB
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_DBus_in => OPB_DBus_in,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_DBus_out => OPB_DBus_out,
OPB_XferAck => OPB_XferAck,
OPB_retry => OPB_retry,
OPB_toutSup => OPB_toutSup,
OPB_errAck => OPB_errAck,
-- Quantizer RAM
qdata => qdata,
qaddr => qaddr,
qwren => qwren,
-- CTRL
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- ByteStuffer
outram_base_addr => outram_base_addr,
num_enc_bytes => num_enc_bytes,
-- global
img_size_x => img_size_x,
img_size_y => img_size_y,
img_size_wr => img_size_wr,
sof => sof
);
-------------------------------------------------------------------
-- Controller
-------------------------------------------------------------------
U_CtrlSM : entity work.CtrlSM
port map
(
CLK => CLK,
RST => RST,
-- output IF
outif_almost_full => outif_almost_full,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
jpeg_ready => jpeg_ready,
jpeg_busy => jpeg_busy,
-- FDCT
fdct_start => fdct_start,
fdct_ready => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- ZIGZAG
zig_start => zig_start,
zig_ready => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_start => qua_start,
qua_ready => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_start => rle_start,
rle_ready => rle_ready,
rle_sm_settings => rle_sm_settings,
-- Huffman
huf_start => huf_start,
huf_ready => huf_ready,
huf_sm_settings => huf_sm_settings,
-- ByteStuffdr
bs_start => bs_start,
bs_ready => bs_ready,
bs_sm_settings => bs_sm_settings,
-- JFIF GEN
jfif_start => jfif_start,
jfif_ready => jfif_ready,
jfif_eoi => jfif_eoi,
-- OUT MUX
out_mux_ctrl => out_mux_ctrl
);
-------------------------------------------------------------------
-- FDCT
-------------------------------------------------------------------
U_FDCT : entity work.FDCT
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => fdct_start,
ready_pb => fdct_ready,
fdct_sm_settings => fdct_sm_settings,
-- BUF_FIFO
bf_fifo_rd => fdct_fifo_rd,
bf_fifo_q => fdct_fifo_q,
bf_fifo_hf_full => fdct_fifo_hf_full,
bf_fifo_dval_o => fdct_fifo_dval_o,
-- ZIG ZAG
zz_buf_sel => zz_buf_sel,
zz_rd_addr => zz_rd_addr,
zz_data => zz_data,
zz_rden => zz_rden,
-- HOST
img_size_x => img_size_x,
img_size_y => img_size_y,
sof => sof
);
-------------------------------------------------------------------
-- ZigZag top level
-------------------------------------------------------------------
U_ZZ_TOP : entity work.ZZ_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => zig_start,
ready_pb => zig_ready,
zig_sm_settings => zig_sm_settings,
-- Quantizer
qua_buf_sel => qua_buf_sel,
qua_rdaddr => qua_rdaddr,
qua_data => qua_data,
-- FDCT
fdct_buf_sel => zz_buf_sel,
fdct_rd_addr => zz_rd_addr,
fdct_data => zz_data,
fdct_rden => zz_rden
);
-------------------------------------------------------------------
-- Quantizer top level
-------------------------------------------------------------------
U_QUANT_TOP : entity work.QUANT_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => qua_start,
ready_pb => qua_ready,
qua_sm_settings => qua_sm_settings,
-- RLE
rle_buf_sel => rle_buf_sel,
rle_rdaddr => rle_rdaddr,
rle_data => rle_data,
-- ZIGZAG
zig_buf_sel => qua_buf_sel,
zig_rd_addr => qua_rdaddr,
zig_data => qua_data,
-- HOST
qdata => qdata,
qaddr => qaddr,
qwren => qwren
);
-------------------------------------------------------------------
-- RLE TOP
-------------------------------------------------------------------
U_RLE_TOP : entity work.RLE_TOP
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => rle_start,
ready_pb => rle_ready,
rle_sm_settings => rle_sm_settings,
-- HUFFMAN
huf_buf_sel => huf_buf_sel,
huf_rden => huf_rden,
huf_runlength => huf_runlength,
huf_size => huf_size,
huf_amplitude => huf_amplitude,
huf_dval => huf_dval,
huf_fifo_empty => huf_fifo_empty,
-- Quantizer
qua_buf_sel => rle_buf_sel,
qua_rd_addr => rle_rdaddr,
qua_data => rle_data,
-- HostIF
sof => sof
);
-------------------------------------------------------------------
-- Huffman Encoder
-------------------------------------------------------------------
U_Huffman : entity work.Huffman
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => huf_start,
ready_pb => huf_ready,
huf_sm_settings => huf_sm_settings,
-- HOST IF
sof => sof,
img_size_x => img_size_x,
img_size_y => img_size_y,
-- RLE
rle_buf_sel => huf_buf_sel,
rd_en => huf_rden,
runlength => huf_runlength,
VLI_size => huf_size,
VLI => huf_amplitude,
d_val => huf_dval,
rle_fifo_empty => huf_fifo_empty,
-- Byte Stuffer
bs_buf_sel => bs_buf_sel,
bs_fifo_empty => bs_fifo_empty,
bs_rd_req => bs_rd_req,
bs_packed_byte => bs_packed_byte
);
-------------------------------------------------------------------
-- Byte Stuffer
-------------------------------------------------------------------
U_ByteStuffer : entity work.ByteStuffer
port map
(
CLK => CLK,
RST => RST,
-- CTRL
start_pb => bs_start,
ready_pb => bs_ready,
-- HOST IF
sof => sof,
num_enc_bytes => num_enc_bytes,
outram_base_addr => outram_base_addr,
-- Huffman
huf_buf_sel => bs_buf_sel,
huf_fifo_empty => bs_fifo_empty,
huf_rd_req => bs_rd_req,
huf_packed_byte => bs_packed_byte,
-- OUT RAM
ram_byte => bs_ram_byte,
ram_wren => bs_ram_wren,
ram_wraddr => bs_ram_wraddr
);
--debug signal
frame_size <= num_enc_bytes;
-------------------------------------------------------------------
-- JFIF Generator
-------------------------------------------------------------------
U_JFIFGen : entity work.JFIFGen
port map
(
CLK => CLK,
RST => RST,
outif_almost_full => outif_almost_full,
-- CTRL
start => jfif_start,
ready => jfif_ready,
eoi => jfif_eoi,
-- ByteStuffer
num_enc_bytes => num_enc_bytes,
-- HOST IF
qwren => qwren,
qwaddr => qaddr,
qwdata => qdata,
image_size_reg => image_size_reg,
image_size_reg_wr => img_size_wr,
-- OUT RAM
ram_byte => jfif_ram_byte,
ram_wren => jfif_ram_wren,
ram_wraddr => jfif_ram_wraddr
);
image_size_reg <= img_size_x & img_size_y;
-------------------------------------------------------------------
-- OutMux
-------------------------------------------------------------------
U_OutMux : entity work.OutMux
port map
(
CLK => CLK,
RST => RST,
-- CTRL
out_mux_ctrl => out_mux_ctrl,
-- ByteStuffer
bs_ram_byte => bs_ram_byte,
bs_ram_wren => bs_ram_wren,
bs_ram_wraddr => bs_ram_wraddr,
-- ByteStuffer
jfif_ram_byte => jfif_ram_byte,
jfif_ram_wren => jfif_ram_wren,
jfif_ram_wraddr => jfif_ram_wraddr,
-- OUT RAM
ram_byte => ram_byte,
ram_wren => ram_wren,
ram_wraddr => ram_wraddr
);
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
814009f10058adb78432a382b33110c0
| 0.393354 | 4.584139 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 5/Parte I/ShiftRegister_Demo.vhd
| 1 | 794 |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ShiftRegister_Demo is
port( SW : in std_logic_vector(11 downto 0);
LEDR : out std_logic_vector(8 downto 0);
CLOCK_50: in std_logic);
end ShiftRegister_Demo;
architecture Structural of ShiftRegister_Demo is
signal s_clk : std_logic;
begin
FreqDiv: entity work.FreqDivider(Behavioral)
generic map(K => 50000000)
port map(clkIn => CLOCK_50,
clkOut=> s_clk);
ShiftRegister_8: entity work.ShiftRegisterN(Behavioral)
generic map(N => 8)
port map(clk => s_clk,
si => SW(0),
dataOut => LEDR(7 downto 0),
so => LEDR(8),
reset => SW(1),
load => SW(2),
dataIn=> SW(11 downto 4));
end Structural;
|
gpl-2.0
|
7e1d0ee0f7c641db7ef399c218e775dd
| 0.575567 | 3.214575 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 8/TrafficLights/TrafficLightsTop.vhd
| 1 | 1,369 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TrafficLightsTop is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(0 downto 0);
LEDR : out std_logic_vector(17 downto 0));
end TrafficLightsTop;
architecture Shell of TrafficLightsTop is
signal s_clk1Hz : std_logic;
signal s_newTime, s_timeExp : std_logic;
signal s_timeVal : std_logic_vector(7 downto 0);
signal s_yBlink : std_logic;
signal s_yellow1, s_yellow2 : std_logic;
begin
clk_div_1hz : entity work.ClkDividerN(RTL)
generic map(divFactor => 50000000)
port map(clkIn => CLOCK_50,
clkOut => s_clk1Hz);
main_fsm : entity work.TrafficLightsFSM(Behavioral)
port map(reset => not KEY(0),
clk => s_clk1Hz,
intermit => SW(0),
newTime => s_newTime,
timeVal => s_timeVal,
timeExp => s_timeExp,
yBlink => s_yBlink,
red1 => LEDR(15),
yellow1 => s_yellow1,
green1 => LEDR(17),
red2 => LEDR(2),
yellow2 => s_yellow2,
green2 => LEDR(0));
LEDR(16) <= s_yellow1 and (not s_yBlink or s_clk1Hz);
LEDR(1) <= s_yellow2 and (not s_yBlink or s_clk1Hz);
timer_fsm : entity work.TimerAuxFSM(Behavioral)
port map(reset => not KEY(0),
clk => not s_clk1Hz,
newTime => s_newTime,
timeVal => s_timeVal,
timeExp => s_timeExp);
end Shell;
|
gpl-2.0
|
23538ba188f55049c4f805c356baf827
| 0.628196 | 2.627639 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2-Separate/Part2-B/HexDigSSegCntrl.vhd
| 1 | 2,034 |
-----------------------------------------------
-- Module Name: HexDigSSegCntrl - control --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity HexDigSSegCntrl is
port ( clock : in std_logic;
sw0 : in std_logic;
anodes : out std_logic_vector (3 downto 0);
cathodes : out std_logic_vector (7 downto 0));
end HexDigSSegCntrl;
architecture control of HexDigSSegCntrl is
signal cntr : std_logic_vector (3 downto 0);
signal clk : std_logic := '0'; -- Current clock
constant TC5Hz : integer := 56; -- TC for 5 Hz clock
signal clk5Hz : std_logic := '0'; -- 5Hz clock
signal c0, c1, c2, c3 : integer range 0 to 31;
signal delay : std_logic := '0';
begin
-- Get the current clock & 5 Hz clock
sclk: ClockController port map (clock, sw0, clk);
c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
HexDs: Hex4Digs_2_SSeg port map (clk, sw0, cntr, anodes, cathodes);
process (clk5Hz)
begin
if (clk5Hz'event and clk5Hz = '1') then
if (delay = '1') then
cntr <= "0000";
delay <= '0';
else
c0 <= c0 + 1;
if (c0 mod 2 = 1) then
cntr(0) <= '1';
if (c0 = 31) then
c1 <= c1 + 1;
end if;
elsif (c1 mod 2 = 1) then
cntr(1) <= '1';
if (c1 = 31) then
c2 <= c2 + 1;
end if;
elsif (c2 mod 2 = 1) then
cntr(2) <= '1';
if (c2 = 31) then
c3 <= c3 + 1;
end if;
elsif (c3 mod 2 = 1) then
cntr(3) <= '1';
end if;
delay <= '1';
end if;
end if;
end process;
end control;
|
gpl-3.0
|
c3aa14ff9a566f33132bafbfd36f3944
| 0.436087 | 3.889101 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/HostIF.vhd
| 2 | 9,721 |
-------------------------------------------------------------------------------
-- File Name : HostIF.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostIF
--
-- Content : Host Interface (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HostIF is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(11 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- Quantizer RAM
qdata : out std_logic_vector(7 downto 0);
qaddr : out std_logic_vector(6 downto 0);
qwren : out std_logic;
-- CTRL
jpeg_ready : in std_logic;
jpeg_busy : in std_logic;
-- ByteStuffer
outram_base_addr : out std_logic_vector(9 downto 0);
num_enc_bytes : in std_logic_vector(23 downto 0);
-- others
img_size_x : out std_logic_vector(15 downto 0);
img_size_y : out std_logic_vector(15 downto 0);
img_size_wr : out std_logic;
sof : out std_logic
);
end entity HostIF;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostIF is
constant C_ENC_START_REG : std_logic_vector(11 downto 0) := X"000";
constant C_IMAGE_SIZE_REG : std_logic_vector(11 downto 0) := X"004";
constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(11 downto 0) := X"008";
constant C_ENC_STS_REG : std_logic_vector(11 downto 0) := X"00C";
constant C_COD_DATA_ADDR_REG : std_logic_vector(11 downto 0) := X"010";
constant C_ENC_LENGTH_REG : std_logic_vector(11 downto 0) := X"014";
constant C_QUANTIZER_RAM_LUM_BASE : std_logic_vector(11 downto 0) := X"100";
constant C_QUANTIZER_RAM_CHR_BASE : std_logic_vector(11 downto 0) := X"200";
signal enc_start_reg : std_logic_vector(31 downto 0);
signal image_size_reg : std_logic_vector(31 downto 0);
signal image_ram_access_reg : std_logic_vector(31 downto 0);
signal enc_sts_reg : std_logic_vector(31 downto 0);
signal cod_data_addr_reg : std_logic_vector(31 downto 0);
signal read_ack : std_logic;
signal write_ack : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
OPB_retry <= '0';
OPB_toutSup <= '0';
OPB_errAck <= '0';
img_size_x <= image_size_reg(31 downto 16);
img_size_y <= image_size_reg(15 downto 0);
outram_base_addr <= cod_data_addr_reg(outram_base_addr'range);
-------------------------------------------------------------------
-- OPB read
-------------------------------------------------------------------
p_read : process(CLK, RST)
begin
if RST = '1' then
read_ack <= '0';
OPB_DBus_out <= (others => '0');
elsif CLK'event and CLK = '1' then
read_ack <= '0';
if OPB_select = '1' and read_ack = '0' then
-- only double word transactions are be supported
if OPB_RNW = '1' and OPB_BE = X"F" then
read_ack <= '1';
case OPB_ABus is
when C_ENC_START_REG =>
OPB_DBus_out <= enc_start_reg;
when C_IMAGE_SIZE_REG =>
OPB_DBus_out <= image_size_reg;
when C_IMAGE_RAM_ACCESS_REG =>
OPB_DBus_out <= image_ram_access_reg;
when C_ENC_STS_REG =>
OPB_DBus_out <= enc_sts_reg;
when C_COD_DATA_ADDR_REG =>
OPB_DBus_out <= cod_data_addr_reg;
when C_ENC_LENGTH_REG =>
OPB_DBus_out(31 downto 24) <= (others => '0');
OPB_DBus_out(23 downto 0) <= num_enc_bytes;
when others =>
OPB_DBus_out <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- OPB write
-------------------------------------------------------------------
p_write : process(CLK, RST)
begin
if RST = '1' then
qwren <= '0';
write_ack <= '0';
enc_start_reg <= (others => '0');
image_size_reg <= (others => '0');
image_ram_access_reg <= (others => '0');
enc_sts_reg <= (others => '0');
cod_data_addr_reg <= (others => '0');
qdata <= (others => '0');
qaddr <= (others => '0');
sof <= '0';
img_size_wr <= '0';
elsif CLK'event and CLK = '1' then
qwren <= '0';
write_ack <= '0';
sof <= '0';
img_size_wr <= '0';
if OPB_select = '1' and write_ack = '0' then
-- only double word transactions are be supported
if OPB_RNW = '0' and OPB_BE = X"F" then
write_ack <= '1';
case OPB_ABus is
when C_ENC_START_REG =>
enc_start_reg <= OPB_DBus_in;
if OPB_DBus_in(0) = '1' then
sof <= '1';
end if;
when C_IMAGE_SIZE_REG =>
image_size_reg <= OPB_DBus_in;
img_size_wr <= '1';
when C_IMAGE_RAM_ACCESS_REG =>
image_ram_access_reg <= OPB_DBus_in;
when C_ENC_STS_REG =>
enc_sts_reg <= (others => '0');
when C_COD_DATA_ADDR_REG =>
cod_data_addr_reg <= OPB_DBus_in;
when C_ENC_LENGTH_REG =>
--enc_length_reg <= OPB_DBus_in;
when others =>
if OPB_ABus(11 downto 8) = C_QUANTIZER_RAM_LUM_BASE(11 downto 8) then
qwren <= '1';
qaddr <= '0' & OPB_ABus(qaddr'high+2-1 downto 2);
elsif OPB_ABus(11 downto 8) = C_QUANTIZER_RAM_CHR_BASE(11 downto 8) then
qwren <= '1';
qaddr <= '1' & OPB_ABus(qaddr'high+2-1 downto 2);
end if;
end case;
end if;
qdata <= OPB_DBus_in(qdata'range);
end if;
-- special handling of status reg
if jpeg_ready = '1' then
-- set jpeg done flag
enc_sts_reg(1) <= '1';
end if;
enc_sts_reg(0) <= jpeg_busy;
end if;
end process;
-------------------------------------------------------------------
-- transfer ACK
-------------------------------------------------------------------
OPB_XferAck <= read_ack or write_ack;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
5551cf7dd72d7a4107b39a801248a368
| 0.449542 | 4.206404 | false | false | false | false |
tejainece/VHDLExperiments
|
FloatingPointMul23/Multiply16Booth4.vhd
| 1 | 3,757 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:23 01/22/2014
-- Design Name:
-- Module Name: Multiply16Booth4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Multiply16Booth4 is
PORT (
a: IN STD_LOGIC_VECTOR(15 downto 0);
b: IN STD_LOGIC_VECTOR(15 downto 0);
o: OUT STD_LOGIC_VECTOR(15 downto 0));
end Multiply16Booth4;
architecture Behavioral of Multiply16Booth4 is
COMPONENT BoothPartProdGen is
PORT (
bin3: in STD_LOGIC_VECTOR(2 downto 0);
a: in STD_LOGIC_VECTOR(15 downto 0);
product: out STD_LOGIC_VECTOR(16 downto 0)
);
end COMPONENT;
COMPONENT BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end COMPONENT;
SIGNAL aTmp: STD_LOGIC_VECTOR(16 downto 0);
SIGNAL oTmp: STD_LOGIC_VECTOR(31 downto 0);
SIGNAL prod0: STD_LOGIC_VECTOR(19 downto 0);
SIGNAL prod1: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod2: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod3: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod4: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod5: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod6: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod7: STD_LOGIC_VECTOR(17 downto 0);
begin
aTmp <= a & '0';
prod0(19 downto 17) <= (not prod0(16)) & prod0(16) & prod0(16);
prod1(18 downto 17) <= '1' & (not prod1(16));
prod2(18 downto 17) <= '1' & (not prod2(16));
prod3(18 downto 17) <= '1' & (not prod3(16));
prod4(18 downto 17) <= '1' & (not prod4(16));
prod5(18 downto 17) <= '1' & (not prod5(16));
prod6(18 downto 17) <= '1' & (not prod6(16));
prod7(17) <= not prod7(16);
prodgen0: BoothPartProdGen PORT MAP (
bin3 => aTmp(2 downto 0),
a => b,
product => prod0(16 downto 0)
);
prodgen1: BoothPartProdGen PORT MAP (
bin3 => aTmp(4 downto 2),
a => b,
product => prod1(16 downto 0)
);
prodgen2: BoothPartProdGen PORT MAP (
bin3 => aTmp(6 downto 4),
a => b,
product => prod2(16 downto 0)
);
prodgen3: BoothPartProdGen PORT MAP (
bin3 => aTmp(8 downto 6),
a => b,
product => prod3(16 downto 0)
);
prodgen4: BoothPartProdGen PORT MAP (
bin3 => aTmp(10 downto 8),
a => b,
product => prod4(16 downto 0)
);
prodgen5: BoothPartProdGen PORT MAP (
bin3 => aTmp(12 downto 10),
a => b,
product => prod5(16 downto 0)
);
prodgen6: BoothPartProdGen PORT MAP (
bin3 => aTmp(14 downto 12),
a => b,
product => prod6(16 downto 0)
);
prodgen7: BoothPartProdGen PORT MAP (
bin3 => aTmp(16 downto 14),
a => b,
product => prod7(16 downto 0)
);
output: BoothPartProdRed PORT MAP (
prod0 => prod0,
prod1 => prod1,
prod2 => prod2,
prod3 => prod3,
prod4 => prod4,
prod5 => prod5,
prod6 => prod6,
prod7 => prod7,
result => oTmp
);
o <= oTmp(29 downto 14);
end Behavioral;
|
gpl-3.0
|
d91ff3e1d10d568db9d403f382d2f276
| 0.624434 | 3.049513 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/decoder_tb.vhd
| 1 | 4,352 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity decoder_tb is
end decoder_tb;
architecture Behavior of decoder_tb is
constant I_clk_period : time := 10 ns;
signal I_clk : std_logic := '0';
signal I_en: std_logic := '1';
signal I_instr: std_logic_vector(XLEN-1 downto 0) := X"00000000";
signal O_rs1: std_logic_vector(4 downto 0);
signal O_rs2: std_logic_vector(4 downto 0);
signal O_rd: std_logic_vector(4 downto 0);
signal O_imm: std_logic_vector(XLEN-1 downto 0) := X"00000000";
signal O_opcode: std_logic_vector(4 downto 0);
signal O_funct3: std_logic_vector(2 downto 0);
signal O_funct7: std_logic_vector(6 downto 0);
begin
-- instantiate unit under test
uut: entity work.decoder port map(
I_clk => I_clk,
I_en => I_en,
I_instr => I_instr,
O_rs1 => O_rs1,
O_rs2 => O_rs2,
O_rd => O_rd,
O_imm => O_imm,
O_opcode => O_opcode,
O_funct3 => O_funct3,
O_funct7 => O_funct7
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
wait until falling_edge(I_clk);
I_instr <= X"00f00313"; -- addi t1,x0,15
wait until falling_edge(I_clk);
assert O_rs1 = R0 report "wrong rs1 decoded" severity failure;
assert O_rd = T1 report "wrong rd decoded" severity failure;
assert to_integer(signed(O_imm)) = 15 report "wrong immediate decoded" severity failure;
I_instr <= X"006282b3"; -- add t0,t0,t1
wait until falling_edge(I_clk);
assert O_rs1 = T0 report "wrong rs1 decoded" severity failure;
assert O_rs2 = T1 report "wrong rs2 decoded" severity failure;
assert O_rd = T0 report "wrong rd decoded" severity failure;
I_instr <= X"00502e23"; -- sw t0,28(x0)
wait until falling_edge(I_clk);
assert O_rs1 = R0 report "wrong rs1 decoded" severity failure;
assert O_rs2 = T0 report "wrong rs2 decoded" severity failure;
assert to_integer(signed(O_imm)) = 28 report "wrong immediate decoded" severity failure;
I_instr <= X"e0502023"; -- sw t0,-512(x0)
wait until falling_edge(I_clk);
assert O_rs1 = R0 report "wrong rs1 decoded" severity failure;
assert O_rs2 = T0 report "wrong rs2 decoded" severity failure;
assert to_integer(signed(O_imm)) = -512 report "wrong immediate decoded" severity failure;
I_instr <= X"01c02283"; -- lw t0,28(x0)
wait until falling_edge(I_clk);
assert O_rs1 = R0 report "wrong rs1 decoded" severity failure;
assert O_rd = T0 report "wrong rd decoded" severity failure;
assert to_integer(signed(O_imm)) = 28 report "wrong immediate decoded" severity failure;
I_instr <= X"ff1ff3ef"; -- jal x7,4 (from 0x14)
wait until falling_edge(I_clk);
assert O_rd = R7 report "wrong rd decoded" severity failure;
assert to_integer(signed(O_imm)) = -16 report "wrong immediate decoded" severity failure;
I_instr <= X"fec003e7"; -- jalr x7,x0,-20
wait until falling_edge(I_clk);
assert O_rs1 = R0 report "wrong rs1 decoded" severity failure;
assert O_rd = R7 report "wrong rd decoded" severity failure;
assert to_integer(signed(O_imm)) = -20 report "wrong immediate decoded" severity failure;
I_instr <= X"f0f0f2b7"; -- lui t0,0xf0f0f
wait until falling_edge(I_clk);
assert O_rs1 = R1 report "wrong rs1 decoded" severity failure;
assert O_rd = T0 report "wrong rd decoded" severity failure;
assert O_imm = X"f0f0f000" report "wrong immediate decoded" severity failure;
I_instr <= X"fe7316e3"; -- bne t1,t2,4 (from 0x18)
wait until falling_edge(I_clk);
assert O_rs1 = T1 report "wrong rs1 decoded" severity failure;
assert O_rs2 = T2 report "wrong rs2 decoded" severity failure;
assert to_integer(signed(O_imm)) = -20 report "wrong immediate decoded" severity failure;
I_instr <= X"c0002373"; -- rdcycle t1
wait until falling_edge(I_clk);
assert O_rs1 = R0 report "wrong rs1 decoded" severity failure;
assert O_rs2 = R0 report "wrong rs2 decoded" severity failure;
I_instr <= X"c80023f3"; -- rdcycleh t1
wait until falling_edge(I_clk);
assert O_rs1 = R0 report "wrong rs1 decoded" severity failure;
assert O_rs2 = R0 report "wrong rs2 decoded" severity failure;
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
c716f3f7fa43fd7cda060b3e1511b36f
| 0.689338 | 2.884029 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 5/Parte I/ShiftRegisterN.vhd
| 1 | 820 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ShiftRegisterN is
generic (N : positive := 4);
port( clk : in std_logic;
si : in std_logic;
dataOut : out std_logic_vector(N-1 downto 0);
so : out std_logic;
reset : in std_logic;
load : in std_logic;
dataIn : in std_logic_vector(N-1 downto 0));
end ShiftRegisterN;
architecture Behavioral of ShiftRegisterN is
signal s_dataOut : std_logic_vector(N-1 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset='1') then
s_dataOut <= (others=>'0');
elsif(load='1') then
s_dataOut <= dataIn;
else
s_dataOut <= s_dataOut(N-2 downto 0) & si;
end if;
end if;
end process;
dataOut <= s_dataOut(N-1 downto 0);
so <= s_dataOut(N-1);
end Behavioral;
|
gpl-2.0
|
5af44d3c8debab8afa8ee0b1ead3389a
| 0.628049 | 2.628205 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/attic/ram.vhd
| 1 | 2,883 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
use work.ram_init.all;
entity ram is
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_write: in std_logic;
I_addr: in std_logic_vector(XLEN-1 downto 0);
I_data: in std_logic_vector(XLEN-1 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0);
O_busy: out std_logic
);
end ram;
architecture Behavioral of ram is
type ram_states is (IDLE, READ1, WRITE1, WRITE2);
signal state: ram_states := IDLE;
signal read_buf: std_logic_vector(63 downto 0) := X"0000000000000000";
signal write_buf: std_logic_vector(31 downto 0) := X"00000000";
signal ram: store_t := RAM_INIT;
begin
process(I_clk)
variable word0,word1: std_logic_vector(ADDRLEN-1 downto 0);
variable byte: std_logic_vector(1 downto 0) := "00";
begin
if rising_edge(I_clk) and I_en = '1' then
-- address for first word
word0 := I_addr(word0'length+1 downto 2);
-- address for second word
word1 := std_logic_vector(unsigned(word0) + 1);
-- byte offset
byte := I_addr(1 downto 0);
case state is
when IDLE =>
if byte = "00" then
-- aligned access
if I_write = '0' then
-- read!
O_data <= ram(to_integer(unsigned(word0)));
else
-- write!
ram(to_integer(unsigned(word0))) <= I_data;
end if;
O_busy <= '0';
else
-- unaligned access!
O_busy <= '1';
read_buf <= ram(to_integer(unsigned(word0))) & ram(to_integer(unsigned(word1)));
if I_write = '0' then
-- unaligned read
state <= READ1;
else
-- unaligned write
state <= WRITE1;
end if;
end if;
when READ1 =>
case byte is
when "01" => O_data <= read_buf(55 downto 24);
when "10" => O_data <= read_buf(47 downto 16);
when others => O_data <= read_buf(39 downto 8);
end case;
O_busy <= '0';
state <= IDLE;
when WRITE1 =>
-- write first affected word, put other word in buffer
case byte is
when "01" =>
ram(to_integer(unsigned(word0))) <= read_buf(63 downto 56) & I_data(31 downto 8);
write_buf <= I_data(7 downto 0) & read_buf(23 downto 0);
when "10" =>
ram(to_integer(unsigned(word0))) <= read_buf(63 downto 48) & I_data(31 downto 16);
write_buf <= I_data(15 downto 0) & read_buf(15 downto 0);
when others =>
ram(to_integer(unsigned(word0))) <= read_buf(63 downto 40) & I_data(31 downto 24);
write_buf <= I_data(23 downto 0) & read_buf(7 downto 0);
end case;
state <= WRITE2;
when WRITE2 =>
-- write second word
ram(to_integer(unsigned(word1))) <= write_buf;
state <= IDLE;
O_busy <= '0';
when others =>
null;
end case;
end if;
end process;
end Behavioral;
|
mit
|
97751f0a41be9192066d6fb3fad3cb07
| 0.583073 | 2.966049 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2-Separate/Part2-B/CDiv.vhd
| 1 | 1,284 |
-----------------------------------
-- Module Name: CDiv - Divide --
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CDiv is
port(Cin : in std_logic;
TCvl : in integer;
Cout : out std_logic);
end CDiv;
-- Important values (for 50 MHz CLK):
-- 1 Hz -> TC = 84
-- 2 Hz -> TC = 71
-- 5 Hz -> TC = 56
-- 8 Hz -> TC = 50
-- 16 Hz -> TC = 42
-- 1 KHz (~987.6 Hz) -> TC = 15
-- 5 KHz -> TC = 10
architecture Divide of CDiv is
constant TC: integer := TCvl; -- Time Constant
signal c0,c1,c2,c3: integer range 0 to 1000;
signal D: std_logic := '0';
begin
process(Cin)
begin
if (Cin'event and Cin='1') then
c0 <= c0 + 1;
if c0 = TC then
c0 <= 0;
c1 <= c1 + 1;
elsif c1 = TC then
c1 <= 0;
c2 <= c2 + 1;
elsif c2 = TC then
c2 <= 0;
c3 <= c3 + 1;
elsif c3 = TC then
c3 <= 0;
D <= NOT D;
end if;
end if;
Cout <= D;
end process ;
end Divide ;
|
gpl-3.0
|
a1be6fb1bad2ad7c6a455b5c49b4d15e
| 0.386293 | 3.732558 | false | false | false | false |
spoorcc/realtimestagram
|
src/curves_pkg.vhd
| 2 | 9,705 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--! Package which provides functions to create Look Up Tables for various functions
--! The generated Look Up Table can be placed in a lookup_table entity.
--! \see lookup_table
package curves_pkg is
--! Bit depth of pixels
constant wordsize : integer := 8;
--! \brief array of std_logic_vectors
type array_pixel is array (natural range <>) of std_logic_vector(wordsize-1 downto 0);
----------------------------------------------------------------------
--! Function to create Look up table for a straight line
--! Used for testing purposes, creates a straight line.
--! The straight function is \f[p_{out}=c*p_{in} \f]
--! \param[in] size Number of elements to create
--! \param[in] c Amplification factor
--! \image html straight.png
function create_straight_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a negated line
--! The negate function is \f[p_{out}=p_{max}-p_{in} \f]
--! \param[in] size Number of elements to create
--! \image html negate.png
function create_negated_lut( size: integer)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a sigmoid function
--! The sigmoid function is \f[p_{out}=\frac{p_{max}}{1+\exp({-c/p_{max}*(p_{in}-p_{max})})} \f]
--! \param[in] size Number of elements to create
--! \param[in] c Amplification factor
--! \image html sigmoid.png
function create_sigmoid_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a gamma function
--! The gamma function is \f[p_{out}=c*p_{max}*(\frac{p_{in}}{p_{max}})^{\gamma} \f]
--! \param[in] size Number of elements to create
--! \param[in] gamma Gamma factor
--! \param[in] c Amplification factor
--! \image html gamma.png
function create_gamma_lut( size: integer;
gamma: real := 1.0;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a sine function
--! The sine function is \f[p_{out}=p_{max} * sin^c\left (\frac{\pi*x}{width} \right)\f]
--! \param[in] size Number of elements to create
--! \param[in] c Order
--! \image html vignette_curve.png
function create_sine_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Procedure to assert that value can be represented in bit range
--! \param[in] value Value to compare
--! \param[in] wordsize Bit depth
procedure verify_valid_value( variable value: in real;
constant wordsize: in integer);
----------------------------------------------------------------------
--! Procedure to pretty print out a LUT value
--! \param[in] value Value to be printed
--! \param[in] index Index to print
procedure report_lut_value( variable value: in real;
constant index: in integer);
end curves_pkg;
package body curves_pkg is
--======================================================================================--
function create_straight_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable calc_val: real := 0.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := c * real(i);
calc_val := realmin( calc_val, real( 2**wordsize ) - 1.0 );
calc_val := realmax( calc_val, 0.0 );
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_straight_lut;
--======================================================================================--
function create_negated_lut( size: integer)
return array_pixel is
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := max_val-real(i);
-- report_lut_value( calc_val, i);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_negated_lut;
--======================================================================================--
function create_sigmoid_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable exponent: real := 0.0;
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
exponent := (c/max_val)*(real(i) - max_val * 0.5 );
calc_val := ceil(max_val / (real(1) + exp(-exponent)));
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_sigmoid_lut;
--======================================================================================--
function create_gamma_lut( size: integer;
gamma: real := 1.0;
c: real := 1.0)
return array_pixel is
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := c*max_val*(real(i)/max_val)**gamma;
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_gamma_lut;
--======================================================================================--
function create_sine_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable exponent: real := 0.0;
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := max_val * sin( math_pi * real(i) / real(size))**c;
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_sine_lut;
--======================================================================================--
procedure verify_valid_value( variable value: in real;
constant wordsize: in integer) is
constant max_val : integer := integer(2**wordsize)-1;
begin
assert(integer(value) <= max_val) report "LUT filled with invalid value: " & integer'image(integer(value)) severity failure;
assert(integer(value) >= 0) report "LUT filled with invalid value" severity failure;
end procedure verify_valid_value;
--======================================================================================--
procedure report_lut_value( variable value: in real;
constant index: in integer) is
begin
report "LUT[" & integer'image(index) & "]: " & integer'image(integer(value));
end procedure report_lut_value;
end curves_pkg;
|
gpl-2.0
|
77299a95b7011f5b9e41f951437937bd
| 0.486759 | 4.482679 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/JFIFGen.vhd
| 2 | 12,077 |
-------------------------------------------------------------------------------
-- File Name : JFIFGen.vhd
--
-- Project : JPEG_ENC
--
-- Module : JFIFGen
--
-- Content : JFIF Header Generator
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090309: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JFIFGen is
port
(
CLK : in std_logic;
RST : in std_logic;
outif_almost_full : in std_logic;
-- CTRL
start : in std_logic;
ready : out std_logic;
eoi : in std_logic;
-- ByteStuffer
num_enc_bytes : in std_logic_vector(23 downto 0);
-- HOST IF
qwren : in std_logic;
qwaddr : in std_logic_vector(6 downto 0);
qwdata : in std_logic_vector(7 downto 0);
image_size_reg : in std_logic_vector(31 downto 0);
image_size_reg_wr : in std_logic;
-- OUT RAM
ram_byte : out std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_wraddr : out std_logic_vector(23 downto 0)
);
end entity JFIFGen;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JFIFGen is
constant C_SIZE_Y_H : integer := 25;
constant C_SIZE_Y_L : integer := 26;
constant C_SIZE_X_H : integer := 27;
constant C_SIZE_X_L : integer := 28;
constant C_EOI : std_logic_vector(15 downto 0) := X"FFD9";
constant C_QLUM_BASE : integer := 44;
constant C_QCHR_BASE : integer := 44+69;
signal hr_data : std_logic_vector(7 downto 0):=(others =>'0');
signal hr_waddr : std_logic_vector(9 downto 0):=(others =>'0');
signal hr_raddr : std_logic_vector(9 downto 0):=(others =>'0');
signal hr_we : std_logic:='0';
signal hr_q : std_logic_vector(7 downto 0):=(others =>'0');
signal size_wr_cnt : unsigned(2 downto 0):=(others =>'0');
signal size_wr : std_logic:='0';
signal rd_cnt : unsigned(9 downto 0):=(others =>'0');
signal rd_en : std_logic:='0';
signal rd_en_d1 : std_logic:='0';
signal rd_cnt_d1 : unsigned(rd_cnt'range):=(others =>'0');
signal rd_cnt_d2 : unsigned(rd_cnt'range):=(others =>'0');
signal eoi_cnt : unsigned(1 downto 0):=(others =>'0');
signal eoi_wr : std_logic:='0';
signal eoi_wr_d1 : std_logic:='0';
signal reading_header : std_logic;
component HeaderRam is
port
(
d : in STD_LOGIC_VECTOR(7 downto 0);
waddr : in STD_LOGIC_VECTOR(9 downto 0);
raddr : in STD_LOGIC_VECTOR(9 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------
-- Header RAM
-------------------------------------------------------------------
U_Header_RAM : HeaderRam
port map
(
d => hr_data,
waddr => hr_waddr,
raddr => hr_raddr,
we => hr_we,
clk => CLK,
q => hr_q
);
hr_raddr <= std_logic_vector(rd_cnt);
-------------------------------------------------------------------
-- Host programming
-------------------------------------------------------------------
p_host_wr : process(CLK, RST)
begin
if RST = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '0';
hr_we <= '0';
hr_data <= (others => '0');
hr_waddr <= (others => '0');
elsif CLK'event and CLK = '1' then
hr_we <= '0';
if image_size_reg_wr = '1' then
size_wr_cnt <= (others => '0');
size_wr <= '1';
end if;
-- write image size
if size_wr = '1' then
if size_wr_cnt = 4 then
size_wr_cnt <= (others => '0');
size_wr <= '0';
else
size_wr_cnt <= size_wr_cnt + 1;
hr_we <= '1';
case size_wr_cnt is
-- height H byte
when "000" =>
hr_data <= image_size_reg(15 downto 8);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_H,hr_waddr'length));
-- height L byte
when "001" =>
hr_data <= image_size_reg(7 downto 0);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_Y_L,hr_waddr'length));
-- width H byte
when "010" =>
hr_data <= image_size_reg(31 downto 24);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_H,hr_waddr'length));
-- width L byte
when "011" =>
hr_data <= image_size_reg(23 downto 16);
hr_waddr <= std_logic_vector(to_unsigned(C_SIZE_X_L,hr_waddr'length));
when others =>
null;
end case;
end if;
-- write Quantization table
elsif qwren = '1' then
-- luminance table select
if qwaddr(6) = '0' then
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QLUM_BASE,hr_waddr'length));
else
-- chrominance table select
hr_waddr <= std_logic_vector
( resize(unsigned(qwaddr(5 downto 0)),hr_waddr'length) +
to_unsigned(C_QCHR_BASE,hr_waddr'length));
end if;
hr_we <= '1';
hr_data <= qwdata;
end if;
end if;
end process;
-------------------------------------------------------------------
-- CTRL
-------------------------------------------------------------------
p_ctrl : process(CLK, RST)
begin
if RST = '1' then
ready <= '0';
rd_en <= '0';
rd_cnt <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_cnt_d2 <= (others => '0');
rd_cnt_d1 <= (others => '0');
rd_en_d1 <= '0';
eoi_wr_d1 <= '0';
eoi_wr <= '0';
eoi_cnt <= (others => '0');
ram_wren <= '0';
ram_byte <= (others => '0');
ram_wraddr <= (others => '0');
reading_header <= '0';
elsif CLK'event and CLK = '1' then
ready <= '0';
rd_cnt_d1 <= rd_cnt;
rd_cnt_d2 <= rd_cnt_d1;
rd_en_d1 <= rd_en;
eoi_wr_d1 <= eoi_wr;
-- defaults: encoded data write
ram_wren <= rd_en_d1;
ram_wraddr <= std_logic_vector(resize(rd_cnt_d1,ram_wraddr'length));
ram_byte <= hr_q;
-- start JFIF
if start = '1' and eoi = '0' then
rd_cnt <= (others => '0');
rd_en <= '1';
reading_header <= '1';
elsif start = '1' and eoi = '1' then
eoi_wr <= '1';
eoi_cnt <= (others => '0');
end if;
-- read JFIF Header
if reading_header = '1' then
if rd_cnt = C_HDR_SIZE-1 then
reading_header <= '0';
rd_en <= '0';
ready <= '1';
else
if outif_almost_full = '0' then
rd_en <= '1';
rd_cnt <= rd_cnt + 1;
else
rd_en <= '0';
end if;
end if;
end if;
-- EOI MARKER write
if eoi_wr = '1' then
if eoi_cnt = 2 then
eoi_cnt <= (others => '0');
eoi_wr <= '0';
ready <= '1';
else
eoi_cnt <= eoi_cnt + 1;
ram_wren <= '1';
if eoi_cnt = 0 then
ram_byte <= C_EOI(15 downto 8);
ram_wraddr <= num_enc_bytes;
elsif eoi_cnt = 1 then
ram_byte <= C_EOI(7 downto 0);
ram_wraddr <= std_logic_vector(unsigned(num_enc_bytes) +
to_unsigned(1,ram_wraddr'length));
end if;
end if;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
beabd78aff7ac70c2f8a6292dec2d9fe
| 0.39629 | 4.438442 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/Debouncer/Debouncer.vhd
| 1 | 576 |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Debouncer is
generic (N : positive);
port (clk : in std_logic;
dirty_In : in std_logic;
cleanOut : out std_logic);
end Debouncer;
architecture Behavioral of Debouncer is
signal s_dirty_In : std_logic_vector(N downto 1);
begin
process(clk, dirty_In)
begin
if(dirty_In='1') then
s_dirty_In <= (others => '0');
elsif(rising_edge(clk)) then
--s_dirty_In <= (others => '1');
s_dirty_In <= '1' & s_dirty_In(N downto 2);
end if;
cleanOut <= s_dirty_In(N);
end process;
end Behavioral;
|
gpl-2.0
|
8ce186a6a17262405eb95720dbf748fd
| 0.633681 | 2.618182 | false | false | false | false |
tejainece/VHDLExperiments
|
FloatingPointMul23/Selector.vhd
| 1 | 1,809 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:29 11/20/2013
-- Design Name:
-- Module Name: Selector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.MyTypes.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Selector is
generic (
num_sum: integer := 0;
num_buffer: integer := 0
);
Port ( cIn : in PairT;
cSel : in PairT;
cOut : out PairT;
sumIn : in PairArr(num_sum downto 0);
sumOut : out PairArr(num_sum downto 0);
bufferIn: in PairArr(num_buffer downto 0);
bufferOut:out PairArr(num_buffer downto 0));
end Selector;
architecture Behavioral of Selector is
begin
process (cIn, cSel, sumIn)
begin
if (cSel(0) = cSel(1)) then
if (cSel(0) = '0') then
for index in 0 to num_sum loop
sumOut(index) <= (1 downto 0 => sumIn(index)(0));
end loop;
cOut <= (1 downto 0 => cIn(0));
else
for index in 0 to num_sum loop
sumOut(index) <= (1 downto 0 => sumIn(index)(1));
end loop;
cOut <= (1 downto 0 => cIn(1));
end if;
else
for index in 0 to num_sum loop
sumOut <= sumIn;
end loop;
cOut <= cIn;
end if;
end process;
bufferOut <= bufferIn;
end Behavioral;
|
gpl-3.0
|
044730256faff04fa49f95c03b042807
| 0.580431 | 3.472169 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/ram/sram_external.vhd
| 1 | 1,155 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_external is
generic(
ADDRBITS: integer := 19;
DATABITS: integer := 8
);
port(
I_addr: in std_logic_vector(ADDRBITS-1 downto 0);
I_data: in std_logic_vector(DATABITS-1 downto 0);
I_en: in std_logic := '0';
I_we: in std_logic := '0';
O_data: out std_logic_vector(DATABITS-1 downto 0);
IO_external_data: inout std_logic_vector(DATABITS-1 downto 0);
O_external_addr: out std_logic_vector(ADDRBITS-1 downto 0);
O_external_ce: out std_logic := '1';
O_external_oe: out std_logic := '1';
O_external_we: out std_logic := '1'
);
end sram_external;
architecture Behavioral of sram_external is
begin
process(I_we, I_data, IO_external_data)
begin
if I_we = '1' then
IO_external_data <= I_data;
O_data <= I_data;
else
IO_external_data <= (others => 'Z');
O_data <= IO_external_data;
end if;
end process;
-- pass through address
O_external_addr <= I_addr;
-- control signals for external SRAM are active low
O_external_ce <= not I_en;
O_external_we <= not I_we;
O_external_oe <= not (I_en and (not I_we));
end Behavioral;
|
mit
|
0ab36ece93c11cb38a38161d2b9c831f
| 0.658874 | 2.711268 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/Bin7SecDec.vhd
| 1 | 989 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin7SecDec is
port( binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0));
end Bin7SecDec;
architecture Behavioral of Bin7SecDec is
begin
decOut_n <= "1111001" when binInput="0001" else --1
"0100100" when binInput="0010" else --2
"0110000" when binInput="0011" else --3
"0011001" when binInput="0100" else --4
"0010010" when binInput="0101" else --5
"0000010" when binInput="0110" else --6
"1111000" when binInput="0111" else --7
"0000000" when binInput="1000" else --8
"0010000" when binInput="1001" else --9
"0001000" when binInput="1010" else --A
"0000011" when binInput="1011" else --B
"1000110" when binInput="1100" else --C
"0100001" when binInput="1101" else --D
"0000110" when binInput="1110" else --E
"0001110" when binInput="1111" else --F
"1000000"; --0
end Behavioral;
|
gpl-2.0
|
d66099e1de3ef1ad471b51c22e035ebd
| 0.648129 | 3.307692 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/BasicWatchWithBugs/Resolução/BasicWatch.vhd
| 1 | 999 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BasicWatch is
port(SW : in std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(2 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
LEDG : out std_logic_vector(8 downto 7));
end BasicWatch;
architecture Shell of BasicWatch is
begin
system_core : entity work.BasicWatchCore(RTL)
port map(reset => SW(0),
clk => CLOCK_50,
mode => not KEY(1),
hSet => not KEY(2),
mSet => not KEY(0),
hTens => HEX7,
hUnits => HEX6,
mTens => HEX5,
mUnits => HEX4,
sTens => HEX3,
sUnits => HEX2,
sTick => LEDG(8),
ledOut => LEDG(7));
end Shell;
|
gpl-2.0
|
7203b4e07a6161459cea32240888e731
| 0.558559 | 2.838068 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/registers.vhd
| 1 | 1,437 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity registers is
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_op: in regops_t;
I_selS1: in std_logic_vector(4 downto 0);
I_selS2: in std_logic_vector(4 downto 0);
I_selD: in std_logic_vector(4 downto 0);
I_data: in std_logic_vector(XLEN-1 downto 0);
O_dataS1: out std_logic_vector(XLEN-1 downto 0) := XLEN_ZERO;
O_dataS2: out std_logic_vector(XLEN-1 downto 0) := XLEN_ZERO
);
end registers;
architecture Behavioral of registers is
type store_t is array(0 to 31) of std_logic_vector(XLEN-1 downto 0);
signal regs: store_t := (others => X"00000000");
attribute ramstyle : string;
attribute ramstyle of regs : signal is "no_rw_check";
begin
process(I_clk, I_en, I_op, I_selS1, I_selS2, I_selD, I_data)
variable data: std_logic_vector(XLEN-1 downto 0);
begin
if rising_edge(I_clk) and I_en = '1' then
data := X"00000000";
if I_op = REGOP_WRITE and I_selD /= "00000" then
data := I_data;
end if;
-- this is a pattern that Quartus RAM synthesis understands
-- as *not* being read-during-write (with no_rw_check attribute)
if I_op = REGOP_WRITE then
regs(to_integer(unsigned(I_selD))) <= data;
else
O_dataS1 <= regs(to_integer(unsigned(I_selS1)));
O_dataS2 <= regs(to_integer(unsigned(I_selS2)));
end if;
end if;
end process;
end Behavioral;
|
mit
|
0c00290909b0f36f194499ad46afb0e2
| 0.672234 | 2.726755 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 6/Parte 1/Dec2_4En.vhd
| 1 | 560 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Dec2_4En is
port( enable : in std_logic;
inputs : in std_logic_vector(1 downto 0);
outputs : out std_logic_vector(3 downto 0));
end Dec2_4En;
architecture RTL of Dec2_4En is
begin
process(enable, inputs)
begin
if (enable = '0') then
outputs <= "0000";
else
if (inputs = "00") then
outputs <= "0001";
elsif (inputs = "01") then
outputs <= "0010";
elsif (inputs = "10") then
outputs <= "0100";
else
outputs <= "1000";
end if;
end if;
end process;
end RTL;
|
gpl-2.0
|
4d4e849c880e7332b690c814befaa0e8
| 0.616071 | 2.81407 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Misc/debounce.vhd
| 1 | 860 |
--------------------------------------
-- Module Name: debounce - pulse --
--------------------------------------
-- Button debounce logic;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debounce is
port (
clk : in std_logic;
key : in std_logic;
pulse : out std_logic
);
end debounce;
architecture pulse of debounce is
signal cnt : std_logic_vector (1 downto 0) := "00";
begin
process (clk,key)
begin
if key = '1' then
cnt <= "00";
elsif (clk'event and clk = '1') then
if (cnt /= "11") then
cnt <= cnt + 1;
end if;
end if;
if (cnt = "10") and (key = '0') then
pulse <= '1';
else
pulse <= '0';
end if;
end process;
end pulse;
|
gpl-3.0
|
5983ad21ddcbafc90227e8b9de6f3a2d
| 0.445349 | 3.926941 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/ram/bus_ram_toplevel_tb.vhd
| 1 | 3,335 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity bus_ram_toplevel_tb is
end bus_ram_toplevel_tb;
architecture Behavior of bus_ram_toplevel_tb is
component bus_ram_toplevel
Port(
I_clk: in std_logic;
I_reset: in std_logic;
I_en: in std_logic;
I_op: in busops_t; -- memory opcodes
I_iaddr: in std_logic_vector(31 downto 0); -- instruction address, provided by PCU
I_daddr: in std_logic_vector(31 downto 0); -- data address, provided by ALU
I_data: in std_logic_vector(31 downto 0); -- data to be stored on write ops
I_mem_imem: in std_logic := '0'; -- denotes if instruction memory is accessed (signal from control unit)
O_data : out std_logic_vector(31 downto 0);
O_busy: out std_logic := '0';
O_clk: out std_logic := '0';
O_reset: out std_logic := '0'
);
end component;
signal I_clk, I_reset, I_en, I_mem_imem, O_busy, O_clk, O_reset: std_logic := '0';
signal I_iaddr, I_daddr, I_data, O_data: std_logic_vector(31 downto 0) := X"00000000";
signal I_op: busops_t;
constant I_clk_period : time := 10 ns;
begin
uut: bus_ram_toplevel port map(
I_clk => I_clk,
I_reset => I_reset,
I_en => I_en,
I_op => I_op,
I_iaddr => I_iaddr,
I_daddr => I_daddr,
I_data => I_data,
I_mem_imem => I_mem_imem,
O_data => O_data,
O_busy => O_busy,
O_clk => O_clk,
O_reset => O_reset
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
wait until falling_edge(I_clk);
I_en <= '1';
I_daddr <= X"00000000";
I_op <= BUS_READW;
wait until falling_edge(O_busy);
I_en <= '0';
-- test writing a word
wait until falling_edge(I_clk);
I_en <= '1';
I_data <= X"CAFEBABE";
I_daddr <= X"CAFE0000";
I_mem_imem <= '0';
I_op <= BUS_WRITEW;
wait until falling_edge(O_busy);
I_en <= '0';
-- read a word from memory, check if contents match what we've written
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READW;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"CAFEBABE" report "wrong data read" severity failure;
-- read a half word from memory, check sign extension
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READH;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"FFFFBABE" report "wrong data read" severity failure;
-- read a half word from memory, check zero extension
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READHU;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"0000BABE" report "wrong data read" severity failure;
-- read a byte from memory, check sign extension
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READB;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"FFFFFFBE" report "wrong data read" severity failure;
-- read a byte from memory, check zero extension
wait until falling_edge(I_clk);
I_en <= '1';
I_op <= BUS_READBU;
wait until falling_edge(O_busy);
I_en <= '0';
assert O_data = X"000000BE" report "wrong data read" severity failure;
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
27a89d934cdfe921f6a6fda33f9b39df
| 0.636582 | 2.713588 | false | false | false | false |
ncareol/nidas
|
src/firmware/analog/DSM3A2D.vhd
| 1 | 14,224 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : DSM3A2D.vhf
-- /___/ /\ Timestamp : 02/10/2006 14:47:21
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w DSM3A2D.sch DSM3A2D.vhf
--Design Name: DSM3A2D
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity DSM3A2D is
port ( AEN : in std_logic;
A2DINT : in std_logic_vector (7 downto 0);
BRDSEL : in std_logic;
FIFOAFAE : in std_logic;
FIFOEMPTYN : in std_logic;
FIFOFULL : in std_logic;
FIFOHF : in std_logic;
IORN : in std_logic;
IOWN : in std_logic;
ONEPPS : in std_logic;
PLLOUT : in std_logic;
clk : in std_logic;
SA0 : in std_logic;
SA1 : in std_logic;
SA2 : in std_logic;
SA3 : in std_logic;
SA4 : in std_logic;
A2DCLK : out std_logic;
A2DCS0N : out std_logic;
A2DCS1N : out std_logic;
A2DCS2N : out std_logic;
A2DCS3N : out std_logic;
A2DCS4N : out std_logic;
A2DCS5N : out std_logic;
A2DCS6N : out std_logic;
A2DCS7N : out std_logic;
A2DINTRP : out std_logic;
A2DRS : out std_logic;
A2DRWN : out std_logic;
A2DSYNC : out std_logic;
CAL_OFFSET : out std_logic_vector (15 downto 0);
D2ACAL : out std_logic_vector (4 downto 0);
-- D2ARWN : out std_logic;
-- D2A0ABN : out std_logic;
-- D2A0DS1 : out std_logic;
-- D2A0DS2 : out std_logic;
-- D2A1ABN : out std_logic;
-- D2A1DS1 : out std_logic;
-- D2A1DS2 : out std_logic;
-- D2A2ABN : out std_logic;
-- D2A2DS1 : out std_logic;
-- D2A2DS2 : out std_logic;
FIFOCLRN : out std_logic;
FIFODAFN : out std_logic;
FIFOLDCK : out std_logic;
FIFOOE : out std_logic;
FIFOUNCK : out std_logic;
IOCS16N : out std_logic;
I2CSCL : out std_logic;
PLLDBN : out std_logic;
SIORN : out std_logic;
SIOW : out std_logic;
-- TEST43 : out std_logic;
-- TEST45 : out std_logic;
SDIN : out std_logic;
CLKIN : out std_logic;
FSIN : out std_logic;
LDAC : out std_logic;
BRDSELO : out std_logic;
A2DBUS : inout std_logic_vector (15 downto 0);
BSD : inout std_logic_vector (15 downto 0);
I2CSDA : inout std_logic);
end DSM3A2D;
architecture BEHAVIORAL of DSM3A2D is
signal A2DDATA : std_logic;
signal A2DIOEBL : std_logic;
signal A2DSTAT : std_logic;
signal D2A0 : std_logic;
signal D2A1 : std_logic;
signal D2A2 : std_logic;
signal FIFO : std_logic;
signal FIFOCTL : std_logic_vector (7 downto 0);
signal FIFOSTAT : std_logic;
signal LBSD3 : std_logic;
signal PRESYNC : std_logic;
signal SIOR : std_logic;
signal SIORW : std_logic;
signal SIOWN : std_logic;
signal SYSCTL : std_logic;
signal A2DINTRP_DUMMY : std_logic;
signal A2DSYNC_DUMMY : std_logic;
signal SIOW_DUMMY : std_logic;
signal BRDSELO_DUMMY : std_logic;
signal A2DRS_DUMMY : std_logic;
attribute keep: string;
attribute keep of BRDSELO: signal is "yes";
component d2aio
port ( AEN : in std_logic;
D2A0 : in std_logic;
D2A1 : in std_logic;
D2A2 : in std_logic;
SA0 : in std_logic;
SA1 : in std_logic;
SA2 : in std_logic;
BRDSEL : in std_logic;
SIOW : in std_logic;
clk : in std_logic; -- 10 KHz
BSD : in std_logic_vector (15 downto 0);
D2ACAL : out std_logic_vector (4 downto 0);
SDIN : out std_logic;
CLKIN : out std_logic;
FSIN : out std_logic;
LDAC : out std_logic;
BRDSELO : out std_logic);
end component;
component fifoio
port ( SIOR : in std_logic;
FIFOHF : in std_logic;
FIFOAFAE : in std_logic;
FIFOEMPTYN : in std_logic;
FIFOFULL : in std_logic;
FIFOSTAT : in std_logic;
SIOWN : in std_logic;
FIFO : in std_logic;
ONEPPS : in std_logic;
A2DSYNC : in std_logic;
PRESYNC : in std_logic;
clk : in std_logic;
BSD : inout std_logic_vector (15 downto 0);
FIFOCLRN : out std_logic;
FIFODAFN : out std_logic;
FIFOOE : out std_logic;
FIFOCTL : out std_logic_vector (7 downto 0);
FIFOUNCK : out std_logic);
-- TEST43 : out std_logic);
end component;
component isaintfc
port ( SA4 : in std_logic;
SA3 : in std_logic;
SA2 : in std_logic;
SA1 : in std_logic;
SA0 : in std_logic;
IOWN : in std_logic;
IORN : in std_logic;
BRDSELO : in std_logic;
PLLOUT : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
BSD : inout std_logic_vector (15 downto 0);
I2CSDA : inout std_logic;
SIOW : out std_logic;
SIOR : out std_logic;
SIOWN : out std_logic;
SIORN : out std_logic;
A2DSTAT : out std_logic;
A2DDATA : out std_logic;
D2A0 : out std_logic;
D2A1 : out std_logic;
D2A2 : out std_logic;
SYSCTL : out std_logic;
FIFOSTAT : out std_logic;
FIFO : out std_logic;
IOCS16N : out std_logic;
SIORW : out std_logic;
LBSD3 : out std_logic;
I2CSCL : out std_logic);
end component;
component a2dstatio
port ( A2DIOEBL : in std_logic;
PLLOUT : in std_logic;
SIOR : in std_logic;
SIOW : in std_logic;
A2DRS : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
PLLDBN : out std_logic;
-- TEST45 : out std_logic;
A2DBUS : inout std_logic_vector (15 downto 0);
BSD : inout std_logic_vector (15 downto 0));
-- port ( SIOW : in std_logic;
-- SIOR : in std_logic;
-- A2DIOEBL : in std_logic;
-- PLLOUT : in std_logic;
-- A2DRS : in std_logic;
-- A2DBUS : inout std_logic_vector (15 downto 0);
-- BSD : inout std_logic_vector (15 downto 0);
-- PLLDBN : out std_logic);
-- TEST45 : out std_logic);
end component;
component sysctrl
port ( SYSCTL : in std_logic;
SIOWN : in std_logic;
A2DINT : in std_logic_vector (7 downto 0);
SIOR : in std_logic;
FIFOSTAT : in std_logic;
BSD : inout std_logic_vector (15 downto 0);
CAL_OFFSET : out std_logic_vector (15 downto 0);
A2DINTRP : out std_logic);
end component;
component a2dtiming
port ( A2DSTAT : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
SA3 : in std_logic;
SA2 : in std_logic;
SA1 : in std_logic;
SIORW : in std_logic;
ONEPPS : in std_logic;
LBSD3 : in std_logic;
A2DINTRP : in std_logic;
PLLOUT : in std_logic;
D2A0 : in std_logic;
A2DCS0N : out std_logic;
A2DCS1N : out std_logic;
A2DCS2N : out std_logic;
A2DCS3N : out std_logic;
A2DCS4N : out std_logic;
A2DCS5N : out std_logic;
A2DCS6N : out std_logic;
A2DCS7N : out std_logic;
A2DIOEBL : out std_logic;
A2DCLK : out std_logic;
A2DRS : out std_logic;
A2DRWN : out std_logic;
A2DSYNC : out std_logic;
FIFOLDCK : out std_logic;
PRESYNC : out std_logic);
end component;
begin
A2DINTRP <= A2DINTRP_DUMMY;
A2DSYNC <= A2DSYNC_DUMMY;
SIOW <= SIOW_DUMMY;
BRDSELO <= BRDSELO_DUMMY;
A2DRS <= A2DRS_DUMMY;
XLXI_4 : d2aio
port map( AEN=>AEN,
D2A0=>D2A0,
D2A1=>D2A1,
D2A2=>D2A2,
SA0=>SA0,
SA1=>SA1,
SA2=>SA2,
BRDSEL=>BRDSEL,
SIOW=>SIOW_DUMMY,
clk=>clk,
BSD(15 downto 0)=>BSD(15 downto 0),
D2ACAL(4 downto 0) => D2ACAL(4 downto 0),
SDIN=>SDIN,
CLKIN=>CLKIN,
FSIN=>FSIN,
LDAC=>LDAC,
BRDSELO=>BRDSELO_DUMMY);
XLXI_10 : fifoio
port map (A2DSYNC=>A2DSYNC_DUMMY,
FIFO=>FIFO,
FIFOAFAE=>FIFOAFAE,
FIFOEMPTYN=>FIFOEMPTYN,
FIFOFULL=>FIFOFULL,
FIFOHF=>FIFOHF,
FIFOSTAT=>FIFOSTAT,
ONEPPS=>ONEPPS,
PRESYNC=>PRESYNC,
SIOR=>SIOR,
SIOWN=>SIOWN,
clk=>clk,
FIFOCLRN=>FIFOCLRN,
FIFOCTL(7 downto 0)=>FIFOCTL(7 downto 0),
FIFODAFN=>FIFODAFN,
FIFOOE=>FIFOOE,
FIFOUNCK=>FIFOUNCK,
-- TEST43=>TEST43,
BSD(15 downto 0)=>BSD(15 downto 0));
XLXI_11 : isaintfc
port map (BRDSELO=>BRDSELO_DUMMY,
FIFOCTL(7 downto 0)=>FIFOCTL(7 downto 0),
IORN=>IORN,
IOWN=>IOWN,
SA0=>SA0,
SA1=>SA1,
SA2=>SA2,
SA3=>SA3,
SA4=>SA4,
PLLOUT=>PLLOUT,
A2DDATA=>A2DDATA,
A2DSTAT=>A2DSTAT,
D2A0=>D2A0,
D2A1=>D2A1,
D2A2=>D2A2,
FIFO=>FIFO,
FIFOSTAT=>FIFOSTAT,
IOCS16N=>IOCS16N,
I2CSCL=>I2CSCL,
LBSD3=>LBSD3,
SIOR=>SIOR,
SIORN=>SIORN,
SIORW=>SIORW,
SIOW=>SIOW_DUMMY,
SIOWN=>SIOWN,
SYSCTL=>SYSCTL,
BSD(15 downto 0)=>BSD(15 downto 0),
I2CSDA=>I2CSDA);
XLXI_14 : a2dstatio
port map (A2DIOEBL=>A2DIOEBL,
PLLOUT=>PLLOUT,
SIOR=>SIOR,
SIOW=>SIOW_DUMMY,
A2DRS=>A2DRS_DUMMY,
FIFOCTL(7 downto 0)=>FIFOCTL(7 downto 0),
PLLDBN=>PLLDBN,
-- TEST45=>TEST45,
A2DBUS(15 downto 0)=>A2DBUS(15 downto 0),
BSD(15 downto 0)=>BSD(15 downto 0));
XLXI_17 : sysctrl
port map (A2DINT(7 downto 0)=>A2DINT(7 downto 0),
FIFOSTAT=>FIFOSTAT,
SIOR=>SIOR,
SIOWN=>SIOWN,
SYSCTL=>SYSCTL,
A2DINTRP=>A2DINTRP_DUMMY,
CAL_OFFSET(15 downto 0)=>CAL_OFFSET(15 downto 0),
BSD(15 downto 0)=>BSD(15 downto 0));
XLXI_21 : a2dtiming
port map (A2DINTRP=>A2DINTRP_DUMMY,
A2DSTAT=>A2DSTAT,
FIFOCTL(7 downto 0)=>FIFOCTL(7 downto 0),
LBSD3=>LBSD3,
ONEPPS=>ONEPPS,
PLLOUT=>PLLOUT,
D2A0=>D2A0,
SA1=>SA1,
SA2=>SA2,
SA3=>SA3,
SIORW=>SIORW,
A2DCLK=>A2DCLK,
A2DCS0N=>A2DCS0N,
A2DCS1N=>A2DCS1N,
A2DCS2N=>A2DCS2N,
A2DCS3N=>A2DCS3N,
A2DCS4N=>A2DCS4N,
A2DCS5N=>A2DCS5N,
A2DCS6N=>A2DCS6N,
A2DCS7N=>A2DCS7N,
A2DIOEBL=>A2DIOEBL,
A2DRS=>A2DRS_DUMMY,
A2DRWN=>A2DRWN,
A2DSYNC=>A2DSYNC_DUMMY,
FIFOLDCK=>FIFOLDCK,
PRESYNC=>PRESYNC);
end BEHAVIORAL;
|
gpl-2.0
|
70c0436b91452aa0bc10568d2fa96ea9
| 0.431313 | 3.651861 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/ControlBranch.vhd
| 2 | 1,947 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:04:29 12/04/2012
-- Design Name:
-- Module Name: ControlBranch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ControlBranch is
port (cero , mayorque, saltar,EscrPC,EscrPC_Cond1,EscrPC_Cond2: in std_logic;--1 es menos significativo
salida: out std_logic);
end ControlBranch;
architecture Behavioral of ControlBranch is
signal aux: std_logic;
begin
salida<= aux or EscrPC;
process(cero , mayorque,EscrPC,EscrPC_Cond1,EscrPC_Cond2,saltar)
begin
if(saltar='1')then
if(EscrPC_Cond2='0')then
if(EscrPC_Cond1='0')then --caso 00 beq
if(cero='1')then
aux<='1';
else
aux<='0';
end if;
else --caso 01 bne
if(cero='0')then
aux<='1';
else
aux<='0';
end if;
end if;
else --cond2=1
if(EscrPC_Cond1='0')then --caso 10 bgt
if(cero='0' and mayorque='1')then
aux<='1';
else
aux<='0';
end if;
else --caso 11 blt
if(cero='0' and mayorque='0')then
aux<='1';
else
aux<='0';
end if;
end if;
end if;
else
aux<='0';
end if;
end process;
end Behavioral;
|
gpl-2.0
|
24b6d751503af7d98b0d0c18a3b4a2a0
| 0.529533 | 3.54 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 4/Parte IV e V/FreqDivider_Demo.vhd
| 1 | 1,115 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider_Demo is
port( LEDR : out std_logic_vector(0 downto 0);
CLOCK_50 : in std_logic;
SW : in std_logic_vector(1 downto 0);
HEX7 : out std_logic_vector(6 downto 0));
end FreqDivider_Demo;
architecture Structural of FreqDivider_Demo is
signal s_count : std_logic_vector(3 downto 0);
signal s_clk_out:std_logic;
begin
--FreqDivider: entity work.FreqDivider(Behavioral)
-- generic map(K => 25000000)
-- port map(clkIn => CLOCK_50,
-- clkOut=> LEDR(0));
FreqDivider: entity work.FreqDivider(Behavioral)
generic map(K => 50000000)
port map(clkIn => CLOCK_50,
clkOut => s_clk_out);
UpDown4: entity work.CounterUpDown4(Behavioral)
port map(clk => s_clk_out,
updown => SW(0),
reset => SW(1),
count => s_count);
Bin7SegDec: entity work.Bin7SegDecoder(Behavioral)
port map(enable => '1',
decOut_n => HEX7(6 downto 0),
binInput => s_count);
end Structural;
|
gpl-2.0
|
5c5d250c5f64abc6b1a4eace90bba58e
| 0.604484 | 3.194842 | false | false | false | false |
rbaummer/UART
|
uart_rx.vhd
| 1 | 6,386 |
--------------------------------------------------------------------------------
--
-- File: UART RX
-- Author: Rob Baummer
--
-- Description: A 8x oversampling UART receiver from 9600 to 57600 baud. Uses
-- 1 start bit, 1 stop bit and no parity.
--------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
entity uart_rx is
port (
--System Interface
reset : in std_logic;
enable : in std_logic;
sys_clk : in std_logic;
--UART serial interface
DIN : in std_logic;
--Receiver interface
baud_en : in std_logic;
rx_byte : out std_logic_vector(7 downto 0);
rx_valid : out std_logic;
rx_frame_error : out std_logic;
rx_break : out std_logic
);
end uart_rx;
architecture behavorial of uart_rx is
signal cnt_rst : std_logic;
signal cnt_en : std_logic;
signal cnt : std_logic_vector(2 downto 0);
signal bit_cnt_en : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal data_reg: std_logic_vector(7 downto 0);
signal frame_error : std_logic;
signal frame_error_reg : std_logic;
signal valid : std_logic;
signal valid_reg : std_logic;
signal shift : std_logic;
signal shift_dly : std_logic;
signal bit_in : std_logic;
signal sample_reg : std_logic_vector(2 downto 0);
type statetype is (idle, start, data, stop, frame_err);
signal cs, ns : statetype;
begin
--RX Byte
rx_byte <= data_reg;
--Edge detection of valid signal
rx_valid <= valid and not valid_reg;
--Edge detection of frame error signal
rx_frame_error <= frame_error and not frame_error_reg;
--Sequential process for RX Statemachine
--Baud_en is used as an enable to allow state machine to operate at proper
--frequency
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or enable = '0' then
cs <= idle;
elsif baud_en = '1' then
cs <= ns;
end if;
end if;
end process;
--Next State Combinatorial process
process (cs, cnt, bit_cnt_en, DIN)
begin
--default values for output signals
cnt_rst <= '0';
cnt_en <= '0';
bit_cnt_en <= '0';
frame_error <= '0';
valid <= '0';
shift <= '0';
case cs is
--wait for DIN = 0 which signals a start bit
when idle =>
cnt_rst <= '1';
if DIN = '0' then
ns <= start;
else
ns <= idle;
end if;
--potential start bit found, test at midpoint to verify start
when start =>
--test at midpoint of serial symbol
if cnt = "011" then
--reset 8x oversampling counter at centerpoint of start bit
cnt_rst <= '1';
--if input is a start bit DIN will still equal 0
if DIN = '0' then
ns <= data;
--false start bit, return to idle and wait for valid start
else
ns <= idle;
end if;
else
cnt_rst <= '0';
ns <= start;
end if;
--valid start found, start sampling data at midpoint of bits
when data =>
--8 counts from center of start bit is the center of a data bit
if cnt = "111" then
--shift in next serial bit
shift <= '1';
--increment bit counter
bit_cnt_en <= '1';
--if 8 bits captured start looking for stop bit
if bit_cnt = "111" then
ns <= stop;
else
ns <= data;
end if;
--wait for center of data bit
else
shift <= '0';
bit_cnt_en <= '0';
ns <= data;
end if;
--check for valid stop bit
when stop =>
--sample DIN at center of stop bit
if cnt = "111" then
--valid stop bit if DIN = '1'
if DIN = '1' then
valid <= '1';
--returning to idle allows resyncing of start bit
ns <= idle;
--generate frame error is stop bit is invalid
else
valid <= '0';
ns <= frame_err;
end if;
--wait for center of stop bit
else
valid <= '0';
ns <= stop;
end if;
--invalid stop bit found, generate frame_error
when frame_err =>
frame_error <= '1';
ns <= idle;
when others =>
ns <= idle;
end case;
end process;
--8x oversampling counter
--oversampling counter is used to determine optimal sampling time of asynchronous DIN
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' or (cnt_rst = '1' and baud_en = '1') then
cnt <= "000";
--baud_en allows counter to operate at proper baud rate
elsif baud_en = '1' then
cnt <= cnt + "001";
end if;
end if;
end process;
--bit counter
--bit counter determines how many bits have been received
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
bit_cnt <= "000";
--baud_en allows counter to operate at proper baud rate
elsif baud_en = '1' and bit_cnt_en = '1' then
bit_cnt <= bit_cnt + "001";
end if;
end if;
end process;
--sample shift register
--for majority vote around bit center to help prevent glitches causing faulty byte
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
sample_reg <= "000";
elsif baud_en = '1' then
sample_reg <= DIN & sample_reg(2 downto 1);
end if;
end if;
end process;
--Majority voter
bit_in <= (sample_reg(0) and sample_reg(1)) or (sample_reg(1) and sample_reg(2)) or (sample_reg(0) and sample_reg(2));
--shift delay register
--delay the shift by a baud_en to get the sample after the bit center
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
shift_dly <= '0';
elsif baud_en = '1' then
shift_dly <= shift;
end if;
end if;
end process;
--byte shift register
--collect the serial bits as they are received
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
data_reg <= X"00";
--capture serial bit when commanded
elsif shift_dly = '1' and baud_en = '1' then
data_reg <= bit_in & data_reg(7 downto 1);
end if;
end if;
end process;
--break detection
rx_break <= '1' when data_reg = X"00" and frame_error = '1' else '0';
--Edge detection registers
process (sys_clk)
begin
if sys_clk = '1' and sys_clk'event then
if reset = '1' then
valid_reg <= '0';
frame_error_reg <= '0';
else
valid_reg <= valid;
frame_error_reg <= frame_error;
end if;
end if;
end process;
end behavorial;
|
mit
|
49d585f08aefdf96f096ed5cc7fa0c08
| 0.605857 | 3.08056 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/AluDisplayex5.vhd
| 1 | 2,147 |
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity AluDisplayex5 is
generic(N : natural := 8);
port( decOut_n, m2 : out std_logic_vector(6 downto 0);
a, b : in std_logic_vector(N-1 downto 0);
op : in std_logic_vector(2 downto 0);
r, m : out std_logic_vector(N-1 downto 0));
end AluDisplayex5;
architecture Behavioral of AluDisplayex5 is
signal s_a, s_b, s_r : unsigned(N-1 downto 0);
signal s_m : unsigned((2*N)-1 downto 0);
begin
decOut_n <= "1111001" when r="0001" else --1
"0100100" when r="0010" else --2
"0110000" when r="0011" else --3
"0011001" when r="0100" else --4
"0010010" when r="0101" else --5
"0000010" when r="0110" else --6
"1111000" when r="0111" else --7
"0000000" when r="1000" else --8
"0010000" when r="1001" else --9
"0001000" when r="1010" else --A
"0000011" when r="1011" else --B
"1000110" when r="1100" else --C
"0100001" when r="1101" else --D
"0000110" when r="1110" else --E
"0001110" when r="1111" else --F
"1000000"; --0
m2 <= "1111001" when m="0001" else --1
"0100100" when m="0010" else --2
"0110000" when m="0011" else --3
"0011001" when m="0100" else --4
"0010010" when m="0101" else --5
"0000010" when m="0110" else --6
"1111000" when m="0111" else --7
"0000000" when m="1000" else --8
"0010000" when m="1001" else --9
"0001000" when m="1010" else --A
"0000011" when m="1011" else --B
"1000110" when m="1100" else --C
"0100001" when m="1101" else --D
"0000110" when m="1110" else --E
"0001110" when m="1111" else --F
"1000000"; --0
s_a <= unsigned(a);
s_b <= unsigned(b);
s_m <= s_a * s_b;
with op select
s_r <= (s_a + s_b) when "000",
(s_a - s_b) when "001",
s_m(N-1 downto 0) when "010",
(s_a / s_b) when "011",
s_a rem s_b when "100",
s_a and s_b when "101",
s_a or s_b when "110",
s_a xor s_b when "111";
r <= std_logic_vector(s_r);
m <= std_logic_vector(s_m((2*N)-1 downto 4)) when (op = "010") else
(others => '0');
end Behavioral;
|
gpl-2.0
|
93a9f6f91b4ac0b73272500798c304b6
| 0.560782 | 2.631127 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 1/LogicUnit.vhd
| 1 | 538 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LogicUnit is
port(input0 : in std_logic;
input1 : in std_logic;
invOut : out std_logic;
andOut : out std_logic;
orOut : out std_logic;
xorOut : out std_logic;
nandOut : out std_logic;
norOut : out std_logic);
end LogicUnit;
architecture Behavioral of LogicUnit is
begin
invOut <= not input0;
andOut <= input0 and input1;
orOut <= input0 or input1;
xorOut <= input0 xor input1;
nandOut <= input0 nand input1;
norOut <= input0 nor input1;
end Behavioral;
|
gpl-2.0
|
9f9c87c8240ff4dc9cc9e73e1854f9f2
| 0.693309 | 3.022472 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2-Separate/Part2-A/H4D2SSegCntrl.vhd
| 1 | 1,376 |
-------------------------------------------------
-- Module Name: Hex4Dig2SSegCntrl - control --
-------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Dig2SSeg_Package.all;
entity Hex4Dig2SSegCntrl is
port (
clock : in std_logic;
sw0 : in std_logic; -- Switch to control clock
btns : in std_logic_vector (3 downto 0);
anodes : out std_logic_vector (3 downto 0);
cathodes : out std_logic_vector (7 downto 0)
);
end Hex4Dig2SSegCntrl;
architecture control of Hex4Dig2SSegCntrl is
signal pulses : std_logic_vector (3 downto 0);
signal clk : std_logic := '0'; -- Current Clock
signal clk2Hz : std_logic := '0'; -- 2 Hz clock
signal clk5Hz : std_logic := '0'; -- 5 Hz clock
signal clk1KHz : std_logic := '0'; -- 1 KHz clock
begin
-- Get divided clocks
sclk: ClockController port map (clock, clk2Hz, clk5Hz, clk1KHz);
Pls: Deb4Btns port map (clk, btns, pulses);
HexDs: Hex4Digs2SSeg port map (clk, pulses, anodes, cathodes);
-- use switch to select fast or slow clk
process (sw0)
begin
case sw0 is
when '0' =>
clk <= clk1KHz;
when others =>
clk <= clk2Hz;
end case;
end process;
end control;
|
gpl-3.0
|
87a86c5b22f66d80f0fadebbd87ada27
| 0.558866 | 3.669333 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/simu_ControlG.vhd
| 2 | 3,806 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:20:52 12/14/2012
-- Design Name:
-- Module Name: C:/hlocal/hoy/simu_ControlG.vhd
-- Project Name: hoy
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: control
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY simu_ControlG IS
END simu_ControlG;
ARCHITECTURE behavior OF simu_ControlG IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control
PORT(
instruction : IN std_logic_vector(5 downto 0);
estado : IN ESTADOS;
RegDst : OUT std_logic;
RegWrite : OUT std_logic;
MemWrite : OUT std_logic;
MemRead : OUT std_logic;
MemtoReg : OUT std_logic;
PcWriteCond0 : OUT std_logic;
PcWriteCond1 : OUT std_logic;
PcWriteCond2 : OUT std_logic;
ALUOp0 : OUT std_logic;
ALUOp1 : OUT std_logic;
ALUA : OUT std_logic;
ALUB0 : OUT std_logic;
ALUB1 : OUT std_logic;
PcSrc0 : OUT std_logic;
PcSrc1 : OUT std_logic;
PcWrite : OUT std_logic
);
END COMPONENT;
--Inputs
signal instruction : std_logic_vector(5 downto 0) := (others => '0');
signal estado : ESTADOS;
--Outputs
signal RegDst : std_logic;
signal RegWrite : std_logic;
signal MemWrite : std_logic;
signal MemRead : std_logic;
signal MemtoReg : std_logic;
signal PcWriteCond0 : std_logic;
signal PcWriteCond1 : std_logic;
signal PcWriteCond2 : std_logic;
signal ALUOp0 : std_logic;
signal ALUOp1 : std_logic;
signal ALUA : std_logic;
signal ALUB0 : std_logic;
signal ALUB1 : std_logic;
signal PcSrc0 : std_logic;
signal PcSrc1 : std_logic;
signal PcWrite : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: control PORT MAP (
instruction => instruction,
estado => estado,
RegDst => RegDst,
RegWrite => RegWrite,
MemWrite => MemWrite,
MemRead => MemRead,
MemtoReg => MemtoReg,
PcWriteCond0 => PcWriteCond0,
PcWriteCond1 => PcWriteCond1,
PcWriteCond2 => PcWriteCond2,
ALUOp0 => ALUOp0,
ALUOp1 => ALUOp1,
ALUA => ALUA,
ALUB0 => ALUB0,
ALUB1 => ALUB1,
PcSrc0 => PcSrc0,
PcSrc1 => PcSrc1,
PcWrite => PcWrite
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
instruction<="000000";
estado<=F;
wait for 100 ns;
estado<=id;
wait for 100 ns;
estado<=ex;
-- insert stimulus here
wait;
end process;
END;
|
gpl-2.0
|
2f810c72d4ec5fa8be812fd457a302ab
| 0.564372 | 4.150491 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Counter99.vhd
| 1 | 1,342 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter99 is
port( clk : in std_logic;
reset : in std_logic;
enable: in std_logic;
count0: out std_logic_vector(3 downto 0);
count1: out std_logic_vector(3 downto 0));
end Counter99;
-- Contador de quatro dígitos decimais com entrada de enable, reset e clock.
architecture Behavioral of Counter99 is
signal s_count0, s_count1 : unsigned (3 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(reset='1') then
s_count0 <= (others => '0');
s_count1 <= (others => '0');
elsif(s_count0 = "1001" and s_count1 = "1001") then
s_count0 <= s_count0;
s_count1 <= s_count1;
elsif(not(s_count0(0)='0') and not(s_count0(0)='1')) then
s_count0 <= (others => '0');
s_count1 <= (others => '0');
elsif (enable = '0') then
s_count0 <= s_count0;
s_count1 <= s_count1;
else
if (s_count0="1001") then
s_count0 <= "0000";
if(s_count1 = "1001") then
s_count1 <= "0000";
else
s_count1 <= s_count1 + 1;
end if;
else
s_count0 <= s_count0 + 1;
end if;
end if;
end if;
end process;
count0 <= std_logic_vector(s_count0);
count1 <= std_logic_vector(s_count1);
end Behavioral;
|
gpl-2.0
|
2dfd9c2eb689e5fd48d30aa493a10ba5
| 0.615958 | 2.64497 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/RandomNumber.vhd
| 1 | 1,321 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RandomNumber is
port( clock : in std_logic;
stop_signal : in std_logic;
reset : in std_logic;
count : out std_logic;
resetOut : out std_logic);
end RandomNumber;
-- Máquina de estados onde no estado inicial, counter = 1. Caso ocorra stop_signal,
-- count = 0. count só volta a 1 após reset = 1, e nesse caso resetOut = 1.
architecture Behavioral of RandomNumber is
type Tstate is (S0, S1, S2);
signal pState, nState : Tstate;
begin
clk_proc:process(clock)
begin
if(rising_edge(clock)) then
pState <= nState;
end if;
end process;
comb_proc:process(pState, stop_signal, reset)
begin
resetOut <= '0';
count <= '0';
case pState is
when S0 =>
count <= '1';
if(stop_signal = '1') then
nState <= S1;
elsif(reset = '1') then
nState <= S2;
else
nState <= S0;
end if;
when S1 =>
resetOut <= '0';
if(reset = '1') then
nState <= S2;
else
nState <= S1;
end if;
when S2 =>
resetOut <= '1';
if(reset = '0') then
nState <= S0;
else
nState <= S2;
end if;
when others =>
nState <= S2;
resetOut <= '0';
end case;
end process;
end Behavioral;
|
gpl-2.0
|
579442ca5df52d2c81b9f9b52ed08a22
| 0.600152 | 2.852814 | false | false | false | false |
vinodpa/openPowerlink-FPGA
|
Examples/ipcore/common/lib/src/edgedet.vhd
| 3 | 2,725 |
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY edgeDet IS
PORT (
din : IN STD_LOGIC;
rising : OUT STD_LOGIC;
falling : OUT STD_LOGIC;
any : OUT STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END ENTITY edgeDet;
ARCHITECTURE rtl OF edgeDet IS
signal RegDin, RegDinL : std_logic;
BEGIN
any <= RegDinL xor RegDin;
falling <= RegDinL and not RegDin;
rising <= not RegDinL and RegDin;
process(clk)
begin
if rising_edge(clk) then
RegDin <= din;
RegDinL <= RegDin;
end if;
end process;
END ARCHITECTURE rtl;
|
gpl-2.0
|
447dc32e900160d3791540686780901c
| 0.598165 | 4.755672 | false | false | false | false |
tejainece/VHDLExperiments
|
BoothPartProdGen/BoothPartProdGen.vhd
| 1 | 1,563 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:00:36 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BoothPartProdGen is
PORT (
bin3: in STD_LOGIC_VECTOR(2 downto 0);
a: in STD_LOGIC_VECTOR(15 downto 0);
product: out STD_LOGIC_VECTOR(16 downto 0)
);
end BoothPartProdGen;
architecture Behavioral of BoothPartProdGen is
constant ONE17: STD_LOGIC_VECTOR(16 downto 0) := "00000000000000001";
begin
PROCESS(bin3, a)
BEGIN
if bin3 = "001" or bin3 = "010" then
product <= "0" & a;
elsif bin3 = "011" then
product <= a & '0';
elsif bin3 = "101" or bin3 = "110" then
product <= std_logic_vector(unsigned(not('0' & a)) + unsigned(ONE17));
elsif bin3 = "100" then
product <= std_logic_vector(unsigned(not(a & '0')) + unsigned(ONE17));
else
product <= (others => '0');
end if;
END PROCESS;
end Behavioral;
|
gpl-3.0
|
0f8aa64cecf8e3654da4ee5cc54afb23
| 0.616123 | 3.552273 | false | false | false | false |
tejainece/VHDLExperiments
|
Multiply16Booth4/BoothPartProdRed.vhd
| 3 | 7,858 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:29:03 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdRed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end BoothPartProdRed;
architecture Behavioral of BoothPartProdRed is
COMPONENT HAdder is
port( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
END COMPONENT;
COMPONENT FAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
END COMPONENT;
COMPONENT Counter4_2 is
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC;
tout : out STD_LOGIC
);
END COMPONENT;
SIGNAL tempS1: STD_LOGIC_VECTOR(24 downto 2);
SIGNAL tempC1: STD_LOGIC_VECTOR(23 downto 3);
SIGNAL ctemp1: STD_LOGIC_VECTOR(21 downto 7);
SIGNAL tempS2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempC2: STD_LOGIC_VECTOR(31 downto 11);
SIGNAL ctemp2: STD_LOGIC_VECTOR(31 downto 8);
SIGNAL tempS3: STD_LOGIC_VECTOR(31 downto 3);
SIGNAL tempC3: STD_LOGIC_VECTOR(32 downto 4);
SIGNAL ctemp3: STD_LOGIC_VECTOR(25 downto 12);
begin
result(1 downto 0) <= prod0(1 downto 0);
result(2) <= tempS1(2);
tempS2(9 downto 8) <= prod4(9 downto 8);
tempS1(24 downto 23) <= prod3(24 downto 23);
tempS2(31) <= prod7(31);
result(3) <= tempS3(3);
result(31 downto 4) <= std_logic_vector(unsigned(tempS3(31 downto 4)) + unsigned(tempC3(31 downto 4)));
mainfor: FOR index in 2 to 31 GENERATE
if1_2to3:IF index >= 2 and index <= 3 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_4to5:IF index >= 4 and index <= 5 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod0(index),
b=>prod1(index),
c=>prod2(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_6:IF index = 6 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => '0',
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_7tp19:IF index >= 7 and index <= 19 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod0(index),
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_20:IF index = 20 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod1(index),
c => prod2(index),
d => prod3(index),
tin => ctemp1(index),
s => tempS1(index),
co => tempC1(index+1),
tout => ctemp1(index+1));
END GENERATE;
if1_21:IF index = 21 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp1(index),
b=>prod2(index),
c=>prod3(index),
s=>tempS1(index),
co=>tempC1(index+1));
END GENERATE;
if1_22:IF index = 22 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod2(index),
b=>prod3(index),
s=>tempS1(index),
c=>tempC1(index+1));
END GENERATE;
if1_10to11:IF index >= 10 and index <= 11 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if1_12to13:IF index >= 12 and index <= 13 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>prod4(index),
b=>prod5(index),
c=>prod6(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_14:IF index = 14 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => '0',
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_15to26:IF index >= 15 and index <= 26 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => prod4(index),
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_27to28:IF index >= 27 and index <= 28 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => '0',
b => prod5(index),
c => prod6(index),
d => prod7(index),
tin => ctemp2(index),
s => tempS2(index),
co => tempC2(index+1),
tout => ctemp2(index+1));
END GENERATE;
if1_29:IF index = 29 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp2(index),
b=>prod6(index),
c=>prod7(index),
s=>tempS2(index),
co=>tempC2(index+1));
END GENERATE;
if1_30:IF index = 30 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>prod6(index),
b=>prod7(index),
s=>tempS2(index),
c=>tempC2(index+1));
END GENERATE;
if2_3to7:IF index >= 3 and index <= 7 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
if2_8to10:IF index >= 8 and index <= 10 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>tempS1(index),
b=>tempC1(index),
c=>tempS2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_11:IF index = 11 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => '0',
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_12to23:IF index >= 12 and index <= 23 GENERATE
SUM7to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => tempC1(index),
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_24:IF index = 24 GENERATE
SUM6to19: Counter4_2 PORT MAP (
a => tempS1(index),
b => '0',
c => tempS2(index),
d => tempC2(index),
tin => ctemp3(index),
s => tempS3(index),
co => tempC3(index+1),
tout => ctemp3(index+1));
END GENERATE;
if2_25:IF index = 25 GENERATE
SUM_BIT4: FAdder PORT MAP (
a=>ctemp3(index),
b=>tempS2(index),
c=>tempC2(index),
s=>tempS3(index),
co=>tempC3(index+1));
END GENERATE;
if2_26to31:IF index >= 26 and index <= 31 GENERATE
SUM_BIT2: HAdder PORT MAP (
a=>tempS2(index),
b=>tempC2(index),
s=>tempS3(index),
c=>tempC3(index+1));
END GENERATE;
END GENERATE;
end Behavioral;
|
gpl-3.0
|
650aeeeb95cf017f89aaf70b65f5c2fe
| 0.559557 | 2.950807 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/Huffman.vhd
| 2 | 19,871 |
-------------------------------------------------------------------------------
-- File Name : Huffman.vhd
--
-- Project : JPEG_ENC
--
-- Module : Huffman
--
-- Content : Huffman Encoder
--
-- Description : Huffman encoder core
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity Huffman is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
huf_sm_settings : in T_SM_SETTINGS;
-- HOST IF
sof : in std_logic;
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
-- RLE
rle_buf_sel : out std_logic;
rd_en : out std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLI : in std_logic_vector(11 downto 0);
d_val : in std_logic;
rle_fifo_empty : in std_logic;
-- Byte Stuffer
bs_buf_sel : in std_logic;
bs_fifo_empty : out std_logic;
bs_rd_req : in std_logic;
bs_packed_byte : out std_logic_vector(7 downto 0)
);
end entity Huffman;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of Huffman is
type T_STATE is (IDLE, RUN_VLC, RUN_VLI, PAD);
constant C_M : integer := 23;
constant BLK_SIZE : integer := 64;
signal state : T_STATE;
signal rle_buf_sel_s : std_logic:='0';
signal first_rle_word : std_logic:='0';
signal word_reg : unsigned(C_M-1 downto 0):=(others =>'0');
signal bit_ptr : unsigned(4 downto 0):=(others =>'0');
signal num_fifo_wrs : unsigned(1 downto 0):=(others =>'0');
signal VLI_ext : unsigned(15 downto 0):=(others =>'0');
signal VLI_ext_size : unsigned(4 downto 0):=(others =>'0');
signal ready_HFW : std_logic:='0';
signal fifo_wbyte : std_logic_vector(7 downto 0):=(others =>'0');
signal fifo_wrt_cnt : unsigned(1 downto 0):=(others =>'0');
signal fifo_wren : std_logic:='0';
signal last_block : std_logic:='0';
signal image_area_size : unsigned(31 downto 0):=(others =>'0');
signal block_cnt : unsigned(27 downto 0):=(others =>'0');
signal VLC_size : unsigned(4 downto 0):=(others =>'0');
signal VLC : unsigned(15 downto 0):=(others =>'0');
signal VLC_DC_size : std_logic_vector(3 downto 0):=(others =>'0');
signal VLC_DC : unsigned(8 downto 0):=(others =>'0');
signal VLC_AC_size : unsigned(4 downto 0):=(others =>'0');
signal VLC_AC : unsigned(15 downto 0):=(others =>'0');
signal vlc_vld : std_logic:='0';
signal d_val_d1 : std_logic:='0';
signal d_val_d2 : std_logic:='0';
signal d_val_d3 : std_logic:='0';
signal d_val_d4 : std_logic:='0';
signal VLI_size_d : std_logic_vector(3 downto 0):=(others =>'0');
signal VLI_d : std_logic_vector(11 downto 0):=(others =>'0');
signal VLI_size_d1 : std_logic_vector(3 downto 0):=(others =>'0');
signal VLI_d1 : std_logic_vector(11 downto 0):=(others =>'0');
signal HFW_running : std_logic:='0';
signal runlength_r : std_logic_vector(3 downto 0):=(others =>'0');
signal VLI_size_r : std_logic_vector(3 downto 0):=(others =>'0');
signal VLI_r : std_logic_vector(11 downto 0):=(others =>'0');
signal rd_en_s : std_logic:='0';
signal pad_byte : std_logic_vector(7 downto 0):=(others =>'0');
signal pad_reg : std_logic:='0';
signal VLC_CR_DC_size : std_logic_vector(3 downto 0):=(others =>'0');
signal VLC_CR_DC : unsigned(10 downto 0):=(others =>'0');
signal VLC_CR_AC_size : unsigned(4 downto 0):=(others =>'0');
signal VLC_CR_AC : unsigned(15 downto 0):=(others =>'0');
signal start_pb_d1 : std_logic:='0';
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rle_buf_sel <= rle_buf_sel_s;
rd_en <= rd_en_s;
vlc_vld <= rd_en_s;
-------------------------------------------------------------------
-- latch FIFO Q
-------------------------------------------------------------------
p_latch_fifo : process(CLK, RST)
begin
if RST = '1' then
VLI_size_r <= (others => '0');
VLI_r <= (others => '0');
elsif CLK'event and CLK = '1' then
if d_val = '1' then
VLI_size_r <= VLI_size;
VLI_r <= VLI;
end if;
end if;
end process;
-------------------------------------------------------------------
-- DC_ROM Luminance
-------------------------------------------------------------------
U_DC_ROM : entity work.DC_ROM
port map
(
CLK => CLK,
RST => RST,
VLI_size => VLI_size,
VLC_DC_size => VLC_DC_size,
VLC_DC => VLC_DC
);
-------------------------------------------------------------------
-- AC_ROM Luminance
-------------------------------------------------------------------
U_AC_ROM : entity work.AC_ROM
port map
(
CLK => CLK,
RST => RST,
runlength => runlength,
VLI_size => VLI_size,
VLC_AC_size => VLC_AC_size,
VLC_AC => VLC_AC
);
-------------------------------------------------------------------
-- DC_ROM Chrominance
-------------------------------------------------------------------
U_DC_CR_ROM : entity work.DC_CR_ROM
port map
(
CLK => CLK,
RST => RST,
VLI_size => VLI_size,
VLC_DC_size => VLC_CR_DC_size,
VLC_DC => VLC_CR_DC
);
-------------------------------------------------------------------
-- AC_ROM Chrominance
-------------------------------------------------------------------
U_AC_CR_ROM : entity work.AC_CR_ROM
port map
(
CLK => CLK,
RST => RST,
runlength => runlength,
VLI_size => VLI_size,
VLC_AC_size => VLC_CR_AC_size,
VLC_AC => VLC_CR_AC
);
-------------------------------------------------------------------
-- Double Fifo
-------------------------------------------------------------------
U_DoubleFifo : entity work.DoubleFifo
port map
(
CLK => CLK,
RST => RST,
-- HUFFMAN
data_in => fifo_wbyte,
wren => fifo_wren,
-- BYTE STUFFER
buf_sel => bs_buf_sel,
rd_req => bs_rd_req,
fifo_empty => bs_fifo_empty,
data_out => bs_packed_byte
);
-------------------------------------------------------------------
-- RLE buf_sel
-------------------------------------------------------------------
p_rle_buf_sel : process(CLK, RST)
begin
if RST = '1' then
rle_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
rle_buf_sel_s <= not rle_buf_sel_s;
end if;
end if;
end process;
-------------------------------------------------------------------
-- mux for DC/AC ROM Luminance/Chrominance
-------------------------------------------------------------------
p_mux : process(CLK, RST)
begin
if RST = '1' then
VLC_size <= (others => '0');
VLC <= (others => '0');
elsif CLK'event and CLK = '1' then
-- DC
if first_rle_word = '1' then
-- luminance
if huf_sm_settings.cmp_idx < 2 then
VLC_size <= unsigned('0' & VLC_DC_size);
VLC <= resize(VLC_DC, VLC'length);
-- chrominance
else
VLC_size <= unsigned('0' & VLC_CR_DC_size);
VLC <= resize(VLC_CR_DC, VLC'length);
end if;
-- AC
else
-- luminance
if huf_sm_settings.cmp_idx < 2 then
VLC_size <= VLC_AC_size;
VLC <= VLC_AC;
-- chrominance
else
VLC_size <= VLC_CR_AC_size;
VLC <= VLC_CR_AC;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- Block Counter / Last Block detector
-------------------------------------------------------------------
p_blk_cnt : process(CLK, RST)
begin
if RST = '1' then
image_area_size <= (others => '0');
last_block <= '0';
elsif CLK'event and CLK = '1' then
image_area_size <= unsigned(img_size_x)*unsigned(img_size_y);
if sof = '1' then
block_cnt <= (others => '0');
elsif start_pb = '1' then
block_cnt <= block_cnt + 1;
end if;
if block_cnt = image_area_size(31 downto 5) then
last_block <= '1';
else
last_block <= '0';
end if;
end if;
end process;
VLI_ext <= unsigned("0000" & VLI_d1);
VLI_ext_size <= unsigned('0' & VLI_size_d1);
-------------------------------------------------------------------
-- delay line
-------------------------------------------------------------------
p_vli_dly : process(CLK)
begin
if CLK'event and CLK = '1' then
VLI_d1 <= VLI_r;
VLI_size_d1 <= VLI_size_r;
VLI_d <= VLI_d1;
VLI_size_d <= VLI_size_d1;
d_val_d1 <= d_val;
d_val_d2 <= d_val_d1;
d_val_d3 <= d_val_d2;
d_val_d4 <= d_val_d3;
end if;
end process;
-------------------------------------------------------------------
-- HandleFifoWrites
-------------------------------------------------------------------
p_HandleFifoWrites : process(CLK, RST)
begin
if RST = '1' then
ready_HFW <= '0';
fifo_wrt_cnt <= (others => '0');
fifo_wren <= '0';
fifo_wbyte <= (others => '0');
rd_en_s <= '0';
start_pb_d1 <= '0';
elsif CLK'event and CLK = '1' then
fifo_wren <= '0';
ready_HFW <= '0';
rd_en_s <= '0';
start_pb_d1 <= start_pb;
if start_pb_d1 = '1' then
rd_en_s <= '1' and not rle_fifo_empty;
end if;
if HFW_running = '1' and ready_HFW = '0' then
-- there is no at least one integer byte to write this time
if num_fifo_wrs = 0 then
ready_HFW <= '1';
if state = RUN_VLI then
rd_en_s <= '1' and not rle_fifo_empty;
end if;
-- single byte write to FIFO
else
fifo_wrt_cnt <= fifo_wrt_cnt + 1;
fifo_wren <= '1';
-- last byte write
if fifo_wrt_cnt + 1 = num_fifo_wrs then
ready_HFW <= '1';
if state = RUN_VLI then
rd_en_s <= '1' and not rle_fifo_empty;
end if;
fifo_wrt_cnt <= (others => '0');
end if;
end if;
end if;
case fifo_wrt_cnt is
when "00" =>
fifo_wbyte <= std_logic_vector(word_reg(C_M-1 downto C_M-8));
when "01" =>
fifo_wbyte <= std_logic_vector(word_reg(C_M-8-1 downto C_M-16));
when others =>
fifo_wbyte <= (others => '0');
end case;
if pad_reg = '1' then
fifo_wbyte <= pad_byte;
end if;
end if;
end process;
-- divide by 8
num_fifo_wrs <= bit_ptr(4 downto 3);
-------------------------------------------------------------------
-- Variable Length Processor FSM
-------------------------------------------------------------------
p_vlp : process(CLK, RST)
begin
if RST = '1' then
ready_pb <= '0';
first_rle_word <= '0';
state <= IDLE;
word_reg <= (others => '0');
bit_ptr <= (others => '0');
HFW_running <= '0';
pad_reg <= '0';
pad_byte <= (others => '0');
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
case state is
when IDLE =>
if start_pb = '1' then
first_rle_word <= '1';
state <= RUN_VLC;
end if;
when RUN_VLC =>
-- data valid DC or data valid AC
if (d_val_d1 = '1' and first_rle_word = '1') or
(d_val = '1' and first_rle_word = '0') then
for i in 0 to C_M-1 loop
if i < to_integer(VLC_size) then
word_reg(C_M-1-to_integer(bit_ptr)-i) <= VLC(to_integer(VLC_size)-1-i);
end if;
end loop;
bit_ptr <= bit_ptr + resize(VLC_size,bit_ptr'length);
-- HandleFifoWrites
HFW_running <= '1';
-- HandleFifoWrites completed
elsif HFW_running = '1' and
(num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then
-- shift word reg left to skip bytes already written to FIFO
word_reg <= shift_left(word_reg, to_integer(num_fifo_wrs & "000"));
-- adjust bit pointer after some bytes were written to FIFO
-- modulo 8 operation
bit_ptr <= bit_ptr - (num_fifo_wrs & "000");
HFW_running <= '0';
first_rle_word <= '0';
state <= RUN_VLI;
end if;
when RUN_VLI =>
if HFW_running = '0' then
for i in 0 to C_M-1 loop
if i < to_integer(VLI_ext_size) then
word_reg(C_M-1-to_integer(bit_ptr)-i)
<= VLI_ext(to_integer(VLI_ext_size)-1-i);
end if;
end loop;
bit_ptr <= bit_ptr + resize(VLI_ext_size,bit_ptr'length);
-- HandleFifoWrites
HFW_running <= '1';
-- HandleFifoWrites completed
elsif HFW_running = '1' and
(num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then
-- shift word reg left to skip bytes already written to FIFO
word_reg <= shift_left(word_reg, to_integer(num_fifo_wrs & "000"));
-- adjust bit pointer after some bytes were written to FIFO
-- modulo 8 operation
bit_ptr <= bit_ptr - (num_fifo_wrs & "000");
HFW_running <= '0';
-- end of block
if rle_fifo_empty = '1' then
-- end of segment
if bit_ptr - (num_fifo_wrs & "000") /= 0 and last_block = '1' then
state <= PAD;
else
ready_pb <= '1';
state <= IDLE;
end if;
else
state <= RUN_VLC;
end if;
end if;
-- end of segment which requires bit padding
when PAD =>
if HFW_running = '0' then
-- 1's bit padding to integer number of bytes
for i in 0 to 7 loop
if i < bit_ptr then
pad_byte(7-i) <= word_reg(C_M-1-i);
else
pad_byte(7-i) <= '1';
end if;
end loop;
pad_reg <= '1';
bit_ptr <= to_unsigned(8, bit_ptr'length);
-- HandleFifoWrites
HFW_running <= '1';
elsif HFW_running = '1' and
(num_fifo_wrs = 0 or fifo_wrt_cnt + 1 = num_fifo_wrs) then
bit_ptr <= (others => '0');
HFW_running <= '0';
pad_reg <= '0';
ready_pb <= '1';
state <= IDLE;
end if;
when others =>
end case;
if sof = '1' then
bit_ptr <= (others => '0');
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
792863db20f17b5d16e542b78ca5d31f
| 0.399829 | 4.299221 | false | false | false | false |
vinodpa/openPowerlink-FPGA
|
Examples/ipcore/common/openmac/src/openFILTER.vhd
| 3 | 10,167 |
-------------------------------------------------------------------------------
-- OpenFILTER
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv and RxDat have to be synchron to Clk
-- The following Conditions are checked:
-- RxDV >163.64µsec HIGH -> invalid
-- RxDV <0.64µsec LOW -> invalid
-- RxDV 4x <5.12µsec HIGH -> invalid
-- RxDV >5.12µsec HIGH -> valid
-- RxErr HIGH -> invalid
-- if invalid deactivation of port, until RxDv and RxErr > 10.24µsec low
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY openFILTER is
Generic (
bypassFilter : boolean := false
);
Port ( Rst : in std_logic;
Clk : in std_logic;
nCheckShortFrames : in std_logic := '0'; -- Rx Port von Hub;
RxDvIn : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
RxDatOut : out std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
TxDatIn : in std_logic_vector(1 downto 0);
TxEnOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
RxErr : in std_logic := '0'
);
END ENTITY openFILTER;
ARCHITECTURE rtl OF openFILTER IS
type aRxSet is record
RxDv : std_logic;
RxDat: std_logic_vector(1 downto 0);
end record;
type aRxSetArr is array (3 downto 0) of aRxSet;
type aFiltState is (fs_init, fs_GAP2short, fs_GAPext, fs_GAPok, fs_FRMnopre,
fs_FRMpre2short, fs_FRMpreOk, fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll);
signal FiltState : aFiltState;
signal RxDel : aRxSetArr;
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
BEGIN
disFilter : if bypassFilter generate
begin
RxDvOut <= RxDvIn;
RxDatOut <= RxDatIn;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
end generate;
enFilter : if not bypassFilter generate
begin
-- IN --
RxDel(0).RxDv <= RxDvIn;
RxDel(0).RxDat <= RxDatIn;
BlockRxPort <= '1' when FiltState = fs_FRMnopre or FiltState = fs_BlockAll or LastFrameNOK = '1' else '0';
-- OUTPUT MUX --
RxDvOut <= '0' when BlockRxPort = '1' else
RxDel(3).RxDv when FrameShift = '1' else
RxDel(1).RxDv;
RxDatOut <= "00" when BlockRxPort = '1' else
RxDel(3).RxDat when FrameShift = '1' else
RxDel(1).RxDat;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
fsm: PROCESS(Rst, Clk)
VARIABLE RstStCnt : std_logic;
begin
if Rst = '1' then
StCnt <= (others => '0');
FiltState <= fs_init;
FrameShift <= '0';
RxDel(3 downto 1) <= (others => ('0',"00"));
LastFrameNOK <= '0';
elsif rising_edge(Clk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := '0';
case FiltState is
-------------------------------- INIT ---------------------------------------
when fs_init =>
FiltState <= fs_GAP2short; RstStCnt := '1';
-------------------------------- GAP 2 SHORT --------------------------------
when fs_GAP2short =>
FrameShift <= '0';
IF StCnt(4) = '1' then FiltState <= fs_GAPext; END IF; -- 360ns
IF RxDel(0).RxDv = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- Gap < 360 ns -> too short -> Block Filter
-------------------------------- GAP EXTEND ---------------------------------
when fs_GAPext =>
IF StCnt(5 downto 0) = "101110" then FiltState <= fs_GAPok; END IF;
IF RxDel(0).RxDv = '1' then -- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := '1';
FrameShift <= '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- GAP OK -------------------------------------
when fs_GAPok =>
IF RxDel(0).RxDv = '1' then
RstStCnt := '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- FRAME, BUT STILL NO PREAMBLE ---------------
when fs_FRMnopre =>
IF StCnt(5) = '1' or -- no preamble for >=660 ns -> Block Filter
RxDel(0).RxDat = "11" or RxDel(0).RxDat = "10" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
elsif RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; RstStCnt := '1'; -- preamble starts -> Check Preamble
END IF;
-------------------------------- FRAME CHECK PREAMBLE TOO SHORT --------------
when fs_FRMpre2short =>
IF RxDel(0).RxDat /= "01" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
ELSIF StCnt(3) = '1' then FiltState <= fs_FRMpreOk; END IF; -- preamble ok for 180 ns -> Preamble OK
-------------------------------- FRAME CHECK PREAMBLE OK ---------------
when fs_FRMpreOk =>
IF RxDel(0).RxDat /= "01" then FiltState <= fs_FRMok; END IF; -- preamble done -> Start Frame
IF (StCnt(5) = '1' and StCnt(2) = '1') or -- preamble to long for 740 ns -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF;
LastFrameNOK <= '0'; -- preamble is OK
-------------------------------- FRAME OK -----------------------------------
when fs_FRMok =>
IF StCnt(13) = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- FRAME > 163,842 us -> too long -> Block Filter
IF RxDel(0).RxDv = '0' and
RxDel(1).RxDv = '0' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- FRAME [163,842 us] -> OK -> Start GAP
-------------------------------- Block Filter -------------------------------
when fs_BlockAll =>
IF StCnt(2) = '1' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- Block for 100 nsec
IF RxDel(0).RxDv = '1' then RstStCnt := '1'; END IF; -- RxDv != '0' -> Reset Wait Period
LastFrameNOK <= '1'; -- block next rx frame (until receive a valid preamble)
when others =>
FiltState <= fs_init;
end case;
IF RxErr = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- RxErr -> Block Filter
-- State Counter --
StCnt <= StCnt + 1;
if RstStCnt = '1' then StCnt <= (others => '0'); end if;
end if;
end process;
end generate;
END rtl;
|
gpl-2.0
|
e8e390c8537a268dbdf1968c57c95028
| 0.481656 | 4.492709 | false | false | false | false |
miree/vhdl_cores
|
delay/delay.vhd
| 1 | 1,779 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delay is
generic (
depth : integer;
bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
d_i : in std_logic_vector ( bit_width-1 downto 0 );
q_o : out std_logic_vector ( bit_width-1 downto 0 )
);
end entity;
architecture rtl of delay is
-- calculate the number of words from
-- the depth (which is like the address width)
constant number_of_words : integer := 2**depth;
-- define data type of the storage array
type fifo_data_array is array ( 0 to number_of_words-1)
of std_logic_vector ( bit_width-1 downto 0);
-- define the storage array
signal fifo_data : fifo_data_array;
-- read and write index pointers
-- give them one bit more then needed to quickly check for overflow
-- by looking at the most significant bit (tip from Matthias Kreider)
signal w_idx : std_logic_vector ( depth downto 0 );
signal r_idx : std_logic_vector ( depth downto 0 );
begin
main: process (clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
-- force reset state
w_idx <= (others => '0');
r_idx <= (others => '0');
q_o <= (others => '0');
else
-- writing
fifo_data(to_integer(unsigned(w_idx(depth-1 downto 0)))) <= d_i;
w_idx <= std_logic_vector(unsigned(w_idx) + 1);
-- reading
r_idx <= r_idx;
q_o <= (others => '0');
if (r_idx(depth) xor w_idx(depth)) = '1' then
q_o <= fifo_data(to_integer(unsigned(r_idx(depth-1 downto 0))));
r_idx <= std_logic_vector(unsigned(r_idx) + 1);
end if;
end if;
end if;
end process;
end architecture;
|
mit
|
b46b7ac7e65e0fc8605d9131004aee20
| 0.580101 | 3.343985 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
CPU/Control.vhd
| 1 | 9,948 |
library IEEE;
use IEEE.std_logic_1164.all;
use work.cpu_lib.all;
entity control is
port( clock : in std_logic;
reset : in std_logic;
instrReg : in bit16;
compout : in std_logic;
ready : in std_logic;
progCntrWr : out std_logic;
progCntrRd : out std_logic;
addrRegWr : out std_logic;
addrRegRd : out std_logic;
outRegWr : out std_logic;
outRegRd : out std_logic;
shiftSel : out t_shift;
aluSel : out t_alu;
compSel : out t_comp;
opRegRd : out std_logic;
opRegWr : out std_logic;
instrWr : out std_logic;
regSel : out t_reg;
regRd : out std_logic;
regWr : out std_logic;
rw : out std_logic;
vma : out std_logic
);
end control;
architecture rtl of control is
signal current_state, next_state : state;
begin
nxtstateproc: process( current_state, instrReg, compout, ready)
begin
progCntrWr <= '0';
progCntrRd <= '0';
addrRegWr <= '0';
outRegWr <= '0';
outRegRd <= '0';
shiftSel <= shftpass;
aluSel <= alupass;
compSel <= eq;
opRegRd <= '0';
opRegWr <= '0';
instrWr <= '0';
regSel <= "000";
regRd <= '0';
regWr <= '0';
rw <= '0';
vma <= '0';
case current_state is
when reset1 =>
aluSel <= zero after 1 ns;
shiftSel <= shftpass;
next_state <= reset2;
when reset2 =>
aluSel <= zero;
shiftSel <= shftpass;
outRegWr <= '1';
next_state <= reset3;
when reset3 =>
outRegRd <= '1';
next_state <= reset4;
when reset4 =>
outRegRd <= '1';
progCntrWr <= '1';
addrRegWr <= '1';
next_state <= reset5;
when reset5 =>
vma <= '1';
rw <= '0';
next_state <= reset6;
when reset6 =>
vma <= '1';
rw <= '0';
if ready = '1' then
instrWr <= '1';
next_state <= execute;
else
next_state <= reset6;
end if;
when execute =>
case instrReg(15 downto 11) is
when "00000" => --- nop
next_state <= incPc;
when "00001" => --- load
regSel <= instrReg(5 downto 3);
regRd <= '1';
next_state <= load2;
when "00010" => --- store
regSel <= instrReg(2 downto 0);
regRd <= '1';
next_state <= store2;
when "00011" => ----- move
regSel <= instrReg(5 downto 3);
regRd <= '1';
aluSel <= alupass;
shiftSel <= shftpass;
next_state <= move2;
when "00100" => ---- loadI
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
next_state <= loadI2;
when "00101" => ---- BranchImm
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
next_state <= braI2;
when "00110" => ---- BranchGTImm
regSel <= instrReg(5 downto 3);
regRd <= '1';
next_state <= bgtI2;
when "00111" => ------- inc
regSel <= instrReg(2 downto 0);
regRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
next_state <= inc2;
when others =>
next_state <= incPc;
end case;
when load2 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
addrregWr <= '1';
next_state <= load3;
when load3 =>
vma <= '1';
rw <= '0';
next_state <= load4;
when load4 =>
vma <= '1';
rw <= '0';
regSel <= instrReg(2 downto 0);
regWr <= '1';
next_state <= incPc;
when store2 =>
regSel <= instrReg(2 downto 0);
regRd <= '1';
addrregWr <= '1';
next_state <= store3;
when store3 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
next_state <= store4;
when store4 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
vma <= '1';
rw <= '1';
next_state <= incPc;
when move2 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
aluSel <= alupass;
shiftsel <= shftpass;
outRegWr <= '1';
next_state <= move3;
when move3 =>
outRegRd <= '1';
next_state <= move4;
when move4 =>
outRegRd <= '1';
regSel <= instrReg(2 downto 0);
regWr <= '1';
next_state <= incPc;
when loadI2 =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= loadI3;
when loadI3 =>
outregRd <= '1';
next_state <= loadI4;
when loadI4 =>
outregRd <= '1';
progcntrWr <= '1';
addrregWr <= '1';
next_state <= loadI5;
when loadI5 =>
vma <= '1';
rw <= '0';
next_state <= loadI6;
when loadI6 =>
vma <= '1';
rw <= '0';
if ready = '1' then
regSel <= instrReg(2 downto 0);
regWr <= '1';
next_state <= incPc;
else
next_state <= loadI6;
end if;
when braI2 =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= braI3;
when braI3 =>
outregRd <= '1';
next_state <= braI4;
when braI4 =>
outregRd <= '1';
progcntrWr <= '1';
addrregWr <= '1';
next_state <= braI5;
when braI5 =>
vma <= '1';
rw <= '0';
next_state <= braI6;
when braI6 =>
vma <= '1';
rw <= '0';
if ready = '1' then
progcntrWr <= '1';
next_state <= loadPc;
else
next_state <= braI6;
end if;
when bgtI2 =>
regSel <= instrReg(5 downto 3);
regRd <= '1';
opRegWr <= '1';
next_state <= bgtI3;
when bgtI3 =>
opRegRd <= '1';
regSel <= instrReg(2 downto 0);
regRd <= '1';
compsel <= gt;
next_state <= bgtI4;
when bgtI4 =>
opRegRd <= '1' after 1 ns;
regSel <= instrReg(2 downto 0);
regRd <= '1';
compsel <= gt;
if compout = '1' then
next_state <= bgtI5;
else
next_state <= incPc;
end if;
when bgtI5 =>
progcntrRd <= '1';
alusel <= inc;
shiftSel <= shftpass;
next_state <= bgtI6;
when bgtI6 =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= bgtI7;
when bgtI7 =>
outregRd <= '1';
next_state <= bgtI8;
when bgtI8 =>
outregRd <= '1';
progcntrWr <= '1';
addrregWr <= '1';
next_state <= bgtI9;
when bgtI9 =>
vma <= '1';
rw <= '0';
next_state <= bgtI10;
when bgtI10 =>
vma <= '1';
rw <= '0';
if ready = '1' then
progcntrWr <= '1';
next_state <= loadPc;
else
next_state <= bgtI10;
end if;
when inc2 =>
regSel <= instrReg(2 downto 0);
regRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= inc3;
when inc3 =>
outregRd <= '1';
next_state <= inc4;
when inc4 =>
outregRd <= '1';
regsel <= instrReg(2 downto 0);
regWr <= '1';
next_state <= incPc;
when loadPc =>
progcntrRd <= '1';
next_state <= loadPc2;
when loadPc2 =>
progcntrRd <= '1';
addrRegWr <= '1';
next_state <= loadPc3;
when loadPc3 =>
vma <= '1';
rw <= '0';
next_state <= loadPc4;
when loadPc4 =>
vma <= '1';
rw <= '0';
if ready = '1' then
instrWr <= '1';
next_state <= execute;
else
next_state <= loadPc4;
end if;
when incPc =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
next_state <= incPc2;
when incPc2 =>
progcntrRd <= '1';
alusel <= inc;
shiftsel <= shftpass;
outregWr <= '1';
next_state <= incPc3;
when incPc3 =>
outregRd <= '1';
next_state <= incPc4;
when incPc4 =>
outregRd <= '1';
progcntrWr <= '1';
addrregWr <= '1';
next_state <= incPc5;
when incPc5 =>
vma <= '1';
rw <= '0';
next_state <= incPc6;
when incPc6 =>
vma <= '1';
rw <= '0';
if ready = '1' then
instrWr <= '1';
next_state <= execute;
else
next_state <= incPc6;
end if;
when others =>
next_state <= incPc;
end case;
end process;
controlffProc: process(clock, reset)
begin
if reset = '1' then
current_state <= reset1 after 1 ns;
elsif clock'event and clock = '1' then
current_state <= next_state after 1 ns;
end if;
end process;
end rtl;
|
gpl-3.0
|
9bbd4fa3facdae35936a728a2b9a75ce
| 0.412545 | 4.209903 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/checkEndTb.vhd
| 1 | 1,208 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity checkEndTb is
end checkEndTb;
-- Testes funcionais para entidade CheckEnd
architecture Stimulus of checkEndTb is
signal s_try0, s_try1, s_p, s_n, s_t1, s_t0 : std_logic_vector(3 downto 0);
signal s_clock, s_reset, s_isBlink : std_logic;
signal s_erra, s_cert : std_logic_vector(3 downto 0);
begin
uut : entity work.checkEnd(Behavioral)
port map(try0 => s_try0,
try1 => s_try1,
p => s_p,
n => s_n,
t1 => s_t1,
t0 => s_t0,
clock => s_clock,
reset => s_reset,
isBlink => s_isBlink,
cert => s_cert,
erra => s_erra);
clk:process
begin
s_clock <= '1';
wait for 15 ns;
s_clock <= '0';
wait for 15 ns;
end process;
comb_proc:process
begin
s_reset <= '0';
s_erra <= "0011";
s_cert <= "0001";
s_try1 <= "0000";
s_try0 <= "0001";
wait for 40 ns;
s_erra <= "0100";
s_cert <= "0000";
s_try1 <= "0000";
s_try0 <= "0001";
wait for 40 ns;
s_reset <= '1';
wait for 40 ns;
end process;
end Stimulus;
|
gpl-2.0
|
0daa695034b916470cd5f53ee0f5cdd3
| 0.551325 | 2.465306 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/with screen/MIPSconPantallaME/MemoriaDeInstrucciones.vhd
| 1 | 4,226 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:33:34 11/21/2012
-- Design Name:
-- Module Name: MemoriaDeInstrucciones - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MemoriaDeInstrucciones is
--generic( P: integer:=32; -- ancho de palabra 32 bits
-- N: integer:=32; -- nº de palabras 32 de 32
--M: integer:= 64; -- grupos de 4 palabras (2^32 / 4)=1073741824
--tam_addr: integer:=5); -- ancho dirección 2^5=32
port( Clock: in std_logic;
ADDR: in std_logic_vector(4 downto 0);
--write_addr: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0)
--DW: in std_logic_vector(31 downto 0);
--R: in std_logic
--W: in std_logic
);
end MemoriaDeInstrucciones;
architecture Behavioral of MemoriaDeInstrucciones is
type RamType is array (0 to 31) of bit_vector(31 downto 0);
impure function InitRamFromFile (RamFileName : in string) return RamType is
FILE RamFile : text is in RamFileName;
variable RamFileLine : line;
variable RAM : RamType;
begin
for I in RamType'range loop
readline (RamFile, RamFileLine);
read (RamFileLine, RAM(I));
end loop;
return RAM;
end function;
signal RAM : RamType := InitRamFromFile("partidaGuardada.txt");
-- signal RAM : RamType :=(
--"00000000000000000000000000100010", --sub 0 0 0 #contador
--"00000000001000010000100000100010", --sub 1 1 1 #g(n-1)
--"00000000010000100001000000100010", --sub 2 2 2 #g(n)
--"00000000011000110001100000100010", --sub 3 3 3 #g(n+1)
--"00000000100001000010000000100010", --sub 4 4 4 #maximo
--"00000000101001010010100000100010", --sub 5 5 5 #indice array
--"00000000110001100011000000100010", --sub 6 6 6 #es un 0
--"01000000010000100000000000000001", --addi 2 2 1 #g(n) = 1 y g(n-1) = 0
--"01000000100001000000000000000101", --addi 4 4 5 #inicializa maximo a 5
--"10101100001000010000000000000000", --sw 1 1 0 #almacenamos las primeras componentes g(0) y g(1)
--"10101100010000100000000000000000", --sw 2 2 0 -- store r2, r2[0] r1 guardamos en la dir r1+0
--"01000000101001010000000000000010", --addi 5 5 2 #se inicializa a 2
--"00010000000001000000000000000111", --beq 0 4 buclefin1 // fibo
--"00000000010000010001100000100000", --add 3 2 1 # g(n+1) <= g(n) + g(n-1)
--"00000000011000010000100000100010", --sub 1 3 1 # g(n-1) <= g(n) = g(n+1) - g(n-1)
--"00000000011001100001000000100010", --sub 2 3 6 # g(n) <= g(n+1) + 0
--"10101100101000110000000000000000", --sw 3 5 0 # guardamos g(n+1) en el indice del array
--"01000000101001010000000000000001", --addi 5 5 1 # actualizamos el indice del array
--"01000000000000000000000000000001", --addi 0 0 1 # actualizamos el contador
--"11111100000000000000000000001100", --j fibo
--"11111100000000000000000000010101",
--"11111100000000000000000000010100",
--
--
--"11111100000000000000000000000101",--jump
--"00010100001000000000000000000011", --bne
--"00011000001000000000000000000010",--bgt al 4
--"01001011111001100000000000001010",--andi R6, R31, 10
--"10001100000000100000000000000000",--lw R2, R0, 0
--"00011000001000000000000000001000",--bgt
--"00010000001000000000000000000011",--beq
--"00000000111001110011100000100010",--resta R7, R7, R7 NOP
--"00000000111001110011100000100010",--resta R7, R7, R7 NOP
--"00000000000000010000000000100000");
begin
--Salida registros
-- Lectura
process(Clock)
begin
if (Clock'event and Clock='1') then
DR <= to_stdlogicvector(RAM(conv_integer(ADDR)));
end if;
end process;
end Behavioral;
|
gpl-2.0
|
a38591618fb2d79dec9089d244a45429
| 0.679602 | 3.684394 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 3/cliente_em_fila.vhd
| 1 | 763 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity cliente_em_fila is
port( client : in std_logic;
reset : in std_logic;
binOut2 : out std_logic_vector(6 downto 0);
compareTo: in std_logic_vector(6 downto 0);
outLed : out std_logic);
end cliente_em_fila;
architecture Behavioral of cliente_em_fila is
signal count : unsigned(6 downto 0);
begin
process(client, reset, compareTo)
begin
if(compareTo="1100011") then
outLed <='0';
elsif(unsigned(compareTo)<count) then
outLed <= '1';
else
outLed <='0';
end if;
if(reset='1') then
count <= (others => '0');
elsif(rising_edge(client)) then
count <= count + 1;
end if;
end process;
binOut2<= std_logic_vector(count);
end Behavioral;
|
gpl-2.0
|
3fc13f1994a5325e6b275ebd5c5c7696
| 0.664482 | 2.857678 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Blink.vhd
| 1 | 983 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Blink is
port( enable : in std_logic;
numberIn : in std_logic_vector(3 downto 0);
numberOut: out std_logic_vector(3 downto 0);
clock : in std_logic;
load : in std_logic);
end Blink;
-- Entidade que faz piscar a uma certa frequência o valor de entrada caso o enable estiver ligado('1').
architecture Behavioral of Blink is
signal checkblink : std_logic;
signal s_nin : std_logic_vector(3 downto 0);
begin
process(clock, enable, load)
begin
if(enable = '1') then
if(rising_edge(clock))then
if(checkblink = '1') then
numberOut <= s_nin;
checkblink<= '0';
else
checkblink<= '1';
numberOut <= "1111";
end if;
end if;
else
checkblink<= '0';
numberOut <= s_nin;
end if;
if(load = '1') then
s_nin <= numberIn;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
1db423e20d59b215a789b7859ebf821d
| 0.654786 | 2.913947 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/alu_tb.vhd
| 1 | 5,101 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity alu_tb is
end alu_tb;
architecture Behavior of alu_tb is
constant I_clk_period : time := 10 ns;
signal I_clk : std_logic := '0';
signal I_en: std_logic := '0';
signal I_imm: std_logic_vector(XLEN-1 downto 0) := X"00000000";
signal I_dataS1: std_logic_vector(XLEN-1 downto 0) := X"00000000";
signal I_dataS2: std_logic_vector(XLEN-1 downto 0) := X"00000000";
signal I_reset: std_logic;
signal I_aluop: aluops_t;
signal I_enter_interrupt: boolean := false;
signal O_busy: std_logic;
signal O_data: std_logic_vector(31 downto 0);
signal O_PC: std_logic_vector(XLEN-1 downto 0);
signal O_in_interrupt: boolean := false;
signal O_interrupt_enabled: boolean := false;
signal O_in_trap: boolean := false;
signal O_lt, O_ltu, O_eq: boolean := false;
begin
-- instantiate unit under test
uut: entity work.alu port map(
I_clk => I_clk,
I_en => I_en,
I_dataS1 => I_dataS1,
I_dataS2 => I_dataS2,
I_reset => I_reset,
I_aluop => I_aluop,
O_busy => O_busy,
O_data => O_data,
O_lt => O_lt,
O_ltu => O_ltu,
O_eq => O_eq
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
-- test sub/add
wait until falling_edge(I_clk);
I_en <= '1';
I_dataS1 <= X"0000000F";
I_dataS2 <= X"00000001";
I_aluop <= ALU_SUB;
wait until falling_edge(I_clk);
assert O_data = X"0000000E" report "wrong output value" severity failure;
I_aluop <= ALU_ADD;
wait until falling_edge(I_clk);
assert O_data = X"00000010" report "wrong output value" severity failure;
-- test xor
wait until falling_edge(I_clk);
I_en <= '1';
I_dataS1 <= X"00000055";
I_dataS2 <= X"000000FF";
I_aluop <= ALU_XOR;
wait until falling_edge(I_clk);
assert O_data = X"000000AA" report "wrong output value" severity failure;
-- test shift operations
wait until falling_edge(I_clk);
I_dataS1 <= X"0000000F";
I_dataS2 <= X"00000004";
I_aluop <= ALU_SLL;
wait until falling_edge(O_busy);
assert O_data = X"000000F0" report "wrong output value" severity failure;
wait until falling_edge(I_clk);
I_dataS1 <= X"0000000F";
I_dataS2 <= X"00000008";
I_aluop <= ALU_SLL;
wait until falling_edge(O_busy);
assert O_data = X"00000F00" report "wrong output value" severity failure;
wait until falling_edge(I_clk);
I_dataS1 <= X"0000000F";
I_dataS2 <= X"00000000"; -- test shift by zero, should output original value
I_aluop <= ALU_SLL;
wait until falling_edge(O_busy);
assert O_data = X"0000000F" report "wrong output value" severity failure;
wait until falling_edge(I_clk);
I_dataS1 <= X"F0000000";
I_dataS2 <= X"00000004";
I_aluop <= ALU_SRA;
wait until falling_edge(O_busy);
assert O_data = X"FF000000" report "wrong output value" severity failure;
I_aluop <= ALU_SRL;
wait until falling_edge(O_busy);
assert O_data = X"0F000000" report "wrong output value" severity failure;
wait until falling_edge(I_clk);
I_dataS1 <= X"0000000F";
I_dataS2 <= X"00000008";
I_aluop <= ALU_SLL;
wait until falling_edge(O_busy);
assert O_data = X"00000F00" report "wrong output value" severity failure;
wait until falling_edge(I_clk);
I_dataS1 <= X"F0000000";
I_dataS2 <= X"00000004";
I_aluop <= ALU_SRA;
wait until falling_edge(O_busy);
assert O_data = X"FF000000" report "wrong output value" severity failure;
I_aluop <= ALU_SRL;
wait until falling_edge(O_busy);
assert O_data = X"0F000000" report "wrong output value" severity failure;
-- test flags
wait until falling_edge(I_clk);
I_dataS1 <= X"F0000000";
I_dataS2 <= X"0000000F";
I_aluop <= ALU_SUB;
wait until falling_edge(I_clk);
assert O_data = X"EFFFFFF1" report "wrong output value" severity failure;
assert O_lt = true report "wrong output value" severity failure;
assert O_ltu = false report "wrong output value" severity failure;
assert O_eq = false report "wrong output value" severity failure;
wait until falling_edge(I_clk);
I_dataS1 <= X"F0000000";
I_dataS2 <= X"F0000000";
I_aluop <= ALU_SUB;
wait until falling_edge(I_clk);
assert O_data = X"00000000" report "wrong output value" severity failure;
assert O_lt = false report "wrong output value" severity failure;
assert O_ltu = false report "wrong output value" severity failure;
assert O_eq = true report "wrong output value" severity failure;
wait until falling_edge(I_clk);
I_dataS1 <= X"00000001";
I_dataS2 <= X"00000002";
I_aluop <= ALU_SUB;
wait until falling_edge(I_clk);
assert O_data = X"FFFFFFFF" report "wrong output value" severity failure;
assert O_lt = true report "wrong output value" severity failure;
assert O_ltu = true report "wrong output value" severity failure;
assert O_eq = false report "wrong output value" severity failure;
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
d0bc19f4c7631e26103f9e6bb91cdc33
| 0.674182 | 2.914857 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/JPEG_PKG.vhd
| 2 | 3,751 |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2009 --
-- --
--------------------------------------------------------------------------------
--
-- Title : JPEG_PKG
-- Design : JPEG_ENC
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : JPEG_PKG.VHD
-- Created : Sat Mar 7 2009
--
--------------------------------------------------------------------------------
--
-- Description : Package for JPEG core
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package JPEG_PKG is
-- do not change, constant
constant C_HDR_SIZE : integer := 623;
-- 24 bit format RGB 888 bits
-- 16 bit format RGB 565 bits
constant C_PIXEL_BITS : integer := 24;
type T_SM_SETTINGS is record
x_cnt : unsigned(15 downto 0);
y_cnt : unsigned(15 downto 0);
cmp_idx : unsigned(2 downto 0);
end record;
constant C_SM_SETTINGS : T_SM_SETTINGS :=
(
(others => '0'),
(others => '0'),
(others => '0')
);
function log2(n : natural) return natural;
end package JPEG_PKG;
package body JPEG_PKG is
-----------------------------------------------------------------------------
function log2(n : natural)
return natural is
begin
for i in 0 to 31 loop
if (2**i) >= n then
return i;
end if;
end loop;
return 32;
end log2;
-----------------------------------------------------------------------------
end package body JPEG_PKG;
|
bsd-2-clause
|
68cd2c669713d0eabf1532f1ae45f738
| 0.469741 | 5.145405 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/ram/sram_external_wb8.vhd
| 1 | 1,399 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_external_wb8 is
generic(
ADDRBITS: integer := 19;
DATABITS: integer := 8
);
port(
-- signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
WE_I: in std_logic;
ADR_I: in std_logic_vector(ADDRBITS-1 downto 0);
DAT_I: in std_logic_vector(DATABITS-1 downto 0);
DAT_O: out std_logic_vector(DATABITS-1 downto 0);
ACK_O: out std_logic;
-- interface to external SRAM
O_sram_adr: out std_logic_vector(ADDRBITS-1 downto 0);
O_sram_we: out std_logic := '1';
O_sram_ce: out std_logic := '1';
O_sram_oe: out std_logic := '1';
IO_sram_dat: inout std_logic_vector(DATABITS-1 downto 0) := X"00"
);
end sram_external_wb8;
architecture Behavioral of sram_external_wb8 is
begin
sram_external_instance: entity work.sram_external port map(
I_addr => ADR_I,
I_data => DAT_I,
I_en => STB_I,
I_we => (WE_I and STB_I),
O_data => DAT_O,
IO_external_data => IO_sram_dat,
O_external_addr => O_sram_adr(ADDRBITS-1 downto 0),
O_external_ce => O_sram_ce,
O_external_oe => O_sram_oe,
O_external_we => O_sram_we
);
process(CLK_I, STB_I)
variable ack: std_logic := '0';
begin
if rising_edge(CLK_I) then
ack := '0';
if STB_I = '1' then
ack := '1';
end if;
end if;
ACK_O <= ack and STB_I;
end process;
end Behavioral;
|
mit
|
e8deb5b0c3e02b539612e5657dfb56b7
| 0.636169 | 2.557587 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/sys_wb8_tb.vhd
| 1 | 1,673 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity sys_wb8_tb is
end sys_wb8_tb;
architecture Behavior of sys_wb8_tb is
component sys_toplevel_wb8
Port(
I_clk: in std_logic;
I_reset: in std_logic := '0';
I_serial_rx: in std_logic;
I_interrupt: in std_logic;
O_leds: out std_logic_vector(7 downto 0) := X"00";
O_serial_tx: out std_logic;
O_vga_vsync, O_vga_hsync, O_vga_r, O_vga_g, O_vga_b: out std_logic := '0'
);
end component;
constant I_clk_period : time := 10 ns;
signal I_clk : std_logic := '0';
signal I_reset: std_logic := '0';
signal I_serial_rx, O_serial_tx: std_logic := '0';
signal I_interrupt: std_logic := '0';
signal O_leds: std_logic_vector(7 downto 0) := X"00";
signal O_vga_vsync, O_vga_hsync, O_vga_r, O_vga_g, O_vga_b: std_logic := '0';
begin
-- instantiate unit under test
uut: sys_toplevel_wb8 port map(
I_clk => I_clk,
I_reset => I_reset,
I_serial_rx => I_serial_rx,
I_interrupt => I_interrupt,
O_leds => O_leds,
O_serial_tx => O_serial_tx,
O_vga_vsync => O_vga_vsync,
O_vga_hsync => O_vga_hsync,
O_vga_r => O_vga_r,
O_vga_g => O_vga_g,
O_vga_b => O_vga_b
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
I_reset <= '0';
wait for 10 * I_clk_period;
I_reset <= '1';
wait for 100 * I_clk_period;
I_reset <= '0';
wait for 10* I_clk_period;
I_reset <= '1';
wait for 10000 * I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
a5912516763952440b94367975b5bfdc
| 0.622833 | 2.421129 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/streamer/vhdl/fx2_jpeg_streamer.vhd
| 2 | 5,205 |
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013, Jahanzeb Ahmad
-- Copyright (c) 2015, Florent Kermarrec
--
-- fx2_jpeg_streamer
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- L I B R A R I E S
-------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- E N T I T Y
-------------------------------------------------------------------------------
entity fx2_jpeg_streamer is
port
(
-- Clock / Reset
---------------------------------------------------------------------------
rst : in std_logic;
clk : in std_logic;
-- Sink
---------------------------------------------------------------------------
sink_stb : in std_logic;
sink_ack : out std_logic;
sink_data : in std_logic_vector(7 downto 0);
-- FX2 slave fifo interface
---------------------------------------------------------------------------
fx2_data : inout std_logic_vector(7 downto 0);
fx2_full_n : in std_logic;
fx2_empty_n : in std_logic;
fx2_addr : out std_logic_vector(1 downto 0);
fx2_cs_n : out std_logic;
fx2_wr_n : out std_logic;
fx2_rd_n : out std_logic;
fx2_oe_n : out std_logic;
fx2_pktend_n : out std_logic
);
end entity fx2_jpeg_streamer;
-------------------------------------------------------------------------------
-- A R C H I T E C T U R E
-------------------------------------------------------------------------------
architecture rtl of fx2_jpeg_streamer is
--===================================--
-- Signals Declaration
--===================================--
signal packet_sent : std_logic;
signal packet_fid : std_logic;
signal packet_counter : unsigned(11 downto 0);
signal sink_data_d : std_logic_vector(7 downto 0);
type fsm_states is (S_RESET,
S_WAIT,
S_PACKET_END,
S_SEND_DATA);
signal fsm_state : fsm_states;
signal sending_data : std_logic;
begin
--===========================================================================
-- Static assignements
--===========================================================================
fx2_cs_n <= '0';
fx2_oe_n <= '1';
fx2_rd_n <= '1';
fx2_addr <= "10";
--===========================================================================
-- Main process
--===========================================================================
main_p : process(rst, clk)
begin
if rst = '1' then
fx2_wr_n <= '1';
fx2_pktend_n <= '1';
packet_fid <= '0';
packet_sent <= '0';
packet_counter <= (others => '0');
sink_data_d <= (others => '0');
fsm_state <= S_RESET;
elsif falling_edge(clk) then
fx2_wr_n <= '1';
fx2_pktend_n <= '1';
case fsm_state is
when S_RESET =>
packet_fid <= '0';
packet_sent <= '0';
fsm_state <= S_WAIT;
fx2_data <= (others => '0');
sink_data_d <= (others => '0');
packet_counter <= (others => '0');
when S_WAIT =>
if fx2_full_n = '1' then
fsm_state <= S_SEND_DATA;
end if;
when S_SEND_DATA =>
if sink_stb = '1' and fx2_full_n = '1' then
packet_counter <= packet_counter + 1;
if packet_counter = 1024 then
fsm_state <= S_WAIT;
packet_counter <= (others => '0');
elsif packet_counter = 0 then
fx2_wr_n <= '0';
fx2_data <= X"0C"; -- header length
packet_sent <= '0';
elsif packet_counter = 1 then
fx2_wr_n <= '0';
-- EOH ERR STI RES SCR PTS EOF packet_fid
fx2_data <= ("100" & "000" & "0" & packet_fid);
elsif packet_counter <= 11 then
fx2_wr_n <= '0';
fx2_data <= X"00";
else
fx2_wr_n <= '0';
sink_data_d <= sink_data;
fx2_data <= sink_data;
if sink_data_d = X"FF" and sink_data = X"D9" then
packet_fid <= not packet_fid;
fsm_state <= S_PACKET_END;
packet_sent <= '1';
packet_counter <= (others => '0');
end if;
end if;
end if;
when S_PACKET_END =>
fx2_pktend_n <= '0';
fsm_state <= S_WAIT;
when others =>
fsm_state <= S_RESET;
end case;
end if;
end process;
sending_data <= '1' when ((fsm_state = S_SEND_DATA) and (packet_counter > X"00B" and packet_counter < X"400")) else
'0';
sink_ack <= (sink_stb and fx2_full_n) when sending_data = '1' else '0';
end architecture;
|
bsd-2-clause
|
482a34569047205bc09a5065e1ec7994
| 0.357541 | 4.177368 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/FDCT.vhd
| 2 | 21,601 |
-------------------------------------------------------------------------------
-- File Name : FDCT.vhd
--
-- Project : JPEG_ENC
--
-- Module : FDCT
--
-- Content : FDCT
--
-- Description : 2D Discrete Cosine Transform
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity FDCT is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
fdct_sm_settings : in T_SM_SETTINGS;
-- BUF_FIFO
bf_fifo_rd : out std_logic;
bf_fifo_q : in std_logic_vector(23 downto 0);
bf_fifo_hf_full : in std_logic;
bf_fifo_dval_o : out std_logic;
-- ZIG ZAG
zz_buf_sel : in std_logic;
zz_rd_addr : in std_logic_vector(5 downto 0);
zz_data : out std_logic_vector(11 downto 0);
zz_rden : in std_logic;
-- HOST
img_size_x : in std_logic_vector(15 downto 0);
img_size_y : in std_logic_vector(15 downto 0);
sof : in std_logic
);
end entity FDCT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of FDCT is
signal mdct_data_in : std_logic_vector(7 downto 0):=(others=>'0');
signal mdct_idval : std_logic:='0';
signal mdct_odval : std_logic:='0';
signal mdct_data_out : std_logic_vector(11 downto 0):=(others=>'0');
signal odv1 : std_logic:='0';
signal dcto1 : std_logic_vector(11 downto 0):=(others=>'0');
signal x_pixel_cnt : unsigned(15 downto 0):=(others=>'0');
signal y_line_cnt : unsigned(15 downto 0):=(others=>'0');
signal rd_addr : std_logic_vector(31 downto 0):=(others=>'0');
signal input_rd_cnt : unsigned(6 downto 0):=(others=>'0');
signal rd_en : std_logic:='0';
signal rd_en_d1 : std_logic:='0';
signal rdaddr : unsigned(31 downto 0):=(others=>'0');
signal bf_dval : std_logic:='0';
signal bf_dval_m1 : std_logic:='0';
signal bf_dval_m2 : std_logic:='0';
signal bf_dval_m3 : std_logic:='0';
signal wr_cnt : unsigned(5 downto 0):=(others=>'0');
signal dbuf_data : std_logic_vector(11 downto 0):=(others=>'0');
signal dbuf_q : std_logic_vector(11 downto 0):=(others=>'0');
signal dbuf_we : std_logic:='0';
signal dbuf_waddr : std_logic_vector(6 downto 0):=(others=>'0');
signal dbuf_raddr : std_logic_vector(6 downto 0):=(others=>'0');
signal xw_cnt : unsigned(2 downto 0):=(others=>'0');
signal yw_cnt : unsigned(2 downto 0):=(others=>'0');
signal dbuf_q_z1 : std_logic_vector(11 downto 0):=(others=>'0');
constant C_SIMA_ASZ : integer := 9;
signal sim_rd_addr : unsigned(C_SIMA_ASZ-1 downto 0):=(others=>'0');
signal Y_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cb_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cr_8bit : unsigned(7 downto 0):=(others=>'0');
signal cmp_idx : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d1 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d2 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d3 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d4 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d5 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d6 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d7 : unsigned(2 downto 0):=(others=>'0');
signal cur_cmp_idx_d8 : unsigned(2 downto 0):=(others=>'0');
signal fifo1_rd : std_logic:='0';
signal fifo1_wr : std_logic:='0';
signal fifo1_q : std_logic_vector(11 downto 0):=(others=>'0');
signal fifo1_full : std_logic:='0';
signal fifo1_empty : std_logic:='0';
signal fifo1_count : std_logic_vector(9 downto 0):=(others=>'0');
signal fifo1_rd_cnt : unsigned(5 downto 0):=(others=>'0');
signal fifo1_q_dval : std_logic:='0';
signal fifo_data_in : std_logic_vector(11 downto 0):=(others=>'0');
signal fifo_rd_arm : std_logic:='0';
signal eoi_fdct : std_logic:='0';
signal bf_fifo_rd_s : std_logic:='0';
signal start_int : std_logic:='0';
signal start_int_d : std_logic_vector(4 downto 0):=(others=>'0');
signal fram1_data : std_logic_vector(23 downto 0):=(others=>'0');
signal fram1_q : std_logic_vector(23 downto 0):=(others=>'0');
signal fram1_we : std_logic:='0';
signal fram1_waddr : std_logic_vector(6 downto 0):=(others=>'0');
signal fram1_raddr : std_logic_vector(6 downto 0):=(others=>'0');
signal fram1_rd_d : std_logic_vector(8 downto 0):=(others=>'0');
signal fram1_rd : std_logic:='0';
signal rd_started : std_logic:='0';
signal writing_en : std_logic:='0';
signal fram1_q_vld : std_logic:='0';
signal fram1_line_cnt : unsigned(2 downto 0):=(others=>'0');
signal fram1_pix_cnt : unsigned(2 downto 0):=(others=>'0');
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
zz_data <= dbuf_q;
bf_fifo_rd <= bf_fifo_rd_s;
-------------------------------------------------------------------
-- FRAM1 (Frame RAM, hold 16x8)
-------------------------------------------------------------------
U_FRAM1 : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 24
)
port map
(
d => fram1_data,
waddr => fram1_waddr,
raddr => fram1_raddr,
we => fram1_we,
clk => CLK,
q => fram1_q
);
bf_fifo_dval_o <= bf_dval;
fram1_we <= bf_dval; -- moving a new block
fram1_data <= bf_fifo_q; -- data from BUF_FIFO
fram1_q_vld <= fram1_rd_d(5); -- onto the next ...
-------------------------------------------------------------------
-- FRAM1 address process
-------------------------------------------------------------------
p_fram1_acc : process(CLK, RST)
begin
if RST = '1' then
fram1_waddr <= (others => '0');
elsif CLK'event and CLK = '1' then
if fram1_we = '1' then
fram1_waddr <= std_logic_vector(unsigned(fram1_waddr) + 1);
end if;
end if;
end process;
-------------------------------------------------------------------
-- Intermidiate (I)RAM read process
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d1 <= '0';
x_pixel_cnt <= (others => '0');
y_line_cnt <= (others => '0');
input_rd_cnt <= (others => '0');
cmp_idx <= (others => '0');
cur_cmp_idx <= (others => '0');
cur_cmp_idx_d1 <= (others => '0');
cur_cmp_idx_d2 <= (others => '0');
cur_cmp_idx_d3 <= (others => '0');
cur_cmp_idx_d4 <= (others => '0');
cur_cmp_idx_d5 <= (others => '0');
cur_cmp_idx_d6 <= (others => '0');
cur_cmp_idx_d7 <= (others => '0');
cur_cmp_idx_d8 <= (others => '0');
eoi_fdct <= '0';
start_int <= '0';
bf_fifo_rd_s <= '0';
bf_dval <= '0';
bf_dval_m1 <= '0';
bf_dval_m2 <= '0';
fram1_rd <= '0';
fram1_rd_d <= (others => '0');
start_int_d <= (others => '0');
fram1_raddr <= (others => '0');
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d1 <= rd_en;
cur_cmp_idx_d1 <= cur_cmp_idx;
cur_cmp_idx_d2 <= cur_cmp_idx_d1;
cur_cmp_idx_d3 <= cur_cmp_idx_d2;
cur_cmp_idx_d4 <= cur_cmp_idx_d3;
cur_cmp_idx_d5 <= cur_cmp_idx_d4;
cur_cmp_idx_d6 <= cur_cmp_idx_d5;
cur_cmp_idx_d7 <= cur_cmp_idx_d6;
cur_cmp_idx_d8 <= cur_cmp_idx_d7;
start_int <= '0';
bf_dval_m3 <= bf_fifo_rd_s;
bf_dval_m2 <= bf_dval_m3;
bf_dval_m1 <= bf_dval_m2;
bf_dval <= bf_dval_m1;
fram1_rd_d <= fram1_rd_d(fram1_rd_d'length-2 downto 0) & fram1_rd;
start_int_d <= start_int_d(start_int_d'length-2 downto 0) & start_int;
----------------------------------------------------------------
-- SOF or internal self-start
if (sof = '1' or start_int = '1') then
input_rd_cnt <= (others => '0');
-- enable BUF_FIFO/FRAM1 reading
rd_started <= '1';
-- component index
if cmp_idx = 4-1 then
cmp_idx <= (others => '0');
-- horizontal block counter
if x_pixel_cnt = unsigned(img_size_x)-16 then
x_pixel_cnt <= (others => '0');
-- vertical block counter
if y_line_cnt = unsigned(img_size_y)-8 then
y_line_cnt <= (others => '0');
-- set end of image flag
eoi_fdct <= '1';
else
y_line_cnt <= y_line_cnt + 8;
end if;
else
x_pixel_cnt <= x_pixel_cnt + 16;
end if;
else
cmp_idx <=cmp_idx + 1;
end if;
cur_cmp_idx <= cmp_idx;
end if;
----------------------------------------------------------------
-- wait until FIFO becomes half full but only for component 0
-- as we read buf FIFO only during component 0
if rd_started = '1' and (bf_fifo_hf_full = '1' or cur_cmp_idx > 1) then
rd_en <= '1';
rd_started <= '0';
end if;
bf_fifo_rd_s <= '0';
fram1_rd <= '0';
----------------------------------------------------------------
-- stall reading from input FIFO and writing to output FIFO
-- when output FIFO is almost full
if rd_en = '1' and unsigned(fifo1_count) < 512-64 then
-- read request goes to BUF_FIFO only for component 0.
if cur_cmp_idx < 2 then
bf_fifo_rd_s <= '1';
end if;
-- count number of samples read from input in one run
if input_rd_cnt = 64-1 then
rd_en <= '0';
-- internal restart
start_int <= '1' and not eoi_fdct;
eoi_fdct <= '0';
else
input_rd_cnt <= input_rd_cnt + 1;
end if;
-- FRAM read enable
fram1_rd <= '1';
end if;
----------------------------------------------------------------
-- increment FRAM1 read address according to subsampling
-- idea is to extract 8x8 from 16x8 block
-- there are two luminance blocks left and right
-- there is 2:1 subsampled Cb block
-- there is 2:1 subsampled Cr block
-- subsampling done as simple decimation by 2 wo/ averaging
if sof = '1' then
fram1_raddr <= (others => '0');
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
elsif start_int_d(4) = '1' then
fram1_line_cnt <= (others => '0');
fram1_pix_cnt <= (others => '0');
case cur_cmp_idx_d4 is
-- Y1, Cr, Cb
when "000" | "010" | "011" =>
fram1_raddr <= (others => '0');
-- Y2
when "001" =>
fram1_raddr <= std_logic_vector(to_unsigned(64, fram1_raddr'length));
when others =>
null;
end case;
elsif fram1_rd_d(4) = '1' then
if fram1_pix_cnt = 8-1 then
fram1_pix_cnt <= (others => '0');
if fram1_line_cnt = 8-1 then
fram1_line_cnt <= (others => '0');
else
fram1_line_cnt <= fram1_line_cnt + 1;
end if;
else
fram1_pix_cnt <= fram1_pix_cnt + 1;
end if;
case cur_cmp_idx_d6 is
when "000" | "001" =>
fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 1);
when "010" | "011" =>
if fram1_pix_cnt = 4-1 then
fram1_raddr <= std_logic_vector('1' & fram1_line_cnt & "000");
elsif fram1_pix_cnt = 8-1 then
if fram1_line_cnt = 8-1 then
fram1_raddr <= '0' & "000" & "000";
else
fram1_raddr <= std_logic_vector('0' & (fram1_line_cnt+1) & "000");
end if;
else
fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 2);
end if;
when others =>
null;
end case;
end if;
----------------------------------------------------------------
end if;
end process;
-------------------------------------------------------------------
-- FDCT with input level shift
-------------------------------------------------------------------
U_MDCT : entity work.MDCT
port map
(
clk => CLK,
rst => RST,
dcti => mdct_data_in,
idv => mdct_idval,
odv => mdct_odval,
dcto => mdct_data_out,
odv1 => odv1,
dcto1 => dcto1
);
mdct_idval <= fram1_rd_d(7);
p_pipe : process(CLK)
begin
if CLK'event and CLK = '1' then
Y_8bit <= unsigned(fram1_q(7 downto 0));
Cb_8bit <= unsigned(fram1_q(15 downto 8));
Cr_8bit <= unsigned(fram1_q(23 downto 16));
end if;
end process;
-------------------------------------------------------------------
-- Mux1
-------------------------------------------------------------------
p_mux1 : process(CLK, RST)
begin
if RST = '1' then
mdct_data_in <= (others => '0');
elsif CLK'event and CLK = '1' then
case cur_cmp_idx_d8 is
when "000" | "001" =>
mdct_data_in <= std_logic_vector(Y_8bit);
when "010" =>
mdct_data_in <= std_logic_vector(Cb_8bit);
when "011" =>
mdct_data_in <= std_logic_vector(Cr_8bit);
when others =>
null;
end case;
end if;
end process;
-------------------------------------------------------------------
-- FIFO1
-------------------------------------------------------------------
U_FIFO1 : entity work.FIFO
generic map
(
DATA_WIDTH => 12,
ADDR_WIDTH => 9
)
port map
(
rst => RST,
clk => CLK,
rinc => fifo1_rd,
winc => fifo1_wr,
datai => fifo_data_in,
datao => fifo1_q,
fullo => fifo1_full,
emptyo => fifo1_empty,
count => fifo1_count
);
fifo1_wr <= mdct_odval;
fifo_data_in <= mdct_data_out;
-------------------------------------------------------------------
-- FIFO1 rd controller
-------------------------------------------------------------------
p_fifo_rd_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo1_rd <= '0';
fifo_rd_arm <= '0';
fifo1_rd_cnt <= (others => '0');
fifo1_q_dval <= '0';
elsif CLK'event and CLK = '1' then
fifo1_rd <= '0';
fifo1_q_dval <= fifo1_rd;
if start_pb = '1' then
fifo_rd_arm <= '1';
fifo1_rd_cnt <= (others => '0');
end if;
if fifo_rd_arm = '1' then
if fifo1_rd_cnt = 64-1 then
fifo_rd_arm <= '0';
fifo1_rd <= '1';
elsif fifo1_empty = '0' then
fifo1_rd <= '1';
fifo1_rd_cnt <= fifo1_rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- write counter
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
xw_cnt <= (others => '0');
yw_cnt <= (others => '0');
writing_en <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
xw_cnt <= (others => '0');
yw_cnt <= (others => '0');
writing_en <= '1';
end if;
if writing_en = '1' then
if fifo1_q_dval = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
ready_pb <= '1';
writing_en <= '0';
else
wr_cnt <= wr_cnt + 1;
end if;
if yw_cnt = 8-1 then
yw_cnt <= (others => '0');
xw_cnt <= xw_cnt+1;
else
yw_cnt <= yw_cnt+1;
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= fifo1_q;
dbuf_we <= fifo1_q_dval;
dbuf_waddr <= (not zz_buf_sel) & std_logic_vector(yw_cnt & xw_cnt);
dbuf_raddr <= zz_buf_sel & zz_rd_addr;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------
|
bsd-2-clause
|
4a369a7d8016474f181cd8de724f9670
| 0.415536 | 3.967855 | false | false | false | false |
rbaummer/UART
|
synchronizer.vhd
| 1 | 869 |
--------------------------------------------------------------------------------
--
-- File: Synchronizer.vhd
-- Author: Rob Baummer
--
-- Description: Synchronizes I to clock using 2 flip flops
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer is
port (
clk : in std_logic;
reset : in std_logic;
I : in std_logic;
O : out std_logic
);
end synchronizer;
architecture behavioral of synchronizer is
signal dff1 : std_logic;
signal dff2 : std_logic;
begin
--Dual synchronization registers
process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
dff1 <= '0';
dff2 <= '0';
else
dff1 <= I;
dff2 <= dff1;
end if;
end if;
end process;
--Synchronized output
O <= dff2;
end behavioral;
|
mit
|
9726c10e4ad9d57edd9542c310f73eb7
| 0.531646 | 3.576132 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 8/Parte 1/SeqDetFSM_Tb.vhd
| 1 | 712 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SeqDetFSM_Tb is
end SeqDetFSM_Tb;
architecture Stimulus of SeqDetFSM_Tb is
signal s_clk : std_logic;
signal s_xin, s_yout : std_logic;
begin
uut: entity work.SeqDetFSM(MealyArch)
port map(clk => s_clk,
xin => s_xin,
yout=> s_yout);
clk_proc: process
begin
s_clk <= '1';
wait for 25 ns;
s_clk <= '0';
wait for 25 ns;
end process;
stim_proc: process
begin
s_xin <= '1';
wait for 35 ns;
s_xin <= '0';
wait for 20 ns;
s_xin <= '1';
wait for 20 ns;
s_xin <= '0';
wait for 20 ns;
s_xin <= '1';
wait for 20 ns;
s_xin <= '1';
wait for 20 ns;
s_xin <= '1';
wait for 20 ns;
end process;
end Stimulus;
|
gpl-2.0
|
1e5712b8504ea7ea684d3b6cfcdd7936
| 0.592697 | 2.421769 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/with screen/MIPSconPantallaME/mips.vhd
| 1 | 10,119 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:45:27 11/28/2012
-- Design Name:
-- Module Name: mips - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mips is
port (clock, reset : in std_logic;
velocidad0: in std_logic;velocidad1: in std_logic;
hsyncb: inout std_logic; -- horizontal (line) sync
vsyncb: out std_logic; -- vertical (frame) sync
rgb: out std_logic_vector(8 downto 0) -- red,green,blue colors
);
end mips;
architecture Behavioral of mips is
signal Estado, sig_estado: Estados;
--Señales memorias
--banco de registros
signal RW: std_logic_vector(4 downto 0);
signal busW, busB, busA: std_logic_vector(31 downto 0);
signal reg0B, reg1B, reg2B, reg3B:std_logic_vector(31 downto 0);
--memoria de instrucciones
--signal ADDR: std_logic_vector(4 downto 0);
signal DR: std_logic_vector(31 downto 0);
signal reg0M, reg1M, reg2M, reg3M: std_logic_vector(31 downto 0);
--memoria de datos
signal DRDat : std_logic_vector(31 downto 0);
signal RDat, WDat: std_logic;
--Señales Controles
--control ALU
signal ALUCtrl: std_logic_vector(1 downto 0);
--control saltos
signal EscrPC: std_logic;
signal salida: std_logic;
--control general
signal PcWriteCond0, PcWriteCond1, PcWriteCond2: std_logic;
signal Reg_Write: std_logic;
signal ALUOp0, ALUOp1, ALUOp2: std_logic;
signal ALUOp: std_logic_vector(2 downto 0);
signal RegDst, MemtoReg: std_logic;
signal ALUA,ALUB0,ALUB1, PcSrc0, PcSrc1:std_logic;
signal sig_estadoControl: Estados;
--Señales ALU
signal entradaA, entradaB: std_logic_vector(31 downto 0);
signal cero: std_logic;
signal mayorque: std_logic;
signal resultado: std_logic_vector(31 downto 0);
--Señales Extensor
signal extendido: std_logic_vector(31 downto 0);
--señales PC
signal loadPC: std_logic;
signal tempPC, PC: std_logic_vector(31 downto 0);
--registros temporales --
signal registroA, registroB, salidaALU, Instruction: std_logic_vector(31 downto 0);
signal entradaControl: std_logic_vector(5 downto 0);
signal tempA, tempB, tempSalidaALU, tempInstruction: std_logic_vector(31 downto 0);
signal loadA,loadB,loadSalidaALU, loadInstruction, loadEntradaControl: std_logic;
signal entradaExtensor: std_logic_vector(15 downto 0);
component MemoriaDeInstrucciones is
port( Clock: in std_logic;
ADDR: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0)
);
end component;
component MemoriaDeDatos is
port( Clock: in std_logic;
ADDR, write_addr: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0);
DW: in std_logic_vector(31 downto 0);
R, W: in std_logic;
reg0: out std_logic_vector(31 downto 0);
reg1: out std_logic_vector(31 downto 0);
reg2: out std_logic_vector(31 downto 0);
reg3: out std_logic_vector(31 downto 0)
);
end component;
component BancoDeRegistros is
port(
Clock: in std_logic;
Reg_Write: in std_logic;
RA: in std_logic_vector(4 downto 0);
RB: in std_logic_vector(4 downto 0);
RW: in std_logic_vector(4 downto 0);
busW: in std_logic_vector(31 downto 0);
busA: out std_logic_vector(31 downto 0);
busB: out std_logic_vector(31 downto 0);
reg0: out std_logic_vector(31 downto 0);
reg1: out std_logic_vector(31 downto 0);
reg2: out std_logic_vector(31 downto 0);
reg3: out std_logic_vector(31 downto 0)
);
end component;
component ExtensorSigno is
port(
A: in std_logic_vector (15 downto 0);
S: out std_logic_vector (31 downto 0)
);
end component;
component alu8bit is
port(
a, b : in std_logic_vector(31 downto 0);
op : in std_logic_vector(1 downto 0);
zero, bigthan : out std_logic;
result : out std_logic_vector(31 downto 0)
);
end component;
component control is
port(instruction: in std_logic_vector(5 downto 0);
Estado: in ESTADOS;
sig_estado: out ESTADOS;
RegDst, RegWrite, MemWrite, MemRead, MemtoReg, PcWriteCond0, PcWriteCond1, PcWriteCond2,
ALUOp0, ALUOp1, ALUOp2, ALUA, ALUB0, ALUB1, PcSrc0, PcSrc1, PcWrite:out std_logic
);
end component;
component AluControl is
port (funct: in std_logic_vector(5 downto 0);
AluOp:in std_logic_vector(2 downto 0);
--AluOp(1) es 1
AluCtr: out std_logic_vector(1 downto 0)
);
end component;
component ControlBranch is
port (cero , mayorque, saltar,EscrPC,EscrPC_Cond1,EscrPC_Cond2: in std_logic;--1 es menos significativo
salida: out std_logic
);
end component;
--pantalla
component vgacore is
port
(
reset: in std_logic; -- reset
clock: in std_logic;
ins: in std_logic_vector(31 downto 0);--instruccion
salidaAlu: in std_logic_vector(31 downto 0);--salidaALU
estado: in Estados;
reg0: in std_logic_vector(31 downto 0);
reg1: in std_logic_vector(31 downto 0);
reg2: in std_logic_vector(31 downto 0);
reg3: in std_logic_vector(31 downto 0);
reg4: in std_logic_vector(31 downto 0);
reg5: in std_logic_vector(31 downto 0);
reg6: in std_logic_vector(31 downto 0);
reg7: in std_logic_vector(31 downto 0);
hsyncb: inout std_logic; -- horizontal (line) sync
vsyncb: out std_logic; -- vertical (frame) sync
rgb: out std_logic_vector(8 downto 0) -- red,green,blue colors
);
end component;
signal reloj:std_logic;
signal clk:std_logic;
component divisor2 is
port (
reset: in STD_LOGIC;
clk: in STD_LOGIC; -- reloj de entrada de la entity superior
reloj: out STD_LOGIC; -- reloj que se utiliza en los process del programa principal
velocidad0: in std_logic;
velocidad1: in std_logic
);
end component;
begin
ALUOp<=ALUOp2&ALUOp1&ALUOp0;
MemIns: MemoriaDeInstrucciones
port map(clk, PC(4 downto 0), DR);--siempre se lee nunca se escribe
MemDatos: MemoriaDeDatos
port map(clk, salidaALU(4 downto 0), salidaALU(4 downto 0), DRDat, registroB, RDat, WDat,reg0M,reg1M,reg2M,reg3M);
Banco_Registros: BancoDeRegistros
port map(clk, Reg_Write, DR(25 downto 21), DR(20 downto 16), RW, busW, busA, busB,reg0B,reg1B,reg2B,reg3B);
ControlSaltos: ControlBranch
port map(cero , mayorque, PcWriteCond2,EscrPC, PcWriteCond0,PcWriteCond1, salida);
ControlAlu: AluControl
port map(Instruction(5 downto 0), ALUOp, ALUCtrl);
ControlG: control
port map(entradaControl, Estado, sig_estadoControl,
RegDst, Reg_Write, WDat, RDat, MemtoReg, PcWriteCond0,PcWriteCond1,PcWriteCond2, ALUOp0, ALUOp1,
ALUOp2, ALUA, ALUB0, ALUB1, PcSrc0, PcSrc1, EscrPc);
ALU: alu8bit
port map(entradaA,entradaB, ALUCtrl, cero, mayorque, resultado);
Extensor: ExtensorSigno
port map(entradaExtensor,extendido);
--pantalla
Pantalla: vgacore port map(reset,clock,Instruction,salidaALU,estado,reg0B,reg1B,reg2B,reg3B,reg0M,reg1M,reg2M,reg3M, hsyncb, vsyncb, rgb);
Nuevo_reloj: divisor2 port map(reset,clock, reloj, velocidad0, velocidad1);
clk<=reloj;
--Conexiones
RW<=Instruction(20 downto 16) when RegDst='0' else
Instruction(15 downto 11);
busW<= salidaALU when MemtoReg='0' else
DRDat;
entradaA<=PC when ALUA='0' else
registroA;
entradaB<= registroB when (ALUB1='0' and ALUB0='0') else
X"00000001" when (ALUB1='0' and ALUB0='1') else
extendido;
tempPC<= resultado when (PcSrc1='0' and PcSrc0='0') else
salidaALU when (PcSrc1='0' and PcSrc0='1') else
PC(31 downto 26)&Instruction(25 downto 0);
loadPC<=salida;
tempSalidaALU<=resultado;
tempInstruction<=DR;
tempA<=busA;
tempB<=busB;
sig_estado <= sig_estadoControl;
Síncrono: process(clk, reset)
begin
if reset='1' then
Estado<=F;
PC<=X"00000000";
elsif clk'event and clk ='1' then
Estado<=sig_estado;
if loadPC='1' then
PC<=tempPC;
end if;
if loadA='1' then
registroA<=tempA;
end if;
if loadB='1' then
registroB<=tempB;
end if;
if loadSalidaALU='1' then
salidaALU<=tempSalidaALU;
end if;
if loadInstruction='1' then
Instruction<=tempInstruction;
end if;
if loadEntradaControl='0' then
entradaControl <= DR(31 downto 26);
elsif loadEntradaControl='1' then
entradaControl <= Instruction(31 downto 26);
end if;
end if;
end process Síncrono;
Combinacional:process(clk,Estado--,registroA,registroB,salidaALU, PC
)
begin
case Estado is
when F =>
loadInstruction<='1';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl <= '0';
entradaExtensor <= DR(15 downto 0);--indefinido
when ID => --en ID la instrucción siempre es la correcta
loadInstruction<='1';
loadA<='1';
loadB<='1';
loadSalidaALU<='1';
loadEntradaControl<='0';
entradaExtensor <= DR(15 downto 0);
when EX =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='1';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
when MEM =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
when WB =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
end case;
end process Combinacional;
end Behavioral;
|
gpl-2.0
|
f1b4709761bae15d11f75c2732dffe2c
| 0.662318 | 3.250562 | false | false | false | false |
tejainece/VHDLExperiments
|
FloatingPointMul23/FloatingPointMul23.vhd
| 1 | 3,398 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:05 01/29/2014
-- Design Name:
-- Module Name: FloatingPointMul23 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FloatingPointMul23 is
PORT (
a_in : in STD_LOGIC_VECTOR(22 downto 0);
b_in : in STD_LOGIC_VECTOR(22 downto 0);
res_out : out STD_LOGIC_VECTOR(22 downto 0);
sign : out STD_LOGIC;
zero : out STD_LOGIC;
overflow : out STD_LOGIC;
underflow : out STD_LOGIC
);
end FloatingPointMul23;
architecture Behavioral of FloatingPointMul23 is
COMPONENT Multiply16Booth4 is
PORT (
a: IN STD_LOGIC_VECTOR(15 downto 0);
b: IN STD_LOGIC_VECTOR(15 downto 0);
o: OUT STD_LOGIC_VECTOR(15 downto 0));
end COMPONENT;
COMPONENT CSA8 is
generic (width : integer := 32);
Port ( a : in STD_LOGIC_VECTOR (width-1 downto 0);
b : in STD_LOGIC_VECTOR (width-1 downto 0);
o : out STD_LOGIC_VECTOR (width-1 downto 0);
cout : out STD_LOGIC);
end COMPONENT;
SIGNAL tmp_mA : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL tmp_mB : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL mul_t : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL add_t : STD_LOGIC_VECTOR(9 downto 0);
SIGNAL add_t2 : STD_LOGIC_VECTOR(9 downto 0);
SIGNAL bias_normalized : unsigned(9 downto 0);
SIGNAL a_zero : STD_LOGIC;
SIGNAL b_zero : STD_LOGIC;
SIGNAL output : STD_LOGIC_VECTOR(22 downto 0);
CONSTANT C_M127 : unsigned(9 downto 0) := to_unsigned(127, 10);
CONSTANT C_M126 : unsigned(9 downto 0) := to_unsigned(126, 10);
begin
tmp_mA <= "01" & a_in(13 downto 0);
tmp_mB <= "01" & b_in(13 downto 0);
multiplier_i : Multiply16Booth4 PORT MAP (
a =>tmp_mA,
b => tmp_mB,
o => mul_t
);
exponent_i : CSA8 GENERIC MAP (
width => 8
)
PORT MAP (
a => a_in(21 downto 14),
b => b_in(21 downto 14),
o => add_t(7 downto 0),
cout => add_t(8)
);
add_t(9) <= '0';
bias_normalized(9 downto 0) <= C_M126 when mul_t(15) = '1' else
C_M127;
add_t2 <= std_logic_vector(unsigned(add_t) - bias_normalized);
a_zero <= '1' when a_in(21 downto 0) = "0000000000000000000000" else
'0';
b_zero <= '1' when b_in(21 downto 0) = "0000000000000000000000" else
'0';
output(13 downto 0) <= "00000000000000" when a_zero = '1' or b_zero = '1' else
mul_t(14 downto 1) when mul_t(15) = '1' else
mul_t(13 downto 0);
output(21 downto 14) <= "00000000" when a_zero = '1' or b_zero = '1' else
add_t2(7 downto 0);
output(22) <= '0' when a_zero = '1' or b_zero = '1' else
a_in(22) xor b_in(22);
sign <= a_in(22) xor b_in(22);
zero <= '1' when output(21 downto 0) = "0000000000000000000000" else
'0';
overflow <= '1' when add_t2(9 downto 8) = "01" else
'0';
underflow <= '1' when add_t2(9 downto 8) = "11" else
'0';
res_out <= output;
end Behavioral;
|
gpl-3.0
|
397e09db43d69c1468112d13b0f7a31d
| 0.586227 | 3.064022 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Compare_Tb.vhd
| 1 | 1,943 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Compare_Tb is
end Compare_Tb;
-- Teste funcional para a entidade compare.
architecture Stimulus of Compare_Tb is
signal num1, num2,num3, num4,num5, num6,num7, num8 : std_logic_vector(3 downto 0);
signal s_cert, s_erra : std_logic_vector(3 downto 0);
signal s_clk, s_reset : std_logic;
begin
uut : entity work.Compare2(Behavioral)
port map(randomnum0 => num1,
usernum0 => num2,
randomnum1 => num3,
usernum1 => num4,
randomnum2 => num5,
usernum2 => num6,
randomnum3 => num7,
usernum3 => num8,
cert => s_cert,
erra => s_erra,
clock => s_clk,
reset => s_reset);
clk_proc: process
begin
s_clk <= '1';
wait for 1 ns;
s_clk <= '0';
wait for 1 ns;
end process;
comb_proc : process
begin
s_reset <= '0';
num1 <= "1010";
num2 <= "0101";
num3 <= "1010";
num4 <= "0101";
num5 <= "1010";
num6 <= "0101";
num7 <= "1010";
num8 <= "0101";
wait for 5 ns;
s_reset <= '1';
wait for 5 ns;
s_reset <= '0';
wait for 10 ns;
num1 <= "0011";
num2 <= "0011";
num3 <= "0011";
num4 <= "0011";
num5 <= "0011";
num6 <= "0011";
num7 <= "0011";
num8 <= "0011";
s_reset <= '1';
wait for 5 ns;
s_reset <= '0';
wait for 15 ns;
num1 <= "0001";
wait for 15 ns;
num1 <= "0010";
num2 <= "0001";
num3 <= "0010";
num4 <= "0010";
num5 <= "0001";
num6 <= "0010";
num7 <= "0001";
num8 <= "0001";
s_reset <= '1';
wait for 5 ns;
s_reset <= '0';
wait for 15 ns;
num1 <= "0010";
num2 <= "0001";
num3 <= "0010";
num4 <= "0010";
num5 <= "0001";
num6 <= "0010";
num7 <= "0001";
num8 <= "0010";
s_reset <= '1';
wait for 5 ns;
s_reset <= '0';
wait for 15 ns;
end process;
end Stimulus;
|
gpl-2.0
|
2b4d028afcf1251d75de12db32780072
| 0.528564 | 2.543194 | false | false | false | false |
miree/vhdl_cores
|
uart/uart_chipsim.vhd
| 1 | 4,449 |
package uart_chipsim_pkg is
procedure uart_chipsim_init(stop_unitl_connected : boolean);
attribute foreign of uart_chipsim_init : procedure is "VHPIDIRECT uart_chipsim_init";
-- if the function returns a positive integer, it is a valid value
-- if the function returns a negative value it is either
-- TIMEOUT, meaning that nothing was read
-- or HANGUP, meaning that the client disconnected
function uart_chipsim_read(timeout_value : integer) return integer;
attribute foreign of uart_chipsim_read : function is "VHPIDIRECT uart_chipsim_read";
procedure uart_chipsim_write(x : integer);
attribute foreign of uart_chipsim_write : procedure is "VHPIDIRECT uart_chipsim_write";
procedure uart_chipsim_flush;
attribute foreign of uart_chipsim_flush : procedure is "VHPIDIRECT uart_chipsim_flush";
shared variable my_var : integer := 43;
end package;
package body uart_chipsim_pkg is
procedure uart_chipsim_init(stop_unitl_connected : boolean) is
begin
assert false report "VHPI" severity failure;
end procedure;
function uart_chipsim_read(timeout_value : integer) return integer is
begin
assert false report "VHPI" severity failure;
return 0;
end function;
procedure uart_chipsim_write(x : integer) is
begin
assert false report "VHPI" severity failure;
end procedure;
procedure uart_chipsim_flush is
begin
assert false report "VHPI" severity failure;
end procedure;
end package body;
library ieee;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.uart_chipsim_pkg.all;
entity uart_chipsim is
generic (
g_wait_until_connected : boolean := true;
g_continue_after_disconnect : boolean := true;
g_baud_rate : integer := 9600
);
port (
tx_o : out std_logic;
rx_i : in std_logic
);
end entity;
architecture simulation of uart_chipsim is
signal tx : std_logic := '1';
signal clk_internal : std_logic := '1';
constant clk_internal_period : time := 100 ms / g_baud_rate;
signal value_from_file : integer := -1;
signal tx_dat, rx_dat : std_logic_vector(7 downto 0) := (others => '0');
signal tx_stb, rx_stb : std_logic := '0';
signal tx_stall : std_logic := '0';
function fix_rx_dat(rx : std_logic_vector(7 downto 0)) return std_logic_vector is
variable result : std_logic_vector(rx'range) := rx;
begin
for i in result'range loop
if result(i) /= '1' then
result(i) := '0';
end if;
end loop;
return result;
end function;
begin
-- clock generation
clk_internal <= not clk_internal after clk_internal_period/2;
-- instantiate a uart serializer
uart_tx_inst: entity work.uart_tx
generic map (
g_clk_freq => g_baud_rate*10,
g_baud_rate => g_baud_rate,
g_bits => 8)
port map (
clk_i => clk_internal,
dat_i => tx_dat,
stb_i => tx_stb,
stall_o => tx_stall,
tx_o => tx_o
);
uart_rx_inst: entity work.uart_rx
generic map (
g_clk_freq => g_baud_rate*10,
g_baud_rate => g_baud_rate,
g_bits => 8)
port map (
clk_i => clk_internal,
dat_o => rx_dat,
stb_o => rx_stb,
rx_i => rx_i
);
main: process
variable client_connected : boolean;
variable stop_until_client_connects : boolean := g_wait_until_connected;
begin
wait until rising_edge(clk_internal);
while true loop
uart_chipsim_init(stop_until_client_connects);
stop_until_client_connects := not g_continue_after_disconnect;
client_connected := true;
while client_connected loop
wait until rising_edge(clk_internal);
-- get value from device
if value_from_file < 0 then
value_from_file <= uart_chipsim_read(timeout_value=>0);
if value_from_file = -2 then
client_connected := false;
end if;
end if;
-- provide value to simulation
tx_stb <= '0';
if value_from_file >= 0 and tx_stall = '0' then
tx_dat <= std_logic_vector(to_signed(value_from_file,8));
tx_stb <= '1';
value_from_file <= -1;
end if;
if rx_stb = '1' then
uart_chipsim_write(to_integer(unsigned(fix_rx_dat(rx_dat))));
uart_chipsim_flush;
end if;
end loop;
end loop;
end process;
end architecture;
|
mit
|
74d4de1fb82544e3a75ce898e2e2a230
| 0.635199 | 3.587903 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 7/Parte 1/ChronometerCore.vhd
| 1 | 3,170 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ChronometerCore is
port(reset : in std_logic;
clk50MHz : in std_logic;
statop : in std_logic;
laprst : in std_logic;
dispOut0_n : out std_logic_vector(6 downto 0);
dispOut1_n : out std_logic_vector(6 downto 0);
dispOut2_n : out std_logic_vector(6 downto 0);
dispOut3_n : out std_logic_vector(6 downto 0);
dispOut4_n : out std_logic_vector(6 downto 0);
dispOut5_n : out std_logic_vector(6 downto 0));
end ChronometerCore;
architecture Structural of ChronometerCore is
signal s_clk100Hz : std_logic;
signal s_statop, s_laprst : std_logic;
signal s_cntReset, s_cntEnable : std_logic;
signal s_regEnable : std_logic;
signal s_counterOut, s_registerOut : std_logic_vector(23 downto 0);
begin
clk_divider_500000 : entity WORK.ClkDividerN(Behavioral)
generic map(divFactor => 500000)
port map(reset => '0',
clkIn => clk50MHz,
clkOut => s_clk100Hz);
statop_debounce : entity WORK.DebounceUnit(Behavioral)
generic map(clkFrekHz => 50000,
blindmSec => 100,
inPol => '0',
outPol => '1')
port map(reset => reset,
refClk => clk50MHz,
dirtyIn => statop,
pulsedOut => s_statop);
laprst_debounce : entity WORK.DebounceUnit(Behavioral)
generic map(clkFrekHz => 50000,
blindmSec => 100,
inPol => '0',
outPol => '1')
port map(reset => reset,
refClk => clk50MHz,
dirtyIn => laprst,
pulsedOut => s_laprst);
control_unit : entity WORK.ControlUnit(Behavioral)
port map(reset => reset,
clk => clk50MHz,
statop => s_statop,
laprst => s_laprst,
cntReset => s_cntReset,
cntEnable => s_cntEnable,
regEnable => s_regEnable);
bcd_counter : entity WORK.CntBCDUp4(Behavioral)
port map(reset => s_cntReset,
clk => s_clk100Hz,
clkEnable => s_cntEnable,
count => s_counterOut);
freeze_register : entity WORK.RegN(Behavioral)
generic map(size => 24,
resetValue => "000000000000000000000000")
port map(asyncReset => '0',
clk => clk50MHz,
clkEnable => s_regEnable,
syncReset => '0',
dataIn => s_counterOut,
dataOut => s_registerOut);
disp_0_decoder : entity WORK.Bin7SegDecoder(Behavioral)
port map(binInput => s_registerOut(3 downto 0),
decOut_n => dispOut0_n);
disp_1_decoder : entity WORK.Bin7SegDecoder(Behavioral)
port map(binInput => s_registerOut(7 downto 4),
decOut_n => dispOut1_n);
disp_2_decoder : entity WORK.Bin7SegDecoder(Behavioral)
port map(binInput => s_registerOut(11 downto 8),
decOut_n => dispOut2_n);
disp_3_decoder : entity WORK.Bin7SegDecoder(Behavioral)
port map(binInput => s_registerOut(15 downto 12),
decOut_n => dispOut3_n);
disp_4_decoder : entity WORK.Bin7SegDecoder(Behavioral)
port map(binInput => s_registerOut(19 downto 16),
decOut_n => dispOut4_n);
disp_5_decoder : entity WORK.Bin7SegDecoder(Behavioral)
port map(binInput => s_registerOut(23 downto 20),
decOut_n => dispOut5_n);
end Structural;
|
gpl-2.0
|
0367dee7ece96129d21f37002a08453b
| 0.636593 | 3.144841 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/AluDisplay.vhd
| 1 | 2,138 |
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
entity AluDisplay is
generic(N : natural := 8);
port( decOut_n, m2 : out std_logic_vector(6 downto 0);
a, b : in std_logic_vector(N-1 downto 0);
op : in std_logic_vector(2 downto 0);
r, m : out std_logic_vector(N-1 downto 0));
end AluDisplay;
architecture Behavioral of AluDisplay is
signal s_a, s_b, s_r : unsigned(N-1 downto 0);
signal s_m : unsigned((2*N)-1 downto 0);
begin
decOut_n <= "1111001" when r="0001" else --1
"0100100" when r="0010" else --2
"0110000" when r="0011" else --3
"0011001" when r="0100" else --4
"0010010" when r="0101" else --5
"0000010" when r="0110" else --6
"1111000" when r="0111" else --7
"0000000" when r="1000" else --8
"0010000" when r="1001" else --9
"0001000" when r="1010" else --A
"0000011" when r="1011" else --B
"1000110" when r="1100" else --C
"0100001" when r="1101" else --D
"0000110" when r="1110" else --E
"0001110" when r="1111" else --F
"1000000"; --0
m2 <= "1111001" when m="0001" else --1
"0100100" when m="0010" else --2
"0110000" when m="0011" else --3
"0011001" when m="0100" else --4
"0010010" when m="0101" else --5
"0000010" when m="0110" else --6
"1111000" when m="0111" else --7
"0000000" when m="1000" else --8
"0010000" when m="1001" else --9
"0001000" when m="1010" else --A
"0000011" when m="1011" else --B
"1000110" when m="1100" else --C
"0100001" when m="1101" else --D
"0000110" when m="1110" else --E
"0001110" when m="1111" else --F
"1000000"; --0
s_a <= unsigned(a);
s_b <= unsigned(b);
s_m <= s_a * s_b;
with op select
s_r <= (s_a + s_b) when "000",
(s_a - s_b) when "001",
s_m(N-1 downto 0) when "010",
(s_a / s_b) when "011",
s_a rem s_b when "100",
s_a and s_b when "101",
s_a or s_b when "110",
s_a xor s_b when "111";
r <= std_logic_vector(s_r);
m <= std_logic_vector(s_m((2*N)-1 downto 4)) when (op = "010") else
(others => '0');
end Behavioral;
|
gpl-2.0
|
e52ed60a7d4bab6e75047c082a7d490d
| 0.558934 | 2.639506 | false | false | false | false |
rbaummer/UART
|
fifo_cell.vhd
| 1 | 2,541 |
--------------------------------------------------------------------------------
--
-- File: FIFO Cell for Mixed-Clock FIFO - Register Based
-- Author: Rob Baummer
--
-- Description: Individual cell for a word in the Mixed-Clock FIFO
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_cell is
generic (
N : integer);
port (
--Read Interface
clk_get : in std_logic;
en_get : in std_logic;
valid : out std_logic;
v : out std_logic;
data_get : out std_logic_vector(N-1 downto 0);
empty : out std_logic;
--Write Interface
clk_put : in std_logic;
en_put : in std_logic;
req_put : in std_logic;
data_put : in std_logic_vector(N-1 downto 0);
full : out std_logic;
--Token Interface
ptok_in : in std_logic;
gtok_in : in std_logic;
ptok_out : out std_logic;
gtok_out : out std_logic;
reset : in std_logic;
init_token : in std_logic
);
end fifo_cell;
architecture behavioral of fifo_cell is
signal data_reg : std_logic_vector(N downto 0);
signal ptok : std_logic;
signal gtok : std_logic;
signal S : std_logic;
signal R : std_logic;
begin
--Register for the data stored in the cell
--MSB is a valid bit
process (clk_put)
begin
if clk_put = '1' and clk_put'event then
if reset = '1' then
data_reg <= (others => '0');
elsif ptok_in = '1' and en_put = '1' then
data_reg <= req_put & data_put;
end if;
end if;
end process;
--Output Tristate
data_get <= data_reg(N-1 downto 0) when R = '1' else (others => 'Z');
valid <= data_reg(N) when R = '1' else 'Z';
v <= data_reg(N);
--Put Token register
process (clk_put)
begin
if clk_put = '1' and clk_put'event then
if reset = '1' then
ptok <= init_token;
elsif en_put = '1' then
ptok <= ptok_in;
end if;
end if;
end process;
--Put token is pased right to left
ptok_out <= ptok;
--Get Token register
process (clk_get)
begin
if clk_get = '1' and clk_get'event then
if reset = '1' then
gtok <= init_token;
elsif en_get = '1' then
gtok <= gtok_in;
end if;
end if;
end process;
--Get token is pased right to left
gtok_out <= gtok;
--SR flip flop reset
R <= en_get and gtok_in;
--SR flip flop set
S <= en_put and ptok_in;
--Full/Empty SR flip flop
process (S, R)
begin
if R = '1' or reset = '1' then
empty <= '1';
full <= '0';
elsif S = '1' then
empty <= '0';
full <= '1';
end if;
end process;
end behavioral;
|
mit
|
9a8cd72435021afb6e6013851af472f0
| 0.577725 | 2.871186 | false | false | false | false |
mithro/HDMI2USB-litex-firmware
|
gateware/encoder/vhdl/ROME.vhd
| 2 | 6,909 |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROME.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (even part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROME is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROME;
architecture RTL of ROME is
type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP+AP+AP, ROMDATA_W) ),
-- 16
(others => '0'),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(CM+BM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
std_logic_vector( to_signed(CP+BM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(BP+CM, ROMDATA_W) ),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(BP+CP, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
(others => '0'),
-- 32
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AM+AM, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AP+AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(AP, ROMDATA_W) ),
std_logic_vector( to_signed(AM, ROMDATA_W) ),
(others => '0'),
-- 48
(others => '0'),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
std_logic_vector( to_signed(BP+CM, ROMDATA_W) ),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(BM+CM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(CM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(CP+BP, ROMDATA_W) ),
std_logic_vector( to_signed(BP, ROMDATA_W) ),
std_logic_vector( to_signed(CP+BM, ROMDATA_W) ),
std_logic_vector( to_signed(BM, ROMDATA_W) ),
std_logic_vector( to_signed(CP, ROMDATA_W) ),
(others => '0')
);
begin
process(clk)
begin
if rising_edge(clk) then
datao <= rom(to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
bsd-2-clause
|
7a9383f59954419913ae41963090dce4
| 0.496888 | 3.80871 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/constants.vhd
| 1 | 6,715 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package constants is
constant XLEN: integer := 32;
constant XLEN_ZERO: std_logic_vector(XLEN-1 downto 0) := X"00000000";
constant XLEN_ONE: std_logic_vector(XLEN-1 downto 0) := X"00000001";
constant RESET_VECTOR: std_logic_vector(XLEN-1 downto 0) := X"00000000";
constant TRAP_VECTOR: std_logic_vector(XLEN-1 downto 0) := X"00000004";
constant INTERRUPT_VECTOR: std_logic_vector(XLEN-1 downto 0) := X"00000008";
-- Opcodes
constant OP_OP: std_logic_vector(4 downto 0) := "01100"; -- R-type
constant OP_CUSTOM0: std_logic_vector(4 downto 0) := "00010"; -- R-type
constant OP_JALR: std_logic_vector(4 downto 0) := "11001"; -- I-type
constant OP_LOAD: std_logic_vector(4 downto 0) := "00000"; -- I-type
constant OP_OPIMM: std_logic_vector(4 downto 0) := "00100"; -- I-type
constant OP_SYSTEM: std_logic_vector(4 downto 0) := "11100"; -- I-type
constant OP_MISCMEM: std_logic_vector(4 downto 0) := "00011"; -- I-type?
constant OP_STORE: std_logic_vector(4 downto 0) := "01000"; -- S-type
constant OP_BRANCH: std_logic_vector(4 downto 0) := "11000"; -- SB-type
constant OP_LUI: std_logic_vector(4 downto 0) := "01101"; -- U-type
constant OP_AUIPC: std_logic_vector(4 downto 0) := "00101"; -- U-type
constant OP_JAL: std_logic_vector(4 downto 0) := "11011"; -- UJ-type
constant FUNC_JALR: std_logic_vector(2 downto 0) := "000";
-- Functions
constant FUNC_BEQ: std_logic_vector(2 downto 0) := "000";
constant FUNC_BNE: std_logic_vector(2 downto 0) := "001";
constant FUNC_BLT: std_logic_vector(2 downto 0) := "100";
constant FUNC_BGE: std_logic_vector(2 downto 0) := "101";
constant FUNC_BLTU: std_logic_vector(2 downto 0) := "110";
constant FUNC_BGEU: std_logic_vector(2 downto 0) := "111";
constant FUNC_LB: std_logic_vector(2 downto 0) := "000";
constant FUNC_LH: std_logic_vector(2 downto 0) := "001";
constant FUNC_LW: std_logic_vector(2 downto 0) := "010";
constant FUNC_LBU: std_logic_vector(2 downto 0) := "100";
constant FUNC_LHU: std_logic_vector(2 downto 0) := "101";
constant FUNC_SB: std_logic_vector(2 downto 0) := "000";
constant FUNC_SH: std_logic_vector(2 downto 0) := "001";
constant FUNC_SW: std_logic_vector(2 downto 0) := "010";
constant FUNC_ADDI: std_logic_vector(2 downto 0) := "000";
constant FUNC_SLLI: std_logic_vector(2 downto 0) := "001";
constant FUNC_SLTI: std_logic_vector(2 downto 0) := "010";
constant FUNC_SLTIU: std_logic_vector(2 downto 0) := "011";
constant FUNC_XORI: std_logic_vector(2 downto 0) := "100";
constant FUNC_SRLI_SRAI: std_logic_vector(2 downto 0) := "101";
constant FUNC_ORI: std_logic_vector(2 downto 0) := "110";
constant FUNC_ANDI: std_logic_vector(2 downto 0) := "111";
constant FUNC_ADD_SUB: std_logic_vector(2 downto 0) := "000";
constant FUNC_SLL: std_logic_vector(2 downto 0) := "001";
constant FUNC_SLT: std_logic_vector(2 downto 0) := "010";
constant FUNC_SLTU: std_logic_vector(2 downto 0) := "011";
constant FUNC_XOR: std_logic_vector(2 downto 0) := "100";
constant FUNC_SRL_SRA: std_logic_vector(2 downto 0) := "101";
constant FUNC_OR: std_logic_vector(2 downto 0) := "110";
constant FUNC_AND: std_logic_vector(2 downto 0) := "111";
constant FUNC_FENCE: std_logic_vector(2 downto 0) := "000";
constant FUNC_FENCEI: std_logic_vector(2 downto 0) := "001";
constant FUNC_SCALL_SBREAK: std_logic_vector(2 downto 0) := "000";
constant FUNC_RD: std_logic_vector(2 downto 0) := "010";
constant R0: std_logic_vector(4 downto 0) := "00000";
constant R1: std_logic_vector(4 downto 0) := "00001";
constant R2: std_logic_vector(4 downto 0) := "00010";
constant R3: std_logic_vector(4 downto 0) := "00011";
constant R4: std_logic_vector(4 downto 0) := "00100";
constant R5, T0: std_logic_vector(4 downto 0) := "00101";
constant R6, T1: std_logic_vector(4 downto 0) := "00110";
constant R7, T2: std_logic_vector(4 downto 0) := "00111";
constant R8: std_logic_vector(4 downto 0) := "01000";
constant R9: std_logic_vector(4 downto 0) := "01001";
constant R10: std_logic_vector(4 downto 0) := "01010";
constant R11: std_logic_vector(4 downto 0) := "01011";
constant R12: std_logic_vector(4 downto 0) := "01100";
constant R13: std_logic_vector(4 downto 0) := "01101";
constant R14: std_logic_vector(4 downto 0) := "01110";
constant R15: std_logic_vector(4 downto 0) := "01111";
constant R16: std_logic_vector(4 downto 0) := "10000";
constant R17: std_logic_vector(4 downto 0) := "10001";
constant R18: std_logic_vector(4 downto 0) := "10010";
constant R19: std_logic_vector(4 downto 0) := "10011";
constant R20: std_logic_vector(4 downto 0) := "10100";
constant R21: std_logic_vector(4 downto 0) := "10101";
constant R22: std_logic_vector(4 downto 0) := "10110";
constant R23: std_logic_vector(4 downto 0) := "10111";
constant R24: std_logic_vector(4 downto 0) := "11000";
constant R25: std_logic_vector(4 downto 0) := "11001";
constant R26: std_logic_vector(4 downto 0) := "11010";
constant R27: std_logic_vector(4 downto 0) := "11011";
constant R28: std_logic_vector(4 downto 0) := "11100";
constant R29: std_logic_vector(4 downto 0) := "11101";
constant R30: std_logic_vector(4 downto 0) := "11110";
constant R31: std_logic_vector(4 downto 0) := "11111";
-- muxer ports
constant MUX_BUS_ADDR_PORTS: integer := 2;
constant MUX_BUS_ADDR_PORT_ALU: integer := 0;
constant MUX_BUS_ADDR_PORT_PC: integer := 1;
constant MUX_REG_DATA_PORTS: integer := 4;
constant MUX_REG_DATA_PORT_ALU: integer := 0;
constant MUX_REG_DATA_PORT_BUS: integer := 1;
constant MUX_REG_DATA_PORT_IMM: integer := 2;
constant MUX_REG_DATA_PORT_TRAPRET: integer := 3;
constant MUX_ALU_DAT1_PORTS: integer := 2;
constant MUX_ALU_DAT1_PORT_S1: integer := 0;
constant MUX_ALU_DAT1_PORT_PC: integer := 1;
constant MUX_ALU_DAT2_PORTS: integer := 3;
constant MUX_ALU_DAT2_PORT_S2: integer := 0;
constant MUX_ALU_DAT2_PORT_IMM: integer := 1;
constant MUX_ALU_DAT2_PORT_INSTLEN: integer := 2;
attribute enum_encoding : string;
-- ALU operations, signalled by decode unit
type aluops_t is (ALU_ADD, ALU_SUB, ALU_AND, ALU_OR, ALU_XOR, ALU_SLT, ALU_SLTU, ALU_SLL, ALU_SRL, ALU_SRA);
--attribute enum_encoding of aluops_t : type is "sequential";
-- commands for bus unit
type busops_t is (BUS_READB, BUS_READBU, BUS_READH, BUS_READHU, BUS_READW, BUS_WRITEB, BUS_WRITEH, BUS_WRITEW);
attribute enum_encoding of busops_t : type is "one-hot";
-- commands for program counter unit (PCU)
type pcuops_t is (PCU_SETPC, PCU_ENTERTRAP, PCU_RETTRAP, PCU_ENTERINT, PCU_RETINT);
attribute enum_encoding of pcuops_t : type is "one-hot";
-- commands for register unit
type regops_t is (REGOP_READ, REGOP_WRITE);
attribute enum_encoding of regops_t : type is "sequential";
end constants;
package body constants is
end constants;
|
mit
|
38bf71314764413c2c67b350b6de96d1
| 0.694415 | 2.788621 | false | false | false | false |
rbaummer/UART
|
nbit_synchronizer.vhd
| 1 | 1,019 |
--------------------------------------------------------------------------------
--
-- File: Synchronizer.vhd
-- Author: Rob Baummer
--
-- Description: Synchronizes I to clock using 2 flip flops
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nbit_synchronizer is
generic (
N : integer);
port (
clk : in std_logic;
reset : in std_logic;
I : in std_logic_vector(N-1 downto 0);
O : out std_logic_vector(N-1 downto 0)
);
end nbit_synchronizer;
architecture behavioral of nbit_synchronizer is
signal dff1 : std_logic_vector(N-1 downto 0);
signal dff2 : std_logic_vector(N-1 downto 0);
begin
--Dual synchronization registers
process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
dff1 <= (others => '0');
dff2 <= (others => '0');
else
dff1 <= I;
dff2 <= dff1;
end if;
end if;
end process;
--Synchronized output
O <= dff2;
end behavioral;
|
mit
|
42ca6597fe03e99e5d84c4417a36f95c
| 0.55054 | 3.419463 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/without screen/MIPScomoME/mips.vhd
| 1 | 8,004 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:45:27 11/28/2012
-- Design Name:
-- Module Name: mips - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.tipos.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mips is
port (clk, reset : in std_logic;
inst: out std_logic_vector(31 downto 0)
);
end mips;
architecture Behavioral of mips is
signal Estado, sig_estado: Estados;
--Señales memorias
--banco de registros
signal RW: std_logic_vector(4 downto 0);
signal busW, busB, busA: std_logic_vector(31 downto 0);
--memoria de instrucciones
--signal ADDR: std_logic_vector(4 downto 0);
signal DR: std_logic_vector(31 downto 0);
--memoria de datos
signal DRDat : std_logic_vector(31 downto 0);
signal RDat, WDat: std_logic;
--Señales Controles
--control ALU
signal ALUCtrl: std_logic_vector(1 downto 0);
--control saltos
signal EscrPC: std_logic;
signal salida: std_logic;
--control general
signal PcWriteCond0, PcWriteCond1, PcWriteCond2: std_logic;
signal Reg_Write: std_logic;
signal ALUOp0, ALUOp1, ALUOp2: std_logic;
signal ALUOp: std_logic_vector(2 downto 0);
signal RegDst, MemtoReg: std_logic;
signal ALUA,ALUB0,ALUB1, PcSrc0, PcSrc1:std_logic;
signal sig_estadoControl: Estados;
--Señales ALU
signal entradaA, entradaB: std_logic_vector(31 downto 0);
signal cero: std_logic;
signal mayorque: std_logic;
signal resultado: std_logic_vector(31 downto 0);
--Señales Extensor
signal extendido: std_logic_vector(31 downto 0);
--señales PC
signal loadPC: std_logic;
signal tempPC, PC: std_logic_vector(31 downto 0);
--registros temporales --
signal registroA, registroB, salidaALU, Instruction: std_logic_vector(31 downto 0);
signal entradaControl: std_logic_vector(5 downto 0);
signal tempA, tempB, tempSalidaALU, tempInstruction: std_logic_vector(31 downto 0);
signal loadA,loadB,loadSalidaALU, loadInstruction, loadEntradaControl: std_logic;
signal entradaExtensor: std_logic_vector(15 downto 0);
component MemoriaDeInstrucciones is
port( Clock: in std_logic;
ADDR: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0)
);
end component;
component MemoriaDeDatos is
port( Clock: in std_logic;
ADDR, write_addr: in std_logic_vector(4 downto 0);
DR : out std_logic_vector(31 downto 0);
DW: in std_logic_vector(31 downto 0);
R, W: in std_logic
);
end component;
component BancoDeRegistros is
port(
Clock: in std_logic;
Reg_Write: in std_logic;
RA: in std_logic_vector(4 downto 0);
RB: in std_logic_vector(4 downto 0);
RW: in std_logic_vector(4 downto 0);
busW: in std_logic_vector(31 downto 0);
busA: out std_logic_vector(31 downto 0);
busB: out std_logic_vector(31 downto 0)
);
end component;
component ExtensorSigno is
port(
A: in std_logic_vector (15 downto 0);
S: out std_logic_vector (31 downto 0)
);
end component;
component alu8bit is
port(
a, b : in std_logic_vector(31 downto 0);
op : in std_logic_vector(1 downto 0);
zero, bigthan : out std_logic;
result : out std_logic_vector(31 downto 0)
);
end component;
component control is
port(instruction: in std_logic_vector(5 downto 0);
Estado: in ESTADOS;
sig_estado: out ESTADOS;
RegDst, RegWrite, MemWrite, MemRead, MemtoReg, PcWriteCond0, PcWriteCond1, PcWriteCond2,
ALUOp0, ALUOp1, ALUOp2, ALUA, ALUB0, ALUB1, PcSrc0, PcSrc1, PcWrite:out std_logic
);
end component;
component AluControl is
port (funct: in std_logic_vector(5 downto 0);
AluOp:in std_logic_vector(2 downto 0);
--AluOp(1) es 1
AluCtr: out std_logic_vector(1 downto 0)
);
end component;
component ControlBranch is
port (cero , mayorque, saltar,EscrPC,EscrPC_Cond1,EscrPC_Cond2: in std_logic;--1 es menos significativo
salida: out std_logic
);
end component;
begin
ALUOp<=ALUOp2&ALUOp1&ALUOp0;
MemIns: MemoriaDeInstrucciones
port map(clk, PC(4 downto 0), DR);--siempre se lee nunca se escribe
MemDatos: MemoriaDeDatos
port map(clk, salidaALU(4 downto 0), salidaALU(4 downto 0), DRDat, registroB, RDat, WDat);
Banco_Registros: BancoDeRegistros
port map(clk, Reg_Write, DR(25 downto 21), DR(20 downto 16), RW, busW, busA, busB);
ControlSaltos: ControlBranch
port map(cero , mayorque, PcWriteCond2,EscrPC, PcWriteCond0,PcWriteCond1, salida);
ControlAlu: AluControl
port map(Instruction(5 downto 0), ALUOp, ALUCtrl);
ControlG: control
port map(entradaControl, Estado, sig_estadoControl,
RegDst, Reg_Write, WDat, RDat, MemtoReg, PcWriteCond0,PcWriteCond1,PcWriteCond2, ALUOp0, ALUOp1,
ALUOp2, ALUA, ALUB0, ALUB1, PcSrc0, PcSrc1, EscrPc);
ALU: alu8bit
port map(entradaA,entradaB, ALUCtrl, cero, mayorque, resultado);
Extensor: ExtensorSigno
port map(entradaExtensor,extendido);
RW<=Instruction(20 downto 16) when RegDst='0' else
Instruction(15 downto 11);
busW<= salidaALU when MemtoReg='0' else
DRDat;
entradaA<=PC when ALUA='0' else
registroA;
entradaB<= registroB when (ALUB1='0' and ALUB0='0') else
X"00000001" when (ALUB1='0' and ALUB0='1') else
extendido;
tempPC<= resultado when (PcSrc1='0' and PcSrc0='0') else
salidaALU when (PcSrc1='0' and PcSrc0='1') else
PC(31 downto 26)&Instruction(25 downto 0);
loadPC<=salida;
tempSalidaALU<=resultado;
tempInstruction<=DR;
tempA<=busA;
tempB<=busB;
sig_estado <= sig_estadoControl;
inst<=Instruction;
Síncrono: process(clk, reset)
begin
if reset='1' then
Estado<=F;
PC<=X"00000000";
elsif clk'event and clk ='1' then
Estado<=sig_estado;
if loadPC='1' then
PC<=tempPC;
end if;
if loadA='1' then
registroA<=tempA;
end if;
if loadB='1' then
registroB<=tempB;
end if;
if loadSalidaALU='1' then
salidaALU<=tempSalidaALU;
end if;
if loadInstruction='1' then
Instruction<=tempInstruction;
end if;
if loadEntradaControl='0' then
entradaControl <= DR(31 downto 26);
elsif loadEntradaControl='1' then
entradaControl <= Instruction(31 downto 26);
end if;
end if;
end process Síncrono;
Combinacional:process(clk,Estado--,registroA,registroB,salidaALU, PC
)
begin
case Estado is
when F =>
loadInstruction<='1';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl <= '0';
entradaExtensor <= DR(15 downto 0);--indefinido
when ID => --en ID la instrucción siempre es la correcta
loadInstruction<='1';
loadA<='1';
loadB<='1';
loadSalidaALU<='1';
loadEntradaControl<='0';
entradaExtensor <= DR(15 downto 0);
when EX =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='1';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
when MEM =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
when WB =>
loadInstruction<='0';
loadA<='0';
loadB<='0';
loadSalidaALU<='0';
loadEntradaControl<='1';
entradaExtensor <= Instruction(15 downto 0);
end case;
end process Combinacional;
end Behavioral;
|
gpl-2.0
|
9f8b09fbb5b525225e9a2213703f2604
| 0.656172 | 3.370105 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/BasicWatchWithBugs/Resolução/ClkDividerN.vhd
| 3 | 586 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ClkDividerN is
generic(divFactor : natural);
port(clkIn : in std_logic;
clkOut : out std_logic);
end ClkDividerN;
architecture RTL of ClkDividerN is
signal s_divCounter : natural;
begin
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_divCounter = divFactor - 1) then
clkOut <= '0';
s_divCounter <= 0;
else
if (s_divCounter = (divFactor / 2 - 1)) then
clkOut <= '1';
end if;
s_divCounter <= s_divCounter + 1;
end if;
end if;
end process;
end RTL;
|
gpl-2.0
|
7a8b8ca2d6c2cc82152550be9d64549c
| 0.650171 | 2.974619 | false | false | false | false |
ncareol/nidas
|
src/firmware/analog/sysctrl.vhd
| 1 | 17,910 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : sysctrl.vhf
-- /___/ /\ Timestamp : 02/10/2006 14:47:26
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w sysctrl.sch sysctrl.vhf
--Design Name: sysctrl
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
--library ieee;
--use ieee.std_logic_1164.ALL;
--use ieee.numeric_std.ALL;
---- synopsys translate_off
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
---- synopsys translate_on
--
--entity FD4CE_MXILINX_sysctrl is
-- port ( C : in std_logic;
-- CE : in std_logic;
-- CLR : in std_logic;
-- D0 : in std_logic;
-- D1 : in std_logic;
-- D2 : in std_logic;
-- D3 : in std_logic;
-- Q0 : out std_logic;
-- Q1 : out std_logic;
-- Q2 : out std_logic;
-- Q3 : out std_logic);
--end FD4CE_MXILINX_sysctrl;
--
--architecture BEHAVIORAL of FD4CE_MXILINX_sysctrl is
-- attribute BOX_TYPE : string ;
-- component FDCE
-- port ( C : in std_logic;
-- CE : in std_logic;
-- CLR : in std_logic;
-- D : in std_logic;
-- Q : out std_logic);
-- end component;
-- attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
--
--begin
-- U0 : FDCE
-- port map (C=>C,
-- CE=>CE,
-- CLR=>CLR,
-- D=>D0,
-- Q=>Q0);
--
-- U1 : FDCE
-- port map (C=>C,
-- CE=>CE,
-- CLR=>CLR,
-- D=>D1,
-- Q=>Q1);
--
-- U2 : FDCE
-- port map (C=>C,
-- CE=>CE,
-- CLR=>CLR,
-- D=>D2,
-- Q=>Q2);
--
-- U3 : FDCE
-- port map (C=>C,
-- CE=>CE,
-- CLR=>CLR,
-- D=>D3,
-- Q=>Q3);
--
--end BEHAVIORAL;
--library ieee;
--use ieee.std_logic_1164.ALL;
--use ieee.numeric_std.ALL;
---- synopsys translate_off
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
---- synopsys translate_on
--
--entity M2_1E_MXILINX_sysctrl is
-- port ( D0 : in std_logic;
-- D1 : in std_logic;
-- E : in std_logic;
-- S0 : in std_logic;
-- O : out std_logic);
--end M2_1E_MXILINX_sysctrl;
--
--architecture BEHAVIORAL of M2_1E_MXILINX_sysctrl is
-- attribute BOX_TYPE : string ;
-- signal M0 : std_logic;
-- signal M1 : std_logic;
-- component AND3
-- port ( I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- O : out std_logic);
-- end component;
-- attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
--
-- component AND3B1
-- port ( I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- O : out std_logic);
-- end component;
-- attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
--
-- component OR2
-- port ( I0 : in std_logic;
-- I1 : in std_logic;
-- O : out std_logic);
-- end component;
-- attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
--
--begin
-- I_36_30 : AND3
-- port map (I0=>D1,
-- I1=>E,
-- I2=>S0,
-- O=>M1);
--
-- I_36_31 : AND3B1
-- port map (I0=>S0,
-- I1=>E,
-- I2=>D0,
-- O=>M0);
--
-- I_36_38 : OR2
-- port map (I0=>M1,
-- I1=>M0,
-- O=>O);
--
--end BEHAVIORAL;
--
--
--
--library ieee;
--use ieee.std_logic_1164.ALL;
--use ieee.numeric_std.ALL;
---- synopsys translate_off
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
---- synopsys translate_on
--
--entity M2_1_MXILINX_sysctrl is
-- port ( D0 : in std_logic;
-- D1 : in std_logic;
-- S0 : in std_logic;
-- O : out std_logic);
--end M2_1_MXILINX_sysctrl;
--
--architecture BEHAVIORAL of M2_1_MXILINX_sysctrl is
-- attribute BOX_TYPE : string ;
-- signal M0 : std_logic;
-- signal M1 : std_logic;
-- component AND2B1
-- port ( I0 : in std_logic;
-- I1 : in std_logic;
-- O : out std_logic);
-- end component;
-- attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
--
-- component OR2
-- port ( I0 : in std_logic;
-- I1 : in std_logic;
-- O : out std_logic);
-- end component;
-- attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
--
-- component AND2
-- port ( I0 : in std_logic;
-- I1 : in std_logic;
-- O : out std_logic);
-- end component;
-- attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
--
--begin
-- I_36_7 : AND2B1
-- port map (I0=>S0,
-- I1=>D0,
-- O=>M0);
--
-- I_36_8 : OR2
-- port map (I0=>M1,
-- I1=>M0,
-- O=>O);
--
-- I_36_9 : AND2
-- port map (I0=>D1,
-- I1=>S0,
-- O=>M1);
--
--end BEHAVIORAL;
--
--
--
--library ieee;
--use ieee.std_logic_1164.ALL;
--use ieee.numeric_std.ALL;
---- synopsys translate_off
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
---- synopsys translate_on
--
--entity M8_1E_MXILINX_sysctrl is
-- port ( D0 : in std_logic;
-- D1 : in std_logic;
-- D2 : in std_logic;
-- D3 : in std_logic;
-- D4 : in std_logic;
-- D5 : in std_logic;
-- D6 : in std_logic;
-- D7 : in std_logic;
-- E : in std_logic;
-- S0 : in std_logic;
-- S1 : in std_logic;
-- S2 : in std_logic;
-- O : out std_logic);
--end M8_1E_MXILINX_sysctrl;
--
--architecture BEHAVIORAL of M8_1E_MXILINX_sysctrl is
-- attribute HU_SET : string ;
-- signal M01 : std_logic;
-- signal M03 : std_logic;
-- signal M23 : std_logic;
-- signal M45 : std_logic;
-- signal M47 : std_logic;
-- signal M67 : std_logic;
-- component M2_1E_MXILINX_sysctrl
-- port ( D0 : in std_logic;
-- D1 : in std_logic;
-- E : in std_logic;
-- S0 : in std_logic;
-- O : out std_logic);
-- end component;
--
-- component M2_1_MXILINX_sysctrl
-- port ( D0 : in std_logic;
-- D1 : in std_logic;
-- S0 : in std_logic;
-- O : out std_logic);
-- end component;
--
-- attribute HU_SET of U1 : label is "U1_6";
-- attribute HU_SET of U2 : label is "U2_5";
-- attribute HU_SET of U3 : label is "U3_4";
-- attribute HU_SET of U4 : label is "U4_3";
-- attribute HU_SET of U5 : label is "U5_1";
-- attribute HU_SET of U6 : label is "U6_0";
-- attribute HU_SET of U7 : label is "U7_2";
--begin
-- U1 : M2_1E_MXILINX_sysctrl
-- port map (D0=>D0,
-- D1=>D1,
-- E=>E,
-- S0=>S0,
-- O=>M01);
--
-- U2 : M2_1E_MXILINX_sysctrl
-- port map (D0=>D2,
-- D1=>D3,
-- E=>E,
-- S0=>S0,
-- O=>M23);
--
-- U3 : M2_1E_MXILINX_sysctrl
-- port map (D0=>D4,
-- D1=>D5,
-- E=>E,
-- S0=>S0,
-- O=>M45);
--
-- U4 : M2_1E_MXILINX_sysctrl
-- port map (D0=>D6,
-- D1=>D7,
-- E=>E,
-- S0=>S0,
-- O=>M67);
--
-- U5 : M2_1_MXILINX_sysctrl
-- port map (D0=>M01,
-- D1=>M23,
-- S0=>S1,
-- O=>M03);
--
-- U6 : M2_1_MXILINX_sysctrl
-- port map (D0=>M45,
-- D1=>M67,
-- S0=>S1,
-- O=>M47);
--
-- U7 : M2_1_MXILINX_sysctrl
-- port map (D0=>M03,
-- D1=>M47,
-- S0=>S2,
-- O=>O);
--
--end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity BUFE8_MXILINX_sysctrl is
port ( E : in std_logic;
I : in std_logic_vector (7 downto 0);
O : out std_logic_vector (7 downto 0));
end BUFE8_MXILINX_sysctrl;
architecture BEHAVIORAL of BUFE8_MXILINX_sysctrl is
attribute BOX_TYPE : string ;
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
begin
I_36_30 : BUFE
port map (E=>E,
I=>I(0),
O=>O(0));
I_36_31 : BUFE
port map (E=>E,
I=>I(1),
O=>O(1));
I_36_32 : BUFE
port map (E=>E,
I=>I(2),
O=>O(2));
I_36_33 : BUFE
port map (E=>E,
I=>I(3),
O=>O(3));
I_36_34 : BUFE
port map (E=>E,
I=>I(7),
O=>O(7));
I_36_35 : BUFE
port map (E=>E,
I=>I(6),
O=>O(6));
I_36_36 : BUFE
port map (E=>E,
I=>I(5),
O=>O(5));
I_36_37 : BUFE
port map (E=>E,
I=>I(4),
O=>O(4));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FD16CE_MXILINX_sysctrl is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic_vector (15 downto 0);
Q : out std_logic_vector (15 downto 0));
end FD16CE_MXILINX_sysctrl;
architecture BEHAVIORAL of FD16CE_MXILINX_sysctrl is
attribute BOX_TYPE : string ;
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
Q0 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(0),
Q=>Q(0));
Q1 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(1),
Q=>Q(1));
Q2 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(2),
Q=>Q(2));
Q3 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(3),
Q=>Q(3));
Q4 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(4),
Q=>Q(4));
Q5 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(5),
Q=>Q(5));
Q6 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(6),
Q=>Q(6));
Q7 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(7),
Q=>Q(7));
Q8 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(8),
Q=>Q(8));
Q9 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(9),
Q=>Q(9));
Q10 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(10),
Q=>Q(10));
Q11 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(11),
Q=>Q(11));
Q12 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(12),
Q=>Q(12));
Q13 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(13),
Q=>Q(13));
Q14 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(14),
Q=>Q(14));
Q15 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>D(15),
Q=>Q(15));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity sysctrl is
port ( A2DINT : in std_logic_vector (7 downto 0);
FIFOSTAT : in std_logic;
SIOR : in std_logic;
SIOWN : in std_logic;
SYSCTL : in std_logic;
A2DINTRP : out std_logic;
CAL_OFFSET : out std_logic_vector (15 downto 0);
BSD : inout std_logic_vector (15 downto 0));
end sysctrl;
architecture BEHAVIORAL of sysctrl is
attribute HU_SET : string ;
attribute BOX_TYPE : string ;
signal XLXN_21 : std_logic;
signal XLXN_23 : std_logic;
signal XLXN_40 : std_logic;
signal XLXN_41 : std_logic;
signal XLXN_42 : std_logic;
signal XLXN_43 : std_logic;
signal XLXN_52 : std_logic;
signal calnot : std_logic_vector(15 downto 0):=X"FFFF";
component FD16CE_MXILINX_sysctrl
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic_vector (15 downto 0);
Q : out std_logic_vector (15 downto 0));
end component;
component BUFE8_MXILINX_sysctrl
port ( E : in std_logic;
I : in std_logic_vector (7 downto 0);
O : out std_logic_vector (7 downto 0));
end component;
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
-- component M8_1E_MXILINX_sysctrl
-- port ( D0 : in std_logic;
-- D1 : in std_logic;
-- D2 : in std_logic;
-- D3 : in std_logic;
-- D4 : in std_logic;
-- D5 : in std_logic;
-- D6 : in std_logic;
-- D7 : in std_logic;
-- E : in std_logic;
-- S0 : in std_logic;
-- S1 : in std_logic;
-- S2 : in std_logic;
-- O : out std_logic);
-- end component;
--
-- component FD4CE_MXILINX_sysctrl
-- port ( C : in std_logic;
-- CE : in std_logic;
-- CLR : in std_logic;
-- D0 : in std_logic;
-- D1 : in std_logic;
-- D2 : in std_logic;
-- D3 : in std_logic;
-- Q0 : out std_logic;
-- Q1 : out std_logic;
-- Q2 : out std_logic;
-- Q3 : out std_logic);
-- end component;
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
attribute HU_SET of XLXI_1 : label is "XLXI_1_7";
attribute HU_SET of XLXI_3 : label is "XLXI_3_8";
-- attribute HU_SET of XLXI_15 : label is "XLXI_15_9";
-- attribute HU_SET of XLXI_16 : label is "XLXI_16_10";
begin
A2DINTRP <= A2DINT(0);
CAL_OFFSET <= not calnot;
XLXI_1 : FD16CE_MXILINX_sysctrl
port map (C=>SIOWN,
CE=>SYSCTL,
CLR=>XLXN_23,
D(15 downto 0)=> BSD(15 downto 0),
Q(15 downto 0)=> calnot(15 downto 0));
XLXI_3 : BUFE8_MXILINX_sysctrl
port map (E=>XLXN_21,
I(7 downto 0)=>A2DINT(7 downto 0),
O(7 downto 0)=>BSD(7 downto 0));
XLXI_8 : AND2
port map (I0=>SIOR,
I1=>SYSCTL,
O=>XLXN_21);
XLXI_9 : GND
port map (G=>XLXN_23);
-- XLXI_15 : M8_1E_MXILINX_sysctrl
-- port map (D0=>A2DINT(0),
-- D1=>A2DINT(1),
-- D2=>A2DINT(2),
-- D3=>A2DINT(3),
-- D4=>A2DINT(4),
-- D5=>A2DINT(5),
-- D6=>A2DINT(6),
-- D7=>A2DINT(7),
-- E=>XLXN_43,
-- S0=>XLXN_40,
-- S1=>XLXN_41,
-- S2=>XLXN_42,
-- O=>A2DINTRP);
--
-- XLXI_16 : FD4CE_MXILINX_sysctrl
-- port map (C=>SIOWN,
-- CE=>FIFOSTAT,
-- CLR=>XLXN_52,
-- D0=>BSD(0),
-- D1=>BSD(1),
-- D2=>BSD(2),
-- D3=>XLXN_52,
-- Q0=>XLXN_40,
-- Q1=>XLXN_41,
-- Q2=>XLXN_42,
-- Q3=>open);
XLXI_17 : GND
port map (G=>XLXN_52);
XLXI_19 : VCC
port map (P=>XLXN_43);
end BEHAVIORAL;
|
gpl-2.0
|
c0d362dc96952931964cbb3d16a73e18
| 0.422892 | 3.120753 | false | false | false | false |
miree/vhdl_cores
|
wishbone/wbp_mux.vhd
| 1 | 8,381 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- S S
-- |/
-- M
entity wbp_2s1m is
port (
clk_i : in std_logic;
slaves_i : in t_wbp_slave_in_array(0 to 1);
slaves_o : out t_wbp_slave_out_array(0 to 1);
master_o : out t_wbp_master_out;
master_i : in t_wbp_master_in
);
end entity;
architecture rtl of wbp_2s1m is
type t_state is (s_cyc0, s_cyc1);
signal state : t_state := s_cyc0;
signal slave0_prio : boolean;
begin
slave0_prio <= state = s_cyc0 or (state = s_cyc1 and slaves_i(1).cyc = '0');
master_o <= slaves_i(0) when slave0_prio and slaves_i(0).cyc = '1'
else slaves_i(1) when slaves_i(1).cyc = '1'
else (cyc=>'0',stb=>'0',we=>'-',sel=>(others=>'-'),adr=>(others=>'-'),dat=>(others=>'-'));
slaves_o(0) <= master_i when slave0_prio and slaves_i(0).cyc = '1'
else (ack=>'0',err=>'0',rty=>'0',stall=>'1',dat=>(others=>'-'));
slaves_o(1) <= master_i when state = s_cyc1 or (slaves_i(1).cyc = '1' and slaves_i(0).cyc = '0')
else (ack=>'0',err=>'0',rty=>'0',stall=>'1',dat=>(others=>'-'));
process
begin
wait until rising_edge(clk_i);
case state is
when s_cyc0 =>
if slaves_i(1).cyc = '1' and slaves_i(0).cyc = '0' then
state <= s_cyc1;
end if;
when s_cyc1 =>
if slaves_i(1).cyc = '0' then
state <= s_cyc0;
end if;
end case;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- S
-- /|
-- M M
entity wbp_1s2m is
generic (
adr_bit : natural
);
port (
clk_i : in std_logic;
slave_i : in t_wbp_slave_in;
slave_o : out t_wbp_slave_out;
masters_o : out t_wbp_master_out_array(0 to 1);
masters_i : in t_wbp_master_in_array(0 to 1)
);
end entity;
architecture rtl of wbp_1s2m is
signal master_o : t_wbp_master_out := c_wbp_master_out_init;
begin
master_o.cyc <= slave_i.cyc;
master_o.stb <= slave_i.stb;
master_o.we <= slave_i.we;
master_o.adr(31 downto adr_bit ) <= (others => '0');
master_o.adr(adr_bit-1 downto 0) <= slave_i.adr(adr_bit-1 downto 0);
master_o.dat <= slave_i.dat;
master_o.sel <= slave_i.sel;
masters_o(0) <= master_o when unsigned(slave_i.adr(31 downto adr_bit)) = 0
else (cyc=>'0',stb=>'0',we=>'-',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
masters_o(1) <= master_o when unsigned(slave_i.adr(31 downto adr_bit)) /= 0
else (cyc=>'0',stb=>'0',we=>'-',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
slave_o <= masters_i(0) when unsigned(slave_i.adr(31 downto adr_bit)) = 0
else masters_i(1);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- This implementation stalls if the adressed slave changes while
-- there are non-acked stbs on the previously adressed slave.
-- This is achieved by counting number of open stbs and costs more resources
-- S
-- /|
-- M M
entity wbp_1s2m_protected is
generic (
adr_bit : natural
);
port (
clk_i : in std_logic;
slave_i : in t_wbp_slave_in;
slave_o : out t_wbp_slave_out;
masters_o : out t_wbp_master_out_array(0 to 1);
masters_i : in t_wbp_master_in_array(0 to 1)
);
end entity;
architecture rtl of wbp_1s2m_protected is
type t_state is (s_idle, s_cyc0, s_cyc1);
signal state : t_state := s_idle;
signal sel_0, sel_1, stall: boolean := false;
signal inc_cnt, dec_cnt: boolean := false;
signal cnt : integer := 0;
begin
masters_o(0) <= slave_i when sel_0 and not stall
else (cyc=>'1',stb=>'0',we=>'-',adr=>(others=>'0'),dat=>(others=>'-'),sel=>(others=>'-')) when sel_0 and stall
else (cyc=>'0',stb=>'0',we=>'-',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
masters_o(1) <= slave_i when sel_1 and not stall
else (cyc=>'1',stb=>'0',we=>'-',adr=>(others=>'0'),dat=>(others=>'-'),sel=>(others=>'-')) when sel_1 and stall
else (cyc=>'0',stb=>'0',we=>'-',adr=>(others=>'-'),dat=>(others=>'-'),sel=>(others=>'-'));
slave_o <= (ack=>masters_i(0).ack,err=>masters_i(0).err,rty=>masters_i(0).rty,stall=>slave_i.cyc,dat=>masters_i(0).dat) when sel_0 and stall
else (ack=>masters_i(1).ack,err=>masters_i(1).err,rty=>masters_i(1).rty,stall=>slave_i.cyc,dat=>masters_i(1).dat) when sel_1 and stall
else masters_i(0) when sel_0
else masters_i(1) when sel_1
else (ack=>'-',err=>'-',rty=>'-',stall=>'-',dat=>(others=>'-'));
sel_0 <= (state = s_cyc0 and slave_i.cyc = '1') or
(state = s_idle and slave_i.adr(adr_bit) = '0') or
(state = s_cyc1 and slave_i.adr(adr_bit) = '0' and cnt = 0);
sel_1 <= (state = s_cyc1 and slave_i.cyc = '1') or
(state = s_idle and slave_i.adr(adr_bit) = '1') or
(state = s_cyc0 and slave_i.adr(adr_bit) = '1' and cnt = 0);
stall <= (state = s_cyc0 and slave_i.adr(adr_bit) = '1' and cnt /= 0) or
(state = s_cyc1 and slave_i.adr(adr_bit) = '0' and cnt /= 0);
lock: process
begin
wait until rising_edge(clk_i);
case state is
when s_idle =>
if slave_i.cyc = '1' then
if slave_i.adr(adr_bit) = '0' then
state <= s_cyc0;
else
state <= s_cyc1;
end if;
end if;
when s_cyc0 =>
if slave_i.cyc = '0' then
state <= s_idle;
elsif slave_i.adr(adr_bit) = '1' and ((cnt = 0) or (cnt = 1 and dec_cnt)) then
state <= s_cyc1;
end if;
when s_cyc1 =>
if slave_i.cyc = '0' then
state <= s_idle;
elsif slave_i.adr(adr_bit) = '0' and ((cnt = 0) or (cnt = 1 and dec_cnt)) then
state <= s_cyc0;
end if;
end case;
if inc_cnt then cnt <= cnt+1; end if;
if dec_cnt then cnt <= cnt-1; end if;
end process;
inc_cnt <= (sel_0 and masters_i(0).ack = '0' and masters_i(0).err = '0' and masters_i(0).rty = '0' and slave_i.stb = '1') or
(sel_1 and masters_i(1).ack = '0' and masters_i(1).err = '0' and masters_i(1).rty = '0' and slave_i.stb = '1');
dec_cnt <= (sel_0 and (masters_i(0).ack = '1' or masters_i(0).err = '1' or masters_i(0).rty = '1') and (slave_i.stb = '0' or stall)) or
(sel_1 and (masters_i(1).ack = '1' or masters_i(1).err = '1' or masters_i(1).rty = '1') and (slave_i.stb = '0' or stall));
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbp_pkg.all;
-- S S
-- |X|
-- M M
--
-- is build like this from basic blocks
-- S S
-- /| |\
-- M M M M
-- S S S S
-- | X |
-- | / \ |
-- |/ \|
-- M M
--
entity wbp_2s2m_crossbar is
generic (
adr_bit : natural
);
port (
clk_i : in std_logic;
slaves_i : in t_wbp_slave_in_array(0 to 1);
slaves_o : out t_wbp_slave_out_array(0 to 1);
masters_o : out t_wbp_master_out_array(0 to 1);
masters_i : in t_wbp_master_in_array(0 to 1)
);
end entity;
architecture rtl of wbp_2s2m_crossbar is
signal intermediate : t_wbp_array(0 to 3);
begin
spread_0: entity work.wbp_1s2m
generic map(adr_bit=>adr_bit)
port map(clk_i=>clk_i,
slave_i=>slaves_i(0),
slave_o=>slaves_o(0),
masters_o(0)=>intermediate(0).mosi,
masters_o(1)=>intermediate(1).mosi,
masters_i(0)=>intermediate(0).miso,
masters_i(1)=>intermediate(1).miso);
spread_1: entity work.wbp_1s2m
generic map(adr_bit=>adr_bit)
port map(clk_i=>clk_i,
slave_i=>slaves_i(1),
slave_o=>slaves_o(1),
masters_o(0)=>intermediate(2).mosi,
masters_o(1)=>intermediate(3).mosi,
masters_i(0)=>intermediate(2).miso,
masters_i(1)=>intermediate(3).miso);
combine_0: entity work.wbp_2s1m
port map(clk_i => clk_i,
slaves_i(0) => intermediate(0).mosi,
slaves_i(1) => intermediate(2).mosi,
slaves_o(0) => intermediate(0).miso,
slaves_o(1) => intermediate(2).miso,
master_o => masters_o(0),
master_i => masters_i(0));
combine_1: entity work.wbp_2s1m
port map(clk_i => clk_i,
slaves_i(0) => intermediate(1).mosi,
slaves_i(1) => intermediate(3).mosi,
slaves_o(0) => intermediate(1).miso,
slaves_o(1) => intermediate(3).miso,
master_o => masters_o(1),
master_i => masters_i(1));
end architecture;
|
mit
|
f4360726a7c9f5b99b73c492fddd5c34
| 0.567355 | 2.653055 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2-Separate/Part2-A/debounce.vhd
| 1 | 896 |
--------------------------------------------
-- Module Name: debounce - clean_pulse --
--------------------------------------------
-- Button debounce circuit;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity debounce is
port (
clk : in std_logic; -- make it low frequency
key : in std_logic; -- active low input
pulse : out std_logic
);
end debounce;
architecture clean_pulse of debounce is
signal cnt : std_logic_vector (1 downto 0);
begin
process (clk,key)
begin
if key = '1' then
cnt <= "00";
elsif (clk'event and clk = '1') then
if (cnt /= "11") then cnt <= cnt + 1; end if;
end if;
if (cnt = "10") and (key = '0') then
pulse <= '1';
else
pulse <= '0';
end if;
end process;
end clean_pulse;
|
gpl-3.0
|
48918855e8a8c5b329bf1edaeacea770
| 0.479911 | 3.912664 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 9/Parte IV/Ram1_N_demo.vhd
| 1 | 563 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram1_N_demo is
port( KEY : in std_logic_vector(0 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(7 downto 0));
end Ram1_N_demo;
architecture Behavioral of Ram1_N_demo is
begin
ram: entity work.Ram1_N(Behavioral)
generic map(addr => 4,
data => 8)
port map(clk => KEY(0),
writeenable => SW(0),
address => SW(17 downto 14),
writeData => SW(8 downto 1),
readData => LEDG(7 downto 0));
end Behavioral;
|
gpl-2.0
|
e14417c459d85e05361c196fbbe2968b
| 0.632327 | 2.73301 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/AluDemo.vhd
| 1 | 1,094 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity AluDemo is
port( SW : in std_logic_vector(17 downto 0);
LEDR: out std_logic_vector(7 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0));
end AluDemo;
architecture Structural of AluDemo is
signal s : std_logic_vector(3 downto 0);
begin
--Alu4: entity work.AluN(Behavioral)
-- generic map(N => 4)
-- port map(a => SW(7 downto 4),
-- b => SW(3 downto 0),
-- op => SW(17 downto 15),
-- m => LEDR(7 downto 4),
-- r2 => s,
-- r => LEDR(3 downto 0));
--Bin7SecDec: entity work.Bin7SecDec(Behavioral)
-- port map(binInput => s,
-- decOut_n => HEX7(6 downto 0));
aluDuaplay: entity work.AluDisplay(Behavioral)
generic map(N => 4)
port map(a => SW(7 downto 4),
b => SW(3 downto 0),
op => SW(17 downto 15),
r => LEDR(3 downto 0),
m => LEDR(7 downto 4),
decOut_n => HEX7(6 downto 0),
m2 => HEX6 (6 downto 0));
end Structural;
|
gpl-2.0
|
4ad921e82aefd7e6d74d5d44d7ee8363
| 0.563985 | 2.77665 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 3/PEnc4_2.vhd
| 2 | 669 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity PEnc4_2 is
port( decodedIn : in std_logic_vector(3 downto 0);
encodedOut : out std_logic_vector(1 downto 0);
validOut : out std_logic);
end PEnc4_2;
architecture BehavProcess of PEnc4_2 is
begin
process(decodedIn) is
begin
if (decodedIn(3) = '1') then
encodedOut<="11";
validOut<='1';
elsif (decodedIn(2) = '1') then
encodedOut<="10";
validOut<='1';
elsif (decodedIn(1) = '1') then
encodedOut<="01";
validOut<='1';
elsif (decodedIn(0) = '1') then
encodedOut<="00";
validOut<='1';
else
encodedOut<="00";
validOut<='0';
end if;
end process;
end BehavProcess;
|
gpl-2.0
|
c7ba5ba72e757d5f696a5237aa1929ea
| 0.635277 | 2.686747 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Compare2.vhd
| 1 | 4,373 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Compare2 is
port( randomnum0 : in std_logic_vector(3 downto 0);
usernum0 : in std_logic_vector(3 downto 0);
randomnum1 : in std_logic_vector(3 downto 0);
usernum1 : in std_logic_vector(3 downto 0);
randomnum2 : in std_logic_vector(3 downto 0);
usernum2 : in std_logic_vector(3 downto 0);
randomnum3 : in std_logic_vector(3 downto 0);
usernum3 : in std_logic_vector(3 downto 0);
cert : out std_logic_vector(3 downto 0);
erra : out std_logic_vector(3 downto 0);
clock : in std_logic;
reset : in std_logic);
end Compare2;
-- Entidade que compara os dois números recebidos e calcula os digitos nas posiçoes certas
-- e os digitos certos nas posições erradas.
architecture Behavioral of Compare2 is
type state is (S0, S1, S2);
signal CState, NState: state;
signal s_cert, s_erra: std_logic_vector(3 downto 0);
begin
process(clock)
variable comparar_user : unsigned(3 downto 0):= "0000";
variable comparar_rand : unsigned(3 downto 0):= "0000";
variable err : unsigned(3 downto 0) := "0000";
variable cer : unsigned(3 downto 0) := "0000";
begin
if(rising_edge(clock))then
case CState is
when S0 =>
err := "0000";
cer := "0000";
comparar_user := "0000";
comparar_rand := "0000";
if (reset = '1') then
NState <= S0;
else
NState <= S1;
end if;
when S1 =>
if (randomnum0 = usernum0) then
cer := cer +1;
comparar_user(0) := '1';
comparar_rand(0) := '1';
end if;
if (randomnum1 = usernum1) then
cer := cer +1;
comparar_user(1) := '1';
comparar_rand(1) := '1';
end if;
if (randomnum2 = usernum2) then
cer := cer +1;
comparar_user(2) := '1';
comparar_rand(2) := '1';
end if;
if (randomnum3 = usernum3) then
cer := cer +1;
comparar_user(3) := '1';
comparar_rand(3) := '1';
end if;
if(cer = 4)then
NState <= S2;
else
if (comparar_rand(0) = '0' ) then
if(randomnum0 = usernum1 and comparar_user(1) = '0') then
err := err + 1;
comparar_user(1) := '1';
elsif(randomnum0 = usernum2 and comparar_user(2) = '0') then
err := err + 1;
comparar_user(2) := '1';
elsif(randomnum0 = usernum3 and comparar_user(3) = '0') then
err := err + 1;
comparar_user(3) := '1';
end if;
end if;
if (comparar_rand(1) = '0') then
if(randomnum1 = usernum0 and comparar_user(0) = '0') then
err := err + 1;
comparar_user(0) := '1';
elsif(randomnum1 = usernum2 and comparar_user(2) = '0') then
err := err + 1;
comparar_user(2) := '1';
elsif(randomnum1 = usernum3 and comparar_user(3) = '0') then
err := err + 1;
comparar_user(3) := '1';
end if;
end if;
if (comparar_rand(2) = '0') then
if(randomnum2 = usernum0 and comparar_user(0) = '0') then
err := err + 1;
comparar_user(0) := '1';
elsif(randomnum2 = usernum1 and comparar_user(1) = '0') then
err := err + 1;
comparar_user(1) := '1';
elsif(randomnum2 = usernum3 and comparar_user(3) = '0') then
err := err + 1;
comparar_user(3) := '1';
end if;
end if;
if (comparar_rand(3) = '0') then
if(randomnum3 = usernum0 and comparar_user(0) = '0') then
err := err + 1;
comparar_user(0) := '1';
elsif(randomnum3 = usernum1 and comparar_user(1) = '0') then
err := err + 1;
comparar_user(1) := '1';
elsif(randomnum3 = usernum2 and comparar_user(2) = '0') then
err := err + 1;
comparar_user(2) := '1';
end if;
end if;
NState <= S2;
end if;
when S2 =>
if(reset = '1') then
NState <= S0;
end if;
when others =>
NState <= S0;
end case;
end if;
s_cert <= std_logic_vector(cer);
s_erra <= std_logic_vector(err);
end process;
process(NState)
begin
CState <= NState;
end process;
cert <= std_logic_vector(s_cert);
erra <= std_logic_vector(s_erra);
end Behavioral;
|
gpl-2.0
|
8a7ff4f5a61440d523fc91097f286290
| 0.549325 | 2.950034 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Demultiplexer.vhd
| 1 | 594 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Demultiplexer is
port( S : in std_logic_vector(1 downto 0);
out1, out2, out3, out4 : out std_logic);
end Demultiplexer;
-- Demultiplexer simples
architecture Behavioral of Demultiplexer is
begin
process(S)
begin
out1 <= '0';
out2 <= '0';
out3 <= '0';
out4 <= '0';
if(s="11") then
out4 <= '1';
elsif(s = "01") then
out2 <= '1';
elsif (s="10") then
out3 <= '1';
else
out1 <= '1';
end if;
end process;
end Behavioral;
|
gpl-2.0
|
4972fc5f8f8712a7f39144dad87eb89c
| 0.617845 | 2.687783 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Exercícios/BasicWatchWithBugs/Resolução/BasicWatchCore.vhd
| 1 | 4,747 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BasicWatchCore is
port(reset : in std_logic;
clk : in std_logic;
mode : in std_logic;
hSet : in std_logic;
mSet : in std_logic;
hTens : out std_logic_vector(6 downto 0);
hUnits : out std_logic_vector(6 downto 0);
mTens : out std_logic_vector(6 downto 0);
mUnits : out std_logic_vector(6 downto 0);
sTens : out std_logic_vector(6 downto 0);
sUnits : out std_logic_vector(6 downto 0);
sTick : out std_logic;
ledOut : out std_logic);
end BasicWatchCore;
architecture RTL of BasicWatchCore is
signal s_clk1Hz, s_clkFast : std_logic;
signal s_clk : std_logic;
signal s_sReset, s_finreset, treset, treset2 : std_logic;
signal s_sUnitsBin, s_sTensBin : std_logic_vector(3 downto 0);
signal s_mUnitsBin, s_mTensBin : std_logic_vector(3 downto 0);
signal s_hUnitsBin, s_hTensBin : std_logic_vector(3 downto 0);
signal s_sUnitsTerm, s_sTensTerm : std_logic;
signal s_mUnitsTerm, s_mTensTerm : std_logic;
signal s_hUnitsTerm : std_logic;
signal s_sUnitsEnb, s_sTensEnb : std_logic;
signal s_mUnitsEnb, s_mTensEnb : std_logic;
signal s_hUnitsEnb, s_hTensEnb : std_logic;
begin
clk_div_1hz : entity work.ClkDividerN(RTL)
generic map(divFactor => 50000000)
port map(clkIn => clk,
clkOut => s_clk1Hz);
clk_div_fast : entity work.ClkDividerN(RTL)
generic map(divFactor => 12500000)
port map(clkIn => clk,
clkOut => s_clkFast);
s_clk <= s_clk1Hz when (mode = '0') else
s_clkFast;
sTick <= s_clk;
s_sReset <= reset or mode;
s_sUnitsEnb <= '1';
treset <= s_finreset or s_sReset;
s_units_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 9)
port map(reset => treset,
clk => s_clk,
enable => s_sUnitsEnb,
valOut => s_sUnitsBin,
termCnt => s_sUnitsTerm);
s_sTensEnb <= s_sUnitsTerm or reset;
s_tens_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 5)
port map(reset => treset,
clk => s_clk,
enable => s_sTensEnb,
valOut => s_sTensBin,
termCnt => s_sTensTerm);
s_mUnitsEnb <= ((s_sTensTerm and s_sUnitsTerm) and not mode) or
reset or (mode and mSet);
treset2 <= s_finreset or reset;
m_units_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 9)
port map(reset => treset2,
clk => s_clk,
enable => s_mUnitsEnb,
valOut => s_mUnitsBin,
termCnt => s_mUnitsTerm);
s_mTensEnb <= (s_mUnitsTerm and s_mUnitsEnb) or reset;
m_tens_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 5)
port map(reset => treset2,
clk => s_clk,
enable => s_mTensEnb,
valOut => s_mTensBin,
termCnt => s_mTensTerm);
s_hUnitsEnb <= ((s_mTensTerm and s_mTensEnb) and not mode) or
reset or (mode and hSet);
h_units_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 9)
port map(reset => treset2,
clk => s_clk,
enable => s_hUnitsEnb,
valOut => s_hUnitsBin,
termCnt => s_hUnitsTerm);
s_hTensEnb <= (s_hUnitsTerm and s_hUnitsEnb) or reset;
h_tens_cnt : entity work.Counter4Bits(RTL)
generic map(MAX => 2)
port map(reset => treset2,
clk => s_clk,
enable => s_hTensEnb,
valOut => s_hTensBin,
termCnt => open);
process(s_hTensBin,s_hUnitsBin, s_mTensBin, s_mUnitsBin, s_sTensBin, s_sUnitsBin)
begin
if(s_hTensBin="0010" and s_hUnitsBin="0011" and s_mTensBin="0101" and s_mUnitsBin="1001" and s_sTensBin="0101" and s_sUnitsBin="1001") then
s_finreset <= '1';
ledOut <= '1';
else
s_finreset <= '0';
ledOut <= '0';
end if;
end process;
s_units_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_sUnitsBin,
decOut_n => sUnits);
s_tens_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_sTensBin,
decOut_n => sTens);
m_units_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_mUnitsBin,
decOut_n => mUnits);
m_tens_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_mTensBin,
decOut_n => mTens);
h_units_decod : entity work.Bin7SegDecoder(RTL)
port map(enable => '1',
binInput => s_hUnitsBin,
decOut_n => hUnits);
h_tens_decod : entity work.Bin7SegDecoderH(RTL)
port map(enable => '1',
binInput => s_hTensBin,
decOut_n => hTens);
end RTL;
|
gpl-2.0
|
0e7e57e0f5f7464b5feb11a8e8de0236
| 0.589214 | 2.928439 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2/CDiv.vhd
| 2 | 1,294 |
-----------------------------------
-- Module Name: CDiv - Divide --
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CDiv is
port(Cin : in std_logic;
TCvl : in integer;
Cout : out std_logic);
end CDiv;
-- Important values (for 50 MHz CLK):
-- 1 Hz -> TC = 84
-- 2 Hz -> TC = 71
-- 5 Hz -> TC = 56
-- 8 Hz -> TC = 50
-- 16 Hz -> TC = 42
-- 1 KHz (~987.6 Hz) -> TC = 15
-- 5 KHz -> TC = 10
architecture Divide of CDiv is
signal TC: integer; -- Time Constant
signal c0,c1,c2,c3: integer range 0 to 1000;
signal D: std_logic := '0';
begin
TC <= TCvl;
process(Cin, D)
begin
if (Cin'event and Cin='1') then
c0 <= c0 + 1;
if c0 = TC then
c0 <= 0;
c1 <= c1 + 1;
elsif c1 = TC then
c1 <= 0;
c2 <= c2 + 1;
elsif c2 = TC then
c2 <= 0;
c3 <= c3 + 1;
elsif c3 = TC then
c3 <= 0;
D <= NOT D;
end if;
end if;
Cout <= D;
end process ;
end Divide ;
|
gpl-3.0
|
e4b19ac7de81c8cb3afbc339f98b8173
| 0.38408 | 3.707736 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/attic/leds.vhd
| 1 | 772 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity leds is
Port(
I_addr: in std_logic_vector(31 downto 0);
I_clk: in std_logic;
I_data: in std_logic_vector(31 downto 0);
I_en: in std_logic;
I_write: in std_logic;
O_busy: out std_logic;
O_data: out std_logic_vector(31 downto 0);
O_leds: out std_logic_vector(7 downto 0)
);
end leds;
architecture Behavioral of leds is
signal led_value: std_logic_vector(7 downto 0) := X"00";
begin
O_leds <= led_value;
O_data <= led_value & X"000000";
O_busy <= '0';
process(I_clk)
begin
if rising_edge(I_clk) and I_en = '1' then
if I_write = '1' then
led_value <= I_data(31 downto 24);
end if;
end if;
end process;
end Behavioral;
|
mit
|
674df8c3d20f58ea6b84962deb602361
| 0.661917 | 2.531148 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2-Separate/Part2-A/Deb4Btns.vhd
| 1 | 957 |
------------------------------------------
-- module name: Deb4Btns - btnpulses --
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Hex4Dig2SSeg_Package.all;
entity Deb4Btns is
port (
clk : in std_logic;
btns : in std_logic_vector (3 downto 0);
pulses : out std_logic_vector (3 downto 0)
);
end Deb4Btns;
architecture btnpulses of Deb4Btns is
signal bp0, bp1, bp2, bp3 : std_logic := '0'; -- Button debounce pulses
begin
-- Assign the debounce pulses to buttons
bdb0: debounce port map (clk, btns(0), bp0);
bdb1: debounce port map (clk, btns(1), bp1);
bdb2: debounce port map (clk, btns(2), bp2);
bdb3: debounce port map (clk, btns(3), bp3);
pulses(0) <= '1' when bp0 = '1' else '0';
pulses(1) <= '1' when bp1 = '1' else '0';
pulses(2) <= '1' when bp2 = '1' else '0';
pulses(3) <= '1' when bp3 = '1' else '0';
end btnpulses;
|
gpl-3.0
|
8aa2476713a12dee2e8f145add50f35a
| 0.548589 | 3.137705 | false | false | false | false |
miree/vhdl_cores
|
maw/maw.vhd
| 1 | 1,797 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maw is
generic (
-- window width is 2^depth
depth : integer;
input_bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
value_i : in unsigned ( input_bit_width-1 downto 0 );
-- the ouput value's maximum is 2^input_bit_width * 2^depth
value_o : out unsigned ( input_bit_width+depth-1 downto 0 )
);
end entity;
architecture rtl of maw is
signal delayed : std_logic_vector ( input_bit_width-1 downto 0 );
signal sum : unsigned (input_bit_width+depth-1 downto 0);
signal add, sub : unsigned (input_bit_width+depth-1 downto 0);
begin
buf : entity work.delay
generic map (
depth => depth,
bit_width => input_bit_width
)
port map (
clk_i => clk_i,
rst_i => rst_i,
q_o => delayed, -- type conversion only works for inputs (see line below)
-- so here an additional signal is used for type matching
d_i => std_logic_vector(value_i)
);
process (clk_i)
variable leading_zeros : unsigned (depth-1 downto 0) := (others => '0');
begin
if rising_edge(clk_i) then
if rst_i = '1' then
value_o <= (others => '0');
sum <= (others => '0');
sub <= (others => '0');
add <= (others => '0');
else
add <= leading_zeros & value_i ;
sub <= leading_zeros & unsigned(delayed);
-- here it is imporatant to do the subtraction first,
-- otherwise the intermediate value can overflow (be greater than 2^input_bit_width * 2^depth)
sum <= sum - sub + add;
value_o <= sum;
end if;
end if;
end process;
end architecture;
|
mit
|
140bb07de7cae9f1f4b07641b8f86e73
| 0.559265 | 3.537402 | false | false | false | false |
miree/vhdl_cores
|
fifo/slow_read_fifo/testbench.vhd
| 1 | 3,184 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- package with component to test on this testbench
use work.fifo_pkg.all;
use work.guarded_fifo_pkg.all;
entity testbench is
end entity;
architecture simulation of testbench is
-- clock generation
constant clk_period : time := 20 ns;
constant clk_fast_period : time := 4 ns;
-- signals to connect to fifo
constant depth : integer := 2; -- the number of fifo entries is 2**depth
constant bit_width : integer := 32; -- number of bits in each entry
signal clk_fast : std_logic;
signal clk : std_logic;
signal rst_fast : std_logic;
signal rst : std_logic;
signal d, q : std_logic_vector ( bit_width-1 downto 0 );
signal push, data_acknowledge : std_logic;
signal full, data_ready : std_logic;
-- the value that is pushed to the fifo
signal ctr : std_logic_vector ( bit_width-1 downto 0 ) := (others => '0');
-- the value that is expected to be read from the fifo (initialized with -1)
signal expected : std_logic_vector ( bit_width-1 downto 0 ) := (others => '0');
begin
-- instantiate device under test (dut)
dut : work.guarded_fifo_pkg.guarded_fifo
generic map (
depth => depth ,
bit_width => bit_width
)
port map (
clk_fast_i => clk_fast,
clk_i => clk,
rst_fast_i => rst_fast,
rst_i => rst,
d_i => ctr,
q_o => q,
push_i => push,
dack_i => data_acknowledge,
full_o => full,
drdy_o => data_ready
);
clk_gen: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
clk_fast_gen: process
begin
wait for 0.567 ns;
for i in 0 to 1000000000 loop
clk_fast <= '0';
wait for clk_fast_period/2;
clk_fast <= '1';
wait for clk_fast_period/2;
end loop;
end process;
rst_initial: process
begin
rst <= '1';
rst_fast <= '1';
wait for clk_period*20;
rst <= '0';
rst_fast <= '0';
wait;
end process;
p_read_write : process
begin
push <= '0';
--=============================
-- fill fifo
--=============================
--wait for clk_period*40.5;
wait until falling_edge(rst);
for i in 0 to 10000 loop
wait until rising_edge(clk_fast);
push <= not push;
end loop;
end process;
p_read: process
begin
data_acknowledge <= '0';
for i in 0 to 10000 loop
wait until data_ready = '1';
wait for clk_period;
data_acknowledge <= '1';
wait for clk_period;
data_acknowledge <= '0';
end loop;
end process;
-- this process increments the counter (that is the value which is written to the fifo)
-- only on rising clock edges when the acknowledge signal was sent back from the fifo, i.e.
-- if a value was successfully pushed into the fifo.
p_increment_ctr : process(clk_fast)
begin
if rising_edge(clk_fast) then
if full = '0' and push = '1' then
ctr <= std_logic_vector(unsigned(ctr) + 1);
end if;
end if;
end process;
end architecture;
|
mit
|
04692bb91991832d0102ec0a806622b9
| 0.581658 | 3.537778 | false | false | false | false |
tejainece/VHDLExperiments
|
GoldschmidtDivider/Multiply16Booth4.vhd
| 1 | 3,756 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:23 01/22/2014
-- Design Name:
-- Module Name: Multiply16Booth4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Multiply16Booth4 is
PORT (
a: IN STD_LOGIC_VECTOR(15 downto 0);
b: IN STD_LOGIC_VECTOR(15 downto 0);
o: OUT STD_LOGIC_VECTOR(15 downto 0));
end Multiply16Booth4;
architecture Behavioral of Multiply16Booth4 is
COMPONENT BoothPartProdGen is
PORT (
bin3: in STD_LOGIC_VECTOR(2 downto 0);
a: in STD_LOGIC_VECTOR(15 downto 0);
product: out STD_LOGIC_VECTOR(16 downto 0)
);
end COMPONENT;
COMPONENT BoothPartProdRed is
PORT(
prod0: in STD_LOGIC_VECTOR(19 downto 0);
prod1: in STD_LOGIC_VECTOR(20 downto 2);
prod2: in STD_LOGIC_VECTOR(22 downto 4);
prod3: in STD_LOGIC_VECTOR(24 downto 6);
prod4: in STD_LOGIC_VECTOR(26 downto 8);
prod5: in STD_LOGIC_VECTOR(28 downto 10);
prod6: in STD_LOGIC_VECTOR(30 downto 12);
prod7: in STD_LOGIC_VECTOR(31 downto 14);
result: out STD_LOGIC_VECTOR(31 downto 0));
end COMPONENT;
SIGNAL aTmp: STD_LOGIC_VECTOR(16 downto 0);
SIGNAL oTmp: STD_LOGIC_VECTOR(31 downto 0);
SIGNAL prod0: STD_LOGIC_VECTOR(19 downto 0);
SIGNAL prod1: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod2: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod3: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod4: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod5: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod6: STD_LOGIC_VECTOR(18 downto 0);
SIGNAL prod7: STD_LOGIC_VECTOR(17 downto 0);
begin
aTmp <= a & '0';
prod0(19 downto 17) <= (not prod0(16)) & prod0(16) & prod0(16);
prod1(18 downto 17) <= '1' & (not prod1(16));
prod2(18 downto 17) <= '1' & (not prod2(16));
prod3(18 downto 17) <= '1' & (not prod3(16));
prod4(18 downto 17) <= '1' & (not prod4(16));
prod5(18 downto 17) <= '1' & (not prod5(16));
prod6(18 downto 17) <= '1' & (not prod6(16));
prod7(17) <= not prod7(16);
prodgen0: BoothPartProdGen PORT MAP (
bin3 => aTmp(2 downto 0),
a => b,
product => prod0(16 downto 0)
);
prodgen1: BoothPartProdGen PORT MAP (
bin3 => aTmp(4 downto 2),
a => b,
product => prod1(16 downto 0)
);
prodgen2: BoothPartProdGen PORT MAP (
bin3 => aTmp(6 downto 4),
a => b,
product => prod2(16 downto 0)
);
prodgen3: BoothPartProdGen PORT MAP (
bin3 => aTmp(8 downto 6),
a => b,
product => prod3(16 downto 0)
);
prodgen4: BoothPartProdGen PORT MAP (
bin3 => aTmp(10 downto 8),
a => b,
product => prod4(16 downto 0)
);
prodgen5: BoothPartProdGen PORT MAP (
bin3 => aTmp(12 downto 10),
a => b,
product => prod5(16 downto 0)
);
prodgen6: BoothPartProdGen PORT MAP (
bin3 => aTmp(14 downto 12),
a => b,
product => prod6(16 downto 0)
);
prodgen7: BoothPartProdGen PORT MAP (
bin3 => aTmp(16 downto 14),
a => b,
product => prod7(16 downto 0)
);
output: BoothPartProdRed PORT MAP (
prod0 => prod0,
prod1 => prod1,
prod2 => prod2,
prod3 => prod3,
prod4 => prod4,
prod5 => prod5,
prod6 => prod6,
prod7 => prod7,
result => oTmp
);
o <= oTmp(23 downto 8);
end Behavioral;
|
gpl-3.0
|
aa6b4ab699ddab7d888fccd105ab201d
| 0.624334 | 3.048701 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 2/Bin7Seg.vhd
| 2 | 980 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Bin7Seg is
port( binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0));
end Bin7Seg;
architecture Behavioral of Bin7Seg is
begin
decOut_n <= "1111001" when binInput="0001" else --1
"0100100" when binInput="0010" else --2
"0110000" when binInput="0011" else --3
"0011001" when binInput="0100" else --4
"0010010" when binInput="0101" else --5
"0000010" when binInput="0110" else --6
"1111000" when binInput="0111" else --7
"0000000" when binInput="1000" else --8
"0010000" when binInput="1001" else --9
"0001000" when binInput="1010" else --A
"0000011" when binInput="1011" else --B
"1000110" when binInput="1100" else --C
"0100001" when binInput="1101" else --D
"0000110" when binInput="1110" else --E
"0001110" when binInput="1111" else --F
"1000000"; --0
end Behavioral;
|
gpl-2.0
|
c0d40cc8ac2ff7e584d8d23c23865fd3
| 0.644898 | 3.277592 | false | false | false | false |
tutugordillo/Computer-Technology
|
TOC/mips as state machine/with screen/MIPSconPantallaME/BancoDeRegistros.vhd
| 1 | 3,298 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:44:15 11/21/2012
-- Design Name:
-- Module Name: BancoDeRegistros - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BancoDeRegistros is
--generic( P: integer:=32; -- ancho de palabra
--N: integer:=32; -- nº de palabras
--tam_addr: integer:=5); -- ancho dirección
port( Clock: in std_logic;
Reg_Write: in std_logic;
RA: in std_logic_vector(4 downto 0);
RB: in std_logic_vector(4 downto 0);
RW: in std_logic_vector(4 downto 0);
busW: in std_logic_vector(31 downto 0);
busA: out std_logic_vector(31 downto 0);
busB: out std_logic_vector(31 downto 0);
reg0: out std_logic_vector(31 downto 0);
reg1: out std_logic_vector(31 downto 0);
reg2: out std_logic_vector(31 downto 0);
reg3: out std_logic_vector(31 downto 0)
);
end BancoDeRegistros;
architecture Behavioral of BancoDeRegistros is
type br_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal tmp: br_type:=(
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000011000000000000000",
"00000000000000000000100000000001",
"00000000000000000000000000000111",
"00000000000000000000000000000001",
"00000000000000000000000000000110",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000000001",
"00000000000000000000000000000000",
"00000000000000000000000000001111");
begin
-- Lectura asíncrona
busA <= tmp(conv_integer(RA));
busB <= tmp(conv_integer(RB));
reg0 <= tmp(conv_integer(0));
reg1 <= tmp(conv_integer(1));
reg2 <= tmp(conv_integer(2));
reg3 <= tmp(conv_integer(3));
-- Escritura
process(Clock, Reg_Write)
begin
if (Clock'event and Clock='1') then
if Reg_Write='1' then
tmp(conv_integer(RW)) <= busW;
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
f44b9ddf04d41cb7d450807113fadc2c
| 0.711037 | 4.148428 | false | false | false | false |
jpcofr/PDUAMaude
|
PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/pdua.vhdl
| 1 | 5,038 |
-- *******************************************************
-- ** PDUA **
-- ** PROCESADOR DIDACTICO **
-- ** Arquitectura y Diseno de Sistemas Digitales **
-- ** UNIVERSIDAD DE LOS ANDES **
-- *******************************************************
-- ** Version 0.0 Arquitectura basica. **
-- ** Por: Mauricio Guerrero H. **
-- ** Junio 2007 **
-- ** Revision 0.1 Noviembre 2007 **
-- ** Conjunto de Instrucciones **
-- ** Memoria Doble Puerto **
-- ** Por: Diego Mendez Chaves **
-- ** Mauricio Guerrero H. **
-- ** Revision 0.2 Marzo de 2008 **
-- ** ALU BIT_SLICE **
-- ** Por: Mauricio Guerrero H. **
-- *******************************************************
-- Descripcion: CLK| |Rst_n
-- ____|____|_____
-- | |
-- INT -->| |<-- Bus_DATA_in
-- IOM <--| |--> Bus_DATA_out
-- RW <--| |--> Bus_DIR
-- |_______________|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pdua is
Port ( clk : in std_logic;
rst_n : in std_logic;
int : in std_logic;
iom : out std_logic; -- IO=0,M=1
rw : out std_logic; -- R=0,W=1
bus_dir : out std_logic_vector(7 downto 0);
bus_data_in : in std_logic_vector(7 downto 0);
bus_data_out : out std_logic_vector(7 downto 0));
end pdua;
architecture Behavioral of pdua is
component ctrl is
Port ( clk : in std_logic;
rst_n : in std_logic;
urst_n : in std_logic;
HRI : in std_logic;
INST : in std_logic_vector(4 downto 0);
C : in std_logic;
Z : in std_logic;
N : in std_logic;
P : in std_logic;
INT : in std_logic;
COND : in std_logic_vector(2 downto 0);
DIR : in std_logic_vector(2 downto 0);
UI : out std_logic_vector(24 downto 0));
end component;
component banco is
Port ( CLK : in std_logic;
RESET_n : in std_logic;
HR : in std_logic;
SC,SB : in std_logic_vector(2 downto 0);
BUSC : in std_logic_vector(7 downto 0);
BUSA,BUSB : out std_logic_vector(7 downto 0)
);
end component;
component ALU is
Port (CLK,HF: in std_logic;
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
SELOP : in std_logic_vector(2 downto 0);
DESP : in std_logic_vector(1 downto 0);
S : inout std_logic_vector(7 downto 0);
C,N,Z,P : out std_logic
);
end component;
component MAR is
Port ( CLK : in std_logic;
BUS_DIR: out std_logic_vector(7 downto 0);
BUS_C : in std_logic_vector(7 downto 0);
HMAR : in std_logic);
end component;
component MDR is
Port ( DATA_EX_in : in std_logic_vector(7 downto 0);
DATA_EX_out : out std_logic_vector(7 downto 0);
DATA_ALU : in std_logic_vector(7 downto 0);
DATA_C : out std_logic_vector(7 downto 0);
HMDR : in std_logic;
RD_WR : in std_logic);
end component;
signal hf, hr, urst_n, hri, C, Z, N, P ,HMAR, HMDR : std_logic;
signal sc, sb, cond : std_logic_vector(2 downto 0);
signal func,dir : std_logic_vector(2 downto 0);
signal busa, busb, busc, bus_alu : std_logic_vector(7 downto 0);
signal desp : std_logic_vector(1 downto 0);
signal ui : std_logic_vector(24 downto 0);
begin
-- Microinstruccion
hf <= ui(24); -- Habilitador de almacenamiento de banderas
sb <= ui(23 downto 21); -- Selector bus B (salida)
func <= ui(20 downto 18); -- Selector funcion ALU
desp <= ui(17 downto 16); -- Habilitador desplazamiento
sc <= ui(15 downto 13); -- Selector bus C (entrada)
hr <= ui(12); -- Habilitador registro destino
HMAR <= ui(11); -- Habilitador MAR
HMDR <= ui(10); -- Habilitador MDR
RW <= ui(9); -- Read/Write 0/1
iom <= ui(8); -- IO/MEM 0/1
hri <= ui(7); -- Habilitador registro instruccion
urst_n <= ui(6); -- Reset de microcontador
cond <= ui(5 downto 3); -- Condicion de salto
dir <= ui(2 downto 0); -- Micro-offset de salto
u1: ctrl port map (clk,rst_n,urst_n,hri,busc(7 downto 3),C,Z,N,P,int,cond,dir,ui);
u2: banco port map (clk, rst_n, hr, sc, sb, busc, busa, busb);
u3: alu port map (clk,hf,busa, busb, func, desp, bus_alu, C, N, Z, P );
u4: mar port map (clk, bus_dir, busc, HMAR );
u5: mdr port map (bus_data_in,bus_data_out,bus_alu,busc,HMDR,ui(9));
end Behavioral;
|
mit
|
a0af38ad85f1fea820988a645c2a4da9
| 0.485113 | 3.06821 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 9/Parte IV/Ram1_N.vhd
| 1 | 761 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Ram1_n is
generic( addr : natural := 8;
data : natural := 4);
port( clk : in std_logic;
writeEnable : in std_logic;
address : in std_logic_vector(addr-1 downto 0);
writeData : in std_logic_vector(data-1 downto 0);
readData : out std_logic_vector(data-1 downto 0));
end Ram1_N;
architecture Behavioral of Ram1_n is
type ram is array(0 to (2**addr-1)) of std_logic_vector(0 to (data-1));
signal memory : ram;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(writeEnable='1') then
memory(to_integer(unsigned(address))) <= writeData;
end if;
end if;
end process;
readData <= memory(to_integer(unsigned(address)));
end Behavioral;
|
gpl-2.0
|
a9632b916feb47451d3e03fd07e79856
| 0.672799 | 2.73741 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Aula 7/Parte 1/Chronometer.vhd
| 1 | 808 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Chronometer is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0));
end Chronometer;
architecture Shell of Chronometer is
begin
system_core : entity work.ChronometerCore(Structural)
port map(reset => not KEY(3),
clk50MHz => CLOCK_50,
statop => KEY(0),
laprst => KEY(1),
dispOut0_n => HEX2,
dispOut1_n => HEX3,
dispOut2_n => HEX4,
dispOut3_n => HEX5,
dispOut4_n => HEX6,
dispOut5_n => HEX7);
end Shell;
|
gpl-2.0
|
a99d4c2bd96a4a35131dd6a1422868a0
| 0.631188 | 2.631922 | false | false | false | false |
ncareol/nidas
|
src/firmware/usb2d/Fast2D/new2d.vhd
| 1 | 11,522 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
entity new2d is
port(
in1_bus:in std_logic_vector(15 downto 0);
in2_bus:in std_logic_vector(15 downto 0);
in3_bus:in std_logic_vector(15 downto 0);
in4_bus:in std_logic_vector(15 downto 0);
fullflag:in std_logic;
emptyflag: in std_logic;
add_bus_hi:in std_logic;
add_bus_lo:in std_logic_vector(3 downto 0);
data_bus:inout std_logic_vector(7 downto 0);
fd_bus:inout std_logic_vector(15 downto 0);
clkin:in std_logic; -- 48 MHz
psen:in std_logic;
rd:in std_logic;
wr:in std_logic;
reset:in std_logic;
particle: in std_logic;
dof:in std_logic;
ram_ce:out std_logic;
ram_rd:out std_logic;
ram_wr:out std_logic;
tasbase:in std_logic;
tas:out std_logic;
slwr: out std_logic;
fifoadr0: out std_logic;
fifoadr1: out std_logic;
pktend: out std_logic;
oscdiv: out std_logic;
debug:out std_logic);
end new2d;
Architecture behavior of new2d is
--Below here is 2dmuxusb1
signal sync_pattern: std_logic_vector(15 downto 0);
signal time_count: std_logic_vector(39 downto 0);
signal in1_latch: std_logic_vector(15 downto 0);
signal in2_latch: std_logic_vector(15 downto 0);
signal in3_latch: std_logic_vector(15 downto 0);
signal in4_latch: std_logic_vector(15 downto 0);
signal particle_flag: std_logic;
signal tas_old2: std_logic;
signal tas_old1: std_logic;
signal sreset: std_logic:='0';
signal progtas: std_logic;
signal tdiv: std_logic_vector(1 downto 0);
signal tcnt: std_logic_vector(1 downto 0);
signal shdwor: std_logic_vector(15 downto 0):=X"0000";
signal particle_old2: std_logic:='0';
signal particle_old1: std_logic:='0';
signal tasbase_old2: std_logic:='0';
signal tasbase_old1: std_logic:='0';
signal sread0: std_logic;
signal sread1: std_logic;
signal pkend: std_logic;
signal div2clk: std_logic;
signal div4clk: std_logic;
signal div8clk: std_logic;
signal clkcount: std_logic_vector(2 downto 0):="000";
signal start_flag: std_logic:='0';
signal stateflag: std_logic;
signal shadflag: std_logic;
signal shadflag_old2: std_logic;
signal shadflag_old1: std_logic;
signal sync: std_logic:='1';
signal ifclk: std_logic;
type state_value is (s0,s1,s2,s3,s4,s5,s6,s7);
signal state: state_value;
signal next_state: state_value;
begin
sync_pattern <= "1010101010101010";
fifoadr0 <= '0';
fifoadr1 <= '0';
pktend <= pkend;
ifclk <= not clkin;
--0x000
progtas <= psen and add_bus_hi
and not add_bus_lo(3)
and not add_bus_lo(2)
and not add_bus_lo(1)
and not add_bus_lo(0)
and not wr;
--0x011
-- debug <= psen and add_bus_hi
-- and not add_bus_lo(3)
-- and not add_bus_lo(2)
-- and add_bus_lo(1)
-- and add_bus_lo(0)
-- and not wr;
--0x100
sreset <= psen and add_bus_hi
and not add_bus_lo(3)
and add_bus_lo(2)
and not add_bus_lo(1)
and not add_bus_lo(0)
and not wr;
--0x1001
sread0 <= psen and add_bus_hi
and add_bus_lo(3)
and not add_bus_lo(2)
and not add_bus_lo(1)
and add_bus_lo(0)
and not rd;
--0x1010
sread1 <= psen and add_bus_hi
and add_bus_lo(3)
and not add_bus_lo(2)
and add_bus_lo(1)
and not add_bus_lo(0)
and not rd;
clock2: process(ifclk,reset,sreset) --Divide 48 MHz by 2 = 24 MHz
begin
if reset = '1' or sreset = '1' then
div2clk <= '0';
div4clk <= '0';
div8clk <= '0';
clkcount <= "000";
else
if rising_edge(ifclk) then
clkcount <= clkcount + 1;
if clkcount(0) = '0' then
div2clk <= '0';
else
div2clk <= '1';
end if;
if clkcount(0) = '0' and clkcount(1) = '0' then
div4clk <= '1';
else
if clkcount(0) = '0' and clkcount(1) = '1' then
div4clk <= '0';
end if;
end if;
if clkcount = "000" then
div8clk <= '1';
else
if clkcount = "100" then
div8clk <= '0';
end if;
end if;
end if;
end if;
end process clock2;
ram: process(ifclk,reset,sreset)
begin
if reset = '1' or sreset = '1' then
ram_ce <= '1';
ram_rd <= '1';
ram_wr <= '1';
else
ram_ce <= not add_bus_hi;
ram_rd <= rd or psen;
ram_wr <= wr;
end if;
end process ram;
nextstate: process(ifclk,reset,sreset)
begin
if reset = '1' or sreset = '1' then
state <= s0;
if emptyflag = '1' then
pkend <= '0';
end if;
else
pkend <= '1';
if falling_edge(ifclk) then
state <= next_state;
end if;
end if;
end process nextstate;
machine: process(ifclk,reset,sreset)
begin
slwr <= '1';
if reset = '1' or sreset = '1' then
next_state <= s0;
elsif rising_edge(ifclk) then
tasbase_old2 <= tasbase_old1;
tasbase_old1 <= tasbase;
if tasbase_old2 = '0' and tasbase_old1 = '1' then
in1_latch <= in1_bus;
in2_latch <= in2_bus;
in3_latch <= in3_bus;
in4_latch <= in4_bus;
end if;
case state is
when s0=> -- wait for particle strobe
if tasbase_old2 = '0' and tasbase_old1 = '1' and
particle_flag = '1' then
if fullflag = '1' then
fd_bus(15 downto 8) <= in4_latch(7 downto 0);
fd_bus(7 downto 0) <= in4_latch(15 downto 8);
slwr <= '0';
start_flag <= '1';
next_state <= s1;
else
sync <= '0';
next_state <= s0;
end if;
else
if particle_flag = '0' and start_flag = '1' then
next_state <= s4;
else
next_state <= s0;
end if;
end if;
when s1=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= in3_latch(7 downto 0);
fd_bus(7 downto 0) <= in3_latch(15 downto 8);
slwr <= '0';
next_state <= s2;
else
sync <= '0';
next_state <= s1;
end if;
when s2=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= in2_latch(7 downto 0);
fd_bus(7 downto 0) <= in2_latch(15 downto 8);
slwr <= '0';
next_state <= s3;
else
sync <= '0';
next_state <= s2;
end if;
when s3=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= in1_latch(7 downto 0);
fd_bus(7 downto 0) <= in1_latch(15 downto 8);
slwr <= '0';
if particle_flag = '0' then
next_state <= s4;
else
next_state <= s0;
end if;
else
sync <= '0';
next_state <= s3;
end if;
when s4=> -- write sync and time stamp
if fullflag = '1' then
start_flag <= '0';
if sync = '1' then
fd_bus(15 downto 0) <= sync_pattern(15 downto 0);
else
fd_bus(15 downto 0) <= not sync_pattern(15 downto 0);
end if;
slwr <= '0';
next_state <= s5;
else
next_state <= s4;
end if;
when s5=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= time_count(39 downto 32);
fd_bus(7 downto 0) <= sync_pattern(7 downto 0);
slwr <= '0';
next_state <= s6;
else
next_state <= s5;
end if;
when s6=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= time_count(23 downto 16);
fd_bus(7 downto 0) <= time_count(31 downto 24);
slwr <= '0';
next_state <= s7;
else
next_state <= s6;
end if;
when s7=> -- latch data and send to USB fifo
if fullflag = '1' then
fd_bus(15 downto 8) <= time_count(7 downto 0);
fd_bus(7 downto 0) <= time_count(15 downto 8);
slwr <= '0';
sync <= '1';
next_state <= s0;
else
next_state <= s7;
end if;
end case;
else
next_state <= next_state;
end if;
end process machine;
tascnt: process(tasbase, reset, sreset)
begin
if reset = '1' or sreset = '1' then
tcnt <= "00";
else
if rising_edge(tasbase) then
tcnt <= tcnt + 1;
end if;
end if;
end process tascnt;
databus: process(reset,progtas,sreset,sread0,sread1)
begin
if reset = '1' or sreset = '1' then
tdiv(1 downto 0) <= "00";
end if;
if progtas = '1' then
tdiv(1 downto 0) <= data_bus(1 downto 0);
else
tdiv(1 downto 0) <= tdiv(1 downto 0);
end if;
if sread0 = '1' then
data_bus(7 downto 0) <= shdwor(7 downto 0);
shadflag <= '0';
elsif sread1 = '1' then
data_bus(7 downto 0) <= shdwor(15 downto 8);
shadflag <= '1';
else
data_bus(7 downto 0) <= "ZZZZZZZZ";
end if;
end process databus;
airspeed: process(reset,tdiv,sreset)
begin
if reset = '1' or sreset = '1' then
tas <= '0';
oscdiv <= '0';
else
case tdiv(1 downto 0) is
when "00" =>
tas <= tcnt(1);
oscdiv <= '0';
when "01" =>
tas <= tcnt(1);
oscdiv <= 'Z';
when others =>
tas <= '0';
end case;
end if;
end process airspeed;
ParticleCounter: process (ifclk)
begin
if falling_edge(ifclk) then
particle_old2 <= particle_old1;
particle_old1 <= particle;
shadflag_old2 <= shadflag_old1;
shadflag_old1 <= shadflag;
if particle_old2 = '1' and particle_old1 = '0' then
shdwor <= shdwor + 1;
if dof = '1' then
debug <= '1';
particle_flag <= '1';
end if;
end if;
if particle_old2 = '0' and particle_old1 = '1' then
particle_flag <= '0';
debug <= '0';
end if;
if shadflag_old2 = '0' and shadflag_old1 = '1' then
shdwor(15 downto 0) <= X"0000";
end if;
end if;
end process ParticleCounter;
-- count_time: process(tasbase,reset,sreset)
count_time: process(div4clk,reset,sreset)
begin
if reset = '1' or sreset = '1' then
-- time_count (37 downto 36) <= "00";
time_count(39 downto 0) <= X"0000000000";
else
if time_count(39 downto 0) = X"FFFFFFFFFF" then
-- time_count (37 downto 36) <= "00";
time_count(39 downto 0) <= X"0000000000";
-- elsif rising_edge(tasbase) then
elsif rising_edge(div4clk) then
time_count <= time_count + 1;
else
time_count(39 downto 0) <= time_count(39 downto 0);
end if;
end if;
end process count_time;
end behavior;
|
gpl-2.0
|
afb5bee6db37f583febf30c2909c6930
| 0.513973 | 3.376905 | false | false | false | false |
maikmerten/riscv-tomthumb
|
src/vhdl/vga/vga_wb8_tb.vhd
| 1 | 1,456 |
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity vga_wb8_tb is
end vga_wb8_tb;
architecture Behavior of vga_wb8_tb is
component vga_wb8
Port(
-- naming according to Wishbone B4 spec
ADR_I: in std_logic_vector(31 downto 0);
CLK_I: in std_logic;
DAT_I: in std_logic_vector(7 downto 0);
STB_I: in std_logic;
WE_I: in std_logic;
ACK_O: out std_logic;
DAT_O: out std_logic_vector(7 downto 0);
I_vga_clk: in std_logic := '0';
O_vga_vsync, O_vga_hsync, O_vga_r, O_vga_g, O_vga_b: out std_logic := '0'
);
end component;
constant I_clk_period : time := 10 ns;
signal I_clk : std_logic := '0';
signal vga_ack, vga_vsync, vga_hsync, vga_r, vga_g, vga_b: std_logic := '0';
signal vga_dat: std_logic_vector(7 downto 0);
begin
-- instantiate unit under test
uut: vga_wb8 port map(
ADR_I => X"00000000",
CLK_I => I_clk,
DAT_I => X"00",
STB_I => '0',
WE_I => '0',
ACK_O => vga_ack,
DAT_O => vga_dat,
I_vga_clk => I_clk,
O_vga_vsync => vga_vsync,
O_vga_hsync => vga_hsync,
O_vga_r => vga_r,
O_vga_g => vga_g,
O_vga_b => vga_b
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
wait for 10000 * I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
b62ba64aea3f17645a7b46e8d8da97e1
| 0.621566 | 2.451178 | false | false | false | false |
zephyrer/resim-simulating-partial-reconfiguration
|
examples/state_migration/edk/pcores/xps_math_v1_01_a/hdl/vhdl/user_logic.vhd
| 3 | 8,191 |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 2
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component math_core
-- lingkang: must declare a component, unless ISE won't synthesize a black box
port (
clk : in std_logic;
rst : in std_logic;
ain : in std_logic_vector(0 to C_SLV_DWIDTH-1);
bin : in std_logic_vector(0 to C_SLV_DWIDTH-1);
result : out std_logic_vector(0 to C_SLV_DWIDTH-1);
statistic : out std_logic_vector(0 to C_SLV_DWIDTH-1) -- lingkang
);
end component math_core;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 1);
signal slv_reg_read_sel : std_logic_vector(0 to 1);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal result : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal statistic : std_logic_vector(0 to C_SLV_DWIDTH-1); -- lingkang
begin
--USER logic implementation added here
math_core_i : math_core
port map (
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
ain => slv_reg0,
bin => slv_reg1,
result => result,
statistic => statistic -- lingkang
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 1);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 1);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_sel is
when "10" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "01" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, result, statistic ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= result;
when "01" => slv_ip2bus_data <= statistic; -- lingkang
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
bsd-3-clause
|
f2c8e4d94037acea5a87f3bf655558d0
| 0.482115 | 4.069051 | false | false | false | false |
johnmurrayvi/vhdl-projects
|
Hex2SSeg_Controller/Part2-Separate/Part2-A/Hex4Digs2SSeg.vhd
| 1 | 1,995 |
------------------------------------------------
-- Module Name: Hex4Digs2SSeg - behavioral --
------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Dig2SSeg_Package.all;
entity Hex4Digs2SSeg is
port (
clock : in std_logic; -- Input clock
incr : in std_logic_vector (3 downto 0); -- Increment digits
anodes : out std_logic_vector (3 downto 0); -- Anodes for display
cathodes : out std_logic_vector (7 downto 0) -- Cathodes for segments
);
end Hex4Digs2SSeg;
architecture behavioral of Hex4Digs2SSeg is
signal dsel : std_logic_vector (1 downto 0) := "00"; -- Display select
signal hx0, hx1, hx2, hx3 : std_logic_vector (3 downto 0) := "0000"; -- Hex digits
signal sg0, sg1, sg2, sg3 : std_logic_vector (7 downto 0) := "11111111"; -- Segments
begin
-- Get 4 Hex digits and assign their segments
dig0: HexD2SSeg port map (hx0, sg0);
dig1: HexD2SSeg port map (hx1, sg1);
dig2: HexD2SSeg port map (hx2, sg2);
dig3: HexD2SSeg port map (hx3, sg3);
hx0 <= hx0 + 1 when incr(0) = '1' else hx0;
hx1 <= hx1 + 1 when incr(1) = '1' else hx1;
hx2 <= hx2 + 1 when incr(2) = '1' else hx2;
hx3 <= hx3 + 1 when incr(3) = '1' else hx3;
process (clock) -- choose output display with dsel
begin
if (clock'event and clock = '1') then
case dsel is
when "00" =>
cathodes <= sg0;
anodes <= "0111";
when "01" =>
cathodes <= sg1;
anodes <= "1011";
when "10" =>
cathodes <= sg2;
anodes <= "1101";
when others =>
cathodes <= sg3;
anodes <= "1110";
end case;
dsel <= dsel - 1;
end if;
end process;
end behavioral;
|
gpl-3.0
|
b13ae3e421ab1dae308e4efa0e6e93ef
| 0.500752 | 3.694444 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Projeto/Projeto-MasterMind-final/Counter9.vhd
| 1 | 1,077 |
-- Projeto MasterMind
-- Diogo Daniel Soares Ferreira e Eduardo Reis Silva
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Counter9 is
port( clk : in std_logic;
reset : in std_logic;
up : in std_logic;
down : in std_logic;
count : out std_logic_vector(3 downto 0));
end Counter9;
-- Contador de um algarismo decimal com entrada de clock, reset, up e down
architecture Behavioral of Counter9 is
signal s_count : unsigned (3 downto 0);
begin
process(clk)
begin
if(rising_edge(clk)) then
if(not(s_count(0)='0') and not(s_count(0)='1')) then
s_count <= (others => '0');
elsif(reset='1') then
s_count <= (others => '0');
elsif (up = '1') then
if(s_count = "1001") then
s_count <= (others => '0');
else
s_count <= s_count + 1;
end if;
elsif(down = '1') then
if(s_count = "0000") then
s_count <= "1001";
else
s_count <= s_count - 1;
end if;
else
s_count <= s_count;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;
|
gpl-2.0
|
0d5333d36cde5d41e321fdd38d569df1
| 0.609099 | 2.726582 | false | false | false | false |
jpcofr/PDUAMaude
|
PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/ALU_BIT.vhd
| 1 | 1,603 |
-- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: ALU SLICE **
-- ** Creacion: Marzo 08 **
-- ** Por: MGH-CMUA-UNIANDES **
-- ***********************************************
-- Descripcion:
-- ALU Slice de 1 Bit
-- A B
-- __|_ __|_
-- \ \/ /
-- SELOP-->\ / -->Cout
-- Cin-->\____/
-- |
-- R
-- ***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_BIT is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
SELOP : in STD_LOGIC_VECTOR (2 downto 0);
Cout : out STD_LOGIC;
R : out STD_LOGIC);
end ALU_BIT;
architecture Behavioral of ALU_BIT is
Begin
Process (A,B,Cin,SELOP)
Begin
case SELOP is
when "000" => R <= B; -- R = B
Cout <= 'X';
when "001" => R <= not B; -- R = /B
Cout <= 'X';
when "010" => R <= A and B; -- R = AB
Cout <= 'X';
when "011" => R <= A or B; -- R = A or B
Cout <= 'X';
when "100" => R <= A xor B; -- R = A xor B
Cout <= 'X';
when "101" => -- R = A + B
R <= A xor B xor Cin;
Cout <= (A and B)or (Cin and (A or B));
when "110" => -- R = B + 1
R <= B xor Cin;
Cout <= B and Cin;
when "111" => -- R = /B + 1
R <= (not B) xor Cin;
Cout <= (not B) and Cin;
when others => R <= 'X';
Cout <= 'X';
end case;
end process;
end Behavioral;
|
mit
|
884187e99ca16b93d9e27d9baad98a68
| 0.389894 | 2.888288 | false | false | false | false |
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