repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
mitchsm/nvc
|
test/regress/arith1.vhd
| 3 | 778 |
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
assert 5 mod 3 = 2;
assert 5 rem 3 = 2;
assert (-5) rem 3 = -2;
assert (-5) mod 3 = 2;
assert x = +x;
wait;
end process;
end architecture;
|
gpl-3.0
|
bd051a1d8e4f6f888aa4d4679469ebdd
| 0.430591 | 3.536364 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/cdc_sync.vhd
| 1 | 25,113 |
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d6 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d7 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
s_out_d5 <= '0';
s_out_d6 <= '0';
s_out_d7 <= '0';
scndry_out <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
s_out_d5 <= s_out_d4;
s_out_d6 <= s_out_d5;
s_out_d7 <= s_out_d6;
scndry_out <= s_out_re;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= s_out_d2 xor s_out_d3;
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= s_out_d3 xor s_out_d4;
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= s_out_d4 xor s_out_d5;
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= s_out_d5 xor s_out_d6;
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= s_out_d6 xor s_out_d7;
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
s_level_out_d3 <= '0';
s_level_out_d4 <= '0';
s_level_out_d5 <= '0';
s_level_out_d6 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_int;
s_level_out_d2 <= s_level_out_d1_cdc_to;
s_level_out_d3 <= s_level_out_d2;
s_level_out_d4 <= s_level_out_d3;
s_level_out_d5 <= s_level_out_d4;
s_level_out_d6 <= s_level_out_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_bus_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_bus_d1_cdc_from <= (others => '0');
else
p_level_in_bus_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_bus_d1_cdc_to <= (others => '0');
s_level_out_bus_d2 <= (others => '0');
s_level_out_bus_d3 <= (others => '0');
s_level_out_bus_d4 <= (others => '0');
s_level_out_bus_d5 <= (others => '0');
s_level_out_bus_d6 <= (others => '0');
else
s_level_out_bus_d1_cdc_to <= p_level_in_bus_int;
s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
s_level_out_bus_d3 <= s_level_out_bus_d2;
s_level_out_bus_d4 <= s_level_out_bus_d3;
s_level_out_bus_d5 <= s_level_out_bus_d4;
s_level_out_bus_d6 <= s_level_out_bus_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d6 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d4 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d5 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' and C_RESET_STATE = 1)then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
s_level_out_d3 <= '0';
s_level_out_d4 <= '0';
s_level_out_d5 <= '0';
s_level_out_d6 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_int;
s_level_out_d2 <= s_level_out_d1_cdc_to;
s_level_out_d3 <= s_level_out_d2;
s_level_out_d4 <= s_level_out_d3;
s_level_out_d5 <= s_level_out_d4;
s_level_out_d6 <= s_level_out_d5;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' and C_RESET_STATE = 1)then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
p_level_out_d3 <= '0';
p_level_out_d4 <= '0';
p_level_out_d5 <= '0';
p_level_out_d6 <= '0';
p_level_out_d7 <= '0';
prmry_ack <= '0';
else
p_level_out_d1_cdc_to <= scndry_out_int;
p_level_out_d2 <= p_level_out_d1_cdc_to;
p_level_out_d3 <= p_level_out_d2;
p_level_out_d4 <= p_level_out_d3;
p_level_out_d5 <= p_level_out_d4;
p_level_out_d6 <= p_level_out_d5;
p_level_out_d7 <= p_level_out_d6;
prmry_ack <= prmry_pulse_ack;
end if;
end if;
end process CROSS_PLEVEL_SCNDRY2PRMRY;
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
|
mit
|
906b2e3666951e1c26a595cd9304620f
| 0.470155 | 3.681179 | false | false | false | false |
mitchsm/nvc
|
test/regress/issue104.vhd
| 5 | 590 |
ENTITY dummy IS PORT(
i : IN bit;
o : OUT bit );
END ENTITY dummy;
ARCHITECTURE arch OF dummy IS
BEGIN
o <= i;
END ARCHITECTURE arch;
ENTITY issue104 IS
END ENTITY issue104;
ARCHITECTURE arch OF issue104 IS
SIGNAL v : bit_vector(4 DOWNTO 0);
BEGIN
fold : FOR i IN 0 TO 3 GENERATE
BEGIN
dummy : ENTITY work.dummy PORT MAP(
i => v(i+1),
o => v(i)
);
END GENERATE fold;
process is
begin
v(4) <= '1';
wait for 1 ns;
assert v(0) = '1';
wait;
end process;
END ARCHITECTURE arch;
|
gpl-3.0
|
3b23ef57bfa2d206216ec72968543204
| 0.559322 | 3.597561 | false | false | false | false |
mitchsm/nvc
|
test/regress/proc6.vhd
| 5 | 573 |
entity proc6 is
end entity;
architecture test of proc6 is
procedure delay(signal x : out integer;
signal y : in integer;
constant d : in delay_length) is
begin
x <= y after d;
end procedure;
signal a, b : integer;
begin
foo: delay(a, b, 10 ns);
check: process is
begin
b <= 6;
wait for 11 ns;
assert a = 6;
b <= 7;
wait for 5 ns;
assert a = 6;
wait for 5 ns;
assert a = 7;
wait;
end process;
end architecture;
|
gpl-3.0
|
40233b33ede4216253c0ab4d2a57fad5
| 0.495637 | 3.897959 | false | false | false | false |
mitchsm/nvc
|
test/regress/func2.vhd
| 4 | 1,220 |
entity func2 is
end entity;
architecture rtl of func2 is
type int_array is array (integer range <>) of integer;
function len(x : int_array) return integer is
begin
return x'length;
end function;
function sum(x : int_array) return integer is
variable tmp : integer := 0;
begin
for i in x'range loop
tmp := tmp + x(i);
end loop;
return tmp;
end function;
function asc(x : int_array) return boolean is
begin
return x'ascending;
end function;
function get_low(x : int_array) return integer is
begin
return x'low;
end function;
function get_high(x : int_array) return integer is
begin
return x'high;
end function;
begin
process is
variable u : int_array(5 downto 1) := (6, 3, 1, 1, 2);
variable v : int_array(1 to 5) := (3, 5, 6, 1, 2);
begin
assert len(v) = 5;
assert sum(v) = 17;
assert sum(u) = 13;
assert asc(v);
assert get_low(u) = 1;
assert get_low(v) = 1;
assert get_high(u) = 5;
assert get_high(v) = 5;
assert not asc(u);
wait;
end process;
end architecture;
|
gpl-3.0
|
c05869dd185970ca256aee11793fea6f
| 0.554918 | 3.59882 | false | false | false | false |
mitchsm/nvc
|
test/regress/wait9.vhd
| 5 | 705 |
entity wait9 is
end entity;
architecture test of wait9 is
signal s : bit_vector(3 downto 0);
signal n : integer := 0;
begin
a: process is
variable cnt : integer := 0;
begin
wait on s(1), s(2);
cnt := cnt + 1;
n <= cnt;
end process;
b: process is
begin
s <= "0000";
wait for 1 ns;
s <= "1001";
wait for 1 ns;
s <= "0101";
wait for 1 ns;
s <= "0010";
wait for 1 ns;
s(1) <= '0';
s(2) <= '1';
wait for 1 ns;
s(2) <= '0';
wait for 1 ns;
report integer'image(n);
assert n = 4;
wait;
end process;
end architecture;
|
gpl-3.0
|
73ae1cf8aa952d6054612394de41c4d4
| 0.448227 | 3.507463 | false | false | false | false |
mitchsm/nvc
|
test/regress/operator4.vhd
| 5 | 480 |
entity operator4 is
end entity;
architecture test of operator4 is
type byte_vec is array (integer range <>) of bit_vector(7 downto 0);
begin
process is
variable v : byte_vec(1 to 3);
begin
v := ( X"01", X"02", X"03" );
assert v = ( X"01", X"02", X"03" );
assert v /= ( X"01", X"02", X"05" );
assert v /= ( X"01", X"02", X"03", X"04" );
assert v /= ( X"01", X"02" );
wait;
end process;
end architecture;
|
gpl-3.0
|
4dd4af895b6cedcc48e872c81202299e
| 0.5125 | 3.037975 | false | false | false | false |
blutsvente/MIX
|
test/results/autoopen/aaa/inst_t_e-rtl-a.vhd
| 1 | 3,928 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Thu Jul 6 07:18:32 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.2 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.2 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_s_aio17_gc : inout std_ulogic;
p_mix_s_ao11_go : out std_ulogic_vector(7 downto 0);
p_mix_s_ao3_go : out std_ulogic;
s_ai14 : in std_ulogic_vector(7 downto 0);
s_ai16 : out std_ulogic_vector(7 downto 0);
s_ai6 : in std_ulogic;
s_ai8 : out std_ulogic;
s_aio18 : inout std_ulogic;
s_aio19 : inout std_ulogic;
s_ao1 : out std_ulogic;
s_ao12 : out std_ulogic_vector(7 downto 0);
s_ao13 : out std_ulogic_vector(7 downto 0);
s_ao4 : out std_ulogic;
s_ao5 : out std_ulogic;
s_ao9 : in std_ulogic_vector(7 downto 0);
s_outname : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_e_e
-- No Generated Generics
-- Generated Generics for Entity inst_e_e
-- End of Generated Generics for Entity inst_e_e
port (
-- Generated Port for Entity inst_e_e
p_mix_s_eo3_go : out std_ulogic;
s_eo1 : out std_ulogic;
s_eo2 : out std_ulogic;
s_eo4 : out std_ulogic;
s_eo5 : out std_ulogic;
s_outname : in std_ulogic
-- End of Generated Port for Entity inst_e_e
);
end component;
-- ---------
--
-- Generated Signal List
--
-- __I_OUT_OPEN signal s_ao1 : std_ulogic;
-- __I_OUT_OPEN signal s_ao12 : std_ulogic_vector(7 downto 0);
-- __I_OUT_OPEN signal s_ao4 : std_ulogic;
-- __I_NODRV_I signal s_ao9 : std_ulogic_vector(7 downto 0);
-- __I_OUT_OPEN signal s_eo1 : std_ulogic;
-- __I_OUT_OPEN signal s_eo2 : std_ulogic;
-- __I_OUT_OPEN signal s_eo4 : std_ulogic;
signal s_outname : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: inst_a_e
port map (
p_mix_s_aio17_gc => s_aio17,
p_mix_s_ao11_go => s_ao11,
p_mix_s_ao3_go => s_ao3,
s_ai14 => s_ai14,
s_ai16 => s_ai16,
s_ai6 => s_ai6,
s_ai8 => s_ai8,
s_aio18 => s_aio18,
s_aio19 => s_aio19,
s_ao1 => open, -- __I_OUT_OPEN
s_ao12 => open, -- __I_OUT_OPEN
s_ao13 => s_ao13,
s_ao4 => open, -- __I_OUT_OPEN
s_ao5 => s_ao5,
-- __I_NODRV_I s_ao9 => __nodrv__/s_ao9,
s_outname => s_outname
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_e
inst_e: inst_e_e
port map (
p_mix_s_eo3_go => s_eo3,
s_eo1 => open, -- __I_OUT_OPEN
s_eo2 => open, -- __I_OUT_OPEN
s_eo4 => open, -- __I_OUT_OPEN
s_eo5 => s_eo5,
s_outname => s_outname
);
-- End of Generated Instance Port Map for inst_e
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
b4a5e0dd6e273fc7d65f6a9f141f5389
| 0.580703 | 2.585912 | false | false | false | false |
mitchsm/nvc
|
test/parse/seq.vhd
| 4 | 2,984 |
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
end process;
-- Blocking assignment
process is
variable a : integer;
begin
a := 2;
a := a + (a * 3);
end process;
-- Assert and report
process is
begin
assert true;
assert false severity note;
assert 1 > 2 report "oh no" severity failure;
report "hello";
report "boo" severity error;
end process;
-- Function calls
process is
begin
x := foo(1, 2, 3);
a := "abs"(b);
end process;
-- If
process is
begin
if true then
x := 1;
end if;
test: if true then
x := y;
end if test;
if x > 2 then
x := 5;
else
y := 2;
end if;
if x > 3 then
null;
elsif x > 5 then
null;
elsif true then
null;
else
x := 2;
end if;
end process;
-- Null
process is
begin
null;
end process;
-- Return
process is
begin
return 4 * 4;
end process;
-- While
process is
begin
while n > 0 loop
n := n - 1;
end loop;
loop
null;
end loop;
end process;
-- Delayed assignment
process is
begin
x <= 4 after 5 ns;
x <= 5 after 1 ns, 7 after 8 ns;
x <= 5, 7 after 8 ns;
x <= inertial 5;
x <= transport 4 after 2 ns;
x <= reject 4 ns inertial 6 after 10 ns;
end process;
-- For
process is
begin
for i in 0 to 10 loop
null;
end loop;
for i in foo'range loop
null;
end loop;
end process;
-- Exit
process is
begin
exit;
exit when x = 1;
end process;
-- Procedure call
process is
begin
foo(x, y, 1);
bar;
foo(a => 1, b => 2, 3);
end process;
-- Case
process is
begin
case x is
when 1 =>
null;
when 2 =>
null;
when 3 | 4 =>
null;
when others =>
null;
end case;
end process;
-- Next
process is
begin
next;
next when foo = 5;
end process;
-- Signal assignment to aggregate
process is
begin
( x, y, z ) <= foo;
end process;
-- Case statement range bug
process is
begin
case f is
when 1 =>
for i in x'range loop
end loop;
end case;
end process;
end architecture;
|
gpl-3.0
|
8a70bc7be653e7a59ca3d8990b03567b
| 0.437668 | 4.299712 | false | false | false | false |
mitchsm/nvc
|
test/regress/bitvec.vhd
| 3 | 679 |
entity bitvec is
end entity;
architecture test of bitvec is
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
begin
process is
variable b : bit_vector(3 downto 0);
begin
b := "1101";
assert not b = "0010";
assert (b and "1010") = "1000";
assert (b or "0110") = "1111";
assert (b xor "0111") = "1010";
assert (b xnor "0111") = "0101";
assert (b nand "1010") = "0111";
assert (b nor "0110") = "0000";
assert get_bitvec(1, 2) = "00";
wait;
end process;
end architecture;
|
gpl-3.0
|
2a8ea16e6b8e6ac6f629a36144b1da26
| 0.530191 | 3.5 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab5.vhd
| 5 | 749 |
entity sub is
port (
x : out integer );
end entity;
architecture one of sub is
begin
x <= 1;
end architecture;
architecture two of sub is
begin
x <= 2;
end architecture;
-------------------------------------------------------------------------------
entity elab5 is
end entity;
architecture test of elab5 is
signal x1, x2, x3 : integer;
begin
sub1: entity work.sub(one)
port map ( x1 );
sub2: entity work.sub(two)
port map ( x2 );
sub3: entity work.sub -- Should select `two'
port map ( x3 );
process is
begin
wait for 1 ns;
assert x1 = 1;
assert x2 = 2;
assert x3 = 2;
wait;
end process;
end architecture;
|
gpl-3.0
|
cd957d5d8929d98660d6d2dc609cefe0
| 0.497997 | 3.921466 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_input_scalars_fifo.vhd
| 1 | 57,851 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_input_scalars_fifo.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
entity xd_input_scalars_fifo is
generic (
C_FAMILY : string := "virtex6";
C_MTBF_STAGES : integer := 4;
WIDTH : integer := 16);
port (
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
wr_used : out std_logic_vector(3 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_clk : in std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic;
rd_clk : in std_logic;
rst : in std_logic);
end xd_input_scalars_fifo;
architecture rtl of xd_input_scalars_fifo is
constant DEPTH : integer := 16;
constant FIFO_DEPTH : integer := calc_fifo_depth(DEPTH)+ 1;
constant ADDR_BITS : integer := log2(FIFO_DEPTH);
signal rst_vec : std_logic_vector(0 downto 0);
signal wr_rst_vec : std_logic_vector(0 downto 0);
signal rd_rst_vec : std_logic_vector(0 downto 0);
signal wr_rst : std_logic;
signal rd_rst : std_logic;
signal rd_addr : unsigned(ADDR_BITS-1 downto 0);
signal wr_addr : unsigned(ADDR_BITS-1 downto 0);
-- Next signals are gray values:
signal wr_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_wr_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_gray_ahead : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal prev_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal din_rdy_i : std_logic;
signal empty_i : std_logic;
signal rd_en : std_logic;
signal dout_vld_i : std_logic;
signal empty : std_logic;
signal rd_en_dly : std_logic;
signal wr_en_dly : std_logic;
signal din_dly : std_logic_vector(WIDTH-1 downto 0);
signal full : std_logic;
signal rstn : std_logic;
signal almost_full :std_logic;
signal wr_ack :std_logic;
signal overflow :std_logic;
signal almost_empty :std_logic;
signal valid :std_logic;
signal underflow :std_logic;
signal data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal prog_full :std_logic;
signal prog_empty :std_logic;
signal sbiterr :std_logic;
signal dbiterr :std_logic;
signal wr_rst_busy :std_logic;
signal rd_rst_busy :std_logic;
signal m_axi_awid :std_logic_vector(0 downto 0);
signal m_axi_awaddr :std_logic_vector(31 downto 0);
signal m_axi_awlen :std_logic_vector(7 downto 0);
signal m_axi_awsize :std_logic_vector(2 downto 0);
signal m_axi_awburst :std_logic_vector(1 downto 0);
signal m_axi_awlock :std_logic_vector(0 downto 0);
signal m_axi_awcache :std_logic_vector(3 downto 0);
signal m_axi_awprot :std_logic_vector(2 downto 0);
signal m_axi_awqos :std_logic_vector(3 downto 0);
signal m_axi_awregion :std_logic_vector(3 downto 0);
signal m_axi_awuser :std_logic_vector(0 downto 0);
signal m_axi_awvalid :std_logic;
signal m_axi_wid :std_logic_vector(0 downto 0);
signal m_axi_wdata :std_logic_vector(63 downto 0);
signal m_axi_wstrb :std_logic_vector(7 downto 0);
signal m_axi_wlast :std_logic;
signal m_axi_wuser :std_logic_vector(0 downto 0);
signal m_axi_wvalid :std_logic;
signal m_axi_bready :std_logic;
signal s_axi_awready :std_logic;
signal s_axi_wready :std_logic;
signal s_axi_bid :std_logic_vector(0 downto 0);
signal s_axi_bresp :std_logic_vector(1 downto 0);
signal s_axi_buser :std_logic_vector(0 downto 0);
signal m_axi_arid :std_logic_vector(0 downto 0);
signal m_axi_araddr :std_logic_vector(31 downto 0);
signal m_axi_arlen :std_logic_vector(7 downto 0);
signal m_axi_arsize :std_logic_vector(2 downto 0);
signal m_axi_arburst :std_logic_vector(1 downto 0);
signal m_axi_arlock :std_logic_vector(0 downto 0);
signal m_axi_arcache :std_logic_vector(3 downto 0);
signal m_axi_arprot :std_logic_vector(2 downto 0);
signal m_axi_arqos :std_logic_vector(3 downto 0);
signal m_axi_arregion :std_logic_vector(3 downto 0);
signal m_axi_aruser :std_logic_vector(0 downto 0);
signal m_axi_arvalid :std_logic;
signal m_axi_rready :std_logic;
signal s_axi_arready :std_logic;
signal s_axi_rid :std_logic_vector(0 downto 0);
signal s_axi_rdata :std_logic_vector(63 downto 0);
signal s_axi_rresp :std_logic_vector(1 downto 0);
signal s_axi_rlast :std_logic;
signal s_axi_ruser :std_logic_vector(0 downto 0);
signal m_axis_tvalid :std_logic;
signal m_axis_tdata :std_logic_vector(7 downto 0);
signal m_axis_tstrb :std_logic_vector(0 downto 0);
signal m_axis_tlast :std_logic;
signal m_axis_tkeep :std_logic_vector(0 downto 0);
signal m_axis_tid :std_logic_vector(0 downto 0);
signal m_axis_tdest :std_logic_vector(0 downto 0);
signal m_axis_tuser :std_logic_vector(3 downto 0);
signal s_axis_tready :std_logic;
signal axi_aw_data_count :std_logic_vector(4 downto 0);
signal axi_aw_wr_data_count :std_logic_vector(4 downto 0);
signal axi_aw_rd_data_count :std_logic_vector(4 downto 0);
signal axi_aw_sbiterr :std_logic;
signal axi_aw_dbiterr :std_logic;
signal axi_aw_overflow :std_logic;
signal axi_aw_underflow :std_logic;
signal axi_aw_prog_full :std_logic;
signal axi_aw_prog_empty :std_logic;
signal axi_w_data_count :std_logic_vector(10 downto 0);
signal axi_w_wr_data_count :std_logic_vector(10 downto 0);
signal axi_w_rd_data_count :std_logic_vector(10 downto 0);
signal axi_w_sbiterr :std_logic;
signal axi_w_dbiterr :std_logic;
signal axi_w_overflow :std_logic;
signal axi_w_underflow :std_logic;
signal axi_w_prog_full :std_logic;
signal axi_w_prog_empty :std_logic;
signal axi_b_data_count :std_logic_vector(4 downto 0);
signal axi_b_wr_data_count :std_logic_vector(4 downto 0);
signal axi_b_rd_data_count :std_logic_vector(4 downto 0);
signal axi_b_sbiterr :std_logic;
signal axi_b_dbiterr :std_logic;
signal axi_b_overflow :std_logic;
signal axi_b_underflow :std_logic;
signal axi_b_prog_full :std_logic;
signal axi_b_prog_empty :std_logic;
signal axi_ar_data_count :std_logic_vector(4 downto 0);
signal axi_ar_wr_data_count :std_logic_vector(4 downto 0);
signal axi_ar_rd_data_count :std_logic_vector(4 downto 0);
signal axi_ar_sbiterr :std_logic;
signal axi_ar_dbiterr :std_logic;
signal axi_ar_overflow :std_logic;
signal axi_ar_underflow :std_logic;
signal axi_ar_prog_full :std_logic;
signal axi_ar_prog_empty :std_logic;
signal axi_r_data_count :std_logic_vector(10 downto 0);
signal axi_r_wr_data_count :std_logic_vector(10 downto 0);
signal axi_r_rd_data_count :std_logic_vector(10 downto 0);
signal axi_r_sbiterr :std_logic;
signal axi_r_dbiterr :std_logic;
signal axi_r_overflow :std_logic;
signal axi_r_underflow :std_logic;
signal axi_r_prog_full :std_logic;
signal axi_r_prog_empty :std_logic;
signal axis_data_count :std_logic_vector(10 downto 0);
signal axis_wr_data_count :std_logic_vector(10 downto 0);
signal axis_rd_data_count :std_logic_vector(10 downto 0);
signal axis_sbiterr :std_logic;
signal axis_dbiterr :std_logic;
signal axis_overflow :std_logic;
signal axis_underflow :std_logic;
signal axis_prog_full :std_logic;
signal axis_prog_empty :std_logic;
type mem_type is array (2**ADDR_BITS-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal mem : mem_type;
attribute ram_style : string;
attribute ram_style of mem : signal is "distributed";
signal mem_dout : std_logic_vector(WIDTH-1 downto 0);
-- Read gray counter synchronized with write clock.
signal reg_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_gray_sync : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_bin : unsigned(ADDR_BITS-1 downto 0);
signal wr_bin : unsigned(ADDR_BITS-1 downto 0);
signal ptr_dist : unsigned(ADDR_BITS-1 downto 0);
signal wr_used_i : std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_empty_i : std_logic;
constant C_EXTRA_SYNCS : integer := 5;
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, rst)
begin
if(rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rst)
begin
if(rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
process(rd_clk, rst)
begin
if(rst = '1') then
next_rd_gray <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
rd_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
prev_rd_gray <= bin2gray(2**ADDR_BITS-3, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_gray <= rd_gray;
rd_gray <= next_rd_gray;
next_rd_gray <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
next_wr_gray <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
wr_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray <= next_wr_gray;
next_wr_gray <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
wr_gray_ahead <= bin2gray(2**ADDR_BITS-0, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
end if;
end if;
end process;
-----------------------------------------------------------------
process(wr_clk, rst)
begin
if(rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if(din_rdy_i = '1') then
if (wr_gray_ahead = prev_rd_gray) then
din_rdy_i <= not(fifo_we);
else
din_rdy_i <= '1';
end if;
else
if (wr_gray_ahead = rd_gray) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
process(rd_clk, rst)
begin
if(rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if(empty_i = '0') then
if(next_rd_gray = wr_gray) then
empty_i <= fifo_re;
else
empty_i <= '0';
end if;
else
if(rd_gray = wr_gray) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rst)
begin
if(rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
-----------------------------------------------------------------------
-- Memory bank modeling. Tool to infer the memory.
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rst)
begin
if(rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
-----------------------------------------------------------------------
process(rd_clk, rst)
begin
if(rst = '1') then
reg_rd_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
reg_rd_gray <= rd_gray;
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
rd_gray_sync <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
rd_gray_sync <= reg_rd_gray;
end if;
end process;
rd_bin <= unsigned(gray2bin(rd_gray_sync));
process(wr_clk, rst)
begin
if(rst = '1') then
wr_bin <= to_unsigned(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if (fifo_we = '1') then
wr_bin <= wr_bin + 1;
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
ptr_dist <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if (fifo_we = '1') then
ptr_dist <= ptr_dist + 1;
else
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
wr_used <= std_logic_vector(ptr_dist);
wr_full <= not(din_rdy_i);
process(wr_clk, rst)
begin
if(rst = '1') then
wr_empty_i <= '1';
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_empty_i <= '0';
else
if(rd_gray_sync = wr_gray) then
wr_empty_i <= '1';
else
wr_empty_i <= '0';
end if;
end if;
end if;
end process;
wr_empty <= wr_empty_i;
end generate EXISTING;
NEW_INTRO : if (C_EXTRA_SYNCS = 2) generate
begin
rst_vec(0) <= rst;
wr_rst <= wr_rst_vec(0);
rd_rst <= rd_rst_vec(0);
wr_rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 0,
C_WIDTH => 1
)
PORT MAP (
RST => open,
CLK => wr_clk,
D => rst_vec,
Q => wr_rst_vec
);
rd_rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 0,
C_WIDTH => 1
)
PORT MAP (
RST => open,
CLK => rd_clk,
D => rst_vec,
Q => rd_rst_vec
);
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
next_rd_gray <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
rd_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
prev_rd_gray <= bin2gray(2**ADDR_BITS-3, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_gray <= rd_gray;
rd_gray <= next_rd_gray;
next_rd_gray <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
next_wr_gray <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
wr_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray <= next_wr_gray;
next_wr_gray <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_gray_ahead <= bin2gray(2**ADDR_BITS-0, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
end if;
end if;
end process;
-----------------------------------------------------------------
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if(din_rdy_i = '1') then
if (wr_gray_ahead = prev_rd_gray) then
din_rdy_i <= not(fifo_we);
else
din_rdy_i <= '1';
end if;
else
if (wr_gray_ahead = rd_gray) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if(empty_i = '0') then
if(next_rd_gray = wr_gray) then
empty_i <= fifo_re;
else
empty_i <= '0';
end if;
else
if(rd_gray = wr_gray) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
-----------------------------------------------------------------------
-- Memory bank modeling. Tool to infer the memory.
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
-----------------------------------------------------------------------
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
reg_rd_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
reg_rd_gray <= rd_gray;
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
rd_gray_sync <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
rd_gray_sync <= reg_rd_gray;
end if;
end process;
rd_bin <= unsigned(gray2bin(rd_gray_sync));
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_bin <= to_unsigned(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if (fifo_we = '1') then
wr_bin <= wr_bin + 1;
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
ptr_dist <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if (fifo_we = '1') then
ptr_dist <= ptr_dist + 1;
else
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
wr_used <= std_logic_vector(ptr_dist(3 downto 0));
wr_full <= not(din_rdy_i);
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_empty_i <= '1';
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_empty_i <= '0';
else
if(rd_gray_sync = wr_gray) then
wr_empty_i <= '1';
else
wr_empty_i <= '0';
end if;
end if;
end if;
end process;
wr_empty <= wr_empty_i;
end generate NEW_INTRO;
NEW_INTRO3 : if (C_EXTRA_SYNCS = 5) generate
begin
rstn <= not(rst);
din_rdy <= not(full);
din_rdy_i <= not(full);
wr_full <= (full);
wr_empty <= (empty);
dout_vld <= not(empty);
wr_en_dly <= din_vld ;--AFTER 100ps;
rd_en_dly <= dout_rdy ;--AFTER 100ps;
din_dly <= din ;--AFTER 100ps;
wr_used <= wr_used_i(3 downto 0);
FIF_DMG_INST : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => WIDTH,
C_ENABLE_RLOCS => 0,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 1,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 29,
C_PROG_FULL_THRESH_NEGATE_VAL => 28,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADDR_BITS,
C_RD_DEPTH => FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADDR_BITS,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => ADDR_BITS,
C_WR_DEPTH => FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADDR_BITS,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 3,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din_dly,
wr_en => wr_en_dly,
rd_en => rd_en_dly,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
valid => valid,
underflow => underflow,
data_count => data_count,
rd_data_count => rd_data_count,
wr_data_count => wr_used_i,
prog_full => prog_full,
prog_empty => prog_empty,
sbiterr => sbiterr,
dbiterr => dbiterr,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awuser => m_axi_awuser,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => '0',
m_axi_wid => m_axi_wid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wuser => m_axi_wuser,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
m_axi_bready => m_axi_bready,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_awready => s_axi_awready,
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bready => '0',
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_aruser => m_axi_aruser,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
m_axi_rready => m_axi_rready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rready => '0',
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => '0',
m_axis_tdata => m_axis_tdata ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tkeep => m_axis_tkeep ,
m_axis_tlast => m_axis_tlast ,
m_axis_tid => m_axis_tid ,
m_axis_tdest => m_axis_tdest ,
m_axis_tuser => m_axis_tuser ,
s_axis_tvalid => '0',
s_axis_tready => s_axis_tready,
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_data_count => axi_aw_data_count,
axi_aw_wr_data_count => axi_aw_wr_data_count,
axi_aw_rd_data_count => axi_aw_rd_data_count,
axi_aw_sbiterr => axi_aw_sbiterr,
axi_aw_dbiterr => axi_aw_dbiterr,
axi_aw_overflow => axi_aw_overflow,
axi_aw_underflow => axi_aw_underflow,
axi_aw_prog_full => axi_aw_prog_full,
axi_aw_prog_empty => axi_aw_prog_empty,
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_data_count => axi_w_data_count,
axi_w_wr_data_count => axi_w_wr_data_count,
axi_w_rd_data_count => axi_w_rd_data_count,
axi_w_sbiterr => axi_w_sbiterr,
axi_w_dbiterr => axi_w_dbiterr,
axi_w_overflow => axi_w_overflow,
axi_w_underflow => axi_w_underflow,
axi_w_prog_full => axi_w_prog_full,
axi_w_prog_empty => axi_w_prog_empty,
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_data_count => axi_b_data_count,
axi_b_wr_data_count => axi_b_wr_data_count,
axi_b_rd_data_count => axi_b_rd_data_count,
axi_b_sbiterr => axi_b_sbiterr,
axi_b_dbiterr => axi_b_dbiterr,
axi_b_overflow => axi_b_overflow,
axi_b_underflow => axi_b_underflow,
axi_b_prog_full => axi_b_prog_full,
axi_b_prog_empty => axi_b_prog_empty,
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_data_count => axi_ar_data_count,
axi_ar_wr_data_count => axi_ar_wr_data_count,
axi_ar_rd_data_count => axi_ar_rd_data_count,
axi_ar_sbiterr => axi_ar_sbiterr,
axi_ar_dbiterr => axi_ar_dbiterr,
axi_ar_overflow => axi_ar_overflow,
axi_ar_underflow => axi_ar_underflow,
axi_ar_prog_full => axi_ar_prog_full,
axi_ar_prog_empty => axi_ar_prog_empty,
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_data_count => axi_r_data_count,
axi_r_wr_data_count => axi_r_wr_data_count,
axi_r_rd_data_count => axi_r_rd_data_count,
axi_r_sbiterr => axi_r_sbiterr,
axi_r_dbiterr => axi_r_dbiterr,
axi_r_overflow => axi_r_overflow,
axi_r_underflow => axi_r_underflow,
axi_r_prog_full => axi_r_prog_full,
axi_r_prog_empty => axi_r_prog_empty,
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count,
axis_wr_data_count => axis_wr_data_count,
axis_rd_data_count => axis_rd_data_count,
axis_sbiterr => axis_sbiterr,
axis_dbiterr => axis_dbiterr,
axis_overflow => axis_overflow,
axis_underflow => axis_underflow,
axis_prog_full => axis_prog_full,
axis_prog_empty => axis_prog_empty
);
-- COMP_FIFO : entity fifo_generator_v12_0_5.fifo_generator_v12_0_5
-- generic map (
-- C_COMMON_CLOCK => 0,
-- C_COUNT_TYPE => 0,
-- C_DATA_COUNT_WIDTH => 10,
-- C_DEFAULT_VALUE => "BlankString",
-- C_DIN_WIDTH => 18,
-- C_DOUT_RST_VAL => "0",
-- C_DOUT_WIDTH => 18,
-- C_ENABLE_RLOCS => 0,
-- C_FAMILY => C_FAMILY,
-- C_FULL_FLAGS_RST_VAL => 1,
-- C_HAS_ALMOST_EMPTY => 0,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_BACKUP => 0,
-- C_HAS_DATA_COUNT => 0,
-- C_HAS_INT_CLK => 0,
-- C_HAS_MEMINIT_FILE => 0,
-- C_HAS_OVERFLOW => 0,
-- C_HAS_RD_DATA_COUNT => 0,
-- C_HAS_RD_RST => 0,
-- C_HAS_RST => 1,
-- C_HAS_SRST => 0,
-- C_HAS_UNDERFLOW => 0,
-- C_HAS_VALID => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_DATA_COUNT => 0,
-- C_HAS_WR_RST => 0,
-- C_IMPLEMENTATION_TYPE => 0,
-- C_INIT_WR_PNTR_VAL => 0,
-- C_MEMORY_TYPE => 1,
-- C_MIF_FILE_NAME => "BlankString",
-- C_OPTIMIZATION_MODE => 0,
-- C_OVERFLOW_LOW => 0,
-- C_PRELOAD_LATENCY => 1,
-- C_PRELOAD_REGS => 0,
-- C_PRIM_FIFO_TYPE => "4kx4",
-- C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
-- C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
-- C_PROG_EMPTY_TYPE => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
-- C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
-- C_PROG_FULL_TYPE => 0,
-- C_RD_DATA_COUNT_WIDTH => 10,
-- C_RD_DEPTH => 16,
-- C_RD_FREQ => 1,
-- C_RD_PNTR_WIDTH => ADDR_BITS,
-- C_UNDERFLOW_LOW => 0,
-- C_USE_DOUT_RST => 1,
-- C_USE_ECC => 0,
-- C_USE_EMBEDDED_REG => 0,
-- C_USE_PIPELINE_REG => 0,
-- C_POWER_SAVING_MODE => 0,
-- C_USE_FIFO16_FLAGS => 0,
-- C_USE_FWFT_DATA_COUNT => 0,
-- C_VALID_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_DATA_COUNT_WIDTH => 10,
-- C_WR_DEPTH => 16,
-- C_WR_FREQ => 1,
-- C_WR_PNTR_WIDTH => ADDR_BITS,
-- C_WR_RESPONSE_LATENCY => 1,
-- C_MSGON_VAL => 1,
-- C_ENABLE_RST_SYNC => 1,
-- C_ERROR_INJECTION_TYPE => 0,
-- C_SYNCHRONIZER_STAGE => 2,
-- C_INTERFACE_TYPE => 1,
-- C_AXI_TYPE => 1,
-- C_HAS_AXI_WR_CHANNEL => 1,
-- C_HAS_AXI_RD_CHANNEL => 1,
-- C_HAS_SLAVE_CE => 0,
-- C_HAS_MASTER_CE => 0,
-- C_ADD_NGC_CONSTRAINT => 0,
-- C_USE_COMMON_OVERFLOW => 0,
-- C_USE_COMMON_UNDERFLOW => 0,
-- C_USE_DEFAULT_SETTINGS => 0,
-- C_AXI_ID_WIDTH => 1,
-- C_AXI_ADDR_WIDTH => 32,
-- C_AXI_DATA_WIDTH => 64,
-- C_AXI_LEN_WIDTH => 8,
-- C_AXI_LOCK_WIDTH => 1,
-- C_HAS_AXI_ID => 0,
-- C_HAS_AXI_AWUSER => 0,
-- C_HAS_AXI_WUSER => 0,
-- C_HAS_AXI_BUSER => 0,
-- C_HAS_AXI_ARUSER => 0,
-- C_HAS_AXI_RUSER => 0,
-- C_AXI_ARUSER_WIDTH => 1,
-- C_AXI_AWUSER_WIDTH => 1,
-- C_AXI_WUSER_WIDTH => 1,
-- C_AXI_BUSER_WIDTH => 1,
-- C_AXI_RUSER_WIDTH => 1,
-- C_HAS_AXIS_TDATA => 0,
-- C_HAS_AXIS_TID => 0,
-- C_HAS_AXIS_TDEST => 0,
-- C_HAS_AXIS_TUSER => 0,
-- C_HAS_AXIS_TREADY => 1,
-- C_HAS_AXIS_TLAST => 1,
-- C_HAS_AXIS_TSTRB => 0,
-- C_HAS_AXIS_TKEEP => 0,
-- C_AXIS_TDATA_WIDTH => 1,
-- C_AXIS_TID_WIDTH => 1,
-- C_AXIS_TDEST_WIDTH => 1,
-- C_AXIS_TUSER_WIDTH => 1,
-- C_AXIS_TSTRB_WIDTH => 1,
-- C_AXIS_TKEEP_WIDTH => 1,
-- C_WACH_TYPE => 0,
-- C_WDCH_TYPE => 0,
-- C_WRCH_TYPE => 0,
-- C_RACH_TYPE => 0,
-- C_RDCH_TYPE => 0,
-- C_AXIS_TYPE => 0,
-- C_IMPLEMENTATION_TYPE_WACH => 12,
-- C_IMPLEMENTATION_TYPE_WDCH => 11,
-- C_IMPLEMENTATION_TYPE_WRCH => 12,
-- C_IMPLEMENTATION_TYPE_RACH => 12,
-- C_IMPLEMENTATION_TYPE_RDCH => 11,
-- C_IMPLEMENTATION_TYPE_AXIS => 11,
-- C_APPLICATION_TYPE_WACH => 0,
-- C_APPLICATION_TYPE_WDCH => 0,
-- C_APPLICATION_TYPE_WRCH => 0,
-- C_APPLICATION_TYPE_RACH => 0,
-- C_APPLICATION_TYPE_RDCH => 0,
-- C_APPLICATION_TYPE_AXIS => 1,
-- C_PRIM_FIFO_TYPE_WACH => "512x36",
-- C_PRIM_FIFO_TYPE_WDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_WRCH => "512x36",
-- C_PRIM_FIFO_TYPE_RACH => "512x36",
-- C_PRIM_FIFO_TYPE_RDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_AXIS => "512x36",
-- C_USE_ECC_WACH => 0,
-- C_USE_ECC_WDCH => 0,
-- C_USE_ECC_WRCH => 0,
-- C_USE_ECC_RACH => 0,
-- C_USE_ECC_RDCH => 0,
-- C_USE_ECC_AXIS => 0,
-- C_ERROR_INJECTION_TYPE_WACH => 0,
-- C_ERROR_INJECTION_TYPE_WDCH => 0,
-- C_ERROR_INJECTION_TYPE_WRCH => 0,
-- C_ERROR_INJECTION_TYPE_RACH => 0,
-- C_ERROR_INJECTION_TYPE_RDCH => 0,
-- C_ERROR_INJECTION_TYPE_AXIS => 0,
-- C_DIN_WIDTH_WACH => 32,
-- C_DIN_WIDTH_WDCH => 64,
-- C_DIN_WIDTH_WRCH => 2,
-- C_DIN_WIDTH_RACH => 32,
-- C_DIN_WIDTH_RDCH => 64,
-- C_DIN_WIDTH_AXIS => 1,
-- C_WR_DEPTH_WACH => 16,
-- C_WR_DEPTH_WDCH => 1024,
-- C_WR_DEPTH_WRCH => 16,
-- C_WR_DEPTH_RACH => 16,
-- C_WR_DEPTH_RDCH => 1024,
-- C_WR_DEPTH_AXIS => 16,
-- C_WR_PNTR_WIDTH_WACH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_WDCH => 10,
-- C_WR_PNTR_WIDTH_WRCH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_RACH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_RDCH => 10,
-- C_WR_PNTR_WIDTH_AXIS => ADDR_BITS,
-- C_HAS_DATA_COUNTS_WACH => 0,
-- C_HAS_DATA_COUNTS_WDCH => 0,
-- C_HAS_DATA_COUNTS_WRCH => 0,
-- C_HAS_DATA_COUNTS_RACH => 0,
-- C_HAS_DATA_COUNTS_RDCH => 0,
-- C_HAS_DATA_COUNTS_AXIS => 3,
-- C_HAS_PROG_FLAGS_WACH => 0,
-- C_HAS_PROG_FLAGS_WDCH => 0,
-- C_HAS_PROG_FLAGS_WRCH => 0,
-- C_HAS_PROG_FLAGS_RACH => 0,
-- C_HAS_PROG_FLAGS_RDCH => 0,
-- C_HAS_PROG_FLAGS_AXIS => 0,
-- C_PROG_FULL_TYPE_WACH => 0,
-- C_PROG_FULL_TYPE_WDCH => 0,
-- C_PROG_FULL_TYPE_WRCH => 0,
-- C_PROG_FULL_TYPE_RACH => 0,
-- C_PROG_FULL_TYPE_RDCH => 0,
-- C_PROG_FULL_TYPE_AXIS => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 15,
-- C_PROG_EMPTY_TYPE_WACH => 0,
-- C_PROG_EMPTY_TYPE_WDCH => 0,
-- C_PROG_EMPTY_TYPE_WRCH => 0,
-- C_PROG_EMPTY_TYPE_RACH => 0,
-- C_PROG_EMPTY_TYPE_RDCH => 0,
-- C_PROG_EMPTY_TYPE_AXIS => 0,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1021,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1021,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 13,
-- C_REG_SLICE_MODE_WACH => 0,
-- C_REG_SLICE_MODE_WDCH => 0,
-- C_REG_SLICE_MODE_WRCH => 0,
-- C_REG_SLICE_MODE_RACH => 0,
-- C_REG_SLICE_MODE_RDCH => 0,
-- C_REG_SLICE_MODE_AXIS => 0
-- )
-- PORT MAP (
-- backup => '0',
-- backup_marker => '0',
-- clk => '0',
-- rst => '0',
-- srst => '0',
-- wr_clk => '0',
-- wr_rst => '0',
-- rd_clk => '0',
-- rd_rst => '0',
-- din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
-- wr_en => '0',
-- rd_en => '0',
-- prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- int_clk => '0',
-- injectdbiterr => '0',
-- injectsbiterr => '0',
-- sleep => '0',
-- m_aclk => rd_clk,
-- s_aclk => wr_clk,
-- s_aresetn => rstn,
-- m_aclk_en => '0',
-- s_aclk_en => '0',
-- s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awvalid => '0',
-- s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_wlast => '0',
-- s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wvalid => '0',
-- s_axi_bready => '0',
-- m_axi_awready => '0',
-- m_axi_wready => '0',
-- m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bvalid => '0',
-- s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arvalid => '0',
-- s_axi_rready => '0',
-- m_axi_arready => '0',
-- m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_rlast => '0',
-- m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rvalid => '0',
-- s_axis_tvalid => din_vld,
-- s_axis_tready => open,
-- s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tlast => din_rdy_i,
-- s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axis_tvalid => dout_vld_i,
-- m_axis_tready => m_axis_tready,
-- m_axis_tlast => m_axis_tlast,
-- axi_aw_injectsbiterr => '0',
-- axi_aw_injectdbiterr => '0',
-- axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_w_injectsbiterr => '0',
-- axi_w_injectdbiterr => '0',
-- axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_b_injectsbiterr => '0',
-- axi_b_injectdbiterr => '0',
-- axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- axi_ar_injectsbiterr => '0',
-- axi_ar_injectdbiterr => '0',
-- axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_r_injectsbiterr => '0',
-- axi_r_injectdbiterr => '0',
-- axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axis_injectsbiterr => '0',
-- axis_injectdbiterr => '0',
-- axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axis_wr_data_count => wr_used_i,
-- axis_rd_data_count => open
-- );
end generate NEW_INTRO3;
end rtl;
|
mit
|
62018d4bb37ac2b82c7585dd7647f458
| 0.504745 | 3.174092 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_add_sub1.vhd
| 1 | 4,698 |
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_ADD_SUB
-- ============================================================
-- File Name: lpm_add_sub1.vhd
-- Megafunction Name(s):
-- LPM_ADD_SUB
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_add_sub1;
ARCHITECTURE SYN OF lpm_add_sub1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(7 DOWNTO 0);
LPM_ADD_SUB_component : LPM_ADD_SUB
GENERIC MAP (
lpm_direction => "SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_representation => "SIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "3"
-- Retrieval info: PRIVATE: Function NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "1"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
296f61ab9f631be3ed4bb268ccf1999b
| 0.656875 | 3.613846 | false | false | false | false |
mitchsm/nvc
|
test/regress/ram1.vhd
| 5 | 2,321 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
generic (
WIDTH : integer );
port (
clk : in std_logic;
addr : in unsigned(7 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic );
end entity;
architecture rtl of memory is
type ram_t is array (0 to 255) of std_logic_vector(WIDTH - 1 downto 0);
signal addr_r : unsigned(7 downto 0);
signal ram : ram_t;
begin
reg: process (clk) is
begin
if rising_edge(clk) then
addr_r <= addr;
if we = '1' then
ram(to_integer(addr)) <= din;
end if;
end if;
end process;
dout <= ram(to_integer(addr_r));
end architecture;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram1 is
end entity;
architecture test of ram1 is
constant ITERS : integer := 1;
constant WIDTH : integer := 8;
signal clk : std_logic := '0';
signal addr : unsigned(7 downto 0);
signal din : std_logic_vector(WIDTH - 1 downto 0);
signal dout : std_logic_vector(WIDTH - 1 downto 0);
signal we : std_logic := '1';
signal running : boolean := true;
begin
clk <= not clk after 5 ns when running else '0';
uut: entity work.memory
generic map (
WIDTH => WIDTH )
port map (
clk => clk,
addr => addr,
din => din,
dout => dout,
we => we );
stim: process is
begin
for j in 1 to ITERS loop
wait for 20 ns;
we <= '1';
for i in 0 to 255 loop
addr <= to_unsigned(i, 8);
din <= std_logic_vector(to_unsigned((i + j) mod 256, WIDTH));
wait for 10 ns;
end loop;
we <= '0';
for i in 0 to 255 loop
addr <= to_unsigned(i, 8);
wait for 10 ns;
assert dout = std_logic_vector(to_unsigned((i + j) mod 256, WIDTH));
end loop;
end loop;
running <= false;
wait;
end process;
end architecture;
|
gpl-3.0
|
131839fc3d76ca7e395911835c88dd4f
| 0.50237 | 3.874791 | false | false | false | false |
mitchsm/nvc
|
test/regress/delay2.vhd
| 5 | 846 |
entity delay2 is
end entity;
architecture test of delay2 is
signal clk : bit;
begin
clock_p: process is
begin
if now < 1 us then
clk <= '1' after 5 ns, '0' after 10 ns;
wait for 10 ns;
else
wait;
end if;
end process;
check_p: process is
variable now_ns : integer;
begin
if now < 1 us then
wait for 0 ns;
now_ns := integer(now / ns);
case now_ns mod 10 is
when 0 =>
assert clk = '0';
when 5 =>
assert clk = '1';
when others =>
report "clk changed at unexpected time";
end case;
wait for 5 ns;
else
wait;
end if;
end process;
end architecture;
|
gpl-3.0
|
12c3876a1199154c171ecb89429f2ba4
| 0.444444 | 4.47619 | false | false | false | false |
DacHt/CU_Droptest
|
component/Actel/DirectCore/COREUART/5.6.102/rtl/vhdl/test/common/textio.vhd
| 1 | 23,329 |
-- ********************************************************************/
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: PRINTF SUPPORT for cores using std_logic_arith or std_logic_unsigned
--
--
-- Revision Information:
-- Date Description
-- 01Sep07 Initial Release
-- 14Sep07 Updated for 1.2 functionality
-- 25Sep07 Updated for 1.3 functionality
-- 09Nov07 Updated for 1.4 functionality
-- 08May08 2.0 for Soft IP Usage
-- 22Oct08 3.0 Moved into SVN Properly (TEXTIO Project)
--
--
-- SVN Revision Information:
-- SVN $Revision: 3758 $
-- SVN $Date: 2008-10-22 01:56:45 -0700 (Wed, 22 Oct 2008) $
--
--
-- Resolved SARs
-- SAR Date Who Description
--
--
-- Notes:
--
-- *********************************************************************/
-- Notes :
-- Supported Formats
-- %d decimal
-- %h hexadecimal Integer or known vector
-- %x hexadecimal Integer or vector with X's
-- %b binary
-- %s string
-- %t prints time in ns
--
-- Also Supports %6 i.e Width Field
-- %0 Fill with Zeros
--
---------------------------------------------------------------------------
library std;
use std.textio.all;
use work.misc.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------
-- Declarations etc
--
package textio is
-- synthesis translate_off
constant MAXSTRLEN : INTEGER := 256;
type T_NUMTYPE is ( NONE, INT, VECT, STRG);
type T_FMT is record
f_type : T_NUMTYPE;
f_integer : INTEGER;
f_vector : QWORD;
f_length : INTEGER;
f_string : STRING (1 to MAXSTRLEN);
end record;
type T_FMT_ARRAY is array ( integer range <> ) of T_FMT;
function is01 ( v: std_logic) return BOOLEAN;
function is01 ( v: STD_LOGIC_VECTOR; len : INTEGER) return BOOLEAN;
function strlen( str: STRING) return INTEGER;
function strcopy ( instr : STRING) return STRING;
procedure printf( str : STRING; params : T_FMT_ARRAY);
procedure printf( str : STRING; params : T_FMT);
procedure printf( str : STRING );
procedure sprintf( strout : out STRING; str : STRING; params : T_FMT_ARRAY);
procedure sprintf( strout : out STRING; str : STRING; params : T_FMT);
procedure sprintf( strout : out STRING; str : STRING );
procedure ifprintf( enable : BOOLEAN; str : STRING; params : T_FMT_ARRAY);
procedure ifprintf( enable : BOOLEAN; str : STRING; params : T_FMT);
procedure ifprintf( enable : BOOLEAN; str : STRING );
function fmt ( x : INTEGER) return T_FMT;
function fmt ( x : STD_LOGIC_VECTOR) return T_FMT;
function fmt ( x : string ) return T_FMT;
function fmt ( x : character ) return T_FMT;
function fmt ( x : boolean ) return T_FMT;
function fmt ( x : std_logic) return T_FMT;
function inttostr( value : INTEGER; base : INTEGER;
numlen : INTEGER :=0; zeros: BOOLEAN:=FALSE) return STRING;
function inrange ( x, l: integer) return integer;
-- synthesis translate_on
end textio;
-- synthesis translate_off
---------------------------------------------------------------------------
-- The Body
--
package body textio is
function inrange ( x, l: integer) return integer is
begin
if x<=l then return(x); else return(l);
end if;
end inrange;
---------------------------------------------------------------------------
-- Basic Character Converters
--
function to_char( x : INTEGER range 0 to 15) return character is
begin
case x is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when 10 => return('A');
when 11 => return('B');
when 12 => return('C');
when 13 => return('D');
when 14 => return('E');
when 15 => return('F');
end case;
end to_char;
function to_char( v : std_logic ) return CHARACTER is
begin
case v is
when '0' => return('0');
when '1' => return('1');
when 'L' => return('L');
when 'H' => return('H');
when 'Z' => return('Z');
when 'X' => return('X');
when 'U' => return('U');
when '-' => return('-');
when 'W' => return('W');
end case;
end to_char;
---------------------------------------------------------------------------
-- special std_logic_vector handling
--
function is01 ( v: std_logic) return BOOLEAN is
begin
return ( v='0' or v='1');
end is01;
function is01 ( v: STD_LOGIC_VECTOR ; len : INTEGER) return BOOLEAN is
variable ok : BOOLEAN;
begin
ok := TRUE;
for i in 0 to len-1 loop
ok := ok and is01( v(i));
end loop;
return (ok);
end is01;
---------------------------------------------------------------------------
-- String Functions
--
function strlen( str: STRING) return INTEGER is
variable i: INTEGER;
begin
i:=1;
while i<= MAXSTRLEN and str(i)/=NUL loop
i:=i+1;
end loop;
return(i-1);
end strlen;
function strcopy ( instr : STRING) return STRING is
variable outstr : STRING (1 to MAXSTRLEN);
variable i: INTEGER;
begin
outstr(1 to instr'length) := instr;
outstr(instr'length+1) := NUL;
return(outstr);
end strcopy;
---------------------------------------------------------------------------
-- Number Printing Routines
--
function hexchar ( vect : STD_LOGIC_VECTOR) return character is
variable v : STD_LOGIC_VECTOR ( 3 downto 0);
variable char : CHARACTER;
begin
v := vect;
if is01(v(0)) and is01(v(1)) and is01(v(2)) and is01(v(3)) then
char := to_char (to_integer(v));
elsif v(0)=v(1) and v(0)=v(2) and v(0)=v(3) then
char:= to_char(v(0));
else
char:='?';
end if;
return(char);
end hexchar;
function inttostr( value : INTEGER; base : INTEGER;
numlen : INTEGER :=0; zeros: BOOLEAN:=FALSE) return STRING is
variable str : STRING (1 to MAXSTRLEN);
variable s1 : STRING (MAXSTRLEN downto 1);
variable pos,x,xn,x1 : INTEGER;
begin
if value=-2147483648 then
case base is
when 2 => str(1 to 33) := ( 1=> '1', 33 => NUL, others => '0');
when 10 => str(1 to 12) := "-2147483648" & NUL;
when 16 => str(1 to 9) := "80000000" & NUL;
when others => str ( 1 to 12) := "MAXNEGVALUE" & NUL;
end case;
else
x := abs(value);
pos := 0;
while x>0 or pos=0 loop
pos:=pos+1;
xn := x / base;
x1 := x - xn * base ;
x := xn;
s1(pos) := to_char(x1);
end loop;
if value<0 then
pos:=pos+1;
s1(pos):='-';
end if;
if pos>numlen then
str(1 to pos) := s1 (pos downto 1);
str(pos+1) := NUL;
else
str := (others => ' ');
if ZEROS and base/=10 then
str := (others => '0');
end if;
str( (1+numlen-pos) to numlen) := s1(pos downto 1);
str(numlen+1) := NUL;
end if;
end if;
return(str);
end inttostr;
function vecttostr( value : STD_LOGIC_VECTOR; len : INTEGER; base : INTEGER;
numlen : INTEGER :=0;
zeros: BOOLEAN:=FALSE) return STRING is
variable str : STRING (1 to MAXSTRLEN);
variable s1 : STRING (MAXSTRLEN downto 1);
variable pos, len4 : INTEGER;
variable x : QWORD;
variable vect4 : std_logic_vector(3 downto 0);
begin
x:=value;
if len<64 then
x(63 downto len) := (others =>'0');
end if;
case base is
when 2 => for i in 0 to len-1 loop
s1(i+1) := to_char(value(i));
end loop;
pos:=len;
when 16 => len4 := ((len+3)/4);
for i in 0 to len4-1 loop
vect4 := x( 3+(4*i) downto 4*i);
s1(i+1) := hexchar(vect4);
end loop;
pos:=len4;
when others => s1:=strcopy("ESAB LAGELLI");
end case;
if pos>numlen then
str(1 to pos) := s1 (pos downto 1);
str(pos+1) := NUL;
else
case ZEROS is
when TRUE => str := (others => '0');
when FALSE => str := (others => ' ');
end case;
str( (1+numlen-pos) to numlen) := s1(pos downto 1);
str(numlen+1) := NUL;
end if;
return(str);
end vecttostr;
---------------------------------------------------------------------------
-- Multi Type input handlers
--
function fmt ( x : BOOLEAN) return T_FMT is
variable fm : T_FMT;
begin
fm.f_type := INT;
if x then fm.f_integer := 1;
else fm.f_integer := 0;
end if;
return(fm);
end fmt;
function fmt ( x : INTEGER) return T_FMT is
variable fm : T_FMT;
begin
fm.f_type := INT;
fm.f_integer := x;
return(fm);
end fmt;
function fmt ( x : STD_LOGIC_VECTOR) return T_FMT is
variable fm : T_FMT;
begin
fm.f_type := VECT;
fm.f_vector(x'length-1 downto 0) := x;
fm.f_length := x'length;
return(fm);
end fmt;
function fmt ( x : string ) return T_FMT is
variable fm : T_FMT;
begin
fm.f_type := STRG;
fm.f_string(x'range) := x;
if x'length+1<MAXSTRLEN then
fm.f_string(x'length+1) := NUL;
end if;
fm.f_length := x'length;
return(fm);
end fmt;
function fmt ( x : character ) return T_FMT is
variable fm : T_FMT;
begin
fm.f_type := STRG;
fm.f_string(1) := x;
fm.f_string(2) := NUL;
fm.f_length := 1;
return(fm);
end fmt;
function fmt ( x : std_logic) return T_FMT is
variable fm : T_FMT;
variable x1 : STD_LOGIC_VECTOR ( 0 downto 0);
begin
x1(0) := x;
fm.f_type := VECT;
fm.f_vector(x1'length-1 downto 0) := x1;
fm.f_length := x1'length;
return(fm);
end fmt;
---------------------------------------------------------------------------
-- The Main Print Routine
--
procedure theprintf( SPRINTF : BOOLEAN;
strout : out string;
str : STRING;
Params : T_FMT_ARRAY ) is
variable ll : LINE;
variable str1,pstr : STRING (1 to MAXSTRLEN);
variable ip,op,pp,iplen : INTEGER;
variable numlen : INTEGER;
variable zeros : BOOLEAN;
variable more : BOOLEAN;
variable intval : INTEGER;
variable vectval: QWORD;
variable len : INTEGER;
variable ftype : T_NUMTYPE;
variable tnow : INTEGER;
begin
iplen := str'length;
ip:=1; op:=0; pp:=params'low;
while ip<=iplen and str( inrange(ip,iplen))/=NUL loop
if str(ip) = '%' then
more:=TRUE;
numlen:=0; zeros:=FALSE;
while more loop
more:=FALSE;
ip:=ip+1;
ftype := params(pp).f_type;
intval := params(pp).f_integer;
vectval:= params(pp).f_vector;
len := params(pp).f_length;
case str(ip) is
when '0' => ZEROS:=TRUE;
more:=TRUE;
when '1' to '9' =>
numlen:= 10* numlen + character'pos(str(ip))-48;
more := TRUE;
when '%' => pstr := strcopy("%");
when 'd' => case ftype is
when INT => pstr := inttostr(intval,10,numlen,zeros);
when VECT => if is01(vectval,len) then
intval:= to_integer(vectval(len-1 downto 0));
pstr := inttostr(intval,10,numlen,zeros);
else
pstr := strcopy("UNKNOWN" );
end if;
when others => pstr := strcopy("INVALID PRINTF d:" & str);
end case;
pp:=pp+1;
when 't' => tnow := NOW / 1 ns;
pstr := inttostr(tnow,10,numlen,zeros);
when 'h' => case ftype is
when INT => vectval(31 downto 0) := conv_STD_LOGIC_VECTOR(intval,32);
len := 32;
pstr := vecttostr(vectval,len,16,numlen,zeros);
when VECT => pstr := vecttostr(vectval,len,16,numlen,zeros);
when others => pstr := strcopy("INVALID PRINTF h:" & str);
end case;
pp:=pp+1;
when 'u' => case ftype is
when INT => vectval(31 downto 0) := conv_STD_LOGIC_VECTOR(intval,32);
len := 32;
pstr := vecttostr(vectval,len,16,numlen,zeros);
when VECT => pstr := vecttostr(vectval,len,16,numlen,zeros);
when others => pstr := strcopy("INVALID PRINTF h:" & str);
end case;
pp:=pp+1;
when 'b' => case ftype is
when INT => vectval := ( others => '0');
vectval(31 downto 0) := conv_STD_LOGIC_VECTOR(intval,32);
len:=1;
for i in 1 to 31 loop
if vectval(i)='1' then
len:=i+1; -- Fix 3Oct06 CoreABC
end if;
end loop;
pstr := vecttostr(vectval,len,2,numlen,zeros);
when VECT => pstr := vecttostr(vectval,len,2,numlen,zeros);
when others => pstr := strcopy("INVALID PRINTF b:" & str);
end case;
pp:=pp+1;
when 'x' => case ftype is
when INT => vectval(31 downto 0) := conv_STD_LOGIC_VECTOR(intval,32);
len := 32;
pstr := vecttostr(vectval,len,16,numlen,zeros);
when VECT => pstr := vecttostr(vectval,len,16,numlen,zeros);
when others => pstr := strcopy("INVALID PRINTF x:" & str);
end case;
pp:=pp+1;
when 's' => case ftype is
when STRG => pstr:=params(pp).f_string;
when others => pstr := strcopy("INVALID PRINTF s:" & str);
end case;
pp:=pp+1;
when 'c' => case ftype is
when STRG => pstr:=params(pp).f_string;
when others => pstr := strcopy("INVALID PRINTF s:" & str);
end case;
pp:=pp+1;
when others => pstr := strcopy("ILLEGAL FORMAT");
assert FALSE
report "TEXTIO Processing Problem"
severity FAILURE;
end case;
end loop;
len := strlen(pstr);
for i in 1 to len loop
str1(op+i) := pstr(i);
end loop;
ip:=ip+1;
op:=op+len;
elsif str(ip)='\' then
case str(ip+1) is
when 'n' => str1(op+1):= NUL;
if not SPRINTF then
write( ll , str1 );
writeline( output, ll);
end if;
op := 0; ip:=ip+1;
str1(op+1) := NUL;
when others =>
end case;
ip:=ip+1;
else
op:=op+1;
str1(op) := str(ip);
ip:=ip+1;
end if;
end loop;
if op>0 then
str1(op+1):=NUL;
if SPRINTF then
strout := str1(strout'range);
else
write( ll , str1 );
writeline(output, ll);
end if;
end if;
end theprintf;
-------------------------------------------------------------------------------------
procedure printf( str : STRING; params : T_FMT ) is
variable strout : STRING (1 to MAXSTRLEN);
variable f_fmt : T_FMT_ARRAY ( 1 to 1);
begin
f_fmt(1) := params;
theprintf(FALSE,strout,str,f_fmt);
end printf;
procedure printf( str : STRING ) is
variable strout : STRING (1 to MAXSTRLEN);
variable fm : T_FMT_ARRAY ( 1 to 1);
begin
fm(1).f_type := NONE;
theprintf(FALSE,strout,str,fm);
end printf;
procedure printf( str : STRING;
Params : T_FMT_ARRAY ) is
variable strout : STRING (1 to MAXSTRLEN);
begin
theprintf(FALSE,strout,str,Params);
end printf;
-------------------------------------------------------------------------------------
procedure sprintf( strout : out STRING;
str : STRING;
Params : T_FMT_ARRAY ) is
begin
theprintf( TRUE, strout, str,Params);
end sprintf;
procedure sprintf( strout : out STRING; str : STRING; params : T_FMT ) is
variable f_fmt : T_FMT_ARRAY ( 1 to 1);
begin
f_fmt(1) := params;
theprintf( TRUE,strout,str,f_fmt);
end sprintf;
procedure sprintf( strout : out STRING; str : STRING ) is
variable fm : T_FMT_ARRAY ( 1 to 1);
begin
fm(1).f_type := NONE;
theprintf( TRUE,strout,str,fm);
end sprintf;
-------------------------------------------------------------------------------------
procedure ifprintf( enable : BOOLEAN;
str : STRING;
Params : T_FMT_ARRAY ) is
begin
if enable then
printf(str,params);
end if;
end ifprintf;
procedure ifprintf( enable : BOOLEAN; str : STRING; params : T_FMT ) is
variable f_fmt : T_FMT_ARRAY ( 1 to 1);
begin
if enable then
f_fmt(1) := params;
printf(str,f_fmt);
end if;
end ifprintf;
procedure ifprintf( enable : BOOLEAN; str : STRING ) is
variable fm : T_FMT_ARRAY ( 1 to 1);
begin
if enable then
fm(1).f_type := NONE;
printf(str,fm);
end if;
end ifprintf;
end textio;
---------------------------------------------------------------------------
-- This a Test For the above Routines
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
use work.textio.all;
entity textio_test is
end textio_test;
architecture TB of textio_test is
begin
process
variable dw : std_logic_vector ( 9 downto 0);
variable xx : std_logic_vector(15 downto 0);
variable xv : std_logic_vector(31 downto 0);
variable xi : integer;
variable ll : LINE;
file FSTR : text open write_mode is "Cpulog.txt" ;
variable strout : STRING(1 to 80);
begin
wait for 1 ns ;
printf("Textio Test strings v1.2");
printf("Note I think MTI uses variable width Fonts");
xx:= conv_std_logic_vector( 16#AAAA#,16);
printf("Using 04x %04x",fmt(xx));
printf("Using 04u %04u",fmt(xx));
printf("-d...123456 = %d",fmt(123456));
printf("-8d..123456 = %8d",fmt(123456));
printf("-08d.123456 = %08d",fmt(123456));
printf("-02d.123456 = %02d",fmt(123456));
printf("This is a Binary %016b",fmt(16#55AA#));
printf("This is a Decimal %d",fmt(1234));
printf("This is a Hex %h",fmt(16#1234#));
printf("This is a Simple String");
printf("This is a Simple String with a CRLF\nin the middle");
printf("Read Location %d = %h",fmt(123456)&fmt(16#654321#));
printf("-d...-123456 = %d",fmt(-123456));
printf("-d...-123456 = %08d",fmt(-123456));
dw := ( others => '0');
printf("-x...000 = %x",fmt(dw));
dw := "0101010101";
printf("-x...155 = %x",fmt(dw));
printf("-b...155 = %b",fmt(dw));
dw := "0101U10101";
printf("-x...1?5 = %x",fmt(dw));
printf("-b...1?5 = %b",fmt(dw));
dw := "01UUUU0101";
printf("-x...1U5 = %x",fmt(dw));
printf("-b...1U5 = %b",fmt(dw));
printf(" Time is %t ns ");
wait for 1500 ps;
printf(" Time 1.5ns later is %t ns ");
sprintf( strout , "SPRINTF Read Location %d = %h",fmt(123456)&fmt(16#654321#));
printf("OUT STRING %s",fmt(strout));
write( ll , strout );
writeline(FSTR, ll);
file_close( FSTR);
printf("Around Zero Handling");
for i in 2 downto -2 loop
xi := i;
printf("Value Integer (d x u h) %d %x %u %h ",fmt(xi)&fmt(xi)&fmt(xi)&fmt(xi));
end loop;
for i in 2 downto -2 loop
case i is
when -2 => xv := ( others => '1'); xv(0) := '0';
when -1 => xv := ( others => '1');
when 0 => xv := ( others => '0');
when 1 => xv := ( others => '0'); xv(0) := '1';
when 2 => xv := ( others => '0'); xv(1) := '1';
end case;
printf("Value std_logic (d x u h) %d %x %u %h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv));
end loop;
printf("Negative Handling Extended Print");
for i in 2 downto -2 loop
xi := i;
printf("Value Integer (d x u h) %0d %0x %0u %0h ",fmt(xi)&fmt(xi)&fmt(xi)&fmt(xi));
end loop;
for i in 2 downto -2 loop
case i is
when -2 => xv := ( others => '1'); xv(0) := '0';
when -1 => xv := ( others => '1');
when 0 => xv := ( others => '0');
when 1 => xv := ( others => '0'); xv(0) := '1';
when 2 => xv := ( others => '0'); xv(1) := '1';
end case;
printf("Value std_logic (d x u h) %08d %08x %08u %08h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv));
end loop;
printf("Negative Handling Extended Print with dont cares");
for i in 2 downto -2 loop
case i is
when -2 => xv := ( others => '1'); xv(0) := '0';
when -1 => xv := ( others => '1');
when 0 => xv := ( others => '0');
when 1 => xv := ( others => '0'); xv(0) := '1';
when 2 => xv := ( others => '0'); xv(1) := '1';
end case;
xv(6) := 'X';
printf("Value std_logic (d x u h) %08d %08x %08u %08h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv));
end loop;
printf("Max Values Positive");
for i in 0 to 2 loop
case i is
when 0 => xi := 16#7FFFFFFD#;
when 1 => xi := 16#7FFFFFFE#;
when 2 => xi := 16#7FFFFFFF#;
end case;
printf("Value Integer (d x u h) %0d %0x %0u %0h ",fmt(xi)&fmt(xi)&fmt(xi)&fmt(xi));
end loop;
for i in 0 to 2 loop
case i is
when 0 => xv := ( others => '1'); xv(31) := '0'; xv(1) := '0';
when 1 => xv := ( others => '1'); xv(31) := '0'; xv(0) := '0';
when 2 => xv := ( others => '1'); xv(31) := '0'; xv(0) := '1';
end case;
printf("Value std_logic (d x u h) %08d %08x %08u %08h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv));
end loop;
printf("Max Values Negative");
for i in 0 to 2 loop -- if extended to most positive simulator loops for ever
case i is
-- Put these three lines back in for real testing -- commented out to stop warnings!
-- when 0 => xi := 16#80000002#;
-- when 1 => xi := 16#80000001#;
-- when 2 => xi := 16#80000000#;
when others => xi:=1000;
end case;
printf("Value Integer (d x u h) %0d %0x %0u %0h ",fmt(xi)&fmt(xi)&fmt(xi)&fmt(xi));
end loop;
for i in 0 to 2 loop
case i is
when 0 => xv := ( others => '0'); xv(31) := '1'; xv(1) := '1';
when 1 => xv := ( others => '0'); xv(31) := '1'; xv(0) := '1';
when 2 => xv := ( others => '0'); xv(31) := '1'; xv(0) := '0';
end case;
printf("Value std_logic (d x u h) %08d %08x %08u %08h ",fmt(xv)&fmt(xv)&fmt(xv)&fmt(xv));
end loop;
wait for 1 ns;
wait;
end process;
end TB;
-- synthesis translate_off
|
mit
|
f67180ccc066752f44ea7c70d5ac15e0
| 0.502508 | 3.536841 | false | false | false | false |
mitchsm/nvc
|
test/sem/scope.vhd
| 2 | 7,103 |
package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.pack2;
entity no_use_clause is
port (
a : in pack1.my_int1;
b : out pack2.my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of no_use_clause is
type my_int1 is range 10 to 50;
begin
process is
begin
-- Should fail as types have same name but from different packages
b <= a;
end process;
process is
variable v : pack2.my_int1;
begin
b <= v; -- OK
end process;
process is
variable v : my_int1;
begin
-- Should fail as local my_int1 distinct from pack1.my_int1
v := a;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack1.all;
entity foo is
generic ( g : my_int1 );
port ( p : in my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of foo is
-- Architecture decls exist in same scope as entity so this should
-- generate an error
signal g : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture b of foo is
-- Should also generate an error
signal p : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture c of foo is
begin
-- This is OK as processes define a new scope
process is
variable p : my_int1;
variable g : my_int1;
begin
g := 6;
p := 2;
wait for 1 ns;
end process;
end architecture;
-------------------------------------------------------------------------------
entity overload is
port (
SI: in bit;
SO: out bit
);
end ;
architecture behave of overload is
begin
foo_inst:
SO <= SI;
end behave;
-------------------------------------------------------------------------------
use work.all;
entity no_use_clause is
port (
a : in pack1.my_int1; -- OK
b : out my_int1 ); -- Error
end entity;
-------------------------------------------------------------------------------
package pack3 is
type my_enum is (E1, E2, E3);
end package;
-------------------------------------------------------------------------------
use work.pack3.all;
package pack4 is
type my_enum_array is array (integer range <>) of my_enum;
end package;
-------------------------------------------------------------------------------
use work.pack4.all;
architecture a of foo is
signal x : my_enum_array(1 to 3); -- OK
signal y : my_enum_array(1 to 3) := (others => E1);
-- Error: E1 not visible
begin
end architecture;
-------------------------------------------------------------------------------
package pack5 is
function func1(x : integer) return boolean;
function func2(x : integer) return boolean;
function "and"(x, y : integer) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack5.func1;
architecture a2 of foo is
begin
process is
begin
assert func1(4); -- OK
assert func2(5); -- Error
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack5.not_here; -- Error
architecture a3 of foo is
begin
end architecture;
-------------------------------------------------------------------------------
entity bar is
end entity;
architecture a4 of bar is
begin
process is
use work.pack1.all;
variable x : my_int1; -- OK
begin
x := 5;
end process;
process is
variable x : my_int1; -- Error
begin
end process;
b: block is
use work.pack1;
signal x : pack1.my_int1; -- OK
begin
end block;
end architecture;
-------------------------------------------------------------------------------
use work.pack5."and";
architecture a5 of bar is
begin
process is
begin
assert 1 and 2; -- OK
assert work.pack5."and"(1, 2); -- OK
assert pack5."and"(1, 2); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
package pack6 is
component bar is
end component;
end package;
-------------------------------------------------------------------------------
use work.pack6.all;
architecture a6 of bar is
begin
process is
begin
report bar'path_name; -- OK (references entity)
end process;
end architecture;
-------------------------------------------------------------------------------
use foo.bar.all; -- Error
architecture a7 of bar is
begin
end architecture;
-------------------------------------------------------------------------------
package pack7 is
function foo(x : in integer) return boolean;
function foo(y : in real) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack7.foo;
architecture issue62 of bar is
begin
process is
begin
assert foo(integer'(1)); -- OK
assert foo(real'(1.6)); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
use work.all;
use work.pack1.all;
architecture issue63 of bar is
signal x : my_int1; -- OK
begin
end architecture;
-------------------------------------------------------------------------------
package pack8 is
function min(x, y : in integer) return integer;
end package;
-------------------------------------------------------------------------------
use work.pack8.all; -- OK
architecture unit_decl_crash of bar is
begin
process is
variable x : integer := min(1, 2); -- OK
begin
end process;
end architecture;
-------------------------------------------------------------------------------
architecture labels of bar is
signal mySignalVector: bit_vector (7 downto 0);
signal myOtherSignal: bit := '1';
begin
process
begin
L1:
for i in 0 to 9 loop
for i in 0 to 7 loop
mySignalVector(i) <= myOtherSignal;
report "outer loop i = " & integer'image(L1.i);
report "inner loop i = " & integer'image(i);
report integer'image(L1.x); -- Error
end loop;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
69fc916cbaf24ce09b9318655a214950
| 0.41039 | 4.812331 | false | false | false | false |
mitchsm/nvc
|
test/regress/cover1.vhd
| 5 | 527 |
entity cover1 is
end entity;
architecture test of cover1 is
signal s : integer;
begin
process is
variable v : integer;
begin
v := 1;
s <= 2;
wait for 1 ns;
if s = 2 or s > 10 then
v := 3;
else
v := 2;
end if;
while v > 0 loop
if v mod 2 = 0 then
v := v - 1;
else
v := (v / 2) * 2;
end if;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
e6a301adff50b87f780c3b6e6d2b5939
| 0.404175 | 3.992424 | false | false | false | false |
blutsvente/MIX
|
test/results/bugver/20051018d/ent_a-struct-a.vhd
| 1 | 3,453 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of ent_a
--
-- Generated
-- by: wig
-- on: Wed Nov 2 10:48:49 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-struct-a.vhd,v 1.2 2005/11/02 14:29:09 wig Exp $
-- $Date: 2005/11/02 14:29:09 $
-- $Log: ent_a-struct-a.vhd,v $
-- Revision 1.2 2005/11/02 14:29:09 wig
-- Remove extra ; from port map if port has comment
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.66 2005/10/24 15:43:48 wig Exp
--
-- Generator: mix_0.pl Revision: 1.38 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of ent_a
--
architecture struct of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa -- is i_padframe / hier inst_aa inst_aa inst_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
ramd_oe_i : in std_ulogic_vector(31 downto 0); -- bad conection bits detected
ramd_oe_i_r : in std_ulogic_vector(31 downto 0); -- reverse order
ramdm_oe_i : in std_ulogic_vector(3 downto 0); -- bad conection bits detected
ramdm_oe_i_r : in std_ulogic_vector(3 downto 0) -- reverse order
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab -- is i_vgca / hier inst_ab inst_ab inst_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
p_mix_sig_20051018d_go : out std_ulogic_vector(31 downto 0);
p_mix_sigrev_20051018d_go : out std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_20051018d : std_ulogic_vector(31 downto 0);
signal sigrev_20051018d : std_ulogic_vector(31 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa -- is i_padframe / hier inst_aa inst_aa inst_a
port map (
ramd_oe_i => sig_20051018d, -- bad conection bits detected
ramd_oe_i_r => sigrev_20051018d, -- reverse order
ramdm_oe_i(1 downto 0) => sig_20051018d(8 downto 7), -- bad conection bits detected
ramdm_oe_i(3 downto 2) => sig_20051018d(24 downto 23), -- bad conection bits detected
ramdm_oe_i_r(1 downto 0) => sigrev_20051018d(8 downto 7), -- reverse order
ramdm_oe_i_r(3 downto 2) => sigrev_20051018d(24 downto 23) -- reverse order
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab -- is i_vgca / hier inst_ab inst_ab inst_a
port map (
p_mix_sig_20051018d_go => sig_20051018d, -- bad conection bits detected
p_mix_sigrev_20051018d_go => sigrev_20051018d -- reverse order
);
-- End of Generated Instance Port Map for inst_ab
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
6f650240c22bd2d23004f44a2fb2fbe9
| 0.62786 | 3.159195 | false | false | false | false |
mitchsm/nvc
|
test/lower/arith1.vhd
| 3 | 778 |
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
assert 5 mod x = 2;
assert 5 rem x = 2;
assert (-5) rem x = -2;
assert (-5) mod x = 2;
assert x = +x;
wait;
end process;
end architecture;
|
gpl-3.0
|
ee0463d82fddb05ee8f7a0f75116fcfa
| 0.430591 | 3.536364 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/verilog/inst_t_e-rtl-a.vhd
| 1 | 2,850 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:44:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.3 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e -- a instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_signal_aa_ba_go : out std_ulogic;
p_mix_signal_bb_ab_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e -- b instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic;
signal s_int_signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_bb_ab <= s_int_signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a_i
inst_a_i: inst_a_e -- a instance
port map (
p_mix_signal_aa_ba_go => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_gi => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_a_i
-- Generated Instance Port Map for inst_b_i
inst_b_i: inst_b_e -- b instance
port map (
p_mix_signal_aa_ba_gi => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_go => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_b_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
d879627307279208514a78926ed047a3
| 0.599298 | 2.944215 | false | false | false | false |
blutsvente/MIX
|
test/results/bugver/ramd/vgca-struct-a.vhd
| 1 | 5,946 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of vgca
--
-- Generated
-- by: wig
-- on: Thu Jul 6 16:43:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca-struct-a.vhd,v 1.3 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: vgca-struct-a.vhd,v $
-- Revision 1.3 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of vgca
--
architecture struct of vgca is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component adc
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component bsr
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component clkgen
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component dac
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component padframe
-- No Generated Generics
port (
-- Generated Port for Entity padframe
mix_logic0_0 : in std_ulogic; -- padin
mix_logic0_bus_4 : in std_ulogic_vector(31 downto 0); -- padin
ramd_i : in std_ulogic_vector(31 downto 0); -- padin
ramd_i2 : in std_ulogic_vector(31 downto 0); -- padin
ramd_o : out std_ulogic_vector(31 downto 0); -- padout
ramd_o2 : out std_ulogic_vector(31 downto 0); -- padout
ramd_o3 : out std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity padframe
);
end component;
-- ---------
component tap_con
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_cpu
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_di
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_dp
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_fe
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_mm
-- No Generated Generics
port (
-- Generated Port for Entity vgca_mm
ramd_i : in std_ulogic_vector(31 downto 0);
ramd_i2 : in std_ulogic_vector(31 downto 0);
ramd_i3 : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity vgca_mm
);
end component;
-- ---------
component vgca_rc
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal mix_logic0_bus_4 : std_ulogic_vector(31 downto 0);
signal mm_ramd : std_ulogic_vector(31 downto 0);
signal mm_ramd2 : std_ulogic_vector(31 downto 0);
signal mm_ramd3 : std_ulogic_vector(31 downto 0);
-- __I_NODRV_I signal ramd_i : std_ulogic_vector(31 downto 0);
-- __I_NODRV_I signal ramd_i2 : std_ulogic_vector(31 downto 0);
-- __I_OUT_OPEN signal ramd_o : std_ulogic_vector(31 downto 0);
-- __I_OUT_OPEN signal ramd_o2 : std_ulogic_vector(31 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_0 <= '0';
mix_logic0_bus_4 <= ( others => '0' );
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for i_adc
i_adc: adc
;
-- End of Generated Instance Port Map for i_adc
-- Generated Instance Port Map for i_bsr
i_bsr: bsr
;
-- End of Generated Instance Port Map for i_bsr
-- Generated Instance Port Map for i_clkgen
i_clkgen: clkgen
;
-- End of Generated Instance Port Map for i_clkgen
-- Generated Instance Port Map for i_dac
i_dac: dac
;
-- End of Generated Instance Port Map for i_dac
-- Generated Instance Port Map for i_padframe
i_padframe: padframe
port map (
mix_logic0_0 => mix_logic0_0, -- padin
mix_logic0_bus_4 => mix_logic0_bus_4, -- padin
-- __I_NODRV_I -- __I_NODRV_I ramd_i => __nodrv__/ramd_i2/ramd_i, -- padin (X4)
-- __I_NODRV_I ramd_i2 => __nodrv__/ramd_i2, -- padin (X4)
ramd_o => mm_ramd,
-- __I_RECONN -- __I_RECONN ramd_o => open, -- padout (X4) -- __I_OUT_OPEN
ramd_o2 => mm_ramd2,
-- __I_RECONN ramd_o2 => open, -- padout (X4) -- __I_OUT_OPEN
ramd_o3 => mm_ramd3
);
-- End of Generated Instance Port Map for i_padframe
-- Generated Instance Port Map for i_tap_con
i_tap_con: tap_con
;
-- End of Generated Instance Port Map for i_tap_con
-- Generated Instance Port Map for i_vgca_cpu
i_vgca_cpu: vgca_cpu
;
-- End of Generated Instance Port Map for i_vgca_cpu
-- Generated Instance Port Map for i_vgca_di
i_vgca_di: vgca_di
;
-- End of Generated Instance Port Map for i_vgca_di
-- Generated Instance Port Map for i_vgca_dp
i_vgca_dp: vgca_dp
;
-- End of Generated Instance Port Map for i_vgca_dp
-- Generated Instance Port Map for i_vgca_fe
i_vgca_fe: vgca_fe
;
-- End of Generated Instance Port Map for i_vgca_fe
-- Generated Instance Port Map for i_vgca_mm
i_vgca_mm: vgca_mm
port map (
ramd_i => mm_ramd,
ramd_i2 => mm_ramd2,
ramd_i3 => mm_ramd3
);
-- End of Generated Instance Port Map for i_vgca_mm
-- Generated Instance Port Map for i_vgca_rc
i_vgca_rc: vgca_rc
;
-- End of Generated Instance Port Map for i_vgca_rc
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
e171c289a4b2c7f1a8a9f4175e76537d
| 0.61554 | 3.060216 | false | false | false | false |
blutsvente/MIX
|
test/results/bugver/ramd/padframe-struct-a.vhd
| 1 | 7,628 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of padframe
--
-- Generated
-- by: wig
-- on: Thu Jul 6 16:43:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: padframe-struct-a.vhd,v 1.5 2007/03/05 15:42:14 wig Exp $
-- $Date: 2007/03/05 15:42:14 $
-- $Log: padframe-struct-a.vhd,v $
-- Revision 1.5 2007/03/05 15:42:14 wig
-- Removed some bogus lines in reference files: mix_logic0_0 <= mic_logic0_0
--
-- Revision 1.4 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of padframe
--
architecture struct of padframe is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component pads_eastnord
-- No Generated Generics
port (
-- Generated Port for Entity pads_eastnord
ramd_i : in std_ulogic_vector(31 downto 0); -- padinpadinpadin
ramd_i2 : in std_ulogic_vector(31 downto 0); -- padinpadinpadin
ramd_o : out std_ulogic_vector(31 downto 0); -- padoutpadoutpadout
ramd_o2 : out std_ulogic_vector(31 downto 0); -- padoutpadoutpadout
ramd_o3 : out std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity pads_eastnord
);
end component;
-- ---------
component pads_eastsouth
-- No Generated Generics
port (
-- Generated Port for Entity pads_eastsouth
ramd_i : in std_ulogic_vector(31 downto 0); -- padinpadinpadin
ramd_i2 : in std_ulogic_vector(31 downto 0); -- padinpadinpadin
ramd_o : out std_ulogic_vector(31 downto 0); -- padoutpadoutpadout
ramd_o2 : out std_ulogic_vector(31 downto 0); -- padoutpadoutpadout
ramd_o3 : out std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity pads_eastsouth
);
end component;
-- ---------
component pads_nordeast
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_nordwest
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_southeast
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_southwest
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_westnord
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component pads_westsouth
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mix_logic0_1 : std_ulogic;
signal mix_logic0_2 : std_ulogic;
signal mix_logic0_3 : std_ulogic;
signal mix_logic0_bus_4 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal mix_logic0_bus_5 : std_ulogic_vector(31 downto 0);
signal mix_logic0_bus_6 : std_ulogic_vector(31 downto 0);
signal mix_logic0_bus_7 : std_ulogic_vector(31 downto 0);
signal mm_ramd : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal mm_ramd2 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal mm_ramd3 : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_0 <= '0';
mix_logic0_1 <= '0';
mix_logic0_2 <= '0';
mix_logic0_3 <= '0';
mix_logic0_bus_4 <= ( others => '0' );
mix_logic0_bus_5 <= ( others => '0' );
mix_logic0_bus_6 <= ( others => '0' );
mix_logic0_bus_7 <= ( others => '0' );
ramd_o <= mm_ramd; -- __I_O_BUS_PORT
ramd_o2 <= mm_ramd2; -- __I_O_BUS_PORT
ramd_o3 <= mm_ramd3; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for i_pads_en
i_pads_en: pads_eastnord
port map (
ramd_i(10) => mix_logic0_0, -- __I_BIT_TO_BUSPORT -- padin
ramd_i(15 downto 11) => ramd_i(15 downto 11), -- padin (X4)
ramd_i(23) => mix_logic0_1, -- __I_BIT_TO_BUSPORT -- padin
ramd_i(31 downto 24) => ramd_i(31 downto 24), -- padin (X4)
ramd_i2(10 downto 0) => mix_logic0_bus_4(10 downto 0), -- padin
ramd_i2(15 downto 11) => ramd_i2(15 downto 11), -- padin (X4)
ramd_i2(23 downto 16) => mix_logic0_bus_5(7 downto 0), -- padin
ramd_i2(31 downto 24) => ramd_i2(31 downto 24), -- padin (X4)
ramd_o(10 downto 0) => open, -- __W_PORT -- padout
ramd_o(15 downto 11) => ramd_o(15 downto 11), -- padout (X4)
ramd_o(20 downto 0) => mm_ramd(31 downto 11),
ramd_o(23 downto 16) => open, -- __W_PORT -- padout
ramd_o(31 downto 24) => ramd_o(31 downto 24), -- padout (X4)
ramd_o2 => mm_ramd2,
ramd_o2(10 downto 0) => open, -- __W_PORT -- padout
ramd_o2(15 downto 11) => ramd_o2(15 downto 11), -- padout (X4)
ramd_o2(23 downto 16) => open, -- __W_PORT -- padout
ramd_o2(31 downto 24) => ramd_o2(31 downto 24), -- padout (X4)
ramd_o3 => mm_ramd3
);
-- End of Generated Instance Port Map for i_pads_en
-- Generated Instance Port Map for i_pads_es
i_pads_es: pads_eastsouth
port map (
ramd_i(10 downto 0) => ramd_i(10 downto 0), -- padin (X4)
ramd_i(15) => mix_logic0_2, -- __I_BIT_TO_BUSPORT -- padin
ramd_i(23 downto 16) => ramd_i(23 downto 16), -- padin (X4)
ramd_i(31) => mix_logic0_3, -- __I_BIT_TO_BUSPORT -- padin
ramd_i2(10 downto 0) => ramd_i2(10 downto 0), -- padin (X4)
ramd_i2(15 downto 11) => mix_logic0_bus_6(4 downto 0), -- padin
ramd_i2(23 downto 16) => ramd_i2(23 downto 16), -- padin (X4)
ramd_i2(31 downto 24) => mix_logic0_bus_7(7 downto 0), -- padin
ramd_o(10 downto 0) => mm_ramd(10 downto 0),
ramd_o(10 downto 0) => ramd_o(10 downto 0), -- padout (X4)
ramd_o(15 downto 11) => open, -- __W_PORT -- padout
ramd_o(23 downto 16) => ramd_o(23 downto 16), -- padout (X4)
ramd_o(31 downto 24) => open, -- __W_PORT -- padout
ramd_o2(10 downto 0) => mm_ramd2(10 downto 0),
ramd_o2(10 downto 0) => ramd_o2(10 downto 0), -- padout (X4)
ramd_o2(15 downto 11) => open, -- __W_PORT -- padout
ramd_o2(23 downto 16) => ramd_o2(23 downto 16), -- padout (X4)
ramd_o2(31 downto 24) => open, -- __W_PORT -- padout
ramd_o3 => mm_ramd3
);
-- End of Generated Instance Port Map for i_pads_es
-- Generated Instance Port Map for i_pads_ne
i_pads_ne: pads_nordeast
;
-- End of Generated Instance Port Map for i_pads_ne
-- Generated Instance Port Map for i_pads_nw
i_pads_nw: pads_nordwest
;
-- End of Generated Instance Port Map for i_pads_nw
-- Generated Instance Port Map for i_pads_se
i_pads_se: pads_southeast
;
-- End of Generated Instance Port Map for i_pads_se
-- Generated Instance Port Map for i_pads_sw
i_pads_sw: pads_southwest
;
-- End of Generated Instance Port Map for i_pads_sw
-- Generated Instance Port Map for i_pads_wn
i_pads_wn: pads_westnord
;
-- End of Generated Instance Port Map for i_pads_wn
-- Generated Instance Port Map for i_pads_ws
i_pads_ws: pads_westsouth
;
-- End of Generated Instance Port Map for i_pads_ws
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
a2593cbfc547b1e980846cd262db79c7
| 0.619297 | 2.795163 | false | false | false | false |
mitchsm/nvc
|
test/regress/cond2.vhd
| 5 | 643 |
entity cond2 is
end entity;
architecture test of cond2 is
signal x, y : integer;
begin
process is
begin
x <= 5;
y <= 2;
wait for 1 ns;
if x = 5 then
if y = 2 then
report "y = 2";
if x = 4 then
report "x = 4" severity failure;
else
report "x /= 4";
end if;
else
report "y /= 2" severity failure;
end if;
else
report "x /= 5" severity failure;
end if;
wait;
end process;
end architecture;
|
gpl-3.0
|
5222cbe31403957230855fa9be1c13fc
| 0.404355 | 4.592857 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/given/ioblock1_e-rtl-a.vhd
| 1 | 15,694 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock1_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock1_e-rtl-a.vhd,v 1.2 2005/07/19 07:13:14 wig Exp $
-- $Date: 2005/07/19 07:13:14 $
-- $Log: ioblock1_e-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:14 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock1_e
--
architecture rtl of ioblock1_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_r_io --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(4 downto 0);
en : in std_ulogic_vector(4 downto 0);
nand_dir : in std_ulogic;
nand_in : in std_ulogic;
nand_out : out std_ulogic;
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_r_io
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_out_12 : std_ulogic;
signal nand_out_13 : std_ulogic;
signal nand_out_14 : std_ulogic;
signal nand_out_15 : std_ulogic;
signal nand_out_16 : std_ulogic;
signal nand_out_17 : std_ulogic;
signal nand_out_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
nand_out_2 <= p_mix_nand_out_2_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_r_io_12
ioc_r_io_12: ioc_r_io
port map (
di => di2(0), -- io data
do(0) => disp2(0), -- io data
do(1) => display_ls_min(0), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(0), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(0), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(0), -- Display storage buffer 1 ms_min
en(0) => disp2_en(0), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_2, -- Links ...
nand_out => nand_out_12, -- out to in
p_di => pad_di_12, -- data in from pad
p_do => pad_do_12, -- data out to pad
p_en => pad_en_12, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_12
-- Generated Instance Port Map for ioc_r_io_13
ioc_r_io_13: ioc_r_io
port map (
di => di2(1), -- io data
do(0) => disp2(1), -- io data
do(1) => display_ls_min(1), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(1), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(1), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(1), -- Display storage buffer 1 ms_min
en(0) => disp2_en(1), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_12, -- out to in
nand_out => nand_out_13, -- out to in
p_di => pad_di_13, -- data in from pad
p_do => pad_do_13, -- data out to pad
p_en => pad_en_13, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_13
-- Generated Instance Port Map for ioc_r_io_14
ioc_r_io_14: ioc_r_io
port map (
di => di2(3), -- io data
do(0) => disp2(3), -- io data
do(1) => display_ls_min(2), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(2), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(2), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(2), -- Display storage buffer 1 ms_min
en(0) => disp2_en(3), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_13, -- out to in
nand_out => nand_out_14, -- out to in
p_di => pad_di_14, -- data in from pad
p_do => pad_do_14, -- data out to pad
p_en => pad_en_14, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_14
-- Generated Instance Port Map for ioc_r_io_15
ioc_r_io_15: ioc_r_io
port map (
di => di2(4), -- io data
do(0) => disp2(4), -- io data
do(1) => display_ls_min(3), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(3), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(3), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(3), -- Display storage buffer 1 ms_min
en(0) => disp2_en(4), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_14, -- out to in
nand_out => nand_out_15, -- out to in
p_di => pad_di_15, -- data in from pad
p_do => pad_do_15, -- data out to pad
p_en => pad_en_15, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_15
-- Generated Instance Port Map for ioc_r_io_16
ioc_r_io_16: ioc_r_io
port map (
di => di2(5), -- io data
do(0) => disp2(5), -- io data
do(1) => display_ls_min(4), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(4), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(4), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(4), -- Display storage buffer 1 ms_min
en(0) => disp2_en(5), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_15, -- out to in
nand_out => nand_out_16, -- out to in
p_di => pad_di_16, -- data in from pad
p_do => pad_do_16, -- data out to pad
p_en => pad_en_16, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_16
-- Generated Instance Port Map for ioc_r_io_17
ioc_r_io_17: ioc_r_io
port map (
di => di2(6), -- io data
do(0) => disp2(6), -- io data
do(1) => display_ls_min(5), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(5), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(5), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(5), -- Display storage buffer 1 ms_min
en(0) => disp2_en(6), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_16, -- out to in
nand_out => nand_out_17, -- out to in
p_di => pad_di_17, -- data in from pad
p_do => pad_do_17, -- data out to pad
p_en => pad_en_17, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_17
-- Generated Instance Port Map for ioc_r_io_18
ioc_r_io_18: ioc_r_io
port map (
di => di2(7), -- io data
do(0) => disp2(7), -- io data
do(1) => display_ls_min(6), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(6), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(6), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(6), -- Display storage buffer 1 ms_min
en(0) => disp2_en(7), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_17, -- out to in
nand_out => open, -- Last is open
p_di => pad_di_18, -- data in from pad
p_do => pad_do_18, -- data out to pad
p_en => pad_en_18, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_18
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
42ac852e3c59f8a69c13afb50ff81a80
| 0.586721 | 2.463736 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/lib/psl.vhd
| 1 | 13,721 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.all;
package psl is
----------------------------------------------------------------------------------------------------------------------- clock/reset
type cr_in is record
clk : std_logic;
rst : std_logic;
end record;
----------------------------------------------------------------------------------------------------------------------- psl interface
constant PSL_AFU_DESC_WIDTH : natural := 64;
constant PSL_TAG_WIDTH : natural := 8;
constant PSL_COMMAND_WIDTH : natural := 13;
constant PSL_ABT_WIDTH : natural := 3;
constant PSL_ADDRESS_WIDTH : natural := 64;
constant PSL_CH_WIDTH : natural := 16;
constant PSL_SIZE_WIDTH : natural := 12;
constant PSL_ROOM_WIDTH : natural := 8;
constant PSL_HALFLINE_INDEX_WIDTH : natural := 6;
constant PSL_LATENCY_WIDTH : natural := 4;
constant PSL_DATA_WIDTH : natural := 512;
constant PSL_RESPONSE_WIDTH : natural := 8;
constant PSL_CREDITS_WIDTH : natural := 9;
constant PSL_CACHESTATE_WIDTH : natural := 2;
constant PSL_CACHEPOS_WIDTH : natural := 13;
constant PSL_MMIO_ADDRESS_WIDTH : natural := 24;
constant PSL_MMIO_DATA_WIDTH : natural := 64;
constant PSL_JOB_COMMAND_WIDTH : natural := 8;
constant PSL_ERROR_WIDTH : natural := 64;
constant PSL_WORD_WIDTH : natural := 32;
constant PSL_DOUBLE_WORD_WIDTH : natural := 64;
constant PSL_ERAT_WIDTH : natural := 9;
constant PSL_PAGESIZE : natural := 65536;
constant PSL_CACHELINE_SIZE : natural := 128;
constant PSL_CACHELINE_BYTES : unsigned(log2(PSL_CACHELINE_SIZE) downto 0) := u(PSL_CACHELINE_SIZE, log2(PSL_CACHELINE_SIZE) + 1);
constant PSL_CACHELINE_BYTES_OUT : unsigned(PSL_SIZE_WIDTH - 1 downto 0) := u(PSL_CACHELINE_SIZE, PSL_SIZE_WIDTH);
----------------------------------------------------------------------------------------------------------------------- psl flags
constant PCO_READ_CL_S : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0a50#, PSL_COMMAND_WIDTH);
constant PCO_READ_CL_M : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0a60#, PSL_COMMAND_WIDTH);
constant PCO_READ_CL_LCK : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0a6b#, PSL_COMMAND_WIDTH);
constant PCO_READ_CL_RES : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0240#, PSL_COMMAND_WIDTH);
constant PCO_TOUCH_I : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0250#, PSL_COMMAND_WIDTH);
constant PCO_TOUCH_M : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0260#, PSL_COMMAND_WIDTH);
constant PCO_WRITE_MI : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0d60#, PSL_COMMAND_WIDTH);
constant PCO_WRITE_MS : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0d70#, PSL_COMMAND_WIDTH);
constant PCO_WRITE_UNLOCK : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0d6b#, PSL_COMMAND_WIDTH);
constant PCO_WRITE_C : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0d67#, PSL_COMMAND_WIDTH);
constant PCO_PUSH_I : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0140#, PSL_COMMAND_WIDTH);
constant PCO_PUSH_S : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0150#, PSL_COMMAND_WIDTH);
constant PCO_EVICT_I : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#1140#, PSL_COMMAND_WIDTH);
constant PCO_RESERVED : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#1260#, PSL_COMMAND_WIDTH);
constant PCO_LOCK : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#016b#, PSL_COMMAND_WIDTH);
constant PCO_UNLOCK : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#017b#, PSL_COMMAND_WIDTH);
constant PCO_READ_CL_NA : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0a00#, PSL_COMMAND_WIDTH);
constant PCO_READ_PNA : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0e00#, PSL_COMMAND_WIDTH);
constant PCO_WRITE_NA : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0d00#, PSL_COMMAND_WIDTH);
constant PCO_WRITE_NJ : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0d10#, PSL_COMMAND_WIDTH);
constant PCO_FLUSH : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0100#, PSL_COMMAND_WIDTH);
constant PCO_INTREQ : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0000#, PSL_COMMAND_WIDTH);
constant PCO_RESTART : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0) := slv(16#0001#, PSL_COMMAND_WIDTH);
constant PTOB_STRICT : std_logic_vector(PSL_ABT_WIDTH - 1 downto 0) := slv(16#0#, PSL_ABT_WIDTH);
constant PTOB_ABORT : std_logic_vector(PSL_ABT_WIDTH - 1 downto 0) := slv(16#1#, PSL_ABT_WIDTH);
constant PTOB_PAGE : std_logic_vector(PSL_ABT_WIDTH - 1 downto 0) := slv(16#2#, PSL_ABT_WIDTH);
constant PTOB_PREF : std_logic_vector(PSL_ABT_WIDTH - 1 downto 0) := slv(16#3#, PSL_ABT_WIDTH);
constant PTOB_SPEC : std_logic_vector(PSL_ABT_WIDTH - 1 downto 0) := slv(16#7#, PSL_ABT_WIDTH);
constant PRC_DONE : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#00#, PSL_RESPONSE_WIDTH);
constant PRC_AERROR : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#01#, PSL_RESPONSE_WIDTH);
constant PRC_DERROR : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#03#, PSL_RESPONSE_WIDTH);
constant PRC_NLOCK : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#04#, PSL_RESPONSE_WIDTH);
constant PRC_NRES : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#05#, PSL_RESPONSE_WIDTH);
constant PRC_FLUSHED : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#06#, PSL_RESPONSE_WIDTH);
constant PRC_FAULT : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#07#, PSL_RESPONSE_WIDTH);
constant PRC_FAILED : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#08#, PSL_RESPONSE_WIDTH);
constant PRC_PAGED : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0) := slv(16#0a#, PSL_RESPONSE_WIDTH);
constant PCC_START : std_logic_vector(PSL_JOB_COMMAND_WIDTH - 1 downto 0) := slv(16#90#, PSL_JOB_COMMAND_WIDTH);
constant PCC_RESET : std_logic_vector(PSL_JOB_COMMAND_WIDTH - 1 downto 0) := slv(16#80#, PSL_JOB_COMMAND_WIDTH);
constant PCC_TIMEBASE : std_logic_vector(PSL_JOB_COMMAND_WIDTH - 1 downto 0) := slv(16#42#, PSL_JOB_COMMAND_WIDTH);
----------------------------------------------------------------------------------------------------------------------- afu descriptors
-- dedicated mode with 1 dedicated process
constant AFUD_0 : std_logic_vector(PSL_AFU_DESC_WIDTH - 1 downto 0) := x"0000_0001_0000_8010";
-- problem state area
constant AFUD_30 : std_logic_vector(PSL_AFU_DESC_WIDTH - 1 downto 0) := x"0100_0000_0000_0000";
----------------------------------------------------------------------------------------------------------------------- psl command
--type psl_command_in is record
-- room : std_logic_vector(PSL_ROOM_WIDTH - 1 downto 0);
--end record;
type psl_command_out is record
valid : std_logic;
tag : unsigned(PSL_TAG_WIDTH - 1 downto 0);
-- tagpar : std_logic;
com : std_logic_vector(PSL_COMMAND_WIDTH - 1 downto 0);
-- compar : std_logic;
-- abt : std_logic_vector(PSL_ABT_WIDTH - 1 downto 0);
ea : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
-- eapar : std_logic;
-- ch : unsigned(PSL_CH_WIDTH - 1 downto 0);
size : unsigned(PSL_SIZE_WIDTH - 1 downto 0);
end record;
----------------------------------------------------------------------------------------------------------------------- psl control
type psl_control_in is record
val : std_logic;
com : std_logic_vector(PSL_JOB_COMMAND_WIDTH - 1 downto 0);
-- compar : std_logic;
ea : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
-- eapar : std_logic;
pclock : std_logic;
end record;
type psl_control_out is record
running : std_logic;
done : std_logic;
-- ack : std_logic;
error : std_logic_vector(PSL_ERROR_WIDTH - 1 downto 0);
-- yield : std_logic;
-- tbreq : std_logic;
-- paren : std_logic;
end record;
----------------------------------------------------------------------------------------------------------------------- psl buffer
type psl_buffer_in is record
rvalid : std_logic;
rtag : unsigned(PSL_TAG_WIDTH - 1 downto 0);
-- rtagpar : std_logic;
rad : unsigned(PSL_HALFLINE_INDEX_WIDTH - 1 downto 0);
wvalid : std_logic;
wtag : unsigned(PSL_TAG_WIDTH - 1 downto 0);
-- wtagpar : std_logic;
wad : unsigned(PSL_HALFLINE_INDEX_WIDTH - 1 downto 0);
wdata : std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
-- wpar : std_logic_vector((PSL_DATA_WIDTH / PSL_DOUBLE_WORD_WIDTH) - 1 downto 0);
end record;
type psl_buffer_out is record
-- rlat : unsigned(PSL_LATENCY_WIDTH - 1 downto 0);
rdata : std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
-- rpar : std_logic_vector((PSL_DATA_WIDTH / PSL_DOUBLE_WORD_WIDTH) - 1 downto 0);
end record;
----------------------------------------------------------------------------------------------------------------------- psl mmio
type psl_mmio_in is record
val : std_logic;
cfg : std_logic;
rnw : std_logic;
dw : std_logic;
ad : unsigned(PSL_MMIO_ADDRESS_WIDTH - 1 downto 0);
-- adpar : std_logic;
data : std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
-- datapar : std_logic;
end record;
type psl_mmio_out is record
ack : std_logic;
data : std_logic_vector(PSL_MMIO_DATA_WIDTH - 1 downto 0);
-- datapar : std_logic;
end record;
----------------------------------------------------------------------------------------------------------------------- psl response
type psl_response_in is record
valid : std_logic;
tag : unsigned(PSL_TAG_WIDTH - 1 downto 0);
-- tagpar : std_logic;
response : std_logic_vector(PSL_RESPONSE_WIDTH - 1 downto 0);
-- credits : unsigned(PSL_CREDITS_WIDTH - 1 downto 0);
-- cachestate : std_logic_vector(PSL_CACHESTATE_WIDTH - 1 downto 0);
-- cachepos : std_logic_vector(PSL_CACHEPOS_WIDTH - 1 downto 0);
end record;
end package psl;
|
bsd-2-clause
|
3a95d339fadb67332eeec22f534db0d1
| 0.449166 | 4.379508 | false | false | false | false |
mitchsm/nvc
|
test/regress/jcore5.vhd
| 3 | 1,214 |
package cpu2j0_pack is
type cpu_debug_o_t is record
ack : bit;
d : bit_vector(31 downto 0);
rdy : bit;
end record;
constant bits_exp : natural := 5;
constant bits : natural := 2**bits_exp;
type bus_val_t is record
en : bit;
d : bit_vector(bits-1 downto 0);
end record;
constant BUS_VAL_RESET : bus_val_t := ('0', (others => '0'));
type ybus_val_pipeline_t is array (2 downto 0) of bus_val_t;
type datapath_reg_t is record
debug_o : cpu_debug_o_t;
ybus_override : ybus_val_pipeline_t;
end record;
constant DATAPATH_RESET : datapath_reg_t := (
debug_o => (ack => '0', d => (others => '0'), rdy => '0'),
ybus_override => (others => BUS_VAL_RESET) );
end package;
-------------------------------------------------------------------------------
entity jcore5 is
end entity;
use work.cpu2j0_pack.all;
architecture test of jcore5 is
signal x : datapath_reg_t := DATAPATH_RESET;
begin
process is
begin
assert x = (
debug_o => (ack => '0', d => (others => '0'), rdy => '0'),
ybus_override => (others => BUS_VAL_RESET) );
wait;
end process;
end architecture;
|
gpl-3.0
|
411558fe0d55961a2d8f094b4f20ba33
| 0.52883 | 3.391061 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_set_0_if_0/sim/zc702_set_0_if_0.vhd
| 1 | 50,762 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axis_accelerator_adapter:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axis_accelerator_adapter_v2_1_6;
USE axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter;
ENTITY zc702_set_0_if_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
interrupt : OUT STD_LOGIC
);
END zc702_set_0_if_0;
ARCHITECTURE zc702_set_0_if_0_arch OF zc702_set_0_if_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_set_0_if_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_accelerator_adapter IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_AP_ADAPTER_ID : INTEGER;
C_N_INPUT_ARGS : INTEGER;
C_N_OUTPUT_ARGS : INTEGER;
C_S_AXIS_TDATA_WIDTH : INTEGER;
C_S_AXIS_TUSER_WIDTH : INTEGER;
C_S_AXIS_TID_WIDTH : INTEGER;
C_S_AXIS_TDEST_WIDTH : INTEGER;
C_AP_IARG_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_IARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_IARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_0_DWIDTH : INTEGER;
C_AP_IARG_1_DWIDTH : INTEGER;
C_AP_IARG_2_DWIDTH : INTEGER;
C_AP_IARG_3_DWIDTH : INTEGER;
C_AP_IARG_4_DWIDTH : INTEGER;
C_AP_IARG_5_DWIDTH : INTEGER;
C_AP_IARG_6_DWIDTH : INTEGER;
C_AP_IARG_7_DWIDTH : INTEGER;
C_M_AXIS_TDATA_WIDTH : INTEGER;
C_M_AXIS_TUSER_WIDTH : INTEGER;
C_M_AXIS_TID_WIDTH : INTEGER;
C_M_AXIS_TDEST_WIDTH : INTEGER;
C_AP_OARG_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_OARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_OARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_0_DWIDTH : INTEGER;
C_AP_OARG_1_DWIDTH : INTEGER;
C_AP_OARG_2_DWIDTH : INTEGER;
C_AP_OARG_3_DWIDTH : INTEGER;
C_AP_OARG_4_DWIDTH : INTEGER;
C_AP_OARG_5_DWIDTH : INTEGER;
C_AP_OARG_6_DWIDTH : INTEGER;
C_AP_OARG_7_DWIDTH : INTEGER;
C_N_INOUT_SCALARS : INTEGER;
C_N_INPUT_SCALARS : INTEGER;
C_INPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_INPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_OUTPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_AP_ISCALAR_DOUT_WIDTH : INTEGER;
C_AP_ISCALAR_IO_DOUT_WIDTH : INTEGER;
C_INPUT_SCALAR_0_WIDTH : INTEGER;
C_INPUT_SCALAR_1_WIDTH : INTEGER;
C_INPUT_SCALAR_2_WIDTH : INTEGER;
C_INPUT_SCALAR_3_WIDTH : INTEGER;
C_INPUT_SCALAR_4_WIDTH : INTEGER;
C_INPUT_SCALAR_5_WIDTH : INTEGER;
C_INPUT_SCALAR_6_WIDTH : INTEGER;
C_INPUT_SCALAR_7_WIDTH : INTEGER;
C_INPUT_SCALAR_8_WIDTH : INTEGER;
C_INPUT_SCALAR_9_WIDTH : INTEGER;
C_INPUT_SCALAR_10_WIDTH : INTEGER;
C_INPUT_SCALAR_11_WIDTH : INTEGER;
C_INPUT_SCALAR_12_WIDTH : INTEGER;
C_INPUT_SCALAR_13_WIDTH : INTEGER;
C_INPUT_SCALAR_14_WIDTH : INTEGER;
C_INPUT_SCALAR_15_WIDTH : INTEGER;
C_OUTPUT_SCALAR_0_WIDTH : INTEGER;
C_OUTPUT_SCALAR_1_WIDTH : INTEGER;
C_OUTPUT_SCALAR_2_WIDTH : INTEGER;
C_OUTPUT_SCALAR_3_WIDTH : INTEGER;
C_OUTPUT_SCALAR_4_WIDTH : INTEGER;
C_OUTPUT_SCALAR_5_WIDTH : INTEGER;
C_OUTPUT_SCALAR_6_WIDTH : INTEGER;
C_OUTPUT_SCALAR_7_WIDTH : INTEGER;
C_OUTPUT_SCALAR_8_WIDTH : INTEGER;
C_OUTPUT_SCALAR_9_WIDTH : INTEGER;
C_OUTPUT_SCALAR_10_WIDTH : INTEGER;
C_OUTPUT_SCALAR_11_WIDTH : INTEGER;
C_OUTPUT_SCALAR_12_WIDTH : INTEGER;
C_OUTPUT_SCALAR_13_WIDTH : INTEGER;
C_OUTPUT_SCALAR_14_WIDTH : INTEGER;
C_OUTPUT_SCALAR_15_WIDTH : INTEGER;
C_N_OUTPUT_SCALARS : INTEGER;
C_OUTPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_AP_OSCALAR_DIN_WIDTH : INTEGER;
C_AP_OSCALAR_IO_DIN_WIDTH : INTEGER;
C_ENABLE_STREAM_CLK : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_S_AXIS_HAS_TSTRB : INTEGER;
C_S_AXIS_HAS_TKEEP : INTEGER;
C_NONE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_aresetn : IN STD_LOGIC;
s_axis_0_aclk : IN STD_LOGIC;
s_axis_0_aresetn : IN STD_LOGIC;
s_axis_0_tvalid : IN STD_LOGIC;
s_axis_0_tready : OUT STD_LOGIC;
s_axis_0_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_0_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tlast : IN STD_LOGIC;
s_axis_0_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_aclk : IN STD_LOGIC;
s_axis_1_aresetn : IN STD_LOGIC;
s_axis_1_tvalid : IN STD_LOGIC;
s_axis_1_tready : OUT STD_LOGIC;
s_axis_1_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_1_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tlast : IN STD_LOGIC;
s_axis_1_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_aclk : IN STD_LOGIC;
s_axis_2_aresetn : IN STD_LOGIC;
s_axis_2_tvalid : IN STD_LOGIC;
s_axis_2_tready : OUT STD_LOGIC;
s_axis_2_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_2_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tlast : IN STD_LOGIC;
s_axis_2_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_aclk : IN STD_LOGIC;
s_axis_3_aresetn : IN STD_LOGIC;
s_axis_3_tvalid : IN STD_LOGIC;
s_axis_3_tready : OUT STD_LOGIC;
s_axis_3_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_3_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tlast : IN STD_LOGIC;
s_axis_3_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_aclk : IN STD_LOGIC;
s_axis_4_aresetn : IN STD_LOGIC;
s_axis_4_tvalid : IN STD_LOGIC;
s_axis_4_tready : OUT STD_LOGIC;
s_axis_4_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_4_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tlast : IN STD_LOGIC;
s_axis_4_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_aclk : IN STD_LOGIC;
s_axis_5_aresetn : IN STD_LOGIC;
s_axis_5_tvalid : IN STD_LOGIC;
s_axis_5_tready : OUT STD_LOGIC;
s_axis_5_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_5_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tlast : IN STD_LOGIC;
s_axis_5_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_aclk : IN STD_LOGIC;
s_axis_6_aresetn : IN STD_LOGIC;
s_axis_6_tvalid : IN STD_LOGIC;
s_axis_6_tready : OUT STD_LOGIC;
s_axis_6_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_6_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tlast : IN STD_LOGIC;
s_axis_6_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_aclk : IN STD_LOGIC;
s_axis_7_aresetn : IN STD_LOGIC;
s_axis_7_tvalid : IN STD_LOGIC;
s_axis_7_tready : OUT STD_LOGIC;
s_axis_7_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_7_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tlast : IN STD_LOGIC;
s_axis_7_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_iarg_0_clk : IN STD_LOGIC;
ap_iarg_0_rst : IN STD_LOGIC;
ap_iarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_ce : IN STD_LOGIC;
ap_iarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_clk : IN STD_LOGIC;
ap_iarg_1_rst : IN STD_LOGIC;
ap_iarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_ce : IN STD_LOGIC;
ap_iarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_clk : IN STD_LOGIC;
ap_iarg_2_rst : IN STD_LOGIC;
ap_iarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_ce : IN STD_LOGIC;
ap_iarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_clk : IN STD_LOGIC;
ap_iarg_3_rst : IN STD_LOGIC;
ap_iarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_ce : IN STD_LOGIC;
ap_iarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_clk : IN STD_LOGIC;
ap_iarg_4_rst : IN STD_LOGIC;
ap_iarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_ce : IN STD_LOGIC;
ap_iarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_clk : IN STD_LOGIC;
ap_iarg_5_rst : IN STD_LOGIC;
ap_iarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_ce : IN STD_LOGIC;
ap_iarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_clk : IN STD_LOGIC;
ap_iarg_6_rst : IN STD_LOGIC;
ap_iarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_ce : IN STD_LOGIC;
ap_iarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_clk : IN STD_LOGIC;
ap_iarg_7_rst : IN STD_LOGIC;
ap_iarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_ce : IN STD_LOGIC;
ap_iarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_read : IN STD_LOGIC;
ap_fifo_iarg_0_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_1_read : IN STD_LOGIC;
ap_fifo_iarg_1_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_2_read : IN STD_LOGIC;
ap_fifo_iarg_2_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_3_read : IN STD_LOGIC;
ap_fifo_iarg_3_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_4_read : IN STD_LOGIC;
ap_fifo_iarg_4_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_5_read : IN STD_LOGIC;
ap_fifo_iarg_5_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_6_read : IN STD_LOGIC;
ap_fifo_iarg_6_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_7_read : IN STD_LOGIC;
ap_fifo_iarg_7_empty_n : OUT STD_LOGIC;
m_axis_aclk : IN STD_LOGIC;
m_axis_aresetn : IN STD_LOGIC;
m_axis_0_aclk : IN STD_LOGIC;
m_axis_0_aresetn : IN STD_LOGIC;
m_axis_0_tvalid : OUT STD_LOGIC;
m_axis_0_tready : IN STD_LOGIC;
m_axis_0_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_0_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tlast : OUT STD_LOGIC;
m_axis_0_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_aclk : IN STD_LOGIC;
m_axis_1_aresetn : IN STD_LOGIC;
m_axis_1_tvalid : OUT STD_LOGIC;
m_axis_1_tready : IN STD_LOGIC;
m_axis_1_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_1_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tlast : OUT STD_LOGIC;
m_axis_1_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_aclk : IN STD_LOGIC;
m_axis_2_aresetn : IN STD_LOGIC;
m_axis_2_tvalid : OUT STD_LOGIC;
m_axis_2_tready : IN STD_LOGIC;
m_axis_2_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_2_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tlast : OUT STD_LOGIC;
m_axis_2_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_aclk : IN STD_LOGIC;
m_axis_3_aresetn : IN STD_LOGIC;
m_axis_3_tvalid : OUT STD_LOGIC;
m_axis_3_tready : IN STD_LOGIC;
m_axis_3_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_3_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tlast : OUT STD_LOGIC;
m_axis_3_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_aclk : IN STD_LOGIC;
m_axis_4_aresetn : IN STD_LOGIC;
m_axis_4_tvalid : OUT STD_LOGIC;
m_axis_4_tready : IN STD_LOGIC;
m_axis_4_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_4_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tlast : OUT STD_LOGIC;
m_axis_4_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_aclk : IN STD_LOGIC;
m_axis_5_aresetn : IN STD_LOGIC;
m_axis_5_tvalid : OUT STD_LOGIC;
m_axis_5_tready : IN STD_LOGIC;
m_axis_5_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_5_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tlast : OUT STD_LOGIC;
m_axis_5_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_aclk : IN STD_LOGIC;
m_axis_6_aresetn : IN STD_LOGIC;
m_axis_6_tvalid : OUT STD_LOGIC;
m_axis_6_tready : IN STD_LOGIC;
m_axis_6_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_6_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tlast : OUT STD_LOGIC;
m_axis_6_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_aclk : IN STD_LOGIC;
m_axis_7_aresetn : IN STD_LOGIC;
m_axis_7_tvalid : OUT STD_LOGIC;
m_axis_7_tready : IN STD_LOGIC;
m_axis_7_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_7_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tlast : OUT STD_LOGIC;
m_axis_7_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_oarg_0_clk : IN STD_LOGIC;
ap_oarg_0_rst : IN STD_LOGIC;
ap_oarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_ce : IN STD_LOGIC;
ap_oarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_clk : IN STD_LOGIC;
ap_oarg_1_rst : IN STD_LOGIC;
ap_oarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_ce : IN STD_LOGIC;
ap_oarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_clk : IN STD_LOGIC;
ap_oarg_2_rst : IN STD_LOGIC;
ap_oarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_ce : IN STD_LOGIC;
ap_oarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_clk : IN STD_LOGIC;
ap_oarg_3_rst : IN STD_LOGIC;
ap_oarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_ce : IN STD_LOGIC;
ap_oarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_clk : IN STD_LOGIC;
ap_oarg_4_rst : IN STD_LOGIC;
ap_oarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_ce : IN STD_LOGIC;
ap_oarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_clk : IN STD_LOGIC;
ap_oarg_5_rst : IN STD_LOGIC;
ap_oarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_ce : IN STD_LOGIC;
ap_oarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_clk : IN STD_LOGIC;
ap_oarg_6_rst : IN STD_LOGIC;
ap_oarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_ce : IN STD_LOGIC;
ap_oarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_clk : IN STD_LOGIC;
ap_oarg_7_rst : IN STD_LOGIC;
ap_oarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_ce : IN STD_LOGIC;
ap_oarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_write : IN STD_LOGIC;
ap_fifo_oarg_0_full_n : OUT STD_LOGIC;
ap_fifo_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_1_write : IN STD_LOGIC;
ap_fifo_oarg_1_full_n : OUT STD_LOGIC;
ap_fifo_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_2_write : IN STD_LOGIC;
ap_fifo_oarg_2_full_n : OUT STD_LOGIC;
ap_fifo_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_3_write : IN STD_LOGIC;
ap_fifo_oarg_3_full_n : OUT STD_LOGIC;
ap_fifo_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_4_write : IN STD_LOGIC;
ap_fifo_oarg_4_full_n : OUT STD_LOGIC;
ap_fifo_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_5_write : IN STD_LOGIC;
ap_fifo_oarg_5_full_n : OUT STD_LOGIC;
ap_fifo_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_6_write : IN STD_LOGIC;
ap_fifo_oarg_6_full_n : OUT STD_LOGIC;
ap_fifo_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_7_write : IN STD_LOGIC;
ap_fifo_oarg_7_full_n : OUT STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_8_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_9_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_10_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_11_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_12_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_13_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_14_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_15_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_8_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_9_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_10_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_11_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_12_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_13_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_14_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_15_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_vld : IN STD_LOGIC;
ap_oscalar_1_vld : IN STD_LOGIC;
ap_oscalar_2_vld : IN STD_LOGIC;
ap_oscalar_3_vld : IN STD_LOGIC;
ap_oscalar_4_vld : IN STD_LOGIC;
ap_oscalar_5_vld : IN STD_LOGIC;
ap_oscalar_6_vld : IN STD_LOGIC;
ap_oscalar_7_vld : IN STD_LOGIC;
ap_oscalar_8_vld : IN STD_LOGIC;
ap_oscalar_9_vld : IN STD_LOGIC;
ap_oscalar_10_vld : IN STD_LOGIC;
ap_oscalar_11_vld : IN STD_LOGIC;
ap_oscalar_12_vld : IN STD_LOGIC;
ap_oscalar_13_vld : IN STD_LOGIC;
ap_oscalar_14_vld : IN STD_LOGIC;
ap_oscalar_15_vld : IN STD_LOGIC;
ap_oscalar_0_ack : OUT STD_LOGIC;
ap_oscalar_1_ack : OUT STD_LOGIC;
ap_oscalar_2_ack : OUT STD_LOGIC;
ap_oscalar_3_ack : OUT STD_LOGIC;
ap_oscalar_4_ack : OUT STD_LOGIC;
ap_oscalar_5_ack : OUT STD_LOGIC;
ap_oscalar_6_ack : OUT STD_LOGIC;
ap_oscalar_7_ack : OUT STD_LOGIC;
ap_oscalar_8_ack : OUT STD_LOGIC;
ap_oscalar_9_ack : OUT STD_LOGIC;
ap_oscalar_10_ack : OUT STD_LOGIC;
ap_oscalar_11_ack : OUT STD_LOGIC;
ap_oscalar_12_ack : OUT STD_LOGIC;
ap_oscalar_13_ack : OUT STD_LOGIC;
ap_oscalar_14_ack : OUT STD_LOGIC;
ap_oscalar_15_ack : OUT STD_LOGIC;
ap_iscalar_0_ack : IN STD_LOGIC;
ap_iscalar_1_ack : IN STD_LOGIC;
ap_iscalar_2_ack : IN STD_LOGIC;
ap_iscalar_3_ack : IN STD_LOGIC;
ap_iscalar_4_ack : IN STD_LOGIC;
ap_iscalar_5_ack : IN STD_LOGIC;
ap_iscalar_6_ack : IN STD_LOGIC;
ap_iscalar_7_ack : IN STD_LOGIC;
ap_iscalar_8_ack : IN STD_LOGIC;
ap_iscalar_9_ack : IN STD_LOGIC;
ap_iscalar_10_ack : IN STD_LOGIC;
ap_iscalar_11_ack : IN STD_LOGIC;
ap_iscalar_12_ack : IN STD_LOGIC;
ap_iscalar_13_ack : IN STD_LOGIC;
ap_iscalar_14_ack : IN STD_LOGIC;
ap_iscalar_15_ack : IN STD_LOGIC;
ap_iscalar_0_vld : OUT STD_LOGIC;
ap_iscalar_1_vld : OUT STD_LOGIC;
ap_iscalar_2_vld : OUT STD_LOGIC;
ap_iscalar_3_vld : OUT STD_LOGIC;
ap_iscalar_4_vld : OUT STD_LOGIC;
ap_iscalar_5_vld : OUT STD_LOGIC;
ap_iscalar_6_vld : OUT STD_LOGIC;
ap_iscalar_7_vld : OUT STD_LOGIC;
ap_iscalar_8_vld : OUT STD_LOGIC;
ap_iscalar_9_vld : OUT STD_LOGIC;
ap_iscalar_10_vld : OUT STD_LOGIC;
ap_iscalar_11_vld : OUT STD_LOGIC;
ap_iscalar_12_vld : OUT STD_LOGIC;
ap_iscalar_13_vld : OUT STD_LOGIC;
ap_iscalar_14_vld : OUT STD_LOGIC;
ap_iscalar_15_vld : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END COMPONENT axis_accelerator_adapter;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ap_start: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL start";
ATTRIBUTE X_INTERFACE_INFO OF ap_ready: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL ready";
ATTRIBUTE X_INTERFACE_INFO OF ap_done: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done";
ATTRIBUTE X_INTERFACE_INFO OF ap_continue: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL continue";
ATTRIBUTE X_INTERFACE_INFO OF ap_idle: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL idle";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axis_accelerator_adapter
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_AP_ADAPTER_ID => 1,
C_N_INPUT_ARGS => 0,
C_N_OUTPUT_ARGS => 0,
C_S_AXIS_TDATA_WIDTH => 64,
C_S_AXIS_TUSER_WIDTH => 8,
C_S_AXIS_TID_WIDTH => 4,
C_S_AXIS_TDEST_WIDTH => 4,
C_AP_IARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_IARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_IARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_IARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_0_DWIDTH => 32,
C_AP_IARG_1_DWIDTH => 32,
C_AP_IARG_2_DWIDTH => 32,
C_AP_IARG_3_DWIDTH => 32,
C_AP_IARG_4_DWIDTH => 32,
C_AP_IARG_5_DWIDTH => 32,
C_AP_IARG_6_DWIDTH => 32,
C_AP_IARG_7_DWIDTH => 32,
C_M_AXIS_TDATA_WIDTH => 64,
C_M_AXIS_TUSER_WIDTH => 8,
C_M_AXIS_TID_WIDTH => 4,
C_M_AXIS_TDEST_WIDTH => 4,
C_AP_OARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_OARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_OARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_DIM => X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008",
C_AP_OARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_OARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_0_DWIDTH => 32,
C_AP_OARG_1_DWIDTH => 32,
C_AP_OARG_2_DWIDTH => 32,
C_AP_OARG_3_DWIDTH => 32,
C_AP_OARG_4_DWIDTH => 32,
C_AP_OARG_5_DWIDTH => 32,
C_AP_OARG_6_DWIDTH => 32,
C_AP_OARG_7_DWIDTH => 32,
C_N_INOUT_SCALARS => 0,
C_N_INPUT_SCALARS => 3,
C_INPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_INPUT_SCALAR_MODE => X"0000000000000000",
C_OUTPUT_SCALAR_MODE => X"0000000000000000",
C_AP_ISCALAR_DOUT_WIDTH => 96,
C_AP_ISCALAR_IO_DOUT_WIDTH => 32,
C_INPUT_SCALAR_0_WIDTH => 32,
C_INPUT_SCALAR_1_WIDTH => 32,
C_INPUT_SCALAR_2_WIDTH => 32,
C_INPUT_SCALAR_3_WIDTH => 32,
C_INPUT_SCALAR_4_WIDTH => 32,
C_INPUT_SCALAR_5_WIDTH => 32,
C_INPUT_SCALAR_6_WIDTH => 32,
C_INPUT_SCALAR_7_WIDTH => 32,
C_INPUT_SCALAR_8_WIDTH => 32,
C_INPUT_SCALAR_9_WIDTH => 32,
C_INPUT_SCALAR_10_WIDTH => 32,
C_INPUT_SCALAR_11_WIDTH => 32,
C_INPUT_SCALAR_12_WIDTH => 32,
C_INPUT_SCALAR_13_WIDTH => 32,
C_INPUT_SCALAR_14_WIDTH => 32,
C_INPUT_SCALAR_15_WIDTH => 32,
C_OUTPUT_SCALAR_0_WIDTH => 32,
C_OUTPUT_SCALAR_1_WIDTH => 32,
C_OUTPUT_SCALAR_2_WIDTH => 32,
C_OUTPUT_SCALAR_3_WIDTH => 32,
C_OUTPUT_SCALAR_4_WIDTH => 32,
C_OUTPUT_SCALAR_5_WIDTH => 32,
C_OUTPUT_SCALAR_6_WIDTH => 32,
C_OUTPUT_SCALAR_7_WIDTH => 32,
C_OUTPUT_SCALAR_8_WIDTH => 32,
C_OUTPUT_SCALAR_9_WIDTH => 32,
C_OUTPUT_SCALAR_10_WIDTH => 32,
C_OUTPUT_SCALAR_11_WIDTH => 32,
C_OUTPUT_SCALAR_12_WIDTH => 32,
C_OUTPUT_SCALAR_13_WIDTH => 32,
C_OUTPUT_SCALAR_14_WIDTH => 32,
C_OUTPUT_SCALAR_15_WIDTH => 32,
C_N_OUTPUT_SCALARS => 1,
C_OUTPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_AP_OSCALAR_DIN_WIDTH => 32,
C_AP_OSCALAR_IO_DIN_WIDTH => 32,
C_ENABLE_STREAM_CLK => 0,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_S_AXIS_HAS_TSTRB => 0,
C_S_AXIS_HAS_TKEEP => 0,
C_NONE => 2
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axis_aclk => '0',
s_axis_aresetn => '0',
s_axis_0_aclk => '0',
s_axis_0_aresetn => '0',
s_axis_0_tvalid => '0',
s_axis_0_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_0_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tlast => '0',
s_axis_0_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_aclk => '0',
s_axis_1_aresetn => '0',
s_axis_1_tvalid => '0',
s_axis_1_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_1_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tlast => '0',
s_axis_1_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_aclk => '0',
s_axis_2_aresetn => '0',
s_axis_2_tvalid => '0',
s_axis_2_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_2_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tlast => '0',
s_axis_2_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_aclk => '0',
s_axis_3_aresetn => '0',
s_axis_3_tvalid => '0',
s_axis_3_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_3_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tlast => '0',
s_axis_3_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_aclk => '0',
s_axis_4_aresetn => '0',
s_axis_4_tvalid => '0',
s_axis_4_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_4_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tlast => '0',
s_axis_4_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_aclk => '0',
s_axis_5_aresetn => '0',
s_axis_5_tvalid => '0',
s_axis_5_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_5_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tlast => '0',
s_axis_5_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_aclk => '0',
s_axis_6_aresetn => '0',
s_axis_6_tvalid => '0',
s_axis_6_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_6_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tlast => '0',
s_axis_6_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_aclk => '0',
s_axis_7_aresetn => '0',
s_axis_7_tvalid => '0',
s_axis_7_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_7_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tlast => '0',
s_axis_7_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
ap_iarg_0_clk => '0',
ap_iarg_0_rst => '0',
ap_iarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_0_ce => '0',
ap_iarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_clk => '0',
ap_iarg_1_rst => '0',
ap_iarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_ce => '0',
ap_iarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_clk => '0',
ap_iarg_2_rst => '0',
ap_iarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_ce => '0',
ap_iarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_clk => '0',
ap_iarg_3_rst => '0',
ap_iarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_ce => '0',
ap_iarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_clk => '0',
ap_iarg_4_rst => '0',
ap_iarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_ce => '0',
ap_iarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_clk => '0',
ap_iarg_5_rst => '0',
ap_iarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_ce => '0',
ap_iarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_clk => '0',
ap_iarg_6_rst => '0',
ap_iarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_ce => '0',
ap_iarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_clk => '0',
ap_iarg_7_rst => '0',
ap_iarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_ce => '0',
ap_iarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_iarg_0_read => '0',
ap_fifo_iarg_1_read => '0',
ap_fifo_iarg_2_read => '0',
ap_fifo_iarg_3_read => '0',
ap_fifo_iarg_4_read => '0',
ap_fifo_iarg_5_read => '0',
ap_fifo_iarg_6_read => '0',
ap_fifo_iarg_7_read => '0',
m_axis_aclk => '0',
m_axis_aresetn => '0',
m_axis_0_aclk => '0',
m_axis_0_aresetn => '0',
m_axis_0_tready => '0',
m_axis_1_aclk => '0',
m_axis_1_aresetn => '0',
m_axis_1_tready => '0',
m_axis_2_aclk => '0',
m_axis_2_aresetn => '0',
m_axis_2_tready => '0',
m_axis_3_aclk => '0',
m_axis_3_aresetn => '0',
m_axis_3_tready => '0',
m_axis_4_aclk => '0',
m_axis_4_aresetn => '0',
m_axis_4_tready => '0',
m_axis_5_aclk => '0',
m_axis_5_aresetn => '0',
m_axis_5_tready => '0',
m_axis_6_aclk => '0',
m_axis_6_aresetn => '0',
m_axis_6_tready => '0',
m_axis_7_aclk => '0',
m_axis_7_aresetn => '0',
m_axis_7_tready => '0',
ap_oarg_0_clk => '0',
ap_oarg_0_rst => '0',
ap_oarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_0_ce => '0',
ap_oarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_clk => '0',
ap_oarg_1_rst => '0',
ap_oarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_ce => '0',
ap_oarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_clk => '0',
ap_oarg_2_rst => '0',
ap_oarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_ce => '0',
ap_oarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_clk => '0',
ap_oarg_3_rst => '0',
ap_oarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_ce => '0',
ap_oarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_clk => '0',
ap_oarg_4_rst => '0',
ap_oarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_ce => '0',
ap_oarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_clk => '0',
ap_oarg_5_rst => '0',
ap_oarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_ce => '0',
ap_oarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_clk => '0',
ap_oarg_6_rst => '0',
ap_oarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_ce => '0',
ap_oarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_clk => '0',
ap_oarg_7_rst => '0',
ap_oarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_ce => '0',
ap_oarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_write => '0',
ap_fifo_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_1_write => '0',
ap_fifo_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_2_write => '0',
ap_fifo_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_3_write => '0',
ap_fifo_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_4_write => '0',
ap_fifo_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_5_write => '0',
ap_fifo_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_6_write => '0',
ap_fifo_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_7_write => '0',
aclk => aclk,
aresetn => aresetn,
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
ap_iscalar_0_dout => ap_iscalar_0_dout,
ap_iscalar_1_dout => ap_iscalar_1_dout,
ap_iscalar_2_dout => ap_iscalar_2_dout,
ap_oscalar_0_din => ap_oscalar_0_din,
ap_oscalar_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_8_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_9_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_10_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_11_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_12_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_13_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_14_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_15_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_0_vld => '0',
ap_oscalar_1_vld => '0',
ap_oscalar_2_vld => '0',
ap_oscalar_3_vld => '0',
ap_oscalar_4_vld => '0',
ap_oscalar_5_vld => '0',
ap_oscalar_6_vld => '0',
ap_oscalar_7_vld => '0',
ap_oscalar_8_vld => '0',
ap_oscalar_9_vld => '0',
ap_oscalar_10_vld => '0',
ap_oscalar_11_vld => '0',
ap_oscalar_12_vld => '0',
ap_oscalar_13_vld => '0',
ap_oscalar_14_vld => '0',
ap_oscalar_15_vld => '0',
ap_iscalar_0_ack => '0',
ap_iscalar_1_ack => '0',
ap_iscalar_2_ack => '0',
ap_iscalar_3_ack => '0',
ap_iscalar_4_ack => '0',
ap_iscalar_5_ack => '0',
ap_iscalar_6_ack => '0',
ap_iscalar_7_ack => '0',
ap_iscalar_8_ack => '0',
ap_iscalar_9_ack => '0',
ap_iscalar_10_ack => '0',
ap_iscalar_11_ack => '0',
ap_iscalar_12_ack => '0',
ap_iscalar_13_ack => '0',
ap_iscalar_14_ack => '0',
ap_iscalar_15_ack => '0',
interrupt => interrupt
);
END zc702_set_0_if_0_arch;
|
mit
|
81d2851cfe3e22c0f4d64af9b86f50c9
| 0.6168 | 2.905833 | false | false | false | false |
mitchsm/nvc
|
test/parse/conc.vhd
| 4 | 277 |
architecture a of e is
begin
x <= a or b;
x <= 1 when foo
else 2 when bar
else 3;
with y select x <=
1 when a,
2 when b,
3 when others;
pcall(x, y);
assert x = 5;
(a, b) <= c;
xxx;
end architecture;
|
gpl-3.0
|
7b107ec21931842d61cfb4481378b206
| 0.451264 | 3.419753 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter4.vhd
| 1 | 4,338 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter4.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter4 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_counter4;
ARCHITECTURE SYN OF lpm_counter4 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(1 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 2
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
35866dc94368156fa6acad8c9c796f47
| 0.650761 | 3.69821 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_proc_sys_reset_2_1/sim/zc702_proc_sys_reset_2_1.vhd
| 1 | 5,843 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_2_1 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_2_1;
ARCHITECTURE zc702_proc_sys_reset_2_1_arch OF zc702_proc_sys_reset_2_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_2_1_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_2_1_arch;
|
mit
|
9a1ced834256cd8b966f11033e7ba0c6
| 0.706144 | 3.575887 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare10.vhd
| 1 | 4,246 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare10.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare10 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare10;
ARCHITECTURE SYN OF lpm_compare10 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END COMPONENT;
BEGIN
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 24
)
PORT MAP (
dataa => dataa,
datab => datab,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "24"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 24 0 INPUT NODEFVAL "dataa[23..0]"
-- Retrieval info: USED_PORT: datab 0 0 24 0 INPUT NODEFVAL "datab[23..0]"
-- Retrieval info: CONNECT: @dataa 0 0 24 0 dataa 0 0 24 0
-- Retrieval info: CONNECT: @datab 0 0 24 0 datab 0 0 24 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
953d6d0e9c4dadbc3288d4ded357f345
| 0.655205 | 3.808072 | false | false | false | false |
mitchsm/nvc
|
test/bounds/case.vhd
| 2 | 3,133 |
entity bounds_case is
end entity;
architecture test of bounds_case is
begin
process is
type letter is (A, B, C);
subtype ab is letter range B to letter'right;
variable l : letter;
variable m : ab;
begin
case l is -- Choice C not covered
when a =>
null;
when b =>
null;
end case;
case m is -- Choice B not covered
when c =>
null;
end case;
wait;
end process;
process is
variable x : integer;
variable y : natural;
begin
case x is -- Missing range
when 0 to 9 =>
null;
when 20 =>
null;
end case;
case x is -- Missing range
when 1 | 2 | 3 =>
null;
end case;
case x is -- OK
when others =>
null;
end case;
case x is -- Missing integer'right
when integer'left to integer'right - 1 =>
null;
end case;
case x is
when 1 to 100 =>
null;
when 50 => -- Duplicate
null;
when 60 to 64 => -- Duplicate
null;
when others =>
null;
end case;
case y is
when -1 => -- Out of range
null;
end case;
end process;
process is
variable x : bit_vector(1 to 3);
variable y : bit_vector(0 to 0);
subtype small is character range 'a' to 'k';
type char_vector is array (integer range <>) of character;
type small_vector is array (integer range <>) of small;
variable p : char_vector(1 to 2);
variable q : small_vector(1 to 2);
begin
case y is
when "0" =>
null;
when "1" =>
null;
end case; -- OK
case x is
when "000" | "001" =>
null;
end case; -- Missing 6 values
case x is
when ('0', '1') => -- Too few values
null;
when ('1', '0', '1', '1') => -- Too many values
null;
when "10" => -- Too few values
null;
when "1111" => -- Too many values
null;
when others =>
null;
end case;
case p is
when ('0', '1') =>
null;
when ('1', '1') =>
null;
end case; -- Missing lots of values
case q is
when ('0', '1') =>
null;
when ('1', '1') =>
null;
end case; -- Missing 98 values
end process;
end architecture;
|
gpl-3.0
|
30c82646748911b44bab772a4acc2275
| 0.369614 | 5.061389 | false | false | false | false |
mitchsm/nvc
|
test/regress/logical1.vhd
| 5 | 1,071 |
entity logical1 is
end entity;
architecture test of logical1 is
signal x : bit;
begin
process is
begin
x <= '0';
wait for 1 ns;
assert (x and '0') = '0';
assert (x and '1') = '0';
assert (x or '0') = '0';
assert (x or '1') = '1';
assert (x xor '0') = '0';
assert (x xor '1') = '1';
assert (x xnor '0') = '1';
assert (x xnor '1') = '0';
assert (x nand '0') = '1';
assert (x nand '1') = '1';
assert (x nor '0') = '1';
assert (x nor '1') = '0';
x <= '1';
wait for 1 ns;
assert (x and '0') = '0';
assert (x and '1') = '1';
assert (x or '0') = '1';
assert (x or '1') = '1';
assert (x xor '0') = '1';
assert (x xor '1') = '0';
assert (x xnor '0') = '0';
assert (x xnor '1') = '1';
assert (x nand '0') = '1';
assert (x nand '1') = '0';
assert (x nor '0') = '0';
assert (x nor '1') = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
142cf9be1679f919b4ac0c6b13207f02
| 0.398693 | 3.025424 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/connport/inst_e_e-rtl-a.vhd
| 1 | 6,062 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.1 2006/04/10 15:42:05 wig Exp $
-- $Date: 2006/04/10 15:42:05 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:05 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_ea_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ea_e
p_mix_unsplice_a1_125_0_gi : in std_ulogic_vector(125 downto 0);
p_mix_unsplice_a1_127_127_gi : in std_ulogic;
p_mix_unsplice_a2_all128_127_0_gi : in std_ulogic_vector(127 downto 0);
p_mix_unsplice_a3_up100_100_0_gi : in std_ulogic_vector(100 downto 0);
p_mix_unsplice_a4_mid100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_a5_midp100_99_2_gi : in std_ulogic_vector(97 downto 0);
p_mix_unsplice_bad_a_1_1_gi : in std_ulogic;
p_mix_unsplice_bad_b_1_0_gi : in std_ulogic_vector(1 downto 0)
-- End of Generated Port for Entity inst_ea_e
);
end component;
-- ---------
component inst_eb_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ec_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ed_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ee_e
-- No Generated Generics
-- Generated Generics for Entity inst_ee_e
-- End of Generated Generics for Entity inst_ee_e
-- No Generated Port
end component;
-- ---------
component inst_ef_e
-- No Generated Generics
-- Generated Generics for Entity inst_ef_e
-- End of Generated Generics for Entity inst_ef_e
-- No Generated Port
end component;
-- ---------
component inst_eg_e
-- No Generated Generics
-- Generated Generics for Entity inst_eg_e
-- End of Generated Generics for Entity inst_eg_e
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal unsplice_a1 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a2_all128 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a3_up100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a4_mid100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_a5_midp100 : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_a : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal unsplice_bad_b : std_ulogic_vector(127 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
unsplice_a1(127) <= p_mix_unsplice_a1_127_127_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_a1(125 downto 0) <= p_mix_unsplice_a1_125_0_gi(125 downto 0); -- __I_I_SLICE_PORT
unsplice_a2_all128 <= p_mix_unsplice_a2_all128_127_0_gi; -- __I_I_BUS_PORT
unsplice_a3_up100(100 downto 0) <= p_mix_unsplice_a3_up100_100_0_gi(100 downto 0); -- __I_I_SLICE_PORT
unsplice_a4_mid100(99 downto 2) <= p_mix_unsplice_a4_mid100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_a5_midp100(99 downto 2) <= p_mix_unsplice_a5_midp100_99_2_gi(97 downto 0); -- __I_I_SLICE_PORT
unsplice_bad_a(1) <= p_mix_unsplice_bad_a_1_1_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
unsplice_bad_b(1 downto 0) <= p_mix_unsplice_bad_b_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
port map (
p_mix_unsplice_a1_125_0_gi => unsplice_a1(125 downto 0), -- leaves 3 unconnected
p_mix_unsplice_a1_127_127_gi => unsplice_a1(127), -- leaves 3 unconnected
p_mix_unsplice_a2_all128_127_0_gi => unsplice_a2_all128, -- full 128 bit port
p_mix_unsplice_a3_up100_100_0_gi => unsplice_a3_up100(100 downto 0), -- connect 100 bits from 0
p_mix_unsplice_a4_mid100_99_2_gi => unsplice_a4_mid100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_a5_midp100_99_2_gi => unsplice_a5_midp100(99 downto 2), -- connect mid 100 bits
p_mix_unsplice_bad_a_1_1_gi => unsplice_bad_a(1),
p_mix_unsplice_bad_b_1_0_gi => unsplice_bad_b(1 downto 0) -- # conflict
);
-- End of Generated Instance Port Map for inst_ea
-- Generated Instance Port Map for inst_eb
inst_eb: inst_eb_e
;
-- End of Generated Instance Port Map for inst_eb
-- Generated Instance Port Map for inst_ec
inst_ec: inst_ec_e
;
-- End of Generated Instance Port Map for inst_ec
-- Generated Instance Port Map for inst_ed
inst_ed: inst_ed_e
;
-- End of Generated Instance Port Map for inst_ed
-- Generated Instance Port Map for inst_ee
inst_ee: inst_ee_e
;
-- End of Generated Instance Port Map for inst_ee
-- Generated Instance Port Map for inst_ef
inst_ef: inst_ef_e
;
-- End of Generated Instance Port Map for inst_ef
-- Generated Instance Port Map for inst_eg
inst_eg: inst_eg_e
;
-- End of Generated Instance Port Map for inst_eg
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
ddf903d15e43270be41caa76d596e94d
| 0.640878 | 2.863486 | false | false | false | false |
mitchsm/nvc
|
test/elab/const1.vhd
| 5 | 954 |
entity pwm is
generic (
CLK_FREQ : real;
PWM_FREQ : real );
end entity;
architecture rtl of pwm is
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
constant DIVIDE : integer := integer(CLK_FREQ / PWM_FREQ);
constant BITS : integer := log2(DIVIDE);
signal ctr_r : bit_vector(BITS - 1 downto 0) := (others => '0');
begin
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
begin
pwm_1: entity work.pwm
generic map (
CLK_FREQ => 24.0e6,
PWM_FREQ => 1.0e3 );
end architecture;
|
gpl-3.0
|
b1016e7745294234c35f42cb7bb762ba
| 0.471698 | 4.112069 | false | false | false | false |
mitchsm/nvc
|
test/regress/func10.vhd
| 5 | 817 |
entity func10 is
end entity;
architecture test of func10 is
type int3d is array (natural range <>,
natural range <>,
natural range <>) of integer;
function func1(x, y, z : in integer) return integer is
variable r : int3d(1 to x, 1 to y, 1 to z);
begin
for i in 1 to x loop
for j in 1 to y loop
for k in 1 to z loop
r(i, j, k) := i + j + k;
end loop;
end loop;
end loop;
return r(x / 2, y / 2, z / 2);
end function;
begin
process is
variable x, y, z : integer;
begin
x := 4;
y := 5;
z := 6;
wait for 1 ns;
assert func1(x, y, z) = 7;
wait;
end process;
end architecture;
|
gpl-3.0
|
3aff12de87a3e9a5d145382ce0ff7b79
| 0.455324 | 3.8 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_counter3.vhd
| 1 | 4,338 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter3 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END lpm_counter3;
ARCHITECTURE SYN OF lpm_counter3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(5 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 6
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 6 0 @q 0 0 6 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
a958aa7f3d8dd77059a1126376f51a9b
| 0.650761 | 3.69821 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/inst_ec_e-rtl-a.vhd
| 1 | 4,067 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ec_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-rtl-a.vhd,v 1.4 2006/09/25 09:49:31 wig Exp $
-- $Date: 2006/09/25 09:49:31 $
-- $Log: inst_ec_e-rtl-a.vhd,v $
-- Revision 1.4 2006/09/25 09:49:31 wig
-- Update testcase repository.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_ec_e
--
architecture rtl of inst_ec_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eca_e
-- No Generated Generics
-- Generated Generics for Entity inst_eca_e
-- End of Generated Generics for Entity inst_eca_e
port (
-- Generated Port for Entity inst_eca_e
c_add : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0); -- CPUinterface
v_select : in std_ulogic_vector(5 downto 0) -- RequestBusinterface:RequestBus#6(VPU)
-- End of Generated Port for Entity inst_eca_e
);
end component;
-- ---------
component inst_ecb_e
-- No Generated Generics
-- Generated Generics for Entity inst_ecb_e
-- End of Generated Generics for Entity inst_ecb_e
port (
-- Generated Port for Entity inst_ecb_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ecb_e
);
end component;
-- ---------
component inst_ecc_e
-- No Generated Generics
-- Generated Generics for Entity inst_ecc_e
-- End of Generated Generics for Entity inst_ecc_e
port (
-- Generated Port for Entity inst_ecc_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0) -- CPUInterface
-- End of Generated Port for Entity inst_ecc_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
v_select(5) <= p_mix_v_select_5_5_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
v_select(2) <= p_mix_v_select_2_2_gi; -- __I_I_SLICE_PORT -- __W_SINGLE_BIT_SLICE
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eca
inst_eca: inst_eca_e
port map (
c_add => c_addr,
c_bus_in => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
v_select => v_select -- RequestBusinterface:RequestBus#6(VPU)VPUinterface
);
-- End of Generated Instance Port Map for inst_eca
-- Generated Instance Port Map for inst_ecb
inst_ecb: inst_ecb_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ecb
-- Generated Instance Port Map for inst_ecc
inst_ecc: inst_ecc_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ecc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
7a84e34019075ae4a186f747474a73e9
| 0.632899 | 3.028295 | false | false | false | false |
blutsvente/MIX
|
test/results/verilog/vhdl/ent_t-rtl-a.vhd
| 1 | 5,093 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a --
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic;
port_o_a : out std_ulogic;
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0);
sig_i_a2 : in std_ulogic;
sig_o_a2 : out std_ulogic
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b --
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic;
port_b_3 : in std_ulogic;
port_b_4 : out std_ulogic;
port_b_5_1 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0);
port_b_6o : out std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
456a9cc281c64c22f02229e7fea7a4d7
| 0.615158 | 2.78154 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_compare4.vhd
| 2 | 4,435 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare4.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare4 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare4;
ARCHITECTURE SYN OF lpm_compare4 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "000001100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "12"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 12 0 0 9 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
fe26100e3a940ce6925febe2ea89d4d7
| 0.655242 | 3.692756 | false | false | false | false |
blutsvente/MIX
|
test/results/constant/inst_a_e-rtl-a.vhd
| 1 | 15,954 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_aa_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
bit_vector_p : in bit_vector(7 downto 0);
bug20040329a_t1 : in std_ulogic;
bug20040329a_t2 : in std_ulogic;
bug20040329a_t3 : in std_ulogic;
bug20040329a_t4 : in std_ulogic;
bus20040728_all_i : in std_ulogic_vector(7 downto 0);
bus20040728_part_i : in std_ulogic_vector(7 downto 0);
bus20050930 : in std_ulogic_vector(7 downto 0);
bus20050930_2 : in std_ulogic_vector(7 downto 0);
bus20050930_3 : in std_ulogic_vector(7 downto 0);
const_01_p : in std_ulogic;
const_02_p : in std_ulogic;
const_03 : in std_ulogic_vector(6 downto 0);
const_05 : in std_ulogic;
inst_duo_1 : in std_ulogic_vector(7 downto 0);
int_time_p : in time;
integer_p : in integer;
one_p : in std_ulogic;
real_p : in real;
real_time_p : in time;
reale_p : in real;
std_u_11_vport : in std_ulogic_vector(7 downto 0);
std_u_logic_bin_p : in std_ulogic_vector(7 downto 0);
std_u_logic_binv_p : in std_ulogic_vector(7 downto 0);
std_u_logic_hexerr_p : in std_ulogic_vector(3 downto 0);
std_u_logic_octv_p : in std_ulogic_vector(7 downto 0);
std_u_logic_port_02 : in std_ulogic_vector(7 downto 0);
std_u_logic_quadv_p : in std_ulogic_vector(7 downto 0);
std_u_logic_vport : in std_ulogic_vector(7 downto 0);
std_u_logic_vport_ext : in std_ulogic_vector(10 downto 0);
std_ulogic_vector_p : in std_ulogic_vector(7 downto 0);
string_p : in string;
under_p : in real;
vector_duo_1 : in std_ulogic_vector(7 downto 0);
vector_duo_2 : in std_ulogic_vector(7 downto 0);
vhdl_basehex_p : in integer;
vhdlbase2_p : in integer;
zero_p : in std_ulogic
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
bus20040728_altop_o1 : out std_ulogic_vector(3 downto 0);
bus20040728_o1 : out std_ulogic_vector(1 downto 0);
bus20040728_o2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
bus20040728_top_o1 : out std_ulogic_vector(3 downto 0);
bus20050930 : out std_ulogic_vector(4 downto 0);
bus20050930_2 : out std_ulogic_vector(5 downto 0);
bus20050930_3 : out std_ulogic_vector(4 downto 0);
bus20050930_p7 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
const_04 : in std_ulogic_vector(3 downto 0);
const_08_p : in std_ulogic_vector(4 downto 0);
const_09_p : in std_ulogic_vector(2 downto 0);
const_10_2 : in std_ulogic_vector(3 downto 0);
inst_duo_2 : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
component inst_ac_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ac_e
bus20040728_oc : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_ac_e
);
end component;
-- ---------
component inst_ad_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ae_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ae_e
bus20040728_altop_i : in std_ulogic_vector(7 downto 0);
p_mix_bus20040728_top_7_4_gi : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity inst_ae_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
constant bug20040329a_t1_c : std_ulogic := 16#0#; -- __I_ConvConstant2:0x0
signal bug20040329a_t1 : std_ulogic;
constant bug20040329a_t2_c : std_ulogic := '0';
signal bug20040329a_t2 : std_ulogic;
constant bug20040329a_t3_c : std_ulogic := 2#0#; -- __I_ConvConstant3:0b0
signal bug20040329a_t3 : std_ulogic;
constant bug20040329a_t4_c : std_ulogic := 2#0101_0101#; -- __I_ConvConstant3:0b0101_0101
signal bug20040329a_t4 : std_ulogic;
constant bus20040728_c : std_ulogic_vector(7 downto 0) := ( others => '0' );
signal bus20040728 : std_ulogic_vector(7 downto 0);
constant bus20040728_altconst : std_ulogic_vector(2 downto 0) := ( others => '0' );
constant bus20040728_altconst2 : std_ulogic := '1'; -- __W_SINGLE_BIT_BUS
signal bus20040728_altop : std_ulogic_vector(7 downto 0);
signal bus20040728_part : std_ulogic_vector(7 downto 0);
constant bus20040728_part_c1 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant bus20040728_part_c2 : std_ulogic_vector(2 downto 0) := ( others => '0' );
signal bus20040728_top : std_ulogic_vector(7 downto 0);
constant bus20040728_top_c1 : std_ulogic_vector(2 downto 0) := ( others => '0' );
constant bus20040728_top_c2 : std_ulogic := '1'; -- __W_SINGLE_BIT_BUS
constant bus20050930_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
signal bus20050930 : std_ulogic_vector(7 downto 0);
constant bus20050930_2_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
signal bus20050930_2 : std_ulogic_vector(7 downto 0);
constant bus20050930_3_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
signal bus20050930_3 : std_ulogic_vector(7 downto 0);
constant const_01_c : std_ulogic := '0';
signal const_01 : std_ulogic;
constant const_02_c : std_ulogic := '1';
signal const_02 : std_ulogic;
constant const_03_c : std_ulogic_vector(6 downto 0) := "64"; -- __I_VectorConv
signal const_03 : std_ulogic_vector(6 downto 0);
constant const_04_c : std_ulogic_vector(3 downto 0) := "32"; -- __I_VectorConv
signal const_04 : std_ulogic_vector(3 downto 0);
constant const_05_c : std_ulogic := '1';
signal const_05 : std_ulogic;
constant mix_const_1_c : std_ulogic_vector(4 downto 0) := ( others => '0' );
signal mix_const_1 : std_ulogic_vector(4 downto 0);
constant mix_const_10_c : integer := 16#FF#; -- __I_ConstNoconv
signal mix_const_10 : integer;
constant mix_const_11_c : integer := 2#1010_1010#; -- __I_ConstNoconv
signal mix_const_11 : integer;
constant mix_const_12_c : real := 2.2E-6; -- __I_ConstNoconv
signal mix_const_12 : real;
constant mix_const_13_c : time := 10 ns;
signal mix_const_13 : time;
constant mix_const_14_c : time := 2.27 us;
signal mix_const_14 : time;
constant mix_const_15_c : string := "ein string"; -- __I_ConstNoconv
signal mix_const_15 : string;
constant mix_const_16_c : bit_vector(7 downto 0) := "11111111"; -- __I_VectorConv
signal mix_const_16 : bit_vector(7 downto 0);
constant mix_const_18_c : std_ulogic_vector(7 downto 0) := "01010101"; -- __I_VectorConv
signal mix_const_18 : std_ulogic_vector(7 downto 0);
constant mix_const_2_c : std_ulogic_vector(2 downto 0) := ( others => '1' );
signal mix_const_2 : std_ulogic_vector(2 downto 0);
constant mix_const_21_c : std_ulogic_vector(7 downto 0) := "10101100"; -- __I_VectorConv
signal mix_const_21 : std_ulogic_vector(7 downto 0);
constant mix_const_22_c : std_ulogic_vector(7 downto 0) := "10101100"; -- __I_VectorConv
signal mix_const_22 : std_ulogic_vector(7 downto 0);
constant mix_const_23_c : std_ulogic_vector(7 downto 0) := "11111111"; -- __I_ConvConstant: 16#FF#
signal mix_const_23 : std_ulogic_vector(7 downto 0);
constant mix_const_24_c : std_ulogic_vector(7 downto 0) := "00010001"; -- __I_ConvConstant: 16#11#
signal mix_const_24 : std_ulogic_vector(7 downto 0);
constant mix_const_25_c : std_ulogic_vector(10 downto 0) := "00011111111"; -- __I_ConvConstant: 16#FF#
signal mix_const_25 : std_ulogic_vector(10 downto 0);
constant mix_const_26_c : std_ulogic_vector(7 downto 0) := "11111111"; -- __I_ConvConstant: 0xff
signal mix_const_26 : std_ulogic_vector(7 downto 0);
constant mix_const_27_c : std_ulogic_vector(7 downto 0) := "01010101"; -- __I_ConvConstant: 0b01010101
signal mix_const_27 : std_ulogic_vector(7 downto 0);
constant mix_const_28_c : std_ulogic_vector(7 downto 0) := "00000111"; -- __I_ConvConstant: 8#07#
signal mix_const_28 : std_ulogic_vector(7 downto 0);
constant mix_const_29_c : std_ulogic_vector(7 downto 0) := "11001100"; -- __I_ConvConstant: 2#11001100#
signal mix_const_29 : std_ulogic_vector(7 downto 0);
constant mix_const_3_c : std_ulogic_vector(3 downto 0) := ( others => '1' );
signal mix_const_3 : std_ulogic_vector(3 downto 0);
constant mix_const_30_c : std_ulogic_vector(7 downto 0) := 4#3030#; -- __I_ConvConstant: 4#3030#
signal mix_const_30 : std_ulogic_vector(7 downto 0);
constant mix_const_31_c : std_ulogic_vector(3 downto 0) := "11101110"; -- __E_VECTOR_WIDTH -- __I_ConvConstant: 16#ee#
signal mix_const_31 : std_ulogic_vector(3 downto 0);
constant mix_const_4_c : std_ulogic_vector(3 downto 0) := ( others => '0' );
signal mix_const_4 : std_ulogic_vector(3 downto 0);
constant mix_const_5_c : std_ulogic := '0';
signal mix_const_5 : std_ulogic;
constant mix_const_6_c : std_ulogic := '1';
signal mix_const_6 : std_ulogic;
constant mix_const_7_c : integer := 10; -- __I_ConstNoconv
signal mix_const_7 : integer;
constant mix_const_8_c : real := 10.2; -- __I_ConstNoconv
signal mix_const_8 : real;
constant mix_const_9_c : real := 1_000_000.0; -- __I_ConstNoconv
signal mix_const_9 : real;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
bug20040329a_t1 <= bug20040329a_t1_c;
bug20040329a_t2 <= bug20040329a_t2_c;
bug20040329a_t3 <= bug20040329a_t3_c;
bug20040329a_t4 <= bug20040329a_t4_c;
bus20040728 <= bus20040728_c;
bus20040728_altop(3 downto 1) <= bus20040728_altconst;
--!wig: bus20040728_altconst2 is one bit!
bus20040728_altop(0) <= bus20040728_altconst2; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
bus20040728_part(2) <= bus20040728_part_c1; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
bus20040728_part(6 downto 4) <= bus20040728_part_c2;
bus20040728_top(3 downto 1) <= bus20040728_top_c1;
bus20040728_top(0) <= bus20040728_top_c2; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
bus20050930(6 downto 5) <= bus20050930_c;
bus20050930_2(6 downto 5) <= bus20050930_2_c;
bus20050930_3(6 downto 5) <= bus20050930_3_c;
const_01 <= const_01_c;
const_02 <= const_02_c;
const_03 <= const_03_c;
const_04 <= const_04_c;
const_05 <= const_05_c;
mix_const_1 <= mix_const_1_c;
mix_const_10 <= mix_const_10_c;
mix_const_11 <= mix_const_11_c;
mix_const_12 <= mix_const_12_c;
mix_const_13 <= mix_const_13_c;
mix_const_14 <= mix_const_14_c;
mix_const_15 <= mix_const_15_c;
mix_const_16 <= mix_const_16_c;
mix_const_18 <= mix_const_18_c;
mix_const_2 <= mix_const_2_c;
mix_const_21 <= mix_const_21_c;
mix_const_22 <= mix_const_22_c;
mix_const_23 <= mix_const_23_c;
mix_const_24 <= mix_const_24_c;
mix_const_25 <= mix_const_25_c;
mix_const_26 <= mix_const_26_c;
mix_const_27 <= mix_const_27_c;
mix_const_28 <= mix_const_28_c;
mix_const_29 <= mix_const_29_c;
mix_const_3 <= mix_const_3_c;
mix_const_30 <= mix_const_30_c;
mix_const_31 <= mix_const_31_c;
mix_const_4 <= mix_const_4_c;
mix_const_5 <= mix_const_5_c;
mix_const_6 <= mix_const_6_c;
mix_const_7 <= mix_const_7_c;
mix_const_8 <= mix_const_8_c;
mix_const_9 <= mix_const_9_c;
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
port map (
bit_vector_p => mix_const_16,
bug20040329a_t1 => bug20040329a_t1,
bug20040329a_t2 => bug20040329a_t2,
bug20040329a_t3 => bug20040329a_t3,
bug20040329a_t4 => bug20040329a_t4,
bus20040728_all_i => bus20040728,
bus20040728_part_i => bus20040728_part,
bus20050930 => bus20050930, -- assign 6:5 a 1
bus20050930_2 => bus20050930_2, -- create port 5:0
bus20050930_3 => bus20050930_3, -- creates duplicate assignment
const_01_p => const_01,
const_02_p => const_02,
const_03 => const_03, -- Constant Wire, wire port const_wire to constant
const_05 => const_05, -- Constant Wire, wire port const_wire to constant
inst_duo_1 => mix_const_22,
int_time_p => mix_const_13,
integer_p => mix_const_7,
one_p => mix_const_6,
real_p => mix_const_8,
real_time_p => mix_const_14,
reale_p => mix_const_12,
std_u_11_vport => mix_const_24,
std_u_logic_bin_p => mix_const_27,
std_u_logic_binv_p => mix_const_29,
std_u_logic_hexerr_p => mix_const_31,
std_u_logic_octv_p => mix_const_28,
std_u_logic_port_02 => mix_const_26,
std_u_logic_quadv_p => mix_const_30,
std_u_logic_vport => mix_const_23,
std_u_logic_vport_ext => mix_const_25,
std_ulogic_vector_p => mix_const_18,
string_p => mix_const_15,
under_p => mix_const_9,
vector_duo_1 => mix_const_21,
vector_duo_2 => mix_const_21,
vhdl_basehex_p => mix_const_10,
vhdlbase2_p => mix_const_11,
zero_p => mix_const_5
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
port map (
bus20040728_altop_o1 => bus20040728_altop(7 downto 4),
bus20040728_o1 => bus20040728_part(1 downto 0),
bus20040728_o2 => bus20040728_part(3),
bus20040728_top_o1 => bus20040728_top(7 downto 4),
bus20050930 => bus20050930(4 downto 0), -- assign 6:5 a 1
bus20050930_2(4 downto 0) => bus20050930_2(4 downto 0), -- create port 5:0
bus20050930_2(5) => bus20050930_2(7), -- create port 5:0
bus20050930_3 => bus20050930_3(4 downto 0), -- creates duplicate assignment
bus20050930_3(0) => bus20050930_3(7), -- creates duplicate assignment
bus20050930_p7 => bus20050930(7) -- assign 6:5 a 1
const_04 => const_04, -- Constant Wire, wire port const_wire to constant
const_08_p => mix_const_1, -- Set to 0
const_09_p => mix_const_2, -- Set to 1
const_10_2(0) => mix_const_3(0),
const_10_2(1) => mix_const_4(0),
const_10_2(2) => mix_const_3(0), -- Set two pins to 1
const_10_2(3) => mix_const_4(0), -- Set two pins to 0
inst_duo_2 => mix_const_22
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: inst_ac_e
port map (
bus20040728_oc => bus20040728_part(7)
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: inst_ad_e
;
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: inst_ae_e
port map (
bus20040728_altop_i => bus20040728_altop,
p_mix_bus20040728_top_7_4_gi => bus20040728_top(7 downto 4)
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
92d8b86bf0265fc245d25ce34bacaacf
| 0.640216 | 2.756869 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare11.vhd
| 1 | 4,219 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare11.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare11 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
agb : OUT STD_LOGIC
);
END lpm_compare11;
ARCHITECTURE SYN OF lpm_compare11 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
agb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
agb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_representation => "SIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
agb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "1"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "1"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare11.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare11.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare11.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare11.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare11_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
30f854b1183fa855e47a9c6a8cfcaeeb
| 0.652998 | 3.783857 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_proc_sys_reset_4_3/synth/zc702_proc_sys_reset_4_3.vhd
| 1 | 6,659 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_4_3 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_4_3;
ARCHITECTURE zc702_proc_sys_reset_4_3_arch OF zc702_proc_sys_reset_4_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_4_3_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zc702_proc_sys_reset_4_3_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zc702_proc_sys_reset_4_3_arch : ARCHITECTURE IS "zc702_proc_sys_reset_4_3,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zc702_proc_sys_reset_4_3_arch: ARCHITECTURE IS "zc702_proc_sys_reset_4_3,proc_sys_reset,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_4_3_arch;
|
mit
|
8e7c1038ff674e842667a72c8823eddc
| 0.71317 | 3.439566 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/mix/inst_t_e-rtl-a.vhd
| 1 | 2,977 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e -- a instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_signal_aa_ba_go : out std_ulogic;
p_mix_signal_bb_ab_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e -- Change parent to verilog
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic;
signal s_int_signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_bb_ab <= s_int_signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a_i
inst_a_i: inst_a_e -- a instance
port map (
p_mix_signal_aa_ba_go => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_gi => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_a_i
-- Generated Instance Port Map for inst_b_i
inst_b_i: inst_b_e -- Change parent to verilog
port map (
p_mix_signal_aa_ba_gi => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_go => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_b_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
71bd4bf1f82801ce2b92ab1ee35834bf
| 0.6043 | 2.974026 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/Forward_Unit.vhd
| 2 | 8,662 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:47:55 11/23/2013
-- Design Name:
-- Module Name: Forward_Unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Forward_Unit is
Port ( -- current instruction info, if use reg as alu src, conflict may exist
CUR_RS_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
CUR_RT_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
CUR_ALU_A_SRC_SELECT : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
CUR_ALU_B_SRC_SELECT : in STD_LOGIC_VECTOR (1 downto 0) := "ZZ";
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC := WRITE_REGS_NO;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
LAST_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
-- last last instruction info, if write regs, conflict may exist
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC := WRITE_REGS_NO;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0) := "ZZZ";
STALL_OR_NOT : out STD_LOGIC := STALL_NO;
ALU_A_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0) := ALU_A_SRC_SELECT_FINAL_ORIGIN;
ALU_B_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0) := ALU_B_SRC_SELECT_FINAL_ORIGIN
);
end Forward_Unit;
architecture Behavioral of Forward_Unit is
begin
process(CUR_RS_REG_NUM, CUR_RT_REG_NUM, CUR_ALU_A_SRC_SELECT, CUR_ALU_B_SRC_SELECT,
LAST_WRITE_REGS_OR_NOT, LAST_WRITE_REGS_TARGET, LAST_DM_READ_WRITE,
LAST_LAST_WRITE_REGS_OR_NOT, LAST_LAST_WRITE_REGS_TARGET)
begin
-- 本条指令用A B 作为ALU操作数，可能有冲突
if (CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A or CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
if (LAST_DM_READ_WRITE = MEM_READ and LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
-- 上访，上写，冲突则必须停
if (LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_YES;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
elsif (LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_YES;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
else
-- 无冲突，正常执行
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
elsif (LAST_DM_READ_WRITE = MEM_READ and LAST_WRITE_REGS_OR_NOT = WRITE_REGS_NO) then
-- 上访，上不写，上上写，有冲突选旁路
if (LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
-- A conflict, need not stall, select mem/wb reg value
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_MEM_WB_REG ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
-- B conflict, need not stall, select mem/wb reg value
elsif (LAST_LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_MEM_WB_REG ;
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
else
-- 无冲突，正常执行
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
elsif (LAST_DM_READ_WRITE /= MEM_READ and LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
-- 上不访，上写，上上写，有冲突优先选EXE/MEM(优先判断上条指令)
if (LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
if (LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_EXE_MEM_REG ;
-- 还要判断上上条是否和B冲突
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_MEM_WB_REG;
else
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
elsif (LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_MEM_WB_REG ;
else
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN;
end if;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_EXE_MEM_REG;
else
-- 上条指令无冲突，判断上上条指令是否冲突
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_MEM_WB_REG;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
elsif (LAST_LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_MEM_WB_REG;
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
end if;
-- 上不访，上写，上上不写，有冲突选旁路
else
if (LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_EXE_MEM_REG ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
elsif (LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_EXE_MEM_REG ;
else
-- 无冲突，正常执行
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
end if;
-- 上不访，上不写，上上写，有冲突选旁路
elsif (LAST_LAST_WRITE_REGS_OR_NOT = WRITE_REGS_YES) then
if (LAST_LAST_WRITE_REGS_TARGET = CUR_RS_REG_NUM and CUR_ALU_A_SRC_SELECT = ALU_A_SRC_A) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_MEM_WB_REG;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
elsif (LAST_LAST_WRITE_REGS_TARGET = CUR_RT_REG_NUM and CUR_ALU_B_SRC_SELECT = ALU_B_SRC_B) then
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_MEM_WB_REG;
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
-- 上不访，上不写，上上不写，无冲突
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
else
STALL_OR_NOT <= STALL_NO;
ALU_A_SRC_SELECT_FINAL <= ALU_A_SRC_SELECT_FINAL_ORIGIN ;
ALU_B_SRC_SELECT_FINAL <= ALU_B_SRC_SELECT_FINAL_ORIGIN ;
end if;
end process;
end Behavioral;
|
apache-2.0
|
1ab57c56669053c066c4d8bd2596f377
| 0.631199 | 2.643334 | false | false | false | false |
agural/FPGA-Oscilloscope
|
FPGA/vramstates.vhd
| 1 | 9,769 |
----------------------------------------------------------------------------
--
-- Oscilloscope VRAM State Machine
--
-- This is an implementation of a VRAM State machine for a digital scope in
-- VHDL. There are three inputs to the system, one selects the trigger
-- slope and the other two determine the relationship between the trigger
-- level and the signal level. The only output is a trigger signal which
-- indicates a trigger event has occurred.
--
-- The file contains multiple architectures for a Moore state machine
-- implementation to demonstrate the different ways of building a state
-- machine.
--
--
-- Revision History:
-- 2014/02/23 Albert Gural Created file and updated with VRAM
-- state machine.
--
----------------------------------------------------------------------------
-- bring in the necessary packages
library ieee;
use ieee.std_logic_1164.all;
--
-- Oscilloscope VRAM entity declaration
--
entity ScopeVRAM is
port (
clk : in std_logic; -- clock input
reset : in std_logic; -- reset to idle state (active low)
cs : in std_logic; -- whether CPU is requesting R/W (active low)
rw : in std_logic; -- whether CPU is requesting R or W
srt : in std_logic; -- display requesting serial row transfer
RAS : out std_logic; -- row address select output
CAS : out std_logic; -- col address select output
TRG : out std_logic; -- trigger output (active low)
WE : out std_logic; -- write enable output (active low)
AS : out std_logic_vector(1 downto 0); -- address select
-- 00 = low 9 bits
-- 01 = high 9 bits
-- 10 = row transfer
-- 11 = col transfer (0)
ACK : out std_logic; -- send acknowledge back to display driver
BUSY : out std_logic -- busy signal to CPU for read/write
);
end ScopeVRAM;
--
-- Oscilloscope VRAM Moore State Machine
-- State Assignment Architecture
--
-- This architecture just shows the basic state machine syntax when the state
-- assignments are made manually. This is useful for minimizing output
-- decoding logic and avoiding glitches in the output (due to the decoding
-- logic).
--
architecture assign_statebits of ScopeVRAM is
subtype states is std_logic_vector(12 downto 0); -- state type
-- define the actual states as constants
-- bits: [RAS][CAS][TRG][WE][AS<2>][ACK][BUSY]
-- [type <000 IDLE, 010 READ, 011 WRITE, 100 REFRESH, 101 TRANSFER>]
-- [number <00, 01, ...>]
constant IDLE : states := "1111001100000"; -- idle (can accept R/W)
constant READ1 : states := "0111011101000"; -- read cycle
constant READ2 : states := "0001001101000"; -- read cycle
constant READ3 : states := "0001001101001"; -- read cycle
constant READ4 : states := "0001001001010"; -- read cycle
constant READ5 : states := "1111001101000"; -- read cycle
constant READ6 : states := "1111001101001"; -- read cycle
constant READ7 : states := "1111001101010"; -- read cycle
constant WRITE1 : states := "0111011001100"; -- write cycle
constant WRITE2 : states := "0000001101100"; -- write cycle
constant WRITE3 : states := "0000001101101"; -- write cycle
constant WRITE4 : states := "0000001101110"; -- write cycle
constant WRITE5 : states := "1110001101100"; -- write cycle
constant WRITE6 : states := "1111001101100"; -- write cycle
constant WRITE7 : states := "1111001101101"; -- write cycle
constant TRANSFER1 : states := "1101101110100"; -- transfer cycle
constant TRANSFER2 : states := "0101101110100"; -- transfer cycle
constant TRANSFER3 : states := "0001111110100"; -- transfer cycle
constant TRANSFER4 : states := "0011111110100"; -- transfer cycle
constant TRANSFER5 : states := "1111110110100"; -- transfer cycle
constant REFRESH1 : states := "0111101110000"; -- refresh cycle
constant REFRESH2 : states := "0111101110001"; -- refresh cycle
constant REFRESH3 : states := "0111101110010"; -- refresh cycle
constant REFRESH4 : states := "1111001110000"; -- refresh cycle
constant REFRESH5 : states := "1111001110001"; -- refresh cycle
constant REFRESH6 : states := "1111001110010"; -- refresh cycle
signal CurrentState : states; -- current state
signal NextState : states; -- next state
begin
-- the output is always the high bit of the state encoding
RAS <= CurrentState(12);
CAS <= CurrentState(11);
TRG <= CurrentState(10);
WE <= CurrentState(9);
AS <= CurrentState(8 downto 7);
ACK <= CurrentState(6);
BUSY <= CurrentState(5);
-- compute the next state (function of current state and inputs)
transition: process (reset, cs, rw, srt, CurrentState)
begin
case CurrentState is -- do the state transition/output
when IDLE => -- in idle state, do transition
if (cs = '0' and rw = '1') then
NextState <= READ1; -- start read cycle
elsif (cs = '0' and rw = '0') then
NextState <= WRITE1; -- start write cycle
elsif (srt = '0') then
NextState <= TRANSFER1; -- start serial row transfer
else
NextState <= REFRESH1; -- start refresh cycle
end if;
when READ1 => -- read cycle
NextState <= READ2; -- go to next part of read cycle
when READ2 => -- read cycle
NextState <= READ3; -- go to next part of read cycle
when READ3 => -- read cycle
NextState <= READ4; -- go to next part of read cycle
when READ4 => -- read cycle
NextState <= READ5; -- go to next part of read cycle
when READ5 => -- read cycle
NextState <= READ6; -- go to next part of read cycle
when READ6 => -- read cycle
NextState <= READ7; -- go to next part of read cycle
when READ7 => -- read cycle
NextState <= IDLE; -- go back to idle
when WRITE1 => -- write cycle
NextState <= WRITE2; -- go to next part of write cycle
when WRITE2 => -- write cycle
NextState <= WRITE3; -- go to next part of write cycle
when WRITE3 => -- write cycle
NextState <= WRITE4; -- go to next part of write cycle
when WRITE4 => -- write cycle
NextState <= WRITE5; -- go to next part of write cycle
when WRITE5 => -- write cycle
NextState <= WRITE6; -- go to next part of write cycle
when WRITE6 => -- write cycle
NextState <= WRITE7; -- go to next part of write cycle
when WRITE7 => -- write cycle
NextState <= IDLE; -- go back to idle
when TRANSFER1 => -- transfer cycle
NextState <= TRANSFER2; -- go to next part of transfer cycle
when TRANSFER2 => -- transfer cycle
NextState <= TRANSFER3; -- go to next part of transfer cycle
when TRANSFER3 => -- transfer cycle
NextState <= TRANSFER4; -- go to next part of transfer cycle
when TRANSFER4 => -- transfer cycle
NextState <= TRANSFER5; -- go to next part of transfer cycle
when TRANSFER5 => -- transfer cycle
NextState <= IDLE; -- go back to idle
when REFRESH1 => -- refresh cycle
NextState <= REFRESH2; -- go to next part of refresh cycle
when REFRESH2 => -- refresh cycle
NextState <= REFRESH3; -- go to next part of refresh cycle
when REFRESH3 => -- refresh cycle
NextState <= REFRESH4; -- go to next part of refresh cycle
when REFRESH4 => -- refresh cycle
NextState <= REFRESH5; -- go to next part of refresh cycle
when REFRESH5 => -- refresh cycle
NextState <= REFRESH6; -- go to next part of refresh cycle
when REFRESH6 => -- refresh cycle
NextState <= IDLE; -- go back to idle
when others => -- default
NextState <= IDLE; -- go back to idle
end case;
if reset = '1' then -- reset overrides everything
NextState <= IDLE; -- go to idle on reset
end if;
end process transition;
-- storage of current state (loads the next state on the clock)
process (clk)
begin
if clk = '1' then -- only change on rising edge of clock
CurrentState <= NextState; -- save the new state information
end if;
end process;
end assign_statebits;
|
mit
|
970f704c37dfa48dca0d60062cf818bd
| 0.526564 | 4.719324 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/inst_t_e-rtl-a.vhd
| 1 | 2,847 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:33:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e -- a instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_signal_aa_ba_go : out std_ulogic;
p_mix_signal_bb_ab_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e -- b instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic;
signal s_int_signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_bb_ab <= s_int_signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a_i
inst_a_i: inst_a_e -- a instance
port map (
p_mix_signal_aa_ba_go => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_gi => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_a_i
-- Generated Instance Port Map for inst_b_i
inst_b_i: inst_b_e -- b instance
port map (
p_mix_signal_aa_ba_gi => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_go => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_b_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
594b9d5891ca579276f2bb42bf6546fd
| 0.59993 | 2.941116 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/fifo_generator_v13_0/hdl/fifo_generator_v13_0.vhd
| 1 | 91,022 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
p2uKwpGifAgpoZdWTJormYLkghAL+Nt1EUf6bq161tC9Af/4e3kAo8EHswflkywqXNa/oWHTqJi7
a6PCGGd9zw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iGKN0YBzsq5cm4a1PWhln5xZAeWyxV/jTGvrN1yEtrTE9mu9DfIzb1BDdmYW2ylOwGS8TkFzKzOx
s4irvfBKfbF7jvhNLAuz6xmxflvoBkV92580GGY/Tx/9IEtCWksEDcHnIy7MG1OB/lwrpNKjBU6V
Rai8jXsKpp2lxz8js9w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FKhA3iWWCrDqWKez2FKMp3EP8wahbz1/AXoSTe92Z9HYsVfnXb21fcOHY6qItNEUK2OViWyYIHxG
tWs//Eiye8JI3RVKZ0BneA9kpnCq3SI0izU5e0VHs8ZgEdLWjSmFbyFNae4+62JO3mu28m8Zsrnz
FSCzBenviBzWyVO86HdDFKbFK1jHjPn5Ex07tuPcCZ9UiZWrI3Maaam60wNGovLHRXgHi0XZTUa9
mnyJwS7xSuBKN/e88ug5GNyfucOKEg6+SX9D8MM6n96zEoWSVjcsKcWcjJEmlvHE9erMeoxORS9y
dB+YPGofRxBOVhvLmA3thmyNRhbszA625n3F0w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
x+vtR/8s7IepFTHmnilVoSQnDsp//QKTBtxjtv1biXyMZ/93FdTJffbOpRtrWEqoC3mgtzFlp7zO
+roThQOys5dfvAIuM2EcKWDQPeNKrcnsGK4xhgI984QJHEjBxG/7Lw0uRR4YjelXwJ5JCJU6DOfl
7E4P322EwzIkOyKgEuQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
z7iZb5jhNZ0BQ3nBV+Pg3qOcZIlZE8y27vC03WriXasmmyW2tRZ6nkQWVpw8+oRYZdtsGtaJFbQ7
Z0ZugUFsUR/l3xgNm0yjZWmeblX2PE0PpLM33qUCT0TQ6xxRGtSvpYddU2RHfrLP1Vn7nBhR3u0i
pLbXoftOgP8jPOdxbOcHXAAjsRYKvIxGSSnQGwiyUoA9UCglkXA5m/TNUFjiNqU4s6Pmj7xrFWWk
eKq/GlMlSLzMA05VOqY7Ur1oVNqPIzACF0znJnkwCSWRH1Z0eRWaXjXp39sNII1MfKricNBNLbv4
TpPXM40K6MjMHNXw9/2OQHHOFnGNil68hcj7zA==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
DcTXq+5FOaKfAHQDgAiwLZrLrGECSSmLD65rjqk7fe9O6pVNypzK2ZASM8ww6b97VxSzQJ0f6FbF
5U6NvctYBZ9j7ew6CchL7ICTdAikQBsRJNsuAjPqENuDsiG3UJZpoQhE3VnHZid+Dox3SB67BrRB
GgN570mVRRrOocDWt7xiTUhOSGMLxhG0ctx0wA/llTlM/R2Vey85haPLh67+z2Tt5rFJs+ET2piK
tUQV9F4CrCtDJsm8r2T75EdCMp5jkejYAb0DD7OajS/y09AQsY0sC3qzb3SXyjCWu0m2+5OoZJ2i
srfHZeMk2mp/kD51B8RfksKyJAX532p06VGhTQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65248)
`protect data_block
T4wIkI45MAF4BgnywBXYEC3irWiAjiDIBwaLA3feHwpEPDPUWXZy9BKlDddjlhParvVt+0HWv02e
F/dh304opuzySf3QvwTq0OYro7dj4nL1eR5vnTuVIlWmHFDwzjgsy+W1rp7BVaSIEK6kiQyzqgz0
E0s5MNNIXgtKXZFMMQb1HbP7s4AnYsPHNWsjpddiRfGy/CuCUyYp+2UgUuMMtXe0vRgj33iTIwAd
riImsExO0v2WSbxY6rnks7OimElfivf7zGoy9NpEi/0zX9WmDWR0kBt2EBETwrhjELv8Z4jLud/F
yIuwPwT24wV6wKOFpYw2mmij80K2PRgXfpFe1ZWElGz8FxBK3H7a5RpuaxZIdVhclE116LUKUTSz
8WLEIYmShowo/oHxVnzlVpMh6dxaKkJkWtysSaeNjFB+PRErJarQdfvxdVDs4jLJBQwcidyKpreA
WiA8oNWjz4n9A2q+2zT0HyJm7pEqZjKx2Z3OSTaCgU2FiMHB51po0Y/K4nJZ3JOx0pNMdJBCvQRO
d6EYpabN8eu0rfXzpy5oocuLs+FRp81hOySWYDDdVI+E2hyLbDloROTGJO1IOGAezV9+tZ7O2rA0
0y0L6YVNdW+51o20BhXPtgP/pxwgISLY+9sxW3RCTSa6vCv1fN0zK7VMkdCzLF7jtf45ehHHvJiC
VjuE/4voKX3cmUSn8JAIQd9527853U8T6TW82w3XFQn95pZzPcpp+YDXWyrIJgsYpMNliy8f0kRp
+dKn9pl0kbzR1/S1CobABZ0gQ8WTF7ZIw1PCz4DyKlo64tnMcuSAYkXSgR/sVJCXnzZTbBqaN4hk
SYqt/zyGrbhLMgXwNjktge9Q7YomQum4jymQts8NZgozF/PjGb7HqQHs8eO58t//3ML0aRbu41ro
1Q7pjbpdzmn8PLwbtPPR1JwUaL6TTHTo5XjmPg4PJdwLQT9uvmF5GsL3UC7VcUW0KvYnTtxikTmw
pC8ss4q2iiaj3mRyWif6EKlPtUcbq+iHzBjj9nMFrgXkB9mQkkW/LLdBLNQOGhGzp2x+3WYs/tKa
vsaKw0xbwq8DKks+xlUBeDJ0QUMWf6vtkbyJDaKPkVVvqGIlRg4G/lhtTJZFj/e9PaqaF8fQHTFu
3bUiJj38TVf9i7l/LGfYaydJyyj64feL9aHO27nqdm3D5F1vr6vqYI+qsCJZOVWF5U3gEEb+Gqwn
gdC8YlDLjog7XEpaAda4K3fBgPa35An5Lg5tJEfb3wxJovZn/0L46lUML2qpE6B7DVKGwcqG2Lnb
yMZGFuc/Ae9ymyBIm4dkbGvxf/4tGjbRhgdagYQLtfUbZKq5XmzZyDGPRAGiq4ZJkTqKNGeGe/yA
jI8iNxDa/eYAqMte8FRoRKINCxvOgmOBt4R6iTVze6sR0S5Ib2eMYvv1X2u0eaI/WNPaf5SQYn5V
XIPkiFa2XB8FqNbWzjYqmJbjBgJIvxTsjFhk1L5sJ5J5yfOnkznb2pHENSioNwUqito13gMvjupu
JFnWIxBVYRGSaKYhtWr70mkIQ5MIqz80vitJPFOAuIcv3esoKxCZia69aXAfoInyoc7y6cvXDWZN
Vs81UlGajbY8yHM+Y9Xi5eZOE/Xic03nOKcHbfAZT3kLt1zqhMXit05ewj6lXv/tCoFK+ohRln2H
fKLdvgNXKxmlRvfp2cs4COFZ2avy9buFgwur0iNzxYBEgfY4138p/B/trIDdT2aIgyOfEVsmg3C7
XeFNfxo8xQwkkMDz7Jag7ahBUyjwwgI2hBBFz7lojFxKFFOZDh+EQspbrZb8vG1vG3y77rP19/Hx
H7KIbhm6C+CsRCsyfRtfgoa89apgvaF9MC6Bh+lZBHk5R6gSFDv40uvCCqe9UTxpQPiBMATdVFdc
xR3OVb0DAhs2S2eTegQeDDeJueyReKFG03HQqiiFI2BsZnUZ2623Pd5mZpbqRZf8BrKP/uBB21Bx
Nxt/Cm/9RrA/4T7LfJU+to1dWf/qTYOIrEOKCA046DJhAURXa70qfdq/SG4jMdeVG0ldbrotcgu7
4038mZt2XjyD9i16rjF2T7qo/JUy5QZdMc/6SX3+twfFYkmJ/ycZ0LB9CRJ1wo4f8BXyaGRbsD0n
WyO3xKXwk8UFgC7SVWTS5GJXDdrDBTffN6d9PlcFCUUi4RruoJt5j6Z650+C3HvG/nTcx7siPD4R
HifkXScWvmowzw9ICwrbn7dhfxoyyBp8M3adC+LXU1AGnVNsK2u8oAWDtI4W+dLCgKwRbdPNETp+
bY+GojUA18qIfu80wWWai4D7xuZOLJMOsH3Mo7LkTGKhq3ysPn+gmIVFgNMVDlbwj+cwQXSXFeB1
dBuZn+Shn61M/5P9H68c7Q7fWcoTUBHBdV2tPLat7QXJOg5NokGSBsAyVSpKQm9tjx+2iAaE1ht5
5ZL3Eup4Gm+tgt6iQcdJNQ8QkT3m0g8qMfDYIdGXjWbbuuetJ5+g+vA/Ji23gLRRWOH1u4NyVd8W
si27t1UAhaVo5iiCb0lQhxf61FcK53fArVPFe9MRkgTHNzBkhDCNGVikHJP1N7IUSUuK7B7rWk6D
abPloLRUodyZHBCEGBPCAHP91c4yUSuEE1EBImDbr6WUhwtelm1BSJb+fiiC8y8zOPWlYe3ByJM0
FkWBuPqzzhVvfurXEp3Yvt061ubsEhxWboJafLxEsLmyBej0vheJujkm8ht6fgApPgcNsza2v5/d
DgBiauCDfQXLH2klWwmKwlaCrot0kgf2tSDbU/RdyO4cDcKryKenibqYFXdMo7wyXeTWxr8Was0H
Soe9/FdMSp842xgAX2+hl1PgTcXQe/b/55Me48DHk1RRRLdFZIdyNMUWDdRy4zgmrbB41xdipzT+
imlvfI6V/Ypz9GbHPiW3vXklkE+h7XFoykdbZfm9zRLGx74YL949ftrDcwFRASMbYAXXKfOSW6Dd
/zbShxQgARFAUvsO9mpO5Kb8Sz20/XfQvPN7VXw+8BhCkt8cygWBJ55iBn+QXm3zPF6+UF+/eQvq
yUUcEjQXuW3J+/lr515hy4zNZ871yY3kKXatMo04fMVlQ3U5qNLk54tFWM+Uz49GRw62XSBmFPRy
jDL0FwygnaRh21S8WMMpzbxuQm9tAS0+UGkGMpWeh7fEUjRN9mFpZH/4vvrlCx85G159SKscyt1Z
D0BulA3d9lmj0vWFU4Zsj7l8Di6Syf9RVdM7fmTtTLiQw3oEqkDK2q9mh8bE7UV1npQhJOSRfPQb
B2gT8AS5Qqz5P7yDdDtWbMSUWztTjwvuNLE/uN0wiIrwaae7OXpdTl5uzxyn8ZFRQSZyMqvf9VAo
QoTe44Xg7DOCz629BlOpkiEAQ8ESa5Jiqk/MfF5IOFS9zQN5lWLTs8KFooFKxMPC8x3NB4ye7niZ
+HtuC3PmjCht/lOeT8CEHYbBAr/ZgCDAjJ4XFJTGm5Qalv/QKoRAihlAY/wH4nF7WI4EOImaUN/Z
fug43s8PTQZ8Vk19sfS2RmqF2uHF9LS/uljPRdoIzqjF/Y/zoecyNfbt8ZQWr7L6LlnmHAn7ydQK
aA/HNzRoOksBlyMLZxM6oESOx+VcwgwYdnwLRHGgoPn4LQI3uBk3gy+RpM+jGqS6QU5ylXmQZM6Q
92cAQhqOg1Vkk+OXoYuzC1bzP4QWbIhDf6WBHmjHuD3IRtzZhBD1/gyIuer63t59XhfrMUH0V9NQ
5MJwGNcmfPSKbOoAo0C9DmI/ckshbvPEYicKYugFrTMdAIwKaOh8N/aKeTr7w+BjwkkgDgSM1GMv
LWoUAWGzfv1xbky2YDIPdGcAOhWsKH6UmGZYPTOCl8n/6/PmjcxdacU2H9xV5PbRDJyYg9FCSwk1
Aa3vglxivz+kfWVSqx65vsLXQhBsEpqKvGPHLojxWfzLetgcIyPHXFrihz/B6pLo6w5b23RP0Nh5
SetuHo9EuwEV9N2Ijfxm3XkjadTdPQtT24g31+1KEMmCEpemxyu/LALE4bNedjRaX7NIHbgBMTuF
yvHuFXkU/p50v6hKSkpUksoQ1lEWD6/djowrci8I/pCV538cTmvrhfWT6Tgfo2wQBVH4A5IWkWpr
vyBoHdw+GnSlhRsWaPsEOLvGCDZ1aYDvKe6O2Aqp6lo7jpKP5wClqSBt38F4sOhAKhcbzzjUnnBM
GuX03lVuaeXUHkLJi+RaK9jP476tfoKgaorTjRvfv9XlZ+fJ4jeYozO5bbtnFVNs1m8r3VkDGKmD
uRxum+v+lxuO1k+ekLF0EQr6kCKcXteB4zi6Xi59h980PhiEUqKmUvWjNYGKfhsgEulXFO4vHh8j
tfUoxzVyCLVcCu1ekf/v8N4IVJl2QicPGJuNGOIjB1yx7LArGvdUeYsVCEX4ND5hXgdR1iqtYfaY
BamaWM2SCYVeEmIyTe6gQquoQrxxZb8ISmKdO26VpR9FWGPygvsQBJV5BNstJhag6hJ0lmZoX1qd
w7W7DCwRHBKvCpBLO2wTsqd+M1J/sFXmaK8MLYibWd4byKMQeYgLvbbKIhCZeeqIXYm9tuUea63q
MTBx3M/07Gldrqh6CpzQS7yB9/bhesLeJnH2nEY1it4yYvrtwtI19A7PAVbKXyIPCIAoUovi3AhN
HbX54k9efEG0rUTaCfB5gPbNNAO3mkn2uAQWqfPzXdhJoSYRC8VjztUquzD/IZVEjRm3cIw+lt3z
w6Bsu/Rt17OKrn05slZkOUxNY49EDei93e8kDy3NJnEN+OODXkMiMHsRcuv0jbObhgKwUtaur4LK
Gkq5v4eHRhrGAJAfKv/QQ3Ul64FKU//FPXF5W2x3lBiS0FU2vD+OVVpuZKCZk5v8z5vkrirEy8xd
pJTAdzJNAJb+DuimkD2brZ7jFnxo4hoWLTj92dz8Ix1bKcWRHjsvT0sZBH+8bQvAk7BHHFKa9kxv
aeDEFPeWVyApUE3lYWB1QcRBszMeLt9cG2vMlg5cFnGBptKd+dfGCkD8fu/X0Xr77PumJlxfJM1m
OHDV7RYzBp3uAe8a5X17A/lV8FHGciVcr4Qy/6lmWrfs9NG1oaBc5bBhKuDlwPXN+NVnMo5dFxGe
d6WH074QpNmeJZaDv8zd0gP1a2t8QEJM+d2GW0MB88UeBUSm4IsCuZxvTiNPFoPdwXhRhmERsM5w
SQe9HeEBMxkxnAsiv/yOeA8nA21iPuP0Ybaug3DbSirApp3efC4v6fAG7ZTeaGFhVbs28MVIOiZs
VaMPGDI4YWsu8NjDSTt2SKaBESg8Bf5mnkjYx8q9SmopQqK+CTI4XAAU9fGlD0el1zECHIfUKQlU
FEwfAJw00pWXygjkGgOHpvEmppPTW/cG6d5b8UunBJBVMGXLK8FO9auI7VoLMHg8uwA1RjQfHBPd
vVuvz5BjOK5AO7+zK91g197+A9PYLIg9gjVDSphc43GN5bZRYDU+w2KIPAuzphTAGoKGKZG93vum
iJE6f0pwo78eEEzZITR8VSdBlNga865mfm5cyBWjvXdWaDFG2yyHhb6YzAaPTxZi2cEil7aEvHmM
17EPz3wIoR8hVVMpBu6Xz/Fi9fr7AoX3FeeuATdxFPGN06bM57KXLsT1H6dmsPz9OLeCWNTpEMqh
XZ7DVsLzCv+fshDo3rgN3Ad3qqzzzOT17OyWxx262vo3JdHcgw9E2CCAomFbJufNCeZpdAiIdx/E
5k+w8UZehI7xhiKml0DmAwhu/cHgkJnHwVJiox/hPbNfJ9L0nhDGz11AGJ5NrfYzVJ1D83L9KyZW
Mq5lsKDXsaNN/hVvg/NA70/2vbA9Ojg4z1hmbXeCfhQXjnIVHVcARXP7y3LWOnrb9PyJIFldBYQq
1QqTzVfjZcMZjqE8mLnZBbRUvI6dRBug1N79dwfQoXWe/h/XHaO0xVSNo1AKOjyWwxWvMfLbI+49
QBALg+ATcvnNeYyfS4kZWUf2DIA4sLGSbymD8aCsYvg6M7Yv2sfaKyEfxgbQk6IoCpMaQW5AtIpQ
AVVCYRVDhJt1u9caA8ZgDkhgDsz23zQK7y9YYwFNsl0JBz8nntt14Wy42PiKFzWFmUivatZLphZG
lmLQCPdFbxhTgJP0veO7aSbPhOZhc0uTGoQoESKnXDAIJ9aLvwBCOGX35nRXQrsKW2UEDVOUL3NA
QHUYLBII4Qe3qJofR7EFsJtBB2zk/BhYTbik9MjzBtXLFjyUK34nlbxsJKu5qWVdjTaev6+jnJ+X
3xsRPFcLq711vuBeAg4n7D0cc3f5Wxi9i7WlCS6bpwsX/QlK8Wya2crVmne9Sjb1x5tmXZvwjfWY
SLhgoT2iwGJbcOYL/LYpu5V9wi3laSvQMwqjeukY3NXgWhms/N4oVi67McBlF9TkJOGaZ4C7SaGX
bsfDS10uKLID8ZwiHe8hF6UoPRxO6CJLPTs8KK8ssEepeH60AjCP2SCPwRjuyEp0hu4sg/jmXjrI
kVh0lRFPE3BuPSln12BfK9FlcmQm9YcpZU1v2kjA6UT0tWXIqaguPgeAvpa2CWsEChINeIF+FJUt
Zkmo3uNcetroMUoFLLdX3/W1NrFdH8OAJyyat9MG5SE6fiayfcMLUUP2tQj9PTXWVFCyv1nnlGbt
7vmFozCjpPkI2qtBg4GSky+4q2BOUu5i2scwq65rovxbSbEIwEFGN7NgFniO8uoiX0PWrBhSZOoE
nV/3UKi9dKNIHbvNyRMcyUP4/uSvAAig/XQBPApYythXuuLY5r/Zd33D8UpTbPxSeSJVokawdO8p
jURwcIwdqNq0Vkq7QAK/7ofpMjyPKGw9o7OlwGN5Irthm7j9zi9PffNBzkp7miwcrfNJovatxmwl
BUrbSk0bSgzYTC0UltHJ0uHV8q8Du8xxx5cHxZZO6nouF4W+x4H9Tsx4YcGEN7gkcoobRa3dhX9j
MLwjvvNonwGPRu5IMxKO2HdlyBNBgcoQl4P1FBTvjb6Mt8rBuR3MLYi51w06aaKzKqON2jAwgXOj
sjx7ayq1mZiR3fG7M7EAuoreqcT1pSwR7pCmW/CrlDEZSl6+TMCOoxCywnZ1LBB5FmVex9JItGZC
KsnGaMptZD8srZG/CZPK0s2zhjvp49OTdIM+q5N5iV/ohCQthEFXM97a1k7r97DDZr3QTNvHH9IR
OBRVdC31oP3of0ZR8peU0gZ/xwowXFtlc41TtFHoHpx6OXNbg6hgHqS/LOPE7H1ymtPZDjKBpTl7
O/0TuOAdZp5htS/uzn/7nGKj4nmPY4XIGmFS2psNmEWd3KFF1Oucf18vn/WcrhCNY4wgWmN3wNg1
yc/3ujNNCEpQH26yJHBGdZHgqRhL1Uk+7J8RA442/saIHcWnE4M+UuoutQTHApyyGP9ZUq8gT9vA
Fu4/qs9a2aa62BciNmK/oP1ZD1OC/59PIjA5N5l/tyfkN6AfdVxYS0Vjwo/aEqtJcVtY+YLhZNNV
D4pnMJRDyovGyzXo+tU6DKnwngoM3LFT6erNYXZrtZz22wJvrH9HXtpTkV3lXq+OuCdYGmhnPB4u
nCAxCMU8fpC8WJhqvsd+m6+YvLgP/rXibMZt6cbvQLtciE6OrSQNFG6Gp/DUIGlVRGhNIRIatAA/
tG0VXrfbKz4YPdof5g5nWrSzSu38Gd7SA9V0Y8cCU0lhfS9wH+HM+R3Hb28UIW2IkkbynSZOnwzL
z6j/Whuzs1/f6qe5x3+uOFcARJE4o4BFmn4vAN8BO8DGKUbGYy0iX5YEvgrEic3EBGgXOVowNPuP
2NQfkUTFBEkzkoAlkFi3mvX8fM/4NyHZrsMb00t5Xg6P158c4DiESdoo7H1ukS923P7pq4B6jBmV
G3UTCD39MeI5Zu4q2npzH03UhNGsVHssya+OpBEK6DM/MtqK4K9APAZuipasuw1ddC4Kw3B6g+v6
Qs//VFmSB3fsk42Ngbx8YsbICP9IIVlPBQ9bJcsgVgGGdyP/U2qC52GMTxlpSc/6tXL4Yb9Khk77
JzCzduYxv00S4ElZM0Gy44ZmuQBovaowkSNfAeSYAeGjxntg5ZEiCtYCF+Qx88oc72w2M9os65RH
3AP7agq/OVrFddcFiBvoxrkRfwHOtz3nyWqJRbdO4KgaTi2fgfFSX31fFHeJG19DvIP1Z0qmt+3s
cucSnrLRjJgRVa2YfQHRrxI6euQONelWma8yBDjKPCL699lX+iUzO8CDG2tJqstdLFd1RIvI27hU
8P11n3+RL8HV7S4R7sCHDbH66o3v0zVkEDZp9neuDbb2VeIF1hlGnuDL2kzv0qtJxnxflUc/De0O
R/sMceka3wGzOrCvFpu2wTs72eNe3LR+WhbeH2Fs/5BXEeTxH3Oew0VaNlML3478P0KjR9eO0UWC
XS3hbZm8TBpva3H28NDwZqUKZkpLgW8xaX6YPTVMbNQv09ictcrIq6ttI5gnOZwLFKGDAcByMuor
xAfVAK4bf/vP1B50jOzWWv330I32aE0cyY/IDtjK4f8DjanwROO/q5EMsb2mMGzwKijN5AgWdbvi
W5XkFLAqQhGGt9oGqKzu64rLJz/WTdD57l88vCrAJLljSUwRXRkeNFkmkWaLygERSx17NujiLjkm
yg4G4WSPKMQZWlxjY2oxuXEhRTpDfETvhcUstnEhoO6C2t/AO+VllTDpbukH6sWk/BZGJMOW5hlH
TioBOlysOZY8rkH7+J6dagH+cgE1Ot4ZiIXWqEYHDZHLSetSAPP7OeYKoBD3VKiN/S4YL8b7Kv27
KWrie9JELUKto2bUbt9MaGwNIuS1cA30YvhFcrBfT6zHqY0FqeNPZpPWXSz9mmsh6NQoFQjz95C+
kHx5xmV5ckHhK/73JTbyR8xW644pCTCAh6NeHN/v3CxGw4Bhq0xV9lPPLQ7pCtq25ZCohMNCKCeJ
YxaFCoZ+DZzYjx+CK04r3nWAahG9QkeecO6ruha41VNvR3Vob03Yf0cGaqLgeFVaB9E0V917uhtA
hJd0q9gfqb+f0bw9rPUZRjGU+PCwX0gSZn8o7f6dMyxfBfEGK2LtMjUq0+IsN+qBgYIgTy9uFJ/o
6s69GqdKB+HIqq5HKIT1GoVYlm+4Ef+iSr6dOvLLy0AHUJYmy7Y44LHRV6BhyijtKsinZ/1ZE+Za
mAbZx8W+a51Kun6Bu52YubdYYnwmBOkQYsJO6xwpCKumhnpxDlIyDjEVCPjqgo076KOtp26Zwn6J
kUm5219JqSe1S72GJ/NZ5sAfn4Zsk21tqS5xtyP0JeND7ElztyZf+WZ7BnF4+byJitMiydxM9NB+
aPJfbhT4aLqnCmfpHF08mQX1JbVqJ9MhpFKwKd2Duv9zpmm3b/gxyIwYWKbwLFrdzSr7guhFwLxB
mXkuzeW0fe7NSZpEpuP6VHZfhIWPgg9MGrGgM9dOrmAyUyQRiY91qkyVxwDKyHnKFg26Hb3Y8/XP
7StfHstOq8eMasIWB83t7gxr+6njS8iaMdRTXID2jcjxr8wKfhIiKDyB1M6J4/mpr8yp+ZGCbrN1
uy4zTluQN0egEGWw2sL0veo0WJSmqOyZGBvcghrv/58m0tgTgPJKO/K7iWyl+JfVbhI22DulyR7w
UeTQb4p1VZh+KIlsePziKQFW+OaC6JIA+tzv04v+MwzuxL+qu0INJ24zfNnSmvksOu8/bE3Hpgd5
AE1Dmp8kTeSZPbtk7oVIgS6Wbt8vlBIZ4u1mnxCXufGNTf4A00Qi99Vy7y+Zs847CfHs4EHw6ZM0
fSeO4N9Fhmlg7rVGc5dmNDnT9Ep/uE4qsjZI7VnLlzV3S3pdmv0Ni490ytIF7M1ieZtKKJ4ZNVpo
P7zhZT9VXgP5UD8Wm0NFhAt7B5OpAWJ+07l4FipuIJLAZffzq8x3qLwKSgVOes3EztodausS+3Qo
ufeJxzWlJvsDGqIPskEzP1hijjxD7FL6v1fixi0tl5bzvbvocyXjjFDCMD5erzbO/YlCCbPDc+Ut
l0UFAFoDDNCoamOM1UviXrvzgSb/brTVoO4skpZK57NR58gHr69+VqVQJ2TgEmqw1/I/5DAox+2c
181JiActOuVHWeCxGESroCjdC3kdJrMM+rJyQuki82R0Wsb3RSjLgUpfhL3xEya4GhBElSlBbdgS
1/pCWfgnK8ixnrmn0fwB4TK1vBfrV5OMbW2e8rlPHc/EMYCrSAAck/Y65fqKF4AO1Z9wvJFf90pH
yWKv02Dx2oq/+GTu2tXjlAcYfKP1NGPxbGZXPmQL+tyIS56vT42vLj6wINGI1U/uN1F4kN1sA1Ds
SmmFAUu7wdQM43NVjilyi0YBp0mfvNJ76se1997Qb3lj3cndVPEoC0B4g5EjtrWR7m2xVQRLqYo8
Yo7uH9SDHxKft5vhm3rqtcNBMZHlO1YxKwa//kV/ldR9iilQhpRBifwxmpMGI/DdboqLK0/pNeg0
uBQQmdRL8+/eBQynzFCIzpZPMq3Cfdgp9YslcCZYtgjE4McEKuljx/qwvrzm34CnE9g7tnlxygp+
Neo0jQtz11V2GPc8/cubPFgvn8JMG3SNIWDZx6vOY8gjU/ugN4Uz6sne9dwTt64qLOoWQYoZUalE
dAw7AuHRPTUYAhhnX5EDO9wIfiC3cMq24WIz8thJPCbNo6IG8cmiU2H/vWSF41AtQFVFqfz9Q8Tp
dkEOX9U1zLFXrjSk8DqxQ83PaAx5KWVWzjaMqLNKiXjfbvydlLDoSqn8OSg42ncsCl+YOzRuIAvr
hCoZnTqpQjhMsnaQTQ8GirzNK9P2tMPgoKhxIZkWtCzOBs5K0oLPlxJDM6KlapTowZjE5QGgVFzH
FIppinKdzfJQmCIIfgVuxISnMegawGxex1vwcFGpb6VmukttbH0JqH7ZhmQJ7jf8SXVbLUICYjrd
Xw6rVd6AzIOf4ivh9u5I06BphzkFh5vziRYz8ScOGNJgOkNrOL3zpCMGsrDzkZL6vrZqyjtQnmH9
3KxnRe+6QOJVuTraAzQn8xAVDt27IfoeGzixfrcBRT2Z+YC/aoLtjSXJ/QvDTsHgMf0IiHmrPHPk
pHG+Wue/3PkvdrFZZrXBN9zVpZolOvgHTnmW7jzkTTJIujT/0DqL2RqXxinrLZu+0oJWWF2h22KG
pXc0TQHXKZSF58SeE/gnFNTOab6YYENO4gbKtN1M3aAFyYP2z8Sx6F/K8c4tBbTrJ7HGqXZRi2c5
fSUNzqKFZp/N12SkkoetZn50cxKaUfW/WP4ltfzDm28oj3ErJrmN3DQYFxIWo/GalG5cNbuM7ae9
wgu3dwGMwUSIWU+sGuze6PbCMK5d5h37bPu7TnpA9RASKXpLD1tBAcQkwmxX/zYm888JQaiitcjB
eyGoWyfzgO4ybjVxQJ8pgU379zWV+gEIGfNL7gWzJTMLuQrurC0tr50dFE+9EEnwAcKdL8/Z98JX
zaRIMGugBNTNZoeoxeNGxfkis+/kGUy+8JcR6HdET8tmiKzNB6lZj4A8FYdzS3vFINYTg6E1tMDg
CvEb1g8j/UmswpLMfwZtbhYeprnjVaHm+9EQ5+xQz4cpkp8602S9gPCPQHR/PtXgbBr54m7sHXd3
DGVUqER5wI11qTV3jmQJaE/ueH8W2DtFgwGqxGJeQ549sG/lB+/ol8PIV1gV+1eIils7p19dlw43
E2qGBo13pqEvJPCLv/ArdtoxVOnDmfiaYSWFMyz0kBPA2lthSVeMYTyc/p0sifPl0jrnqJz6NusP
CJsWg8pi9rR+f5umsf7+jkEHkz8GZjRFZn8xyasSUDdKSVGWLqwZG419Ryod55JZS0U7w5+4REHq
exFJs5uBjgws1NwsYAzA3COAXCH/3iOTiLUjSNVif2nav3R7cdKrJEDSo4GUOca9D6sec0FgxnCH
ojqvDK+xisxJU0+IitLsuQLVSWyksA09hriD79ZpiXOJSaHQALDINUslX+np3rS/j2cQiGN+7Dqt
E8NQNwoDXB1WvQGHTttAiVekS8A3oJcPKYPH4ishWOMhBpSn7yiw+ox3HO7Xyy5a7vu0OHxPaHxP
3TRm65JNfaQ6jEA4fsKnzCAFP9/8SWdt75iHoPgGYNiViXIPqdZ4/zaxxSeBN2hwN1WRyr/lSnnF
T09N2DV10Sbusg8j6TclJa6s70kE/eMTD6WLWoXytujwl1Cu2ryaCPrmCJIZ9bv8i1SjwJQyPuRz
832ZuzrvfyLXhtaspfgn03yyITs05W2Syzc5/nMnnKfNHfNlk9BI4Dx4+oI7nt0UTuGIZc7CUQ/4
5zS8RtN1rvPgDf5zbiYl6oq8nYn6NgrfFOYBo8RcO0zYidCMXJGVNmGjn8AIBH0l58yHQml13bAF
ldGprbQaBvUm9cLSX3CXnqQCDC1KttdFEGl2DOsg1gpoF5I9pg/tn/HRqflfKXw1WI1s/Z36qzYy
cjo+iumAYymeXmqPxQZ4/x1h271qBj8q9mcd7acPORbIAY1EdeMd0WuRIPHSN4mhhybiI+mL8R85
MbUNLsfIkEhM9Es5SBZRNT7Zyvq1emJjeox8jYggDq+j5i3zFSQ/rMaPe6ZUDaohBaLHcOXlVqnN
AejMWyS1Z4C1pIhcCIy+TEBE5ozTfhrzaIEUZo3KwN+nEHigDUsh99FXDuzL6bSFfixikqJA+F+i
mqUfQuRNaZQBSc1tS3fdtjvFdaBUmpTLcxMG+XvnUJ8Fve2WEGK2fzyXfjRzvzQHA1ii/7AX8+EK
ijmJcSd01Kdpu07F6up5oKbKGW3lUBmApJi8M9iR+d7yN1EbbpjSgi7XIgZnd4SNrjwsClvP6ff/
zF342O/iIkz8Gr3UwKeY1XPA4O+fHboUCeIIhJJOdWw7z1tzjG7TPkC3/e9CUcaB6uD5Pf46x5Za
YyKoVxJFjZttrGDBLzGMA0x0XjM7RhNt7UpdkrrA7BPE9R/Sfwlnk5rZuwhAjH651zN/n92r2EUe
QRjzb6j9PKcZAZr9iO7/Tw3PDQBxX3DWGuPLkhXffcuRNOmqsmbZ5AVFUPVWiw3RtV3DZRxBeOnn
YhJGQ2YsExDeXhoXWgTNJxtKVIg2dv4M/apM/TOY7lK3KdBZMMqLmUQkTWBdzfqCeuN1d+oN27An
s6w2hJepslQtmn+nUcgriTnq3EGV/QcwoHqta721MTAd+uXWJ0i1RmbrJMkkHw+Sljq7pvIkKPbW
TljvkAtWGfzBNfV8+sq3lNikBKMZT5pMhpu+03IrZX7w+0qvfSpAZ+L2neW/kjPoWHuLSckV5W10
PeOaj+TiHQzCzn19wrDqQt4o3hYNeo34g6IBjMVdTX4vBgTKUcxguy3b0MNTp5sNs8yMX1+WGctH
l435Fr5XMz5sBDRwQx2YT2D39zflddXlISHlHpRJphDOEZ6ZcsxYzYEMcwrJGR+9Crap3h3/MwiL
0jVxCYyZggrqSb/K8Eego+ota80F18xQk5w6qJ+g4teNBGQoKC/M7m6iAPk7gSMPH9YErL8GCkuM
jCzGBGjD78VOEAJpyXXe+fi9EC3RXJHV9+v0LwF5ls9ZsLs73G02WjMI8/JrsjkmlW0/0J9oD1eY
4w7tsd4V1Bfo8N/kzGeHWuiR9eujFpN+37M3NkCNM+wMatM31W65j4zswfX14f8uOQbdF+Pne0Ct
2se+Xi4XVsCiuk3V57POWQxQx6GVaEbf1mz/vuTuPXYaTIKibAtyvtFOq5OHcRYihz09OZq3aHO8
SWhu52MgCZcsvmJENSRNlvZdp7A5fNTTGYtxSGwsthe0TLV1JHfucEIkgDDRUB5J97tXxdbO0Y5L
rztBRpqo0sYFN21g+r/LQ4BEb14fN53u/ConllL0fAGSbUzIwRgVlSUvMLAKE/izOJwW/Vnlbo0a
siAzq86VUEaXGqJPeliaPlP6o9gt0p0OzlCteEU3a3msJUrckV0wRQyAvIGiuthefAYSOMPTtjTI
f//0wqfwLQzTQMF84rDtxp8LCVdrGK5OIUcHnCx/h0DEfilTEiNVwsl9iwYnQ18tdlqxgJMX/Fz1
keN1jMQiaufK8M1S0XG2cK8ueTAviRKG7SCKHOL2Sr680Kzqe6RPqWloPBG09+oUgId92F3pZ+z7
R8tnPR6XAMKqQDiIpHmJoW8Eds+ne4TmM8PqXU+mQUA0+abdZ/q8NtnklOCmX+qyzb5FshpCC00R
d4VV9V67mKzpv9WnorN2gD119cUOEYT0tFo6kxw4Z3TPxZkkOiwPVnHkY5dCRvakjRkJznZ5gdmW
TS9s9t/Ee7JSpUcxXsu0c9uYuHFI+tCbHeMs6dQSsNtQ9BvttB0036JXLl+L8Fs7AO1Za+jadISm
LWRFUinmvJXWQgRbp93SrgthPLMuEhOA/NRTNvKBHAptcoepiQtgzTe3MIK78cBuPxvIuoC6Cpcl
5ANewf6QZWsgVt4wbJfXsifQXjpxnxguTVADtGylWkhtK87SlmbsmXGdvvq2jj8S7mhYGFIsv2bQ
Iwpf4rXNQTkmoUJmNC8I8YeSS+y9CdVuvZ6KGxY8ynHVUSIWwh/FnDYeD3HiQL4Y21KTty0mxoqR
AS9Lg3Z5yQCNhDyAUf7GPINccAaPM/A+3IDBYiIh1UxIbwPMtb4YmjlrG+O9t+8HfVxb5w8STWqH
RF8eH+J56blkjz0b3WEQMm/abco5+j4JpD9NA2Or0LFhr/sxetk9MtZXVkcfZmSBBok+VQATelh1
s2VNnILlfB+q3Pk1YppwHJNBBDMc6IL39WacQ3e23hO6h5NmNykBHPDUrXlu1cFAjfAFK7VtfDny
SD474/IS9b0Y+yEN7idVOceSLEZzfRfqI8D2DgyRUbYDPbzMO2vOO9xWwuf68we9WAryLvl+YuHj
wvthFvJdNaFbE9GSpX17iTFNkJwW3MHKwJY1K1Unp/AH6+tiiJYlltpgp5nhsWDNR6E3EYcQy+P7
0/p6wG8uxG61xC4VRmm8ebDZF3Cs9ZjxrCb1GqsjRCI1rBUwiNVWcVNCWfxo9uPTFqcsoPOx4LLm
EfnsJ/M4tt1LA5b5xdzQpqfBAjrEr4Ndbf9DIP4a8rSyWu1WlNN2g0b1ZsyKKGQNOBiLurkqNVgv
ZfLhXMnzpsaRN9seghbjzhfQJGPi7Xq9b67urPI6+Jg0tpK+JUfUPbRAIu78dnwz7prsO0lNrL60
jcB3jPjJI0uEhuPO4eKmkuz0O2G8s/yyx6dFHWraTTHUzooFVk4k0KTF2bfF5TnGGI3DbLFkXxCo
w6NlOCTC15XrJcj9nxAGhZLLq+IK7+Z/xieyluHD0VfAyAX3imlelp5z2PYWM5QKU97WUzHryKjY
BFYvKbFS5H+3goJxViJyyCmFTsfZUymc/8WvBOyqWbiIPsnhOqsWkurT+on9bgeSc/pSaY6dDq79
jC08J9TUMNZK28JjS4hzZhJijvZkrHj/3wpxDUKYkjEXb2/ntm3rH6AQFmxYR23vhoP5fheuxbOj
BnBD3swMp1bRDQMbRXvVtGXJGfWiP3cWhgoccb3ZTzoOocnCfb3tWc7ASryCrJisjLA6APsKkCnv
f/gB5aDjqtaoLhqMFeh1Ai4kR2gdKLgwOM4IlGqn3drEYwxw9OiFcRs0ktV1Mq29BqA0mOKjnlRR
PpErM0myW6cazHMyCTg+Ry0/lTJE6FGI8PNjkT6VF/CsojKHV0kWB5RtcDPdOTzEO5Y0T9jniEwk
W8y5aiTCkUcXG8AWCfICWIII5wDzWk562UKkU/eR1aP/EyJyGWFmn8LfbabeRmELCzPh5f+1jlv5
cBb2UcwhNWjVdMVXHBryBvHYs6xUUym435lknU7cg/Sj5VbrHDas4ME9rfrXbHG7YksmPGZNCtvx
wWSLFSq/OCEGcmQQjb7GkkWibt1PpY92H+JPBcW8qTicHvtQWQFoCPO8BBvGccnBTkMjgKTJEQ7e
+X4aMQ06G1ibJvt9LEmm+RERYsnF9gZSiu7rYqfRfafTupIwq2kU40yqaY+jkNDgTASZ5sOZlgB1
AcdQb5NdwCkGd2OanC03y9VmQBLp9J/ka8ukT+LhEXGSLDO1V79Bm3CNTsyb6v1ERrsCA7wfNuiP
OOm1zn+0on757gSHgbqa+ItRr1NUVrCjV711LqpOMFokmzbb3TYsEXgN9ChPxWk4uctB6oEqqSkQ
yT+0wmykfEFQO3mVo60PCvOmib8vlEXCAz2HZgTdLCPQcK56XTIarAV+DnY1wG8hejp8yaSx/lhG
PLMxBiUAkTBsR/E7Asj/v6pyRi95/T0CiCZAT8N4tLON/TssOuPhnZT1UchNU/AE4UKsckZcw6KK
r8INhVu3c3cQXgmONQ9bWWpVNngFxA3qvWO4Tcv13Rh76I9Rhxb6NVKos488+zEBBJ0HbTr+6WHa
tDV/9PTtNVNwSz1DsIExtBQyAedWJ0MnkkTO0CNIChNJo1qgtaLHxTJfaCRwXufMBRkL3bSDPIJH
9EzAiUvUZdMvOt5xDThz86ps8XZLb5tmCZDtobnPQ2g87PdkmtPMy4GDJstSCGtCqGyU/c3l6HPM
4qJvj+1dz3zSgkJCqalvLnpvHs3IpbOr+XPLUS81J434l1cmxL0jnTbXq9bsZHx5kpk7pn8itvSA
z5hMnJGxRGoNs340Ficlho7hJVcRjvRJa72Er95enlJwAsBdwtYaZOAoJaxbAcvXIM4wx93nbeOy
5jh5LeTjfHz3arA2HnXhw5niz64bW+rPXfUmob+RkRYvPh19V1YgSVHeHELu1ipaRkbOE4cJ1dFJ
2lS7o+IUWlbfWazJXKjpwepFhVORyqyDj2MfgQ0vvXSamVM33GRUNihRtExEEg1kfMHnIIRe158q
5EeWU5GoxqWoJXTggi8Qk9XE2MAPwiXRaeVNyQdsHsxqVu0J6sWt2g9BnNtDcBWqLMUhsv8JvPYp
HSUo5QR6AA8Lb5lVxX75F2dC9Vha1KNIUJxwf7CVrKsYfufSrybpbAMkN01faeiI0zeougAsRZzd
FKpjCmDR7TOZVcHfTKvyYGE8RWze2WNCc6EeBnCCRXBlPeI0tFOFPJ2vO7jRUxG+59J4+9SntdMk
lF2QkkPv4Dv5+CJxKNocOppJkEvu4uFrCvhmmBWrOzd+vK55Iq+UwqQN8sPK8bG3KdZiU0QaPlxC
k7iAyWNH1VGFbjEFvZ/BGl7PIMwAlSfUg+jHvakatjaTM1WXsNf74Eyna9hq/uresFjhjouf4wsx
yH/q33cDTwS54GGu3h/G/03X7RkKl0A9eUYMLmtWRi20WAe2XnreAkcIR9Ym0xPAja7Sl97RwE4+
w3uNPAq5ORvvx4mTqi+lNFPjUXysO0MxfOW6VbkNhMpQj0TrdSUiK26QbCRkUlUB2GZ8XShYPw4U
qBfAtT/AvJPTkj2r5xvMgR9fC5WBbJ+JdNHmWCYOlozqedNd7kYTVwJQsguCnFr5R9vD3JMCltf0
mAFEv9v2V8MG46J9odn22jucweuMor1VITa8Jv7i1ObvL5sBCqRFZPu4STYIIylBET54E9HtLbTw
WnTDbgeeQ/jVeaHvb/Zk62NqjsDLIH0QXE0v7xUbNl2Yhk+GK7lJ+P6eY4lLl1WES3t7kiRuLcBR
hWRTvAWTAu0xW+BTxKyWfL/wllRdNDcx2U8Kx2Hno2+6bsvLR+gNCfgsLI86kP+bTS6onHUPvwed
0JVndF0j7nwhkqrWSdB2rYr5JZ4Ybpa+/tVcVsnhpoVkLpna+SjGVvg0VRX6M4Xzgnxiqdd4notW
K1JoDn680LbkZ/cv6I1fSyUDZrzlJSQaV5boP0mEw38U4ua+5Xvzw4J3TSvj6qKznTa8Yt/HdTk2
MwS4bC+DHUhRDTatkXyQbqvwPROu/JR0QamV167NZ5uC4qPAnF3dUMYc8ntbxzs+GOij0tauJgV3
abTH58U41mN8Tn4BCuNj2P8H6D/8BO6G79ZmUWCddKolFEiW8n9M3C7iPqtBCU6e7e8EhQ0GPy4t
o684veYIQSR1LOoTtKEfYPrbThLGyxXbD9WaEjqK5hwHpODc6vfYrhPzoybhcD3lQLxNDR1fe15R
PVtQ4D0xmkg2x4kQCNkayAQVyMAes6xwhbd9mblvDZzVMxQ6ORzbd5K8FwBKY5sqdLixTwhPvBRn
ki8Dgd89ePCKQSkDco0ZgAcUWbVDck5EOrMMTPzL6Vt30m3wfrN6gPV8rI1z+eiMlYhthMTfryjF
2kbYAFfq0AJEvVKx7AqgHoG0FVQ0jf1f8xLOO/nOVrsEdCN04g13nVV33zFIGVzXeHNB++qSw0I0
SrjkXN1VDgPDvNoenvGIgGgYzNsN1p4e54Di/5TMif5nw0iT5CRnCha5PuofQySb1f4zqc3WxSiF
NwthOin6QmeFo169LwBnr4G7q+nW4D1T6yxuO7WT+H3mR8ObjtrBG+PgwsASyseKH/QfnqsNIqrX
gjaBofQYWSBH1UmhT+3B+y86mai8ohEFsk5j178ajPiij5u39zLIs1iwseHwSCKTPB2kIk91JiQs
RWyxSP3DAZyC/m4zmJYEY6E+D9WL1boOwTH59oblwUtAP/MVAY++6dCXrFufO1uEL6RJ0G+7MCTF
o6Z1VByY4fg3o71bNDQf4lE/4FNd0+Y/26eItj+iVwD5WrB+yQ9Dbm5PolqhmygVusdaKgTGNgKL
5veTP0SxYs1MZHbEQPVbo5mTOcOulj9ux/Rmp13r7B1Gq3O0zArPmkE23gbZVo3XPul3xDztoevy
szmwWWejwKjP+ktVMI5HFM8ATeJRQ0naO71/LHv+ZgZTVBoblaWAFOxS1O5K7ggoA8gkPbsU6l/v
c1wca2oSSLb4sgKzhPOR0BVxtKm3gOxn5tUX7vrePKEJsG4zu5b/LjvJ0G/1VJY6CJtLvt7+/kvl
mXKJQ2bUPDvkPA9KyTLAa8vQQoBhSBn75V3Cn2GpCNK0DzXr5aUoECMHD4t6p/PRsT8QGO4lqggp
0ZealasKkYCJZ1wQUC6FOmREChzWKmPSTifIwwk05ni8MmkRCepfo+FjYCVphZ18263pMor11m6N
XVj+Om/fa0SiASfEfnaOS50AuulOUHsF4oaosQ4db47db7+Mh4yg5t8VmtrrIq0ag+zV9b1qHztW
eVzqV1FTEvWsxnhQ7ULGoKCrdU9lgi2fY3rzFoABCXpRLcds/Qm/CYj56VW5J0PfsjZoS88fxeBe
ey93yEnVGsN6DliNwbJ7VupPenEKwLfQG6orZ8iqkJf7d/XUsU28uS5rBqb9in9+Dv2diNHnd6ib
yxQsZpzl8IiGxRBXhICYUSDfwtbVmWJderfIGwrWw90I1uOQkfhM/TNidoeoS6Yl8+fBfAiG3Lpm
AsrojGJzSvKLcE/5KlG1vgIzn3SW1NG1C8cqLon2O7yIePIHn8IEAv17bPXeay1mH/s0BYCDD1sg
W1wBa47S8B/mYpXEwSqr0Gk162+8eX0LItR3wr8LARBVvsDdG2/A1yz/mpI9+swt6EP6BTL+jpuK
Q9d9MD9j5+zTr8t3P8cnKHRl3TSJhNLT01RDb+jvfIl4W8BFBdLV2PHlCOF+I7jvVBpb2lqId2BZ
cT4g42HwGfpNZnUPzegu7dOm5xTll1JYDKaHFZrKN0o6JJybPrKG/rqoMUIyXtmjIGXFuY4HwMQe
K8NhfI7lILc0aE73j94KxfDbBira0BR1TdYdcV0AkYnSibL1A8G9WiX89UBU838/pgVMrX4bZ0Ff
yST2Q1VnH8Uy/8f/oWxZDgGL+S/UzeDs4WZJaIUxmbx9FhfZtgvRbvpg2sENz2ppMBAbJxWWHMZW
nvEedWCFLk5nqZdCKYzo1cTQpd6SDLDICuJ8dtyV6JsD2p+vAttZdUdEa47fP0HpTnnMNsHRQfUG
ZLW4xQh9SwGVBRKs62XnWwxLJrFRHIcZTX/Q+eyaqArQLAAaOsaZOsypsVuqTgQsco2+7183fijV
CQn7x/QOtOgLXeLAvS28c5by1xTopp7RQzojytjQqof7jAQwwO66AjGp982zSr/vDoqYTrcEjvcZ
wnLpkWgXadOuU1oBNZRsG5CNvO9SMXxkZkY4gWwcU03iehFIlA7qbH80eaAkyXmh9SzO7lYVw+7b
eTba3K+VwQ9aqsS4SVYXj3Sh0YitpPfhjZggg2AP4bYBBqVG4O8WnLwLRfhSDFMA15WfI64hq5LV
LNEZ4+b+J2sPx4II6vgvXaA4K1r3e0q7ROJRDXh8OJYrLizXEqR3T71rvI2MJTrtxl4lmiD4Ttc9
HEueVNiCYC4vBMN60kP20e78Uo6iQtAhZPe8JGU5dKiDJCkC8672CS6v26o69F3JvtGIuCBy7EBE
a96CA7aEQXcDF6Mxy8IpOYahITB6FC0H1bkRJAxxZBkBbaS9xbPnl54F4Fwn+B1TS6aQEVt4ApjW
Hj7FCIbWWruMrh2/Pli8pztroc1mFERkEkJ447VdBl06pu1UN/LjPou2pB4A7YC898to9J0N3RJi
xnMyyCSf7U7udA80uNtS+SZZQgwOuP9RBWgwrp8EZSS+tywXMC+6IrqSGzSRxV29/gehhsjEVayC
8htCjrU1ZQjwDtfNoMMPiKsdGYnLRpgCfmQLbSTnhad80t2IevqEaQ8TvwOldePNYITZ5JSHqwlY
aTZfmpCAIMpsOwUDFBmwRyuLhGjdUybuNZy6grx1e2TdIzLD3/kCZEdvEbqcg/lvoHemr1PXs48U
tkzCEPskRShf1QlYVyOmxWFwNQEXhqrmYWvinI8ws3Z56NgNXJNVMqZa0hfcn//OYc6jo9DzaQuD
3N/tzOBETZsQcJdVzY+c9cj/xpvDlm4ND1js9aQxNiOD0ejwW1Iq6782M8ExhvSwl3p3v+gl6Rbf
3jxjqhzNLdLyLD1ETcfcZTVzVThgh2hMQUOIHzZZN3qhxiq+jl0r7I7+b7FalFYiItgRTqxhOeCR
2rROAJkI6clyY9G13I6KPE9NlDx53pu5+KXQ/8Xrbrseq2sPxx+r0RVTxUWtD4xaho5WLaZDlDxd
Hhcu76/7D4BKNGArP/RBdVvP8zRY+DWQ/OKJUdOxUcKKm6b4rDELzpGEMXRjVK1Tq4QiEkkzVNC0
Fav3d3AhkYR3e+7VSj1sdGEfs88xGdjzy5nJl8IAPp2NLm0SHrGjQwx37KHT2cJcJlq1B9oNQ+K7
zn0Q/7l5Bd/dSYAWyckJosbtUdWBH7P8gwuv8n/17s9w4zD/9bnEbRwhUUruhj+2kzGF0rgDqrlU
aZFoUtZOLjC0NgK+WAtQENK+26thJzedWVdP1FgzzRVyvvZ//4NUKMDkFrvshTpt5CCEZayRJAL5
P0zxw1q6Rdy2Q7RyL2XBX/lB0ZX3/++OVRSQrY0dzfq1i89r7xm/i6CWE1sjVlbHUIWEE1NxGRjl
/lHiix3EY+/USoWxxRQvcFTG5ZTJWZjhjjKsh/L05ymAF0+mfuJCqGGOK7Jv6I+KYTe90e7oAdSt
xlRjTUmtVRAyBBDmBAGRznXV49sWjP/ZsnA2FdBArY/5LBIQLTpc3BbuDMGKkjW5Ug8jgcPcwp9f
A3rwk9CXy824DWQUIOgs9rA69sl5gyBleCCaQuQC1FXOZ15tDV44AsUoQ2KmOLafVAAS7zp53a8q
aD7caAt6ShuS04/ZF6oXStogLingwWNf1Pq0856Ijndow/43miz/iN1R83hiOK98Y4MZ2dfgOqEY
Es/AvAwe1xLX8wfaqaboFDTlTP9up975yxVpLV9jZy9WhrwD5K+ApxjesBY4+H+kjedzvbuMcPgB
04QXgfNDpRbd/PfRmQxuh66P9utlAgR/d9L/Dqw+o/FGUF/NXLU7rZPXOQja9tM4UGTpJ1n97JOl
IhA8dwswWchcEHFXntw/F2KEiI3BzmYsKZhrpr+Orda2eq7WdhpjiidDTag/jUpSVmqSLO9I4an5
i4S/3uezGNHVJmrOlJvLCnZWMSWoaiGHHune/DsJcp9N2kdubykxq+EfjTrDez78V+u4kj5LyJCx
6kYNpoXtIgKQYdM3+g3I4jtktFsfWXhPUwZBcVqeTdENVPyttpUZADAuP7fsAbrXwsCu5L1RYIiD
it7jeAChX9OlK8kkExeJLSriMCXRiXbhHTSPCSUE71Oo9KtWXbqnFWLovxznwTtNKPSqsoxgbUz7
4FEyqVW5019F1K0eX5vlV79U5vL90ooBYw/bg6Q9A1uZgtBHEi5ZFo5wurKlznrTrAPE6VEhCKkZ
X2hd2zeSJF1s3XeQ23SIeq6wAObRu5MlZYZ/VEaNlR/GKksapqNq8rZnrKKUUMmPxfWpQpZtayBy
Sd9oyXqQJ+GOgSc9wfZh2gJyPMdsBDoLLaMJ1AKlS3emR7sh9uQqXQEHiHTrmeYdUAK3ggyDFDek
Uan07ar5mMVR6t9bUtY37gXitljljobm8GUSrinQW2ZH4i3Ap1ZdvmzIJ5CMb4+U7QqV7daOOMKg
CN+Uaz1j4czdQ6TmMLU4xRIgMzc4olPnZ+vxdyce6MLUAWiwgoWTscVnB4DTaj0vP7/twmRRhv8C
0Ctx7HwK6yAnWJfWGXfWvi9eJ7bmJMDQzE2CfvWC2fQRAL29GM9dZKd/Rf+dia08NUzUWue32UpF
wnDAO0E9YyN+GiyHbUbvTNu/RM5RT88wYurujYh00BAKr9nmKcVcIBUbCyCNDChDap2SfZHFK+Mt
ilrbAKVLjH1a9+qLn6W87cPhWKPQnXBBur3KvJ1WT1xuswOvMWFTri6YomDbWfQ0f867OWAB6r7v
Ygjhohd8iJ2D8a0Zjp7NgFbcj5xc3kWWOZ//YN8RXIwnmBhBHmuUNO2iW2mkPUnrSbzr/7e6usOm
jotvNCXEhY/VRfA4CmaMffcKFoZrtXqOD+Vm09w99trUR75gHQn+8BJkmFfZibLSlHY5CJeO4rmH
9ccvV/qqLInHeOptoAra/KFGrFkMcKpvniT+GuNoFovFschT+EvDoXtBmadhBLgtBMKHLpD0QO5p
ENe44h7f777mdBtU9MMaUeZoF68d9Esq1gnKv83kISIsKGc4WHUbLf0EP5w2PY2kX+iRDMMFY65x
XXB0+SSoWT5k5OoyGuNvdGwNXMfkptjtcIEUouQR/xgBIed1dpQuQ277jygLefG4Hc5LG9AvFug2
jUNWyBKB1LrvmQK4Aee9OlMwQOxHE9Leu9dUIDeRddqXzID8HVsUuuD2NPBBo8PH2oc5lEWxpRx6
gAgaAmcW4k/kXnEkzZX22W47yafYoOyRUdepBENqt68SrDbPevEsjjg2bivZMhA/IxkPpJg7vg2y
SaT03dNOKGzTpONfGXF3ILnCmGKgCy2Bn6btYGsS7NUq/1yhop2chPWAtIZOgOhYeI+yLe1KDWwi
MUCuMWAF+9AJw+f9+6qhDdEjPj6Q7SZCM5BLL+FRav/hl0n892p1hXAn1oSWWzXkeJtstF3Rw0ns
M1LdtttjQWl22gtYci+8CrSN37oXYoO/E2v5fVr2NatdetQDM+vo23CLImWdHj0Z0B2q73nBOM0k
Dqj9u5zbTKDAYYI4OnoZ1u8kgo7w8jLB9mdifFp2rB5+Q4rV6u3mNeDd2yGI8Wp8SZ/QoDcX1s0w
oH74XYaV+1Q9Tq2yV/CGa8XmLWZmL4Z2sVS5xEdt9Q8+VMZ9M1vA63isTCzKoSS7LjOn5Ak1a6ZN
+v5K0XVpFSX1njhPojXbwRcqvfYZZZkGn4dZpjBuyoi5gQDhbsUYmbEGTjSpHocHJWPztwil41Da
u5sz1Ifux1Qe2TRt4P/4J6937JBYghYjKNuMjHOCwvBQrh0DOxclethRW4oKxdAwL4jNzroDlbNF
bFZbacy0eVfA9OTofXuzdPrK3/ohYdTNrK/y3sftLQQXv9E+XI03/tbqJamnMZVbWR004UUhL24v
sXsSerChWBZXMaGII0uRPWVFWDAxYtJbTj2IoMFUIjXhfEsB6cTasYaM1IEmcxOfdMLSRsdrEZR0
rlbfp736hWtNjH5P3vSnJ+dF6K23LM9WfTGsw1bmwt9C0Y1c01zrkweL8P/2RYxy2ovls9r3O7LS
kKM3pQfCTk6a8uKglhg4od8yhIOEwv6LiSy34vn8dw+LmslfAbrJW0KQce9IANu0FUbPWB1Yg1uj
WNOIIfuS+98CLIJV9fTIHyQPrVkUBe8jTTT+7U8DfvwAp6xu1gmD5BwQ7d4SxA/eQUy28aEHfl2k
0iTMHkvil66yd64MP79Q1IwZqqQiVF1Z4HKz9UK3Sq3rpYksR56y0BZx6sD/y6sqt4YZ6BRO8W0/
QzDpk6AUxE5vj+m1ak6kHu25lZyFFDuixDw8jn2gw74yUvgzSkdNSfT6UiV3ln0mQ8uhEEcHVA7g
fQWBbY/Cm1mBAtd+3tSJmYhUt9V7CL32UdW1aH3XQeNychEJXV8wQteRJM1ngM7ooT9nAipFGlt3
b+xD1cdhD8eY6hhYC+2hGCkahFTwlOhzCj6QZ9F0YaLyLgz4hxkCPiK+PmeMvtK5D27l2E1uo6b3
PQGNVaHb/fMqWep0WdMCydJwO8ha0g80iAQMopkC8jClVIBpwU6vWc66SNMXytSKLAsb0KcIu08X
2bSpvXC/uBX5GJcpa+HUhwTUpCDwG9n5FJN8MnUflbjAeX6nPfZ3PZ/mqrgfEwzirkatFaR1GDVt
bv9B+18DSob151rDHyo05xBHPPizzI08qGAeuz5xukHpXMRh+eBe5wgZU68vtcdwLNiK6a6WIEWH
lgyrsO1kl1vqRPDiyb49vnycSw8MxpmiZfvp98k94OPoYDOeF43rUIsDinv4L4SxR+sgXkmWUZvu
QDO5uUoYqQpCCGnobwZvtCu1IaFcyrdhrBRyJch3/muUwUzdoTtc+1xULVhpF47RO2zAZmdl/TPn
BNjD3fNkivbqeryXf6gLzxLorION/CYnPUz00JfhlzTPMrdfI7GvAxObKCmMUP4SqWngwbSY6ljM
FTF5A85OUfAIsttlwbidqSm/vVKdjoZk4GgSnl/ICpfrMIwhz7uL62DiXoFHqH82qtwfJDgO6G+C
7QHaY+dU4VPlGZmOfezoJaCwqukbuay+3w6fY/RPJyoMs+0Yf5DjNlVicJtykS+c/PLJxfBHoDUE
NYC3tVAxI10w5tMLqKegDdSK+Bno69U2+jUjsUBd5PMkEFazwf8aMgnBHsNM0G4MK2SXPq79W/mc
41s4DkJ9D4c09MGg46LDP5B/O40dpJ8uWfGRI99vlBqPq+LdeC3SdCe43GavYngDUoqf1UQuU8DV
ztggpaQf21Gm0dtXKhy7FUtDTnz0Z+EWM/3m24L4sGqtAl/rk3JkucV5xMhWl+Dt7sfS39w/4FpO
iiJ31WuTtUWQs0YFaczPlUCn2zGga+3LtjlzdqAfwgnSjOjkBkotXxPerHTGEk2xrHpBHk2DGFIR
AqYY5KZIccFnn201dZw2USRzgWQaDcztmpk17QzIRcKR1ri8GGJgPDXBRYGmMIkAptEjBh9osR3O
zC1PLhh4+zunRbokOJdz4/FZXomX6ZEYzxEd50Kqu5uFXyohCKEOWpECgwja7Tfc/zSpsEOmzt3/
79yTIxTd4B560+4fw9fDjgHoXjMODy03NREt7IiCOPf3RZAv4zxMWaSSj55tqk+UtUODuAyY02k1
2NWUzjf5Wnta5/oNoWjjkfacDnVZOX1jgG+LcwEAiFzvYMhgpyXREOd4Oh0z35IxaGGT6rHoCMU6
jnsAPjFFuwZgBR83vu0yaB3k66drmaiv34MJdzzaEiuOgZ9iY9iQIdIHMGuixSEPdGDGlWLyOitQ
JeP2goHWqPjJgRIi1g4MfRsxgoLr9m2YDzYAN0ccFwzxuunGJwe9jvRYX58iy7W3iOMY9IM8j2ny
W8JxQ4AYHp2zmkYWDzMaEoBZDLgeIsnwZY+nuIuou0LjjUZRaN3opDdJayTp4Kyp3oQ5em2CaiHd
TwkmHTthCw5FGXgwzhoYiA32mZy7IZx6B8XqbRXXxQed9Y/mJOGAU9p686RWjEHdcceqKvQ1Yn32
RTzr3tydhpegQgQw0fILMTkqD30lXsG6lfeSJTgNKCC5aQghrCCQ1fmjfbADj4JDATSNcOEG3bbO
Ufu1Bbwj4NKpmbKrzHeSchdYMtRg4H9kC7PfJN3eypc7DJ1RXveiVOdqa67K5TujGsnnviBvYvel
Al3oFpo45Jn7+jOUt8r+YHX9IaV8lc08xSzcMq/NMjCIn7Wgu6XcvArwmnrnC93g9AV5uYpEfDZt
wkUVfuxJ8NHJ80hx8dhEysFniwZ61MWWbpfP46C+IQ6fPpUENBRLi5TT2Vy051tMny3K2uO1NKck
Ao/jU+teBfK/72DCds8L8e7zs7BXAWl2de/cc0yTsejK4AYflW+8SKgQRTHKb+2AuT6134y+1FmP
Dx9BYXcRjH03RWXANWSqFIF+vPdpLcc4nNmis+w6RTRrmARDE2B+WhDg4sGr/YFOvS569PpgWZN1
Z+Ypy9Buas9153ltF7kWQRdC6mQugjwpCn2206hMaCE8g5fAgPMhVdZYlXdDbVCJrHhLhWMalUv5
oke5BgQIHGCQlb58VLsGzRdjrpZ14Y3Xqsbg1nji9XJiwkhVKVx/S5KiS29WE9NQ0UaLqN0bJ0Cp
S9ZE66HJ68au5HAMe2/AM1VcBZ5ILDz0agCpz6jiTbExWAdba/rUHqV9yNhngz4vJ0YZcaLNS0J+
Bx9+MtFBxCpdtLJLb5DjSFKlBmMGgyDtC9RcX/ZiTIwLuXeNvLBrOSWxhu+qWQAUC5UgW/wjkrFG
o6TdQqcIIQz9ETT4pf0YUmCYeZw7eJ5XtEGf+oYAATWh0FPrrOku/GmOdSDJXrNTHXzRtgaJtVXP
QVSXpLUe+9zd+zuIOsZN/dpwcXD9Yzn5M9uadjMjQn8pHpgvZrbMiqUNEAAkWbNqZztdOr1CJNnD
mZiQuhyJo7Uw2G81ViebZLlD2dPPqaRBLKzVh9KRCtWGMpjcHjv3ZcG4s8UnzYz+mGDxjw6IkoCf
559dWJgEdpZ+DWsQQwn0ldDooW+wHoKNtae9rmj1cSj2SRxm0XeTUhCPgOgj0QrBOiNSdrVqo22s
6dL0pbC1hrZo3jyQScAEpkEe8YReEh0TrNKHZngkV1HagRRp6tcPeOvl6+fsxMerWZaz9qcjBp5k
+EHRNRAbkuFpc3J1Ysk0NB1C/TVszuxpnK6/3mmyjs7L6aAR/qvErjsSuR/N1aDwmuisYvorHlsb
51VNvB2s7Td35ORUhukqEvl6vuYJAWqTTxgiOmK9WqkPOgesJspwHPJYM+ES6titIOq/A75wrTS2
kUfKSy84z2uZgt7NUgTaZ9e55tOuVXR21tVN1Ds+ZliZtPVAWrKpX0SPb3jHNjVET7VA4OKhm0EH
uiZq5M5h3n7yugu3zFUkLAQspa24BP18HeuNdgbTzE1MZVVvhUxCM+1ijCWRKgS6XUyY9qYaqCfT
GILJdKTk9whiytp6SU+FzKZXtO/dGS2RigFhSd3d8mIS51meCcy8N2kUHyP8iMVj3iyiHLt/RYQd
chATaW5cAvcfkErqIg4F3ebnpDEMRMdw72YHMhY9J9rV7Hk3smlKsyThxw0GLg7dVGAjTTYIxqb0
+EM51jdRo9E4dYeSwlhtBltX5g0N4f3VMj0VUhOSc6NfFl8OAfF1mSgDCIOZL5/TuCcpKotn7qGW
txXQuQHABfHzGsN/d+HhUzP252XvsLbJKKCQLNf1la7zRUo8w5k9bMk7yoLMc+Rvc3MsBPLS4obv
LjSYbwbFjVGBwEytAeH65tU2MPkSmpozBlj7D8HNJSojeqLGitd60YycwFJB27Hvjsz8h/QUjXqm
hsOuHw2i+aPJ1CdJjfBXLaPxIDbnHdqLRjwUO9OdoRIFySonbELR1nt3/jMPGEitVaFfnafGXf23
Dwy1BS4G/GDo/lxmlyYr8Ol1+L01WckUM9HI5bjh6E87qBS4FACRpIT9x/kXcH75byqtRQE8Vd93
6b1kfT9lXVZoHWBxVyMc1/LCpHUkWD54Ho6J5u2WnOJcwcnJ/cCgXq4BzTx2CxiYMNID2UJH5+Sm
sIpPNuw0ylVb0FOHcK+h2s2xe8upiWGg7Ts9cqQgv6AriwmtApGtk9hmUsZd6gnt5HMyZzBFShE3
RqBC4ZMua0Xn5Fw2c9nXpVE7cMkY0QDGVDjQ3TTnVDffMxwztX7KELJfqJEI5QAtgp/gmkDLErzr
4wE/00w59bXtPH7WVXo7Mwxzr/o1NtJE+cK8SpriugxlRCWfC5lmvJk3487oucXTcO/vQTJsonLg
roTV5Ow8TtOMMpNdctvzmvxlCO6UF02uLpaUaRV/TyOCVP4D8Lzi+kS3D4NlkL7lHxXH7H39Z978
a+LSR3jYc44X4dnnf1W9kREZ/a8N00TTk3wyG0YI62QgCobSww3CwnapWehsOQ6veNiHD2oLPojK
CWlUjPJhEshy/JHhKKv/leKvkQTDKi9S4V3NKsiz2TXWG96Hee0cT21Y6m/EuWTtjG0Pi4cu2vtb
szjTJy01h37jpSyDxW5oRXTYk+Lgmrd6AvWETA8LyGeqU+/KP79x/wRlY2TwwlHNXgBbBREIuZST
hvmPlvokIoLUoxKNdMT264QouEiunXB3DeeMGHdcotj3vOuCOy5PsN3NERCBDmg7BlOSHqACGzWI
RKZY1O55rt+1qKj/+JWMUA4+EbFUzynwfwkyr1LzKxuldgsgg9pC3H+qqT3HdCKQuyGthn4Gc0WZ
AFuC2x95ClRberILtNB/hV4OCv3H+HedK+CvMLBN1Bt218hYDp97ASLel1p1jK4aGWHYyCLHE+iK
IWsnfYuuBLYFViAba5Aw2A79wCNg0uo9C3ijqlWTKWHeLCG2jJ0XGDJGx/Ratr9dpHO4Tn+7Qk0i
G5kIQEUWQ9f/CdoipMvOswSCneLbihfsx8h51oYgLfpUIeG5wL4Yi9Bp8SSiMWIiQfqv6sZEgtY1
87aXqvisdqgO6MVHrFzXAZsTIo9BjPYWVebacNnVVimngpedMyO4bSwtV8OFyDTgefqozNjp8Aqz
1Bue/qgTrE/++IfWxeQ5k1n+0M2Oqaujoa9yFET3LvHw/Qr8MebPxR+biakA5cyG30jEis1u+0LD
iLu3b53e1W1hbNlRA/WqNd0ccIpvC3J+NnwvptSTMxPfZ+VUdgm48m1/BdLBxDQB/eYw6ChHN+ek
EZlUdiNh2B7ZtvcMRUY/EiOTF/FFmwMk/IAAT85PpImpEbxlHpNDPGUXPbbrVGIJ8hMd55vmkI17
I0kvl0vVEl0ZWzXgA6GOqWVLMQgeITFIy53EGCh8e8St0PAKbfby+GCxR+CG761SJRIehTDiUCBL
yepcDj72May2DeI2g9tKoz84q3RZhezqlLL6xD/7Vnx3WfdaZZkluA4ZnJHnjGXmcYQTYAZfG4HC
EEuLAzbpuPvMN0oRIJqiVNzqkNiAH+ctHgVmJabNb0QYJabQPfRoaE56j5YrbFmsb5V9Dc2yjlI7
6hkHxzQOhQhrlN92ZaNlwJkXJCgZUqzcM/IH9GIb9uZvU3TO1W9UHdbh08pshEcx6HTcXj+i89Ej
Sg1pa/uq6UCxsE+j/wayzryEm52dfburGs2YWhRkhf1ftMC/0uxSeL27uVtU+dubRPeoCOlveh7e
szFBtUiIhuJNjaNDN461/YQ8mSvjXTw0nFoHeUUW5nC8nXg+hQNeEP6iactIjghv/YpEgd5/ZKf0
BrDTJIQURjjaHUU37pCALXXAsS5797HPCTaffWgbZtBALQsf3skW77eoVNNHr3++26QvNm+fcFLr
LzKgWodANHw7U+3sOWIJYvqY6kBAlDYsbrTwMNABCr3krd5Me13wGJ+mlad4OdMOARA6rBdv0+o2
3mCDb+8swZgVGk6NwJIOsdSV90ww27xwqk7B+9Gf19f0Kf2uaMp8i4E/0b1f+30KrG1uT5pdWRke
3tl2/UEqFHB+hrsHPC7H1ASeOXULCec7flbTpMC1CGIGMpBDU2ZL5dz/hGexTC/D5DnCwHBp0FbK
XGgutWk338+Bj2oSvaBYr/LHzD/5HonBTTMUuyuxO9zO7hMN1ZbD4V+AyI1g2idWxa4KfWFg/574
kkSKxyDQQD/UR/1Mjq65OdhrCC1FAa2ag5V3pYT9zB0zPHI4mzQLkJNzJq+rbRrICmDvU0c2aCaL
1+qK6/CD0Ocr3fkN7SJ2d+cT+0FyzlP46p1bFGAFh9q0JlUl86th4LIrh5l0c1QXfTmfTYQiK4rE
nxt6PaWLaYrsMMG1fkfc4WMjQTr47KeaieffnWMfwlsliNMVKTYEN7CviyMHGV2gOpOs7CJpqRQM
xq1SmGw/dEJK4YZR23IzYRrz8XhhAiGOwIT2762dsbJgReHtxagysEHptFBE7QKFkX7dshDNYvNB
2O6mwUvzDmPY8l3yOZeRNmNBS21H7zj+6YcJtJntko5Zybeg+Cv9KTR/SNzs277TmbY8Lj0AB8DA
icODP69KvMN9XseoOR7NFxssY1j7Xg6PMexwkVyz7U2J+ZGjJ1IoUM/+twVyYmmdM0Gjk7xWMyRj
OsAf0/Xr/burPXVrjnwLUtKlZnogACbrlcXMSgPYzAFRzrfJFcqu3qGUYRv5wzSTVto/8s1J2bsA
3EWXIXfdEfLz4vY8fUpl+VuRX9EY6t6nuKH0Uum5iGksCDCsYuD1mhDYha8HLinWvcz83sqNSxK6
WRpIC9b/DGH9LqNrbFxy/o8QlRNPsIEmnMcdz3m2+uGkyWB9lRdLDjHFV5gwZJtM576MlwVH85sJ
/m2lUoVO+s0H1BGClqipqpSt3/MFJwEKLti1Rl4HG/VixZ41jvO+6AvT4ulBNhK1DURn+d9eUh9q
gbLUCdzxGi2T9lemnfbbFTnsdTQ1Ruq0ngpVFd559uSd40Jx0INammprFG2OUSNj6SNK1ZKRbah+
1A1C29qjg/szthEIB3DwBTppEgSN6hp9ztfw5CM9feeU8ig6dXydv4rMEM1h/SI3MaparsMTUlsV
TH6TjLUPyzttFEpXXGRo42FrmxGqYVEwqAONwTJFZAmxmQGMcSfqYgtiADj9VHbpnQL/sEX10Lpn
WYyiCqvkeFzzXQlc9PzW0uy1dMq81q+22/QCQ3M2E8vDrQQS/3W6k0VMMsmbt2QcM2dac2DPAw2S
4plSLrEKup3VvIi3IG5lUTIP0iIpVtHcHkb0L8vdg2AZZZrdEn05BXApJuWwOgUpwQb+rORF1j10
RSwMl13ZwmNNZCG5fZHpDjASLJa8uRFXIxDL3kUzsFrdOiEVMjbQL/TvLjHk3qyQrbR5itl1/bEX
CnboR9PDg65QGtkCAdbNfqquX6kn5MEF2fWOxp2TMpKv9bR33YzTUeraIre96x/6TzYbi13p5gTb
cyDggZTjwuORjhCSIHs1Wmcq+jPfkvNjTdgliiXKJre3DxzJD1vUQpez5LJZ2/frABDFc8SBL53e
17fWRxpbogJL94ABFq1W/XIJD4sbbzIbLKGdZvatxwquGTHTb6A/xeYoK2cn8FXi2gj+4hRA+S2c
fX4v5wjOMTKpC3WCfhBepl3g1miT3BknMLGayVSSynhtwQFaaIdOtU7E0IJnamPxegje0aRFOWYT
UqxoRnpTTcKxoxd/I74DOrJ6izywtIwohr9L910mQozDY1CwEYHjCRTyN1eKPbzNpCPjwE6CLewU
+oO7dg2LaNwpEZJbGiL5gUvryFeLwQnW7AM+Kn+QKHQGI6HW8MlY+7JoKHF0oUxlNxPiInCC8VkG
ixpdFPlUE7RYc5rApPlSOwB2UOY7JcoDNAYMbnbCHvPtoXNQ3fLFE2hb76f1iGAp9laZfCBJ02HT
UYeRaYDJzzwfWdVAqCCUDKYkHxKEdCnO8GnKXC/6wOg0JC9tQeWggJyLg6k0peZdMmIGkIfEFfmI
PPSfN2dOv+l7ZBL2QnMVowQEP/t3M7bYiN9LnLe3yWWK+MBgyOwzVnhzUN/KCcFLqz27nnVXOyjV
eIb2cYMbDLfbapi29ILP4oxygU8Js3ToNiyYxWj6pZ8m3xAIHlu8EfcZE5uDq2YjTqkwPTmTzVdl
d9HIKQln/BboZI5IiPiSmjErpxIyQYrBemNrQKhrGIye1B27evKryAyhQHndKDRkjL/7Cv/wp6n6
S3h3DjvDUGSLacX8JY6P7rM8VV/+dsUgKFHHASubpzD2t/viUVyO71WGWnJwxhCNWkaM8IEm4XpW
n6CRA0LEAQkz96Z8xqF2jd5dyLvlTJY7HtdhU6We4gis7ZMaU2sx7vmXzn/Q/U4cLvRSSKLcjK8m
eQyrEH+6ffNfllzhxatdDAM/DVmIWAXaSo/HSJJW2IiBtSIm0qlpRDCPpZuIKNaQ9HH0itIXVa4y
e4GhyGbSbjwxT+EOA7C/UYB4BR+5QADgIvI8CdVhcKm/2Ct/BuFg1NF0NsnbieXuMf3Y3T+/5AxC
ofJmXzONo3pCAx+F/Xos4V7RQuG4lqy57gaO7ycoRpTsOUFmMGk6Ikov5svhDt16La5DecEUyp2L
hXCdzkkYbL4mKEx9/TvFlovB58i2BJ4g7HY0DCYIXYHkbyE4UIDZLtuWe1MI1Wv3epkAjROg8GxI
EdRFX9+ob2T1Jhb6l0t1yQuCT4358bHZoQilzCHszBEqgVEzZ6kYt/0XOU5dQ87VtgnEYoR+CqJE
W86+jXqwwoY9ILLbNmsQ1qhIFbx5fB8QLeIW8YQyZiaeM6tvuZwWtg3Vx4YJW8akYKolCpA8reIn
L7Ujv18uW3J91lSVin8qy1+CsMdWFc0pD/zHjpZewppK1w7vaB0s+rGAj5n1Oub1EKUu54DJYmSX
HL+CvlfaX5P3HN+wzQ5jpoZscmV812oRIvIDcSSNs5H0S6wJqcBglph+4P7qgn6wKEbLxLIXmp6Z
AkRsC+3szYCzDRIYxHrMndKmnYAjJZNPscLF1MmRyGdsbBiflxM1xmFm0FMyvpKJVzEsFxJbtFo4
Q6dB/FStmnDeIYKDgbktqAScCcnZxKqe+ksPEZ+UHmme2/HjMGixYNULBZ40Flw36nqAlFoFSdyX
34hBulkgk50v2f4rRnUFEjX5h0/4Jp08Hux7QbO2x40awkCukHFrB7rKi6azKQRd5l5gA5+1wrkK
kVMJDXObB5lnTGLjs2jj1nbkR5Lu+mgqZnVlukzp7xMSIa0Bn1M7WM8i8LGh1ZbYHb5YtAx4+jAv
sgomDlwWo26dnmmBDW/xmju2i1kacbXc+gp6DUxW8tA1Co4cT7bWJgKhzb6rkeOOIbRWlYYVaR9d
vfBMLfKcuDcFw+O9OmDGp9WGinOUak78xvzQB5SHr/6mFB8YX9NAWkpYUpX6noJLBO7ODOHCYa/V
RASLg9PgbaAMWhwwM0SwpQu9IsRJK5Cx08GX2Lxow6A+0DkgNFsPfBeGQNW5ouiokZEScrPucLJP
ReyBwk+WsuahxUHVBeYgdjr6QgEKu5UCVwiueA75aWBA8Frtfpc5Y/fToEaPik9GddGabVbUKCfE
/SYWRN5RuqGQeYeuWfpueMCOjhjS41yB9zK52cWQjCyzNB4YTxtXLjYHaQn6dNcV1mUd2vXxM51h
c8utJ/yl7gflUGCAjAJMpOr+anY6n3Udr3LVpYdDF/2OMenbUznstOoYiu0m/NG8mZp7JZuuQ5He
JNZpcArWu/IzAcTJzOAnhqxUjQPKaklsKMuoah0Q6+CgLVO7ucgs7OvjFKUMlra30/HgnxSrTtEi
jNxpTOcFbnrtIdHwAkNfgJUIC99EjCtVyNAAZU629vl80V0h5VeG6V9tbevGVbAPUKozsXP0GoZe
MsB64IadXNBqSd452JCgEFQHjcddfinMgpx/vzTh01/OGe0ISxKm3JNDSEzlXhiNarrfS3gukvd+
VmweDBar1/pp8tPnnATaHfSmunSW+/jatyBgQBjHZhTgvtHOnESVWNX43hwxMW3BENfn5GJdIfTV
XOPRy4e59oUFOG1J1OqrcqRZI3cwfYAB78uCmn52WG2FbwyG3DnurrwhKu9oOkrLMC+AVT6OBixT
CTs/DDz3HPi2AG7VK6p1WW5vcg51dgJit/NFpQ0Qs7vO2xs5e6r3rBI8hGwjIFHyjfemKdvCR1Zs
6b8jrSh7YTd7XvSSdw8lOa3o8ZZu4LBH1Dn7t6IceX/EDI1m4cO5UkUY8UmZ/IxGvvI2HVDnCsHz
tno8DZzTz4eL/ydQc9Oa9x6cACL25IpoIhzf5TMllz/vcEi4v3Ek+WyAN3FIgqaCNNJ5aGFoK0Lp
EYD9lvieTbely+5jfRzeSooFU1RS8eDM2Mfwh3Gw07N8FzHQS/d9OtIgOiFyMSxnGXmNaD9x6MJs
0Jm+ebQyvSkF+W7qIaKFCACt7tLNExeQaA0QnNaiX/XWFKbiqCPTGxwuQNCU4bo9SOFqGETrKd5y
c+6UxdIltotm3lTn2zf+NfdAb1obKdrLVwpu2c/Qo1P363Z3LN4rwBLIo9tIOKKi5ppYqn7T627X
9977w43sqGdxhJL5+k/qQOnSM24jE+rcXozl6jJ6TOi6nPFcxLpj8bi5d0noEWJ3fnHW0HkNhxKw
SQ2gglpiBQV1bw3/D2B1gQ/Na6DfKQ5VVEYbgdjvahlN7aKGc7/iT8+pQUg/0YBIBACaa+sFEJed
pdMv3eE76iq0TdMOeLN6SaG0VNtAF4ly7LsbDdWHlWFVSb4q96CtnSgPY25yNkwRxFm2qR/BQZ/Y
bNuhZRdSU5dgHrZeCe/N+A1LEO70/BrphMGqdHLeSCekb8G7A9/6obJHnZru3mkiCbqQzRtxMo+p
JfYBrJ8Ew+ClmJ0lLrGDbsVYjbhV2PlMKiHCbBTG8vBldHv2haWx8KJTb9xbaX3WsyzxVh2RL5Be
gFWc+uWhSsERmHY5tObuPZjyiQyamlP/M/ciKlyOxEBhVzhXtsi5rcctxUknAj4v4/ruupPIXQBE
zmvUZVlIDkBqzOn0AZiVx0+eALutTHW1xfoc4Ll+njpQJrUMeT2fPLKVDx8Ug19slX82h+BCoB/r
QeWBTCDIZKSKcDo9fkjBkgCPSbNdYnQAshDE0W7+dcpZ9B54qfGz6FQS6piNwTONKTNq302S5+py
N8L4bGWCVeomz6UL9kQGn2ut0Z1zp4X3ezQrbRY/IVKrOWRsxaKV7lGK3k8nlYkfeYr+oB/r8h6Z
kKgo41/ZnJtTrknfdEDWwtyc45f5vY3UI1OSYrkI5xHAYkV8jAC9hHE6fHm3RZU0YwU3rcmwwQiF
9Re9wWtLggZItB5SNyFBWh6p9qjZ02lvez83RcbOVBrH5821maL2Pv6ivWcq2J0hnfminIfqUeL3
SHDM/TXc78BN4336Zy3pRxagyF0gMJjLWr2M/PC7dK6Q1WadM4FxYLzJNtBjPbiHnODT6XPkXq+4
HTu9h/yz6pDHE6C+bOzdSsbxMhWEj33WpMFD6dqZtJKT3exHSpjOE0K6O3pcBVSv5LeX3n4wT25G
efYpx3aogVS/9ipbRXfoGIR3ybdYkcUS03xE44Q9qv6GHt3AEuJ5eJhMgR7E2lnVyn8U4gbT/NI5
TTsA+5jzi49aAnQrz1xBUXfTobhHNY2vLCG3Wf4jQ3Fn9+QrIRvd3xX7+xDy3cz033cIkiBz07Q3
8k42eL6RIoYG5M9mBc18MyhIS3egavz+AM+/PflzLOX/DMeRXsvPzXVe2totFqQgez8OBQs7Prfm
OdRvwUsdNdZWjVI83Y1tpMJoRKzdAmkxBVIZRvJPF/3t+iCrqKs079XPPdb+LFjcy4+xDUixbUaW
GLIdvH1okzITvecHwZ+1Dch4FESQ1b/ZUQnWdWxtEl5ATB825x+LVXzCJQRAAkPBBsKQws7rC7UL
7Bp6P+BsNtZcOCn1nUc1DHmfsiAzHhRN1A9l9z6AL6Sde4tW82VedIcD7QKrnxv0qrkGeUSiJDBY
dYBtNubqioOxRyJNeeZNmXJAkfcvO30A/rRHilow60Xe8KHYW7KUFOd59LI6IMI3QhRDXSLLTUhq
ZIVRQjW4u2utcDGgOWSr3O0IRjXAcwEBoqo7VPkq66lVJPzmLQrcvLSo6oEK1V2M3tUdToIX2jMA
e8QmuzRBaBEq7r67pL0ZG8mRhCIr4gSPdUCE4r4EyMaMKDSEm3A49xINJclDDwYeVXNu7wsd9JpM
fTr3WcHIgCYR8suqDjb7SddZIlVxNfwPKL9M4dyhMxdnnFQcqhTSfJJ61vezRxDzcxLXDifEz2B5
fKox4v7f0W6XPtDn6YaX+wUF9ZI6iIlIhXbKcGBx/tHkwBgKWfxizb79GAwmFGvZr14Jql0gzqTC
vNDWCol6kyusavrIpVnTo+OcRshpM02lGHrwV50kqi9+FeLhytoMbRsQRKMj4goYkiRlf+ti+uW4
jwpx/YhqFdG011Bx30kDJozcqeOyzz8EJSH0GaA0QYjirwumNFaSaQW7X24+Z3plEg9P3n5856t6
dxzcxRMPog2O79kl4m0kPQsaeeovSE6rc9xa5MqjMvpXjD45jYICRQwgHEbveXpPX8+1at8QUB2G
wbYV6EJFYMr3WttSmnVxv3Vm6bYv63sJ2uGDsSbCNZg3vEE9ieGQVV8DLlrLwKe/sid7KPxdFwfw
92iKJRsP5W1Xhnq41+716FuDMjFhi+ah3eGxvoCPXD6N6gSVNdupoa5YcNCWoQ/5/HA0bDAYhpHD
XHhk9bTLEJMVDq5FcwfBFVQbkHc1AvmA2PXrzWiTzhAEF6q7HOkRNvUl7ySUKbtPNLy+h/cVUD2B
77kGfgvwbqtutXCiALe2KVSwtCdQe7IkC27HsL5a6Zzth0pEHJAsHsEpAnoTr97YrjjiG/tFEcVA
VfPwm0P2oXgWI9NdRDJspz15sVnTCYzrcUFg5Jm8kT4BWyDwJ2RJd46hi1SdTyjMNL524vn+pHcY
iOLgh5fd0APosDIUzCkDxj/+JvJG1QZ35UPGsyPOUGKAxzvNSX8//HJxjfF54JaEqpynYQ8K+ngY
8ZoU8LvMrc5rlm3vScHp6rnw6NmHJC7j66vSYtNeF2ZA01gSkY26MEIlWQB1ZKjR4r95/IXFC3+1
pzm/IdaiXq5BF43LNqxX9yyJMDXI/Zm0LkaT9V6CTuXAArArgs8zWwhUu06hvNWRJorx8qVVugzQ
PbiMf3zjPxiAK3DLWxW90MZ1npKUrDWXhk8iO68KrA0KTJDDdvd1nDT+EixPmBRMw2Q00lm9CYAK
e5yrLsNLvGq7xVTFsHR032kGYRRLKkK6tp6M+0I0amun6VXBcGLMAuK3FL3fmo5yVjJse4vRNCTA
jBnQSbTvb5rVMDTWUdsVJ+8PufP+16EjLMzliU+xBoX2dzw4iBlCSprJtiN5rngj16mMTexUtoql
/Gv9Kfd+IBuikXrE5cxJIv7FCQqjV808oqjy+TGYK86zyd4oBflEMjMtp0j6xQ7nMUQt0KFf794m
qXUhjmHEcAlTzucgLZfBQ4dKcSCEuLezd0ssPkgcfl5VWlirOqxUMR6LbCIi5jk+sDpl66qSVEp/
Hppdwu/MsfNIac3y2s5Pdw5fiImSvBXqRBpq1kGTahpo74FFUceQZDjrfDskwTHtRG1lPyoHTFEN
wg5V18/bIHP2DKcC8ZrzxszIEhur3NWsMwAgUNlwuGgNM9gkgdUakMkczm3ac5Gotvq/nPUuZhjw
NDPEralF2Rok3pr1esapHgAe+zNx81jbU0RPB/fAqjjRKquX3cy97TEUjS2uHD9OGIkWwKhd1kbp
PMH5OZ8MIvSAQWm4c2N9SMxcWLPHE59m34MmUp3fh27+ZePoe2e+Ng+7RV830eyG4480i9rdwso6
xeE3gf4m9tBKNLg9d0RTszRxXwha0OdCQHtmOpBfoKXNAs3LRmhtN7LdTfl0wIf/SZx8uwBbdJmN
jP5XFsEWsbOHQEai7KAgoQQPN41k/oEa+TCaiLmnGhaqZEKlsEwEER3hVYZny+2rxQfyvNikgpQM
U8XkTUR2GVCWDKEh6pB4Dv016LkIRidSsKiqDnJW/QYqo8yz7aJGZQxijTDkCi+RmOS6jXWD5c6A
uIGi2WcXHAthb1IfhxWMVSZzX60Q91FlO1KUldhIcTtcJhY7BbGLiv+deedC5Iy2wjq3spkrwZRJ
/M6myxkEGtPYTTGq9b3ef+ZaQQwYX+UClnlVKztsXa9af70mO3iR0VHs48ioidQ/w/Ym+LffZnzn
NcMTy9uHtU3t1+u3OfVo0RoDYFFZVlUr2fJxrNVqlfDXzj3yxWrhWL1lPjLRv6uZweEe97++C1t3
WMdI3+d4YOytMtuk82N19kG3HYnBTJ8YetafyUIgT3QAmTIedcM4lgppvQNfbNqaw3OQxWagatDb
Vn/PAxQmJEqo5uUhugJosahCKoKJ71KHKdKKDQ9ibQ+ecqiZPhx2UY9KTmM1oXqJlCfu/4qst1rN
iEzX9m9/i6cCltlPACdLcHb1s6w5ooEG6IyNYh4RKdRLnpniTndsJRlN3F69ivFIrI5eH17FHqG/
owM5zCtM4i6xk04+5CK5aBqDgrAHctqAMjeuQ+qmKNWEdt+6UbpBMvyrC2wNZpYZbkmGA1e5Q1bU
g5TX3dW0Vs9VDUXj1Kp+KQs/dfn8n2scLaN7E5aSH4UyUMh7Hqz60Jz3YXmVE0LHdLOTNjqK6D21
H9f8gMsCYdxKQILDOoxqDr1dBMGn1xgFr1Ds7nmxJnx/UIOO2ErwibAV2FULNh+DzLoR8rNcpp6U
qAo2/IKXXixYM/h2Ha93pi3ygHL+5QgjyC0W1OZLGA+l0MXIXCpF34HvCRGz+uiLhPugP7/WTMrw
jWfFJXBmNiGxDTZA3euch2ezeeAbDa1x7YVwKI7ufoYz3G3oMOyqKpYYj9G1GxOSaSuA4+rfIEDZ
FACfF6jpRKpCM3Xgav9haJxnJV49AmiMwF+uplA5DoIzgc/QUAXFiDHbepyrzdUYSGTeILTETXyy
HSz8PZSO9ur1XnAK0aeZRS32s5LCAILAF68R8aH1OizhvyqO8tBIPMSCVkAJDSZHXKW01HqCSpac
hkyt7vbO783lUBwvcO3SnQRNE2mvB6S5WJyNxaKtBGEoCkfd2Q+6VC/i1qZNw2nRiMC6YHSKrOx+
cqCF+1QXhLtYOB+wPF6V0XayM0MziYPJx3Dp6gHC0SvJ4FEI7Saup8m7cV72HH4bqQXpgZUSiVEy
lbgmUx4UwB6XmYZPn6LUfmDXph6zOZ8OF3Fl/1WU8FSqhvymUYx2kGH+6vsl4bpaAAXdRz7brTBR
CMThY1dtqgL9rg/knImtVbL5gZcnU76EDuMT0kP/ncJUoDE4rwC7jsdCwRlTtsyPQbxD+C+Jndv9
R6JD9/3f7smwDRxg6vgw79jLF9IcoseD86qTo/uudB87mS7XjGLcliByV2QQpdgtwbEbMHY2fT1P
YaXVyuJFkJrhFS1svZAiSw1PLllFiygeuJVDGHKX3QurZQMFGYDsJIEoxVDP3yXzGDg47mc5eqUw
zMl64Z6KTINuNB/hyYs1AcOZqJOmCHr5WcE0xqcWQYlGB4nzACmWoXlcsqHm20pDg1dBAUBjSUB/
YYTZXK686c/cl2r9OY9/Mj0R2HF5EZkbkgdb+c2z5LhXjTSaFIMxYUWJACnhus53tAh75VCZW3Wb
+O3/r5rgLloHMrjBcmrxw9noX41R8Bujm5yn+vv/KO2kopGR6UOtT/tZL7Zb1RNJHIU27j4xhB54
aC++qYlZJuuT+7INPrlf1IpJdCYocaMxp6jZIGUabMeLl6UW1qvHuEuB739aGcrZ+7tpWvUPQnSC
5dEx0sverJtFeedYhqoTI55FAPYyP2zPMPlOnvS928LWCEdP16jynsNSivcCcqvwDinpS1gtXZDN
GpCXl2JDUK/ZJ/B/C7y6N46kn6nAj9u4TWcECk4AK+mMFqtj/g6lYchd81A/vDkGW7UsUzPaakY/
pyOp2QIf2fYYmfEtXgi//g/fOwxrsvDo2QlXyxKo6KAcGNtwqk+bKjfF+bL7waWSfxb1CLrnszUM
vgqh5q4yQ4iVuFS9xYizJs0QlzE/MEbLu8mBQICb2Qzx9CuunMkRDu+XOXuccMjw9+p3dIw6Kmix
4khdTVkluAjqpjI12+QYRUjf80M7ybo3nQvYOYOsm5vgZXsKzUAU/UajnBlRRdZ2xx2qb6uVrn19
Pwsj7btfz4rTPKdGtEarNgMT+MJJGNRw+ZQZDOaoqW5mytFH0wFxVzmpifD2BhHRFKawKLObotlp
jViDCY3y+nSrX1PrKClEldWaaomDcENbtGyGLruhFX4Haj7DMa/F5zuBoMEotCqRnsPmUJs5kwvw
KmcBNVg1J+Z2B1eHfUBrBoPnhP+LuL5/8FcWtbWWlV7gqD+CLa4gS3IE+eI/zyLGNQuUVWjfhPMa
bYYCIjMNjGG2jRPkaTL1B0LtJG5mxyIt1IgJTHYmGum5f0T3evSIVCLLBJPUpOfIjpzf4sEkPgaM
nfaypd0vtOa7oXzKw5yR12gsNCEJTMM3Sa5yNO55BPVHe8mTe898ICcXg3IhXCZEJdNjB2o9D+9o
ge6S048LZFybvcRaIsH1Jjn6lz6EcHFhgMTDDluNG+GvoaJQ+HEnXOaU/Sk87+naIj2+ijiXe+DP
xfQT9bwHPlCuAiqDCJtvs4mqEq+221jfl7yXtnqwZSiRg0qwi9JcZzbPvd00fD724VnqYiJgcF48
B5aTCdqO7k8jSBG3pX3sChVO2jk62x67i8KS0nGILQsYkCwORDH+xq+JlMa/wv6TsKlbRNFo7N0V
RpKbS2zKlACp4NVQCTC29bJdAdgN9v35uDgVkWKI0AxlwiO2M/9dqgVQxIlo8JkjD15bWPLLTr6c
ApSy0tKO+wyOUxXmdJCpmocvemkw7qgtEVq+SrcHlqdkwOdwouj5sTHAmuna86s6ZaaDrwJcVv+l
gHH1ndk0tG03iHsx4Fs03GQKRdi1gmj6cwyjxYkF943NF6JXGnHfnUyc6c79PL8p7P6VS+xpYtq9
qvcrB+Qe3Qr9VFB0WaZMi4Q8fP5is3HkunEpqn5AZ3b5CPzaQHt3vfe2rSEd25xr9mkIJmNlKo46
AgxS5KmrTW4Z+NNDAeaihCbBDJdNkaatal+ZczUmXnxvjuZChWFbuuyeoQu1k0Ce0eI1o+5rNIQ/
khACfT5g4A5Bss0lAWuKm6w4WNCcbh0l9C0SfIGBv0XcZmWAJQ9iu1dKH8FdyVyjaTJSi9E9PoaH
TK9yqd+PEwjE5Yrz6SCGaMRFo/kYYOus+Y0AA9dHYLVdkn7dhtgfdHQoy9xKk2NpyPBDtDk3UK/K
EwRP+A4FKBH47qwNWhbNDzq2xJt/50LYignhPeRK6TECmY0n4jNrwFSXYCOzu9LQ1QwyawZyg37W
OIvXZaK54VViYu/tzsbNOmjQxafMlToplC7ZC5w/5HmvZ6MHiSMRNhh7NBAdj6jr398sTLIbA8a/
Wup5kviXLwY8BHJHUjIc0Cg2qNxiwMCXapsNt0toEVX/9R9kVyHMyegZlp77i/u90VenBEzhvvw5
jOVNfkBXCB9wvxPhemoPePY42TN7Zs3WMXPCs2WTl2yxf7bQNaFz65AYJfq1s1AawenN22BLIctb
sU3Kh3AES6OWG7ipPGvZZkTCywB+Aa9oGMvTcMTH0avV6vavnVnBhomHM8LiZYIkKsGfuDIZdNY7
Zlo1KpFjGsK2VOyv7LX5HtgmiWlUrcMUJ4tP+CCTA6vOiAsM9SqvPq+5SapoPOz0MFmVSl1c9GlM
B+A7LXH/nDuS/KiP28DR1Dd+cEoBReKzWjhBCwtunQEEdVZGriTIheM5VEXexptoaTn3irAiM+u8
sqakAdEZMNAtODDQkB4o6XH2vUhcD2JuaOx2kLPIco9i8MngVO/NzCXc9awwFB14m/7LycoHf6t4
+7nIGXlIm0Q2n/0QenvRGXVcHZ/P5f57e2IDbDb05PqOM7O4wHdjcPxKQ3wM2rMA98+m6jc7+DCx
uAhxly72NNqdHKlDzBmCM+n3P8L2RCWaNeOmMsrGo1vg2k6VeCiImhriyRA+QHL+H+GFiWDZxVFp
+9DSLdBPrOnhJ+OOwkMHNUafuPcG0uDoGUjBiUJVPEfRXGUU/VgLgr/va4wt7gtcz66Q9VeuDdHe
htlE0K2a8vVSUSEyz4qRB7UhXo1+7oSWxP645ojKss2RgmOZcot55tzlNDCUovWFdpz8yPhsjmAn
JYSx9gqGRM6VtkbyKYNz+HF/+qfUuXoxqTKDEHqbnwdoNUIc2mPZXsL1lBmScbxX50eaOHeyrYT9
u/FErQJFoLYRpr9QiwnrhM9w2JQk65DZUhIZDSuV+3+KwuweOvgV41Hh+ji6VHygVMRJ7oXaAtUL
Py+8s9qwqaWUcuIKtBrnOpoM4t/QKX6DneoL2mTZ3ZiA6AqEF0MQXxtvpNXFEsVRsOqUu0FY8UcD
RRPEcSfI4GecrTqBa6FVP3/9tEccvu7eUB1OlJB96zu1gOpiE9ii6NsTyI1MTk0mRfl8vKrCiJid
34+C7C8ZikCQi+8QUcgqucoA64580/bcs0daRDsku0c5okxrcVlabF1IncKoEo0cngJYe5MHwRL0
uAwVt/y6erd+QGmTju4PeT8qzSFKKHZMkEj7gv51sJfZL1K6UeVDioMt6avUrSEHLzjUZYvGdmox
uLcxo3OEvw2FU2LdwysBgvKS92rc1eMA8pSWDDKIdkFPOhSwQI0kkmMT+vjnqRd9Ynq5gPwlw7UM
piTf7o+wQsaZ/ppwC2dYXMAGbUwWA7mGXMBMCHVis7lC4kfg8Rz+P3qQkEL5Lg0YRCl3WmwAHNE7
uN8IR8N3Y1d0MwsHKu4IbTvi1BKR/vNpXaQbvT3dWW9ksL628W6TL/1FepfwKPzLaxKOQJYh0UYg
6VmWDl1d2ysH8AyD1+gM9U13SlGjYQsX79Sb/wpN/JujIFBVMYJ46PpXLcD/4JtFIliRW9xDhUbw
xW9qWrvD48PItTEfgnaUKsVBtB7UgpcuDoBrcJYGgyNhdiMB2GvpYkdsMK92TwegQ7u0vpwncG/A
TOa8rpzvrtxyuqZmDt0XWhvUMcjYiCbeamV/b3x33S0yPJdphDZdB8oJwEe3jr1Xoeh3TB1h27P4
LOH/dJxll+wA0c5BqUPUpMoZ/UDPRcFw/NSGJsOuGyYNvVx+bVl/0vSNUQ9rH/sQ5Kn5zwGBos49
TzA7q7wr/lDf7pH+X3V3otDpvnUpfM/oe0KkfYEXtwvYhJrwWJdDKhPr8/d07eGivT26gGwvC67m
57QF2pPTvJg2cfEBwP1dYhe8J62WV5EPwC6CK5KoTsFb7uc301yOOZvoRmoORSv9wMvnG4X6nhKV
aBbo1lGCnko+XpckazNFW0YlU4meGvXFSjdWILjAzREm9HGyefQtpP8VHgWacNAX/4tac3lkCmWd
UivcrBTMQ1AAP6TMGxUgrnFDG2Vi+K125E8eaofhRLPUugmHZdXAZ0DduIUbAfBvvnWJU27V9KnJ
uWeRfOybYEsbzZOkaQSD1xLJM51scNPXpeSHJtdpXv4mj4mT4AOvhEufn9yAI5eXR8cS1GHq5Enw
15cbBxOB5caKPHnFystbV7Fe007imiDuRxRAJbdFuC3ruc8vtqzzq0S009tjkKkl6JyAcQOi7XCy
l0hnOYyOZR4m2gTJY1CZA5YDu1FsZoCu7EYYWyZpuME22sOe2VfdgsCj5nHoD7dM2BgoGkUET0LA
gsAKonAj/OwFIJcog4rkp8eWK+j5vJyOM1qoTBsYYxnNzDqtFbF4gQJWsCBe0wGRUxxtjcRIvRze
0NiTvQN89WSgoJyKu3TfazA9Eg/PTDzRTg3J9qcxk7oAnOxEHQM7DuB4xaKflJ6Putc9ULgqcfbJ
7TjUx/PtasgdIGY195rXvPKh97fIAwIzInLYm28Vm5OxJH0k1V5SvYI+qGNWJPzYhXGg6p+bBPr7
u/zKjesATmWdWFXkEN9lyF2dZS12kw5r8edUNdsf6d1dEyrNvtE+MzTIzL2dg8SpbRHWQvIcCwBe
EDNlD/A21HVpeVR6yDu/2htPjuMHtz06ftyjZux8pXHOe++XCw3GOU80y14oR4ssI9+HDuANBP3B
qN8/6qsYL5bxGusOyom+clUSN0s7X4/KaccyCUBpLOH4lKrQ91xxUKIiDg9/fwoKb3tp2imHJqdL
zOOG/wJpOyQeNynNRQX5KOabLFKDztKrB01S+OgCwBhuFjB5L/2L7et2nztaUs+lMgHIFdxomHno
7tlyFr34hdCm/7c0l+o5nEtzbnYZKK0rHHIUBh2fTIfPnIjSWHBTkhHODbPNHLFAXO6ERtUf6Z86
lJ2mNitgnffTAA/DJxA+wb6rtwgRmA4pDtXjdYwc5fWxKfBu7g6dFkPPTCAB2jPQ8uczElAobTX/
erER47x16mrzWmirmsLCrM1M4RZBNkr0e0h6HkBcTSkXlfi54X0pZqzfWQLcmRc7cJ9UR858lJ2W
Ck6YaS57y/ip8UGSAMydxZGyCZudy99ugNRWvXcCqLcHYPsuBLY91GrQLOdc70keEqHY+vzbG3Ex
gyFOmNoKT0OMPs7iBwpTSUMEDFf/KnOaoZaVuf6/g6QNcLs4LAGlXhWo+0htZKQDD2ZuESozh3sO
5v0fITCT/G28LJmKQ4Z5AbGf8uDyMX30B5yfR0vO6nUqHLNb/5FyPxRbl/ccwUF8FUHf0PvhSYwp
eKUTFlaliuGdjxkTRERpOEfwpqAS6Iq7DJdrytRMu505DiqOT69DbeysbIL47RglvcPvc+dvaKCO
i74CJuZDHg7FB7BDRV6DfRHMFU6KbblkOckfPuzTAHL2oSqjdUUklEcfsCO7hENYT3mVPjHtcy+5
Xj1ShI4l6qGTdimiBSDDhuaaRGxkiG2+bVqhX63FeGm/kNppBq8NR+getCh1wmOKxAK63nNJSZxW
4W97VH4+7l83tT33XC6hvXKVzFAwsRhFJ21MdH2vhqQ1VKwvYY6CZ/ZMBQ1cCyTFret1zLB/d3JD
cUwuYB6Iw06Uzr9Jb84fJczOwpX56aIe/c86ltpgvBGRqJtgV3kvgLueWHvlJ4MihrPOr4NyvaFe
NENtOtQHELR45bS4jVKK/EJBpoYS4MBW3jPSMkPFE+WwUq9gFRYEPiDmUNKmWve2Aj/qAB0bMZw8
8/6nhq+LVhOZTCopu+r1trOdLE/gcu22FGB3zyai1A8bmom1WTeE+3l7yuKPh3VZZUsoJCG2mNlX
mIAok3/qnx8WwjQ4su3AmFAZFYoxHxxJLsMbwQZd8Vh3VXoOSf3d297UhHUtHTunlmcQgSs9XH9t
kPrpcdxE/CHccTK9jv02GUm+pSwMEaHDeWvwc7gXco2UJN3++eMooBZZmUTtEPo2JJ3KTxxihAtp
ncnb7FsUuk6rD5jh+jSRFNedc4tOiCCu+WTWBFl2D7G0DjWb+h+IztAazKTH0Gwmapgck0xvSrD6
/loNslPNDMY4yy2hKQ71RMBn8CD1F9WJJAoL4Bke+/KabfqKsl3Kz7zV/+QQh0PBYpa1Ssk4uTVC
69H5AsTNcT89BclXVDHY1O6fXKzXTt7gNrPgQ0AGcDzz5BY8m9AL6kl/X1fCV17g3EdCQWYCRnP2
ZppC8QgTCJfVsGedPnRO1xLY9f5JQ6SqYSjRLLBrwPr8HJgsiK0TnL2Og9aYjjyti5tTCxGQIFc1
+OskUZH9RHMLgYtmYlqxCWkNU5nl7qsx9nw7gp+JxAb8hsxmajeyQVANnZQP0kAG1aOrZ4kxg6/y
ekxhYQL7vdbQZMthbkXGQctey+60gFLTVKRnFlhfD6NrW1uLxApbdsUqkQnukoTinC/9Pqi5vWkp
Nb1OoAWweg4irDFWPtelyy/jD/KON9XAHgs/kUfwpyi1/SZF/jniNkbDUose8w8Y0UUVb4foXsfM
/AhltithvXat3iAacGk6+VlBxbNZj1nuqp5A8Dt1vsyM6ugzuxKf95ZvjqUhoUO4OAidZ5EzpqPM
S1ZGkefih/Elteaf58esvFmttZPUB4ibAEXO8z9V+U0yqoyj29URoz6M3eEEIx/CZK8P5N14R3rx
tStkoZi4ZnFkgBtGd2PVOjZFeHy2ZQ8hNYUHvW6XpoL84EMuL+chwS65cbmh3f2LHN9qhSg5H8M5
eg32pyfhUq1MflRCVdS1oqsN+xBRtKDy+5ycW4niSMkewOn/iN2iRdcS33trOu+8pbByKV099+jo
IcXAFmxTMdQ0VlwB1Es2ILDELZLtdDzslKgQ8wNXmQzmMDEAXJXdB6zykojYFY4IxW7MeLRm4iGS
VSEkOuUaQtlmZHIUd2pGN4XmuXvkH1drWEzfThRWK/rKNBpAvQIr/HyJMTQU3zvXk2aBPRSvGdg+
dJIFXu7Kro5cmeZXZHpACugkFcK+YKiZ5/Bb2MB/TRDKzNYj6iSLaioEtJarj2tjz8sBnTx1fpIz
mpmX2t4hRv9W9uMzxBTpPzJ0Q7wgdvrCMBZ0AI4kqO6YCrImn3IYeVY2juHhjDEIeAGJ+oL8fX+0
tEdJPCLDLQ1jAhqUczV3iCpKj1OyHIaK9E6GL3K4qQVAZoCPgmjXWv7gMVQrwfcQ4MUrZspwxLYo
UAyK3rSpAuOK62r4nlJBGqIessRWuK92lDp9JpV/51S7nTD0GnGfene5lG4yhYRJ3VYoqAzDE5DB
IB8KLmsJyjOH1DKJCD9M/nk3MdZGO4Fs5/BC+GpR9fAQP8n0oAAc0EVinmGFoBmF2BtgsFZk7Cay
HTWPVYsjunLhE4UUpukXs4kU7YwFSNR+A7gy0calcfT1YLQO1t/L4W7dSouykj3QguuReFoEIyXo
OzCrUvsC2YJmHtgaPaLGGYJ3Yn8SQ5NRq4VBP4FOcuzXkERdXVBOKXnWbsuCr4x3jbZkQ/P+ESQT
FQaFeCoqx4A2TJLUZWG51fRs4a2P3WPtwIOFJ7AgmUNSFoST8oE66YbLSE9CexsRI0NiSZQDLN+4
3rFEygYeJzRwxmVz5by1n0q1iHJ5UIBPi48gVsIYsXfwn12iDzfH0HPjcHis2I5z3bHbjQzeuE+H
v79+SQHOYoGDa64xWF3i3iC+/D0culZib23GemDsAwfrqBu57ko2CLqSkEG2xiczch2wDmvMW5PW
JX8WwCanXYW6eUnOiFpBlmNKecyH2f4DaseZ9aF0so9p5Bfj0+KQ9dXdNvpDXHYGjQwKpNYC9aLZ
X38n7jUIgu5zQlIAEw9+HRwiAvvpbp+Ld0XaCJ9PbP7yfdxNL3lsOWzs8Y1FvYGQ2vYn7Wpa07U1
4hBtXraIbLsMGcDtLJLBE94W3fzYQTZfyH1fDBQrfwDnAstyLep7hY3WufYZU/cRLhbl6cy273iT
d3/eoklzrUSEgBZPyfQvuQ03mkO7ivZkG+IVry4IkQEFfcTkN2yEN9JEHNmrQGhy1VCa3+O4VHmL
XVlNuJeoJR8MRoAsDlMyDlsQEAm1EqNz4FWXMlC4Sf+03sEqry4wodLl8OE5H6GjNvz1vGWkhLVL
MnmaYGCFv4GlKLs2m9aAwm6urdCLGwMYHkNuo0UXgorKModuRzKc6uhe1nTklsHy1Ub2gHgG/bhA
VEFPf16mTlO4CKN+yAL18JDXOUTljrvuQd1NMniLZUUvh/TaS2bCbLsQeYNsC4vM6SambDt+LPU/
gXB6kqRRaIi7Ch3ZTy+9kJ8BDGiVHax/umwDH2CE/teranpu+N/s8sUCP6DF8wQnHiIXP7uMC3zd
DmnKAgkruTpEXWhnpkeivkrqNAv9Meey1CVJHW2+ooK2mpfQUI7tB3Dxk+hOWt8VOCCkaiylHnHG
ekmhGODEaW5R0KNr4Z/t8qsZRQO+JQjDmfr6Ht4fFbg2wpPyec5EeWyJ74TSir/EP3UulxG39FAk
cEP57s4NBDodL7PomJJ+F0ezk81ZqhCkB1gOWWIMQW/nkK7ylwpu0v8V1BCmXdVEslc6fEyDe+qr
D8a+ifvr5t7Ca2QNOnzhedeTUzU2ARtFJVExKu2qM/nzeXx7E/VPVrCHpZdfixZwHUW/uNGAsd3Y
19ZRDlsiBvq54CbivM42aKctkGGADSrGuG0phGb8OTwHvXLynczB2XRXt/V4/9Va/lhxPdBJ7thC
gzUlR8MaOtbhdm5AxrZKwQx7YMzLFyfv64WSa/De6LVgOQBwhDch0PRe5UYbolVKry2Ttl5Tce9R
GwqWmzIk37w1C6d8Qg9A/SDJRIaYPw58TVD+qWta+HoN1xe3gSAvgu2ZjUMHXiFriWaRwwWvdulU
iadp6srLPQVBtp2kl4erIwgscLLkGFlrwLZ/uESdFFVFOkDFUoj56MikS9O0lWM04MLM/CNkSXvs
JVaj6cC0Y/MFiQ0QjVTOaYGXJbfSkGoqvIkPxZjXEzF67kffTlxuLxH+poVko250LG9nLIza2XCA
+Y8lKf0sPCcYbupOsH/IZiiwkkaJFct1mI2wtNyHwMX/gSA5+wyV/37UJ+TAiepOoC/CbQytXnJi
cvgog3qFVJYXijYoJx8ZHhjTFYPp8vnrL9Nyvddd8vEx8nFqgdC6rlWwWEULUZffOWnGOELbaWo6
NG1UiRgEikG0lLc90JIpos2XkHTmi2boxC5fv0Du/9RsuVmZizAMyhz2N/mYcvDUGwmJAVkFvVrI
N2qcL9qWfE/SXH8lnDJM7TxlS6apx2ktnqqeNc3cPQmAFqsQ3ztNlrF4JFIDloKxLTnDRzylniUK
MsHTiCjFSaY9oq1w46uaNsUCya3cg59P3FkMPi/uvAXDrjNA3TkcehNT7lUYYCwjjJGfa29dPMPR
nKA3oIekpdS7E8eohkza4NV89SYAl2fTxvDXGIRSdFmLt/cJVe5/O/S31wfWZh0amOHuz58obGVM
DsJsL9O5dogfq0ArIQ6zZOiLS9RS/BTFluE4setwJ/xKCTV7xWyjpsbfdvrxYmGhpgBRuLa4MWFG
Zqzw/nv2S5KrhgvrfaMO6HDQqBZpGL6dbLdKTGpc1wkCiCC4xF9emdbJyQ3tGaP+lFFvc5cdNuAy
RydWF/NgBuS3lsFQGPnYJVs/PgM/mplJWD1jojcxGLQu/alEF4tf2U+yJ9VtWwdCPCNqQMyURRWk
4ZYrNYbrnvJorn5IfbzSAzkMPvER9/6WlT1yKhHX1BEqyB63KuWsVvlCF8TOcZEPJBWZQOLMO4py
n2F4vWNHJ6KJt89ZK/KqSNd9lQMvk4Dq3fcLnadBXZyrCHAZSqmeG+fvFC3zdhAuDGr3ZOEDJ/mO
nRnRUq75ZdWeHOR4WnJI43MEWhlYcRKLW3xyB91I22m/baMruCI34m7U5IvIyG4AhjSqn20D4y9k
zt0vNi5dASAY+b+tK+Ks5KaUVv63ueWdGMnhyjf63zvXjj0hkMiR8QQDHqaeuq86ggAeimWrf/vb
NVRpAq8+Y72PKbPTuCQtwxUF4uqOpgDTTV6o5ik6VXH42gHQf5VQxRvzYBAl6zYvSqtw2nue7ZO2
GONfTYrzHfdP41lqfhy/Fx7F6IYgiiM0wWZf1FQOXrG281zPC8H+TwbanuU1SJVuXfSEaPNidBpJ
qqTaHYFxk3cMJdRwXGj08XjQwqgvvb6B0M47BzYIy1MoVqq6Xu1rnp/k8RNwFSAF/2+uYfNxEj24
AWchSzBG5o166CdNDgusgLEjhQ8K/NwIDpMJe3irwTcyzX6EP6TqXha2hJkXuU9t30oeMBpZL4Op
tAjkYqwe26JK2el0KlVNYyGhlrlOkDBnCWIVgMH20ppGeZCyhUlOcX4pwSLKXjHySJsIzteP03Xj
+aHKYFp30ONrEd8NVfDssr78wDAK/BAUfRIHbCVZN1VO+3CS6jFKpfRP1xY8a5+DV/WpuQ0T3uJP
cl9a957o41r1j5nZpnGXn3nqbh/b2o0288+jEhT5fi7v/MWaJiCKlLlvstuXyzP5itjPELLrlXR+
OE8wRLqWoL94mtTf0osesRhUjKfC6/Ytul2LH2eJZjnNWddwQzKgD5QlQRwWE1jJx7iRpaSkMop7
l8kmuwaLrORjzj6gbF44GOXia8F9Kr3ON1GLMjyIHPXD7D4+6jCfnJYl+JjBKrP+Lx//Dwj5kFjK
1h01K9ZGpANYHz/tKtyOvCsX9oX+KexZqpeF8c+xbLxBdmMwULQA+uiU1v/tMBBb0Um1tm7VydTH
xwAy1cwf5Pg51VaK9H2slXzk9d/VZSZz8xREnNeAc3y8seDINvi8k2haRwgadKoYYoU+1Qe+PeHH
OEJ+WPQBWmogGLMFdq3biPco4h0hWzzmR2kiL42b923K+pqtU1kdAscdhRd2U10EhNSxD68DihSl
ibK7K27EUuOUPi3c+4o+rLkOjPcnMSq2oRukMOimvFuYOcc70L/ksFBzd99y8L6ABX5ErK71yR6k
Gp3ieICWABvcTZSJeqJoKHUKGDMyG0OwBIlpFVaaCAtRkzphuJP9q/1QgyVAgY20gE/23sJHYmrW
+rWMqPpr6mE0lFC/jjfJjZ6XMycWJf77k31/CcLbEGN3i5La6S+rmOuwJX/Eu3GZU8jymhnFg/qx
Qgru2VLtVHZ5Snxu8oR15PmcnNfzRafvJdGSSzKhY+ZmsbrhGIuXvOAegIgj3Bp83E1xZgK4uUb2
xrkNbcjJ3/WWupJ0WtTy16nDyh1Fr7UpFZT4G+PvbaBrl1Kx1A0PUgL2MYy3J5vgOnxHWjS61HJM
ZXMXeU9244JyR9qB9eGhMmLM3q1/byo2rhF0s6sAaeX5vbUo0eICIqSaNJrRQfP+3phoktxbFhyY
zg6+tmN6jCAHGKDWttYEQm0Bd3B2XrTFVct0TS1gKa7eLwxzCSmxFoVMTo/Gq8xaIk/iBWpTWdEP
xMOyKpHi49aEXOa4AIK1YthlUTL7M+P7HLP/Ka+s+mkZJRWTNyNipVWw0AIrSWGx3S7OhkvZ2QsJ
dGZ7Ndvmc5lBivGw+1+No20w45r/pmuCuX79OnYi6XGi/f24PkntZaqJuy8stUTFAfUbgI5nv0UP
w60ipXZmPpHbng0QHLlrAmlinna57ds351nqbbTPP4OrQ8AUJhSRDiM06ATXzMXbovBkUSi8vbhL
3VKtcGFjz70Cnxgmzm3iZifdtj9qqT6BkeVZQXMxchSTSOOE4a4rdRRAYnyBlBDyJrub9ZKdTc5E
ZkZtViCqIgfy6GyCqhWvbpXA0gOLD7WIP3ZNxHlLw7bYensndbwsigBfznxGh7fi7IrdHqB4QbJc
BUqfn56+i0qE78YRpo/3bRT75IYxiyXF91hFmtvYE35BxzHf3Hex2uFcudjf1ej2aajxusiq9lEE
MoObKZFUSUT8Qwgd6bOwxZX6cLIAhofdMc4F4BwUvZwCyAEolANR/MlGFwJgIDeB86FjqTLbUj9q
S8JJsLlqFPtUbooXGQR+tDguw0McSEJSdNxawLHk2pUawBDgTh0Z3F2lnObhUjAB8gkn7Ljt5HQg
TIJOcELjMqWdxxoEGH8B5dZyGR+8kOU5JNAX7VZmw3RoT4Reh3idhMjbjs7s7XXcjwJRa81Tt8Nm
sR69OkAlr898NNaobz0Dr06mr6IYscCT48adRO4SPWurtvrrA8nsA0Hu7QmD/cFgVrbNe8INhHLK
S2GWBPw4Of008fUh+0G/SUDejyIwGHIZ3BuXoSDxR5kA9XQ7tmRjL6gOaQ6gosZzMe209zg9zR4o
i5BTYn2fKoeu1k7d223AQjoVVjrmFxBWT75DKSPguGlTs4t9ZwOtSLnHd+Lao508yPuBE7keJu9/
QQgc0bEa5O5mrE1svEHo/qm9kuTqS7SPV4WwXdtuXz8GXdidkDVpd1Z2MDecfC0ZXCdlVhaq85Ni
/9f7hxFqO0hZgUYjkm1WVnp99mUnfZylchcXCWFAtknRqmWYJtOvAvh7ZKmZy4d5Fz/n8SMWKVHa
oaFILcMim6G2s0RDXzTLIqQ1E2xWUQXe+irPVPuoupcAmM3+elT5axozJtSdcjt/BkdOsuozhA1z
YyxDSFK5sydlaG3As+VmxeD0uj7bHbhSGcZR2fkEWidBzrH+uYCH2t0vUT0o9s7UGEZXuEcPv6zB
RmwzCNZZoXmmXpCjQ+7j73KRqY+iqFw602sTgdRfOe9UDxvDO2eWBEKwEbQyvUY/rTQ8pbdcpsMQ
pk8t1FUCcttE2qnIARmkvHgY89goALzL2VQX6GkkZ771jFRfk036pc2S2Tc9AzBZA0VP8gVBS9zD
vOffVMCwj73gAG6+DsY7Lo5gLjztyV81Osa/gywAuLedBIWOqHXtmxbxZbnHU4Gffwv4vVkmgexV
oMJlxs7VXhOsd3hYTXb3hi1+wmKcdUicdw9498M0MNNZGYkALC64w4sojlp1qscZcWHrHA7bLuwz
KDjO6zLFU7/slORrA+Ribisj1Qban9wFy9plTSBZoAOM6mlrSnauefbgmP/G9ksbIrJDJVX+UtD/
Xo7vdiGemEbWsPArunjqiXEGqYVL8J6LYuUY3kINuo0IBqngYX92MY1dImNuGJ48jkWgvOyhcxHv
BjrGEfe40LsqrcwII1vm1stxbGcCQXTTOpQvROMO/lYMGf18GJ7ukkiJFL1/zvONorFkwY/Nh+zs
XYwvKPf2TeKSlAMoCw5YHpTJYQLnZSqO887xmv5oWzOJuoDwQr4J6T6mzzInGBgcB7I1CFDYv+6U
5JsHEOJjRRccL4bNunjzWAZwKjG9lMkjTd6Zxvh1FrHZKPY7L3GtbMS/FDhVnzVj19YwMRI+Dyp8
2yp/OdIDeZZR8SMHu9M+J3x3zXiY+2wwUZbPyNbSgUfgUxHdMI7BD4W59o6IT0qq0YyJ3/F+77Jy
XVNeqLDK2/4HbS9sTPfqmHIUIloyDEtIL2cOF9q1hGOVw9qcIgQnAYvDI1Qcmr1R7pg1tSzVXw6m
hVghRKeOpI8Bnuv327u0kYZeU5BLp2+tFFIBuWi9k5MJJCqUV8hyWAWpWD4jEamLk2cYhRWIywOC
TzEm9bWZjVjMfYkBRjTJfXQwYTP3RFqCsVxlb+9Af47kLx6YQeSoiTuB3HC5l6FZI32RfhcmF18Z
S2Nsm2+dcmgAISGIm7bMBtATq5+55nuckzyVRrBcsigiGRbdnATOXJ0j710M8Lpb6owb8EPRp5ie
LCFTrVSloVX3B/5BtfZ5d9d1GGf5yBpxBlU0lk+HNyaG06VInHjsQlboim7kAcbvKEGAhkXHbZf6
fU5MOKNS1OUdNPEx2LjQBwo0NPc7uK+Ov9EPRdiJEXR1waqz2mSSufVbssP4gWUi/h/spyxpJwON
Z+4UDPKfhyWUMDaYAlo9u7VCdL2+RmRHN1U3sxbPaTJajzxZvTYVBoukBte3b88b7+8+9LPWkEjX
PjOYwe6uyiWya+iBcCHYDp3D5/1+UIJ5pjmOgLFVj037/OmjTnhorbv7ICqVTuO1TL6/LayNdaVe
370fgLHD4wI1TpkwR/3YsGQyAhARwDDy9S6UG7cKfWULFu5tiISvVXI1IINrt9yfgF1sjk8xEBcT
QnbwSrz6oabzhCnRpIdAlbDT9kFj9Mxp2HV9CQ8YYj/bJPfRHstSF+fv7xktvt1fe6tvlTA2yp9D
iK6+hCPNEqA9riN96vO2iJhwIDfAy4Kotfn1dQOl5wYCkUS2jKq683dNFzCKkyNqqf3s1ec4/jnR
OxyPeDJfxiAv0hybtkMmVFVQfxlQZghadfIj4SQpmPW9BXMA9mJLjkNVb8pQu6b4chWasaFp93QU
g3yLTACFkY6DeNCVICeBN/vnCU/yVFmXcjlWaXTNiuQ//7C+unvgdl1I6bC64Saxl07FX3BbUKHS
E9qcfIWjC8FYX17YfQC3KvaTk9e96bfad9/J6ehcE5wQeUglG/4MEHwPYcX6aKK/cYzMNNU9YkUK
4QtAj6i7D1Tx8KGCRjNkGuhkMwP0sAsFsJnaG6A2rgDo4xr7In7/g6tpfQOLAs4seM4H/YRtIsiH
qb428ZAez1mZAFWMobOsltfNpdR3i4aWEZrEP39It12wK0lDeEUnNrqXy5jHGyqlIBKTogA0vhU2
vUJ2a5E+N1g2KBGwwGiL6Ka4lQpBH362goR4tEUt//S1LQnPpMaQV7qruyo78jDiAJEvJLQWHy3H
Ny8jPhfv0epnGdsUEKdOUHUCfrLbkZk9EUMkUInuF3ygSrBVQjynOvwUwh64lP4tg0BOO5tT1iZj
qtaP7dC9Ixvj3TXMwI9/ZtlDyIIJhm+JvfJ9I7BFzFX3YFVWa4s6KpjMMNYmHlvU7g5U5xG8A1ZH
AmW0CTJOeMnQOkEBJdcImyasEX7ZHMd5UMPQbVFsoC7e++DOECVSDVtQ1WpwTSVixgnekDBy6Br5
984CtcYj45PDe9KvMhs8+2eTawf3fuB91cZN4nBC/FLxI/buYLpRD/QxQo1KzANPSm8slI4BLdyS
tMasoGc3qaqTJ2Qhf2gg1usRLIB5W4YPBNtSYtDfiFG8B8BCZ0Iyt3RUrKhb8Fnd3UfW8WiFbO5v
+MdXDWtRofIM4R9ZrJwoiKhFz7XVe82Lfe7T4ui+QauSfzm+tYiEgoLIWpLptcXm2znluqkLU3Fs
v5FYbDQ4VZpEyUHFY3Lvs0A1A4omKA/2yndnlq3zzxrcbsBK3rWIk53BjF/g27dhLVLvajVElJKH
oBDTO/ktMBcg10sgU3kUk54piTXyGKmy4Ojk0TisVjAEBhhldUy2QfSyKX2lgstyHIo7iMg3Gx2W
erBaPkwt5/0BZIOZDGjWp7YAZiXvvGqJ0ohLEjgk0hpo1CQ+yGCAuAKeIDaxFoAf9LzzQxCMq2y5
dCXFDXUnKza5A5eiZW/V4b/jpCvsh0JDYzvmHDetoQGjCa/O+ww6vlMLUP+JxEDzAUUAqunKlXAg
Uy4IoLBOoKAcf0/iS/GdPp5bbkFyrfTfWsJeADNcD4r1lufyrNR8TqcjxOTg540/+WPr2e4Ev+Xh
EWrT3wo6y+UFa56R2lIzyI8dlN0XxXt6U5LyG6u9KQ8KhZ2HDe/kuXdrZod+ZoVQFPALbPMQGr0L
90jP/4HJwm2Kme+xyNRV850QyRxDc70dQqrm7ftFdg5nrFZrf8VdTW0x/vjO7NeHQNyXX6M80dor
b8qy4wUXWNV2dEVTHb8Qx7w3Q/21d1xLhJ/KqKGTpOR6yGSw45+3xdaJ1WVTSnb8PkgpaJEJa29S
/ZKXcuM1h9+Q9T3D2yUW54R8oGjmEeCfHcx8W5/png/LOmb50msBpx023wn5bzxbxo7HEoc/A99J
Uk8j8vZ8KBN0akYn0KAvcEMJxSxbSvN0koxOX3K+q31lrzUbHvk0YrQCCCPTA8gAr1yI8y6ROSoy
2GbBlSljA/hK137OfDeDmfzYVvxPC5HqGFQsRS8V1GZGg7P6Q7i8PMD+ew/QrK93watzV33WAb5k
eu5tUeQRzlyB7JDpQZ+PZwN/ozQATyEMVjdhFc040l5JnMrVbMSCTRpvNARgpwLms92l+nicXeQV
T73AK6qAj9Q7bEfeRDiZdA8P+o5Gu/oZBQcperCJcdDqiwx83fj79LSpdG8NLGkzP9vjzkxpfHXd
dV1xhGnRnTCo+uGxzHOrrbcls9gXyyurpYZxoQv4LIQIePTA2CBeS4ri1y55DiktvX4nrHR3x5rP
apjtaeVVloKBRX6i+dUY+bTqI/KL1b3X274/c6ZzVlyCPqF/TLl1BSbeDBLp6eaqNhlYddOE3qv7
ys4eX3ot276pxr7jv+nyij/Nk1khFzU4rya0NiwEzkQLsX5sTjonBwd1XUfmR4VBIICBi8OATCTU
Unp1WwkPLzS2vxCff3d+q+SwFfHrmyo3DAlp1ZjgxpxK/2YKMGjmIL4nei4zwt+VDpmvPqGQG2RC
SFoji1o7TAivXultRKOjQb4C6HN3eNREfXkZzeIPNdD+I9D6zd7zKECW/q5IGvgay6wspdJcMzLc
4G3WQo4dYNv8jKfKaCF8kB8wu0IZ1OIeOG+E1w77VbbV/kiWVLddmOpo9Ci9DNuZySSeBtB2qJbf
eDYN1zYrNr24njLoLRoYqmsNXKEYoG/AIhgTYKBJ1z5x1f7EdIMfhKiK/zhZTdI3khGBd9gZWA9j
WOwFin3ZlNFDGBGiotuf2MTq8mdOo9t/VAvo1JgeHdt6QUDyqox06paVSpE0FEudLLMwZ451LJWM
64IKV80mJdImJu6ky5jR1pljB3N2L0p/JbJ43q4u4PYFlOUtpwXfKaanssr3CHYf9RwT9Y2x1W92
btB7Vu4Ipcl6+mpL7bmk997DD07nND1Kh28gH+2KodtH8Hr7EyTNv8q3QQtbF/bVmEY4/KwuohcE
tokg5RTy/ojvHY/r/Rz5xBhWvZosUgYZmFkx1s0SFUnufgFPx7SMDyqMjlcqqojWJpna+1aDK87Y
7C/5k0d28pwwyyMRERYxpJdPq4SRSh4TmcyCixUYxIvs8EWRIbOxr/uYQtjE3kQCsBtdwiZqPK++
jVqY4Bp1QglCQ+/CRIcXtf13+F/t/VX38CpA+UqM98og8JGWTgsgFLZWPln3bsN8PsF+JPP3uguR
vbO9LJa08TjFQQrULjHqfA/lIK4Ablkan6xf77cpL/cMbpNxsy3i5ejJ0zCMYYpt4iFfgY4tYKUC
hQnkjDrdUvGXebMoE9jS9BYN40Bx/pi/InzhwR9ckuTIlqHQgg7IryI7hR/9X+0QLYZAywgsAgp0
0OKvfn+o4qxXzqmsbSapeV4PnnkWnbSybn6Kz9WKMmk0kj9tyC1Ij/uoM2Z/9oQygf3/wDuqK3eu
aGrW+2ba4JtBZXKI1iM/fcFLAq3+LU64sysFPvJ/fB6VxVYS50OFcBqMBBOvmfNpUecamv219J72
F2gAbsRMwEgVJOLodx/4M7eyCcOqDE7IcnNPNTy62TiUHaORdMxwtrSK9SRtD1HzfL964UQIB0zY
fDrpw5/RC4fIhPNTymsuzXX758oDIZ6PuGE969cKQKHRCYV0DvKyB3EF+oNJACj5N2lIV2lkgELC
msyGmRHQf0shjHAi00EJgKvfCVKPQM+FLUnx3xn7JXmlHYLXbXNNjWuJ+qspHhG7Lv/8UiJjRe1i
rP2HhbrY4Ggt3PdkJHw6/p2rL6TKDK7BiIis625TPIkHvluZOEwuMOwAV9tzQn6H1joMNTlNR2Di
TAXqoQxccNBPr2iKLYnfO2Stn7JV7kBGXLwIIO4UxfMPclZ//UE8R/jfI/qEp6YG2UjhYgcHXzF2
XYmz5DsizYTJ5Nt6X+WG82bDPbcv5ruN4DS5nenqtBs7Oybl03iyuqnaL/YEYNPf2P2F4QCplU70
j4nBKzZDBahdqr6sHOdY3vqqtsYJBOhFQ3DUn8rYRf4oBgxWJOqAfI/aVnJNcmXW5jvOSSRTgC5n
UJKlfuet9cP8f4vgAmG3lxtBfP0ieVr4DNPJJ4JO+7pt3/Cd6dV4NncW864yUCvZMD83Nl3VwN/+
UOwsSU1uL9BWSIfydoQmg/K96XLO7yrf/rDGhLm0+vqWjb+dxwrvWbFOOYpbgGD/SAyouNcGXLMY
ZlBp0fUZ//ak2iq5SeT94WNofQSX8PLAaG9SIWt/YgWJd563olvXm89WI71WWXSjv98shMAlXejP
anlrMzr9tgePhu639htlWSasdTPiTbkYiclk/wz62rN7gS/dDHj+A3Cl1ayZgES/zwv6UNiImDOv
T6Qp+jQvoPI8t2UlkJ5u4y3d668pBJwa7wLPgoupGl05lQBigrR4RaZZsb2h6y8EEVr0zZI0jw8W
RIXyKav842KhSQCLz7ukIcQeD5DDhB+n+MoYvbsahhj7lGAw7pT4zldV2/AAGwcQyhF6DyFOkDI3
z+a+01EEjEXooBpqPspRPw6sgPRiP4DKIZobiyGo2sFiwoDIiOj2F3oiXJjjZp+zSYrdt/TauGVg
zBR97X1jmxQRm8QZO2tj686llVv+NDpMNt3fTq09p5MyBfkvOSlP1B84zNXhICBFw6hHV3dbsfcG
4otS8MCvxE0qED3zSDS8OIfjLcGFUYVCZlm/TUrVUaRlqBp54l5ODFdLd+8QUKzEu/lvJf2nsi3k
rMCRzJ1f4HkD3Z/OP/7ttvehdDiOc9yqSQ/sWdB7JdniE6H8Dkx7LztrBWPW8LLlCDfOdrz8qs5Z
cE5YZx41RiBnVB/e6VxrlofuBW/GvSMY4z9yGbFkSaNXkIxeNTW3AU6bc8rHSO6FUj7VUiaZFHBu
pe82wnvdIjjS2VRaxniYK7W6vCr/TLMaVj05V1uTY7ukORu6qNoCfCUZV0eln5iusy2Dtix80B6W
uiKGAKYYwb4zkSw8VC/KoG80cmdrzKWE804TD0LgAA6/DM3u5RCbJdpJK29APGdB6El2LEOBOpxP
BdUWKteVTHlYt7dkWGP0EQKOaK6IPQEddEbXDH9s/eauR9+cgwyKzhQOCNixgSu3Zprpmg1bN8VK
hFsBQkvej5aqjSqE2z4VuaVReAvVBnQjjQoja7bx292y84qtr01mvFKJa/p7XDpywTUdwzUoAIUk
6nUVmj7rp53O4MM5IfTul6uFTp8/3UFoJXJGKGo4kRwv29DgWCOBjjftxBIecbta2HwZnLTQDNz9
4Ir9SchoErHSNXuPmqbWDTM9JoOXaXvG3VzVxSOKQYXgirNsCs8bpz6Ix8Gsh9TfLLuc9ViTPYdO
9RhqjXa6Da0trD7SN6ZF/CfOnxWQWhNKHq3sdXQVjS4vOybryJ7j6SXQy8Qp6AyOzUhq9axrjQuh
t+k5PUOVnFx2DUdUvFC2tAyhmXXgc+zOS2schym5N0nhsi7VyO6MKQ7uEluOhpuwrq5AsRKwQjvf
oyEwITi1qgiP83r6lHdipTXdbhce/Fx0FumRl0amvzAZq+tYbnWzDXbgtAQ6Q6CB4D163xlW2tdl
Fo3ykk7nCmr6Xy5zuH57bL9PAkPpKHDyEbDGg97nI99q+GaBPOuQaYQONntktDKCV3UyA/dPCR7m
yYRLersugk896yMvbE7t0U7BX7b4NE4Jtje2iXKJGZP9SDOrFl0kormU2KjmmnEuaZyqIB3b1D8U
HTKgJXJOSNxyblYURVNfI/8tID3uGMP5yUQo8mXu2pCRn7bTN4s22TY2WQ1xpWkkRqcXbprHwbz1
LTk1LNDv9FO6yCyLe53AmaUSjL0jOQsYp7XzrG380Q3h2ih9BO/InGdSA0KGsO0OuQV5uD8zAH6L
oZrKVR6QgILn+CZDxpPo2nYoomAGxmiQ+rwKVB7LlC1ej4mmIOWVNf9YWwrQUHQSalZXKcW8wuR3
9blhPzOBQ4MF3WRqehaxtQ45lb5D/46Bm9ba2cQ9KexB4QFjvHkgB2yNc1MWcCVIDMu0pu3rrJJO
tDt/cJb9RHfOiec3suyezyKATOVpetgKzuWnr/LrskzdPupDw4c3/zGL5Hx7yKhE71MaLwahk+ws
JEHowSW3LUv0VQxEHQFbKVF/vwtluiu5OYheqO26OpXAvaxXSe8hUr2hnE6INU4XN7+hev3PtvIe
9PHRPWYrxr/9R2iSoB24Wm8hrGtJzS0L0t2BCP7FU78LjGKh3cCfpG03Xxh8dnFNyYQ1egDkkFYC
aWZqG9qdshYWL7H8l4oIhh5pHRFrSPFfSRdIiyl6nbJcgkW/hJ5BNkgkZSXP/r1JnkxhJNF9rDY4
Sd08KlLjani5xgc/u8zRwcdOTX+/9W/8uHNMTBlwManBd0xBC93UkiLGM1gsfX4MRWjMQ77q8ns4
zOvtZaSOqwac8M4Nm2Sl4jBm9MrherhnBl1v120oMnCw5JB00QOOcjBQwXwH7mpdDeB6Q4FieMDO
f0a9MG38/THzpOHXh+foJthois+gtSsnJxiG/NRcARnsnJ5BkH/euIzLvs0HG4DiW0woGqlBwcvu
NeZOHyn9ygyA7sBtZtMTTaYIkgCTm4yDlEfh/DTaPwu1PTIAsVqQT8WvRPf0GmlnqGpH/2kvn3AE
m1S8jVpyoplc2O+UVZ1FOtQ/pN12MjFQSn1b/3jqMOFG21yy4Afiw2RXIRFYbTss+m/VC2XmTNMe
qiyufDFzXIvC1KNOJ4VnIbh4ejpZuoFJl86uCFpCsd6xTPQtkHZssNvbDydCuyo53WkVTGhs0TOs
lQxS0fkesP4R7+S8nY8Ex0LtqUgw4Q4XdH8taMh9lkaAZfFbGEufZeKmrSHlPBNFQCpWCQvRgHNG
aUIhUDcI4mfGA45gENFN0rLnAarQOkh8r8QVk8BuCzHnIuk/DKtbvStXcJcOkXj3oN/J86fz32Lx
dAbgHxzx3fVLAbrE/rjn5vhHCxqtL7GNIwwUA+FehXhqq4YiBG3HZiNyy2MTxpfZkrlv3C5Zt6Lo
Rpql7k71FoM/FVZjTD6lf2A0ddNUxZfCOjfd3b5XwtyL5ZVUzVCfSw67UGQh8LegHqZUv6g0RT9L
vrt2xJFl9iXY72549KZ+u8rF1PkhSXUK0nxyvWzxY3UFNAc8LKVFHwEeZUZ/DpdKmM4ryHoAwQ/B
mswZ+xzLIANQlUHACBr1pJpRk8UhNZqhcUEG1hPrHv8VaLPWsYDQJgIq5nlMTqzviQ2loD6aTCAf
ojjCBRUuuCdlexLZRaeNXUZHwYWQYLovTdiN8+RrjwqD36uFMAXSJS69swC7sVQydQ2KhUB3q13d
g6jaId+LGmsZCuRISWtfdlnsstra8OfL3PGs/vGR8Cga3MGEFb7Ph+JlNqlWYGbI8AUfvaXOKBqr
bppkOCnbM/gVVYCEjWuCTB6KHjVbtXtSUD22G+b17+LT4DRd+YFnQK1YStopRhW9a/7qiymfYkA+
sWnhFmX/LSlLQN+O0GAFaDFgV1gXjQEvl4BYmw0Z9ivCa2x749ycj93mCU6BJCiggOrk/yI+LzH0
cFcStHFVqLQhCpHUSJCzN+mSwOa5szKrjN6j8EPh4NtcUGlfxCKQMDOXKyXKtwQJyOBDl//+9Niw
I98tu1sipbM7O25SwZ3sZUN+ogtTg40GIzpMXUEJ9WyUOzZ/ocBEq1akxI/r+SsEkiLgi1XEx985
Mirh1c5T98ZG9KsksM24qLb++oDSRO7ajSaxe4h0zKpz1GHuo+4zjIh7Lr1JKkjo5jRzYR7MpRLX
Gh0yz/Wnw8sc2DEfCIQxkQfRnVCKpyEB0KXB9ZqlBpHoqOOl7v4lf6Y/J7CSKq1+R/wc1Jnxz2ty
PJRihAcMGAkHvBckQGNrTsF8VWJ4JIB/f1Wn/6S+07OQMZVDZgaobqobqA27PwCJf/6ACWPfiKxV
pgeOkT3e71l/7+vvgxpv1DjoGmUApoKzGI1bZWYt9UIGmcu4Ip18AgVD5CgaM6aGOhyVO+BoAnmO
jNOvDERS3mJPzdUPsQdKE9U8mY1x0nfJnl5/UtxTMlyFHLj0+9DPvl04nGixSY+JDfU/bK4dwM2k
Q2Iz7nMd3ENq6cxc+WZ8nE5ofPXc579+9nsdIbOBtIJ8SFkqdJiXZYByMTqtThw3T++iCIHwun99
gQ/NjYGFEczsgbGR0lYLMBpRQvKFg1KzGe3KxORxAK4yoM/FHq0YJOwupGhr57dDGKHuj+QUxeN5
OxPuG/WgYPZp1iJrDKeu168FWxzp0C06ZrvgK0g7TI6uuI5a8KuhWeUeWqRtJ+rZOmL2iDOv8u92
FtfYk/WVk2wEFdHKqzY+d5sQ/TrBMpk2/bIGBwM1PLPXiaqgi8oTR7sATVH/Rf8wVLII4/abcZ5b
jI2fCOc7iCLpxi2H8VWGCbeFBzYFMHazu50V+ZtLufJl9XVVfpEqy1jCBaO4wFkv6OJdVMoV/e1z
L+FNa4ApHgB9LwF9hYCuKV+yB/z68s/7ZnXmPWj+e7asSqG9yIl23Hc3MBu2qMCVdlh7Z5faF1OA
ggC+LTjjmTPMM/TVVZn/MaW2QESbif7nQourPghBvqgunt0W8s1Z4RsV6hYuijigxTZmKs0W+u1d
pxND+DzRoQXX8uqCOiPreLEjTUKJkLJUyKgzy4CTq8ArnqaQZ2RN8WqzGnZq/m6BFE553t7TeTUH
ZcpsMzgFhsJQiq5aE/NW2+OIC2eYzVZvgb/dj81nbzv2Z+lExzgV43/qO9PiSbZh1Hn5Y/d0sauY
/5m1KC9gs386h7Q8+QObqpWYdociRP9w7Sj+UaP3oKh1Yr30uPJPDZRmxUPPB+JOtwGnkZv0+3DW
rZEvjZ/PGjV4IJDnzoQALtlGlPqP9dfB7jUN0tf9yqK38+dDtMmJbLgl3GgsN/2CLm9OuYQleknM
cMOYsoNBXQcSOP63R6mCmeh/sD3j1LDpQIPETnOeKmRFuAmIAyBaM5evq5Rea7Bo6wF+BUr+oIUJ
a4oEZZY8tCJavR+dE4S1JZqIkXD/QRBaTm9llGBPzRFuzGWghZIXXeIcSWiBQ+/Dwd68wQc/lW7x
niCVnqmp/rmO6sWbzWrAdKrnDJrcoZa4cNLWuJs+0pUrGArbE8ETKvVqPOBPwU2id6nhLMC8F9w4
3CyXFEgn3MgXclBt5IC9EEKoSvYqMxAlynp//vdDEO9tM9FXzW0tM2/bYJXqEErpxEl7d7Mlhb5X
nGGkeBnsFgP+Fbs05//YeThb1bOpzVLpSAFMneSMTMSutHXpdOtiY3HrPkXvvCNlS/0SdWleg8tE
5onBXb+tNN4CqkdRAMiaq4UUwmktF5NNn8YY1733o5NiwJ2wTpCBiBQyoEGVTqtSRMHH6t88HD23
ovM72dmKjkI148miwL43wb2Y9znsNN+p2MQcq3IaD8Ab386+Dr55rwpi8MKZUTjaAoBauUmj6SND
xGHYLc9n4d6MfITEW5Jlig+9YfiJ2TVmr0DZ/Cw105bBYY649jeIZvryC2NCn3HJmLIfDKiXMWFR
t0d3VvnN/pozafIr1LlFvSyV+Vfh1Se7SNmjfnKdz0l+NT7qpg0J919nbTIE7nWw/DQbr8czt0NI
hvJRIN9/Vh6KNpv7xZJVzZ37DdQdhr7z4SUNSuBJJR39epZvymvjWXinaJRs7U/CJzDaRLorhPvz
HKg53DO+K09OA8RwYKHbD6cOtqGXgPgfYEHY/ZsM9TzZOB5FAA0D3nuVUioemAzmDSKLzwiOOyNt
vMbZr8keBRbIG5LHCer9WdJwiE6cD4ILQZDLb7AFHKm/vt1qSWBhIP0hzUOn7JeYBFdgA8C6AYF7
b0TQ7YC1+dDqP7bINOsEkNCVc8lMOVDybKQ3la4Fr9uLp7TxPPBgubJy9ps9ef7zVVkPFUTz+hYG
Ltksxau+FBeko33ATAYv87sF//KArMp8kwVoljumz9VPUO1XTCnbDksBQiTVRqKpcQFlo9BmQAOd
80jDTG5QgTmuJBH2voVLmvAyB0WsZqhOZmlBicDJuEDMzMhZR84yvrrkk7XcP3OxK3pvTyNzjy/N
K/bcNXCgF1HYBllVqjuC//e0RueI4ye/79X7/NrY3FodocDTh8LOdsr2Jx6kvjkTKxr+l9OozaPN
1pkEZfMmzbHS2b/pz8l5UTrDpxiBXa397I46XAIS2lHAlw06liCIoWPL5R7LWU9xSsEc6zOa8LCK
tbpcXjato5X4z7VOeDzdUJRsRHd+ZNlH+tXGzuYjx/vNH1mVOO+uxkqYoW58eP6XwuE/ufHUFNPA
lZBJbLijdVU7AOZ28iKvI90eVjsa0UtaPE2V8qYOsd+K2R6wN60WhdEBo44HGuNQ68+MUwh8wRTN
Bw30xPoC2kltbx/O/Q6vGUGSRT3pdaA6+3LOGqdp1qk5egxsJjfOiRG/pBo6RjhdPrFWKK1Kmf3W
4IQSrnPwNAQ4kMldzh7s/0Q7oFUG4hRChXxakah12KX6mR5wshKRrkHY+wyMBdfWsZGlvqkuQjjc
sPOZAlpYYlrwppD3V/dn93V954CyM4+uwG1Pjqp98CFR5LChBFu/ocSTJ+XUzyjhfzswtCO/6c4t
dZi2k5N6CkU9F77KCg9LZkSFhdbsy4TOVYx6Ozl68nZloF7qIke7VUth1Rg77vepKhZlZIpY4Cga
z/T3htam4g3F8tlqxz5a1SEdu00N9bJ1siV1errfBEsnkQf5OVKV4YS8f9wt6uZNZB9BL0kT/wim
fiuqkN7AQUU2g9wDYwwLHyBF0rWOnS+5GA8t1Qa/6pc7wTMJ/STsgeG2rxPIoGMcl/IDKnAaSPbK
Aky3IuqbcGvsb18K7+mD/x6FqM0swpPCzODQ9zcq964xWwcO1pNHK+VxSYqphSdEh8C/fi2QZ9/M
cHZHXumrReeLwImglVAJPRXnDiXyb9HBe0/2VKgjCFHT8aqg+c3aK0dl1srwCCCgQMCpichOGxU+
kDQSMxOtpxJrJO3HAJuQg9karAliA9rkmXlSClEi0YX4DUt2wWWuq7Zf9gSqDcLGpi+PN/qzvUkm
zEBnqX2gv8lc8Xz1mA5OuMqgBxtBGtUjkCP4ITNjRJl3H8jDq6gfPVbtCHQivShE47M+EeJ6UBsG
cnQ+he1/p5l9652hisl71W0O/U12lSmGXqptVxKB2XUQigy0eWW7x+NQpQW/b/FRh3uFuH6MxhCE
pibeEcGxjMutam2VAaA450fD/pjrZA0Plcj1xAgKGtXGt89SKw0NFc7/nQuDyS5IfdB/saZalbTh
E00UI6tMPuJ+jEfCqsn+JYdVb1xlz6fxxPmWlRB1lYMR2T90jX/OGXRNWqxsi57O59z5iFvqu+n4
WIr3k8ls/TwvE8/VcLJrfw0Z5MEt1hWbaUII+eyQPDsVTcs+FARMQQJ4sJ6nZJVzJoB0x3RoNfGB
5/ZuH8qFCVE7WmLoLSPO0Ai7j+WEhtNFfDheJplCNZKIfTJBS9yzyRD3KfEg0C+JPaCCQuP/0vzc
3Yv8v4lKu9U6NkHow+i/7m9C6p+AhkVSayMSNzPMNxx3G01JHqSmip8oDk83sTGfya6385QsPRuJ
an9/Lwwh5Q1E2PH31gu/2bAXzEIpckt0By7MsmWAnWM4sP4++HoofTV4Wx+6TuzZYTBp8JaPZns6
DStabm7wbwmH3KboJh/bBDJuPm1KOSQmnAXvdMr4W2NUI+2ls0qB8lfp/lTHBVnIX+LMgpKY95T5
qmb35XQNFot4P45TxwnrQW8n/KnNOpSBcucLXfZ4FRJCvR19tpArqP1IwRzbJON/nHdFAhjirG6J
i0yDCJ7LStA6lHbTXkgAeKpYnc7YlglG/S9qQL2ayYjwCVRerfYOhpmAt7dPk2lWRyKYuO9Iypvf
DS0chWE50uR2hfVGgEJkKoezPjtOgoyudUD+uEEcw1CDtVPb7Aswn34jUCjoNhQvWumcSLXRaJTo
KVrLfSlwa4ZNIwEYSsEjjAzd/RrWtdOXTcEIRgFKAnzbHXCaq35D3KEt7tJHH9+XnTl0XgDy/qT6
cln4Ktw+vYEttzZjDpv14N3WGzcpsEMi6g+G2/Bc+QxaQg212aZypstc3Wy2WkHqa4O/j6USzYcU
51/arw6XzYiYP56vadkWeaZDpAOqu0z25Dxizkk2MB1HMHjihLOzihJh6fGxjzuPxo3rdsywm0G6
TnL+6WMjuGGFD7jEKkqoLpxeCZqSHfxzl+0cI/l4LEHASbOBdpkuqmbGM/J/7HF9wLpekSYPzeIR
1Z21UDV3poh+vLHukbO9Gcd/yQe8F0SttDteK2f/sDZyYNbZCli9rEy6eHZAnuPgnFoFvJ8bTG8N
pqGAMGWh14enBDuA1nDBGguWW+JM/p+2blzOuopabWNZ3nGQtx5kjTlWDjzJLPzNGv1nrqwYjinN
7qu5kpote01y2RJU6BrQ/5JqCvrsiaVxPYApeuwPLUEtNr90OgqA5cao42SLiE28YbxWLekkJbis
t9Jhk8yZLA6CJUrxz3Muwae9frHbtIKa/FXBPsU7ZN/DlilOvDE/9ZjKy/x1sZ7p9eiAeBfrdC2H
TvboGErC1jOE9k756pS6sDlprmMsB9VNRmk8DKGNlnr+mggmdDddFdYfkbC6lkDej+/+O0uoJnXx
+vvpJWFL+fe6Ae+m2eyAE2vs6eeRdKfArbd6mII82/TrxSBGHG6ldU+0W6X/mxqO6m449SFTuEx7
DFgtHVHBrbkPCqjPS0WNLm6zjL3PRD4Ko4jxzQBUDtkIZ5rpgKzNDwtulRy9GHrBvwYyorhIGNds
mw9eBcQUERwIEojV5JmTqs0r6MZ8kTINdZkiLOthQoxfLRN035TJdG71V1+LvSweGdwN3uJCAlma
5TfQpV9BJchIFTYG/hFdZyqrI2qbkKw3tXn6sBWhgV6tp/gk77mBxZ0TuLa9SBm/rwsIWMQOFNRQ
mYZIZrVvOaODfa7RWp4C5Fz/czqq7VaEOyt2YUREqF4AL27LfelL9k5odKqBVRQaFaYQH6AmGP0n
hMG4T5L3E7iZqqQKx4W18C6WLTivL7ugUYTz1lrqEsrw0z1uOTMhVxMlvcKjFkQIMSFfhOlRJA8l
Nmnh27Gykher4UezX/O4Z2hOmQN53/Au3zB/Wyn2n3Fh329kp/HY21K+iLsNx5rESFPQgiUi62n8
q9uZdLF/PXcgS+T/y4NZaDuu6V7CuIWfWYHZOy5FFdi7i9ftR4hh4njFRhE8iOEnoWzLLYsRsBEW
P/aZZ1iE6cDXJ89DGF6UulRM8xNGRqPxlH9HgjLqAt/eLDc9oxJnWhByj4sfYiYMrAXAudmk6GLd
LdIajdNjzMkaNlwEgCL+R4EKrrruwH9BhPpsG0FUd+On6vjGaYvKEfN927T+SB1HO/HCV6kzqRFn
H80xXdOoTCeOzUvHALe6MoM9woLjIrYZIi0BP0JMPHdo9UITfwMfFBiKVHHxEtF2FpnW9J9UWTaN
ddzvvWT25BRmpAHaC0SnKLmF8P5cG4hIhrYzxugm6QaUB1kWzUbPvDK516NN2AbGwhlzOpOSnLif
QFwHoIJ07FNHu+dVSB8xmSoXZ1iyXjhKP3Z2klUEj9mxUzWQ1ry1PfywxupPz7HmYpPS5nxAWFv9
QNG7ZC/3yykxEIJuT0JKWAsIPhGSSNx4k2tIyMUHUpVKiGskreMmHju0CGBXuPSOeGfBfb54hkWA
8ul5eCEgc9sSK7mtz2MNuHV71UXdfd+vHG5VrMn4onPk5blqmeS65zJ0BVsg62LeaSxvfGSkdyjY
z3D0qJlVqinu99DcXbmV2AMun2pzhJdByssdCGDAYoHpThqsLBj1+XAA7Q22m5NCZA9xA2DFV3hn
z7eXsuiR02p93EtEFUN9D/axl7jBx3X8UOJNJaedUI68EicTNtpYRTLGsBBfTyjvsNaoHmLIXBxT
IXY70Nv13a2NRplM+CNzGKuQSKhVE3eHTX26WFhDOSTHj17IVFjdFsSF9aBDKbKh1JM5U0iSABbX
jEe65OQVfVzYTmexoP2OEEApxhCAjKw4A/oMvUnppNn+6RGznlum5OLZdqm6oEcLNqPGYbvvl6c/
r3XKLNlvaDHjLNY93IEkugL8Y5IWOAOm7YkJvauPuX+tyylpBhXGU0CXvNln7WRlFRXOmuo48tLq
yWvjSVBHMkfM80uttSbkAKRHLBcC8v37QzxscJPx0hT9KZNScu7yYrb9V45K16cfEy9LZYv8oNnD
hP4uNiPpMja6cGnKgfj+mSYnwmS1ul56MjpQHuwtfhXeLGDkz146EOdRqdCPst8nPxLlY09n6NWl
8gG5yoJRSnz5f1qWf/VfwyfvXMDm5/lbi9/U7imh3fPAEkiJb/pzXrUx2CRaH8HdAfrU3FjxYPPN
GPoovfi2vHRmo0Lts+9rVOjiyMjJ8CUqM4IAVfTEIqLjZt0pc6j423fTKu2JEsnf8HbePrLq0Ytr
sWn9PSRUAX6lr9VyroFxQ42FjHPb2bap9sh05y6B85am9TdSTt5MQPqbm8UE+8HcKXtQWJt2ovrs
o21v6vxACoEeDme0hP4pPC4sNNcH5wRntLDfuTUCiCXbotnh2tGn6CugSBvp6i+Ch+E5ELJjFutf
HHfnY7szY9aRDD1UGQaW2rJbSB0eiDl2X7cxX/Y3pt+Bk8K+pgw1qqUCEDRelbviTs6uzkF9buSi
PldhejjY/Z0gQXSuNCeqpWCxd9Rq0EmrLgTh8slDBjen4bGr4r/uj8pfZnkUy3DZxgKySgCUENRA
vKsHltGYFYqxMyX9LDj+oxHqv9/fNipWaUWiWIWX9zAYhSAMmfiXfOUDqxB8VOLQfx2jK/ehQIJy
//vUgRyLE5oLr7/na2Z3EE+NDsQErPpJo1TVeBlJKbLynsUdlWLrXUy78mq7392ACbxj/4O2evNS
M6FnAZVFMdExv3jqJ+eii/sY/ksbKpmfIxE7FOfI52UF8ycAiWfA8ETYe7ovXcJrARzCLDHY3/iF
ir5QPWRbH5uhSGElgyDE+QpboXerXecuLCCo5LJI+nWzqIyIaWhDrm6YF0ro3VDYq99HUg/KBZZZ
iTpZHQEhs2bEzIaqhQ73BfpK3CnVROsFVeYuqeLU+JRVPff2QC6/OVqwor1GzOpCoawXMqRcVxaB
EOf3uMdcjgcb8T9Pu8XeMKKVMBiTVh7k28oucPa+6Dm5Ue0E53iBvsk4hAuIE2Mdx2l99dTUPlck
DSDrBAlhh6O5Ef69oc4StLKkJfCdQ8m7BLkNEsXdDoyOuG0KYZA4VaOHB85Uy0+BI5bSRhT+z5fO
ubtoLg4xkZn+ZXI0GHAKDCoPtncRjuG2gECE8tYGf1DRZUPh0rjmyJFr41GAmRZbHxRAYCg9iGmp
4dw23REi9nawno4bNU4EZiXXJunGi/ybm9ys5KjFp1IEWQH4Ob5mZxRErFh3s4g8qO6dm1DCTFQ2
j1mtHrn+eiEeacGturSM1vnqUkBLuezjkrVqMw3yvo4XKbcWQloLcMK6HF+6oZac6dlN8Zfi8FD/
iu25DTyQptmVoG4k4852RnEVhKBhn229ZxZirEGP17wL50Gq9hCCsNi7eXBASvZ8KzZHTMPL+4Rr
2vR01iK0pLctiGOHeWgsKrIe4jzJ6be8XDJvWFTpu5mld0ND4u6xXMlDZR0YVp4hxKaSZ6Sv/4YG
BLhaGmBLd4Gc4YpjJTwRT6CifiIoY49uwZlmXmdeRZA5YjSeMMdKyLy9GlJ0UCmdb50IuGrKg0Ku
VXcTUVWfO4aKu1dAOmvojjZmC2NKxf6rRkXC8v+YyoMHC66K3V2WlksgOTlzPVQsPnbrZr5maTQu
7HR3O9ZKNdJSfsRoujNl8fGKBUzC+O2oKf/srqX/w75Og9oAVaEq6B7eYjEHQTvMVMRJqcxddxKe
JX4SVOUU6bIqM3YMAaM6uOXavQJjP7u9Lj3lTL8deCngL8e9FxaNtov4lq9k6XyIGc+WLWsxWepD
pfGfLssBOhGhiw5oqMDaf0rHNmIBsNblGbtk29O8Qe35pmxyRSiCTivVryO5aJNtj/IzVOIatnv1
+Rlvk4Rcq7sd+kqT7HDJVWDLofys3r96f9+r4aR+7Y/oKdutXcrMiCdh2U3AZfjSJtEdglNEbwuL
0ZHGLDEFCgrxU9miEU8rlHTGEDl0F2bYpcb5rHQbT0XbOIeAdZsfgsoOaRNcZK4RnTwR7S9sdUb4
sfafsfBz+XYHtGCxFYpjDiqRgE6EBLzOuy2qbwUW8/BWAkMgm3D62M0iE+OjHTmtFjWfxVl/LZyp
1/4qqsFmr+1cfQ8G5bJJGJzUlyzqVmJLiF/DUzUJh8TOGcsKwlauG6o1PAWijwOFSjfggd5A3bh9
gsl2pHrczfAPG/MZlxqQt9luO+OwAnG0MDvNGEBqhrSc/YWPIPSgB8ra9+cdxSeMYPQE/Fv8Tv/i
7G9CnQQV9CA+A/wbJ2ivwPbkctUN/Yyt3TgFiVmmGD/x3JknYAD3hCobpMHKKRKSEQGw18fNPEjC
a1BEPkYOjdgg3rONZJXn+KhIylIXgDa7Uyru3DTajna7gH9vj9EoDRegczmF7Jy6m6stx44wTywJ
z7LC3Tx10cRxQDdW/yWA2v68QHPlcZfXfFKVi9WBXIT0omP5hgLmQc0I3YqfWtGpmjXOAJme64+o
5eqdIvFH9ys1mmGke6PhdD0ivFZYNJxcVDGDU8vDXhPoZmXYBfg5lMKQ3/2r4aZ4b8FTfrn+sKG1
LMK4QvyovC9ePNOHtqH6tqxCjNYgfex9l8bQGbJ9jS6cgd6LWoGTzxcBorDhClJ8LrO/dgQjWPbC
MoS6CxdypDu9r3DwxrZalRZvI4CAEgKRX5KMDCP26953qkvqZRskMqgQGskCEuoFU9F9+Qw82mI1
PS5P10cw7k0amn0gR2Zo6XarLCXq7Zia2Bowo+8pZ9CilJRbQtu0u/1+whzL943OAcRftBXik8h4
3P9llNHldPb3YZTVS0ERM8QibZ4eSqj09jkM2YxkcotpgN6Nj6i8zn2je+jLhE4gJDttmJiGTFsj
hXz+B6TGuHxREKWJL3RO+Lkwwb2ibCcaKexpJFhcA1u8Id/pm73kMiR3A5BMf2ogSbUVHnl80QuQ
9K0nOPsVj0ZRKhNeWhc48kYT+PegSnmxoi+AxSXCW1yG2pg1xHy2TfalLDtG3N2/8pAcnENyF2qL
sBIq6Vg7BKTZlTuLVY0W98tc2mWcfkAlknE2ZMR94BwMm89NyLxF0ogjEnaMTDr9wD0IKc4bDrmB
qStKkdvm/y8Ok6L01s9LRayeP2djuung2i+Rma+2BDH7LB+QAAdGI9myu/W99A9mqwjPtRzVlBVA
cQQO51tLjJLMy683DAdY8XKVZBeLtwow3hTQUW/DTxK1tEkxFxVIT5KmI88GP+OdNGNXkzACmCnc
nbHHSmwQZAi4FFwfaXABw+Rvq+wP0wBPThe3eZGBnmptomRvSzZB6yMkDUE48ndEwPCBY2H2vvYS
d3KfEt4EKlUW8eTyS/tP0JcOYASKPHczcr0EejeybcGmPBrNo9PmwedbKfOsg/U0YBNOAVeVGAaC
g79MBT6YaF1q05DBskXB/CoHr3ep//0TpzXpdHl4s1LQWsFpRBHJsev9YgBSk3uw2RhM+UYupDBq
rppzGydZbyWE8Y4ybzeNPO2SQUL1XeQkUX1lpQSeoiBBXny5D9WpO761mYJ6QdBk905FmKGXnbrF
CVBMtw8WZGvlPLAXQl695+xO82tYpvevcQwQJFPWlz0CsoGKxCve06KZ0iQFAcLDV1+VZsM+LcDj
AI8vNUWS+csRA7dSrXBh9SgJiD24Kr6Fnk3/6/vXR7U3tLap3sdv7SA74Vt8IyoFh3EftF3x7gfJ
A00Db5Ai3iyf/X4MQ5lpcPAo8OWcJY9PcUiFfRH/jL/r3VjilAXtWzHicDRc6CEoqWvJEWmq2R12
vtS5SrpCm8gLRyNQkWhzdKTN98lNRNDoD9G+qd41i3bVniOtO2uGj8glHp08VppxFPfF9kWX8jd5
oKvw6X0P9AA87pFB4LvqUdm4oTTDLFXsZOxBlvga209DkvWJufxqP8gvu7KNrGoB2CH1GA4Y84j8
qGbRDeVcOW0wInV4WCQ8WF68JzpSmTOXk73jp8fIgq8CShxlqtdpopotPvEgkBQg70SDDw9/ptQA
fIVsmI8kXKLw214+k2P6sF4OzrAtl1cmG/qEW4UoJDWhLWadekZRf/uMYqpfKrkZIOmbf1L4jBCo
e5kugOscodQG08gKWREu24YBTctDr3Um/QArVgzrPiY0C/Tcfnmt5rnDqlzeedlbZ8jlx+OUeGWq
5liGcmSX69F9VP1N7N8Lqdcy15ZHmKnVR/Y2mvse56Z8b9x6u0VJvm8pyoeve6pTZJ7JLkPsExBt
eTJFyPBqbWFPua43Y1sLZ7qDesW0z/RUZo3cP2iHoVC8L94ogdLCOGSQWpEwf4u5Z1pbUweo/Lrt
joaMM2iXBSVMEn1sNHluNWJQu3HeaZ/NiNFcVGyXpSSUZ4iZ0vxjUNL8JqZOSwqhs9UNMSOoPvaG
EyGCdTfCvhZLoze1zFUMOoVsGyfrsMiOy8lbWZcHjiPp96/60Gi79gaTTzqV4uXMlO7EWjjC2Hkw
DgMyV3YOEtwfs/KxLm0+q9dEZKpmnko5iwOLMkqMLkPSfr/IUOc53Q06Rk0kvO0T8WDuBQ0k39FC
vhO0RuzjTJND5paLWOTPS9Cumv6BMdWljJpLQnwHMTaVSjQeZQEnraz6Wjs5f1gyuA5KGaDlCBzC
zqjyv5c959rVcetUKxTZgeMyk3DI0tTFc28eJBhHj1pnd79Iw4YFoLCgpdMvxDmpHT2+c+MdhDyS
K9bS1EKH9F+JXh4qJV3kELKNTTh1MdFABbyisn0FsklGkYhko0lE3S5zC+qoLFJPQK1K3JnS1s2P
fmBDckriEkKsgrW+oywRqAeSXvcKtLf7wLyIEZphD27JCyIo8mMJOEzTKOUu+zdMttSv8veNAMZj
ZBOIz7NalEd/gBBZxZUVVubapkpOFgbI3WfvPO9aPosGciTUow4F67rtT9I5kE7SyWB6FgVT3wVh
gdSQK1cVFWCVYxAiB5hQ7bphDGsFdrIE4NBJcbFHyhSDr4f/+8pNgdZRqemHUHPWC+2/HEfN82E8
5gu3w5nVF888peuykEH/81stpL5/nasx/AbWj8bokQtSH12cO+ZFWyV2Grtwa/wL4tEMWSP1Y1pu
XaNN7Me/YKsnAHnEJaiTRnlV2O/YqwWY2i6f3ydXrfcbnM/Tk6e5ExZLma0WZN0jtS74E3XZLYBI
qYkAsoHvKrNs9jDkNqWn0YXolFaWQeCMsMbN3r6sLBAl+SEODk+tdxcw87E9E6HxHeWiZpdZWYj7
7qGAKLnJf94vHx6HJXsxhNa2nA9Z8VkV9EIiPJDx1kxtg7mE6H3Jjj1BC9GhZZg/aZIHISk5M5qS
2xoDpZpHEi1j0N7eOxTuouitJnE7HvbDlCFQPXHjv48iI590g+i66IitbdpcjiYh1VPbC6s0PQSD
j6pH5gOAotJUHJ1Q/bZbt4in8wzjuAcBitOPjHCLxriLh8RNDUSf5qKDLm+1ITuN/VZwiqoJmONg
jdMQszFSOaGlEjjyY+5hjKTkLhjHgpLmKYqfhDnitKiKqyDkQuHPbOxudEnFdL/AVjJC64Jmf1PA
2LPSIZJUEUZ8iapXKLlzAWo+NmPLSmL/hu6T4+5ZYy6fpEapTdpoHswuE49CNnEahobWNaz/g3YA
HVI7AbxPohgzW254smvnQEkSyTwJk4wokkYUA5lpInnjALipipamgIC155thLfRZG1ufYcwvn+OW
JloM0w/l4Qbtd1QACUy3dTqcDwQAAII0qDH/0fWXYpVuBSmdL7J/1R5ZEMAtjwCa2+oEjKHVPE16
7drDPMa0cy7wEPjiI3emjBMF/OFmFwOMxGefCWxKLZRvaRJpmeMKWXOuqJj7zDey4kkQOWuneCzy
6ind0FY1mUahQx7IEfz3tts4jxCdabkWQALmXpTeqSp9yYerRsGyy1TuGkQjDmp7mIpf6YDpunud
TYYXvQ6SFtdbBL26RMK/kA1a0biLiDXVcu10tDm9b3S3JQRxLCOmD28y/IbmeBv12syntTlzszdy
6Y1WyYfcNEMg45WD5XdEXFDtZaBEkiIZaT7vDqLtYtrThFIrSqoComgD97ofZVoxwXgBgZZQc/H0
J0dC0g7/lIzzjjfwNVNBYAVgaEU33EvQSrvmc55H5JKO9KLIH5w75j+T+uPT7Ly/k9TcAGbBsoF8
hbQ91gNJS4XmsQuhDZKItI1PK3Tvu6iz6VpPAKbCvgaB66el4bGIZM/F7QuGocLxTRxz3eOxCZxB
PP15JNKwRIPErgHB7ox9lNpLVEsnVjw/6ZmfoJMrR8jVGquTuVAeTAtLWbc6246t9AMea4qE/wTz
AZY/b0A10wJl0skwerDpwHjpeUkS9GRMHKhdEbM03BSx5UFSgr45PMy5wfABGkD8bfUcfoCmtrFq
iaIRa8q17lkFtTXWWwRC0Y9ASsxZ+b0fe7PX49TLeyEd8oyDsLky4KIaB7yiWXSCzNUo5Wj3/znS
lI/ZO/bKa+29R+S7iX8A4iKMfblEhuYMv/Tv07ZXTSmYelm5FV9LJ27pf4Rjt6xr76LN5BK/Z/i6
E5zaH5qkgbA2pEtqcyrLbfwYyNqHotrB/sELB4Z765q/jcqVVJCeAa5BT98JJiSaRUjokLgRul9f
P2Q7To/hooG4VeDWKS20Gx31LHbV/gGZcbmWdu58S74MKzCZUj2MGZ7aaWkYVI837GTCiju3y9R7
H4mMiaxiaJacf9/uR9Smqr5qvysXldSBAICErUqww8yyv46FdeD9Byi/0gk5A4Wmy7Nn9s3QYO0V
08q9CifSgK/9St+4TfqlcPU9Nw/kVevlhsj9S9hWUtnkwYEypsQU7sVhb4GBpSrG6Ys7qDFaIGK5
Yk44nKULw17tdUKpgzJMLkxAiCDfoxn7JNzof6ze7tp+/30L5Q02Y0+EvTmqjgWhYVLQ8q0CcLTz
2baKqf/tnuO3SaDVHvzagHZ2zqUe63NWvl5CtF+yhP623lYQkqs55FMaABduagUszt0zH0y3TmKt
fCLgFdt7cqzRsH7Nt9VKw7UCM2PsYAShqgAbkGrasWUxc0241NKN5vBSjeFHQtmz8vX4vsdH+bLl
WbjRhmqdJnnJEkvwH78zCRPRhs+T/s/ESssieoZ7vopivnL4PzIZfdVMaJCjjSWxCNbacr6Up8yc
iEPSdmGR64HDgvEwTfjkO3MOPTkmxkvabdjzZFMZzaEI5jzU6Arh4dAw4BSsaYfcZvzutaI/o1T5
44yOr2lLYKhUZ+skxLAmg4Lcn+yBfUdb3kg0AGdIeUTuKPKYJTgTr1W9sXLwReYo4nwoiGaLIkHO
9627yZavhXx7aijts2mDzsqu0s0N/KRExd4j4kfFly/2ZJ5qLuwiy5DJr4X+XCK5VdOZG/5urlQ2
8LRrPTOP/OOKMuC4TuNCtK+/j4mf5EA59WUtXW1F6mUQlHtNHu9eE2DKbW4n3YPYd2+Ah9g+0hRA
Fy7ZhB8PXgw8Zu9OZBycFLsK5ey0HjQUDOcRjWRKDks8nf1QPfQLjXeiLVJJlqOkCMgAVCnSU+T2
IT6R5icDAiqJ7ZwERhXugJtB7g22pptbylTSWKv88qnW32X0pBTVtUipax5Ye4hrcPtZfkgI+/9j
OiAXlSk1/60IRVDNX2ol1q9X5cJHvxWTupAYLJD3GsKrODcH+m15IYYdhPKArPxONsj0V2pWgZ00
/U6A1X6tIqK16bjeGroqBdazT24XJPQyxGc6FRjtekDdLrWSr/Nmoh9kBeR1U1hbmza1/AgCOZbc
94oFrvFb/eW+7MK9PwGJnrjPWUbcOiRP4LxeW3msZXoi/dCO+SZcKN11mdCUdHoYNsPu78kNjg/I
5du3HNF9DzCQLNzTFCGhnWgIo40s/V76CnNm1hQf8lz4osjlyuaV0M/5iS8hPqZdpNoqEutgB8y6
mUb9W0iwPbMIEu0pm0yvRENW0hWnJPDMh6C5x+D1CWD0swxInuoRyKgGQGbSiXNQbN6l5d1ftP+C
SfUk/7xmetrKbbOz1kmsKZmrTXvgUGzH/s/Em5s0sIX7mPRhAhZjA98hvEcE9jg6s4MMMAw8z3xe
hTwXhlnZkv5g5fXs5LI2cCyOidpq4fxq4EzidJDQh3RcTQMyJA/f94zN3mV5oD0+BBzh1IOsvXxu
H6f3Xq9wZ6VUWFf+OG83Yq5/hfH9JwcXy+xcOtKnC9GUSQhkD2IU9JzRTpr1VxeDWXgIVR0bKeYt
pn+5sujm8IoTWEEy7s9p8vr1urPGykF9praUcCPYgXFWpqXTv4X7EuTmxv8krO1QFKUHnq6gOzPU
X1mrsluQ8Ve+NMi0QVXuW4g71svFg08XOCgKYmG+wtsiMKu5Z0bDZicwl9QuVe0NB7NRqXEDU00E
8YRuq96ty9dJlGpVtTXuf9856JDuCqL5bUGu6/n8LTQxCFvgyI+r/UtYI36ucV21b9eJdEf2mgN0
5ya1YcDB13ERYkerzYAA66dsClhZGEUW6htsR/XlS48xbwGwj7OeYieNaUnBXnkLzuvIv3GbO/8Q
saQ9UsY8CZqGoszNsuaaLywYtgSZ2L7bi1Dr7PEgTAehM+cqhOBMuVjMnkbXYdIIFIGg+BgtZKgo
GGzjb829Jbdbh8kHeFnLcWSkiVoFrRmEqiazdC14BVkTkNbEfIsGfug7aZKWS0lQ7X01o548TauJ
+z2ORKR5LnKTopdcbDtRjkmodzqUski458rK7ukjPjZNIgjXg5VhGsxO4GgjFdOnpCKypPH0UUpm
Q46WjH26UMLFXJKiYEIrk/cs95PcZH7m3Lrb3Bxa2RMiTILXTnPKXIVFji5s/+7TU2/svyIcNZ3Y
F0GESCYp1G8gNSGwicHKhzf1tNsQ1oiMdHp1eQEHJ6MBbwviWheeykq1tQTttCBnG4xmTIgwSa9j
2Y69erS6RxtNQqENwF2wRyHdtFiiDS0CuLa64LZfcE2wp0VUZEj7RsDMOUK8lgXr6NfLtBG2oqn8
8VqWP6Q/m8Z545QFhjTuqdje9Fz0zRavvhMKKGLSHqgIcDU1KBaf71oF13Smu8MyTFYlz5yud/3Q
mC/u5gWJADIf430RY8fC86CP0Dvt9NE+nlmfa/f6ekhW3NzZ7VhLP1dtSXXvuCAppiFL+JdXPuWu
3DhcweKoL+jYfA/YgNNAaQG/8mF3GRyyYMOHONylHK5nnmL9DlcxHqQB9B+5dCK8oZqJJRYqlRKu
DFLly0dfYojCBxOZtAKizx12GwaPiXFM3bhvYRO2jr1TkVxInmI4Ki3mcNK3IY1uzLYxTOl3IkH9
KR9+NPW5XNL8M88DZkujrY8X8GWPUlEvAFOAiy6CK/qg0ioFCOqnv+SVzRcvNIDUeGgTyM4ncxTg
T7Mko9hL8ACZgNkfMCSb7KosNZtq6/WaDUwP4aMAMcFIOmQt2v+j6ZjySUEmEnp8zux8kXVvz9n2
0kUS46y9ujdWBJxox6EWEuGWugqQXqwsFRRyLl/q8UGh8SjvOJ0VXc3veQpNmA3wEfLqL9OdCc+o
H5PRR81wMkqMITT8QnWuwuhCdehTBDDhlsF1X7HzLycKd6CJtHY3oaDxNcZ0U2zfkm6ut1oJboaL
7t87Q+S3RLwmIvSHbRr01x8rzL8e4W9c9qxdhyNrCJKXlvYGnXK1QF+t8aQ1NPM8FPNlpJg+QXEd
HppwtLrI5M5qLbLLKTeIRl7bHGHqUi/O3uhXlPpBhtvywugwdPG/7nyVco0pIhf6MsGNRsG/edp6
vT8GbYNUcDrpx8jqai679hjp5FNvo4fzUsgRajiOSK8lymsOstO+9u9oXNDa8YRH/N4ABVk2Iqwi
n45KcC4qH9loYPMOCT39efacfZopvl446Us0UiCB2qX26uuGVdrB7bd+0gdmWxle+d0q+7yCnvGK
51OgmhqZUPov7i+e30C+tYstPXKr1lv7QSlvpyZ3/oRcefaN8miTv+hqKEkBK7/NL/AHY9G+TsG7
MgpIp/K5s49oBGTiHjLGqIC+sZhXjRnE/DkEVo/mFSsvijavE+wbR6axsfnBXh1GLRbwCMedHXjX
n8ckS1q0nNkiOlYxrztgp8MMMcH7KhE99SA95oAoLEPZgAQ1F1CcTzfzth7WqC6JEVmY3VJ4lxC2
iEU1xhkiONucBpMzdSMFkdNuniK4dAq8I90puY8DAwebi/aiG5P5Lp279eUUtM6oGLdMAYqSuXHk
ihD3ae6UZdc3guahORRwR0mtHbtbKXOs5nAea+wC+Iz7EnMAf7YvWMMgtIrRn+yR4xWmvoGEptvQ
d3tR3cYtVosS249ucmUK+juS3PVOr0k1JijuLIYrwuNw9V4FbRE4lclCkLtpaB0XG17pmwlIrqKb
UW2WQKEbcyySXstsbdL07Amp/k/q4gkEtiWXWdg4pwpABvmZA/ln/cKy19XHO8ajicRsekkjhJkd
UGfFhk81L75OExZFpJn/alOLSheKbUWQ5QGBJv/oCEwPDCt9SudBpy0JlZT8vpB20uzgbMykAra2
OwneDib53JbcTKvMGx4B40gb7VHpsPeMFFwpi9F9oU7mafojx2xrwwlDvwYbHhQFLlk/6+R+SR4s
H/lkQzccKXXj5Fb0PRJbgNrMAPpR59+mUZhzqtglcTjUoa6c0QVlfNB3EZxQHDUcyd73AFdNCjP0
wZLODJtlnaz1sK/KcNatO0ARC5Bc0LvkpvUgGZ1/KrACfK74z0hysFNpjFov/gkx++h0xvWUTqG5
kI4KNgg76QF5vLpL5TsG6bcxj1ldlMG5eKnUKKnDUgb+d3d+VNx9U/FDVFkwwTrKZ2osKBsQbM5r
5tYYgcHjc8L+6eHywBgE+6AR86DZ3Bg6UPkuo8TNV3HrVcMV0g2d3igXsThsxFSdGJYzA1Fa1oSB
KEn/Dcm13OtLdM/N+vvRhXzZUqUIX053TmsvvIyB/IC/5X31FZnmf7cRWA4wcyIgi0doq0lpivdA
oZjiSCZxLPTJ6+70nPjDkDawn7fxhZAa2mVBZtaAAgh2qVvhonqLiLboDvd2VUazDAs5YWxnDunD
pzfQqRcDZL+sgnLZIQz4mbtPc58bMw8HbQKM/65dWyA+MuUoeADgygwfgs5o0H2r94u5lVuHvBx5
I9OF6m4OjV5EUb6F93NyxyBk5kugvcEGyq+zYnM2nVpE5v3+xYj3w8vUOVqUt8aaxa27a32z9GUZ
OdCXZ8Qa2esNSJcAJA7kc/YltNUh6wOTQkMsVkSNJNKFTjU1gPysri7bfMoY69scUMSN1CkdoI+9
p7VKo4GoiVFlmrbe0I/sJxjExnb2HmSttjZ7wOz4PIz8J5DR2WKELxzc82r7+1ryymkXyKO+s2JO
yZWf7mJhnjSGV6aMAk6GShjj3wNFsISxVqS7KBJM6GzBLRYLNxK88pYJ02hc3GG3opONmyZUb7oT
9ukDmjBGbabMBHPAjWvivWb/crazR7moqTluiS9Tq/ah8jrvgz+YC9cAeASEvTWb0Oxxa0daoo6U
ECMohueXoLfyAcKaRyI++NoOlrGMTT81xhNB8UpyAIjjaNy8CB0JFZXNAxA2UdIPmnOT6/2TbKAQ
ASflZNgeVC2yV+OPo9TSPeQqqwnjgP3r6rCvRSWubz7BZULmGgwQOp5ZA7esTtNfNUYgMJ5JveKO
AnXIRatLjT3wCfYg4NGRrl3OOyR60blf9MNBZc7nGUamqxlavNYLtmdCECFBcvIMu3+m08/vqFd6
RI8ojiwzaAwRVH2jkon834qtnfNvaiDNGHIiqApRJaO4V0ZC8qVQa61Dz+WV2yuF66YPu+optapv
nDzU9SBPiizv2GnB77H4kdMuD0pUmcJI2lMAmoQxZRiRMx8Iz8p7N/wT95oi/TCyXCEfsqpLgZja
rYDHFOAUxz7M+56evaXrKJhVy4WDTegj5V1EPQrAIqJg+WSs+LZwMGNPKZ2B79t5FacgSD4WyaHr
PoxTHzZXrfdwTCBIkOensjL5ulL6Elux2a1FKd70vqU4FEKDcb4wTRIjJ8uE9QWLFsSkyTUm/YmZ
w5V6D26o5evWJDHzIJ4AhCXJg/sX7h3fVRpCmvI7FpQnOtu4A6zOilk6VUmC36Ldnjo4blHZEURH
zjiu9fnKb0dpg/q7Y5KlvRWw3TWoKZiPxSYF3GKDsS/MfEk152BjNJ9GZE70BOTOPidsbnbsohL3
RIYBh2vZdYB/iTNgW8A+5D0YZOK0hNTOar0AGCbvT1fLyrL8pnOyEDhzUmXj5KFSxV34+P1K7yBR
ZlUg5mNk65NWzMomaUpwyCNxy0lu7HwAe1R4iaBCIiHC1KFXEw9gmSGXPkCwGdZ7iN+aDbSYSXUg
WHpinqpKbvK4oVD9PO9tHvb9JxEAJ8V8chbIMjI41j/irCfo17uKaV0+tGDaHpa78PqXSG2ZZevw
EYijDiK3qjt4FzgniMuw7wSZNf2e0II8tcUVSobIdW/QFitirsZHh3LzMYbOk1DKqxKLPEP1C9Qe
/7lOmjUQHtoIi4wxCtNYDM6JC0Xyo59gijrNHkqxjiqmRSJgPHM5vNX8bcm1Soll0cKsGAvjmlfa
H6oa6o/gjLoeydzNtX0+614sU3/Ct5nk6pBSD7PSOVqq2fZrtvQSlA+wI6cE8tIZkVXF3dNf2N8z
JQGZ/ofujBFRfFl2jNaH8jJF0PYgxKd1xy3p+gCo6QTUP2S1LwlxZugHzrYnwwDGwE4DrQlylVJK
6ceIkeicQU77p2C1ar6IG7Hie3Ia9xDp814VXecL8sRDIvI9vEyObDl4QfVED36+aS2A0+RtCbBP
WEsKAT7juYyhdVp03rstolILV1KOf0R/ZXB5SRMYMO7g2SEuedMM0OEarsjxa6Y6lRiH/9c1n3aT
xGpNagNb+wPmmO3g54rac89fE2SYfgM2oPd2xaLvGUC277lLid81HeK7vhbTvcww1d7tXsAaMBY3
t/6pawzYq45DGTN5zzpS6UJ+6bNx7OaimCqLsib63F1XYIA1qyCzbnSZqJ1vpZDjqeVXrPlJSVbF
BB5GimO0ATESZc2yVHsRYT0RFGZBIiSTogXz6zzbsV683+FCRw1e+F53yM/OGOtAyI8Hac1G55Xo
y2ZBRPW7WmQFsdwyFhv12O7t2LZisbRw+ebY5p47WPneW8ov21ZN1r4XbtoEb7TzxDUQvcAoq/4j
bJC1x8xfueCH4oXd2kt55nUIIBXsFH1xsr+iIzdZgQKYuj7EFMEbKrgZPDPaGiKUr6dSngl+UZD/
3DLNWn/4jTLxdIyQCVjJZSxcjg67VFiEFHfkLXRq+zoUAYjF/ukPhap1nBL7BCWumt/scUHhQ0DT
6vmVx6fhyWYSuqoH7WdL8D9r4hoGZFPy77BCt+H59drApl5WtKUSQnRINnvdUd1nM3kyKcVPrgka
L+4w1AHMM+lH8AlQ5nFetSk+G8p7DB8t2xV9g/lNpfESJ8V4syZ7O4pZ6oRTFQI2flznIbxEro38
ylUt6HV5Hsj/rHO5FX8CeL/venu7vIQJC+odeUdGuViasC3/LLnMhsxGpSOZj1JwiUaM2s12qZJs
nII59Airuev4kxax5YzLMshYzoFmLsxi2wO5MGSDvRO4MNWw/P5bK44z/ibj3/Wmh9YwUgYNkys7
nKKJtzJAxxMgM6MEr+x2oSYLjBh+hI1ZofQw6KqHp4wOfjVSFjd+I1suLTS/KHSJCxiXSCLuwIyL
+D20yTTRxxkFNR5HV41BvmlfWavpo4qRjpVk/SJyHAwBrALhfL8w8Tg1pBQQ20Q8kvntAV0aCtIv
ycFIrNgSurPjAuGm7uLo0RBptDApNe2AxNB/9y9siA+mQ3mBheAp9+jW/j0o/tKcZlYNVwec6012
51Sfqo6jvF8RUtIUEGuOBTZRC8DiJR+YQNsk/2pZ2TNCpLAt/MPm044jcIJgZP6c5UHLULsgOYBD
H5XGW74qkE6TAlAc2WLnBXdTyq8OSCRYFizfmdVfPXU3/JUvr/7/LPP2Pxmbp6p+LS0joCHmBSQ+
ldQWf2e8EZ4NGUe8YK+p7GewA2tWKrH1zeCL8dq8BRtH7SNYw2WiRTf4DCq8q9RbuHmZCvKnO3B+
XdYimP++v5gaw6PQNZbnsBJOIpZ4u2rypMKagQZM7UswFZoppC+TqFkRFXUFYvy8VYGL9kRV/VYo
7qrhq2dC0UFwZH9Gr3Y/lQwzuHTC47kZ4DyHFMnWOtibTpuuzUVCuW2WKB1rr50kLf5OryCvUIYZ
WPFOnLseZSd+fTFR8flBFmzWHpGvZo+wE7Grxt8Ev5w4f2N7bWT9EyDPOYidDnzBGcpGkB+Y8Tmr
oV+z7IgKd4P/Y50PG1A5g1NJyuNQIwBzLBq5WEv3XMG7GQGFJ6klE4O933PuCCmNEtxQlZZSJsQN
gIYh7x+k+zSKa3K6HzK9iJgx4xgzCyebEWvsYNxs00JruWkcNbEe96VsdpLG7OiiGw3neDDXJROj
2ILewdDcMY48F+JrIRw8sEsQwOYKlLES/SCh82Fnj1wcvuRh60r4Ug+TL/afWGqyhTW/qT/eXqcw
6MlyKtuXlLe8qACtn6bYZewq8OEPj1G1DUdXkeLQvjemzc9sahSAJFLmFQ2bh6L1T8uPj6te75ga
mPV4iwYrABkntmY1MpgBpDGo4VsEPWLNStEKWlNswNpqa+6dVxp/8rtlXDMAJvgJvGLoHuYS/+8C
ZlFm/D8qaAHZT0hoUTR1mh70s6c7fsaPK0dEB9C/tYhK6K/pCKCP2m8G8IPHdQpBrGj1/oRszpyH
J41CldmUoIQRzoqCaneq62c2Bm5kgAaFKefu7nycQsicNutXSxrLex4CVQD8Qr777kRHsy36/2/7
uxigNgpYpOQCN+3t3imxNjCEaoOXA8UNr4TQuTXRlrj9wS828htkneL3AwdbUowVdbt0oShKOgPI
Zx6vPrJfNi7DEvMkb9ffsemAonz1tzVNNysNpAqhmgSyyrbMux1LiZ0Naonzld85hDAtOr4tLPbe
F/+KYBy2x2xbJtKpDEMskVs5Pk/5qzPp7LAXk/6cF46ykadsqO70T4uXvykYEfghpHpMoH7wzc7Y
ww+bP222VsaGlhomeGrhnekL0lpLJUAWZue25QlBom/Y6L/GpDD/5SClpIjLkQizKaHHX9WaAjlE
Y1yT73mnR/mGBw+n894tBqpnDth3WQ2++m21CZucLtvY7ZaMGOmz1i/Ag2DN4+bUFBtrBJFTHEOQ
a9gk4C6V1ZIHzUCPnroznsJawUU/FckO0kQ4B3OqsYfce6Jm6ONHaoFlHFFmAP6a7NlQTG6y9WnE
6KoXcpAbWT8/XdcSw1IRxpvwrW6/rHvl/Z6dWTV8C3tAtMJXUx/4lkEqvplNDw0/07OVGkw67HZn
A8Lq6RJITvFGY4GWXbss5BIMS35aepZkR7j6heG6/mXEre72qrzQIvsgs656cvCmOkhjI3NxBRef
hh+Un2yiZS4woC8taIik/0Nxg1LLzlLXUDOEf370unIQw+AtmmOqLJ68UWHJS9Ft47udJAg+D2mS
ErWrgS+b4wBZYKWQMO+P6UyJlPYHm45Nd9NIPufWiLyY2HoXbdUxXnbFEPjs3oxpXa5OZHMvkal4
CiXiQ8bvzYy3j/F6ODcEUKjBVpJ5EN1MP3fIEvIkx0UtraER/BDevz41uOsDWB0AgzRobdkVzOiP
tuisuEiDU8F7pLdoA3+6/u9u1E7bk8ZUOgDcOJSLdcctnV+xNJ6OMOO4xgEORfmus7nhrii4ArYd
CKq2MHwzb4ctOAjEEJeOePpxCNVrBBvxrRtZfu8hkLzjdwNq2zM0nFfTzVTKLTbeJqBsq/L53bVD
1yuJM8UToPe7Xv05AYFi807a5Q6EBG60TTYbw/iWmsaA2PNaLCR+HSdmuodAjGTLFJceRd+3mPmU
HFkFXAG9MS/IgscH2HDwBqm65iKLPInqSvdn83XikOepezKMgFthepZ6fZW6Bzo5+CzifeMhAjul
ufZR7raedBdv8qXI6z//USXdCTD2S42a5ze9bKOVqE67lpFdr1MAmD5MV4UpCLgbxvSqb6Q86S4N
9uNldEI2zKKonN4Z86NPG1hjSb51jzb8NgZnbbG8DwiBc4BG7e5KolLtgp1CgPG//QzebUYbkRJC
dg7EgShllvG2HoBBdSC8oKf/rFbvK08c/cgz/oT9xJ+lNbJPfbLf8bJYdGWk/ZKPLbjk0ff6/oAl
4lGffj+0kDO3Jri2S2PqVXETgaVNZjn//aVdKK8Lh4AvIG8or6ywESPkbVFkSrxZOEe0cyHQNiqb
ldTzL35bQuI7chYqpt5sstYqf1U2/D4sMRW5tgZsCrpxuXv1Qa6alONshZ+yMEsu8OO1GxV2bgbG
al/R363JrBqu2OwzWxy3YVj02hgzbYpO1Ox8HhVP/pAQAr4ZmyptIpgdE3+pRFqLcB+lQfQnZzft
GGh/7tN5CjHCEyTKtLkiT8o3HRR1/SA6MyOWzXywsYvMHfFCEI+6vOl48V6KL2kWPU1Qc6ACuC82
Idy+2UYVT1L7ysnVuus8wmdw3oWkwfTulvptuXgWncUPyxZMtfzZb9g3SdZ/S+q6RsiCPqodWlO2
iTTbqHYe3hgfvtQrVBRhRrq8SnY0gRDGX6wYDKF3M26t/thJT2icF5u8FBF4pAQ1xxJzshgRhvqd
f/+i/hZOAzu5HbeO79QkXrxZ96vqIM1TbSKeoEj7OP/5w7g36zbarHEr5yzmyHs4J+4Dg5Vl8J8x
/+cy0XMQsAJn4QB2BNZdLSHXvBNfO6pob4dRHcq4gLmvo/TVq/f853CaQGgBFQ4sw1SM1NFx8MWt
KmS2D1B3sX4etX1ajZKnGp7XcZvBo9Xg1QZNosBYhIgCfUVwUIqMVOU+1BD7Hn2vpi1AZtzlfR2D
Lstw4qk60Fzt90xB1pTxqd1og9cNHV3b/VD3Rgg7NsvqH1shXWx6Mxu3KdSg3sBiE/ynYITBaeYK
ikOFfCWBevXGJUKlq0k0uJVrDqiu72oUwl2fNFVLv59zn4AwP5pJhCXyDcw9T0wXZ3fLEffs7I1k
584CCQmzh6xW4EMcOxDW7C2lQNOjaO2K57Yhug5yinOo2dyxEIHxsT5L+W6V2KjRCT0L8qE7BtJ3
9qXgdpbAfcsjBp8iKQ1mFhV4PdcEVWJHyeaLXhgLHihmFpv06VOYw0G0yjLfgpzSiUom2chwylhD
JIpi/Mj/fD14gnh1JkOdwzWGxY9jufnOuY8bRcEKviti9HS6Cc4mnxyiK/XZJhOweTQOMwHQVnXo
1PO0EMfcl0qvPopHJowiIeO4BwtBY0VElMQxNQmAB6+e9uda//NN+77Ge6CBBbkMkY75tcay1x5k
GYmoW57YcJ80tmHCQutzUyGcfDtHpbibyGnuISrPa05U5zvcrJ2Nu14NKm9Ze8dJ2UBUM+zBQmZp
R5Icpqf6kkCgcbxf46QEu8rKGfZoIpMJDl03UzfMDtaERcH6PdLggnYGrOQ/u8cW19MV1phAKmEI
WJ7bKYzZocBqe9hwjHFAJZpFElXiPxQyrNZ3lJZlGHSZEP0XTWzHxpEjALBjcE+f0SZ4a8xpxE7N
aU5UK1icsgaVaRMl8Dkjw5nTpoTaL1WKJHSL+o5Bj/f13jsgXEnGIZ2nAQ/bHgKMsppOV4CS7PcY
e+b9dvu/efAcEnihrvZ5o5qfCWgAw6Tq/it8mJSly0kC4LAxfAj8dX4gybqiymxmygXWStr0DuJ0
AKV40deObs+Unmcqg7t9LOTq5XuCTMINDL9o3FJTZb7aMm/T4fXDH4C38+1tSzDJfzm3O+9BtPwZ
so8QTW9oLOrbqBmT1J+r0TWtNHEnZE4Jy3wGxFC+R+0CwmmjcM7uvxOVI6EITq/7pPUNsJfYQS1s
42sSNRLa3/RyzYEnHPaBfxfP1uGzoZEt68no2KdFXcbN1UDLOu3x4G/MClMR3FLRBAW6TD64xbMx
8nyU3CSk9sb+7NXg6VAJBuwkad/zQ933RyGn+DB8B3AwyObaNNBgCzGsO5UByroLDLXROAw3udXa
01W2/4pkvTeLZQVY1mSkuvw+iNBall2P3d5HIKRUYWfOPfyD50gVcWM/+4easzVtcL4Erm1DQ2Kc
FeiM1N42s0vZwAd6CpaQDP8u0/7C32D7aho/1GCnlYFelK0qBKYJ/biasUkFNiJWTNjr34pILcpy
Oq6Y0rqE75Z29t6vvqRBjnZpFhvzysVzGaj8VAcXIN83P4D6iSjmM+2FiMrdhVLJJOTQDByvbm7m
0XKtKvOCLb9OwxizmKXJ5HDHf+P3wh4XQdKH0wL27v5cz57Ce7Nq8jyqjZHIJgZTfkWWPELYygs3
AcQBxRC/seKFdFGP4wNX9t75rXCa4xiqZ9N1fR4ZY869HiQAM/DzciF8FWx27sF8fYYy97Ryd+K3
V/bDX8M1+6CzJhOCRpuqnpuGpM10JmJ7xdWZEq/OQh3s3DechdC+a3A2F2ZteQl/iJbRbtBufzuk
5VIUSg0yR+K9mble4m1Nx2HQRLbU2tWhYaTwaBW57lWV2odl6By0ZTpmT+YnDViBeW1yk9QLxmsu
jCDPUtWySCYKnVwHIfozsYt3zZPKpPEmQc0gfgakXqbgA05uEenxiyozuN+W7t1HxkgxyY1IcScI
I0zCqMUF5qIh+RHjjRtBYh6wNCBeHMUulBIoS3EUPfZV/u96xu/oPTWOvgNkdKvbG12BTLn1VyFo
YirMg4MYs6SKKw6JbqdTZLpjTvknVzAar3VM+mPVTNoOCSrSipp7MgGBQOyt6PF5NMKnwZM/0sj+
fdEN1TcYigbfHHbdLkC/EGu2jObTGJHoduA1oboatVCEOcpVltBvZg9GXvPHSKc8luYtPqFMblwH
CynEQ197sIB+umS037vjuNIHYChOTpEtJrOUp53YRsrWxYkL4u8Ko8yerYASJ6bgDEJ7r5TAaH/A
tosWQLadQ8tDCMfVm52zDHxXiJmzUyCpJ/gkzNNb/gxFfFJVSw8pIA/esNlMSbJwBdYo0fDEgpol
BEB3dWHeFpWWaT4kK8p0My9vIBp0ABuLWVSmQ5K1Ed5mF5/J7dck2AXQcB8zdYwDCS/R25JW5gyO
AUR0XVdmWob5THdfrxOvChevuefUPbzARauS+w+8JwgvF1YPJjEU1xPs9zlaPcetwDN/m+wSuUna
ZziLaXIiiGxwwexVW159KAwbvEJriAuHKE0tG6A/k2+6bZ02mc70sBRXhJ0HMwHJ8K3uXJfA4Nlv
XS2CzL3dPifzBXyMH46T/3FiOcrSrsPDRVFyEPNCoHxklF9QtQOYwKeJL/COz0wPsANFljhIwAeJ
gIXwVcjm7iI1njtPaJOtwvDdjCnsWkHPL+sXzxtLNM4YqONoDApST4wqXqtrfNM7or1XSDzgPNrT
UQ0GCI3usg5bVBBI31GMSs665acG6HCTLXhIDzcf56JU24x362Gnxg==
`protect end_protected
|
mit
|
917cbcb9d0df09e3ec3ee281cdb4f4ba
| 0.952143 | 1.839906 | false | false | false | false |
mitchsm/nvc
|
test/regress/file1.vhd
| 5 | 1,344 |
entity file1 is
end entity;
architecture test of file1 is
type char_file is file of character;
file f1 : char_file;
type string_file is file of string;
file f2 : string_file;
file f3 : string_file open WRITE_MODE is "test2.txt";
begin
process is
variable c : character;
variable s : string(1 to 3);
variable len : natural;
variable status : file_open_status;
begin
file_open(f1, "test.txt", WRITE_MODE);
write(f1, 'x');
write(f1, 'y');
write(f1, LF);
file_close(f1);
file_open(f1, "test.txt");
read(f1, c);
assert c = 'x';
read(f1, c);
assert c = 'y';
read(f1, c);
assert c = LF;
assert endfile(f1);
file_close(f1);
file_open(f2, "test.txt", READ_MODE);
read(f2, s, len);
assert s = "xy" & LF;
assert len = 3;
file_close(f2);
write(f3, "hello");
file_close(f3);
file_open(status, f3, "test2.txt", READ_MODE);
assert status = OPEN_OK;
read(f3, s, len);
assert len = 3;
assert s = "hel";
file_close(f3);
file_open(status, f3, "not_here", READ_MODE);
assert status = NAME_ERROR;
wait;
end process;
end architecture;
|
gpl-3.0
|
9fa465f49b289decefb6edda427acb57
| 0.511905 | 3.310345 | false | true | false | false |
HackLinux/THCO-MIPS-CPU
|
src/ID_EXE_Register.vhd
| 2 | 4,582 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:47 11/22/2013
-- Design Name:
-- Module Name: ID_EXE_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.common.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ID_EXE_Register is
port(
clk : in STD_LOGIC;
--cmd cmd
command_origin_or_nop : in STD_LOGIC;
--common input
in_pc : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_a : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_b : in STD_LOGIC_VECTOR(15 downto 0);
in_imm : in STD_LOGIC_VECTOR(15 downto 0);
in_rs : in STD_LOGIC_VECTOR(2 downto 0);
in_rt : in STD_LOGIC_VECTOR(2 downto 0);
in_rd : in STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
in_alu : in STD_LOGIC_VECTOR(3 downto 0);
in_a_src : in STD_LOGIC_VECTOR(2 downto 0);
in_b_src : in STD_LOGIC_VECTOR(1 downto 0);
in_reg_result : in STD_LOGIC_VECTOR(1 downto 0);
in_mem_src : in STD_LOGIC_VECTOR(1 downto 0);
in_flag_RA : in STD_LOGIC;
in_flag_IH : in STD_LOGIC;
in_flag_T : in STD_LOGIC;
in_flag_SP : in STD_LOGIC;
in_T_src : in STD_LOGIC;
--mem cmd
in_mem_cmd : in STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
in_flag_reg : in STD_LOGIC;
in_reg_src : in STD_LOGIC_VECTOR(1 downto 0);
--common output
out_pc : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
out_imm : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
out_reg_a : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
out_reg_b : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
--memory data
out_mem_data : out STD_LOGIC_VECTOR(15 downto 0) := ZERO;
--result register
out_res_reg : out STD_LOGIC_VECTOR(2 downto 0) := "ZZZ";
--exe cmd
out_alu : out STD_LOGIC_VECTOR(3 downto 0) := ALU_NULL;
out_a_src : out STD_LOGIC_VECTOR(2 downto 0) := ALU_A_SRC_ZERO;
out_b_src : out STD_LOGIC_VECTOR(1 downto 0) := ALU_B_SRC_ZERO;
out_flag_RA : out STD_LOGIC := WRITE_RA_NO;
out_flag_IH : out STD_LOGIC := WRITE_IH_NO;
out_flag_T : out STD_LOGIC := WRITE_T_NO;
out_flag_SP : out STD_LOGIC := WRITE_SP_NO;
out_T_src : out STD_LOGIC := T_SRC_IS_SF;
--mem cmd
out_mem_cmd : out STD_LOGIC_VECTOR(1 downto 0) := MEM_NONE;
--wb cmd
out_flag_reg : out STD_LOGIC := WRITE_REGS_NO;
out_reg_src : out STD_LOGIC_VECTOR(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- addition output
cur_rs_num : out STD_LOGIC_VECTOR(2 downto 0) := "ZZZ";
cur_rt_num : out STD_LOGIC_VECTOR(2 downto 0) := "ZZZ"
);
end ID_EXE_Register;
architecture Behavioral of ID_EXE_Register is
begin
process(clk)
begin
if (clk'EVENT and clk = '1') then
out_pc <= in_pc;
out_imm <= in_imm;
out_reg_a <= in_reg_a;
out_reg_b <= in_reg_b;
-- add by xjl
cur_rs_num <= in_rs;
cur_rt_num <= in_rt;
-- add by xjl
case in_reg_result is
when "00" =>
out_res_reg <= in_rs;
when "01" =>
out_res_reg <= in_rt;
when others =>
out_res_reg <= in_rd;
end case;
if (command_origin_or_nop = COMMAND_ORIGIN) then
case in_mem_src is
when WRITE_DM_DATA_SRC_A =>
out_mem_data <= in_reg_a;
when WRITE_DM_DATA_SRC_B =>
out_mem_data <= in_reg_b;
when others =>
out_mem_data <= HIGH_RESIST;
end case;
out_alu <= in_alu;
out_a_src <= in_a_src;
out_b_src <= in_b_src;
out_flag_RA <= in_flag_RA;
out_flag_IH <= in_flag_IH;
out_flag_T <= in_flag_T;
out_flag_SP <= in_flag_SP;
out_T_src <= in_T_src;
out_mem_cmd <= in_mem_cmd;
out_flag_reg <= in_flag_reg;
out_reg_src <= in_reg_src;
else
out_mem_data <= HIGH_RESIST;
out_alu <= ALU_NULL;
out_a_src <= ALU_A_SRC_ZERO;
out_b_src <= ALU_B_SRC_ZERO;
out_flag_RA <= WRITE_RA_NO;
out_flag_IH <= WRITE_IH_NO;
out_flag_T <= WRITE_T_NO;
out_flag_SP <= WRITE_SP_NO;
out_mem_cmd <= MEM_NONE;
out_flag_reg <= WRITE_REGS_NO;
end if;
end if;
end process;
end Behavioral;
|
apache-2.0
|
9aeba88f165729025f0cd7ba8e658061
| 0.594282 | 2.711243 | false | false | false | false |
mitchsm/nvc
|
test/elab/comp.vhd
| 5 | 1,733 |
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in integer );
end entity;
architecture test of e2 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e3 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e3 is
begin
end architecture;
-------------------------------------------------------------------------------
entity foo is
end entity;
architecture test of foo is
component e1 is
generic (
g : integer);
port (
x : in integer;
y : out integer);
end component;
component e2 is
generic (
g : integer);
port (
y : out integer);
end component;
component e3 is
generic (
g : integer);
port (
x : in bit;
y : out integer);
end component;
signal x : integer;
signal y : integer;
begin
e1_1: e1 -- OK
generic map (
g => 5 )
port map (
x => x,
y => y);
e2_1: e2 -- Error
generic map (
g => 5 )
port map (
y => y);
e3_1: e3 -- Error
generic map (
g => 5 )
port map (
x => '1',
y => y);
end architecture;
|
gpl-3.0
|
27616520b4cbab9f1a18ff300c7cc93e
| 0.379688 | 4.747945 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/names/ioblock1_e-rtl-a.vhd
| 1 | 14,821 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock1_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock1_e-rtl-a.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ioblock1_e-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock1_e
--
architecture rtl of ioblock1_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_r_io --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(4 downto 0);
en : in std_ulogic_vector(4 downto 0);
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ioc_r_io
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
iosel_ms_min <= p_mix_iosel_ms_min_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_disp_2
ioc_disp_2: ioc_r_io
port map (
di => di2(0), -- io data
do(0) => disp2(0), -- io data
do(1) => display_ls_min(0), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(0), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(0), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(0), -- Display storage buffer 1 ms_min
en(0) => disp2_en(0), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_12, -- data in from pad
p_do => pad_do_12, -- data out to pad
p_en => pad_en_12, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_2
-- Generated Instance Port Map for ioc_disp_3
ioc_disp_3: ioc_r_io
port map (
di => di2(1), -- io data
do(0) => disp2(1), -- io data
do(1) => display_ls_min(1), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(1), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(1), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(1), -- Display storage buffer 1 ms_min
en(0) => disp2_en(1), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_13, -- data in from pad
p_do => pad_do_13, -- data out to pad
p_en => pad_en_13, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_3
-- Generated Instance Port Map for ioc_disp_4
ioc_disp_4: ioc_r_io
port map (
di => di2(3), -- io data
do(0) => disp2(3), -- io data
do(1) => display_ls_min(2), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(2), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(2), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(2), -- Display storage buffer 1 ms_min
en(0) => disp2_en(3), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_14, -- data in from pad
p_do => pad_do_14, -- data out to pad
p_en => pad_en_14, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_4
-- Generated Instance Port Map for ioc_disp_5
ioc_disp_5: ioc_r_io
port map (
di => di2(4), -- io data
do(0) => disp2(4), -- io data
do(1) => display_ls_min(3), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(3), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(3), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(3), -- Display storage buffer 1 ms_min
en(0) => disp2_en(4), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_15, -- data in from pad
p_do => pad_do_15, -- data out to pad
p_en => pad_en_15, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_5
-- Generated Instance Port Map for ioc_disp_6
ioc_disp_6: ioc_r_io
port map (
di => di2(5), -- io data
do(0) => disp2(5), -- io data
do(1) => display_ls_min(4), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(4), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(4), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(4), -- Display storage buffer 1 ms_min
en(0) => disp2_en(5), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_16, -- data in from pad
p_do => pad_do_16, -- data out to pad
p_en => pad_en_16, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_6
-- Generated Instance Port Map for ioc_disp_7
ioc_disp_7: ioc_r_io
port map (
di => di2(6), -- io data
do(0) => disp2(6), -- io data
do(1) => display_ls_min(5), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(5), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(5), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(5), -- Display storage buffer 1 ms_min
en(0) => disp2_en(6), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_17, -- data in from pad
p_do => pad_do_17, -- data out to pad
p_en => pad_en_17, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_7
-- Generated Instance Port Map for ioc_disp_8
ioc_disp_8: ioc_r_io
port map (
di => di2(7), -- io data
do(0) => disp2(7), -- io data
do(1) => display_ls_min(6), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(6), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(6), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(6), -- Display storage buffer 1 ms_min
en(0) => disp2_en(7), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
p_di => pad_di_18, -- data in from pad
p_do => pad_do_18, -- data out to pad
p_en => pad_en_18, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_disp_8
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
bf247abb6ba24568ed507b7e2a913463
| 0.587072 | 2.470167 | false | false | false | false |
blutsvente/MIX
|
test/results/padio2/pads_eastsouth-struct-a.vhd
| 1 | 6,002 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pads_eastsouth
--
-- Generated
-- by: wig
-- on: Mon Mar 5 15:01:50 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pads_eastsouth-struct-a.vhd,v 1.6 2007/03/05 15:29:26 wig Exp $
-- $Date: 2007/03/05 15:29:26 $
-- $Log: pads_eastsouth-struct-a.vhd,v $
-- Revision 1.6 2007/03/05 15:29:26 wig
-- Updated testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of pads_eastsouth
--
architecture struct of pads_eastsouth is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc
-- No Generated Generics
port (
-- Generated Port for Entity ioc
bypass : in std_ulogic_vector(1 downto 0);
clk : in std_ulogic_vector(1 downto 0);
clockdr_i : in std_ulogic;
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(1 downto 0);
en : in std_ulogic_vector(1 downto 0);
enq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
iddq : in std_ulogic_vector(1 downto 0);
mode_1_i : in std_ulogic;
mode_2_i : in std_ulogic;
mode_3_i : in std_ulogic;
mux_sel_p : in std_ulogic_vector(1 downto 0);
oe : in std_ulogic_vector(1 downto 0);
pad : inout std_ulogic;
pd : in std_ulogic_vector(1 downto 0);
res_n : in std_ulogic;
scan_en_i : in std_ulogic;
scan_i : in std_ulogic;
scan_o : out std_ulogic;
serial_input_i : in std_ulogic;
serial_output_o : out std_ulogic;
shiftdr_i : in std_ulogic;
tck_i : in std_ulogic;
tenq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
updatedr_i : in std_ulogic
-- End of Generated Port for Entity ioc
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_96 : std_ulogic;
signal mix_logic1_97 : std_ulogic;
signal mix_logic0_32 : std_ulogic;
signal mix_logic0_35 : std_ulogic;
signal clkf81 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal clockdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal default : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_1_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_2_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_3_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pmux_sel_por : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal ramclkin_o : std_ulogic;
signal ramd_12 : std_ulogic;
signal ramd_byp_i : std_ulogic;
signal ramd_enq_i : std_ulogic;
signal ramd_i : std_ulogic_vector(12) -- __W_SINGLE_BIT_BUS;
-- __I_OUT_OPEN signal ramd_o : std_ulogic_vector(12) -- __W_SINGLE_BIT_BUS;
signal ramd_oe_i : std_ulogic;
signal ramd_pd_i : std_ulogic;
signal ramd_tenq_i : std_ulogic;
signal res_f81_n : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_in_ramd_12 : std_ulogic;
-- __I_OUT_OPEN signal s_out_ramd_12 : std_ulogic;
signal scan_en_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal shiftdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tck_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal updatedr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_96 <= '1';
mix_logic1_97 <= '1';
mix_logic0_32 <= '0';
mix_logic0_35 <= '0';
clkf81 <= clkf81_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
clockdr_i <= clockdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
default <= default_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_1_i <= mode_1_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_2_i <= mode_2_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_3_i <= mode_3_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
pmux_sel_por <= pmux_sel_por_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
res_f81_n <= res_f81_n_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
scan_en_i <= scan_en_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
shiftdr_i <= shiftdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
tck_i <= tck_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
updatedr_i <= updatedr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_ramd_12
ioc_ramd_12: ioc
port map (
bypass(0) => ramd_byp_i, -- __I_BIT_TO_BUSPORT
clk(0) => ramclkin_o, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => open, -- __I_OUT_OPEN
do(0 downto 0) => ramd_i, -- __W_PORT
do(1) => mix_logic1_96, -- __I_BIT_TO_BUSPORT
enq => ramd_enq_i,
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
oe(0) => ramd_oe_i, -- __I_BIT_TO_BUSPORT
oe(1) => mix_logic0_32, -- __I_BIT_TO_BUSPORT
pad => ramd_12,
pd(0) => ramd_pd_i, -- __I_BIT_TO_BUSPORT
pd(1) => mix_logic1_97, -- __I_BIT_TO_BUSPORT
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_35,
scan_o => open,
serial_input_i => s_in_ramd_12,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
tenq => ramd_tenq_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_ramd_12
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
65e7a3780011809b15f16dd2f5527ba0
| 0.593635 | 2.480165 | false | false | false | false |
agural/FPGA-Oscilloscope
|
FPGA/oscilloscope.vhd
| 1 | 4,460 |
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-- CREATED "Sun Mar 09 12:12:32 2014"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY oscilloscope IS
PORT
(
RESET_IN : IN STD_LOGIC;
HSYNC_IN : IN STD_LOGIC;
CLK_IN : IN STD_LOGIC;
SRT_IN : IN STD_LOGIC;
CS_IN : IN STD_LOGIC;
RW_IN : IN STD_LOGIC;
RAS : OUT STD_LOGIC;
CAS : OUT STD_LOGIC;
TRG : OUT STD_LOGIC;
WE : OUT STD_LOGIC;
BUSY : OUT STD_LOGIC;
ADDR : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END oscilloscope;
ARCHITECTURE bdf_type OF oscilloscope IS
COMPONENT lpm_mux0
PORT(data0x : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_constant1
PORT( result : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_constant2
PORT( result : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_counter1
PORT(sclr : IN STD_LOGIC;
clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_constant0
PORT( result : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT scopevram
PORT(clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
cs : IN STD_LOGIC;
rw : IN STD_LOGIC;
srt : IN STD_LOGIC;
RAS : OUT STD_LOGIC;
CAS : OUT STD_LOGIC;
TRG : OUT STD_LOGIC;
WE : OUT STD_LOGIC;
ACK : OUT STD_LOGIC;
BUSY : OUT STD_LOGIC;
AS : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
SIGNAL ADDRESS : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL CS : STD_LOGIC;
SIGNAL RESET : STD_LOGIC;
SIGNAL RW : STD_LOGIC;
SIGNAL SYS_CLK : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;
SIGNAL SRFF_inst3 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_3 <= '1';
SYNTHESIZED_WIRE_4 <= '1';
b2v_ADDR_MUX : lpm_mux0
PORT MAP(data0x => ADDRESS(8 DOWNTO 0),
data1x => ADDRESS(17 DOWNTO 9),
data2x => SYNTHESIZED_WIRE_0,
data3x => SYNTHESIZED_WIRE_1,
sel => SYNTHESIZED_WIRE_2,
result => ADDR);
b2v_inst : lpm_constant1
PORT MAP( result => ADDRESS(17 DOWNTO 9));
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_3)
VARIABLE synthesized_var_for_SRFF_inst3 : STD_LOGIC;
BEGIN
IF (SYNTHESIZED_WIRE_4 = '0') THEN
synthesized_var_for_SRFF_inst3 := '0';
ELSIF (SYNTHESIZED_WIRE_3 = '0') THEN
synthesized_var_for_SRFF_inst3 := '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
synthesized_var_for_SRFF_inst3 := (NOT(synthesized_var_for_SRFF_inst3) AND SRT_IN) OR (synthesized_var_for_SRFF_inst3 AND (NOT(SYNTHESIZED_WIRE_5)));
END IF;
SRFF_inst3 <= synthesized_var_for_SRFF_inst3;
END PROCESS;
b2v_inst4 : lpm_constant2
PORT MAP( result => ADDRESS(8 DOWNTO 0));
b2v_ROW_TRANSFER_COUNTER : lpm_counter1
PORT MAP(sclr => RESET,
clock => HSYNC_IN,
q => SYNTHESIZED_WIRE_0);
b2v_SRT_COL_START : lpm_constant0
PORT MAP( result => SYNTHESIZED_WIRE_1);
b2v_STATE_MACHINE : scopevram
PORT MAP(clk => SYS_CLK,
reset => RESET,
cs => CS,
rw => RW,
srt => SRFF_inst3,
RAS => RAS,
CAS => CAS,
TRG => TRG,
WE => WE,
ACK => SYNTHESIZED_WIRE_5,
BUSY => BUSY,
AS => SYNTHESIZED_WIRE_2);
SYS_CLK <= CLK_IN;
RESET <= RESET_IN;
CS <= CS_IN;
RW <= RW_IN;
END bdf_type;
|
mit
|
9d665d2eb771895c5b6fc223039fa4ee
| 0.685874 | 2.989276 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/lpm_compare2.vhd
| 1 | 4,448 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare2.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare2 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
aeb : OUT STD_LOGIC
);
END lpm_compare2;
ARCHITECTURE SYN OF lpm_compare2 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (10 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aeb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(10 DOWNTO 0) <= "11111001111";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
aeb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 11
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
aeb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "1999"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "11"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
-- Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL "dataa[10..0]"
-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
-- Retrieval info: CONNECT: @datab 0 0 11 0 1999 0 0 11 0
-- Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
e90070142c6de28653c0c641a7d5ddfb
| 0.65625 | 3.700499 | false | false | false | false |
mitchsm/nvc
|
test/regress/slice3.vhd
| 5 | 589 |
entity slice3 is
end entity;
architecture test of slice3 is
type bvv is array (integer range <>) of bit_vector(7 downto 0);
signal x : bvv(1 downto 0);
signal y : bit_vector(3 downto 0);
begin
process (y) is
begin
for i in x'range loop
x(i)(3 downto 0) <= y;
x(i)(7 downto 4) <= X"0";
end loop;
end process;
process is
begin
wait for 1 ns;
assert x = ( X"00", X"00" );
y <= X"f";
wait for 1 ns;
assert x = ( X"0f", X"0f" );
wait;
end process;
end architecture;
|
gpl-3.0
|
437ea18ad71b38cad37560b0fe44e5b6
| 0.516129 | 3.327684 | false | false | false | false |
mitchsm/nvc
|
test/lower/cond1.vhd
| 4 | 393 |
entity cond1 is
end entity;
architecture test of cond1 is
signal x : integer := 5;
begin
process is
variable y : integer;
begin
if x = y then
y := 2;
end if;
if x = y + 1 then
y := 1;
else
y := 3;
null;
end if;
report "doo";
wait;
end process;
end architecture;
|
gpl-3.0
|
126e4acfc735bb8ba12f6b9ae97794b3
| 0.447837 | 4.051546 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/inst_b_e-rtl-a.vhd
| 1 | 2,922 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_b_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:33:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_b_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_b_e
--
architecture rtl of inst_b_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_xa_e -- mulitple instantiated
-- No Generated Generics
port (
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end component;
-- ---------
component inst_bb_e -- bb instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_bb_e
port_bb_o : out std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_bb_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
udc: THIS GOES TO DECL of inst_b_i
begin
udc: THIS ARE TWO LINES in BODY of inst_b_i
SECOND LINE
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_aa_ba <= p_mix_signal_aa_ba_gi; -- __I_I_BIT_PORT
p_mix_signal_bb_ab_go <= signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_ba_i
inst_ba_i: inst_xa_e -- mulitple instantiated
port map (
port_xa_i => signal_aa_ba, -- signal test aa to ba
port_xa_o => open -- open signal to create port
);
-- End of Generated Instance Port Map for inst_ba_i
-- Generated Instance Port Map for inst_bb_i
inst_bb_i: inst_bb_e -- bb instance
port map (
port_bb_o => signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_bb_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
6be0fce17792083433e4dc6b688f5197
| 0.606434 | 3.040583 | false | false | false | false |
DacHt/CU_Droptest
|
designer/impl1/CU_Main_ba.vhd
| 1 | 27,693 |
-- Version: v11.8 11.8.0.26
-- File used only for Simulation
library ieee;
use ieee.std_logic_1164.all;
library proasic3;
use proasic3.all;
entity CU_Main is
port( CLK : in std_logic;
BEACON_PWR : out std_logic;
CUTTER_EN : out std_logic;
LDO_FRONTEND_PWR : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
PR_OP_PWR : out std_logic;
STX_PWR : out std_logic;
V3_LINEAR_PWR : out std_logic
);
end CU_Main;
architecture DEF_ARCH of CU_Main is
component DFN1
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
Q : out std_logic
);
end component;
component XOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN0
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
Q : out std_logic
);
end component;
component NOR3C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR2A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR3B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component CLKINT
port( A : in std_logic := 'U';
Y : out std_logic
);
end component;
component AX1C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AND3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component IOTRI_OB_EB
port( D : in std_logic := 'U';
E : in std_logic := 'U';
DOUT : out std_logic;
EOUT : out std_logic
);
end component;
component INV
port( A : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN0E0
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
E : in std_logic := 'U';
Q : out std_logic
);
end component;
component AOI1B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN0E1
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
E : in std_logic := 'U';
Q : out std_logic
);
end component;
component AX1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR2A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR2B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component IOPAD_TRI
port( D : in std_logic := 'U';
E : in std_logic := 'U';
PAD : out std_logic
);
end component;
component OR3C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component IOIN_IB
port( YIN : in std_logic := 'U';
Y : out std_logic
);
end component;
component XNOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component IOPAD_IN
port( PAD : in std_logic := 'U';
Y : out std_logic
);
end component;
component AND2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component GND
port(Y : out std_logic);
end component;
component VCC
port(Y : out std_logic);
end component;
signal CLKINT_0_Y, CLK_c, LED1_c, LED2_c,
\system_clock_0/s_time[1]_net_1\,
\system_clock_0/s_time[0]_net_1\,
\system_clock_0/s_time[3]_net_1\,
\system_clock_0/DWACT_FINC_E[0]\,
\system_clock_0/m_time_i[11]\,
\system_clock_0/m_time[11]\,
\system_clock_0/m_time_i[12]\,
\system_clock_0/m_time[12]\,
\system_clock_0/m_time_i[13]\,
\system_clock_0/m_time[13]\,
\system_clock_0/m_time_i[14]\,
\system_clock_0/m_time[14]\,
\system_clock_0/m_time_i[15]\,
\system_clock_0/m_time[15]\,
\system_clock_0/m_time_i[16]\,
\system_clock_0/m_time[16]\,
\system_clock_0/m_time_i[17]\,
\system_clock_0/m_time[17]\, \system_clock_0/m_time_i[1]\,
\system_clock_0/m_time[1]\, \system_clock_0/m_time_i[7]\,
\system_clock_0/m_time[7]\, \system_clock_0/m_time_i[9]\,
\system_clock_0/m_time[9]\, \system_clock_0/m_time_i[10]\,
\system_clock_0/m_time[10]\, \system_clock_0/l_m6_0_a2_7\,
\system_clock_0/l_m6_0_a2_2\,
\system_clock_0/l_m6_0_a2_1\,
\system_clock_0/l_m6_0_a2_6\,
\system_clock_0/l_m6_0_a2_4\, \system_clock_0/m_time[8]\,
\system_clock_0/un14_flag_3\,
\system_clock_0/s_time[6]_net_1\,
\system_clock_0/un14_flag_1\,
\system_clock_0/un14_flag_2\,
\system_clock_0/s_time[4]_net_1\,
\system_clock_0/l_N_13_mux\, \system_clock_0/N_25\,
\system_clock_0/N_39_i\, \system_clock_0/N_23\,
\system_clock_0/m_time[6]\, \system_clock_0/N_38_i\,
\system_clock_0/N_21\, \system_clock_0/m_time[4]\,
\system_clock_0/m_time[5]\, \system_clock_0/N_37_i\,
\system_clock_0/N_36_i\, \system_clock_0/m_time[2]\,
\system_clock_0/m_time[3]\, \system_clock_0/N_35_i\,
\system_clock_0/l_time_RNO_0[16]_net_1\,
\system_clock_0/l_time_RNIUEA34[14]_net_1\,
\system_clock_0/l_time_RNIQEBK3[13]_net_1\,
\system_clock_0/l_time_RNINFC53[12]_net_1\,
\system_clock_0/l_time_RNILHDM2[11]_net_1\,
\system_clock_0/l_time_RNIKKE72[10]_net_1\,
\system_clock_0/N_27\, \system_clock_0/N_26\,
\system_clock_0/N_24\, \system_clock_0/l_time_n7\,
\system_clock_0/un14_l_time\,
\system_clock_0/s_time_3[7]\, \system_clock_0/I_20\,
\system_clock_0/s_time_3[6]\, \system_clock_0/I_17\,
\system_clock_0/s_time_3[5]\, \system_clock_0/I_14\,
\system_clock_0/s_time_3[4]\, \system_clock_0/I_12\,
\system_clock_0/s_time_3[3]\, \system_clock_0/I_9\,
\system_clock_0/s_time_3[2]\, \system_clock_0/I_7\,
\system_clock_0/s_time_3[1]\, \system_clock_0/I_5\,
\system_clock_0/flag_net_1\, \system_clock_0/I_4\,
\system_clock_0/s_time[2]_net_1\, \system_clock_0/N_2\,
\system_clock_0/DWACT_FINC_E[2]\, \system_clock_0/N_3\,
\system_clock_0/DWACT_FINC_E[1]\, \system_clock_0/N_4\,
\system_clock_0/N_6\, \STX_PWR_pad/U0/NET1\,
\STX_PWR_pad/U0/NET2\, \V3_LINEAR_PWR_pad/U0/NET1\,
\V3_LINEAR_PWR_pad/U0/NET2\, \LED2_pad/U0/NET1\,
\LED2_pad/U0/NET2\, \LDO_FRONTEND_PWR_pad/U0/NET1\,
\LDO_FRONTEND_PWR_pad/U0/NET2\, \PR_OP_PWR_pad/U0/NET1\,
\PR_OP_PWR_pad/U0/NET2\, \BEACON_PWR_pad/U0/NET1\,
\BEACON_PWR_pad/U0/NET2\, \LED1_pad/U0/NET1\,
\LED1_pad/U0/NET2\, \CUTTER_EN_pad/U0/NET1\,
\CUTTER_EN_pad/U0/NET2\, \VCC\, \CLK_pad/U0/NET1\, \GND\,
AFLSDF_VCC, AFLSDF_GND : std_logic;
signal GND_power_net1 : std_logic;
signal VCC_power_net1 : std_logic;
begin
AFLSDF_GND <= GND_power_net1;
\GND\ <= GND_power_net1;
\VCC\ <= VCC_power_net1;
AFLSDF_VCC <= VCC_power_net1;
\system_clock_0/flag\ : DFN1
port map(D => \system_clock_0/un14_l_time\, CLK =>
CLKINT_0_Y, Q => \system_clock_0/flag_net_1\);
\system_clock_0/l_time_RNO[2]\ : XOR2
port map(A => \system_clock_0/m_time[1]\, B =>
\system_clock_0/m_time[2]\, Y => \system_clock_0/N_35_i\);
\system_clock_0/l_time[3]\ : DFN0
port map(D => \system_clock_0/N_36_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[3]\);
\system_clock_0/l_time_RNINQEP1[9]\ : NOR3C
port map(A => \system_clock_0/m_time[9]\, B =>
\system_clock_0/m_time[10]\, C =>
\system_clock_0/l_m6_0_a2_4\, Y =>
\system_clock_0/l_m6_0_a2_6\);
\system_clock_0/l_time_RNIKKE72[10]\ : OR2A
port map(A => \system_clock_0/m_time[10]\, B =>
\system_clock_0/N_27\, Y =>
\system_clock_0/l_time_RNIKKE72[10]_net_1\);
\system_clock_0/l_time_RNIFSK51[6]\ : OR2A
port map(A => \system_clock_0/m_time[6]\, B =>
\system_clock_0/N_23\, Y => \system_clock_0/N_24\);
\system_clock_0/l_time_RNIQVBV[5]\ : OR3B
port map(A => \system_clock_0/m_time[4]\, B =>
\system_clock_0/m_time[5]\, C => \system_clock_0/N_21\, Y
=> \system_clock_0/N_23\);
CLKINT_0 : CLKINT
port map(A => CLK_c, Y => CLKINT_0_Y);
\system_clock_0/l_time_RNO[3]\ : AX1C
port map(A => \system_clock_0/m_time[2]\, B =>
\system_clock_0/m_time[1]\, C =>
\system_clock_0/m_time[3]\, Y => \system_clock_0/N_36_i\);
\system_clock_0/un1_s_time_I_18\ : AND3
port map(A => \system_clock_0/s_time[3]_net_1\, B =>
\system_clock_0/s_time[4]_net_1\, C => LED2_c, Y =>
\system_clock_0/DWACT_FINC_E[2]\);
\BEACON_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\BEACON_PWR_pad/U0/NET1\, EOUT =>
\BEACON_PWR_pad/U0/NET2\);
\system_clock_0/un1_s_time_I_9\ : XOR2
port map(A => \system_clock_0/N_6\, B =>
\system_clock_0/s_time[3]_net_1\, Y =>
\system_clock_0/I_9\);
\system_clock_0/un1_s_time_I_14\ : XOR2
port map(A => \system_clock_0/N_4\, B => LED2_c, Y =>
\system_clock_0/I_14\);
\system_clock_0/l_time_RNO[11]\ : INV
port map(A => \system_clock_0/m_time[11]\, Y =>
\system_clock_0/m_time_i[11]\);
\system_clock_0/un1_s_time_I_8\ : AND3
port map(A => \system_clock_0/s_time[0]_net_1\, B =>
\system_clock_0/s_time[1]_net_1\, C =>
\system_clock_0/s_time[2]_net_1\, Y =>
\system_clock_0/N_6\);
\system_clock_0/l_time_RNIVU641[16]\ : NOR3C
port map(A => \system_clock_0/m_time[12]\, B =>
\system_clock_0/m_time[16]\, C =>
\system_clock_0/m_time[8]\, Y =>
\system_clock_0/l_m6_0_a2_4\);
\system_clock_0/l_time[9]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[9]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/N_26\, Q =>
\system_clock_0/m_time[9]\);
\system_clock_0/s_time_RNO[5]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_14\,
Y => \system_clock_0/s_time_3[5]\);
\system_clock_0/l_time_RNO[9]\ : INV
port map(A => \system_clock_0/m_time[9]\, Y =>
\system_clock_0/m_time_i[9]\);
\system_clock_0/l_time[7]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[7]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/N_24\, Q =>
\system_clock_0/m_time[7]\);
\system_clock_0/l_time[5]\ : DFN0
port map(D => \system_clock_0/N_38_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[5]\);
\V3_LINEAR_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\V3_LINEAR_PWR_pad/U0/NET1\, EOUT =>
\V3_LINEAR_PWR_pad/U0/NET2\);
\system_clock_0/l_time_RNO[12]\ : INV
port map(A => \system_clock_0/m_time[12]\, Y =>
\system_clock_0/m_time_i[12]\);
\system_clock_0/un1_s_time_I_5\ : XOR2
port map(A => \system_clock_0/s_time[0]_net_1\, B =>
\system_clock_0/s_time[1]_net_1\, Y =>
\system_clock_0/I_5\);
\system_clock_0/s_time[1]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[1]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[1]_net_1\);
\system_clock_0/l_time[12]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[12]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNILHDM2[11]_net_1\, Q =>
\system_clock_0/m_time[12]\);
\system_clock_0/l_time_RNO[5]\ : AX1
port map(A => \system_clock_0/N_21\, B =>
\system_clock_0/m_time[4]\, C =>
\system_clock_0/m_time[5]\, Y => \system_clock_0/N_38_i\);
\system_clock_0/s_time[3]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[3]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[3]_net_1\);
\system_clock_0/l_time_RNI9I815[7]\ : NOR2A
port map(A => \system_clock_0/l_m6_0_a2_7\, B =>
\system_clock_0/N_25\, Y => \system_clock_0/l_N_13_mux\);
\system_clock_0/l_time_RNI91UT[14]\ : NOR2B
port map(A => \system_clock_0/m_time[15]\, B =>
\system_clock_0/m_time[14]\, Y =>
\system_clock_0/l_m6_0_a2_1\);
\system_clock_0/l_time[4]\ : DFN0
port map(D => \system_clock_0/N_37_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[4]\);
\system_clock_0/un1_s_time_I_20\ : XOR2
port map(A => \system_clock_0/N_2\, B => LED1_c, Y =>
\system_clock_0/I_20\);
\V3_LINEAR_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \V3_LINEAR_PWR_pad/U0/NET1\, E =>
\V3_LINEAR_PWR_pad/U0/NET2\, PAD => V3_LINEAR_PWR);
\system_clock_0/s_time_RNIF0T8[0]\ : NOR2B
port map(A => \system_clock_0/s_time[3]_net_1\, B =>
\system_clock_0/s_time[0]_net_1\, Y =>
\system_clock_0/un14_flag_2\);
\LED2_pad/U0/U1\ : IOTRI_OB_EB
port map(D => LED2_c, E => \VCC\, DOUT =>
\LED2_pad/U0/NET1\, EOUT => \LED2_pad/U0/NET2\);
\CUTTER_EN_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\CUTTER_EN_pad/U0/NET1\, EOUT => \CUTTER_EN_pad/U0/NET2\);
\system_clock_0/l_time_RNIKOFO1[9]\ : OR2A
port map(A => \system_clock_0/m_time[9]\, B =>
\system_clock_0/N_26\, Y => \system_clock_0/N_27\);
\system_clock_0/l_time_RNIJ9QI[3]\ : OR3C
port map(A => \system_clock_0/m_time[2]\, B =>
\system_clock_0/m_time[1]\, C =>
\system_clock_0/m_time[3]\, Y => \system_clock_0/N_21\);
\system_clock_0/l_time_RNI4STT[11]\ : NOR2B
port map(A => \system_clock_0/m_time[13]\, B =>
\system_clock_0/m_time[11]\, Y =>
\system_clock_0/l_m6_0_a2_2\);
\system_clock_0/un1_s_time_I_4\ : INV
port map(A => \system_clock_0/s_time[0]_net_1\, Y =>
\system_clock_0/I_4\);
\CUTTER_EN_pad/U0/U0\ : IOPAD_TRI
port map(D => \CUTTER_EN_pad/U0/NET1\, E =>
\CUTTER_EN_pad/U0/NET2\, PAD => CUTTER_EN);
\LDO_FRONTEND_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \LDO_FRONTEND_PWR_pad/U0/NET1\, E =>
\LDO_FRONTEND_PWR_pad/U0/NET2\, PAD => LDO_FRONTEND_PWR);
\system_clock_0/un1_s_time_I_10\ : AND3
port map(A => \system_clock_0/s_time[0]_net_1\, B =>
\system_clock_0/s_time[1]_net_1\, C =>
\system_clock_0/s_time[2]_net_1\, Y =>
\system_clock_0/DWACT_FINC_E[0]\);
\system_clock_0/l_time_RNIQEBK3[13]\ : OR2A
port map(A => \system_clock_0/m_time[13]\, B =>
\system_clock_0/l_time_RNINFC53[12]_net_1\, Y =>
\system_clock_0/l_time_RNIQEBK3[13]_net_1\);
\system_clock_0/s_time_RNIL6T8[4]\ : NOR2B
port map(A => LED2_c, B => \system_clock_0/s_time[4]_net_1\,
Y => \system_clock_0/un14_flag_1\);
\LED1_pad/U0/U0\ : IOPAD_TRI
port map(D => \LED1_pad/U0/NET1\, E => \LED1_pad/U0/NET2\,
PAD => LED1);
\system_clock_0/l_time[10]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[10]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/N_27\, Q =>
\system_clock_0/m_time[10]\);
\system_clock_0/un1_s_time_I_7\ : AX1C
port map(A => \system_clock_0/s_time[1]_net_1\, B =>
\system_clock_0/s_time[0]_net_1\, C =>
\system_clock_0/s_time[2]_net_1\, Y =>
\system_clock_0/I_7\);
\system_clock_0/s_time[7]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[7]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q => LED1_c);
\system_clock_0/s_time[5]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[5]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q => LED2_c);
\BEACON_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \BEACON_PWR_pad/U0/NET1\, E =>
\BEACON_PWR_pad/U0/NET2\, PAD => BEACON_PWR);
\system_clock_0/l_time[2]\ : DFN0
port map(D => \system_clock_0/N_35_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[2]\);
\system_clock_0/l_time[13]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[13]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNINFC53[12]_net_1\, Q =>
\system_clock_0/m_time[13]\);
\CLK_pad/U0/U1\ : IOIN_IB
port map(YIN => \CLK_pad/U0/NET1\, Y => CLK_c);
\system_clock_0/l_time_RNIUEA34[14]\ : OR2A
port map(A => \system_clock_0/m_time[14]\, B =>
\system_clock_0/l_time_RNIQEBK3[13]_net_1\, Y =>
\system_clock_0/l_time_RNIUEA34[14]_net_1\);
\system_clock_0/l_time[8]\ : DFN0
port map(D => \system_clock_0/l_time_n7\, CLK => CLKINT_0_Y,
Q => \system_clock_0/m_time[8]\);
\system_clock_0/l_time[17]\ : DFN0E1
port map(D => \system_clock_0/m_time_i[17]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/l_N_13_mux\, Q =>
\system_clock_0/m_time[17]\);
\LED1_pad/U0/U1\ : IOTRI_OB_EB
port map(D => LED1_c, E => \VCC\, DOUT =>
\LED1_pad/U0/NET1\, EOUT => \LED1_pad/U0/NET2\);
\system_clock_0/s_time_RNO[1]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_5\,
Y => \system_clock_0/s_time_3[1]\);
\system_clock_0/l_time_RNO[15]\ : INV
port map(A => \system_clock_0/m_time[15]\, Y =>
\system_clock_0/m_time_i[15]\);
\system_clock_0/s_time_RNO[6]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_17\,
Y => \system_clock_0/s_time_3[6]\);
\system_clock_0/s_time_RNO[4]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_12\,
Y => \system_clock_0/s_time_3[4]\);
\system_clock_0/s_time[4]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[4]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[4]_net_1\);
\system_clock_0/un1_s_time_I_12\ : AX1C
port map(A => \system_clock_0/s_time[3]_net_1\, B =>
\system_clock_0/DWACT_FINC_E[0]\, C =>
\system_clock_0/s_time[4]_net_1\, Y =>
\system_clock_0/I_12\);
\PR_OP_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\PR_OP_PWR_pad/U0/NET1\, EOUT => \PR_OP_PWR_pad/U0/NET2\);
\system_clock_0/s_time_RNO[7]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_20\,
Y => \system_clock_0/s_time_3[7]\);
\system_clock_0/l_time_RNO[8]\ : XNOR2
port map(A => \system_clock_0/m_time[8]\, B =>
\system_clock_0/N_25\, Y => \system_clock_0/l_time_n7\);
\system_clock_0/l_time[6]\ : DFN0
port map(D => \system_clock_0/N_39_i\, CLK => CLKINT_0_Y, Q
=> \system_clock_0/m_time[6]\);
\system_clock_0/l_time[11]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[11]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNIKKE72[10]_net_1\, Q =>
\system_clock_0/m_time[11]\);
\LDO_FRONTEND_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\LDO_FRONTEND_PWR_pad/U0/NET1\, EOUT =>
\LDO_FRONTEND_PWR_pad/U0/NET2\);
\system_clock_0/l_time_RNI5QTB1[7]\ : OR2A
port map(A => \system_clock_0/m_time[7]\, B =>
\system_clock_0/N_24\, Y => \system_clock_0/N_25\);
\PR_OP_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \PR_OP_PWR_pad/U0/NET1\, E =>
\PR_OP_PWR_pad/U0/NET2\, PAD => PR_OP_PWR);
\system_clock_0/l_time_RNO[1]\ : INV
port map(A => \system_clock_0/m_time[1]\, Y =>
\system_clock_0/m_time_i[1]\);
\system_clock_0/l_time[15]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[15]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNIUEA34[14]_net_1\, Q =>
\system_clock_0/m_time[15]\);
\system_clock_0/l_time_RNO[6]\ : XNOR2
port map(A => \system_clock_0/N_23\, B =>
\system_clock_0/m_time[6]\, Y => \system_clock_0/N_39_i\);
\system_clock_0/l_time_RNO[4]\ : XNOR2
port map(A => \system_clock_0/N_21\, B =>
\system_clock_0/m_time[4]\, Y => \system_clock_0/N_37_i\);
\CLK_pad/U0/U0\ : IOPAD_IN
port map(PAD => CLK, Y => \CLK_pad/U0/NET1\);
\system_clock_0/l_time_RNO[10]\ : INV
port map(A => \system_clock_0/m_time[10]\, Y =>
\system_clock_0/m_time_i[10]\);
\system_clock_0/un1_s_time_I_16\ : AND3
port map(A => \system_clock_0/DWACT_FINC_E[0]\, B =>
\system_clock_0/DWACT_FINC_E[1]\, C => LED2_c, Y =>
\system_clock_0/N_3\);
\system_clock_0/l_time_RNO[7]\ : INV
port map(A => \system_clock_0/m_time[7]\, Y =>
\system_clock_0/m_time_i[7]\);
\system_clock_0/l_time_RNO[17]\ : INV
port map(A => \system_clock_0/m_time[17]\, Y =>
\system_clock_0/m_time_i[17]\);
\system_clock_0/l_time[14]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[14]\, CLK =>
CLKINT_0_Y, E =>
\system_clock_0/l_time_RNIQEBK3[13]_net_1\, Q =>
\system_clock_0/m_time[14]\);
\system_clock_0/flag_RNO\ : NOR2B
port map(A => \system_clock_0/l_N_13_mux\, B =>
\system_clock_0/m_time[17]\, Y =>
\system_clock_0/un14_l_time\);
\system_clock_0/s_time[2]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[2]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[2]_net_1\);
\system_clock_0/l_time_RNO[13]\ : INV
port map(A => \system_clock_0/m_time[13]\, Y =>
\system_clock_0/m_time_i[13]\);
\system_clock_0/l_time[16]\ : DFN0E0
port map(D => \system_clock_0/m_time_i[16]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/l_time_RNO_0[16]_net_1\,
Q => \system_clock_0/m_time[16]\);
\LED2_pad/U0/U0\ : IOPAD_TRI
port map(D => \LED2_pad/U0/NET1\, E => \LED2_pad/U0/NET2\,
PAD => LED2);
\system_clock_0/l_time_RNILHDM2[11]\ : OR2A
port map(A => \system_clock_0/m_time[11]\, B =>
\system_clock_0/l_time_RNIKKE72[10]_net_1\, Y =>
\system_clock_0/l_time_RNILHDM2[11]_net_1\);
\system_clock_0/l_time_RNO[14]\ : INV
port map(A => \system_clock_0/m_time[14]\, Y =>
\system_clock_0/m_time_i[14]\);
\system_clock_0/l_time_RNI4OAL3[9]\ : NOR3C
port map(A => \system_clock_0/l_m6_0_a2_2\, B =>
\system_clock_0/l_m6_0_a2_1\, C =>
\system_clock_0/l_m6_0_a2_6\, Y =>
\system_clock_0/l_m6_0_a2_7\);
\system_clock_0/un1_s_time_I_17\ : XOR2
port map(A => \system_clock_0/N_3\, B =>
\system_clock_0/s_time[6]_net_1\, Y =>
\system_clock_0/I_17\);
\system_clock_0/l_time_RNINFC53[12]\ : OR2A
port map(A => \system_clock_0/m_time[12]\, B =>
\system_clock_0/l_time_RNILHDM2[11]_net_1\, Y =>
\system_clock_0/l_time_RNINFC53[12]_net_1\);
\system_clock_0/un1_s_time_I_13\ : AND3
port map(A => \system_clock_0/DWACT_FINC_E[0]\, B =>
\system_clock_0/s_time[3]_net_1\, C =>
\system_clock_0/s_time[4]_net_1\, Y =>
\system_clock_0/N_4\);
\system_clock_0/s_time_RNIEHQH[6]\ : NOR3C
port map(A => \system_clock_0/s_time[6]_net_1\, B => LED1_c,
C => \system_clock_0/un14_flag_1\, Y =>
\system_clock_0/un14_flag_3\);
\system_clock_0/s_time[0]\ : DFN0E1
port map(D => \system_clock_0/I_4\, CLK => CLKINT_0_Y, E
=> \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[0]_net_1\);
\system_clock_0/l_time_RNO[16]\ : INV
port map(A => \system_clock_0/m_time[16]\, Y =>
\system_clock_0/m_time_i[16]\);
\system_clock_0/un1_s_time_I_15\ : AND2
port map(A => \system_clock_0/s_time[3]_net_1\, B =>
\system_clock_0/s_time[4]_net_1\, Y =>
\system_clock_0/DWACT_FINC_E[1]\);
\system_clock_0/s_time[6]\ : DFN0E1
port map(D => \system_clock_0/s_time_3[6]\, CLK =>
CLKINT_0_Y, E => \system_clock_0/flag_net_1\, Q =>
\system_clock_0/s_time[6]_net_1\);
\system_clock_0/l_time_RNISO6I1[8]\ : OR2A
port map(A => \system_clock_0/m_time[8]\, B =>
\system_clock_0/N_25\, Y => \system_clock_0/N_26\);
\system_clock_0/s_time_RNO[2]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_7\,
Y => \system_clock_0/s_time_3[2]\);
\system_clock_0/un1_s_time_I_19\ : AND3
port map(A => \system_clock_0/DWACT_FINC_E[0]\, B =>
\system_clock_0/DWACT_FINC_E[2]\, C =>
\system_clock_0/s_time[6]_net_1\, Y =>
\system_clock_0/N_2\);
\STX_PWR_pad/U0/U1\ : IOTRI_OB_EB
port map(D => \GND\, E => \VCC\, DOUT =>
\STX_PWR_pad/U0/NET1\, EOUT => \STX_PWR_pad/U0/NET2\);
\system_clock_0/l_time[1]\ : DFN0
port map(D => \system_clock_0/m_time_i[1]\, CLK =>
CLKINT_0_Y, Q => \system_clock_0/m_time[1]\);
\system_clock_0/s_time_RNO[3]\ : AOI1B
port map(A => \system_clock_0/un14_flag_3\, B =>
\system_clock_0/un14_flag_2\, C => \system_clock_0/I_9\,
Y => \system_clock_0/s_time_3[3]\);
\STX_PWR_pad/U0/U0\ : IOPAD_TRI
port map(D => \STX_PWR_pad/U0/NET1\, E =>
\STX_PWR_pad/U0/NET2\, PAD => STX_PWR);
\system_clock_0/l_time_RNO_0[16]\ : OR2A
port map(A => \system_clock_0/m_time[15]\, B =>
\system_clock_0/l_time_RNIUEA34[14]_net_1\, Y =>
\system_clock_0/l_time_RNO_0[16]_net_1\);
GND_power_inst1 : GND
port map( Y => GND_power_net1);
VCC_power_inst1 : VCC
port map( Y => VCC_power_net1);
end DEF_ARCH;
|
mit
|
0dee39c77ec35c7fcc87fab58d1577d3
| 0.507637 | 2.542508 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_counter3.vhd
| 2 | 4,437 |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter3 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END lpm_counter3;
ARCHITECTURE SYN OF lpm_counter3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(8 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 286,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 9
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "286"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "286"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
1e3e4c284a416f154ff237fa6a4776ea
| 0.651566 | 3.685216 | false | false | false | false |
blutsvente/MIX
|
test/results/mde_tests/conn_nr_vhdl/inst_eb_e-rtl-a.vhd
| 1 | 4,268 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-rtl-a.vhd,v 1.1 2004/04/06 10:49:59 wig Exp $
-- $Date: 2004/04/06 10:49:59 $
-- $Log: inst_eb_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:49:59 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eb_e
--
architecture rtl of inst_eb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eba_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eba_e
mbist_aci_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_vcd_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_eba_e
);
end component;
-- ---------
component inst_ebb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ebb_e
mbist_sum_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
req_select_o : out std_ulogic_vector(5 downto 0);
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_ebb_e
);
end component;
-- ---------
component inst_ebc_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ebc_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ebc_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
nreset <= p_mix_nreset_gi; -- __I_I_BIT_PORT
nreset_s <= p_mix_nreset_s_gi; -- __I_I_BIT_PORT
p_mix_tmi_sbist_fail_12_10_go(2 downto 0) <= tmi_sbist_fail(12 downto 10); -- __I_O_SLICE_PORT
p_mix_v_select_5_0_go <= v_select; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eba
inst_eba: inst_eba_e
port map (
mbist_aci_fail_o => tmi_sbist_fail(10),
mbist_vcd_fail_o => tmi_sbist_fail(11),
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_eba
-- Generated Instance Port Map for inst_ebb
inst_ebb: inst_ebb_e
port map (
mbist_sum_fail_o => tmi_sbist_fail(12),
req_select_o => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_ebb
-- Generated Instance Port Map for inst_ebc
inst_ebc: inst_ebc_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_ebc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3b295f1bad6d921b65fe14382763f559
| 0.631443 | 3.110787 | false | false | false | false |
ErikAndren/BCDTest
|
BCDTest.vhd
| 1 | 1,227 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.BcdPack.all;
entity BCDTest is
generic (
Displays : positive := 8
);
port (
Clk : in bit1;
--
Segments : out word(8-1 downto 0);
Display : out word(Displays-1 downto 0)
);
end entity;
architecture rtl of BCDTest is
constant Freq : positive := 50000000;
--
signal ClkCnt_N, ClkCnt_D : word(bits(Freq)-1 downto 0);
--
signal CntVal_N, CntVal_D : word(27-1 downto 0);
signal CntValBcd : word(Displays*4-1 downto 0);
signal CurSeg : word(4-1 downto 0);
begin
ClkCntAsync : process (ClkCnt_D, CntVal_D)
begin
CntVal_N <= CntVal_D;
ClkCnt_N <= ClkCnt_D + 1;
if ClkCnt_D = Freq then
ClkCnt_N <= (others => '0');
CntVal_N <= CntVal_D + 1;
end if;
end process;
ClkCntSync : process (Clk)
begin
if rising_edge(Clk) then
ClkCnt_D <= ClkCnt_N;
CntVal_D <= CntVal_N;
end if;
end process;
--
CntValBcd <= ToBcd(CntVal_D, 8);
CurSeg <= ExtractSlice(CntValBcd, 4, conv_integer(ClkCnt_D(15 downto 13)));
--
Segments <= BcdArray(conv_integer(CurSeg));
Display <= not SHL(xt0(Displays-1) & '1', ClkCnt_D(15 downto 13));
end architecture rtl;
|
gpl-2.0
|
d73a1cd32158907bd32d74d3b13e3a29
| 0.659332 | 2.684902 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/fifo_generator_v13_0/simulation/fifo_generator_vhdl_beh.vhd
| 15 | 465,879 |
-------------------------------------------------------------------------------
--
-- FIFO Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Filename: fifo_generator_vhdl_beh.vhd
--
-- Author : Xilinx
--
-------------------------------------------------------------------------------
-- Structure:
--
-- fifo_generator_vhdl_beh.vhd
-- |
-- +-fifo_generator_v13_0_1_conv
-- |
-- +-fifo_generator_v13_0_1_bhv_as
-- |
-- +-fifo_generator_v13_0_1_bhv_ss
-- |
-- +-fifo_generator_v13_0_1_bhv_preload0
--
-------------------------------------------------------------------------------
-- Description:
--
-- The VHDL behavioral model for the FIFO Generator.
--
-- The behavioral model has three parts:
-- - The behavioral model for independent clocks FIFOs (_as)
-- - The behavioral model for common clock FIFOs (_ss)
-- - The "preload logic" block which implements First-word Fall-through
--
-------------------------------------------------------------------------------
--#############################################################################
--#############################################################################
-- Independent Clocks FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- Independent Clocks Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_bhv_as IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2
);
PORT(
---------------------------------------------------------------------------
-- Input and Output Declarations
---------------------------------------------------------------------------
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VALID : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_bhv_as;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_as IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH - 1;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION div_roundup
-- Returns data_value / divisor, with the result rounded-up (if fractional)
-------------------------------------------------------------------------------
FUNCTION divroundup (
data_value : integer;
divisor : integer)
RETURN integer IS
VARIABLE div : integer;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- Derived Constants
-----------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_FIFO_RD_DEPTH : integer
:= actual_fifo_depth(C_RD_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_SMALLER_DATA_WIDTH : integer
:= get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
-- "Extra Words" is the number of write words which fit into the two
-- first-word fall-through output register stages (if using FWFT).
-- For ratios of 1:4 and 1:8, the fractional result is rounded up to 1.
-- This value is used to calculate the adjusted PROG_FULL threshold
-- value for FWFT.
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
CONSTANT EXTRA_WORDS : integer := divroundup(2 * C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD);
-- "Extra words dc" is used for calculating the adjusted WR_DATA_COUNT
-- value for the core when using FWFT.
-- extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
-- -----------------|------------------|-----------------|---------------
-- 1 | 8 | C_RD_PNTR_WIDTH | 2
-- 1 | 4 | C_RD_PNTR_WIDTH | 2
-- 1 | 2 | C_RD_PNTR_WIDTH | 2
-- 1 | 1 | C_WR_PNTR_WIDTH | 2
-- 2 | 1 | C_WR_PNTR_WIDTH | 4
-- 4 | 1 | C_WR_PNTR_WIDTH | 8
-- 8 | 1 | C_WR_PNTR_WIDTH | 16
CONSTANT EXTRA_WORDS_DC : integer
:= if_then_else ((C_DEPTH_RATIO_WR = 1),2,
(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT C_PE_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PE_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL); --NO FWFT
CONSTANT C_PE_THR_ASSERT_VAL_I : integer := C_PE_THR_ASSERT_ADJUSTED;
CONSTANT C_PE_THR_NEGATE_VAL_I : integer := C_PE_THR_NEGATE_ADJUSTED;
CONSTANT C_PF_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PF_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); --NO FWFT
-- NO_ERR_INJECTION will be 1 if ECC is OFF or ECC is ON but no error
-- injection is selected.
CONSTANT NO_ERR_INJECTION : integer
:= if_then_else(C_USE_ECC = 0,1,
if_then_else(C_ERROR_INJECTION_TYPE = 0,1,0));
-- SBIT_ERR_INJECTION will be 1 if ECC is ON and single bit error injection
-- is selected.
CONSTANT SBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 1),1,0);
-- DBIT_ERR_INJECTION will be 1 if ECC is ON and double bit error injection
-- is selected.
CONSTANT DBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 2),1,0);
-- BOTH_ERR_INJECTION will be 1 if ECC is ON and both single and double bit
-- error injection are selected.
CONSTANT BOTH_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE = 3),1,0);
CONSTANT C_DATA_WIDTH : integer := if_then_else(NO_ERR_INJECTION = 1, C_DIN_WIDTH, C_DIN_WIDTH+2);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
TYPE wr_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
TYPE rd_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pntr_q : wr_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL rd_pntr_q : rd_sync_array := (OTHERS => (OTHERS => '0'));
-------------------------------------------------------------------------------
-- Signals Declaration
-------------------------------------------------------------------------------
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_rst_i : std_logic := '0';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL wr_rst_d1 : std_logic := '0';
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL valid_out : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL width_gt1 : std_logic := '0';
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL empty_int : boolean := TRUE;
SIGNAL empty_comb : std_logic := '1';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL empty_comb_d1 : std_logic := '1';
SIGNAL almost_empty_int : boolean := TRUE;
SIGNAL full_int : boolean := FALSE;
SIGNAL full_comb : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL ram_wr_en : std_logic := '0';
SIGNAL almost_full_int : boolean := FALSE;
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
SIGNAL diff_pntr_wr : integer := 0;
SIGNAL diff_pntr_rd : integer := 0;
SIGNAL pf_input_thr_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL pf_input_thr_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------------
-- Asynchronous FIFO
-------------------------------------------------------------------------------
gnll_afifo: IF (C_FIFO_TYPE /= 3) GENERATE
wr_pntr <= conv_std_logic_vector(wr_point,C_WR_PNTR_WIDTH);
rd_pntr <= conv_std_logic_vector(rd_point,C_RD_PNTR_WIDTH);
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
-------------------------------------------------------------------------------
-- calculate number of words in wr and rd domain according to the deepest port
--
-- These steps circumvent the linked-list data structure and keep track of
-- wr_point and rd_point pointers much like the core itself does. The behavioral
-- model uses these to calculate WR_DATA_COUNT and RD_DATA_COUNT. This was done
-- because the sizeof() function always returns the exact number of words in
-- the linked list, and can not account for delays when crossing clock domains.
-------------------------------------------------------------------------------
adj_wr_point <= wr_point * C_DEPTH_RATIO_RD;
adj_rd_point <= rd_point * C_DEPTH_RATIO_WR;
adj_wr_point_d1<= wr_point_d1 * C_DEPTH_RATIO_RD;
adj_rd_point_d1<= rd_point_d1 * C_DEPTH_RATIO_WR;
width_gt1 <= '1' WHEN (C_DIN_WIDTH = 2) ELSE '0';
PROCESS (adj_wr_point, adj_wr_point_d1, adj_rd_point, adj_rd_point_d1)
BEGIN
IF (adj_wr_point >= adj_rd_point_d1) THEN
num_wr_words <= adj_wr_point - adj_rd_point_d1;
ELSE
num_wr_words <= C_WR_DEPTH*C_DEPTH_RATIO_RD + adj_wr_point - adj_rd_point_d1;
END IF;
IF (adj_wr_point_d1 >= adj_rd_point) THEN
num_rd_words <= adj_wr_point_d1 - adj_rd_point;
ELSE
num_rd_words <= C_RD_DEPTH*C_DEPTH_RATIO_WR + adj_wr_point_d1 - adj_rd_point;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_VALID_LOW
-------------------------------------------------------------------------------
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_out;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_out;
END GENERATE gnvh;
-------------------------------------------------------------------------------
--Calculate UNDERFLOW based on C_UNDERFLOW_LOW
-------------------------------------------------------------------------------
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
-------------------------------------------------------------------------------
--Assign PROG_FULL and PROG_EMPTY
-------------------------------------------------------------------------------
PROG_FULL <= prog_full_reg;
PROG_EMPTY <= prog_empty_reg;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1) GENERATE
grdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rdc_fwft_ext_as(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE grdc_fwft_ext;
gnrdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE gnrdc_fwft_ext;
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1) GENERATE
gwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wdc_fwft_ext_as(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gwdc_fwft_ext;
gnwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gnwdc_fwft_ext;
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Write data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
wdc_fwft_ext: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
CONSTANT C_PNTR_WIDTH : integer
:= if_then_else ((C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH),
C_WR_PNTR_WIDTH, C_RD_PNTR_WIDTH);
SIGNAL adjusted_wr_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL adjusted_rd_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
CONSTANT EXTRA_WORDS : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(
if_then_else ((C_DEPTH_RATIO_WR=1),2
,(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD))
,C_PNTR_WIDTH+1);
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_data_count_i : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
BEGIN
-----------------------------------------------------------------------------
--Adjust write and read pointer to the deepest port width
-----------------------------------------------------------------------------
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH
gpadr: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adjusted_rd_pntr(C_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
END GENERATE gpadr;
--C_PNTR_WIDTH=C_RD_PNTR_WIDTH
gpadw: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adjusted_wr_pntr(C_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE gpadw;
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH=C_RD_PNTR_WIDTH
ngpad: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE ngpad;
-----------------------------------------------------------------------------
--Calculate words in write domain
-----------------------------------------------------------------------------
--Subtract the pointers to get the number of words in the RAM, *THEN* pad
--the result
diff_wr_rd_tmp <= adjusted_wr_pntr - adjusted_rd_pntr;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
pwdc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_i <= (OTHERS=>'0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_i <= diff_wr_rd + extra_words;
END IF;
END PROCESS pwdc;
gdc0: IF (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO 0);
END GENERATE gdc0;
gdc1: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gdc1;
END GENERATE wdc_fwft_ext;
-------------------------------------------------------------------------------
-- Read data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
rdc_fwft_ext: IF (C_HAS_RD_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL zero : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL one : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(1, C_RD_PNTR_WIDTH+1);
SIGNAL two : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(2, C_RD_PNTR_WIDTH+1);
SIGNAL adjusted_wr_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
BEGIN
----------------------------------------------------------------------------
-- If write depth is smaller than read depth, pad write pointer.
-- If write depth is bigger than read depth, trim write pointer.
----------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= WR_PNTR_RD;
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r
<= WR_PNTR_RD(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-----------------------------------------------------------------------------
-- This accounts for preload 0 by explicitly handling the preload states
-- which do not have both output stages filled. As a result, the rd_data_count
-- produced will always accurately reflect the number of READABLE words at
-- a given time.
-----------------------------------------------------------------------------
diff_wr_rd_tmp <= adjusted_wr_pntr_r - RD_PNTR;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
prdc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rdc_fwft_ext_as <= zero;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (stage2_valid = '0') THEN
rdc_fwft_ext_as <= zero;
ELSIF (stage2_valid = '1' AND stage1_valid = '0') THEN
rdc_fwft_ext_as <= one;
ELSE
rdc_fwft_ext_as <= diff_wr_rd + two;
END IF;
END IF;
END PROCESS prdc;
END GENERATE rdc_fwft_ext;
-------------------------------------------------------------------------------
-- Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
-------------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr_rd;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr_rd(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-------------------------------------------------------------------------------
-- Generate Empty
-------------------------------------------------------------------------------
-- ram_rd_en used to determine EMPTY should depend on the EMPTY.
ram_rd_en <= RD_EN AND (NOT empty_comb);
empty_int <= ((adj_wr_pntr_rd = rd_pntr) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Empty
-------------------------------------------------------------------------------
almost_empty_int <= ((adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+2),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Empty & Almost Empty
-- Generate read data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
empty_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_comb <= '1' AFTER C_TCQ;
empty_comb_d1 <= '1' AFTER C_TCQ;
ALMOST_EMPTY <= '1' AFTER C_TCQ;
rd_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_data_count_int <= ((adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO 0) -
rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
empty_comb_d1 <= empty_comb AFTER C_TCQ;
IF (empty_int) THEN
empty_comb <= '1' AFTER C_TCQ;
ELSE
empty_comb <= '0' AFTER C_TCQ;
END IF;
IF (empty_comb = '0') THEN
IF (almost_empty_int) THEN
ALMOST_EMPTY <= '1' AFTER C_TCQ;
ELSE
ALMOST_EMPTY <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Read pointer adjustment based on pointers width for FULL/ALMOST_FULL generation
-------------------------------------------------------------------------------
gfpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gfpad;
gftrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
<= rd_pntr_wr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gftrim;
-------------------------------------------------------------------------------
-- Generate Full
-------------------------------------------------------------------------------
-- ram_wr_en used to determine FULL should depend on the FULL.
ram_wr_en <= WR_EN AND (NOT full_comb);
full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+1),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Full
-------------------------------------------------------------------------------
almost_full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+3),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Full & Almost Full
-- Generate write data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
full_proc : PROCESS (WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_comb <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ALMOST_FULL <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (full_int) THEN
full_comb <= '1' AFTER C_TCQ;
ELSE
full_comb <= '0' AFTER C_TCQ;
END IF;
IF (RST_FULL_GEN = '1') THEN
ALMOST_FULL <= '0' AFTER C_TCQ;
ELSIF (full_comb = '0') THEN
IF (almost_full_int) THEN
ALMOST_FULL <= '1' AFTER C_TCQ;
ELSE
ALMOST_FULL <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS full_proc;
wdci_proc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_int <= ((wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO 0) -
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
END IF;
END PROCESS wdci_proc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
user_empty_fb_d1 <= USER_EMPTY_FB;
IF (user_empty_fb_d1 = '0' AND USER_EMPTY_FB = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_comb = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_comb = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_comb = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
gnrd_fwft: IF (C_PRELOAD_LATENCY > 0) GENERATE
rd_fwft_cnt <= X"2";
END GENERATE gnrd_fwft;
-------------------------------------------------------------------------------
-- Assign FULL, EMPTY, ALMOST_FULL and ALMOST_EMPTY
-------------------------------------------------------------------------------
FULL <= full_comb;
EMPTY <= empty_comb;
-------------------------------------------------------------------------------
-- Asynchronous FIFO using linked lists
-------------------------------------------------------------------------------
FIFO_PROC : PROCESS (WR_CLK, RD_CLK, rd_rst_i, wr_rst_i)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF wr_rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
rd_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
rd_pntr_q <= rd_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & rd_pntr_wr_d1;
-- Delay the write pointer before passing to RD_CLK domain to accommodate
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --WR_CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF rd_rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
wr_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
-- DRAM resets asynchronously
IF (C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- BRAM resets synchronously
IF (C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
wr_pntr_q <= wr_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & wr_pntr_rd1;
-- Delay the read pointer before passing to WR_CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (ram_rd_en = '1') THEN
IF empty_comb /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --RD_CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
-----------------------------------------------------------------------------
-- Programmable FULL flags
-----------------------------------------------------------------------------
proc_pf_input: PROCESS(PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT,PROG_FULL_THRESH_NEGATE)
BEGIN
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH - conv_integer(EXTRA_WORDS_DC);
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
END IF;
ELSE -- STD
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH;
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT;
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE;
END IF;
END IF;
END PROCESS proc_pf_input;
proc_wdc: PROCESS(WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
diff_pntr_wr <= 0;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (ram_wr_en = '0') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) after C_TCQ;
ELSIF (ram_wr_en = '1') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) + 1 after C_TCQ;
END IF;
END IF; -- WR_CLK
END PROCESS proc_wdc;
proc_pf: PROCESS(WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_reg <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_reg <= '0' after C_TCQ;
ELSIF (C_PROG_FULL_TYPE = 1) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 2) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < C_PF_THR_NEGATE_ADJUSTED) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 3) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 4) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < conv_integer(pf_input_thr_negate_val)) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
END IF; --C_PROG_FULL_TYPE
END IF; -- WR_CLK
END PROCESS proc_pf;
---------------------------------------------------------------------------
-- Programmable EMPTY Flags
---------------------------------------------------------------------------
proc_pe: PROCESS(RD_CLK, rd_rst_i)
VARIABLE pe_thr_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE pe_thr_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (rd_rst_i = '1') THEN
diff_pntr_rd <= 0;
prog_empty_reg <= '1';
pe_thr_assert_val := (OTHERS => '0');
pe_thr_negate_val := (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (ram_rd_en = '0') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) after C_TCQ;
ELSIF (ram_rd_en = '1') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) - 1 after C_TCQ;
ELSE
diff_pntr_rd <= diff_pntr_rd after C_TCQ;
END IF;
IF (C_PROG_EMPTY_TYPE = 1) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 2) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > C_PE_THR_NEGATE_VAL_I) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 3) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= pe_thr_assert_val) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 4) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT - "10";
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT;
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= conv_integer(pe_thr_assert_val)) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > conv_integer(pe_thr_negate_val)) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
END IF; --C_PROG_EMPTY_TYPE
END IF; -- RD_CLK
END PROCESS proc_pe;
-----------------------------------------------------------------------------
-- overflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
g7s_ovflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
overflow_i <= full_comb AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g7s_ovflw;
g8s_ovflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
--overflow_i <= (wr_rst_i OR full_comb) AND WR_EN after C_TCQ;
overflow_i <= (full_comb) AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g8s_ovflw;
END GENERATE govflw;
-----------------------------------------------------------------------------
-- underflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
g7s_unflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
underflow_i <= empty_comb and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g7s_unflw;
g8s_unflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
--underflow_i <= (rd_rst_i OR empty_comb) and RD_EN after C_TCQ;
underflow_i <= (empty_comb) and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g8s_unflw;
END GENERATE gunflw;
-----------------------------------------------------------------------------
-- wr_ack_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF wr_rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
----------------------------------------------------------------------------
-- valid_i generation: Asynchronous FIFO
----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_comb /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------
-- Delay valid_d1
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1
-----------------------------------------------------------------
gv0_as: IF (C_USE_EMBEDDED_REG>0
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_d1 <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_d1 <= valid_i after C_TCQ;
END IF;
END PROCESS;
END GENERATE gv0_as;
gv1_as: IF NOT (C_USE_EMBEDDED_REG>0
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
valid_d1 <= valid_i;
END GENERATE gv1_as;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Use delayed Valid AND DOUT if we have a LATENCY=2 configurations
-- ( if C_MEMORY_TYPE=0 or 1, C_PRELOAD_REGS=0, C_USE_EMBEDDED_REG=1 )
--Otherwise, connect the valid and DOUT values up directly, with no
--additional latency.
-----------------------------------------------------------------------------
gv0: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)AND C_EN_SAFETY_CKT =0) GENERATE
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF (rd_rst_i = '1') THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv0_safety: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT =1) GENERATE
SIGNAL dout_rst_val_d1 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_rst_val_d2 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS ( RD_CLK )
BEGIN
rst_delayed_sft1 <= rd_rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
PROCESS (rst_delayed_sft4 ,rd_rst_i, RD_CLK )
BEGIN
IF (rst_delayed_sft4 = '1' OR rd_rst_i = '1') THEN
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_delayed_sft4 , RD_CLK )
BEGIN
IF (rst_delayed_sft4 = '1' ) THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
--ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0_safety;
gv1_nsafety: IF (NOT (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) ) GENERATE
gv2a: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_i;
END GENERATE gv2a;
DOUT <= dout_i;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END GENERATE gv1_nsafety;
END GENERATE gnll_afifo;
-------------------------------------------------------------------------------
-- Low Latency Asynchronous FIFO
-------------------------------------------------------------------------------
gll_afifo: IF (C_FIFO_TYPE = 3) GENERATE
TYPE mem_array IS ARRAY (0 TO C_WR_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL wr_pntr_ll_afifo : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo_q : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL ll_afifo_full : std_logic := '0';
SIGNAL ll_afifo_empty : std_logic := '1';
SIGNAL wr_pntr_eq_rd_pntr : std_logic := '0';
SIGNAL wr_pntr_eq_rd_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus2 : std_logic := '0';
BEGIN
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
write_allow <= WR_EN AND (NOT ll_afifo_full);
read_allow <= RD_EN AND (NOT ll_afifo_empty);
wrptr_proc : PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_pntr_ll_afifo <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
wr_pntr_ll_afifo <= wr_pntr_ll_afifo + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
-------------------------------------------------------------------------------
-- Fill the Memory
-------------------------------------------------------------------------------
wr_mem : PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr_ll_afifo)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
rdptr_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_pntr_ll_afifo_q <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_pntr_ll_afifo_q <= rd_pntr_ll_afifo AFTER C_TCQ;
END IF;
END PROCESS rdptr_proc;
rd_pntr_ll_afifo <= rd_pntr_ll_afifo_q + "1" WHEN (read_allow = '1') ELSE rd_pntr_ll_afifo_q;
-------------------------------------------------------------------------------
-- Generate DOUT for DRAM
-------------------------------------------------------------------------------
rd_mem : PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK = '1') THEN
DOUT <= memory(conv_integer(rd_pntr_ll_afifo)) AFTER C_TCQ;
END IF;
END PROCESS rd_mem;
-------------------------------------------------------------------------------
-- Generate EMPTY
-------------------------------------------------------------------------------
wr_pntr_eq_rd_pntr <= '1' WHEN (wr_pntr_ll_afifo = rd_pntr_ll_afifo_q) ELSE '0';
wr_pntr_eq_rd_pntr_plus1 <= '1' WHEN (wr_pntr_ll_afifo = conv_std_logic_vector(
(conv_integer(rd_pntr_ll_afifo_q)+1),
C_RD_PNTR_WIDTH)) ELSE '0';
proc_empty : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
ll_afifo_empty <= '1';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
ll_afifo_empty <= wr_pntr_eq_rd_pntr OR (read_allow AND wr_pntr_eq_rd_pntr_plus1) AFTER C_TCQ;
END IF;
END PROCESS proc_empty;
-------------------------------------------------------------------------------
-- Generate FULL
-------------------------------------------------------------------------------
rd_pntr_eq_wr_pntr_plus1 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+1),
C_WR_PNTR_WIDTH)) ELSE '0';
rd_pntr_eq_wr_pntr_plus2 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+2),
C_WR_PNTR_WIDTH)) ELSE '0';
proc_full : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
ll_afifo_full <= '1';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
ll_afifo_full <= rd_pntr_eq_wr_pntr_plus1 OR (write_allow AND rd_pntr_eq_wr_pntr_plus2) AFTER C_TCQ;
END IF;
END PROCESS proc_full;
EMPTY <= ll_afifo_empty;
FULL <= ll_afifo_full;
END GENERATE gll_afifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Common Clock FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_misc.ALL;
-------------------------------------------------------------------------------
-- Common-Clock Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_bhv_ss IS
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_EN : IN std_logic := '0';
RD_EN_USER : IN std_logic;
WR_EN : IN std_logic := '0';
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_RST_BUSY : IN std_logic := '0';
RD_RST_BUSY : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_bhv_ss;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_ss IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer;
C_COMMON_CLOCK : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic_vector;
false_case : std_logic_vector)
RETURN std_logic_vector IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
running_result := conv_std_logic_vector(value,bitwidth);
RETURN running_result;
END int_2_std_logic_vector;
--------------------------------------------------------------------------------
-- Constant Declaration
--------------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY, 1);
CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_FIFO_DEPTH : integer := C_WR_DEPTH;
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
CONSTANT C_DATA_WIDTH : integer := if_then_else((C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0),
C_DIN_WIDTH+2, C_DIN_WIDTH);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
CONSTANT DO_ALL_ZERO : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT RST_VAL : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
CONSTANT RST_VALUE : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= if_then_else(C_USE_DOUT_RST = 1, RST_VAL, DO_ALL_ZERO);
CONSTANT IS_ASYMMETRY : integer :=if_then_else((C_WR_PNTR_WIDTH /= C_RD_PNTR_WIDTH),1,0);
CONSTANT C_GRTR_PNTR_WIDTH : integer :=if_then_else((C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH),C_WR_PNTR_WIDTH,C_RD_PNTR_WIDTH);
CONSTANT LESSER_WIDTH : integer
:=if_then_else((C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH),
C_WR_PNTR_WIDTH,
C_RD_PNTR_WIDTH);
CONSTANT DIFF_MAX_RD : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
CONSTANT DIFF_MAX_WR : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
TYPE mem_array IS ARRAY (0 TO C_FIFO_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- Internal Signals
-------------------------------------------------------------------------------
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL read_allow_dc : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_full_i : std_logic := '0';
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
SIGNAL rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
SIGNAL srst_wrst_busy : std_logic := '0';
SIGNAL srst_rrst_busy : std_logic := '0';
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
--The delayed reset is used to deassert prog_full
SIGNAL rst_q : std_logic := '0';
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_full_noreg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL prog_empty_noreg: std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := RST_VALUE;
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL mem_pntr : integer := 0;
SIGNAL ram_wr_en_i : std_logic := '0';
SIGNAL ram_rd_en_i : std_logic := '0';
SIGNAL comp1 : std_logic := '0';
SIGNAL comp0 : std_logic := '0';
SIGNAL going_full : std_logic := '0';
SIGNAL leaving_full : std_logic := '0';
SIGNAL ram_full_comb : std_logic := '0';
SIGNAL ecomp1 : std_logic := '0';
SIGNAL ecomp0 : std_logic := '0';
SIGNAL going_empty : std_logic := '0';
SIGNAL leaving_empty : std_logic := '0';
SIGNAL ram_empty_comb : std_logic := '0';
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL wr_point_d2 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_pntr_temp : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL width_gt1 : std_logic := '0';
-------------------------------------------------------------------------------
--Used in computing AE and AF
-------------------------------------------------------------------------------
SIGNAL fcomp2 : std_logic := '0';
SIGNAL going_afull : std_logic := '0';
SIGNAL leaving_afull : std_logic := '0';
SIGNAL ram_afull_comb : std_logic := '0';
SIGNAL ecomp2 : std_logic := '0';
SIGNAL going_aempty : std_logic := '0';
SIGNAL leaving_aempty : std_logic := '0';
SIGNAL ram_aempty_comb : std_logic := '1';
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
-------------------------------------------------------------------------------
--Used in computing RD_DATA_COUNT WR_DATA_COUNT
-------------------------------------------------------------------------------
SIGNAL count_dc : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0) := int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
SIGNAL one : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0);
SIGNAL ratio : std_logic_vector(C_GRTR_PNTR_WIDTH DOWNTO 0);
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
--gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
rst_i <= RST;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST;
srst_rrst_busy <= SRST OR RD_RST_BUSY;
srst_wrst_busy <= SRST OR WR_RST_BUSY;
END GENERATE gsrst;
--No SRST
nosrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
srst_rrst_busy <= '0';
srst_wrst_busy <= '0';
END GENERATE nosrst;
gdc : IF (C_HAS_DATA_COUNT = 1) GENERATE
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
diff_count <= wr_pntr - rd_pntr;
gdcb : IF (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT(C_RD_PNTR_WIDTH-1 DOWNTO 0) <= diff_count;
DATA_COUNT(C_DATA_COUNT_WIDTH-1) <= '0' ;
END GENERATE;
gdcs : IF (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT <=
diff_count(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH);
END GENERATE;
END GENERATE gdc;
gndc : IF (C_HAS_DATA_COUNT = 0) GENERATE
DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_PRELOAD_LATENCY and C_VALID_LOW settings
-------------------------------------------------------------------------------
gvlat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_d1;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_d1;
END GENERATE gnvh;
END GENERATE gvlat1;
-------------------------------------------------------------------------------
-- Calculate UNDERFLOW based on C_PRELOAD_LATENCY and C_UNDERFLOW_LOW settings
-------------------------------------------------------------------------------
guflat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
END GENERATE guflat1;
FULL <= full_i;
gaf_ss: IF (C_HAS_ALMOST_FULL = 1 OR C_PROG_FULL_TYPE > 2 OR C_PROG_EMPTY_TYPE > 2) GENERATE
BEGIN
ALMOST_FULL <= almost_full_i;
END GENERATE gaf_ss;
gafn_ss: IF (C_HAS_ALMOST_FULL = 0 AND C_PROG_FULL_TYPE <= 2 AND C_PROG_EMPTY_TYPE <= 2) GENERATE
BEGIN
ALMOST_FULL <= '0';
END GENERATE gafn_ss;
EMPTY <= empty_i;
gae_ss: IF (C_HAS_ALMOST_EMPTY = 1) GENERATE
BEGIN
ALMOST_EMPTY <= almost_empty_i;
END GENERATE gae_ss;
gaen_ss: IF (C_HAS_ALMOST_EMPTY = 0) GENERATE
BEGIN
ALMOST_EMPTY <= '0';
END GENERATE gaen_ss;
write_allow <= WR_EN AND (NOT full_i);
read_allow <= RD_EN AND (NOT empty_i);
gen_read_allow_for_dc_fwft: IF(C_PRELOAD_REGS =1 AND C_PRELOAD_LATENCY =0) GENERATE
read_allow_dc <= RD_EN_USER AND (NOT USER_EMPTY_FB);
END GENERATE gen_read_allow_for_dc_fwft;
gen_read_allow_for_dc_std: IF(NOT(C_PRELOAD_REGS =1 AND C_PRELOAD_LATENCY =0)) GENERATE
read_allow_dc <= read_allow;
END GENERATE gen_read_allow_for_dc_std;
wrptr_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
wr_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
wr_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (write_allow = '1') THEN
wr_pntr <= wr_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
gecc_mem: IF (C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= INJECTDBITERR & INJECTSBITERR & DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gecc_mem;
gnecc_mem: IF NOT (C_USE_ECC > 0 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gnecc_mem;
rdptr_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
rd_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
rd_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (read_allow = '1') THEN
rd_pntr <= rd_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS rdptr_proc;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (CLK'event AND CLK = '1') THEN
-- user_empty_fb_d1 <= USER_EMPTY_FB;
user_empty_fb_d1 <= empty_i;
IF (user_empty_fb_d1 = '0' AND empty_i = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_i = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_i = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_i = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_i = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_i = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_i = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_i = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
-------------------------------------------------------------------------------
-- Generate DOUT for common clock low latency FIFO
-------------------------------------------------------------------------------
gll_dout: IF(C_FIFO_TYPE = 2) GENERATE
SIGNAL dout_q : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
dout_i <= memory(conv_integer(rd_pntr)) when (read_allow = '1') else dout_q;
dout_reg : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
dout_q <= dout_i AFTER C_TCQ;
END IF;
END PROCESS dout_reg;
END GENERATE gll_dout;
-------------------------------------------------------------------------------
-- Generate FULL flag
-------------------------------------------------------------------------------
gpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr (C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH) <= rd_pntr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr <= rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gtrim;
comp1 <= '1' WHEN (adj_rd_pntr_wr = (wr_pntr + "1")) ELSE '0';
comp0 <= '1' WHEN (adj_rd_pntr_wr = wr_pntr) ELSE '0';
gf_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
END GENERATE gf_wp_eq_rp;
-- Write data width is bigger than read data width
-- Write depth is smaller than read depth
-- One write could be equal to 2 or 4 or 8 reads
gf_asym: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_full <= comp1 AND write_allow AND (NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))));
leaving_full <= (comp0 AND read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))) OR RST_FULL_GEN;
END GENERATE gf_asym;
gf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
END GENERATE gf_wp_gt_rp;
ram_full_comb <= going_full OR (NOT leaving_full AND full_i);
full_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
full_i <= ram_full_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS full_proc;
-------------------------------------------------------------------------------
-- Generate ALMOST_FULL flag
-------------------------------------------------------------------------------
fcomp2 <= '1' WHEN (adj_rd_pntr_wr = (wr_pntr + "10")) ELSE '0';
gaf_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= (comp1 AND read_allow AND NOT write_allow) OR RST_FULL_GEN;
END GENERATE gaf_wp_eq_rp;
gaf_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_afull <= fcomp2 AND write_allow AND (NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))));
leaving_afull <= (comp1 AND (NOT write_allow) AND read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0))) OR RST_FULL_GEN;
END GENERATE gaf_wp_lt_rp;
gaf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= ((comp0 OR comp1 OR fcomp2) AND read_allow) OR RST_FULL_GEN;
END GENERATE gaf_wp_gt_rp;
ram_afull_comb <= going_afull OR (NOT leaving_afull AND almost_full_i);
af_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
almost_full_i <= ram_afull_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS af_proc;
-------------------------------------------------------------------------------
-- Generate EMPTY flag
-------------------------------------------------------------------------------
pad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE pad;
trim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE trim;
ecomp1 <= '1' WHEN (adj_wr_pntr_rd = (rd_pntr + "1")) ELSE '0';
ecomp0 <= '1' WHEN (adj_wr_pntr_rd = rd_pntr) ELSE '0';
ge_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_empty <= (ecomp1 AND (NOT write_allow) AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
END GENERATE ge_wp_eq_rp;
ge_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_empty <= (ecomp1 AND (NOT write_allow) AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
END GENERATE ge_wp_lt_rp;
ge_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_empty <= ecomp1 AND read_allow AND (NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0))));
leaving_empty <= ecomp0 AND write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0));
END GENERATE ge_wp_gt_rp;
ram_empty_comb <= going_empty OR (NOT leaving_empty AND empty_i);
empty_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
empty_i <= '1' AFTER C_TCQ;
ELSE
empty_i <= ram_empty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Generate data_count_int flags for RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rd_depth_gt_wr: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
SIGNAL decr_by_one : std_logic := '0';
SIGNAL incr_by_ratio : std_logic := '0';
BEGIN
ratio <= int_2_std_logic_vector(if_then_else(C_DEPTH_RATIO_RD > C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD, C_DEPTH_RATIO_WR), C_GRTR_PNTR_WIDTH+1);
one <= int_2_std_logic_vector(1, C_GRTR_PNTR_WIDTH+1);
decr_by_one <= read_allow_dc;
incr_by_ratio <= write_allow;
cntr: PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_wrst_busy = '1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1)
AFTER C_TCQ;
ELSE
IF decr_by_one = '1' THEN
IF incr_by_ratio = '0' THEN
count_dc <= count_dc - one AFTER C_TCQ;
ELSE
count_dc <= count_dc - one + ratio AFTER C_TCQ;
END IF;
ELSE
IF incr_by_ratio = '0' THEN
count_dc <= count_dc AFTER C_TCQ;
ELSE
count_dc <= count_dc + ratio AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS cntr;
rd_data_count_int <= count_dc;
wr_data_count_int <= count_dc(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE rd_depth_gt_wr;
wr_depth_gt_rd: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
SIGNAL incr_by_one : std_logic := '0';
SIGNAL decr_by_ratio : std_logic := '0';
BEGIN
ratio <= int_2_std_logic_vector(if_then_else(C_DEPTH_RATIO_RD > C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD, C_DEPTH_RATIO_WR), C_GRTR_PNTR_WIDTH+1);
one <= int_2_std_logic_vector(1, C_GRTR_PNTR_WIDTH+1);
incr_by_one <= write_allow;
decr_by_ratio <= read_allow_dc;
cntr: PROCESS (CLK, RST)
BEGIN
IF (rst_i = '1' ) THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1);
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_wrst_busy='1') THEN
count_dc <= int_2_std_logic_vector(0,C_GRTR_PNTR_WIDTH+1)
AFTER C_TCQ;
ELSE
IF incr_by_one = '1' THEN
IF decr_by_ratio = '0' THEN
count_dc <= count_dc + one AFTER C_TCQ;
ELSE
count_dc <= count_dc + one - ratio AFTER C_TCQ;
END IF;
ELSE
IF decr_by_ratio = '0' THEN
count_dc <= count_dc AFTER C_TCQ;
ELSE
count_dc <= count_dc - ratio AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS cntr;
wr_data_count_int <= count_dc;
rd_data_count_int <= count_dc(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE wr_depth_gt_rd;
-------------------------------------------------------------------------------
-- Generate ALMOST_EMPTY flag
-------------------------------------------------------------------------------
ecomp2 <= '1' WHEN (adj_wr_pntr_rd = (rd_pntr + "10")) ELSE '0';
gae_wp_eq_rp: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
going_aempty <= (ecomp2 AND (NOT write_allow) AND read_allow);
leaving_aempty <= (ecomp1 AND write_allow AND (NOT read_allow));
END GENERATE gae_wp_eq_rp;
gae_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
going_aempty <= (ecomp2 AND (NOT write_allow) AND read_allow);
leaving_aempty <= ((ecomp0 OR ecomp1 OR ecomp2) AND write_allow);
END GENERATE gae_wp_lt_rp;
gae_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
going_aempty <= ecomp2 AND read_allow AND (NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0))));
leaving_aempty <= ecomp1 AND (NOT read_allow) AND write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0));
END GENERATE gae_wp_gt_rp;
ram_aempty_comb <= going_aempty OR (NOT leaving_aempty AND almost_empty_i);
ae_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
almost_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
almost_empty_i <= '1' AFTER C_TCQ;
ELSE
almost_empty_i <= ram_aempty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS ae_proc;
-------------------------------------------------------------------------------
-- synchronous FIFO using linked lists
-------------------------------------------------------------------------------
gnll_cc_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
FIFO_PROC : PROCESS (CLK, rst_i, wr_pntr)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_point_d2 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF CLK'event AND CLK = '1' THEN
IF srst_wrst_busy = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_point_d2 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
ELSE
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_wr_d1 after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
wr_point_d2 <= wr_point_d1 after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_i /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --srst
END IF; --CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF (C_FIFO_TYPE < 2 AND C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
IF (rst_i = '1' OR srst_rrst_busy = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
END IF;
IF rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_FIFO_TYPE < 2 AND (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3 )AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF CLK'event AND CLK = '1' THEN
-- ELSE
IF (srst_rrst_busy= '1') THEN
IF (C_FIFO_TYPE < 2 AND (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3 ) AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
IF srst_rrst_busy = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
-- DRAM resets asynchronously
IF (C_FIFO_TYPE < 2 AND C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSE
-- Delay the read pointer before passing to CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_rd1 after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (RD_EN = '1') THEN
IF empty_i /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --srst
END IF; --CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
END GENERATE gnll_cc_fifo;
-------------------------------------------------------------------------------
-- Generate PROG_FULL and PROG_EMPTY flags
-------------------------------------------------------------------------------
gpf_pe: IF (C_PROG_FULL_TYPE /= 0 OR C_PROG_EMPTY_TYPE /= 0) GENERATE
SIGNAL diff_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_max : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_wr_pntr_rd_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr_asym : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_max : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_reg1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_reg1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_reg2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe_reg2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow_q : std_logic := '0';
SIGNAL read_allow_q : std_logic := '0';
SIGNAL write_only : std_logic := '0';
SIGNAL write_only_q : std_logic := '0';
SIGNAL read_only : std_logic := '0';
SIGNAL read_only_q : std_logic := '0';
SIGNAL prog_full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL prog_empty_i : std_logic := '1';
SIGNAL full_reg : std_logic := '0';
SIGNAL rst_full_ff_reg1 : std_logic := '0';
SIGNAL rst_full_ff_reg2 : std_logic := '0';
SIGNAL carry : std_logic := '0';
CONSTANT WR_RD_RATIO_I_PF : integer := if_then_else((C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH), (C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH), 0);
CONSTANT WR_RD_RATIO_PF : integer := 2**WR_RD_RATIO_I_PF;
-- CONSTANT WR_RD_RATIO_I_PE : integer := if_then_else((C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH), (C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH), 0);
-- CONSTANT WR_RD_RATIO_PE : integer := 2**WR_RD_RATIO_I_PE;
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
--CONSTANT EXTRA_WORDS : integer := if_then_else ((C_DEPTH_RATIO_WR = 1),2,
-- (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT EXTRA_WORDS_PF : integer := 2*WR_RD_RATIO_PF;
--CONSTANT EXTRA_WORDS_PE : integer := 2*WR_RD_RATIO_PE;
CONSTANT C_PF_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF, -- FWFT
C_PROG_FULL_THRESH_ASSERT_VAL); -- STD
CONSTANT C_PF_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF, -- FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); -- STD
CONSTANT C_PE_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2,
C_PROG_EMPTY_THRESH_ASSERT_VAL);
CONSTANT C_PE_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL);
BEGIN
diff_pntr_pe_max <= DIFF_MAX_RD;
dif_pntr_sym: IF (IS_ASYMMETRY = 0) GENERATE
write_only <= write_allow AND NOT read_allow;
read_only <= read_allow AND NOT write_allow;
END GENERATE dif_pntr_sym;
dif_pntr_asym: IF (IS_ASYMMETRY = 1) GENERATE
gpf_wp_lt_rp: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
read_only <= read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)) AND NOT(write_allow);
write_only <= write_allow AND NOT (read_allow AND AND_REDUCE(rd_pntr(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)));
END GENERATE gpf_wp_lt_rp;
gpf_wp_gt_rp: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
read_only <= read_allow AND NOT(write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)));
write_only<= write_allow AND AND_REDUCE(wr_pntr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)) AND NOT(read_allow);
END GENERATE gpf_wp_gt_rp;
END GENERATE dif_pntr_asym;
dif_cal_pntr_sym: IF (IS_ASYMMETRY = 0) GENERATE
wr_rd_q_proc : PROCESS (CLK)
BEGIN
IF (rst_i = '1') THEN
write_only_q <= '0';
read_only_q <= '0';
diff_pntr_reg1 <= (OTHERS => '0');
diff_pntr_pe_reg1 <= (OTHERS => '0');
diff_pntr_reg2 <= (OTHERS => '0');
diff_pntr_pe_reg2 <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_rrst_busy = '1' OR srst_wrst_busy = '1' ) THEN
IF (srst_rrst_busy = '1') THEN
read_only_q <= '0' AFTER C_TCQ;
diff_pntr_pe_reg1 <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_pe_reg2 <= (OTHERS => '0');
END IF;
IF (srst_wrst_busy = '1') THEN
write_only_q <= '0' AFTER C_TCQ;
diff_pntr_reg1 <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_reg2 <= (OTHERS => '0');
END IF;
ELSE
write_only_q <= write_only AFTER C_TCQ;
read_only_q <= read_only AFTER C_TCQ;
diff_pntr_reg2 <= diff_pntr_reg1 AFTER C_TCQ;
diff_pntr_pe_reg2 <= diff_pntr_pe_reg1 AFTER C_TCQ;
-- Add 1 to the difference pointer value when only write happens.
IF (write_only = '1') THEN
diff_pntr_reg1 <= wr_pntr - adj_rd_pntr_wr + "1" AFTER C_TCQ;
ELSE
diff_pntr_reg1 <= wr_pntr - adj_rd_pntr_wr AFTER C_TCQ;
END IF;
-- Add 1 to the difference pointer value when write or both write & read or no write & read happen.
IF (read_only = '1') THEN
diff_pntr_pe_reg1 <= adj_wr_pntr_rd - rd_pntr - "1" AFTER C_TCQ;
ELSE
diff_pntr_pe_reg1 <= adj_wr_pntr_rd - rd_pntr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
diff_pntr <= diff_pntr_reg1(C_WR_PNTR_WIDTH-1 downto 0);
diff_pntr_pe <= diff_pntr_pe_reg1(C_RD_PNTR_WIDTH-1 downto 0);
END GENERATE dif_cal_pntr_sym;
dif_cal_pntr_asym: IF (IS_ASYMMETRY = 1) GENERATE
adj_wr_pntr_rd_asym(C_RD_PNTR_WIDTH downto 1) <= adj_wr_pntr_rd;
adj_wr_pntr_rd_asym(0) <= '1';
rd_pntr_asym(C_RD_PNTR_WIDTH downto 1) <= not(rd_pntr);
rd_pntr_asym(0) <= '1';
wr_rd_q_proc : PROCESS (CLK)
BEGIN
IF (rst_i = '1') THEN
diff_pntr_pe_asym <= (OTHERS => '0');
full_reg <= '0';
rst_full_ff_reg1 <= '1';
rst_full_ff_reg2 <= '1';
diff_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1' OR srst_rrst_busy = '1' OR srst_wrst_busy = '1' ) THEN
IF (srst_rrst_busy = '1') THEN
rst_full_ff_reg1 <= '1' AFTER C_TCQ;
rst_full_ff_reg2 <= '1' AFTER C_TCQ;
full_reg <= '0' AFTER C_TCQ;
diff_pntr_pe_asym <= (OTHERS => '0') AFTER C_TCQ;
END IF;
IF (srst_wrst_busy = '1') THEN
diff_pntr <= (OTHERS => '0') AFTER C_TCQ;
END IF;
ELSE
write_only_q <= write_only AFTER C_TCQ;
read_only_q <= read_only AFTER C_TCQ;
diff_pntr_reg2 <= diff_pntr_reg1 AFTER C_TCQ;
diff_pntr_pe_reg2 <= diff_pntr_pe_reg1 AFTER C_TCQ;
rst_full_ff_reg1 <= RST_FULL_FF AFTER C_TCQ;
rst_full_ff_reg2 <= rst_full_ff_reg1 AFTER C_TCQ;
full_reg <= full_i AFTER C_TCQ;
diff_pntr_pe_asym <= adj_wr_pntr_rd_asym + rd_pntr_asym AFTER C_TCQ;
IF (full_i = '0') THEN
diff_pntr <= wr_pntr - adj_rd_pntr_wr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
carry <= (NOT(OR_REDUCE(diff_pntr_pe_asym (C_RD_PNTR_WIDTH downto 1))));
diff_pntr_pe <= diff_pntr_pe_max when (full_reg = '1' AND rst_full_ff_reg2 = '0' AND carry = '1' ) else diff_pntr_pe_asym (C_RD_PNTR_WIDTH downto 1);
END GENERATE dif_cal_pntr_asym;
-------------------------------------------------------------------------------
-- Generate PROG_FULL flag
-------------------------------------------------------------------------------
gpf: IF (C_PROG_FULL_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold constant
-------------------------------------------------------------------------------
gpf1: IF (C_PROG_FULL_TYPE = 1) GENERATE
pf1_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '0') THEN
IF ((diff_pntr) >= C_PF_ASSERT_VAL ) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((diff_pntr) < C_PF_ASSERT_VAL ) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf1_proc;
END GENERATE gpf1;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpf2: IF (C_PROG_FULL_TYPE = 2) GENERATE
pf2_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1' AND C_HAS_RST = 1) THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_NEGATE_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (RST_FULL_GEN='0') THEN
IF (conv_integer(diff_pntr) >= C_PF_ASSERT_VAL ) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) < C_PF_NEGATE_VAL) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf2_proc;
END GENERATE gpf2;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold input port
-------------------------------------------------------------------------------
gpf3: IF (C_PROG_FULL_TYPE = 3) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH)WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH;
pf3_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) > pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) = pf_assert_val) THEN
IF (read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (full_i='0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) < pf_assert_val) THEN
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf3_proc;
END GENERATE gpf3;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpf4: IF (C_PROG_FULL_TYPE = 4) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pf_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH_ASSERT -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH) WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_ASSERT;
pf_negate_val <= PROG_FULL_THRESH_NEGATE -int_2_std_logic_vector(EXTRA_WORDS_PF,C_WR_PNTR_WIDTH) WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_NEGATE;
pf4_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_wrst_busy = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr) = pf_negate_val) AND read_only_q = '1') OR
(conv_integer(diff_pntr) < pf_negate_val)) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
IF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (full_i='0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF(conv_integer(diff_pntr) < pf_negate_val) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pf4_proc;
END GENERATE gpf4;
PROG_FULL <= prog_full_i;
END GENERATE gpf;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY flag
-------------------------------------------------------------------------------
gpe: IF (C_PROG_EMPTY_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold constant
-------------------------------------------------------------------------------
gpe1: IF (C_PROG_EMPTY_TYPE = 1) GENERATE
pe1_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSE
IF (IS_ASYMMETRY = 0) THEN
IF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (rst_i = '0') THEN
IF (diff_pntr_pe <= (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (diff_pntr_pe > (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS pe1_proc;
END GENERATE gpe1;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpe2: IF (C_PROG_EMPTY_TYPE = 2) GENERATE
pe2_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSE
IF (IS_ASYMMETRY = 0) THEN
IF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_NEGATE_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (rst_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= (C_PE_ASSERT_VAL)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > (C_PE_NEGATE_VAL) ) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS pe2_proc;
END GENERATE gpe2;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold input port
-------------------------------------------------------------------------------
gpe3: IF (C_PROG_EMPTY_TYPE = 3) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH;
pe3_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) < pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) = pe_assert_val) THEN
IF (write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > pe_assert_val) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pe3_proc;
END GENERATE gpe3;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpe4: IF (C_PROG_EMPTY_TYPE = 4) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pe_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_ASSERT;
pe_negate_val <= PROG_EMPTY_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_NEGATE;
pe4_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_rrst_busy = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (IS_ASYMMETRY = 0) THEN
IF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr_pe) = pe_negate_val) AND write_only_q = '1') OR
(conv_integer(diff_pntr_pe) > pe_negate_val)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
IF (conv_integer(diff_pntr_pe) <= (pe_assert_val)) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) > pe_negate_val) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pe4_proc;
END GENERATE gpe4;
PROG_EMPTY <= prog_empty_i;
END GENERATE gpe;
END GENERATE gpf_pe;
-------------------------------------------------------------------------------
-- overflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
g7s_ovflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= full_i AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g7s_ovflw;
g8s_ovflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= (WR_RST_BUSY OR full_i) AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE g8s_ovflw;
END GENERATE govflw;
-------------------------------------------------------------------------------
-- underflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
g7s_unflw: IF (NOT (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= empty_i and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g7s_unflw;
g8s_unflw: IF ((C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus")) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= (RD_RST_BUSY OR empty_i) and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE g8s_unflw;
END GENERATE gunflw;
-------------------------------------------------------------------------------
-- wr_ack_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (CLK,rst_i)
BEGIN
IF rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF srst_wrst_busy = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_EN = '1' THEN
IF full_i /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
-----------------------------------------------------------------------------
-- valid_i generation: Synchronous FIFO
-----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF srst_rrst_busy = '1' THEN
valid_i <= '0' after C_TCQ;
ELSE --srst_i=0
-- Setup default value for underflow and valid
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_i /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Delay Valid AND DOUT
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1, STD
-----------------------------------------------------------------------------
gnll_fifo1: IF (C_FIFO_TYPE < 2) GENERATE
gv0: IF (C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT = 0) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF (rst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
valid_d1 <= valid_i after C_TCQ;
IF (srst_rrst_busy = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv1: IF (C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1) AND C_EN_SAFETY_CKT = 1) GENERATE
SIGNAL dout_rst_val_d2 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_rst_val_d1 : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN
PROCESS ( CLK )
BEGIN
rst_delayed_sft1 <= rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
PROCESS (rst_delayed_sft4 ,rst_i, CLK )
BEGIN
IF (rst_delayed_sft4 = '1' OR rst_i = '1') THEN
valid_d1 <= '0' after C_TCQ;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
valid_d1 <= valid_i after C_TCQ;
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_delayed_sft4 , CLK )
BEGIN
IF (rst_delayed_sft4 = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
--valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
--ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
--valid_d1 <= valid_i after C_TCQ;
IF (srst_rrst_busy = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
--ram_rd_en_d1 <= '0' after C_TCQ;
--valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv1;
END GENERATE gnll_fifo1;
gv1: IF (C_FIFO_TYPE = 2 OR (NOT(C_USE_EMBEDDED_REG>0 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)))) GENERATE
valid_d1 <= valid_i;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
END GENERATE gv1;
--END GENERATE gnll_fifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Preload Latency 0 (First-Word Fall-Through) Module
--#############################################################################
--#############################################################################
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fifo_generator_v13_0_1_bhv_preload0 IS
GENERIC (
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
WR_RST_BUSY : IN std_logic;
RD_RST_BUSY : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic := '0';
USERDBITERR : OUT std_logic := '0';
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0) := (OTHERS => '0')
);
END fifo_generator_v13_0_1_bhv_preload0;
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_bhv_preload0 IS
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
SIGNAL USERDATA_int : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
SIGNAL preloadstage1 : std_logic := '0';
SIGNAL preloadstage2 : std_logic := '0';
SIGNAL ram_valid_i : std_logic := '0';
SIGNAL read_data_valid_i : std_logic := '0';
SIGNAL ram_regout_en : std_logic := '0';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL empty_q : std_logic := '1';
SIGNAL rd_en_q : std_logic := '0';
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_empty_q : std_logic := '1';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
BEGIN -- behavioral
grst: IF (C_HAS_RST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE
rd_rst_i <= RD_RST;
end generate grst;
ngrst: IF (C_HAS_RST = 0 AND C_ENABLE_RST_SYNC = 1) GENERATE
rd_rst_i <= '0';
END GENERATE ngrst;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST OR WR_RST_BUSY OR RD_RST_BUSY;
END GENERATE gsrst;
--SRST
ngsrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
END GENERATE ngsrst;
gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
CONSTANT INVALID : std_logic_vector (1 downto 0) := "00";
CONSTANT STAGE1_VALID : std_logic_vector (1 downto 0) := "10";
CONSTANT STAGE2_VALID : std_logic_vector (1 downto 0) := "01";
CONSTANT BOTH_STAGES_VALID : std_logic_vector (1 downto 0) := "11";
SIGNAL curr_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
SIGNAL next_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
BEGIN
proc_fwft_fsm : PROCESS ( curr_fwft_state, RD_EN, FIFOEMPTY)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
IF (FIFOEMPTY = '0') THEN
next_fwft_state <= STAGE1_VALID;
ELSE --FIFOEMPTY = '1'
next_fwft_state <= INVALID;
END IF;
WHEN STAGE1_VALID =>
IF (FIFOEMPTY = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSE -- FIFOEMPTY = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN STAGE2_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= INVALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= STAGE1_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '0') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- FIFOEMPTY = '1' AND RD_EN = '0'
next_fwft_state <= STAGE2_VALID;
END IF;
WHEN BOTH_STAGES_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- RD_EN = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN OTHERS =>
next_fwft_state <= INVALID;
END CASE;
END PROCESS proc_fwft_fsm;
proc_fsm_reg: PROCESS (rd_rst_i, RD_CLK)
BEGIN
IF (rd_rst_i = '1') THEN
curr_fwft_state <= INVALID;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
curr_fwft_state <= INVALID AFTER C_TCQ;
ELSE
curr_fwft_state <= next_fwft_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_fsm_reg;
proc_regen: PROCESS (curr_fwft_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
STAGE2_REG_EN <= '0';
WHEN STAGE1_VALID =>
STAGE2_REG_EN <= '1';
WHEN STAGE2_VALID =>
STAGE2_REG_EN <= '0';
WHEN BOTH_STAGES_VALID =>
IF (RD_EN = '1') THEN
STAGE2_REG_EN <= '1';
ELSE
STAGE2_REG_EN <= '0';
END IF;
WHEN OTHERS =>
STAGE2_REG_EN <= '0';
END CASE;
END PROCESS proc_regen;
VALID_STAGES <= curr_fwft_state;
--------------------------------------------------------------------------------
-- preloadstage2 indicates that stage2 needs to be updated. This is true
-- whenever read_data_valid is false, and RAM_valid is true.
--------------------------------------------------------------------------------
preloadstage2 <= ram_valid_i AND (NOT read_data_valid_i OR RD_EN);
--------------------------------------------------------------------------------
-- preloadstage1 indicates that stage1 needs to be updated. This is true
-- whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
-- false (indicating that Stage1 needs updating), or preloadstage2 is active
-- (indicating that Stage2 is going to update, so Stage1, therefore, must
-- also be updated to keep it valid.
--------------------------------------------------------------------------------
preloadstage1 <= (((NOT ram_valid_i) OR preloadstage2) AND (NOT FIFOEMPTY));
--------------------------------------------------------------------------------
-- Calculate RAM_REGOUT_EN
-- The output registers are controlled by the ram_regout_en signal.
-- These registers should be updated either when the output in Stage2 is
-- invalid (preloadstage2), OR when the user is reading, in which case the
-- Stage2 value will go invalid unless it is replenished.
--------------------------------------------------------------------------------
ram_regout_en <= preloadstage2;
--------------------------------------------------------------------------------
-- Calculate RAM_RD_EN
-- RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
-- update the value in Stage1.
-- One case when this happens is when preloadstage1=true, which indicates
-- that the data in Stage1 or Stage2 is invalid, and needs to automatically
-- be updated.
-- The other case is when the user is reading from the FIFO, which guarantees
-- that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is
-- replinished by data from the memory. So, as long as the RAM has data in it,
-- a read of the RAM should occur.
--------------------------------------------------------------------------------
ram_rd_en <= (RD_EN AND NOT FIFOEMPTY) OR preloadstage1;
END GENERATE gnll_fifo;
gll_fifo: IF (C_FIFO_TYPE = 2) GENERATE
SIGNAL empty_d1 : STD_LOGIC := '1';
SIGNAL fe_of_empty : STD_LOGIC := '0';
SIGNAL curr_state : STD_LOGIC := '0';
SIGNAL next_state : STD_LOGIC := '0';
SIGNAL leaving_empty_fwft : STD_LOGIC := '0';
SIGNAL going_empty_fwft : STD_LOGIC := '0';
BEGIN
fsm_proc: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
next_state <= '1';
ELSE
next_state <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_state <= '0';
ELSE
next_state <= '1';
END IF;
WHEN OTHERS =>
next_state <= '0';
END CASE;
END PROCESS fsm_proc;
empty_reg: PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_d1 <= '1';
empty_i <= '1';
ram_valid_i <= '0';
curr_state <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
empty_d1 <= '1' AFTER C_TCQ;
empty_i <= '1' AFTER C_TCQ;
ram_valid_i <= '0' AFTER C_TCQ;
curr_state <= '0' AFTER C_TCQ;
ELSE
empty_d1 <= FIFOEMPTY AFTER C_TCQ;
curr_state <= next_state AFTER C_TCQ;
empty_i <= going_empty_fwft OR (NOT leaving_empty_fwft AND empty_i) AFTER C_TCQ;
ram_valid_i <= next_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_reg;
fe_of_empty <= empty_d1 AND (NOT FIFOEMPTY);
prege: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN OTHERS =>
ram_regout_en <= '0';
ram_rd_en <= '0';
END CASE;
END PROCESS prege;
ple: PROCESS (curr_state, fe_of_empty) -- Leaving Empty
BEGIN
CASE curr_state IS
WHEN '0' =>
leaving_empty_fwft <= fe_of_empty;
WHEN '1' =>
leaving_empty_fwft <= '1';
WHEN OTHERS =>
leaving_empty_fwft <= '0';
END CASE;
END PROCESS ple;
pge: PROCESS (curr_state, FIFOEMPTY, RD_EN) -- Going Empty
BEGIN
CASE curr_state IS
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
going_empty_fwft <= '1';
ELSE
going_empty_fwft <= '0';
END IF;
WHEN OTHERS =>
going_empty_fwft <= '0';
END CASE;
END PROCESS pge;
END GENERATE gll_fifo;
--------------------------------------------------------------------------------
-- Calculate ram_valid
-- ram_valid indicates that the data in Stage1 is valid.
--
-- If the RAM is being read from on this clock cycle (ram_rd_en=1), then
-- ram_valid is certainly going to be true.
-- If the RAM is not being read from, but the output registers are being
-- updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
-- therefore causing ram_valid to be false.
-- Otherwise, ram_valid will remain unchanged.
--------------------------------------------------------------------------------
gvalid: IF (C_FIFO_TYPE < 2) GENERATE
regout_valid: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_valid
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSE
IF ram_rd_en = '1' THEN
ram_valid_i <= '1' after C_TCQ;
ELSE
IF ram_regout_en = '1' THEN
ram_valid_i <= '0' after C_TCQ;
ELSE
ram_valid_i <= ram_valid_i after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS regout_valid;
END GENERATE gvalid;
--------------------------------------------------------------------------------
-- Calculate READ_DATA_VALID
-- READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
-- Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1,
-- such that the data in Stage1 is propogated into Stage2.
--------------------------------------------------------------------------------
regout_dvalid : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSE
read_data_valid_i <= ram_valid_i OR (read_data_valid_i AND NOT RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_dvalid;
-------------------------------------------------------------------------------
-- Calculate EMPTY
-- Defined as the inverse of READ_DATA_VALID
--
-- Description:
--
-- If read_data_valid_i indicates that the output is not valid,
-- and there is no valid data on the output of the ram to preload it
-- with, then we will report empty.
--
-- If there is no valid data on the output of the ram and we are
-- reading, then the FIFO will go empty.
--
-------------------------------------------------------------------------------
gempty: IF (C_FIFO_TYPE < 2) GENERATE
regout_empty : PROCESS (RD_CLK, rd_rst_i) --This is equivalent to (NOT read_data_valid_i)
BEGIN
IF (rd_rst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSE
empty_i <= (NOT ram_valid_i AND NOT read_data_valid_i) OR (NOT ram_valid_i AND RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_empty;
END GENERATE gempty;
regout_empty_q: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN --
empty_q <= empty_i after C_TCQ;
END IF;
END PROCESS regout_empty_q;
regout_rd_en: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
rd_en_q <= RD_EN after C_TCQ;
END IF;
END PROCESS regout_rd_en;
-------------------------------------------------------------------------------
-- Calculate user_almost_empty
-- user_almost_empty is defined such that, unless more words are written
-- to the FIFO, the next read will cause the FIFO to go EMPTY.
--
-- In most cases, whenever the output registers are updated (due to a user
-- read or a preload condition), then user_almost_empty will update to
-- whatever RAM_EMPTY is.
--
-- The exception is when the output is valid, the user is not reading, and
-- Stage1 is not empty. In this condition, Stage1 will be preloaded from the
-- memory, so we need to make sure user_almost_empty deasserts properly under
-- this condition.
-------------------------------------------------------------------------------
regout_aempty: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_empty
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSE
IF ((ram_regout_en = '1') OR (FIFOEMPTY = '0' AND read_data_valid_i = '1' AND RD_EN='0')) THEN
almost_empty_i <= FIFOEMPTY after C_TCQ;
END IF;
almost_empty_q <= almost_empty_i after C_TCQ;
END IF;
END IF;
END PROCESS regout_aempty;
USEREMPTY <= empty_i;
USERALMOSTEMPTY <= almost_empty_i;
FIFORDEN <= ram_rd_en;
RAMVALID <= ram_valid_i;
guvh: IF C_USERVALID_LOW=0 GENERATE
USERVALID <= read_data_valid_i;
END GENERATE guvh;
guvl: if C_USERVALID_LOW=1 GENERATE
USERVALID <= NOT read_data_valid_i;
END GENERATE guvl;
gufh: IF C_USERUNDERFLOW_LOW=0 GENERATE
USERUNDERFLOW <= empty_q AND rd_en_q;
END GENERATE gufh;
gufl: if C_USERUNDERFLOW_LOW=1 GENERATE
USERUNDERFLOW <= NOT (empty_q AND rd_en_q);
END GENERATE gufl;
glat0_nsafety: if C_EN_SAFETY_CKT=0 GENERATE
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END GENERATE glat0_nsafety;
glat0_safety: if C_EN_SAFETY_CKT=1 GENERATE
SIGNAL rst_delayed_sft1 : std_logic := '1';
SIGNAL rst_delayed_sft2 : std_logic := '1';
SIGNAL rst_delayed_sft3 : std_logic := '1';
SIGNAL rst_delayed_sft4 : std_logic := '1';
BEGIN -- PROCESS regout_lat0
PROCESS ( RD_CLK )
BEGIN
rst_delayed_sft1 <= rd_rst_i;
rst_delayed_sft2 <= rst_delayed_sft1;
rst_delayed_sft3 <= rst_delayed_sft2;
rst_delayed_sft4 <= rst_delayed_sft3;
END PROCESS;
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2 ) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2 AND rst_delayed_sft4 = '1') THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1' and rd_rst_i = '0') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END GENERATE glat0_safety;
END behavioral;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for Conventional FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_bhv_as;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_bhv_ss;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the conventional
-- FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_v13_0_1_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_INTERFACE_TYPE : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
WR_RST_I_OUT : OUT std_logic := '0';
RD_RST_I_OUT : OUT std_logic := '0'
);
END fifo_generator_v13_0_1_conv;
-------------------------------------------------------------------------------
-- Definition of Parameters
-------------------------------------------------------------------------------
-- C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
-- C_COUNT_TYPE : --not used
-- C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
-- C_DEFAULT_VALUE : --not used
-- C_DIN_WIDTH : Width of DIN bus
-- C_DOUT_RST_VAL : Reset value of DOUT
-- C_DOUT_WIDTH : Width of DOUT bus
-- C_ENABLE_RLOCS : --not used
-- C_FAMILY : not used in bhv model
-- C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
-- C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
-- C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
-- C_HAS_BACKUP : --not used
-- C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
-- C_HAS_INT_CLK : not used in bhv model
-- C_HAS_MEMINIT_FILE : --not used
-- C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
-- C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
-- C_HAS_RD_RST : --not used
-- C_HAS_RST : 1=Core has Async Rst
-- C_HAS_SRST : 1=Core has Sync Rst
-- C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
-- C_HAS_VALID : 1=Core has VALID flag
-- C_HAS_WR_ACK : 1=Core has WR_ACK flag
-- C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
-- C_HAS_WR_RST : --not used
-- C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
-- 1=Common-Clock ShiftRam
-- 2=Indep. Clocks Bram/Dram
-- 3=Virtex-4 Built-in
-- 4=Virtex-5 Built-in
-- C_INIT_WR_PNTR_VAL : --not used
-- C_MEMORY_TYPE : 1=Block RAM
-- 2=Distributed RAM
-- 3=Shift RAM
-- 4=Built-in FIFO
-- C_MIF_FILE_NAME : --not used
-- C_OPTIMIZATION_MODE : --not used
-- C_OVERFLOW_LOW : 1=OVERFLOW active low
-- C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
-- C_PRELOAD_REGS : 1=Use output registers
-- C_PRIM_FIFO_TYPE : not used in bhv model
-- C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
-- C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
-- C_PROG_EMPTY_TYPE : 0=No programmable empty
-- 1=Single prog empty thresh constant
-- 2=Multiple prog empty thresh constants
-- 3=Single prog empty thresh input
-- 4=Multiple prog empty thresh inputs
-- C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
-- C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
-- C_PROG_FULL_TYPE : 0=No prog full
-- 1=Single prog full thresh constant
-- 2=Multiple prog full thresh constants
-- 3=Single prog full thresh input
-- 4=Multiple prog full thresh inputs
-- C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
-- C_RD_DEPTH : Depth of read interface (2^N)
-- C_RD_FREQ : not used in bhv model
-- C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
-- C_UNDERFLOW_LOW : 1=UNDERFLOW active low
-- C_USE_DOUT_RST : 1=Resets DOUT on RST
-- C_USE_ECC : not used in bhv model
-- C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
-- C_USE_FIFO16_FLAGS : not used in bhv model
-- C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
-- C_VALID_LOW : 1=VALID active low
-- C_WR_ACK_LOW : 1=WR_ACK active low
-- C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
-- C_WR_DEPTH : Depth of write interface (2^N)
-- C_WR_FREQ : not used in bhv model
-- C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
-- C_WR_RESPONSE_LATENCY : --not used
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- BACKUP : Not used
-- BACKUP_MARKER: Not used
-- CLK : Clock
-- DIN : Input data bus
-- PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
-- PROG_FULL_THRESH : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
-- RD_CLK : Read Domain Clock
-- RD_EN : Read enable
-- RD_RST : Not used
-- RST : Asynchronous Reset
-- SRST : Synchronous Reset
-- WR_CLK : Write Domain Clock
-- WR_EN : Write enable
-- WR_RST : Not used
-- INT_CLK : Internal Clock
-- ALMOST_EMPTY : One word remaining in FIFO
-- ALMOST_FULL : One empty space remaining in FIFO
-- DATA_COUNT : Number of data words in fifo( synchronous to CLK)
-- DOUT : Output data bus
-- EMPTY : Empty flag
-- FULL : Full flag
-- OVERFLOW : Last write rejected
-- PROG_EMPTY : Programmable Empty Flag
-- PROG_FULL : Programmable Full Flag
-- RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
-- UNDERFLOW : Last read rejected
-- VALID : Last read acknowledged, DOUT bus VALID
-- WR_ACK : Last write acknowledged
-- WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
-- SBITERR : Single Bit ECC Error Detected
-- DBITERR : Double Bit ECC Error Detected
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v13_0_1_conv IS
-----------------------------------------------------------------------------
-- FUNCTION two_comp
-- Returns a 2's complement value
-------------------------------------------------------------------------------
FUNCTION two_comp(
vect : std_logic_vector)
RETURN std_logic_vector IS
VARIABLE local_vect : std_logic_vector(vect'high DOWNTO 0);
VARIABLE toggle : integer := 0;
BEGIN
FOR i IN 0 TO vect'high LOOP
IF (toggle = 1) THEN
IF (vect(i) = '0') THEN
local_vect(i) := '1';
ELSE
local_vect(i) := '0';
END IF;
ELSE
local_vect(i) := vect(i);
IF (vect(i) = '1') THEN
toggle := 1;
END IF;
END IF;
END LOOP;
RETURN local_vect;
END two_comp;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic_vector
-- Returns a std_logic_vector for an integer value for a given width.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
IF (value < 0) THEN
running_value := -1 * value;
END IF;
FOR i IN 0 TO bitwidth-1 LOOP
IF running_value MOD 2 = 0 THEN
running_result(i) := '0';
ELSE
running_result(i) := '1';
END IF;
running_value := running_value/2;
END LOOP;
IF (value < 0) THEN -- find the 2s complement
RETURN two_comp(running_result);
ELSE
RETURN running_result;
END IF;
END int_2_std_logic_vector;
COMPONENT fifo_generator_v13_0_1_bhv_as
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_bhv_ss
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_FAMILY : string := "virtex7";
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_ECC : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
RD_EN_USER : IN std_logic;
RST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
WR_RST_BUSY : IN std_logic := '0';
RD_RST_BUSY : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_ACK : OUT std_logic;
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_bhv_preload0
GENERIC (
C_DOUT_RST_VAL : string;
C_DOUT_WIDTH : integer;
C_HAS_RST : integer;
C_HAS_SRST : integer;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
WR_RST_BUSY : IN std_logic;
RD_RST_BUSY : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic;
USERDBITERR : OUT std_logic;
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
-- Constant to have clock to register delay
CONSTANT C_TCQ : time := 100 ps;
SIGNAL zero : std_logic := '0';
SIGNAL CLK_INT : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals for delayed input signals
-- All the input signals except Clock are delayed by 100 ps and then given to
-- the models.
-----------------------------------------------------------------------------
SIGNAL rst_delayed : std_logic := '0';
SIGNAL srst_delayed : std_logic := '0';
SIGNAL wr_rst_delayed : std_logic := '0';
SIGNAL rd_rst_delayed : std_logic := '0';
SIGNAL din_delayed : std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_en_delayed : std_logic := '0';
SIGNAL rd_en_delayed : std_logic := '0';
SIGNAL prog_empty_thresh_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_assert_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_negate_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_assert_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_negate_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL injectdbiterr_delayed : std_logic := '0';
SIGNAL injectsbiterr_delayed : std_logic := '0';
SIGNAL wr_rst_busy_i : std_logic := '0';
SIGNAL rd_rst_busy_i : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
SIGNAL rd_en_fifo_in : std_logic;
SIGNAL dout_fifo_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fifo_out : std_logic;
SIGNAL almost_empty_fifo_out : std_logic;
SIGNAL valid_fifo_out : std_logic;
SIGNAL underflow_fifo_out : std_logic;
SIGNAL rd_data_count_fifo_out : std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL wr_data_count_fifo_out : std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL data_count_fifo_out : std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL DATA_COUNT_FWFT : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL SS_FWFT_RD : std_logic := '0' ;
SIGNAL SS_FWFT_WR : std_logic := '0' ;
SIGNAL FULL_int : std_logic ;
SIGNAL almost_full_i : std_logic ;
SIGNAL prog_full_i : std_logic ;
SIGNAL dout_p0_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
signal valid_p0_out : std_logic;
signal empty_p0_out : std_logic;
signal underflow_p0_out : std_logic;
signal almost_empty_p0_out : std_logic;
signal empty_p0_out_q : std_logic;
signal almost_empty_p0_out_q : std_logic;
SIGNAL ram_valid : std_logic; --Internal signal used to monitor the
--ram_valid state
signal rst_fwft : std_logic;
signal sbiterr_fifo_out : std_logic;
signal dbiterr_fifo_out : std_logic;
signal wr_rst_i : std_logic := '0';
signal rd_rst_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal rst_full_gen_i : std_logic := '0';
signal rst_full_ff_i : std_logic := '0';
signal rst_2_sync : std_logic := '0';
signal rst_2_sync_safety : std_logic := '0';
signal clk_2_sync : std_logic := '0';
signal clk_2_sync_safety : std_logic := '0';
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION log2roundup
-- Returns a log2 of the input value
-----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
CONSTANT FULL_FLAGS_RST_VAL : integer := if_then_else((C_HAS_SRST = 1),0,C_FULL_FLAGS_RST_VAL);
CONSTANT IS_WR_PNTR_WIDTH_CORRECT : integer := if_then_else((C_WR_PNTR_WIDTH = log2roundup(C_WR_DEPTH)),1,0);
CONSTANT IS_RD_PNTR_WIDTH_CORRECT : integer := if_then_else((C_RD_PNTR_WIDTH = log2roundup(C_RD_DEPTH)),1,0);
BEGIN
rst_delayed <= RST AFTER C_TCQ;
srst_delayed <= SRST AFTER C_TCQ;
wr_rst_delayed <= WR_RST AFTER C_TCQ;
rd_rst_delayed <= RD_RST AFTER C_TCQ;
din_delayed <= DIN AFTER C_TCQ;
wr_en_delayed <= WR_EN AFTER C_TCQ;
rd_en_delayed <= RD_EN AFTER C_TCQ;
prog_empty_thresh_delayed <= PROG_EMPTY_THRESH AFTER C_TCQ;
prog_empty_thresh_assert_delayed <= PROG_EMPTY_THRESH_ASSERT AFTER C_TCQ;
prog_empty_thresh_negate_delayed <= PROG_EMPTY_THRESH_NEGATE AFTER C_TCQ;
prog_full_thresh_delayed <= PROG_FULL_THRESH AFTER C_TCQ;
prog_full_thresh_assert_delayed <= PROG_FULL_THRESH_ASSERT AFTER C_TCQ;
prog_full_thresh_negate_delayed <= PROG_FULL_THRESH_NEGATE AFTER C_TCQ;
injectdbiterr_delayed <= INJECTDBITERR AFTER C_TCQ;
injectsbiterr_delayed <= INJECTSBITERR AFTER C_TCQ;
--Assign Ground Signal
zero <= '0';
ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado." SEVERITY FAILURE;
--
ASSERT (C_IMPLEMENTATION_TYPE /= 2) REPORT "WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information." SEVERITY NOTE;
ASSERT (IS_WR_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH." SEVERITY FAILURE;
ASSERT (IS_RD_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH." SEVERITY FAILURE;
gen_ss : IF ((C_IMPLEMENTATION_TYPE = 0) OR (C_IMPLEMENTATION_TYPE = 1) OR (C_MEMORY_TYPE = 4)) GENERATE
fgss : fifo_generator_v13_0_1_bhv_ss
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => if_then_else(C_MEMORY_TYPE = 4, 1, C_MEMORY_TYPE),
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
CLK => CLK,
DIN => din_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
RD_EN => rd_en_fifo_in,
RD_EN_USER => rd_en_delayed,
RST => rst_i,
SRST => srst_delayed,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_EN => wr_en_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
ALMOST_EMPTY => almost_empty_fifo_out,
ALMOST_FULL => almost_full_i,
DATA_COUNT => data_count_fifo_out,
DOUT => dout_fifo_out,
EMPTY => empty_fifo_out,
FULL => FULL_int,
OVERFLOW => OVERFLOW,
PROG_EMPTY => PROG_EMPTY,
PROG_FULL => prog_full_i,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
VALID => valid_fifo_out,
WR_ACK => WR_ACK,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_ss;
gen_as : IF (C_IMPLEMENTATION_TYPE = 2 OR C_FIFO_TYPE = 3) GENERATE
fgas : fifo_generator_v13_0_1_bhv_as
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
WR_CLK => WR_CLK,
RD_CLK => RD_CLK,
RST => rst_i,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_RST => wr_rst_i,
RD_RST => rd_rst_i,
DIN => din_delayed,
RD_EN => rd_en_fifo_in,
WR_EN => wr_en_delayed,
RD_EN_USER => rd_en_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
DOUT => dout_fifo_out,
FULL => FULL_int,
ALMOST_FULL => almost_full_i,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_fifo_out,
ALMOST_EMPTY => almost_empty_fifo_out,
VALID => valid_fifo_out,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
PROG_FULL => prog_full_i,
PROG_EMPTY => PROG_EMPTY,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_as;
ALMOST_FULL <= almost_full_i;
PROG_FULL <= prog_full_i;
WR_RST_I_OUT <= wr_rst_i;
RD_RST_I_OUT <= rd_rst_i;
-------------------------------------------------------------------------
-- Connect internal clock used for FWFT logic based on C_COMMON_CLOCK ---
-------------------------------------------------------------------------
clock_fwft_common: IF (C_COMMON_CLOCK=1 ) GENERATE
CLK_INT <= CLK;
END GENERATE clock_fwft_common;
clock_fwft: IF (C_COMMON_CLOCK= 0 ) GENERATE
CLK_INT <= RD_CLK;
END GENERATE clock_fwft;
-----------------------------------------------------------------------------
-- Connect Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
latnrm: IF (C_PRELOAD_LATENCY=1 OR C_PRELOAD_LATENCY=2 OR C_FIFO_TYPE = 3) GENERATE
rd_en_fifo_in <= rd_en_delayed;
DOUT <= dout_fifo_out;
VALID <= valid_fifo_out;
EMPTY <= empty_fifo_out;
ALMOST_EMPTY <= almost_empty_fifo_out;
UNDERFLOW <= underflow_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
WR_DATA_COUNT <= wr_data_count_fifo_out;
SBITERR <= sbiterr_fifo_out;
DBITERR <= dbiterr_fifo_out;
END GENERATE latnrm;
lat0: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND C_FIFO_TYPE /= 3) GENERATE
SIGNAL sbiterr_fwft : STD_LOGIC := '0';
SIGNAL dbiterr_fwft : STD_LOGIC := '0';
SIGNAL rd_en_to_fwft_fifo : STD_LOGIC := '0';
SIGNAL dout_fwft : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fwft : STD_LOGIC := '0';
SIGNAL valid_stages_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL stage2_reg_en_i : STD_LOGIC := '0';
BEGIN
rst_fwft <= rd_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
lat0logic : fifo_generator_v13_0_1_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
RD_EN => rd_en_to_fwft_fifo,
FIFOEMPTY => empty_fifo_out,
FIFODATA => dout_fifo_out,
FIFOSBITERR => sbiterr_fifo_out,
FIFODBITERR => dbiterr_fifo_out,
USERDATA => dout_fwft,
USERVALID => valid_p0_out,
USEREMPTY => empty_fwft,
USERALMOSTEMPTY => almost_empty_p0_out,
USERUNDERFLOW => underflow_p0_out,
RAMVALID => ram_valid, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_fifo_in,
USERSBITERR => sbiterr_fwft,
USERDBITERR => dbiterr_fwft,
STAGE2_REG_EN => stage2_reg_en_i,
VALID_STAGES => valid_stages_i
);
gberr_non_pkt_fifo: IF (C_FIFO_TYPE /= 1) GENERATE
VALID <= valid_p0_out;
ALMOST_EMPTY <= almost_empty_p0_out;
UNDERFLOW <= underflow_p0_out;
SBITERR <= sbiterr_fwft;
DBITERR <= dbiterr_fwft;
dout_p0_out <= dout_fwft;
rd_en_to_fwft_fifo <= rd_en_delayed;
empty_p0_out <= empty_fwft;
END GENERATE gberr_non_pkt_fifo;
rdcg: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND C_COMMON_CLOCK = 0) GENERATE
eclk: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk;
rcsproc: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(1, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc;
END GENERATE rdcg;
rdcg1: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND C_COMMON_CLOCK = 0) GENERATE
eclk1: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk1;
rcsproc1: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc1;
END GENERATE rdcg1;
nrdcg: IF (C_USE_FWFT_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= rd_data_count_fifo_out;
END GENERATE nrdcg;
WR_DATA_COUNT <= wr_data_count_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
---------------------------------------------------
-- logics for common-clock data count with fwft
-- For common-clock FIFOs with FWFT, data count
-- is calculated as an up-down counter to maintain
-- accuracy.
---------------------------------------------------
grd_en_npkt: IF (C_FIFO_TYPE /= 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= rd_en_delayed AND NOT valid_p0_out ;
END GENERATE ngfwft_rd;
END GENERATE grd_en_npkt;
grd_en_pkt: IF (C_FIFO_TYPE = 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND (NOT valid_p0_out);
END GENERATE ngfwft_rd;
END GENERATE grd_en_pkt;
SS_FWFT_WR <= wr_en_delayed AND (NOT FULL_int) ;
cc_data_cnt: IF (C_HAS_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
count_fwft: PROCESS (CLK, rst_fwft)
BEGIN
IF (rst_fwft = '1' AND C_HAS_RST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF ((srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') AND C_HAS_SRST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSE
IF (SS_FWFT_WR = '0' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
ELSIF (SS_FWFT_WR = '0' and SS_FWFT_RD ='1') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 after C_TCQ;
ELSIF (SS_FWFT_WR = '1' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 after C_TCQ;
ELSE
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
END IF ;
END IF;
END IF;
END PROCESS count_fwft;
END GENERATE cc_data_cnt;
----------------------------------------------
DOUT <= dout_p0_out;
EMPTY <= empty_p0_out;
gpkt_fifo_fwft: IF (C_FIFO_TYPE = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_plus1 : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_reg : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL eop_at_stage2 : STD_LOGIC := '0';
SIGNAL ram_pkt_empty : STD_LOGIC := '0';
SIGNAL ram_pkt_empty_d1 : STD_LOGIC := '0';
SIGNAL pkt_ready_to_read : STD_LOGIC := '0';
SIGNAL fwft_stage1_valid : STD_LOGIC := '0';
SIGNAL fwft_stage2_valid : STD_LOGIC := '0';
SIGNAL rd_en_2_stage2 : STD_LOGIC := '0';
SIGNAL ram_wr_en_pkt_fifo : STD_LOGIC := '0';
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL dummy_wr_eop : STD_LOGIC := '0';
SIGNAL ram_rd_en_compare : STD_LOGIC := '0';
SIGNAL partial_packet : STD_LOGIC := '0';
SIGNAL wr_rst_fwft_pkt_fifo : STD_LOGIC := '0';
SIGNAL stage1_eop : STD_LOGIC := '0';
SIGNAL stage1_eop_d1 : STD_LOGIC := '0';
SIGNAL rd_en_fifo_in_d1 : STD_LOGIC := '0';
BEGIN
wr_rst_fwft_pkt_fifo <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
-- Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
-- When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
-- When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
-- write packet count
gdummy_wr_eop: IF (C_AXI_TYPE = 0) GENERATE
SIGNAL packet_empty_wr : std_logic := '1';
BEGIN
proc_dummy_wr_eop: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
partial_packet <= '0';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed = '1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
partial_packet <= '0' AFTER C_TCQ;
ELSE
IF (almost_full_i = '1' AND ram_wr_en_pkt_fifo = '1' AND packet_empty_wr = '1' AND din_delayed(0) = '0') THEN
partial_packet <= '1' AFTER C_TCQ;
ELSE
IF (partial_packet = '1' AND din_delayed(0) = '1' AND ram_wr_en_pkt_fifo = '1') THEN
partial_packet <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS proc_dummy_wr_eop;
dummy_wr_eop <= almost_full_i AND ram_wr_en_pkt_fifo AND packet_empty_wr AND (NOT din_delayed(0)) AND (NOT partial_packet);
-- Synchronize the packet EMPTY in WR clock domain to generate the dummy WR_EOP
gpkt_empty_sync: IF (C_COMMON_CLOCK = 0) GENERATE
TYPE pkt_empty_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE-1) OF STD_LOGIC;
SIGNAL pkt_empty_sync : pkt_empty_array := (OTHERS => '1');
BEGIN
proc_empty_sync: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
pkt_empty_sync <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
pkt_empty_sync <= pkt_empty_sync(1 to C_SYNCHRONIZER_STAGE-1) & empty_p0_out AFTER C_TCQ;
END IF;
END PROCESS proc_empty_sync;
packet_empty_wr <= pkt_empty_sync(0);
END GENERATE gpkt_empty_sync;
gnpkt_empty_sync: IF (C_COMMON_CLOCK = 1) GENERATE
packet_empty_wr <= empty_p0_out;
END GENERATE gnpkt_empty_sync;
END GENERATE gdummy_wr_eop;
proc_stage1_eop: PROCESS (rst_fwft, CLK_INT)
BEGIN
IF (rst_fwft = '1') THEN
stage1_eop_d1 <= '0';
rd_en_fifo_in_d1 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed = '1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
stage1_eop_d1 <= '0' AFTER C_TCQ;
rd_en_fifo_in_d1 <= '0' AFTER C_TCQ;
ELSE
stage1_eop_d1 <= stage1_eop AFTER C_TCQ;
rd_en_fifo_in_d1 <= rd_en_fifo_in AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_stage1_eop;
stage1_eop <= dout_fifo_out(0) WHEN (rd_en_fifo_in_d1 = '1') ELSE stage1_eop_d1;
ram_wr_en_pkt_fifo <= wr_en_delayed AND (NOT FULL_int);
wr_eop <= ram_wr_en_pkt_fifo AND ((din_delayed(0) AND (NOT partial_packet)) OR dummy_wr_eop);
ram_rd_en_compare <= stage2_reg_en_i AND stage1_eop;
pkt_fifo_fwft : fifo_generator_v13_0_1_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => 2 -- Enable low latency fwft logic
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
WR_RST_BUSY => wr_rst_busy_i,
RD_RST_BUSY => rd_rst_busy_i,
RD_EN => rd_en_delayed,
FIFOEMPTY => pkt_ready_to_read,
FIFODATA => dout_fwft,
FIFOSBITERR => sbiterr_fwft,
FIFODBITERR => dbiterr_fwft,
USERDATA => dout_p0_out,
USERVALID => OPEN,
USEREMPTY => empty_p0_out,
USERALMOSTEMPTY => OPEN,
USERUNDERFLOW => OPEN,
RAMVALID => OPEN, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_2_stage2,
USERSBITERR => SBITERR,
USERDBITERR => DBITERR,
STAGE2_REG_EN => OPEN,
VALID_STAGES => OPEN
);
pkt_ready_to_read <= NOT ((ram_pkt_empty NOR empty_fwft) AND ((valid_stages_i(0) AND valid_stages_i(1)) OR eop_at_stage2));
rd_en_to_fwft_fifo <= NOT empty_fwft AND rd_en_2_stage2;
pregsm : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
eop_at_stage2 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (stage2_reg_en_i = '1') THEN
eop_at_stage2 <= stage1_eop AFTER C_TCQ;
END IF;
END IF;
END PROCESS pregsm;
-----------------------------------------------------------------------------
-- Write and Read Packet Count
-----------------------------------------------------------------------------
proc_wr_pkt_cnt: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
wr_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (wr_eop = '1') THEN
wr_pkt_count <= wr_pkt_count + int_2_std_logic_vector(1,C_WR_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_wr_pkt_cnt;
grss_pkt_cnt : IF C_COMMON_CLOCK = 1 GENERATE
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count <= (OTHERS => '0');
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH);
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
rd_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
ELSIF (stage2_reg_en_i = '1' AND stage1_eop = '1') THEN
rd_pkt_count <= rd_pkt_count + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
rd_pkt_count_plus1 <= rd_pkt_count_plus1 + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (SRST='1' OR wr_rst_busy_i='1' OR rd_rst_busy_i='1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
ELSE
IF ((rd_pkt_count = wr_pkt_count) AND wr_eop = '1') THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count_plus1 = wr_pkt_count) AND wr_eop = '0' AND almost_full_i = '0' AND ram_rd_en_compare = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS proc_pkt_empty;
END GENERATE grss_pkt_cnt;
gras_pkt_cnt : IF C_COMMON_CLOCK = 0 GENERATE
TYPE wr_pkt_cnt_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pkt_count_q : wr_pkt_cnt_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pkt_count_b2g : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_pkt_count_rd : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
proc_wr_pkt_cnt_b2g: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_b2g <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_pkt_count_b2g <= wr_pkt_count AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_b2g;
-- Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
proc_wr_pkt_cnt_rd: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_q <= (OTHERS => (OTHERS => '0'));
wr_pkt_count_rd <= (OTHERS => '0');
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
wr_pkt_count_q <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-2 DOWNTO 0) & wr_pkt_count_b2g AFTER C_TCQ;
wr_pkt_count_rd <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-1) AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_rd;
rd_pkt_count <= rd_pkt_count_reg + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH)
WHEN (stage1_eop = '1') ELSE rd_pkt_count_reg;
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count_reg <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (rd_en_fifo_in = '1') THEN
rd_pkt_count_reg <= rd_pkt_count AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty_as : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (rd_pkt_count /= wr_pkt_count_rd) THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count = wr_pkt_count_rd) AND stage2_reg_en_i = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_pkt_empty_as;
END GENERATE gras_pkt_cnt;
END GENERATE gpkt_fifo_fwft;
END GENERATE lat0;
gdc_fwft: IF (C_HAS_DATA_COUNT = 1) GENERATE
begin
ss_count: IF ((NOT ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0)) ) OR
(C_USE_FWFT_DATA_COUNT = 0) )GENERATE
begin
DATA_COUNT <= data_count_fifo_out ;
end generate ss_count ;
ss_count_fwft1: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1) ) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO 0) ;
end generate ss_count_fwft1 ;
ss_count_fwft2: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1)) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1) ;
end generate ss_count_fwft2 ;
end generate gdc_fwft;
FULL <= FULL_int;
-------------------------------------------------------------------------------
-- If there is a reset input, generate internal reset signals
-- The latency of reset will match the core behavior
-------------------------------------------------------------------------------
--Single RST
grst_sync : IF (C_ENABLE_RST_SYNC = 1 OR C_FIFO_TYPE = 3) GENERATE
grst : IF (C_HAS_RST = 1) GENERATE
gic_rst : IF (C_COMMON_CLOCK = 0 OR C_FIFO_TYPE = 3) GENERATE
SIGNAL rd_rst_asreg : std_logic:= '0';
SIGNAL rd_rst_asreg_d1 : std_logic:= '0';
SIGNAL rd_rst_asreg_d2 : std_logic:= '0';
SIGNAL rd_rst_comb : std_logic:= '0';
SIGNAL rd_rst_reg : std_logic:= '0';
SIGNAL wr_rst_asreg : std_logic:= '0';
SIGNAL wr_rst_asreg_d1 : std_logic:= '0';
SIGNAL wr_rst_asreg_d2 : std_logic:= '0';
SIGNAL wr_rst_comb : std_logic:= '0';
SIGNAL wr_rst_reg : std_logic:= '0';
SIGNAL rst_active : STD_LOGIC := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
BEGIN
PROCESS (WR_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
wr_rst_asreg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
IF (wr_rst_asreg_d1 = '1') THEN
wr_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_asreg_d1 <= wr_rst_asreg after C_TCQ;
wr_rst_asreg_d2 <= wr_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (wr_rst_asreg, wr_rst_asreg_d2)
BEGIN
wr_rst_comb <= NOT wr_rst_asreg_d2 AND wr_rst_asreg;
END PROCESS;
PROCESS (WR_CLK, wr_rst_comb)
BEGIN
IF (wr_rst_comb = '1') THEN
wr_rst_reg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event and WR_CLK = '1') THEN
rst_delayed_d1 <= rst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (wr_rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= rst_active after C_TCQ;
END IF;
END IF;
END PROCESS;
PROCESS (RD_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rd_rst_asreg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
IF (rd_rst_asreg_d1 = '1') THEN
rd_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_asreg_d1 <= rd_rst_asreg after C_TCQ;
rd_rst_asreg_d2 <= rd_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rd_rst_asreg, rd_rst_asreg_d2)
BEGIN
rd_rst_comb <= NOT rd_rst_asreg_d2 AND rd_rst_asreg;
END PROCESS;
PROCESS (RD_CLK, rd_rst_comb)
BEGIN
IF (rd_rst_comb = '1') THEN
rd_rst_reg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
wr_rst_i <= wr_rst_reg;
rd_rst_i <= rd_rst_reg;
wr_rst_busy <= '0';
wr_rst_busy_i <= '0';
rd_rst_busy <= '0';
rd_rst_busy_i <= '0';
END GENERATE gic_rst;
gcc_rst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
PROCESS (CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rst_asreg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
IF (rst_asreg_d1 = '1') THEN
rst_asreg <= '0' after C_TCQ;
ELSE
rst_asreg <= rst_asreg after C_TCQ;
END IF;
END IF;
IF (CLK'event and CLK = '1') THEN
rst_asreg_d1 <= rst_asreg after C_TCQ;
rst_asreg_d2 <= rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_asreg, rst_asreg_d2)
BEGIN
rst_comb <= NOT rst_asreg_d2 AND rst_asreg;
END PROCESS;
PROCESS (CLK, rst_comb)
BEGIN
IF (rst_comb = '1') THEN
rst_reg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
rst_i <= rst_reg;
wr_rst_busy <= '0';
wr_rst_busy_i <= '0';
rd_rst_busy <= '0';
rd_rst_busy_i <= '0';
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK = '1') THEN
rst_delayed_d1 <= rst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= rst_reg after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gcc_rst;
END GENERATE grst;
gnrst : IF (C_HAS_RST = 0) GENERATE
wr_rst_i <= '0';
rd_rst_i <= '0';
rst_i <= '0';
END GENERATE gnrst;
gsrst : IF (C_HAS_SRST = 1) GENERATE
gcc_srst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
g8s_cc_srst: IF (C_FAMILY = "virtexu" OR C_FAMILY = "kintexu" OR C_FAMILY = "artixu" OR C_FAMILY = "virtexuplus" OR C_FAMILY = "zynquplus" OR C_FAMILY = "kintexuplus") GENERATE
SIGNAL wr_rst_reg : STD_LOGIC := '0';
SIGNAL rst_active_i : STD_LOGIC := '1';
SIGNAL rst_delayed_d1 : STD_LOGIC := '1';
SIGNAL rst_delayed_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (wr_rst_reg = '0' AND srst_delayed = '1') THEN
wr_rst_reg <= '1';
ELSE
IF (wr_rst_reg = '1') THEN
wr_rst_reg <= '0';
ELSE
wr_rst_reg <= wr_rst_reg;
END IF;
END IF;
END IF;
END PROCESS;
rst_i <= wr_rst_reg;
rd_rst_busy <= wr_rst_reg;
rd_rst_busy_i <= wr_rst_reg;
wr_rst_busy <= wr_rst_reg WHEN (C_MEMORY_TYPE /= 4) ELSE rst_active_i;
wr_rst_busy_i <= wr_rst_reg WHEN (C_MEMORY_TYPE /= 4) ELSE rst_active_i;
rst_full_ff_i <= wr_rst_reg;
rst_full_gen_i <= rst_active_i WHEN (C_FULL_FLAGS_RST_VAL = 1) ELSE '0';
PROCESS (CLK)
BEGIN
IF (CLK'event and CLK = '1') THEN
rst_delayed_d1 <= srst_delayed after C_TCQ;
rst_delayed_d2 <= rst_delayed_d1 after C_TCQ;
IF (wr_rst_reg = '1' OR rst_delayed_d2 = '1') THEN
rst_active_i <= '1' after C_TCQ;
ELSE
rst_active_i <= wr_rst_reg after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE g8s_cc_srst;
END GENERATE gcc_srst;
END GENERATE gsrst;
END GENERATE grst_sync;
gnrst_sync : IF (C_ENABLE_RST_SYNC = 0) GENERATE
wr_rst_i <= wr_rst_delayed;
rd_rst_i <= rd_rst_delayed;
rst_i <= '0';
END GENERATE gnrst_sync;
rst_2_sync <= rst_delayed WHEN (C_ENABLE_RST_SYNC = 1) ELSE wr_rst_delayed;
rst_2_sync_safety <= RST WHEN (C_ENABLE_RST_SYNC = 1) ELSE RD_RST;
clk_2_sync <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE WR_CLK;
clk_2_sync_safety <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE RD_CLK;
grst_safety_ckt: IF (C_EN_SAFETY_CKT = 1 AND C_INTERFACE_TYPE = 0) GENERATE
SIGNAL rst_d1_safety : STD_LOGIC := '1';
SIGNAL rst_d2_safety : STD_LOGIC := '1';
SIGNAL rst_d3_safety : STD_LOGIC := '1';
SIGNAL rst_d4_safety : STD_LOGIC := '1';
SIGNAL rst_d5_safety : STD_LOGIC := '1';
SIGNAL rst_d6_safety : STD_LOGIC := '1';
SIGNAL rst_d7_safety : STD_LOGIC := '1';
BEGIN
prst: PROCESS (rst_2_sync_safety, clk_2_sync_safety)
BEGIN
IF (rst_2_sync_safety = '1') THEN
rst_d1_safety <= '1';
rst_d2_safety <= '1';
rst_d3_safety <= '1';
rst_d4_safety <= '1';
rst_d5_safety <= '1';
rst_d6_safety <= '1';
rst_d7_safety <= '1';
ELSIF (clk_2_sync_safety'event AND clk_2_sync_safety = '1') THEN
rst_d1_safety <= '0' AFTER C_TCQ;
rst_d2_safety <= rst_d1_safety AFTER C_TCQ;
rst_d3_safety <= rst_d2_safety AFTER C_TCQ;
rst_d4_safety <= rst_d3_safety AFTER C_TCQ;
rst_d5_safety <= rst_d4_safety AFTER C_TCQ;
rst_d6_safety <= rst_d5_safety AFTER C_TCQ;
rst_d7_safety <= rst_d6_safety AFTER C_TCQ;
END IF;
END PROCESS prst;
assert_safety: PROCESS (rst_d7_safety, wr_en)
BEGIN
IF(rst_d7_safety = '1' AND wr_en = '1') THEN
assert false
report "A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled"
severity warning;
END IF;
END PROCESS assert_safety;
END GENERATE grst_safety_ckt;
grstd1 : IF ((C_HAS_RST = 1 OR C_HAS_SRST = 1 OR C_ENABLE_RST_SYNC = 0)) GENERATE
-- RST_FULL_GEN replaces the reset falling edge detection used to de-assert
-- FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
-- RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
-- PROG_FULL
grst_full: IF (C_FULL_FLAGS_RST_VAL = 1) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
SIGNAL rst_d3 : STD_LOGIC := '1';
SIGNAL rst_d4 : STD_LOGIC := '1';
SIGNAL rst_d5 : STD_LOGIC := '1';
BEGIN
grst_f: IF (C_HAS_SRST = 0) GENERATE
prst: PROCESS (rst_2_sync, clk_2_sync)
BEGIN
IF (rst_2_sync = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
rst_d3 <= '1';
rst_d4 <= '1';
rst_d5 <= '1';
ELSIF (clk_2_sync'event AND clk_2_sync = '1') THEN
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_d4 <= rst_d3 AFTER C_TCQ;
rst_d5 <= rst_d4 AFTER C_TCQ;
END IF;
END PROCESS prst;
g_nsafety_ckt: IF ((C_EN_SAFETY_CKT = 0) ) GENERATE
rst_full_gen_i <= rst_d3;
END GENERATE g_nsafety_ckt;
g_safety_ckt: IF (C_EN_SAFETY_CKT = 1 ) GENERATE
rst_full_gen_i <= rst_d5;
END GENERATE g_safety_ckt;
rst_full_ff_i <= rst_d2;
END GENERATE grst_f;
ngrst_f: IF (C_HAS_SRST = 1) GENERATE
prst: PROCESS (clk_2_sync)
BEGIN
IF (clk_2_sync'event AND clk_2_sync = '1') THEN
IF (srst_delayed = '1') THEN
rst_d1 <= '1' AFTER C_TCQ;
rst_d2 <= '1' AFTER C_TCQ;
rst_d3 <= '1' AFTER C_TCQ;
rst_full_gen_i <= '0' AFTER C_TCQ;
ELSE
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_full_gen_i <= rst_d3 AFTER C_TCQ;
END IF;
END IF;
END PROCESS prst;
rst_full_ff_i <= '0';
END GENERATE ngrst_f;
END GENERATE grst_full;
gnrst_full: IF (C_FULL_FLAGS_RST_VAL = 0) GENERATE
rst_full_gen_i <= '0';
rst_full_ff_i <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i;
END GENERATE gnrst_full;
END GENERATE grstd1;
END behavioral;
-------------------------------------------------------------------------------
--
-- Register Slice
-- Register one AXI channel on forward and/or reverse signal path
--
----------------------------------------------------------------------------
--
-- Structure:
-- reg_slice
--
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fifo_generator_v13_0_1_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END fifo_generator_v13_0_1_axic_reg_slice;
ARCHITECTURE xilinx OF fifo_generator_v13_0_1_axic_reg_slice IS
SIGNAL storage_data1 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_ready_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL m_valid_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL areset_d1 : STD_LOGIC := '0'; -- Reset delay register
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
-- Constant to have clock to register delay
CONSTANT TFF : time := 100 ps;
BEGIN
--------------------------------------------------------------------
--
-- Both FWD and REV mode
--
--------------------------------------------------------------------
gfwd_rev: IF (C_REG_CONFIG = 0) GENERATE
CONSTANT ZERO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ONE : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT TWO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL storage_data2 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL load_s1 : STD_LOGIC;
SIGNAL load_s2 : STD_LOGIC;
SIGNAL load_s1_from_s2 : BOOLEAN;
BEGIN
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with either slave side data or from storage2
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s1 = '1') THEN
IF (load_s1_from_s2) THEN
storage_data1 <= storage_data2 AFTER TFF;
ELSE
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Load storage2 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s2 = '1') THEN
storage_data2 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
-- Always load s2 on a valid transaction even if it's unnecessary
load_s2 <= S_VALID AND s_ready_i;
-- Loading s1
PROCESS(state,S_VALID,M_READY)
BEGIN
IF ((state = ZERO AND S_VALID = '1') OR -- Load when empty on slave transaction
-- Load when ONE if we both have read and write at the same time
(state = ONE AND S_VALID = '1' AND M_READY = '1') OR
-- Load when TWO and we have a transaction on Master side
(state = TWO AND M_READY = '1')) THEN
load_s1 <= '1';
ELSE
load_s1 <= '0';
END IF;
END PROCESS;
load_s1_from_s2 <= (state = TWO);
-- State Machine for handling output signals
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
state <= ZERO AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSE
CASE state IS
WHEN ZERO => -- No transaction stored locally
IF (S_VALID = '1') THEN -- Got one so move to ONE
state <= ONE AFTER TFF;
END IF;
WHEN ONE => -- One transaction stored locally
IF (M_READY = '1' AND S_VALID = '0') THEN -- Read out one so move to ZERO
state <= ZERO AFTER TFF;
END IF;
IF (M_READY = '0' AND S_VALID = '1') THEN -- Got another one so move to TWO
state <= TWO AFTER TFF;
s_ready_i <= '0' AFTER TFF;
END IF;
WHEN TWO => -- TWO transaction stored locally
IF (M_READY = '1') THEN -- Read out one so move to ONE
state <= ONE AFTER TFF;
s_ready_i <= '1' AFTER TFF;
END IF;
WHEN OTHERS =>
state <= state AFTER TFF;
END CASE;
END IF;
END IF;
END PROCESS;
m_valid_i <= state(0);
END GENERATE gfwd_rev;
--------------------------------------------------------------------
--
-- C_REG_CONFIG = 1
-- Light-weight mode.
-- 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
-- Operates same as 1-deep FIFO
--
--------------------------------------------------------------------
gfwd_rev_pipeline1: IF (C_REG_CONFIG = 1) GENERATE
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSIF (m_valid_i = '1' AND M_READY = '1') THEN
s_ready_i <= '1' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (S_VALID = '1' AND s_ready_i = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '1' AFTER TFF;
END IF;
IF (m_valid_i = '0') THEN
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
END GENERATE gfwd_rev_pipeline1;
end xilinx;-- reg_slice
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for AXI
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_misc.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1_conv;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the AXI FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_vhdl_beh IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex7";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_PIPELINE_REG : integer := 0;
C_POWER_SAVING_MODE : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- AXI Built-in FIFO Primitive Type
-- 512x36, 1kx18, 2kx9, 4kx4, etc
C_PRIM_FIFO_TYPE_WACH : string := "512x36";
C_PRIM_FIFO_TYPE_WDCH : string := "512x36";
C_PRIM_FIFO_TYPE_WRCH : string := "512x36";
C_PRIM_FIFO_TYPE_RACH : string := "512x36";
C_PRIM_FIFO_TYPE_RDCH : string := "512x36";
C_PRIM_FIFO_TYPE_AXIS : string := "512x36";
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
SLEEP : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
FULL : OUT std_logic := '0';
ALMOST_FULL : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
EMPTY : OUT std_logic := '1';
ALMOST_EMPTY : OUT std_logic := '1';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '1'; -- Active low reset, default value set to 1
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT std_logic := '0';
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT std_logic := '0';
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT std_logic := '0';
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic := '0';
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic := '0';
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : OUT std_logic := '0';
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RVALID : OUT std_logic := '0';
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT std_logic := '0';
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic := '0';
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic := '0';
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic := '0';
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT std_logic := '0';
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_SBITERR : OUT std_logic := '0';
AXI_AW_DBITERR : OUT std_logic := '0';
AXI_AW_OVERFLOW : OUT std_logic := '0';
AXI_AW_UNDERFLOW : OUT std_logic := '0';
AXI_AW_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_SBITERR : OUT std_logic := '0';
AXI_W_DBITERR : OUT std_logic := '0';
AXI_W_OVERFLOW : OUT std_logic := '0';
AXI_W_UNDERFLOW : OUT std_logic := '0';
AXI_W_PROG_FULL : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_SBITERR : OUT std_logic := '0';
AXI_B_DBITERR : OUT std_logic := '0';
AXI_B_OVERFLOW : OUT std_logic := '0';
AXI_B_UNDERFLOW : OUT std_logic := '0';
AXI_B_PROG_FULL : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_SBITERR : OUT std_logic := '0';
AXI_AR_DBITERR : OUT std_logic := '0';
AXI_AR_OVERFLOW : OUT std_logic := '0';
AXI_AR_UNDERFLOW : OUT std_logic := '0';
AXI_AR_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_SBITERR : OUT std_logic := '0';
AXI_R_DBITERR : OUT std_logic := '0';
AXI_R_OVERFLOW : OUT std_logic := '0';
AXI_R_UNDERFLOW : OUT std_logic := '0';
AXI_R_PROG_FULL : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_SBITERR : OUT std_logic := '0';
AXIS_DBITERR : OUT std_logic := '0';
AXIS_OVERFLOW : OUT std_logic := '0';
AXIS_UNDERFLOW : OUT std_logic := '0';
AXIS_PROG_FULL : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY : OUT STD_LOGIC := '1'
);
END fifo_generator_vhdl_beh;
ARCHITECTURE behavioral OF fifo_generator_vhdl_beh IS
COMPONENT fifo_generator_v13_0_1_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_INTERFACE_TYPE : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_EN_SAFETY_CKT : integer := 0;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
WR_RST_BUSY : OUT std_logic := '0';
RD_RST_BUSY : OUT std_logic := '0';
WR_RST_I_OUT : OUT std_logic := '0';
RD_RST_I_OUT : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v13_0_1_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END COMPONENT;
-- CONSTANT C_AXI_LEN_WIDTH : integer := 8;
CONSTANT C_AXI_SIZE_WIDTH : integer := 3;
CONSTANT C_AXI_BURST_WIDTH : integer := 2;
-- CONSTANT C_AXI_LOCK_WIDTH : integer := 2;
CONSTANT C_AXI_CACHE_WIDTH : integer := 4;
CONSTANT C_AXI_PROT_WIDTH : integer := 3;
CONSTANT C_AXI_QOS_WIDTH : integer := 4;
CONSTANT C_AXI_REGION_WIDTH : integer := 4;
CONSTANT C_AXI_BRESP_WIDTH : integer := 2;
CONSTANT C_AXI_RRESP_WIDTH : integer := 2;
CONSTANT TFF : time := 100 ps;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed and returns string.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : string;
false_case : string)
RETURN string IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
---------------------------------------------------------------------------
-- FUNCTION : log2roundup
---------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
CONSTANT lower_limit : integer := 1;
CONSTANT upper_limit : integer := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : bin2gray
-----------------------------------------------------------------------------
-- This function receives a binary value, and returns the associated
-- graycoded value.
FUNCTION bin2gray (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := indata(I) XOR indata(I+1);
END LOOP;
RETURN tmp_value;
END bin2gray;
-----------------------------------------------------------------------------
-- FUNCTION : gray2bin
-----------------------------------------------------------------------------
-- This function receives a gray-coded value, and returns the associated
-- binary value.
FUNCTION gray2bin (
indata : std_logic_vector;
length : integer)
RETURN std_logic_vector IS
VARIABLE tmp_value : std_logic_vector(length-1 DOWNTO 0);
BEGIN
tmp_value(length-1) := indata(length-1);
gray_loop : FOR I IN length-2 DOWNTO 0 LOOP
tmp_value(I) := XOR_REDUCE(indata(length-1 DOWNTO I));
END LOOP;
RETURN tmp_value;
END gray2bin;
--------------------------------------------------------
-- FUNCION : map_ready_valid
-- Returns the READY signal that is mapped out of FULL or ALMOST_FULL or PROG_FULL
-- Returns the VALID signal that is mapped out of EMPTY or ALMOST_EMPTY or PROG_EMPTY
--------------------------------------------------------
FUNCTION map_ready_valid(
pf_pe_type : integer;
full_empty : std_logic;
af_ae : std_logic;
pf_pe : std_logic)
RETURN std_logic IS
BEGIN
IF (pf_pe_type = 5) THEN
RETURN NOT full_empty;
ELSIF (pf_pe_type = 6) THEN
RETURN NOT af_ae;
ELSE
RETURN NOT pf_pe;
END IF;
END map_ready_valid;
SIGNAL inverted_reset : std_logic := '0';
SIGNAL axi_rs_rst : std_logic := '0';
CONSTANT IS_V8 : INTEGER := if_then_else((C_FAMILY = "virtexu"),1,0);
CONSTANT IS_K8 : INTEGER := if_then_else((C_FAMILY = "kintexu"),1,0);
CONSTANT IS_A8 : INTEGER := if_then_else((C_FAMILY = "artixu"),1,0);
CONSTANT IS_VM : INTEGER := if_then_else((C_FAMILY = "virtexuplus"),1,0);
CONSTANT IS_KM : INTEGER := if_then_else((C_FAMILY = "kintexuplus"),1,0);
CONSTANT IS_ZNQU : INTEGER := if_then_else((C_FAMILY = "zynquplus"),1,0);
CONSTANT IS_8SERIES : INTEGER := if_then_else((IS_V8 = 1 OR IS_K8 = 1 OR IS_A8 = 1 OR IS_VM = 1 OR IS_ZNQU = 1 OR IS_KM = 1),1,0);
BEGIN
inverted_reset <= NOT S_ARESETN;
gaxi_rs_rst: IF (C_INTERFACE_TYPE > 0 AND (C_AXIS_TYPE = 1 OR C_WACH_TYPE = 1 OR
C_WDCH_TYPE = 1 OR C_WRCH_TYPE = 1 OR C_RACH_TYPE = 1 OR C_RDCH_TYPE = 1)) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (inverted_reset, S_ACLK)
BEGIN
IF (inverted_reset = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
rst_d1 <= '0' AFTER TFF;
rst_d2 <= rst_d1 AFTER TFF;
END IF;
END PROCESS prst;
axi_rs_rst <= rst_d2;
END GENERATE gaxi_rs_rst;
---------------------------------------------------------------------------
-- Top level instance for Conventional FIFO.
---------------------------------------------------------------------------
gconvfifo: IF (C_INTERFACE_TYPE = 0) GENERATE
SIGNAL wr_data_count_in : std_logic_vector (C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
signal full_i : std_logic := '0';
signal empty_i : std_logic := '0';
signal WR_RST_INT : std_logic := '0';
signal RD_RST_INT : std_logic := '0';
begin
inst_conv_fifo: fifo_generator_v13_0_1_conv
GENERIC map(
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => if_then_else(C_USE_DOUT_RST = 1, C_DOUT_RST_VAL, "0"),
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RD_RST => C_HAS_RD_RST,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_HAS_WR_RST => C_HAS_WR_RST,
C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_FREQ => C_RD_FREQ,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_FREQ => C_WR_FREQ,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
CLK => CLK,
RST => RST,
SRST => SRST,
WR_CLK => WR_CLK,
WR_RST => WR_RST,
RD_CLK => RD_CLK,
RD_RST => RD_RST,
DIN => DIN,
WR_EN => WR_EN,
RD_EN => RD_EN,
PROG_EMPTY_THRESH => PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => PROG_EMPTY_THRESH_ASSERT,
PROG_EMPTY_THRESH_NEGATE => PROG_EMPTY_THRESH_NEGATE,
PROG_FULL_THRESH => PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => PROG_FULL_THRESH_ASSERT,
PROG_FULL_THRESH_NEGATE => PROG_FULL_THRESH_NEGATE,
INT_CLK => INT_CLK,
INJECTDBITERR => INJECTDBITERR,
INJECTSBITERR => INJECTSBITERR,
--Outputs
DOUT => DOUT,
FULL => full_i,
ALMOST_FULL => ALMOST_FULL,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_i,
ALMOST_EMPTY => ALMOST_EMPTY,
VALID => VALID,
UNDERFLOW => UNDERFLOW,
DATA_COUNT => DATA_COUNT,
RD_DATA_COUNT => RD_DATA_COUNT,
WR_DATA_COUNT => wr_data_count_in,
PROG_FULL => PROG_FULL,
PROG_EMPTY => PROG_EMPTY,
SBITERR => SBITERR,
DBITERR => DBITERR,
WR_RST_BUSY => WR_RST_BUSY,
RD_RST_BUSY => RD_RST_BUSY,
WR_RST_I_OUT => WR_RST_INT,
RD_RST_I_OUT => RD_RST_INT
);
FULL <= full_i;
EMPTY <= empty_i;
fifo_ic_adapter: IF (C_HAS_DATA_COUNTS_AXIS = 3) GENERATE
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL rd_eop : STD_LOGIC := '0';
SIGNAL data_read : STD_LOGIC := '0';
SIGNAL w_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL r_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_gc : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_gc_asreg_last : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_cnt_rd : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL axis_wr_rst : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
--SIGNAL axis_rd_rst : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL d_cnt : std_logic_vector(log2roundup(C_WR_DEPTH)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL d_cnt_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_w_cnt_rd_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (others => '0');
SIGNAL r_inv_pad : std_logic_vector(log2roundup(C_WR_DEPTH) DOWNTO 0) := (others => '0');
-- Defined to connect data output of one FIFO to data input of another
TYPE w_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(log2roundup(C_WR_DEPTH)-1 DOWNTO 0);
SIGNAL w_q : w_sync_array := (OTHERS => (OTHERS => '0'));
TYPE axis_af_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(0 DOWNTO 0);
BEGIN
wr_eop <= WR_EN AND not(full_i);
rd_eop <= RD_EN AND not(empty_i);
-- Write Packet count logic
proc_w_cnt: PROCESS (WR_CLK, WR_RST_INT)
BEGIN
IF (WR_RST_INT = '1') THEN
w_cnt <= (OTHERS => '0');
ELSIF (WR_CLK = '1' AND WR_CLK'EVENT) THEN
IF (wr_eop = '1') THEN
w_cnt <= w_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_w_cnt;
-- Convert Write Packet count to Grey
pw_gc : PROCESS (WR_CLK, WR_RST_INT)
BEGIN
if (WR_RST_INT = '1') then
w_cnt_gc <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
w_cnt_gc <= bin2gray(w_cnt, log2roundup(C_WR_DEPTH)) AFTER TFF;
END IF;
END PROCESS pw_gc;
-- Synchronize the Write Packet count in read domain
-- Synchronize the axis_almost_full in read domain
gpkt_cnt_sync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
-- pkt_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => log2roundup(C_WR_DEPTH_AXIS)
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => wpkt_q(i-1),
-- Q => wpkt_q(i)
-- );
PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1' AND C_HAS_RST = 1) THEN
w_q(i) <= (OTHERS => '0');
ELSIF RD_CLK'EVENT AND RD_CLK = '1' THEN
w_q(i) <= w_q(i-1) AFTER TFF;
END IF;
END PROCESS;
END GENERATE gpkt_cnt_sync_stage;
w_q(0) <= w_cnt_gc;
w_cnt_gc_asreg_last <= w_q(C_SYNCHRONIZER_STAGE);
-- Convert synchronized Write Packet count grey value to binay
pw_rd_bin : PROCESS (RD_CLK, RD_RST_INT)
BEGIN
if (RD_RST_INT = '1') then
w_cnt_rd <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last, log2roundup(C_WR_DEPTH)) AFTER TFF;
END IF;
END PROCESS pw_rd_bin;
-- Read Packet count logic
proc_r_cnt: PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1') THEN
r_cnt <= (OTHERS => '0');
ELSIF (RD_CLK = '1' AND RD_CLK'EVENT) THEN
IF (rd_eop = '1') THEN
r_cnt <= r_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_r_cnt;
-- Take the difference of write and read packet count
-- Logic is similar to rd_pe_as
adj_w_cnt_rd_pad(log2roundup(C_WR_DEPTH) DOWNTO 1) <= w_cnt_rd;
r_inv_pad(log2roundup(C_WR_DEPTH) DOWNTO 1) <= not r_cnt;
p_cry: PROCESS (rd_eop)
BEGIN
IF (rd_eop = '0') THEN
adj_w_cnt_rd_pad(0) <= '1';
r_inv_pad(0) <= '1';
ELSE
adj_w_cnt_rd_pad(0) <= '0';
r_inv_pad(0) <= '0';
END IF;
END PROCESS p_cry;
p_sub: PROCESS (RD_CLK, RD_RST_INT)
BEGIN
IF (RD_RST_INT = '1') THEN
d_cnt_pad <= (OTHERS=>'0');
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad AFTER TFF;
END IF;
END PROCESS p_sub;
d_cnt <= d_cnt_pad(log2roundup(C_WR_DEPTH) DOWNTO 1);
WR_DATA_COUNT <= d_cnt;
END GENERATE fifo_ic_adapter;
fifo_icn_adapter: IF (C_HAS_DATA_COUNTS_AXIS /= 3) GENERATE
WR_DATA_COUNT <= wr_data_count_in;
END GENERATE fifo_icn_adapter;
END GENERATE gconvfifo; -- End of conventional FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Top level instance for ramfifo in AXI Streaming FIFO core. It implements:
-- * BRAM based FIFO
-- * Dist RAM based FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxis_fifo: IF ((C_INTERFACE_TYPE = 1) AND (C_AXIS_TYPE < 2)) GENERATE
SIGNAL axis_din : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_dout : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_full : std_logic := '0';
SIGNAL axis_almost_full : std_logic := '0';
SIGNAL axis_empty : std_logic := '0';
SIGNAL axis_s_axis_tready : std_logic := '0';
SIGNAL axis_m_axis_tvalid : std_logic := '0';
SIGNAL axis_wr_en : std_logic := '0';
SIGNAL axis_rd_en : std_logic := '0';
SIGNAL axis_dc : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_rst_busy_axis : STD_LOGIC := '0';
SIGNAL rd_rst_busy_axis : STD_LOGIC := '0';
CONSTANT TDATA_OFFSET : integer := if_then_else(C_HAS_AXIS_TDATA = 1,C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH,C_DIN_WIDTH_AXIS);
CONSTANT TSTRB_OFFSET : integer := if_then_else(C_HAS_AXIS_TSTRB = 1,TDATA_OFFSET-C_AXIS_TSTRB_WIDTH,TDATA_OFFSET);
CONSTANT TKEEP_OFFSET : integer := if_then_else(C_HAS_AXIS_TKEEP = 1,TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH,TSTRB_OFFSET);
CONSTANT TID_OFFSET : integer := if_then_else(C_HAS_AXIS_TID = 1,TKEEP_OFFSET-C_AXIS_TID_WIDTH,TKEEP_OFFSET);
CONSTANT TDEST_OFFSET : integer := if_then_else(C_HAS_AXIS_TDEST = 1,TID_OFFSET-C_AXIS_TDEST_WIDTH,TID_OFFSET);
CONSTANT TUSER_OFFSET : integer := if_then_else(C_HAS_AXIS_TUSER = 1,TDEST_OFFSET-C_AXIS_TUSER_WIDTH,TDEST_OFFSET);
BEGIN
-- Generate the DIN to FIFO by concatinating the AXIS optional ports
gdin1: IF (C_HAS_AXIS_TDATA = 1) GENERATE
axis_din(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET) <= S_AXIS_TDATA;
M_AXIS_TDATA <= axis_dout(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET);
END GENERATE gdin1;
gdin2: IF (C_HAS_AXIS_TSTRB = 1) GENERATE
axis_din(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET) <= S_AXIS_TSTRB;
M_AXIS_TSTRB <= axis_dout(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET);
END GENERATE gdin2;
gdin3: IF (C_HAS_AXIS_TKEEP = 1) GENERATE
axis_din(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET) <= S_AXIS_TKEEP;
M_AXIS_TKEEP <= axis_dout(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET);
END GENERATE gdin3;
gdin4: IF (C_HAS_AXIS_TID = 1) GENERATE
axis_din(TKEEP_OFFSET-1 DOWNTO TID_OFFSET) <= S_AXIS_TID;
M_AXIS_TID <= axis_dout(TKEEP_OFFSET-1 DOWNTO TID_OFFSET);
END GENERATE gdin4;
gdin5: IF (C_HAS_AXIS_TDEST = 1) GENERATE
axis_din(TID_OFFSET-1 DOWNTO TDEST_OFFSET) <= S_AXIS_TDEST;
M_AXIS_TDEST <= axis_dout(TID_OFFSET-1 DOWNTO TDEST_OFFSET);
END GENERATE gdin5;
gdin6: IF (C_HAS_AXIS_TUSER = 1) GENERATE
axis_din(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET) <= S_AXIS_TUSER;
M_AXIS_TUSER <= axis_dout(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET);
END GENERATE gdin6;
gdin7: IF (C_HAS_AXIS_TLAST = 1) GENERATE
axis_din(0) <= S_AXIS_TLAST;
M_AXIS_TLAST <= axis_dout(0);
END GENERATE gdin7;
-- Write protection
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gaxis_wr_en1: IF (C_PROG_FULL_TYPE_AXIS = 0) GENERATE
gwe_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_wr_en <= S_AXIS_TVALID AND axis_s_axis_tready;
END GENERATE gwe_pkt;
gwe: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_wr_en <= S_AXIS_TVALID;
END GENERATE gwe;
END GENERATE gaxis_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gaxis_wr_en2: IF (C_PROG_FULL_TYPE_AXIS /= 0) GENERATE
axis_wr_en <= axis_s_axis_tready AND S_AXIS_TVALID;
END GENERATE gaxis_wr_en2;
-- Read protection
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gaxis_rd_en1: IF (C_PROG_EMPTY_TYPE_AXIS = 0) GENERATE
gre_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_rd_en <= M_AXIS_TREADY AND axis_m_axis_tvalid;
END GENERATE gre_pkt;
gre_npkt: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_rd_en <= M_AXIS_TREADY;
END GENERATE gre_npkt;
END GENERATE gaxis_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gaxis_rd_en2: IF (C_PROG_EMPTY_TYPE_AXIS /= 0) GENERATE
axis_rd_en <= axis_m_axis_tvalid AND M_AXIS_TREADY;
END GENERATE gaxis_rd_en2;
gaxisf: IF (C_AXIS_TYPE = 0) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
SIGNAL axis_wr_rst : STD_LOGIC := '0';
SIGNAL axis_rd_rst : STD_LOGIC := '0';
BEGIN
axis_we <= axis_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE axis_wr_en AND S_ACLK_EN;
axis_re <= axis_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE axis_rd_en AND M_ACLK_EN;
axisf : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 2 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 11 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_AXIS,
C_WR_DEPTH => C_WR_DEPTH_AXIS,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_DOUT_WIDTH => C_DIN_WIDTH_AXIS,
C_RD_DEPTH => C_WR_DEPTH_AXIS,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_AXIS,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_AXIS,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_AXIS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS,
C_USE_ECC => C_USE_ECC_AXIS,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_AXIS,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => if_then_else(C_APPLICATION_TYPE_AXIS = 1,1,0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else(C_APPLICATION_TYPE_AXIS = 1,0,C_APPLICATION_TYPE_AXIS),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => 0,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => axis_we,
RD_EN => axis_re,
PROG_FULL_THRESH => AXIS_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXIS_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXIS_INJECTDBITERR,
INJECTSBITERR => AXIS_INJECTSBITERR,
DIN => axis_din,
DOUT => axis_dout,
FULL => axis_full,
EMPTY => axis_empty,
ALMOST_FULL => axis_almost_full,
PROG_FULL => AXIS_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXIS_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => AXIS_OVERFLOW,
VALID => OPEN,
UNDERFLOW => AXIS_UNDERFLOW,
DATA_COUNT => axis_dc,
RD_DATA_COUNT => AXIS_RD_DATA_COUNT,
WR_DATA_COUNT => AXIS_WR_DATA_COUNT,
SBITERR => AXIS_SBITERR,
DBITERR => AXIS_DBITERR,
WR_RST_BUSY => wr_rst_busy_axis,
RD_RST_BUSY => rd_rst_busy_axis,
WR_RST_I_OUT => axis_wr_rst,
RD_RST_I_OUT => axis_rd_rst
);
g8s_axis_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_axis_rdy: IF (C_IMPLEMENTATION_TYPE_AXIS = 5 OR C_IMPLEMENTATION_TYPE_AXIS = 13) GENERATE
axis_s_axis_tready <= NOT (axis_full OR wr_rst_busy_axis);
END GENERATE g8s_bi_axis_rdy;
g8s_nbi_axis_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_AXIS = 5 OR C_IMPLEMENTATION_TYPE_AXIS = 13)) GENERATE
axis_s_axis_tready <= NOT (axis_full);
END GENERATE g8s_nbi_axis_rdy;
END GENERATE g8s_axis_rdy;
g7s_axis_rdy: IF (IS_8SERIES = 0) GENERATE
axis_s_axis_tready <= NOT (axis_full);
END GENERATE g7s_axis_rdy;
--axis_m_axis_tvalid <= NOT axis_empty WHEN (C_APPLICATION_TYPE_AXIS /= 1) ELSE NOT axis_empty AND axis_pkt_read;
gnaxis_pkt_fifo: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_m_axis_tvalid <= NOT axis_empty;
END GENERATE gnaxis_pkt_fifo;
S_AXIS_TREADY <= axis_s_axis_tready;
M_AXIS_TVALID <= axis_m_axis_tvalid;
gaxis_pkt_fifo_cc: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 1) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_wr_eop_d1 : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_cnt : INTEGER := 0;
SIGNAL axis_pkt_read : STD_LOGIC := '0';
BEGIN
axis_m_axis_tvalid <= NOT axis_empty AND axis_pkt_read;
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_read <= '0';
axis_wr_eop_d1 <= '0';
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
axis_wr_eop_d1 <= axis_wr_eop;
IF (axis_rd_eop = '1' AND (axis_pkt_cnt = 1) AND axis_wr_eop_d1 = '0') THEN
axis_pkt_read <= '0' AFTER TFF;
ELSIF ((axis_pkt_cnt > 0) OR (axis_almost_full = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
-- Packet count logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_cnt <= 0;
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop_d1 = '1' AND axis_rd_eop = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt + 1 AFTER TFF;
ELSIF (axis_rd_eop = '1' AND axis_wr_eop_d1 = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt - 1 AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gaxis_pkt_fifo_cc;
gaxis_pkt_fifo_ic: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 0) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_read : STD_LOGIC := '0';
SIGNAL axis_wpkt_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_rpkt_cnt : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_gc : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_gc_asreg_last : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_wpkt_cnt_rd : STD_LOGIC_VECTOR(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pkt_cnt : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pkt_cnt_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (OTHERS => '0');
SIGNAL adj_axis_wpkt_cnt_rd_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (others => '0');
SIGNAL rpkt_inv_pad : std_logic_vector(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 0) := (others => '0');
-- Defined to connect data output of one FIFO to data input of another
TYPE wpkt_sync_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(log2roundup(C_WR_DEPTH_AXIS)-1 DOWNTO 0);
SIGNAL wpkt_q : wpkt_sync_array := (OTHERS => (OTHERS => '0'));
TYPE axis_af_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE) OF std_logic_vector(0 DOWNTO 0);
SIGNAL axis_af_q : axis_af_array := (OTHERS => (OTHERS => '0'));
SIGNAL axis_af_rd : std_logic_vector(0 DOWNTO 0) := (others => '0');
BEGIN
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
axis_pkt_read <= '0';
ELSIF (M_ACLK = '1' AND M_ACLK'EVENT) THEN
IF (axis_rd_eop = '1' AND (conv_integer(diff_pkt_cnt) = 1)) THEN
axis_pkt_read <= '0' AFTER TFF;
-- Asserting packet read at the same time when the packet is written is not considered because it causes
-- packet FIFO handshake violation when the packet size is just 2 data beat and each write is separated
-- by more than 2 clocks. This causes the first data to come out at the FWFT stage making the actual FIFO
-- empty and leaving the first stage FWFT stage with no data, and when the last data is written, it
-- actually makes the valid to be high for a clock and de-asserts immediately as the written data will
-- take two clocks to appear at the FWFT output. This situation is a violation of packet FIFO, where
-- TVALID should not get de-asserted in between the packet transfer.
ELSIF ((conv_integer(diff_pkt_cnt) > 0) OR (axis_af_rd(0) = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
axis_m_axis_tvalid <= (NOT axis_empty) AND axis_pkt_read;
-- Write Packet count logic
proc_wpkt_cnt: PROCESS (S_ACLK, axis_wr_rst)
BEGIN
IF (axis_wr_rst = '1') THEN
axis_wpkt_cnt <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop = '1') THEN
axis_wpkt_cnt <= axis_wpkt_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_wpkt_cnt;
-- Convert Write Packet count to Grey
pwpkt_gc : PROCESS (S_ACLK, axis_wr_rst)
BEGIN
if (axis_wr_rst = '1') then
axis_wpkt_cnt_gc <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt, log2roundup(C_WR_DEPTH_AXIS)) AFTER TFF;
END IF;
END PROCESS pwpkt_gc;
-- Synchronize the Write Packet count in read domain
-- Synchronize the axis_almost_full in read domain
gpkt_cnt_sync_stage: FOR I IN 1 TO C_SYNCHRONIZER_STAGE GENERATE
BEGIN
-- pkt_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => log2roundup(C_WR_DEPTH_AXIS)
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => wpkt_q(i-1),
-- Q => wpkt_q(i)
-- );
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1' AND C_HAS_RST = 1) THEN
wpkt_q(i) <= (OTHERS => '0');
ELSIF M_ACLK'EVENT AND M_ACLK = '1' THEN
wpkt_q(i) <= wpkt_q(i-1) AFTER TFF;
END IF;
END PROCESS;
-- af_rd_stg_inst: ENTITY fifo_generator_v13_0_1.synchronizer_ff
-- GENERIC MAP (
-- C_HAS_RST => C_HAS_RST,
-- C_WIDTH => 1
-- )
-- PORT MAP (
-- RST => axis_rd_rst(0),
-- CLK => M_ACLK,
-- D => axis_af_q(i-1),
-- Q => axis_af_q(i)
-- );
PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1' AND C_HAS_RST = 1) THEN
axis_af_q(i) <= (OTHERS => '0');
ELSIF M_ACLK'EVENT AND M_ACLK = '1' THEN
axis_af_q(i) <= axis_af_q(i-1) AFTER TFF;
END IF;
END PROCESS;
END GENERATE gpkt_cnt_sync_stage;
wpkt_q(0) <= axis_wpkt_cnt_gc;
axis_wpkt_cnt_gc_asreg_last <= wpkt_q(C_SYNCHRONIZER_STAGE);
axis_af_q(0)(0) <= axis_almost_full;
axis_af_rd <= axis_af_q(C_SYNCHRONIZER_STAGE);
-- Convert synchronized Write Packet count grey value to binay
pwpkt_rd_bin : PROCESS (M_ACLK, axis_rd_rst)
BEGIN
if (axis_rd_rst = '1') then
axis_wpkt_cnt_rd <= (OTHERS => '0');
ELSIF (M_ACLK'event AND M_ACLK = '1') THEN
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last, log2roundup(C_WR_DEPTH_AXIS)) AFTER TFF;
END IF;
END PROCESS pwpkt_rd_bin;
-- Read Packet count logic
proc_rpkt_cnt: PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
axis_rpkt_cnt <= (OTHERS => '0');
ELSIF (M_ACLK = '1' AND M_ACLK'EVENT) THEN
IF (axis_rd_eop = '1') THEN
axis_rpkt_cnt <= axis_rpkt_cnt + "1" AFTER TFF;
END IF;
END IF;
END PROCESS proc_rpkt_cnt;
-- Take the difference of write and read packet count
-- Logic is similar to rd_pe_as
adj_axis_wpkt_cnt_rd_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1) <= axis_wpkt_cnt_rd;
rpkt_inv_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1) <= not axis_rpkt_cnt;
pkt_cry: PROCESS (axis_rd_eop)
BEGIN
IF (axis_rd_eop = '0') THEN
adj_axis_wpkt_cnt_rd_pad(0) <= '1';
rpkt_inv_pad(0) <= '1';
ELSE
adj_axis_wpkt_cnt_rd_pad(0) <= '0';
rpkt_inv_pad(0) <= '0';
END IF;
END PROCESS pkt_cry;
pkt_sub: PROCESS (M_ACLK, axis_rd_rst)
BEGIN
IF (axis_rd_rst = '1') THEN
diff_pkt_cnt_pad <= (OTHERS=>'0');
ELSIF M_ACLK'event AND M_ACLK = '1' THEN
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad AFTER TFF;
END IF;
END PROCESS pkt_sub;
diff_pkt_cnt <= diff_pkt_cnt_pad(log2roundup(C_WR_DEPTH_AXIS) DOWNTO 1);
END GENERATE gaxis_pkt_fifo_ic;
gdc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 1 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
SIGNAL axis_dc_pkt_fifo : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_dc_pkt_fifo <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_we = '1' AND axis_re = '0') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo + "1" AFTER TFF;
ELSIF (axis_we = '0' AND axis_re = '1') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo - "1" AFTER TFF;
END IF;
END IF;
END PROCESS;
AXIS_DATA_COUNT <= axis_dc_pkt_fifo;
END GENERATE gdc_pkt;
gndc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 0 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
AXIS_DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc_pkt;
gdc: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
AXIS_DATA_COUNT <= axis_dc;
END GENERATE gdc;
END GENERATE gaxisf;
-- Register Slice for AXI Streaming
gaxis_reg_slice: IF (C_AXIS_TYPE = 1) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
BEGIN
axis_we <= S_AXIS_TVALID WHEN (C_HAS_SLAVE_CE = 0) ELSE S_AXIS_TVALID AND S_ACLK_EN;
axis_re <= M_AXIS_TREADY WHEN (C_HAS_MASTER_CE = 0) ELSE M_AXIS_TREADY AND M_ACLK_EN;
axis_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_AXIS,
C_REG_CONFIG => C_REG_SLICE_MODE_AXIS
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => axis_din,
S_VALID => axis_we,
S_READY => S_AXIS_TREADY,
-- Master side
M_PAYLOAD_DATA => axis_dout,
M_VALID => M_AXIS_TVALID,
M_READY => axis_re
);
END GENERATE gaxis_reg_slice;
END GENERATE gaxis_fifo;
gaxifull: IF (C_INTERFACE_TYPE = 2) GENERATE
SIGNAL axi_rd_underflow_i : std_logic := '0';
SIGNAL axi_rd_overflow_i : std_logic := '0';
SIGNAL axi_wr_underflow_i : std_logic := '0';
SIGNAL axi_wr_overflow_i : std_logic := '0';
BEGIN
gwrch: IF (C_HAS_AXI_WR_CHANNEL = 1) GENERATE
SIGNAL wach_din : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout_pkt : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_full : std_logic := '0';
SIGNAL wach_almost_full : std_logic := '0';
SIGNAL wach_prog_full : std_logic := '0';
SIGNAL wach_empty : std_logic := '0';
SIGNAL wach_almost_empty : std_logic := '0';
SIGNAL wach_prog_empty : std_logic := '0';
SIGNAL wdch_din : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_dout : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_full : std_logic := '0';
SIGNAL wdch_almost_full : std_logic := '0';
SIGNAL wdch_prog_full : std_logic := '0';
SIGNAL wdch_empty : std_logic := '0';
SIGNAL wdch_almost_empty : std_logic := '0';
SIGNAL wdch_prog_empty : std_logic := '0';
SIGNAL wrch_din : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_dout : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_full : std_logic := '0';
SIGNAL wrch_almost_full : std_logic := '0';
SIGNAL wrch_prog_full : std_logic := '0';
SIGNAL wrch_empty : std_logic := '0';
SIGNAL wrch_almost_empty : std_logic := '0';
SIGNAL wrch_prog_empty : std_logic := '0';
SIGNAL axi_aw_underflow_i : std_logic := '0';
SIGNAL axi_w_underflow_i : std_logic := '0';
SIGNAL axi_b_underflow_i : std_logic := '0';
SIGNAL axi_aw_overflow_i : std_logic := '0';
SIGNAL axi_w_overflow_i : std_logic := '0';
SIGNAL axi_b_overflow_i : std_logic := '0';
SIGNAL wach_s_axi_awready : std_logic := '0';
SIGNAL wach_m_axi_awvalid : std_logic := '0';
SIGNAL wach_wr_en : std_logic := '0';
SIGNAL wach_rd_en : std_logic := '0';
SIGNAL wdch_s_axi_wready : std_logic := '0';
SIGNAL wdch_m_axi_wvalid : std_logic := '0';
SIGNAL wdch_wr_en : std_logic := '0';
SIGNAL wdch_rd_en : std_logic := '0';
SIGNAL wrch_s_axi_bvalid : std_logic := '0';
SIGNAL wrch_m_axi_bready : std_logic := '0';
SIGNAL wrch_wr_en : std_logic := '0';
SIGNAL wrch_rd_en : std_logic := '0';
SIGNAL awvalid_en : std_logic := '0';
SIGNAL awready_pkt : std_logic := '0';
SIGNAL wdch_we : STD_LOGIC := '0';
SIGNAL wr_rst_busy_wach : std_logic := '0';
SIGNAL wr_rst_busy_wdch : std_logic := '0';
SIGNAL wr_rst_busy_wrch : std_logic := '0';
SIGNAL rd_rst_busy_wach : std_logic := '0';
SIGNAL rd_rst_busy_wdch : std_logic := '0';
SIGNAL rd_rst_busy_wrch : std_logic := '0';
CONSTANT AWID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WACH);
CONSTANT AWADDR_OFFSET : integer := AWID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT AWLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWADDR_OFFSET - C_AXI_LEN_WIDTH,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLEN_OFFSET - C_AXI_SIZE_WIDTH,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWSIZE_OFFSET - C_AXI_BURST_WIDTH,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWBURST_OFFSET - C_AXI_LOCK_WIDTH,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLOCK_OFFSET - C_AXI_CACHE_WIDTH,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : integer := AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT AWQOS_OFFSET : integer := AWPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT AWREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWQOS_OFFSET - C_AXI_REGION_WIDTH, AWQOS_OFFSET);
CONSTANT AWUSER_OFFSET : integer := if_then_else(C_HAS_AXI_AWUSER = 1,AWREGION_OFFSET-C_AXI_AWUSER_WIDTH,AWREGION_OFFSET);
CONSTANT WID_OFFSET : integer := if_then_else(C_AXI_TYPE = 3 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WDCH);
CONSTANT WDATA_OFFSET : integer := WID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT WSTRB_OFFSET : integer := WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
CONSTANT WUSER_OFFSET : integer := if_then_else(C_HAS_AXI_WUSER = 1,WSTRB_OFFSET-C_AXI_WUSER_WIDTH,WSTRB_OFFSET);
CONSTANT BID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WRCH);
CONSTANT BRESP_OFFSET : integer := BID_OFFSET - C_AXI_BRESP_WIDTH;
CONSTANT BUSER_OFFSET : integer := if_then_else(C_HAS_AXI_BUSER = 1,BRESP_OFFSET-C_AXI_BUSER_WIDTH,BRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_wr_ch: IF (C_AXI_TYPE /= 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
gwach_din1: IF (C_HAS_AXI_AWUSER = 1) GENERATE
wach_din(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET) <= S_AXI_AWUSER;
M_AXI_AWUSER <= wach_dout(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET);
END GENERATE gwach_din1;
gwach_din2: IF (C_HAS_AXI_AWUSER = 0) GENERATE
M_AXI_AWUSER <= (OTHERS => '0');
END GENERATE gwach_din2;
gwach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wach_din(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET) <= S_AXI_AWID;
M_AXI_AWID <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET);
END GENERATE gwach_din3;
gwach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_AWID <= (OTHERS => '0');
END GENERATE gwach_din4;
gwach_din5: IF (C_AXI_TYPE = 1) GENERATE
wach_din(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET) <= S_AXI_AWREGION;
M_AXI_AWREGION <= wach_dout(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
END GENERATE gwach_din5;
gwach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_AWREGION <= (OTHERS => '0');
END GENERATE gwach_din6;
wach_din(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET) <= S_AXI_AWADDR;
wach_din(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET) <= S_AXI_AWLEN;
wach_din(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET) <= S_AXI_AWSIZE;
wach_din(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET) <= S_AXI_AWBURST;
wach_din(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET) <= S_AXI_AWLOCK;
wach_din(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET) <= S_AXI_AWCACHE;
wach_din(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET) <= S_AXI_AWPROT;
wach_din(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET) <= S_AXI_AWQOS;
M_AXI_AWADDR <= wach_dout(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWLEN <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
M_AXI_AWSIZE <= wach_dout(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
M_AXI_AWBURST <= wach_dout(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
M_AXI_AWLOCK <= wach_dout(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
M_AXI_AWCACHE <= wach_dout(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
M_AXI_AWPROT <= wach_dout(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
M_AXI_AWQOS <= wach_dout(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
END GENERATE gwach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
gwdch_din1: IF (C_HAS_AXI_WUSER = 1) GENERATE
wdch_din(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET) <= S_AXI_WUSER;
M_AXI_WUSER <= wdch_dout(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET);
END GENERATE gwdch_din1;
gwdch_din2: IF (C_HAS_AXI_WUSER = 0) GENERATE
M_AXI_WUSER <= (OTHERS => '0');
END GENERATE gwdch_din2;
gwdch_din3: IF (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
wdch_din(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET) <= S_AXI_WID;
M_AXI_WID <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET);
END GENERATE gwdch_din3;
gwdch_din4: IF NOT (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
M_AXI_WID <= (OTHERS => '0');
END GENERATE gwdch_din4;
wdch_din(WID_OFFSET-1 DOWNTO WDATA_OFFSET) <= S_AXI_WDATA;
wdch_din(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET) <= S_AXI_WSTRB;
wdch_din(0) <= S_AXI_WLAST;
M_AXI_WDATA <= wdch_dout(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
M_AXI_WLAST <= wdch_dout(0);
END GENERATE gwdch1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Response Channel optional ports
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
gwrch_din1: IF (C_HAS_AXI_BUSER = 1) GENERATE
wrch_din(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET) <= M_AXI_BUSER;
S_AXI_BUSER <= wrch_dout(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET);
END GENERATE gwrch_din1;
gwrch_din2: IF (C_HAS_AXI_BUSER = 0) GENERATE
S_AXI_BUSER <= (OTHERS => '0');
END GENERATE gwrch_din2;
gwrch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wrch_din(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET) <= M_AXI_BID;
S_AXI_BID <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET);
END GENERATE gwrch_din3;
gwrch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_BID <= (OTHERS => '0');
END GENERATE gwrch_din4;
wrch_din(BID_OFFSET-1 DOWNTO BRESP_OFFSET) <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_full_din_wr_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Write Address Channel optional ports
axi_lite_din_wr_ch: IF (C_AXI_TYPE = 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
wach_din <= S_AXI_AWADDR & S_AXI_AWPROT;
M_AXI_AWADDR <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWPROT <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWPROT_OFFSET);
END GENERATE gwach1;
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
wdch_din <= S_AXI_WDATA & S_AXI_WSTRB;
M_AXI_WDATA <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
END GENERATE gwdch1;
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
wrch_din <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_lite_din_wr_ch;
-- Write protection for Write Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwach_wr_en1: IF (C_PROG_FULL_TYPE_WACH = 0) GENERATE
wach_wr_en <= S_AXI_AWVALID;
END GENERATE gwach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwach_wr_en2: IF (C_PROG_FULL_TYPE_WACH /= 0) GENERATE
wach_wr_en <= wach_s_axi_awready AND S_AXI_AWVALID;
END GENERATE gwach_wr_en2;
-- Write protection for Write Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwdch_wr_en1: IF (C_PROG_FULL_TYPE_WDCH = 0) GENERATE
wdch_wr_en <= S_AXI_WVALID;
END GENERATE gwdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwdch_wr_en2: IF (C_PROG_FULL_TYPE_WDCH /= 0) GENERATE
wdch_wr_en <= wdch_s_axi_wready AND S_AXI_WVALID;
END GENERATE gwdch_wr_en2;
-- Write protection for Write Response Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwrch_wr_en1: IF (C_PROG_FULL_TYPE_WRCH = 0) GENERATE
wrch_wr_en <= M_AXI_BVALID;
END GENERATE gwrch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwrch_wr_en2: IF (C_PROG_FULL_TYPE_WRCH /= 0) GENERATE
wrch_wr_en <= wrch_m_axi_bready AND M_AXI_BVALID;
END GENERATE gwrch_wr_en2;
-- Read protection for Write Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwach_rd_en1: IF (C_PROG_EMPTY_TYPE_WACH = 0) GENERATE
gpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= awready_pkt AND awvalid_en;
END GENERATE;
gnpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= M_AXI_AWREADY;
END GENERATE;
END GENERATE gwach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwach_rd_en2: IF (C_PROG_EMPTY_TYPE_WACH /= 0) GENERATE
gaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
END GENERATE gaxi_mm_wach_rd_en2;
gnaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND M_AXI_AWREADY;
END GENERATE gnaxi_mm_wach_rd_en2;
END GENERATE gwach_rd_en2;
-- Read protection for Write Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwdch_rd_en1: IF (C_PROG_EMPTY_TYPE_WDCH = 0) GENERATE
wdch_rd_en <= M_AXI_WREADY;
END GENERATE gwdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwdch_rd_en2: IF (C_PROG_EMPTY_TYPE_WDCH /= 0) GENERATE
wdch_rd_en <= wdch_m_axi_wvalid AND M_AXI_WREADY;
END GENERATE gwdch_rd_en2;
-- Read protection for Write Response Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwrch_rd_en1: IF (C_PROG_EMPTY_TYPE_WRCH = 0) GENERATE
wrch_rd_en <= S_AXI_BREADY;
END GENERATE gwrch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwrch_rd_en2: IF (C_PROG_EMPTY_TYPE_WRCH /= 0) GENERATE
wrch_rd_en <= wrch_s_axi_bvalid AND S_AXI_BREADY;
END GENERATE gwrch_rd_en2;
gwach2: IF (C_WACH_TYPE = 0) GENERATE
SIGNAL wach_we : STD_LOGIC := '0';
SIGNAL wach_re : STD_LOGIC := '0';
BEGIN
wach_we <= wach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wach_wr_en AND S_ACLK_EN;
wach_re <= wach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wach_rd_en AND M_ACLK_EN;
axi_wach : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WACH = 2 OR C_IMPLEMENTATION_TYPE_WACH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WACH = 11 OR C_IMPLEMENTATION_TYPE_WACH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WACH,
C_WR_DEPTH => C_WR_DEPTH_WACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_DOUT_WIDTH => C_DIN_WIDTH_WACH,
C_RD_DEPTH => C_WR_DEPTH_WACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH,
C_USE_ECC => C_USE_ECC_WACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_WACH = 1),0,C_APPLICATION_TYPE_WACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wach_we,
RD_EN => wach_re,
PROG_FULL_THRESH => AXI_AW_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AW_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AW_INJECTDBITERR,
INJECTSBITERR => AXI_AW_INJECTSBITERR,
DIN => wach_din,
DOUT => wach_dout_pkt,
FULL => wach_full,
EMPTY => wach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AW_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AW_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_aw_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_aw_underflow_i,
DATA_COUNT => AXI_AW_DATA_COUNT,
RD_DATA_COUNT => AXI_AW_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AW_WR_DATA_COUNT,
SBITERR => AXI_AW_SBITERR,
DBITERR => AXI_AW_DBITERR,
WR_RST_BUSY => wr_rst_busy_wach,
RD_RST_BUSY => rd_rst_busy_wach,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_wach_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wach_rdy: IF (C_IMPLEMENTATION_TYPE_WACH = 5 OR C_IMPLEMENTATION_TYPE_WACH = 13) GENERATE
wach_s_axi_awready <= NOT (wach_full OR wr_rst_busy_wach);
END GENERATE g8s_bi_wach_rdy;
g8s_nbi_wach_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WACH = 5 OR C_IMPLEMENTATION_TYPE_WACH = 13)) GENERATE
wach_s_axi_awready <= NOT (wach_full);
END GENERATE g8s_nbi_wach_rdy;
END GENERATE g8s_wach_rdy;
g7s_wach_rdy: IF (IS_8SERIES = 0) GENERATE
wach_s_axi_awready <= NOT (wach_full);
END GENERATE g7s_wach_rdy;
wach_m_axi_awvalid <= NOT wach_empty;
S_AXI_AWREADY <= wach_s_axi_awready;
gawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL awvalid_pkt : STD_LOGIC := '0';
BEGIN
awvalid_pkt <= wach_m_axi_awvalid AND awvalid_en;
wach_pkt_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => wach_dout_pkt,
S_VALID => awvalid_pkt,
S_READY => awready_pkt,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gawvld_pkt_fifo;
gnawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
M_AXI_AWVALID <= wach_m_axi_awvalid;
wach_dout <= wach_dout_pkt;
END GENERATE gnawvld_pkt_fifo;
gaxi_wr_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AW_UNDERFLOW <= axi_aw_underflow_i;
END GENERATE gaxi_wr_ch_uf1;
gaxi_wr_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AW_OVERFLOW <= axi_aw_overflow_i;
END GENERATE gaxi_wr_ch_of1;
END GENERATE gwach2;
-- Register Slice for Write Address Channel
gwach_reg_slice: IF (C_WACH_TYPE = 1) GENERATE
wach_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => C_REG_SLICE_MODE_WACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wach_din,
S_VALID => S_AXI_AWVALID,
S_READY => S_AXI_AWREADY,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gwach_reg_slice;
gwdch2: IF (C_WDCH_TYPE = 0) GENERATE
SIGNAL wdch_re : STD_LOGIC := '0';
BEGIN
wdch_we <= wdch_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wdch_wr_en AND S_ACLK_EN;
wdch_re <= wdch_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wdch_rd_en AND M_ACLK_EN;
axi_wdch : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 2 OR C_IMPLEMENTATION_TYPE_WDCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 11 OR C_IMPLEMENTATION_TYPE_WDCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WDCH,
C_WR_DEPTH => C_WR_DEPTH_WDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WDCH,
C_RD_DEPTH => C_WR_DEPTH_WDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH,
C_USE_ECC => C_USE_ECC_WDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wdch_we,
RD_EN => wdch_re,
PROG_FULL_THRESH => AXI_W_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_W_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_W_INJECTDBITERR,
INJECTSBITERR => AXI_W_INJECTSBITERR,
DIN => wdch_din,
DOUT => wdch_dout,
FULL => wdch_full,
EMPTY => wdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_W_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_W_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_w_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_w_underflow_i,
DATA_COUNT => AXI_W_DATA_COUNT,
RD_DATA_COUNT => AXI_W_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_W_WR_DATA_COUNT,
SBITERR => AXI_W_SBITERR,
DBITERR => AXI_W_DBITERR,
WR_RST_BUSY => wr_rst_busy_wdch,
RD_RST_BUSY => rd_rst_busy_wdch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_wdch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wdch_rdy: IF (C_IMPLEMENTATION_TYPE_WDCH = 5 OR C_IMPLEMENTATION_TYPE_WDCH = 13) GENERATE
wdch_s_axi_wready <= NOT (wdch_full OR wr_rst_busy_wdch);
END GENERATE g8s_bi_wdch_rdy;
g8s_nbi_wdch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WDCH = 5 OR C_IMPLEMENTATION_TYPE_WDCH = 13)) GENERATE
wdch_s_axi_wready <= NOT (wdch_full);
END GENERATE g8s_nbi_wdch_rdy;
END GENERATE g8s_wdch_rdy;
g7s_wdch_rdy: IF (IS_8SERIES = 0) GENERATE
wdch_s_axi_wready <= NOT (wdch_full);
END GENERATE g7s_wdch_rdy;
wdch_m_axi_wvalid <= NOT wdch_empty;
S_AXI_WREADY <= wdch_s_axi_wready;
M_AXI_WVALID <= wdch_m_axi_wvalid;
gaxi_wr_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_W_UNDERFLOW <= axi_w_underflow_i;
END GENERATE gaxi_wr_ch_uf2;
gaxi_wr_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_W_OVERFLOW <= axi_w_overflow_i;
END GENERATE gaxi_wr_ch_of2;
END GENERATE gwdch2;
-- Register Slice for Write Data Channel
gwdch_reg_slice: IF (C_WDCH_TYPE = 1) GENERATE
wdch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wdch_din,
S_VALID => S_AXI_WVALID,
S_READY => S_AXI_WREADY,
-- Master side
M_PAYLOAD_DATA => wdch_dout,
M_VALID => M_AXI_WVALID,
M_READY => M_AXI_WREADY
);
END GENERATE gwdch_reg_slice;
gwrch2: IF (C_WRCH_TYPE = 0) GENERATE
SIGNAL wrch_we : STD_LOGIC := '0';
SIGNAL wrch_re : STD_LOGIC := '0';
BEGIN
wrch_we <= wrch_wr_en WHEN (C_HAS_MASTER_CE = 0) ELSE wrch_wr_en AND M_ACLK_EN;
wrch_re <= wrch_rd_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wrch_rd_en AND S_ACLK_EN;
axi_wrch : fifo_generator_v13_0_1_conv -- Write Response Channel
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 2 OR C_IMPLEMENTATION_TYPE_WRCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 11 OR C_IMPLEMENTATION_TYPE_WRCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WRCH,
C_WR_DEPTH => C_WR_DEPTH_WRCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WRCH,
C_RD_DEPTH => C_WR_DEPTH_WRCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WRCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WRCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WRCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH,
C_USE_ECC => C_USE_ECC_WRCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WRCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WRCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wrch_we,
RD_EN => wrch_re,
PROG_FULL_THRESH => AXI_B_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_B_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_B_INJECTDBITERR,
INJECTSBITERR => AXI_B_INJECTSBITERR,
DIN => wrch_din,
DOUT => wrch_dout,
FULL => wrch_full,
EMPTY => wrch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_B_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_B_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_b_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_b_underflow_i,
DATA_COUNT => AXI_B_DATA_COUNT,
RD_DATA_COUNT => AXI_B_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_B_WR_DATA_COUNT,
SBITERR => AXI_B_SBITERR,
DBITERR => AXI_B_DBITERR,
WR_RST_BUSY => wr_rst_busy_wrch,
RD_RST_BUSY => rd_rst_busy_wrch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
wrch_s_axi_bvalid <= NOT wrch_empty;
g8s_wrch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_wrch_rdy: IF (C_IMPLEMENTATION_TYPE_WRCH = 5 OR C_IMPLEMENTATION_TYPE_WRCH = 13) GENERATE
wrch_m_axi_bready <= NOT (wrch_full OR wr_rst_busy_wrch);
END GENERATE g8s_bi_wrch_rdy;
g8s_nbi_wrch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_WRCH = 5 OR C_IMPLEMENTATION_TYPE_WRCH = 13)) GENERATE
wrch_m_axi_bready <= NOT (wrch_full);
END GENERATE g8s_nbi_wrch_rdy;
END GENERATE g8s_wrch_rdy;
g7s_wrch_rdy: IF (IS_8SERIES = 0) GENERATE
wrch_m_axi_bready <= NOT (wrch_full);
END GENERATE g7s_wrch_rdy;
S_AXI_BVALID <= wrch_s_axi_bvalid;
M_AXI_BREADY <= wrch_m_axi_bready;
gaxi_wr_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_B_UNDERFLOW <= axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf3;
gaxi_wr_ch_of3: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_B_OVERFLOW <= axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of3;
END GENERATE gwrch2;
-- Register Slice for Write Response Channel
gwrch_reg_slice: IF (C_WRCH_TYPE = 1) GENERATE
wrch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WRCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WRCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wrch_din,
S_VALID => M_AXI_BVALID,
S_READY => M_AXI_BREADY,
-- Master side
M_PAYLOAD_DATA => wrch_dout,
M_VALID => S_AXI_BVALID,
M_READY => S_AXI_BREADY
);
END GENERATE gwrch_reg_slice;
gaxi_wr_ch_uf4: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_wr_underflow_i <= axi_aw_underflow_i OR axi_w_underflow_i OR axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf4;
gaxi_wr_ch_of4: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_wr_overflow_i <= axi_aw_overflow_i OR axi_w_overflow_i OR axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of4;
gaxi_pkt_fifo_wr: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
BEGIN
txn_count_en_up <= wdch_s_axi_wready AND wdch_we AND wdch_din(0);
txn_count_en_down <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
gaxi_mm_cc_pkt_wr: IF (C_COMMON_CLOCK = 1) GENERATE
proc_wr_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (txn_count_en_up = '1' AND txn_count_en_down = '0') THEN
wr_pkt_count <= wr_pkt_count + conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
ELSIF (txn_count_en_down = '1' AND txn_count_en_up = '0') THEN
wr_pkt_count <= wr_pkt_count - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
END IF;
END IF;
END PROCESS proc_wr_txn_cnt;
awvalid_en <= '1' WHEN (wr_pkt_count > conv_std_logic_vector(0,C_WR_PNTR_WIDTH_WDCH)) ELSE '0';
END GENERATE gaxi_mm_cc_pkt_wr;
END GENERATE gaxi_pkt_fifo_wr;
END GENERATE gwrch;
grdch: IF (C_HAS_AXI_RD_CHANNEL = 1) GENERATE
SIGNAL rach_din : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout_pkt : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_full : std_logic := '0';
SIGNAL rach_almost_full : std_logic := '0';
SIGNAL rach_prog_full : std_logic := '0';
SIGNAL rach_empty : std_logic := '0';
SIGNAL rach_almost_empty : std_logic := '0';
SIGNAL rach_prog_empty : std_logic := '0';
SIGNAL rdch_din : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_dout : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_full : std_logic := '0';
SIGNAL rdch_almost_full : std_logic := '0';
SIGNAL rdch_prog_full : std_logic := '0';
SIGNAL rdch_empty : std_logic := '0';
SIGNAL rdch_almost_empty : std_logic := '0';
SIGNAL rdch_prog_empty : std_logic := '0';
SIGNAL axi_ar_underflow_i : std_logic := '0';
SIGNAL axi_ar_overflow_i : std_logic := '0';
SIGNAL axi_r_underflow_i : std_logic := '0';
SIGNAL axi_r_overflow_i : std_logic := '0';
SIGNAL rach_s_axi_arready : std_logic := '0';
SIGNAL rach_m_axi_arvalid : std_logic := '0';
SIGNAL rach_wr_en : std_logic := '0';
SIGNAL rach_rd_en : std_logic := '0';
SIGNAL rdch_m_axi_rready : std_logic := '0';
SIGNAL rdch_s_axi_rvalid : std_logic := '0';
SIGNAL rdch_wr_en : std_logic := '0';
SIGNAL rdch_rd_en : std_logic := '0';
SIGNAL arvalid_en : std_logic := '0';
SIGNAL arready_pkt : std_logic := '0';
SIGNAL rdch_re : STD_LOGIC := '0';
SIGNAL wr_rst_busy_rach : STD_LOGIC := '0';
SIGNAL wr_rst_busy_rdch : STD_LOGIC := '0';
SIGNAL rd_rst_busy_rach : STD_LOGIC := '0';
SIGNAL rd_rst_busy_rdch : STD_LOGIC := '0';
CONSTANT ARID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RACH);
CONSTANT ARADDR_OFFSET : integer := ARID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT ARLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARADDR_OFFSET - C_AXI_LEN_WIDTH,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLEN_OFFSET - C_AXI_SIZE_WIDTH,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARSIZE_OFFSET - C_AXI_BURST_WIDTH,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARBURST_OFFSET - C_AXI_LOCK_WIDTH,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLOCK_OFFSET - C_AXI_CACHE_WIDTH,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : integer := ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT ARQOS_OFFSET : integer := ARPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT ARREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARQOS_OFFSET - C_AXI_REGION_WIDTH,ARQOS_OFFSET);
CONSTANT ARUSER_OFFSET : integer := if_then_else(C_HAS_AXI_ARUSER = 1,ARREGION_OFFSET-C_AXI_ARUSER_WIDTH,ARREGION_OFFSET);
CONSTANT RID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RDCH);
CONSTANT RDATA_OFFSET : integer := RID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT RRESP_OFFSET : integer := RDATA_OFFSET - C_AXI_RRESP_WIDTH;
CONSTANT RUSER_OFFSET : integer := if_then_else(C_HAS_AXI_RUSER = 1,RRESP_OFFSET-C_AXI_RUSER_WIDTH,RRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_rd_ch: IF (C_AXI_TYPE /= 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
grach_din1: IF (C_HAS_AXI_ARUSER = 1) GENERATE
rach_din(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET) <= S_AXI_ARUSER;
M_AXI_ARUSER <= rach_dout(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET);
END GENERATE grach_din1;
grach_din2: IF (C_HAS_AXI_ARUSER = 0) GENERATE
M_AXI_ARUSER <= (OTHERS => '0');
END GENERATE grach_din2;
grach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rach_din(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET) <= S_AXI_ARID;
M_AXI_ARID <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET);
END GENERATE grach_din3;
grach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_ARID <= (OTHERS => '0');
END GENERATE grach_din4;
grach_din5: IF (C_AXI_TYPE = 1) GENERATE
rach_din(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET) <= S_AXI_ARREGION;
M_AXI_ARREGION <= rach_dout(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
END GENERATE grach_din5;
grach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_ARREGION <= (OTHERS => '0');
END GENERATE grach_din6;
rach_din(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET) <= S_AXI_ARADDR;
rach_din(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET) <= S_AXI_ARLEN;
rach_din(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET) <= S_AXI_ARSIZE;
rach_din(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET) <= S_AXI_ARBURST;
rach_din(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET) <= S_AXI_ARLOCK;
rach_din(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET) <= S_AXI_ARCACHE;
rach_din(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET) <= S_AXI_ARPROT;
rach_din(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET) <= S_AXI_ARQOS;
M_AXI_ARADDR <= rach_dout(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARLEN <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
M_AXI_ARSIZE <= rach_dout(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
M_AXI_ARBURST <= rach_dout(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
M_AXI_ARLOCK <= rach_dout(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
M_AXI_ARCACHE <= rach_dout(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
M_AXI_ARPROT <= rach_dout(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
M_AXI_ARQOS <= rach_dout(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
END GENERATE grach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
grdch_din1: IF (C_HAS_AXI_RUSER = 1) GENERATE
rdch_din(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET) <= M_AXI_RUSER;
S_AXI_RUSER <= rdch_dout(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET);
END GENERATE grdch_din1;
grdch_din2: IF (C_HAS_AXI_RUSER = 0) GENERATE
S_AXI_RUSER <= (OTHERS => '0');
END GENERATE grdch_din2;
grdch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rdch_din(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET) <= M_AXI_RID;
S_AXI_RID <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET);
END GENERATE grdch_din3;
grdch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_RID <= (OTHERS => '0');
END GENERATE grdch_din4;
rdch_din(RID_OFFSET-1 DOWNTO RDATA_OFFSET) <= M_AXI_RDATA;
rdch_din(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET) <= M_AXI_RRESP;
rdch_din(0) <= M_AXI_RLAST;
S_AXI_RDATA <= rdch_dout(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
S_AXI_RLAST <= rdch_dout(0);
END GENERATE grdch1;
END GENERATE axi_full_din_rd_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Read Address Channel optional ports
axi_lite_din_rd_ch: IF (C_AXI_TYPE = 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
rach_din <= S_AXI_ARADDR & S_AXI_ARPROT;
M_AXI_ARADDR <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARPROT <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARPROT_OFFSET);
END GENERATE grach1;
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
rdch_din <= M_AXI_RDATA & M_AXI_RRESP;
S_AXI_RDATA <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
END GENERATE grdch1;
END GENERATE axi_lite_din_rd_ch;
-- Write protection for Read Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grach_wr_en1: IF (C_PROG_FULL_TYPE_RACH = 0) GENERATE
rach_wr_en <= S_AXI_ARVALID;
END GENERATE grach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grach_wr_en2: IF (C_PROG_FULL_TYPE_RACH /= 0) GENERATE
rach_wr_en <= rach_s_axi_arready AND S_AXI_ARVALID;
END GENERATE grach_wr_en2;
-- Write protection for Read Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grdch_wr_en1: IF (C_PROG_FULL_TYPE_RDCH = 0) GENERATE
rdch_wr_en <= M_AXI_RVALID;
END GENERATE grdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grdch_wr_en2: IF (C_PROG_FULL_TYPE_RDCH /= 0) GENERATE
rdch_wr_en <= rdch_m_axi_rready AND M_AXI_RVALID;
END GENERATE grdch_wr_en2;
-- Read protection for Read Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grach_rd_en1: IF (C_PROG_EMPTY_TYPE_RACH = 0) GENERATE
gpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= arready_pkt AND arvalid_en;
END GENERATE;
gnpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= M_AXI_ARREADY;
END GENERATE;
END GENERATE grach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grach_rd_en2: IF (C_PROG_EMPTY_TYPE_RACH /= 0) GENERATE
gaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
END GENERATE gaxi_mm_rach_rd_en2;
gnaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND M_AXI_ARREADY;
END GENERATE gnaxi_mm_rach_rd_en2;
END GENERATE grach_rd_en2;
-- Read protection for Read Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grdch_rd_en1: IF (C_PROG_EMPTY_TYPE_RDCH = 0) GENERATE
rdch_rd_en <= S_AXI_RREADY;
END GENERATE grdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grdch_rd_en2: IF (C_PROG_EMPTY_TYPE_RDCH /= 0) GENERATE
rdch_rd_en <= rdch_s_axi_rvalid AND S_AXI_RREADY;
END GENERATE grdch_rd_en2;
grach2: IF (C_RACH_TYPE = 0) GENERATE
SIGNAL rach_we : STD_LOGIC := '0';
SIGNAL rach_re : STD_LOGIC := '0';
BEGIN
rach_we <= rach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rach_wr_en AND S_ACLK_EN;
rach_re <= rach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE rach_rd_en AND M_ACLK_EN;
axi_rach : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_RACH = 2 OR C_IMPLEMENTATION_TYPE_RACH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_RACH = 11 OR C_IMPLEMENTATION_TYPE_RACH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RACH,
C_WR_DEPTH => C_WR_DEPTH_RACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_DOUT_WIDTH => C_DIN_WIDTH_RACH,
C_RD_DEPTH => C_WR_DEPTH_RACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH,
C_USE_ECC => C_USE_ECC_RACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_RACH = 1),0,C_APPLICATION_TYPE_RACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rach_we,
RD_EN => rach_re,
PROG_FULL_THRESH => AXI_AR_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AR_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AR_INJECTDBITERR,
INJECTSBITERR => AXI_AR_INJECTSBITERR,
DIN => rach_din,
DOUT => rach_dout_pkt,
FULL => rach_full,
EMPTY => rach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AR_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AR_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_ar_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_ar_underflow_i,
DATA_COUNT => AXI_AR_DATA_COUNT,
RD_DATA_COUNT => AXI_AR_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AR_WR_DATA_COUNT,
SBITERR => AXI_AR_SBITERR,
DBITERR => AXI_AR_DBITERR,
WR_RST_BUSY => wr_rst_busy_rach,
RD_RST_BUSY => rd_rst_busy_rach,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
g8s_rach_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_rach_rdy: IF (C_IMPLEMENTATION_TYPE_RACH = 5 OR C_IMPLEMENTATION_TYPE_RACH = 13) GENERATE
rach_s_axi_arready <= NOT (rach_full OR wr_rst_busy_rach);
END GENERATE g8s_bi_rach_rdy;
g8s_nbi_rach_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_RACH = 5 OR C_IMPLEMENTATION_TYPE_RACH = 13)) GENERATE
rach_s_axi_arready <= NOT (rach_full);
END GENERATE g8s_nbi_rach_rdy;
END GENERATE g8s_rach_rdy;
g7s_rach_rdy: IF (IS_8SERIES = 0) GENERATE
rach_s_axi_arready <= NOT (rach_full);
END GENERATE g7s_rach_rdy;
rach_m_axi_arvalid <= NOT rach_empty;
S_AXI_ARREADY <= rach_s_axi_arready;
gaxi_arvld: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL arvalid_pkt : STD_LOGIC := '0';
BEGIN
arvalid_pkt <= rach_m_axi_arvalid AND arvalid_en;
rach_pkt_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => rach_dout_pkt,
S_VALID => arvalid_pkt,
S_READY => arready_pkt,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE gaxi_arvld;
gnaxi_arvld: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
M_AXI_ARVALID <= rach_m_axi_arvalid;
rach_dout <= rach_dout_pkt;
END GENERATE gnaxi_arvld;
gaxi_rd_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AR_UNDERFLOW <= axi_ar_underflow_i;
END GENERATE gaxi_rd_ch_uf1;
gaxi_rd_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AR_OVERFLOW <= axi_ar_overflow_i;
END GENERATE gaxi_rd_ch_of1;
END GENERATE grach2;
-- Register Slice for Read Address Channel
grach_reg_slice: IF (C_RACH_TYPE = 1) GENERATE
rach_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => C_REG_SLICE_MODE_RACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rach_din,
S_VALID => S_AXI_ARVALID,
S_READY => S_AXI_ARREADY,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE grach_reg_slice;
grdch2: IF (C_RDCH_TYPE = 0) GENERATE
SIGNAL rdch_we : STD_LOGIC := '0';
BEGIN
rdch_we <= rdch_wr_en WHEN (C_HAS_MASTER_CE = 0) ELSE rdch_wr_en AND M_ACLK_EN;
rdch_re <= rdch_rd_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rdch_rd_en AND S_ACLK_EN;
axi_rdch : fifo_generator_v13_0_1_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 2 OR C_IMPLEMENTATION_TYPE_RDCH = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 11 OR C_IMPLEMENTATION_TYPE_RDCH = 12),2,6)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RDCH,
C_WR_DEPTH => C_WR_DEPTH_RDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_RDCH,
C_RD_DEPTH => C_WR_DEPTH_RDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH,
C_USE_ECC => C_USE_ECC_RDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_RDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rdch_we,
RD_EN => rdch_re,
PROG_FULL_THRESH => AXI_R_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_R_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_R_INJECTDBITERR,
INJECTSBITERR => AXI_R_INJECTSBITERR,
DIN => rdch_din,
DOUT => rdch_dout,
FULL => rdch_full,
EMPTY => rdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_R_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_R_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_r_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_r_underflow_i,
DATA_COUNT => AXI_R_DATA_COUNT,
RD_DATA_COUNT => AXI_R_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_R_WR_DATA_COUNT,
SBITERR => AXI_R_SBITERR,
DBITERR => AXI_R_DBITERR,
WR_RST_BUSY => wr_rst_busy_rdch,
RD_RST_BUSY => rd_rst_busy_rdch,
WR_RST_I_OUT => OPEN,
RD_RST_I_OUT => OPEN
);
rdch_s_axi_rvalid <= NOT rdch_empty;
g8s_rdch_rdy: IF (IS_8SERIES = 1) GENERATE
g8s_bi_rdch_rdy: IF (C_IMPLEMENTATION_TYPE_RDCH = 5 OR C_IMPLEMENTATION_TYPE_RDCH = 13) GENERATE
rdch_m_axi_rready <= NOT (rdch_full OR wr_rst_busy_rdch);
END GENERATE g8s_bi_rdch_rdy;
g8s_nbi_rdch_rdy: IF (NOT (C_IMPLEMENTATION_TYPE_RDCH = 5 OR C_IMPLEMENTATION_TYPE_RDCH = 13)) GENERATE
rdch_m_axi_rready <= NOT (rdch_full);
END GENERATE g8s_nbi_rdch_rdy;
END GENERATE g8s_rdch_rdy;
g7s_rdch_rdy: IF (IS_8SERIES = 0) GENERATE
rdch_m_axi_rready <= NOT (rdch_full);
END GENERATE g7s_rdch_rdy;
S_AXI_RVALID <= rdch_s_axi_rvalid;
M_AXI_RREADY <= rdch_m_axi_rready;
gaxi_rd_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_R_UNDERFLOW <= axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf2;
gaxi_rd_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_R_OVERFLOW <= axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of2;
END GENERATE grdch2;
-- Register Slice for Read Data Channel
grdch_reg_slice: IF (C_RDCH_TYPE = 1) GENERATE
rdch_reg_slice: fifo_generator_v13_0_1_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_RDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rdch_din,
S_VALID => M_AXI_RVALID,
S_READY => M_AXI_RREADY,
-- Master side
M_PAYLOAD_DATA => rdch_dout,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY
);
END GENERATE grdch_reg_slice;
gaxi_rd_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_rd_underflow_i <= axi_ar_underflow_i OR axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf3;
gaxi_rd_ch_of3: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_rd_overflow_i <= axi_ar_overflow_i OR axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of3;
gaxi_pkt_fifo_rd: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL rd_burst_length : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_free_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_committed_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
SIGNAL rdch_rd_ok : STD_LOGIC := '0';
SIGNAL accept_next_pkt : STD_LOGIC := '0';
SIGNAL decrement_val : INTEGER := 0;
BEGIN
rd_burst_length <= ('0' & rach_dout_pkt(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET)) + conv_std_logic_vector(1,9);
accept_next_pkt <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
rdch_rd_ok <= rdch_re AND rdch_s_axi_rvalid;
arvalid_en <= '1' WHEN (rd_fifo_free_space >= rd_burst_length) ELSE '0';
gaxi_mm_cc_pkt_rd: IF (C_COMMON_CLOCK = 1) GENERATE
rd_fifo_free_space <= conv_std_logic_vector(C_WR_DEPTH_RDCH-conv_integer(rd_fifo_committed_space),C_WR_PNTR_WIDTH_RDCH+1);
decrement_val <= 1 WHEN (rdch_rd_ok = '1') ELSE 0;
proc_rd_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
rd_fifo_committed_space <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (accept_next_pkt = '1') THEN
-- Subtract 1 if read happens on read data FIFO while adding ARLEN
rd_fifo_committed_space <= rd_fifo_committed_space + conv_std_logic_vector((conv_integer(rd_burst_length) - decrement_val), C_WR_PNTR_WIDTH_RDCH+1);
ELSIF (rdch_rd_ok = '1') THEN
-- Subtract 1 whenever read happens on read data FIFO
rd_fifo_committed_space <= rd_fifo_committed_space - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_RDCH+1);
END IF;
END IF;
END PROCESS proc_rd_txn_cnt;
END GENERATE gaxi_mm_cc_pkt_rd;
END GENERATE gaxi_pkt_fifo_rd;
END GENERATE grdch;
gaxi_comm_uf: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
grdwr_uf1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_wr_underflow_i OR axi_rd_underflow_i;
END GENERATE grdwr_uf1;
grdwr_uf2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
UNDERFLOW <= axi_wr_underflow_i;
END GENERATE grdwr_uf2;
grdwr_uf3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_rd_underflow_i;
END GENERATE grdwr_uf3;
END GENERATE gaxi_comm_uf;
gaxi_comm_of: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
grdwr_of1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_wr_overflow_i OR axi_rd_overflow_i;
END GENERATE grdwr_of1;
grdwr_of2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
OVERFLOW <= axi_wr_overflow_i;
END GENERATE grdwr_of2;
grdwr_of3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_rd_overflow_i;
END GENERATE grdwr_of3;
END GENERATE gaxi_comm_of;
END GENERATE gaxifull;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Pass Through Logic or Wiring Logic
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxi_pass_through: IF (C_WACH_TYPE = 2 OR C_WDCH_TYPE = 2 OR C_WRCH_TYPE = 2 OR
C_RACH_TYPE = 2 OR C_RDCH_TYPE = 2 OR C_AXIS_TYPE = 2) GENERATE
gwach_pass_through: IF (C_WACH_TYPE = 2) GENERATE -- Wiring logic for Write Address Channel
M_AXI_AWID <= S_AXI_AWID;
M_AXI_AWADDR <= S_AXI_AWADDR;
M_AXI_AWLEN <= S_AXI_AWLEN;
M_AXI_AWSIZE <= S_AXI_AWSIZE;
M_AXI_AWBURST <= S_AXI_AWBURST;
M_AXI_AWLOCK <= S_AXI_AWLOCK;
M_AXI_AWCACHE <= S_AXI_AWCACHE;
M_AXI_AWPROT <= S_AXI_AWPROT;
M_AXI_AWQOS <= S_AXI_AWQOS;
M_AXI_AWREGION <= S_AXI_AWREGION;
M_AXI_AWUSER <= S_AXI_AWUSER;
S_AXI_AWREADY <= M_AXI_AWREADY;
M_AXI_AWVALID <= S_AXI_AWVALID;
END GENERATE gwach_pass_through;
-- Wiring logic for Write Data Channel
gwdch_pass_through: IF (C_WDCH_TYPE = 2) GENERATE
M_AXI_WID <= S_AXI_WID;
M_AXI_WDATA <= S_AXI_WDATA;
M_AXI_WSTRB <= S_AXI_WSTRB;
M_AXI_WLAST <= S_AXI_WLAST;
M_AXI_WUSER <= S_AXI_WUSER;
S_AXI_WREADY <= M_AXI_WREADY;
M_AXI_WVALID <= S_AXI_WVALID;
END GENERATE gwdch_pass_through;
-- Wiring logic for Write Response Channel
gwrch_pass_through: IF (C_WRCH_TYPE = 2) GENERATE
S_AXI_BID <= M_AXI_BID;
S_AXI_BRESP <= M_AXI_BRESP;
S_AXI_BUSER <= M_AXI_BUSER;
M_AXI_BREADY <= S_AXI_BREADY;
S_AXI_BVALID <= M_AXI_BVALID;
END GENERATE gwrch_pass_through;
-- Pass Through Logic for Read Channel
grach_pass_through: IF (C_RACH_TYPE = 2) GENERATE -- Wiring logic for Read Address Channel
M_AXI_ARID <= S_AXI_ARID;
M_AXI_ARADDR <= S_AXI_ARADDR;
M_AXI_ARLEN <= S_AXI_ARLEN;
M_AXI_ARSIZE <= S_AXI_ARSIZE;
M_AXI_ARBURST <= S_AXI_ARBURST;
M_AXI_ARLOCK <= S_AXI_ARLOCK;
M_AXI_ARCACHE <= S_AXI_ARCACHE;
M_AXI_ARPROT <= S_AXI_ARPROT;
M_AXI_ARQOS <= S_AXI_ARQOS;
M_AXI_ARREGION <= S_AXI_ARREGION;
M_AXI_ARUSER <= S_AXI_ARUSER;
S_AXI_ARREADY <= M_AXI_ARREADY;
M_AXI_ARVALID <= S_AXI_ARVALID;
END GENERATE grach_pass_through;
grdch_pass_through: IF (C_RDCH_TYPE = 2) GENERATE -- Wiring logic for Read Data Channel
S_AXI_RID <= M_AXI_RID;
S_AXI_RLAST <= M_AXI_RLAST;
S_AXI_RUSER <= M_AXI_RUSER;
S_AXI_RDATA <= M_AXI_RDATA;
S_AXI_RRESP <= M_AXI_RRESP;
S_AXI_RVALID <= M_AXI_RVALID;
M_AXI_RREADY <= S_AXI_RREADY;
END GENERATE grdch_pass_through;
gaxis_pass_through: IF (C_AXIS_TYPE = 2) GENERATE -- Wiring logic for AXI Streaming
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TKEEP <= S_AXIS_TKEEP;
M_AXIS_TID <= S_AXIS_TID;
M_AXIS_TDEST <= S_AXIS_TDEST;
M_AXIS_TUSER <= S_AXIS_TUSER;
M_AXIS_TLAST <= S_AXIS_TLAST;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TVALID <= S_AXIS_TVALID;
END GENERATE gaxis_pass_through;
END GENERATE gaxi_pass_through;
END behavioral;
|
mit
|
656612ad310e694ab3255e5d67c9cd4a
| 0.474267 | 3.714847 | false | false | false | false |
mitchsm/nvc
|
test/sem/record.vhd
| 3 | 2,780 |
package p is
type r1 is record -- OK
x : integer;
y : integer;
end record;
type r2 is record -- Error
x, x : integer;
end record;
type r3;
type r3 is record -- Error
x : r3;
end record;
type r4 is record
x, y, z : integer;
end record;
type r5 is record
x : r1;
y : integer;
end record;
type r1_vec is array (integer range <>) of r1;
type r6 is record
x : r1_vec; -- Error
end record;
end package;
package body p is
procedure p1 is
variable v1 : r1 := (1, 2);
variable v2 : r4 := (1, 2); -- Error
variable v3 : r1 := (1, v1); -- Error
variable v4 : r1 := (x => 1, y => 2);
variable v5 : r1 := (x => 1); -- Error
variable v6 : r1 := (x => 1, y => 2, q => 1); -- Error
variable v7 : r1 := (x => 1, y => v1); -- Error
variable v8 : r1 := (others => 9);
variable v9 : r1 := (x => 1, others => 2);
variable v10 : r1 := (x => 1, x => 2, y => 3); -- Error
variable v11 : r1 := (1, x => 4, y => 2); -- Error
variable v12 : r1 := (1, y => 4);
variable v13 : r1;
begin
end procedure;
procedure p2 is
variable v1 : r1;
variable v2 : r5;
begin
v1.x := 2;
v1.y := v1.x + 5;
v2.x.x := 3;
end procedure;
procedure p3 is
variable a1 : r1_vec; -- Error
begin
end procedure;
procedure p4 is
variable a2 : r1_vec(0 to 3); -- OK
begin
a2(2).x := 5; -- OK
a2(1).f := 2; -- Error
a2(0).x := a2(1).y; -- OK
end procedure;
procedure p5 is
subtype r1_sub is r1; -- OK
variable a : r1_sub; -- OK
begin
a.x := 5; -- OK
a.y := a.x + 2; -- OK
a.z := 2; -- Error
end procedure;
procedure p6 is
subtype r1_bad is r1(1 to 3); -- Error
begin
end procedure;
procedure p7 is
type rec is record
vec : bit_vector(1 to 3);
end record;
variable a : rec;
begin
assert a.vec'length = 3; -- OK
end procedure;
procedure p8 is
function make_r1 return r1 is
begin
return (x => 1, y => 2);
end function;
begin
assert make_r1.x = 1; -- OK
assert make_r1.z = 2; -- Error
end procedure;
type int_file is file of integer;
type r7 is record
a : int_file;
end record;
end package body;
|
gpl-3.0
|
3255c1140ef6820468f86776cb344be1
| 0.426259 | 3.501259 | false | false | false | false |
mitchsm/nvc
|
test/regress/attr2.vhd
| 5 | 617 |
entity attr2 is
end entity;
architecture test of attr2 is
type int3d is array (natural range <>,
natural range <>,
natural range <>) of integer;
procedure foo(x : in int3d) is
begin
assert x'length(1) = 2;
assert x'length(2) = 2;
assert x'length(3) = 10;
end procedure;
begin
process is
variable v : int3d(1 to 2, 1 downto 0, 10 to 19);
begin
assert v'length(1) = 2;
assert v'length(2) = 2;
assert v'length(3) = 10;
foo(v);
wait;
end process;
end architecture;
|
gpl-3.0
|
cd48a2f2f933fb0e6c209f20cdd7a604
| 0.523501 | 3.672619 | false | false | false | false |
mitchsm/nvc
|
test/regress/concat1.vhd
| 5 | 696 |
entity concat1 is
end entity;
architecture test of concat1 is
type int_array is array (integer range <>) of integer;
begin
-- See LRM 93 section 9.2.5
process is
variable x : int_array(1 to 5);
variable y : int_array(1 to 2);
variable z : int_array(1 to 3);
variable s : string(1 to 5);
begin
y := (1, 2);
z := (3, 4, 5);
x := y & z;
assert x = (1, 2, 3, 4, 5);
s := "ab" & "cde";
assert s = "abcde";
z := 0 & y;
assert z = (0, 1, 2);
z := y & 3;
assert z = (1, 2, 3);
y := 8 & 9;
assert y = (8, 9);
wait;
end process;
end architecture;
|
gpl-3.0
|
3c900022388fd900c261585ff0ab50cf
| 0.45546 | 3.222222 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/axi_lite_adapter.vhd
| 1 | 63,260 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : axi_lite_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-12-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-08-05 2.0 pvk updated
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.cdc_sync;
entity axi_lite_adapter is
generic (
-- System generics:
C_FAMILY : string := "virtex7"; -- Xilinx FPGA family
-- AXI generics:
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_MAX_N_IARGS : integer;
C_MAX_N_OARGS : integer;
C_MAX_MB_DEPTH : integer;
C_N_INPUT_ARGS : integer;
C_N_OUTPUT_ARGS : integer;
C_PRMRY_IS_ACLK_ASYNC : integer;
C_MTBF_STAGES : integer;
C_MAX_ARG_AWIDTH : integer;
C_MAX_N_ISCALARS : integer;
C_N_INOUT_SCALARS : integer;
C_MAX_N_IOSCALARS : integer;
C_N_INPUT_SCALARS : integer;
C_MAX_N_OSCALARS : integer;
C_N_OUTPUT_SCALARS : integer;
C_MAX_SCALAR_DWIDTH : integer;
C_M_AXIS_TDEST_WIDTH : integer);
port (
-- AXI LITE interface signals:
S_AXI_ACLK : in std_logic; -- AXI Clock
S_AXI_ARESETN : in std_logic; -- AXI Reset, active low
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- AXI Write address
S_AXI_AWVALID : in std_logic; -- Write address valid
S_AXI_AWREADY : out std_logic; -- Write address ready
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Write data
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); -- Write strobes
S_AXI_WVALID : in std_logic; -- Write valid
S_AXI_WREADY : out std_logic; -- Write ready
S_AXI_BRESP : out std_logic_vector(1 downto 0); -- Write response
S_AXI_BVALID : out std_logic; -- Write response valid
S_AXI_BREADY : in std_logic; -- Response ready
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- Read address
S_AXI_ARVALID : in std_logic; -- Read address valid
S_AXI_ARREADY : out std_logic; -- Read address ready
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Read data
S_AXI_RRESP : out std_logic_vector(1 downto 0); -- Read response
S_AXI_RVALID : out std_logic; -- Read valid
S_AXI_RREADY : in std_logic; -- Read ready
--- App. ports
ap_rst : out std_logic; -- Read valid
-- Command input port:
host_cmd_data : out std_logic_vector(31 downto 0);
host_cmd_we : out std_logic;
host_cmd_rdy : in std_logic;
host_complete_re : out std_logic;
host_cmd_error : in std_logic;
-- AP core status signals:
status_ap_start : in std_logic;
status_ap_done : in std_logic;
status_ap_idle : in std_logic;
status_ap_ready : in std_logic;
status_ap_start_clr : out std_logic;
status_ap_done_clr : out std_logic;
status_ap_idle_clr : out std_logic;
status_ap_ready_clr : out std_logic;
-- Input arguments management:
host_iarg_rst : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
iarg_rqt_enable : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_empty : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_full : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_used : in std_logic_vector(C_MAX_N_IARGS*4-1 downto 0);
status_iarg_n_words : in std_logic_vector(C_MAX_N_IARGS*(C_MAX_ARG_AWIDTH+1)-1 downto 0);
-- Output arguments management:
host_oarg_rst : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
oarg_rqt_enable : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
oarg_sw_length : out std_logic_vector(31 downto 0);
oarg_sw_length_m2s : out std_logic_vector(31 downto 0);
oarg_sw_length_we : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
oarg_use_sw_length : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
host_oarg_tdest : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
status_oarg_empty : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_full : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_used : in std_logic_vector(C_MAX_N_OARGS*4-1 downto 0);
-- Input scalar management:
host_iscalar_rst : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
host_iscalar_dout : out std_logic_vector(31 downto 0);
host_iscalar_we : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
host_iscalar_rdy : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_empty : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_full : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_used : in std_logic_vector((C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS)*4-1 downto 0);
-- Output scalar management:
host_oscalar_rst : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
host_oscalar_din : in std_logic_vector((C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS)*C_MAX_SCALAR_DWIDTH-1 downto 0);
host_oscalar_re : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
host_oscalar_rdy : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_empty : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_full : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_used : in std_logic_vector((C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS)*4-1 downto 0);
dbg_iarg_stream_nwords : in std_logic_vector(C_MAX_N_IARGS*16-1 downto 0);
dbg_iarg_buffer_nwords : in std_logic_vector(C_MAX_N_IARGS*16-1 downto 0);
dbg_oarg_stream_nwords : in std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
dbg_oarg_buffer_nwords : in std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
iscalar_rqt_enable : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
oscalar_rqt_enable : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
---
interrupt : out std_logic);
attribute SIGIS : string;
attribute SIGIS of S_AXI_ACLK : signal is "CLK";
attribute SIGIS of S_AXI_ARESETN : signal is "RST";
end entity;
architecture rtl of axi_lite_adapter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
constant DATA_WIDTH : integer := 32;
constant STRB_WIDTH : integer := (C_S_AXI_DATA_WIDTH/8);
constant AXI_RESP_OKAY : std_logic_vector(1 downto 0) := "00";
constant AXI_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
constant AXI_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
constant AXI_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
function ext_32 (
value : std_logic_vector;
width : natural := 32)
return std_logic_vector is
constant N : integer := value'length;
variable ret : std_logic_vector(width-1 downto 0);
begin
ret := (others => '0');
ret(N-1 downto 0) := value;
return ret;
end function ext_32;
function sext_32 (
value : std_logic_vector;
width : natural := 32)
return std_logic_vector is
constant N : integer := value'length;
alias val_dn : std_logic_vector (N-1 downto 0) is value;
variable ret : std_logic_vector(width-1 downto 0);
begin
ret(N-1 downto 0) := val_dn;
if(N < 32) then
ret(31 downto N) := (others => val_dn(N-1));
end if;
return ret;
end function sext_32;
signal axi_rst : std_logic;
signal ap_rst_fb : std_logic;
signal axi_rst1 : std_logic;
signal ap_rst_i : std_logic;
signal axi_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- AXI Write address
signal wr_data_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--------------------------------------------------
-- We use banks of 16 registers (32 bits, 4 bytes):
constant BANK_ADDR_WIDTH : integer := 4; -- Up to 16 banks can be used.
constant BANK_ADDR_LSB : integer := log2(16*4);
constant BANK_ADDR_MSB : integer := BANK_ADDR_LSB+BANK_ADDR_WIDTH-1;
constant GP_REGS_BANK_ADDR : integer := 0;
constant GP_REGS_BANK1_ADDR : integer := 1;
constant ISCALAR_BANK_ADDR : integer := 2;
constant OSCALAR_BANK_ADDR : integer := 3;
constant IARG_STATUS_BANK_ADDR : integer := 4;
constant OARG_STATUS_BANK_ADDR : integer := 5;
constant ISCALAR_STATUS_BANK_ADDR : integer := 6;
constant OSCALAR_STATUS_BANK_ADDR : integer := 7;
constant OARG_LENGTH_BANK_ADDR : integer := 8;
constant OARG_TDEST_BANK_ADDR : integer := 9;
constant CTRL_REG_INDEX : integer := 0;
constant STATUS_REG_INDEX : integer := 1;
constant IARG_RST_REG_INDEX : integer := 2;
constant OARG_RST_REG_INDEX : integer := 3;
constant IARG_RQT_ENABLE_REG_INDEX : integer := 4;
constant OARG_RQT_ENABLE_REG_INDEX : integer := 5;
constant COMMAND_REG_INDEX : integer := 10;
constant COMPLETE_REG_INDEX : integer := 11;
constant INT_ENABLE_REG_INDEX : integer := 12;
constant INT_FLAG_REG_INDEX : integer := 13;
constant OARG_LENGTH_MODE_REG_INDEX : integer := 15;
constant ISCALAR_RST_REG_INDEX : integer := 16;
constant OSCALAR_RST_REG_INDEX : integer := 17;
constant ISCALAR_RQT_ENABLE_REG_INDEX : integer := 18;
constant OSCALAR_RQT_ENABLE_REG_INDEX : integer := 19;
constant BANK1_INDEX : integer := 16;
signal gp_bank : std_logic; -- bank 0
signal gp_bank1 : std_logic; -- bank 1
signal iscalar_bank : std_logic; -- bank 2
signal oscalar_bank : std_logic; -- bank 3
signal iarg_status_bank : std_logic; -- bank 4
signal oarg_status_bank : std_logic; -- bank 5
signal iscalar_status_bank : std_logic; -- bank 6
signal oscalar_status_bank : std_logic; -- bank 7
signal oarg_length_bank : std_logic; -- bank 8
signal oarg_tdest_bank : std_logic; -- bank 9
signal mux_gp_regs : std_logic_vector(31 downto 0);
signal mux_oscalar_data : std_logic_vector(31 downto 0);
signal mux_iarg_status : std_logic_vector(31 downto 0);
signal mux_oarg_status : std_logic_vector(31 downto 0);
signal mux_iscalar_status : std_logic_vector(31 downto 0);
signal mux_oscalar_status : std_logic_vector(31 downto 0);
signal mux_oarg_tdest_regs : std_logic_vector(31 downto 0);
signal rd_bank_addr : std_logic_vector(BANK_ADDR_WIDTH-1 downto 0);
constant REGS_ADDR_WIDTH : integer := 4; -- Inner address width.
constant N_REGS : integer := 2**REGS_ADDR_WIDTH;
signal reg_sel : std_logic_vector(N_REGS-1 downto 0);
signal rd_reg_addr : std_logic_vector(REGS_ADDR_WIDTH-1 downto 0);
signal ctrl_reg : std_logic_vector(31 downto 0);
signal status_reg : std_logic_vector(31 downto 0);
signal ap_iarg_rst_reg : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_oarg_rst_reg : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal iarg_rqt_enable_reg : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal oarg_rqt_enable_reg : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal oarg_length_mode_reg : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal reg_sel1 : std_logic_vector(N_REGS-1 downto 0);
signal iscalar_rst_reg : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal oscalar_rst_reg : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
signal iscalar_rqt_enable_reg : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal oscalar_rqt_enable_reg : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
------------------------------------------------
type state_type is (
-- pragma translate_off
stop,
-- pragma translate_on
idle,
read_regs,
write_regs,
send_resp);
signal state : state_type;
signal wr_addr_rdy : std_logic;
signal rd_addr_rdy : std_logic;
signal wr_resp_vld : std_logic;
signal wr_data_rdy : std_logic;
signal rd_data_vld : std_logic;
signal rd_data_ce : std_logic;
signal rd_data : std_logic_vector(31 downto 0);
signal gp_reg_start : std_logic;
signal rd_start : std_logic;
signal wr_start : std_logic;
signal access_start : std_logic;
signal gp_reg_start1 : std_logic;
--------------------------------------------------------------------
-- pragma translate_off
signal mem_rd : std_logic;
signal mem_wr : std_logic;
-- pragma translate_on
signal scalar_reg_start : std_logic;
signal glb_int_en : std_logic;
---------------------
-- INTERRUPT REGs: --
---------------------
constant N_INTS : integer := 8;
signal int_enable_reg : std_logic_vector(N_INTS-1 downto 0);
signal int_flag_reg : std_logic_vector(N_INTS-1 downto 0);
signal int_rqt : std_logic_vector(N_INTS-1 downto 0);
---------------------
-- Syncrhpnoaer signals
---------------------
signal status_iarg_empty_sync : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal oarg_sw_length_we_event : std_logic;
signal oarg_sw_length_we_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal host_ioscalar_re_i : std_logic_vector(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS);
signal host_oscalar_re_i : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF axi_rst1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi_rst : SIGNAL IS "true";
begin
----------------------
--- status_iarg_empty Synchronizer
----------------------
EN_STRM_TO_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
XD_IARG_RQT_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2 --C_MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => status_iarg_empty,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => status_iarg_empty_sync
);
end generate EN_STRM_TO_LITE_SYNC_GEN;
NO_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_iarg_empty_sync <= status_iarg_empty;
end generate NO_SYNC_GEN;
----------------------
--- status_iarg_empty Synchronizer
----------------------
--axi_rst <= not(S_AXI_ARESETN);
prd1: PROCESS (S_AXI_ACLK, S_AXI_ARESETN)
BEGIN
-- Register Stage #1
IF (S_AXI_ARESETN = '0') THEN
axi_rst1 <= '1';
axi_rst <= '1';
ELSIF (S_AXI_ACLK'event and S_AXI_ACLK = '1') THEN
axi_rst1 <= '0';
axi_rst <= axi_rst1;
END IF;
END PROCESS prd1;
S_AXI_AWREADY <= wr_addr_rdy;
S_AXI_ARREADY <= rd_addr_rdy;
S_AXI_WREADY <= wr_data_rdy;
S_AXI_BVALID <= wr_resp_vld;
S_AXI_BRESP <= AXI_RESP_OKAY;
S_AXI_RDATA <= rd_data;
S_AXI_RVALID <= rd_data_vld;
S_AXI_RRESP <= AXI_RESP_OKAY;
-------------------------------------------
axi_addr <= S_AXI_ARADDR when (S_AXI_ARVALID = '1') else S_AXI_AWADDR;
process(axi_addr)
variable int_addr : integer range 0 to (2**BANK_ADDR_WIDTH)-1;
begin
gp_bank <= '0';
gp_bank1 <= '0';
iscalar_bank <= '0';
oscalar_bank <= '0';
iarg_status_bank <= '0';
oarg_status_bank <= '0';
iscalar_status_bank <= '0';
oscalar_status_bank <= '0';
oarg_length_bank <= '0';
oarg_tdest_bank <= '0';
int_addr := to_integer(unsigned(axi_addr(BANK_ADDR_MSB downto BANK_ADDR_LSB)));
case int_addr is
when GP_REGS_BANK_ADDR => gp_bank <= '1';
when GP_REGS_BANK1_ADDR => gp_bank1 <= '1';
when ISCALAR_BANK_ADDR => iscalar_bank <= '1';
when OSCALAR_BANK_ADDR => oscalar_bank <= '1';
when IARG_STATUS_BANK_ADDR => iarg_status_bank <= '1';
when OARG_STATUS_BANK_ADDR => oarg_status_bank <= '1';
when ISCALAR_STATUS_BANK_ADDR => iscalar_status_bank <= '1';
when OSCALAR_STATUS_BANK_ADDR => oscalar_status_bank <= '1';
when OARG_LENGTH_BANK_ADDR => oarg_length_bank <= '1';
when OARG_TDEST_BANK_ADDR => oarg_tdest_bank <= '1';
when others =>
end case;
end process;
process(S_AXI_ACLK)
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+REGS_ADDR_WIDTH-1;
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(rd_start = '1') then
rd_reg_addr <= S_AXI_ARADDR(MSB downto LSB);
end if;
end if;
end process;
process(S_AXI_ACLK)
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(rd_start = '1') then
rd_bank_addr <= S_AXI_ARADDR(BANK_ADDR_MSB downto BANK_ADDR_LSB);
end if;
end if;
end process;
process(S_AXI_ACLK, axi_rst)
begin
if(axi_rst = '1') then
state <= idle;
wr_resp_vld <= '0';
rd_data_vld <= '0';
rd_addr_rdy <= '0';
wr_addr_rdy <= '0';
wr_data_rdy <= '0';
-- pragma translate_off
mem_rd <= '0';
mem_wr <= '0';
-- pragma translate_on
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
rd_addr_rdy <= '0';
wr_addr_rdy <= '0';
wr_data_rdy <= '0';
-- pragma translate_off
mem_rd <= '0';
mem_wr <= '0';
-- pragma translate_on
case state is
when idle =>
if(S_AXI_ARVALID = '1') then
state <= read_regs;
rd_addr_rdy <= '1';
elsif(S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- During write accesses it's waited until both both address and
-- write data are stables.
state <= write_regs;
wr_addr_rdy <= '1';
wr_data_rdy <= '1';
end if;
when read_regs =>
state <= send_resp;
rd_data_vld <= '1';
when write_regs =>
state <= send_resp;
wr_resp_vld <= '1';
when send_resp =>
if ((wr_resp_vld = '1' and S_AXI_BREADY = '1') or
(rd_data_vld = '1' and S_AXI_RREADY = '1')) then
wr_resp_vld <= '0';
rd_data_vld <= '0';
state <= idle;
end if;
when others =>
end case;
end if;
end process;
process(state, gp_bank, gp_bank1, S_AXI_ARVALID, S_AXI_AWVALID, S_AXI_WVALID)
begin
rd_data_ce <= '0';
gp_reg_start <= '0';
gp_reg_start1 <= '0';
scalar_reg_start <= '0';
rd_start <= '0';
wr_start <= '0';
access_start <= '0';
case state is
when idle =>
rd_start <= S_AXI_ARVALID;
wr_start <= S_AXI_AWVALID and S_AXI_WVALID;
access_start <= S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID);
gp_reg_start <= gp_bank and (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID));
gp_reg_start1 <= gp_bank1 and (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID));
when read_regs =>
rd_data_ce <= '1';
when write_regs =>
when send_resp =>
when others =>
end case;
end process;
--------------------
-- INPUT DATAPATH --
--------------------
process(S_AXI_ACLK)
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
wr_data_i <= S_AXI_WDATA;
end if;
end process;
-----------------------------------------
--- BANK 0: GENERAL PURPOSE REGISTERS ---
-----------------------------------------
-- Selection signal generation for inner registers:
process(S_AXI_ACLK)
variable offset : unsigned(REGS_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+REGS_ADDR_WIDTH-1;
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(axi_rst = '1' or wr_data_rdy = '1' or rd_data_vld = '1') then
reg_sel <= (others => '0');
elsif(gp_reg_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in reg_sel'range loop
if(offset = i) then
reg_sel(i) <= '1';
else
reg_sel(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
---------------------------------
-- CONTROL REGISTER (INDEX 0) --
---------------------------------
process(S_AXI_ACLK, axi_rst)
begin
if(axi_rst = '1') then
ctrl_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(CTRL_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to STRB_WIDTH-1 loop
if(S_AXI_WSTRB(i) = '1') then
ctrl_reg(8*(i+1)-1 downto 8*i) <= S_AXI_WDATA(8*(i+1)-1 downto 8*i);
end if;
end loop;
end if;
end if;
end process;
ap_rst_i <= ctrl_reg(0) or axi_rst;
glb_int_en <= ctrl_reg(1);
process(S_AXI_ACLK, axi_rst)
begin
if(axi_rst = '1') then
ap_rst <= '1';
ap_rst_fb <= '1';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
ap_rst <= ap_rst_i;
ap_rst_fb <= ap_rst_i;
end if;
end process;
--------------------------------
-- STATUS REGISTER (INDEX 1) --
--------------------------------
status_reg(0) <= status_ap_start;
status_reg(1) <= status_ap_done;
status_reg(2) <= status_ap_idle;
status_reg(3) <= status_ap_ready;
status_reg(31 downto 4) <= (others => '0');
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
status_ap_start_clr <= '0';
status_ap_done_clr <= '0';
status_ap_idle_clr <= '0';
status_ap_ready_clr <= '0';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
status_ap_start_clr <= reg_sel(STATUS_REG_INDEX) and wr_data_rdy and S_AXI_WSTRB(0) and S_AXI_WDATA(0);
status_ap_done_clr <= reg_sel(STATUS_REG_INDEX) and wr_data_rdy and S_AXI_WSTRB(0) and S_AXI_WDATA(1);
status_ap_idle_clr <= reg_sel(STATUS_REG_INDEX) and wr_data_rdy and S_AXI_WSTRB(0) and S_AXI_WDATA(2);
status_ap_ready_clr <= reg_sel(STATUS_REG_INDEX) and wr_data_rdy and S_AXI_WSTRB(0) and S_AXI_WDATA(3);
end if;
end process;
-----------------------------------------------------
-- INPUT ARG MULTIBUFFER RESET REGISTER (INDEX 2) --
-----------------------------------------------------
IARGS_RST_GEN : if (C_N_INPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_INPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(IARG_RST_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
host_iarg_rst <= (others => '0');
ap_iarg_rst_reg <= (others => '0');
host_iarg_rst(reg'range) <= reg;
ap_iarg_rst_reg(reg'range) <= reg;
end process;
end generate IARGS_RST_GEN;
NO_IARGS_RST_GEN : if (C_N_INPUT_ARGS = 0) generate
begin
host_iarg_rst <= (others => '0');
ap_iarg_rst_reg <= (others => '0');
end generate NO_IARGS_RST_GEN;
------------------------------------------------------
-- OUTPUT ARG MULTIBUFFER RESET REGISTER (INDEX 3) --
------------------------------------------------------
OARGS_RST_GEN : if (C_N_OUTPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_OUTPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(OARG_RST_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
host_oarg_rst <= (others => '0');
ap_oarg_rst_reg <= (others => '0');
host_oarg_rst(reg'range) <= reg;
ap_oarg_rst_reg(reg'range) <= reg;
end process;
end generate OARGS_RST_GEN;
NO_OARGS_RST_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
host_oarg_rst <= (others => '0');
ap_oarg_rst_reg <= (others => '0');
end generate NO_OARGS_RST_GEN;
--------------------------------------------------
-- INPUT ARG REQUEST ENABLE REGISTER (INDEX 4) --
--------------------------------------------------
IARG_RQT_ENABLE_GEN : if (C_N_INPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_INPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(IARG_RQT_ENABLE_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
iarg_rqt_enable <= (others => '0');
iarg_rqt_enable_reg <= (others => '0');
iarg_rqt_enable(reg'range) <= reg;
iarg_rqt_enable_reg(reg'range) <= reg;
end process;
end generate IARG_RQT_ENABLE_GEN;
NO_IARG_RQT_ENABLE_GEN : if (C_N_INPUT_ARGS = 0) generate
begin
iarg_rqt_enable <= (others => '0');
iarg_rqt_enable_reg <= (others => '0');
end generate NO_IARG_RQT_ENABLE_GEN;
---------------------------------------------------
-- OUTPUT ARG REQUEST ENABLE REGISTER (INDEX 5) --
---------------------------------------------------
OARG_RQT_ENABLE_GEN : if (C_N_OUTPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_OUTPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(OARG_RQT_ENABLE_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
oarg_rqt_enable <= (others => '0');
oarg_rqt_enable_reg <= (others => '0');
oarg_rqt_enable(reg'range) <= reg;
oarg_rqt_enable_reg(reg'range) <= reg;
end process;
end generate OARG_RQT_ENABLE_GEN;
NO_OARG_RQT_ENABLE_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
oarg_rqt_enable <= (others => '0');
oarg_rqt_enable_reg <= (others => '0');
end generate NO_OARG_RQT_ENABLE_GEN;
---------------------------------
-- COMMAND REGISTER (INDEX 10) --
---------------------------------
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
host_cmd_we <= '0';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
host_cmd_we <= reg_sel(COMMAND_REG_INDEX) and wr_data_rdy;
end if;
end process;
host_cmd_data <= wr_data_i;
-----------------------------------
-- COMPLETE REGISTER (INDEX 11) --
-----------------------------------
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
host_complete_re <= '0';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
host_complete_re <= reg_sel(COMPLETE_REG_INDEX) and rd_data_vld; -- ????
end if;
end process;
--------------------------
-- INTERRUPT MANAGEMENT --
--------------------------
------------------------------------------
-- INTERRUPT ENABLE REGISTER (INDEX 12) --
------------------------------------------
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
int_enable_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(INT_ENABLE_REG_INDEX) = '1' and wr_data_rdy = '1') then
int_enable_reg <= S_AXI_WDATA(N_INTS-1 downto 0);
end if;
end if;
end process;
-- Individual asigment for each interrupt source:
int_rqt(0) <= host_cmd_error;
int_rqt(N_INTS-1 downto 1) <= (others => '0');
----------------------------------------
-- INTERRUPT FLAG REGISTER (INDEX 13) --
----------------------------------------
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
int_flag_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(INT_FLAG_REG_INDEX) = '1' and wr_data_rdy = '1') then
int_flag_reg <= int_flag_reg and not(S_AXI_WDATA(N_INTS-1 downto 0));
else
int_flag_reg <= int_flag_reg or int_rqt;
end if;
end if;
end process;
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
interrupt <= '0';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
interrupt <= or_reduce(int_flag_reg and int_enable_reg) and glb_int_en;
end if;
end process;
-----------------------------------------
--- BANK 1: GENERAL PURPOSE REGISTERS ---
-----------------------------------------
-- Selection signal generation for inner registers:
process(S_AXI_ACLK)
variable offset : unsigned(REGS_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+REGS_ADDR_WIDTH-1;
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(ap_rst_fb = '1' or wr_data_rdy = '1' or rd_data_vld = '1') then
reg_sel1 <= (others => '0');
elsif(gp_reg_start1 = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in reg_sel1'range loop
if(offset = i) then
reg_sel1(i) <= '1';
else
reg_sel1(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
-------------------------------------------------
-- INPUT SCALAR FIFO RESET REGISTER (INDEX 16) --
-------------------------------------------------
ISCALAR_RST_GEN : if (C_N_INPUT_SCALARS > 0) generate
signal rst_reg : std_logic_vector(C_N_INPUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
rst_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(ISCALAR_RST_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INPUT_SCALARS-1 loop
rst_reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(rst_reg)
begin
host_iscalar_rst(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rst_reg(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
host_iscalar_rst(rst_reg'range) <= rst_reg;
iscalar_rst_reg(rst_reg'range) <= rst_reg;
end process;
end generate ISCALAR_RST_GEN;
NO_ISCALAR_RST_GEN : if (C_N_INPUT_SCALARS = 0) generate
begin
host_iscalar_rst(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rst_reg(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
end generate NO_ISCALAR_RST_GEN;
ISCALAR_IO_RST_GEN : if (C_N_INOUT_SCALARS > 0) generate
signal rst_reg : std_logic_vector(C_N_INOUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
rst_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(ISCALAR_RST_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INOUT_SCALARS-1 loop
rst_reg(i) <= S_AXI_WDATA(i+C_MAX_N_ISCALARS) and S_AXI_WSTRB((i+C_MAX_N_ISCALARS)/8);
end loop;
end if;
end if;
end process;
process(rst_reg)
begin
host_iscalar_rst(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rst_reg(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
host_iscalar_rst(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) <= rst_reg;
iscalar_rst_reg(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) <= rst_reg;
end process;
end generate ISCALAR_IO_RST_GEN;
NO_ISCALAR_IO_RST_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
host_iscalar_rst(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rst_reg(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
end generate NO_ISCALAR_IO_RST_GEN;
--------------------------------------------------
-- OUTPUT SCALAR FIFO RESET REGISTER (INDEX 17) --
--------------------------------------------------
OSCALAR_RST_GEN : if (C_N_OUTPUT_SCALARS > 0) generate
signal rst_reg : std_logic_vector(C_N_OUTPUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
rst_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(OSCALAR_RST_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_SCALARS-1 loop
rst_reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(rst_reg)
begin
host_oscalar_rst(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rst_reg(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
host_oscalar_rst(rst_reg'range) <= rst_reg;
oscalar_rst_reg(rst_reg'range) <= rst_reg;
end process;
end generate OSCALAR_RST_GEN;
NO_OSCALAR_RST_GEN : if (C_N_OUTPUT_SCALARS = 0) generate
begin
host_oscalar_rst(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rst_reg(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
end generate NO_OSCALAR_RST_GEN;
OSCALAR_IO_RST_GEN : if (C_N_INOUT_SCALARS > 0) generate
signal os_rst_reg : std_logic_vector(C_N_INOUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
os_rst_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(OSCALAR_RST_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INOUT_SCALARS-1 loop
os_rst_reg(i) <= S_AXI_WDATA(i+C_MAX_N_OSCALARS) and S_AXI_WSTRB((i+C_MAX_N_OSCALARS)/8);
end loop;
end if;
end if;
end process;
process(os_rst_reg)
begin
host_oscalar_rst(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rst_reg(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
host_oscalar_rst(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= os_rst_reg;
oscalar_rst_reg(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= os_rst_reg;
end process;
end generate OSCALAR_IO_RST_GEN;
NO_OSCALAR_IO_RST_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
host_oscalar_rst(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rst_reg(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
end generate NO_OSCALAR_IO_RST_GEN;
-----------------------------------------------------
-- INPUT SCALAR REQUEST ENABLE REGISTER (INDEX 18) --
-----------------------------------------------------
ISCALAR_RQT_ENABLE_GEN : if (C_N_INPUT_SCALARS > 0) generate
signal reg : std_logic_vector(C_N_INPUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(ISCALAR_RQT_ENABLE_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INPUT_SCALARS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
iscalar_rqt_enable(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rqt_enable(reg'range) <= reg;
iscalar_rqt_enable_reg(reg'range) <= reg;
end process;
end generate ISCALAR_RQT_ENABLE_GEN;
NO_ISCALAR_RQT_ENABLE_GEN : if (C_N_INPUT_SCALARS = 0) generate
begin
iscalar_rqt_enable(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
end generate NO_ISCALAR_RQT_ENABLE_GEN;
ISCALAR_IO_RQT_ENABLE_GEN : if (C_N_INOUT_SCALARS > 0) generate
signal rqt_reg : std_logic_vector(C_N_INOUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
rqt_reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(ISCALAR_RQT_ENABLE_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INOUT_SCALARS-1 loop
rqt_reg(i) <= S_AXI_WDATA(i+C_MAX_N_ISCALARS) and S_AXI_WSTRB((i+C_MAX_N_ISCALARS)/8);
end loop;
end if;
end if;
end process;
process(rqt_reg)
begin
iscalar_rqt_enable(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rqt_enable(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) <= rqt_reg;
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) <= rqt_reg;
end process;
end generate ISCALAR_IO_RQT_ENABLE_GEN;
NO_ISCALAR_IO_RQT_ENABLE_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
iscalar_rqt_enable(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
end generate NO_ISCALAR_IO_RQT_ENABLE_GEN;
------------------------------------------------------
-- OUTPUT SCALAR REQUEST ENABLE REGISTER (INDEX 19) --
------------------------------------------------------
OSCALAR_RQT_ENABLE_GEN : if (C_N_OUTPUT_SCALARS > 0) generate
signal reg : std_logic_vector(C_N_OUTPUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(OSCALAR_RQT_ENABLE_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_SCALARS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
oscalar_rqt_enable(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rqt_enable(reg'range) <= reg;
oscalar_rqt_enable_reg(reg'range) <= reg;
end process;
end generate OSCALAR_RQT_ENABLE_GEN;
NO_OSCALAR_RQT_ENABLE_GEN : if (C_N_OUTPUT_SCALARS = 0) generate
begin
oscalar_rqt_enable(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
end generate NO_OSCALAR_RQT_ENABLE_GEN;
OSCALAR_IO_RQT_ENABLE_GEN : if (C_N_INOUT_SCALARS > 0) generate
signal os_rqt_reg : std_logic_vector(C_N_INOUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
os_rqt_reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(OSCALAR_RQT_ENABLE_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INOUT_SCALARS-1 loop
os_rqt_reg(i) <= S_AXI_WDATA(i+C_MAX_N_OSCALARS) and S_AXI_WSTRB((i+C_MAX_N_OSCALARS)/8);
end loop;
end if;
end if;
end process;
process(os_rqt_reg)
begin
oscalar_rqt_enable(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rqt_enable(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= os_rqt_reg;
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= os_rqt_reg;
end process;
end generate OSCALAR_IO_RQT_ENABLE_GEN;
NO_OSCALAR_IO_RQT_ENABLE_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
oscalar_rqt_enable(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
end generate NO_OSCALAR_IO_RQT_ENABLE_GEN;
-------------------------------------------------
-- OUTPUT ARGS LENGTH MODE REGISTER (INDEX 15) --
-------------------------------------------------
OARG_USE_SW_LENGTH_GEN : if (C_N_OUTPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_OUTPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(OARG_LENGTH_MODE_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
oarg_use_sw_length <= (others => '0');
oarg_length_mode_reg <= (others => '0');
oarg_use_sw_length(reg'range) <= reg;
oarg_length_mode_reg(reg'range) <= reg;
end process;
end generate OARG_USE_SW_LENGTH_GEN;
NO_OARG_USE_SW_LENGTH_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
oarg_use_sw_length <= (others => '0');
oarg_length_mode_reg <= (others => '0');
end generate NO_OARG_USE_SW_LENGTH_GEN;
----------------------------
-- BANK 0 OUTPUT DATAPATH --
----------------------------
-- For V6/S6, when the number of channel of the multiplexer is lower than 16 it's more
-- efficient to use a mux with binary selection input.
-- Mux for general purpose register read datapath:
process(rd_reg_addr,
ctrl_reg, status_reg,
ap_iarg_rst_reg, ap_oarg_rst_reg,
iarg_rqt_enable_reg, oarg_rqt_enable_reg,
oarg_length_mode_reg)
variable addr : integer range 0 to N_REGS-1;
begin
mux_gp_regs <= (others => '0');
addr := to_integer(unsigned(rd_reg_addr));
case addr is
when CTRL_REG_INDEX => mux_gp_regs <= ext_32(ctrl_reg);
when STATUS_REG_INDEX => mux_gp_regs <= ext_32(status_reg);
when IARG_RST_REG_INDEX => mux_gp_regs <= ext_32(ap_iarg_rst_reg);
when OARG_RST_REG_INDEX => mux_gp_regs <= ext_32(ap_oarg_rst_reg);
when IARG_RQT_ENABLE_REG_INDEX => mux_gp_regs <= ext_32(iarg_rqt_enable_reg);
when OARG_RQT_ENABLE_REG_INDEX => mux_gp_regs <= ext_32(oarg_rqt_enable_reg);
when OARG_LENGTH_MODE_REG_INDEX => mux_gp_regs <= ext_32(oarg_length_mode_reg);
when others =>
end case;
end process;
----------------------------------
--- BANK 2: INPUT SCALAR FIFOs ---
----------------------------------
process(S_AXI_ACLK, ap_rst_fb)
constant N_ELEMENTS : integer := C_MAX_N_ISCALARS + C_MAX_N_IOSCALARS;
constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
begin
if(ap_rst_fb = '1') then
host_iscalar_we <= (others => '0');
--host_oscalar_re(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS -1 downto C_MAX_N_OSCALARS) <= (others => '0');
host_ioscalar_re_i <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
host_iscalar_we <= (others => '0');
--host_oscalar_re(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS -1 downto C_MAX_N_OSCALARS) <= (others => '0');
host_ioscalar_re_i <= (others => '0');
if(iscalar_bank = '1' and wr_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in 0 to N_ELEMENTS-1 loop
if(offset = i) then
host_iscalar_we(i) <= '1';
else
host_iscalar_we(i) <= '0';
end if;
end loop;
end if;
if(iscalar_bank = '1' and rd_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in C_MAX_N_ISCALARS to C_MAX_N_ISCALARS + C_MAX_N_IOSCALARS-1 loop
if(offset = i) then
--host_oscalar_re(i) <= '1';
host_ioscalar_re_i(i) <= '1';
else
--host_oscalar_re(i) <= '0';
host_ioscalar_re_i(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
host_iscalar_dout <= wr_data_i;
host_oscalar_re <= host_ioscalar_re_i & host_oscalar_re_i;
-----------------------------------
--- BANK 3: OUTPUT SCALAR FIFOs ---
-----------------------------------
process(S_AXI_ACLK, ap_rst_fb)
constant N_ELEMENTS : integer := C_MAX_N_OSCALARS;
constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
begin
if(ap_rst_fb = '1') then
--host_oscalar_re(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
host_oscalar_re_i(C_MAX_N_OSCALARS-1 downto 0) <=(others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
--host_oscalar_re(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
host_oscalar_re_i(C_MAX_N_OSCALARS-1 downto 0) <=(others => '0');
if(oscalar_bank = '1' and rd_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in 0 to N_ELEMENTS-1 loop
if(offset = i) then
--host_oscalar_re(i) <= '1';
host_oscalar_re_i(i) <='1';
else
-- host_oscalar_re(i) <= '0';
host_oscalar_re_i(i) <='0';
end if;
end loop;
end if;
end if;
end process;
-- process(S_AXI_ACLK, ap_rst_fb)
-- constant N_ELEMENTS : integer := C_MAX_N_OSCALARS;
--
-- constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
-- variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
-- constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
-- constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
-- begin
-- if(ap_rst_fb = '1') then
-- host_oscalar_re(7 downto 0) <= (others => '0');
-- elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- host_oscalar_re(7 downto 0) <= (others => '0');
-- if(oscalar_bank = '1' and rd_start = '1') then
-- offset := unsigned(axi_addr(MSB downto LSB));
-- for i in 0 to 7 loop
-- if(offset = i) then
-- host_oscalar_re(i) <= '1';
-- else
-- host_oscalar_re(i) <= '0';
-- end if;
-- end loop;
-- end if;
-- end if;
-- end process;
-- Output scalar data mux:
process(rd_reg_addr, host_oscalar_din)
begin
mux_oscalar_data <= (others => '0');
for i in 0 to C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_oscalar_data <= ext_32(host_oscalar_din(C_MAX_SCALAR_DWIDTH*(i+1)-1 downto C_MAX_SCALAR_DWIDTH*i));
end if;
end loop;
end process;
-- -----------------------------------
-- --- BANK 2: INOUT SCALAR FIFOs ---
-- -----------------------------------
--
-- process(S_AXI_ACLK, ap_rst_fb)
-- constant N_ELEMENTS : integer := C_MAX_N_OSCALARS + C_MAX_N_IOSCALARS;
--
-- constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
-- variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
-- constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
-- constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
-- begin
-- if(ap_rst_fb = '1') then
-- host_oscalar_re(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
-- host_iscalar_we(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
-- elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- host_oscalar_re(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
-- host_iscalar_we(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
-- if(iscalar_bank = '1' and wr_start = '1') then
-- offset := unsigned(axi_addr(MSB downto LSB));
-- for i in 8 to N_ELEMENTS-1 loop
-- if(offset = i) then
-- host_iscalar_we(i) <= '1';
-- else
-- host_iscalar_we(i) <= '0';
-- end if;
-- end loop;
-- end if;
-- if(iscalar_bank = '1' and rd_start = '1') then
-- offset := unsigned(axi_addr(MSB downto LSB));
-- for i in 8 to N_ELEMENTS-1 loop
-- if(offset = i) then
-- host_oscalar_re(i) <= '1';
-- else
-- host_oscalar_re(i) <= '0';
-- end if;
-- end loop;
-- end if;
-- end if;
-- end process;
--
------------------------------------------
--- BANK 4: INPUT ARG STATUS REGISTERS ---
------------------------------------------
-- Status registers for input arguments:
process(rd_reg_addr, status_iarg_used, status_iarg_empty_sync, status_iarg_full)
begin
mux_iarg_status <= (others => '0');
for i in 0 to C_MAX_N_IARGS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_iarg_status(3 downto 0) <= status_iarg_used(4*(i+1)-1 downto 4*i);
mux_iarg_status(4) <= status_iarg_empty_sync(i);
mux_iarg_status(5) <= status_iarg_full(i);
end if;
end loop;
end process;
-------------------------------------------
--- BANK 5: OUTPUT ARG STATUS REGISTERS ---
-------------------------------------------
-- Status registers for output arguments:
process(rd_reg_addr, status_oarg_used, status_oarg_empty, status_oarg_full)
begin
mux_oarg_status <= (others => '0');
for i in 0 to C_MAX_N_OARGS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_oarg_status(3 downto 0) <= status_oarg_used(4*(i+1)-1 downto 4*i);
mux_oarg_status(4) <= status_oarg_empty(i);
mux_oarg_status(5) <= status_oarg_full(i);
end if;
end loop;
end process;
---------------------------------------------
--- BANK 6: INPUT SCALAR STATUS REGISTERS ---
---------------------------------------------
-- Status registers for input scalars:
process(rd_reg_addr, status_iscalar_used, status_iscalar_empty, status_iscalar_full)
begin
mux_iscalar_status <= (others => '0');
for i in 0 to C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_iscalar_status(3 downto 0) <= status_iscalar_used(4*(i+1)-1 downto 4*i);
mux_iscalar_status(4) <= status_iscalar_empty(i);
mux_iscalar_status(5) <= status_iscalar_full(i);
end if;
end loop;
end process;
----------------------------------------------
--- BANK 7: OUTPUT SCALAR STATUS REGISTERS ---
----------------------------------------------
-- Status registers for output scalars:
process(rd_reg_addr, status_oscalar_used, status_oscalar_empty, status_oscalar_full)
begin
mux_oscalar_status <= (others => '0');
for i in 0 to C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_oscalar_status(3 downto 0) <= status_oscalar_used(4*(i+1)-1 downto 4*i);
mux_oscalar_status(4) <= status_oscalar_empty(i);
mux_oscalar_status(5) <= status_oscalar_full(i);
end if;
end loop;
end process;
-------------------------------------------
--- BANK 8: OUTPUT ARGS SW LENGTH FIFOs ---
--------------------------------------------
process(S_AXI_ACLK, ap_rst_fb)
constant N_ELEMENTS : integer := C_MAX_N_OARGS;
constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
begin
if(ap_rst_fb = '1') then
oarg_sw_length_we_i <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
oarg_sw_length_we_i <= (others => '0');
if(oarg_length_bank = '1' and wr_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in 0 to N_ELEMENTS-1 loop
if(offset = i) then
oarg_sw_length_we_i(i) <= '1';
else
oarg_sw_length_we_i(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
--oarg_sw_length <= wr_data_i;
oarg_sw_length_we_event <= or_reduce(oarg_sw_length_we_i);
oarg_sw_length_we <= oarg_sw_length_we_i;
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
oarg_sw_length <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(oarg_sw_length_we_event = '1') then
oarg_sw_length <= wr_data_i;
end if;
end if;
end process;
process(S_AXI_ACLK)
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(oarg_sw_length_we_event = '1') then
oarg_sw_length_m2s <= wr_data_i;
end if;
end if;
end process;
-------------------------------------------
--- BANK 9: OUTPUT ARGS TDEST REGISTERS ---
-------------------------------------------
OARG_TDEST_GEN : if (C_N_OUTPUT_ARGS > 0) generate
signal oarg_tdest_reg_we : std_logic_vector(N_REGS-1 downto 0);
signal oarg_tdest_reg : std_logic_vector(C_N_OUTPUT_ARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
constant N_ELEMENTS : integer := C_MAX_N_OARGS;
constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
begin
if(ap_rst_fb = '1') then
oarg_tdest_reg_we <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
oarg_tdest_reg_we <= (others => '0');
if(oarg_tdest_bank = '1' and wr_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in 0 to N_ELEMENTS-1 loop
if(offset = i) then
oarg_tdest_reg_we(i) <= '1';
else
oarg_tdest_reg_we(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
oarg_tdest_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
for i in 0 to C_N_OUTPUT_ARGS-1 loop
if(oarg_tdest_reg_we(i) = '1') then
oarg_tdest_reg(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i) <=
S_AXI_WDATA(C_M_AXIS_TDEST_WIDTH-1 downto 0);
end if;
end loop;
end if;
end process;
process(rd_reg_addr, oarg_tdest_reg)
variable addr : integer range 0 to N_REGS-1;
begin
mux_oarg_tdest_regs <= (others => '0');
addr := to_integer(unsigned(rd_reg_addr));
for i in 0 to C_N_OUTPUT_ARGS-1 loop
if(i = addr) then
mux_oarg_tdest_regs <= ext_32(oarg_tdest_reg(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i));
end if;
end loop;
end process;
process(oarg_tdest_reg)
begin
host_oarg_tdest <= (others => '0');
host_oarg_tdest(C_N_OUTPUT_ARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0) <= oarg_tdest_reg;
end process;
end generate OARG_TDEST_GEN;
NO_OARG_TDEST_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
mux_oarg_tdest_regs <= (others => '0');
host_oarg_tdest <= (others => '0');
end generate NO_OARG_TDEST_GEN;
---------------------
-- OUTPUT DATAPATH --
---------------------
process(S_AXI_ACLK)
variable int_addr : integer range 0 to (2**BANK_ADDR_WIDTH)-1;
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(axi_rst = '1' or (rd_data_vld and S_AXI_RREADY) = '1') then
rd_data <= (others => '0');
elsif(rd_data_ce = '1') then
int_addr := to_integer(unsigned(rd_bank_addr));
case int_addr is
when GP_REGS_BANK_ADDR => rd_data <= mux_gp_regs;
when OSCALAR_BANK_ADDR => rd_data <= mux_oscalar_data;
when ISCALAR_BANK_ADDR => rd_data <= mux_oscalar_data;
when IARG_STATUS_BANK_ADDR => rd_data <= mux_iarg_status;
when OARG_STATUS_BANK_ADDR => rd_data <= mux_oarg_status;
when ISCALAR_STATUS_BANK_ADDR => rd_data <= mux_iscalar_status;
when OSCALAR_STATUS_BANK_ADDR => rd_data <= mux_oscalar_status;
when OARG_TDEST_BANK_ADDR => rd_data <= mux_oarg_tdest_regs;
when others => rd_data <= (others => '0');
end case;
end if;
end if;
end process;
end rtl;
|
mit
|
3664e881f48c723ea20b88aedbc37605
| 0.545542 | 3.251773 | false | false | false | false |
agural/FPGA-Oscilloscope
|
FPGA/oscilloscope (2).vhd
| 1 | 10,632 |
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 32-bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
-- CREATED "Sun Mar 02 11:05:15 2014"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY FPGA-Oscilloscope IS
PORT
(
HSYNC : OUT STD_LOGIC;
SC : OUT STD_LOGIC;
VSYNC : OUT STD_LOGIC;
DCLK : OUT STD_LOGIC;
RAS : OUT STD_LOGIC;
CAS : OUT STD_LOGIC;
TRG : OUT STD_LOGIC;
WE : OUT STD_LOGIC;
ADDR : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END FPGA-Oscilloscope;
ARCHITECTURE bdf_type OF FPGA-Oscilloscope IS
COMPONENT lpm_mux0
PORT(data0x : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_counter2
PORT(sclr : IN STD_LOGIC;
clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare0
PORT(dataa : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare3
PORT(dataa : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare4
PORT(dataa : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare5
PORT(dataa : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
alb : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare1
PORT(dataa : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare2
PORT(dataa : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
alb : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_counter1
PORT(sclr : IN STD_LOGIC;
clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_constant0
PORT( result : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT scopevram
PORT(clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
cs : IN STD_LOGIC;
rw : IN STD_LOGIC;
srt : IN STD_LOGIC;
RAS : OUT STD_LOGIC;
CAS : OUT STD_LOGIC;
TRG : OUT STD_LOGIC;
WE : OUT STD_LOGIC;
ACK : OUT STD_LOGIC;
BUSY : OUT STD_LOGIC;
AS : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_counter3
PORT(sclr : IN STD_LOGIC;
clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_counter0
PORT(sclr : IN STD_LOGIC;
clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
SIGNAL ADDRESS : STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL RESET : STD_LOGIC;
SIGNAL SYS_CLK : STD_LOGIC;
SIGNAL SYS_COUNT : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL VRAM_CLK : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_6 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_43 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_44 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_45 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_23 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_24 : STD_LOGIC;
SIGNAL DFF_inst39 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_25 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_27 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_28 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC;
SIGNAL DFF_inst13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_32 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_34 : STD_LOGIC;
SIGNAL DFF_inst42 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_35 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_37 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_39 : STD_LOGIC;
SIGNAL DFF_inst18 : STD_LOGIC;
SIGNAL SRFF_inst3 : STD_LOGIC;
BEGIN
HSYNC <= DFF_inst18;
SYNTHESIZED_WIRE_4 <= '1';
SYNTHESIZED_WIRE_6 <= '1';
SYNTHESIZED_WIRE_7 <= '1';
SYNTHESIZED_WIRE_9 <= '1';
SYNTHESIZED_WIRE_13 <= '1';
SYNTHESIZED_WIRE_14 <= '1';
SYNTHESIZED_WIRE_15 <= '1';
SYNTHESIZED_WIRE_16 <= '1';
SYNTHESIZED_WIRE_18 <= '1';
SYNTHESIZED_WIRE_20 <= '1';
SYNTHESIZED_WIRE_21 <= '1';
SYNTHESIZED_WIRE_23 <= '1';
SYNTHESIZED_WIRE_24 <= '1';
SYNTHESIZED_WIRE_25 <= '1';
SYNTHESIZED_WIRE_26 <= '1';
SYNTHESIZED_WIRE_27 <= '1';
SYNTHESIZED_WIRE_35 <= '1';
SYNTHESIZED_WIRE_36 <= '1';
SYNTHESIZED_WIRE_37 <= '1';
SYNTHESIZED_WIRE_39 <= '1';
b2v_ADDR_MUX : lpm_mux0
PORT MAP(data0x => ADDRESS(8 DOWNTO 0),
data1x => ADDRESS(17 DOWNTO 9),
data2x => SYNTHESIZED_WIRE_0,
data3x => SYNTHESIZED_WIRE_1,
sel => SYNTHESIZED_WIRE_2,
result => ADDR);
b2v_HORIZONTAL_CNT : lpm_counter2
PORT MAP(sclr => RESET,
clock => VRAM_CLK,
q => SYNTHESIZED_WIRE_42);
b2v_inst : lpm_compare0
PORT MAP(dataa => SYNTHESIZED_WIRE_42,
ageb => SYNTHESIZED_WIRE_5);
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_4,SYNTHESIZED_WIRE_6)
BEGIN
IF (SYNTHESIZED_WIRE_4 = '0') THEN
SYNTHESIZED_WIRE_44 <= '0';
ELSIF (SYNTHESIZED_WIRE_6 = '0') THEN
SYNTHESIZED_WIRE_44 <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
SYNTHESIZED_WIRE_44 <= SYNTHESIZED_WIRE_5;
END IF;
END PROCESS;
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_7,SYNTHESIZED_WIRE_9)
BEGIN
IF (SYNTHESIZED_WIRE_7 = '0') THEN
DFF_inst13 <= '0';
ELSIF (SYNTHESIZED_WIRE_9 = '0') THEN
DFF_inst13 <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
DFF_inst13 <= SYNTHESIZED_WIRE_8;
END IF;
END PROCESS;
b2v_inst14 : lpm_compare3
PORT MAP(dataa => SYNTHESIZED_WIRE_43,
ageb => SYNTHESIZED_WIRE_19);
b2v_inst15 : lpm_compare4
PORT MAP(dataa => SYNTHESIZED_WIRE_43,
ageb => SYNTHESIZED_WIRE_30);
b2v_inst16 : lpm_compare5
PORT MAP(dataa => SYNTHESIZED_WIRE_43,
alb => SYNTHESIZED_WIRE_31);
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_13,SYNTHESIZED_WIRE_14)
BEGIN
IF (SYNTHESIZED_WIRE_13 = '0') THEN
VRAM_CLK <= '0';
ELSIF (SYNTHESIZED_WIRE_14 = '0') THEN
VRAM_CLK <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
VRAM_CLK <= SYS_COUNT(1);
END IF;
END PROCESS;
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_15,SYNTHESIZED_WIRE_16)
BEGIN
IF (SYNTHESIZED_WIRE_15 = '0') THEN
DFF_inst18 <= '0';
ELSIF (SYNTHESIZED_WIRE_16 = '0') THEN
DFF_inst18 <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
DFF_inst18 <= SYNTHESIZED_WIRE_44;
END IF;
END PROCESS;
SYNTHESIZED_WIRE_34 <= NOT(SYNTHESIZED_WIRE_45);
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_18,SYNTHESIZED_WIRE_20)
BEGIN
IF (SYNTHESIZED_WIRE_18 = '0') THEN
VSYNC <= '0';
ELSIF (SYNTHESIZED_WIRE_20 = '0') THEN
VSYNC <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
VSYNC <= SYNTHESIZED_WIRE_19;
END IF;
END PROCESS;
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_21,SYNTHESIZED_WIRE_23)
BEGIN
IF (SYNTHESIZED_WIRE_21 = '0') THEN
SC <= '0';
ELSIF (SYNTHESIZED_WIRE_23 = '0') THEN
SC <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
SC <= SYNTHESIZED_WIRE_22;
END IF;
END PROCESS;
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_24,SYNTHESIZED_WIRE_25)
BEGIN
IF (SYNTHESIZED_WIRE_24 = '0') THEN
DCLK <= '0';
ELSIF (SYNTHESIZED_WIRE_25 = '0') THEN
DCLK <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
DCLK <= DFF_inst39;
END IF;
END PROCESS;
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_27,SYNTHESIZED_WIRE_26)
VARIABLE synthesized_var_for_SRFF_inst3 : STD_LOGIC;
BEGIN
IF (SYNTHESIZED_WIRE_27 = '0') THEN
synthesized_var_for_SRFF_inst3 := '0';
ELSIF (SYNTHESIZED_WIRE_26 = '0') THEN
synthesized_var_for_SRFF_inst3 := '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
synthesized_var_for_SRFF_inst3 := (NOT(synthesized_var_for_SRFF_inst3) AND SYNTHESIZED_WIRE_28) OR (synthesized_var_for_SRFF_inst3 AND (NOT(SYNTHESIZED_WIRE_29)));
END IF;
SRFF_inst3 <= synthesized_var_for_SRFF_inst3;
END PROCESS;
SYNTHESIZED_WIRE_22 <= VRAM_CLK AND DFF_inst13 AND SYNTHESIZED_WIRE_30 AND SYNTHESIZED_WIRE_31;
SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_32 AND SYNTHESIZED_WIRE_45;
SYNTHESIZED_WIRE_28 <= SYNTHESIZED_WIRE_34 AND DFF_inst42;
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_36)
BEGIN
IF (SYNTHESIZED_WIRE_35 = '0') THEN
DFF_inst39 <= '0';
ELSIF (SYNTHESIZED_WIRE_36 = '0') THEN
DFF_inst39 <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
DFF_inst39 <= VRAM_CLK;
END IF;
END PROCESS;
PROCESS(SYS_CLK,SYNTHESIZED_WIRE_37,SYNTHESIZED_WIRE_39)
BEGIN
IF (SYNTHESIZED_WIRE_37 = '0') THEN
DFF_inst42 <= '0';
ELSIF (SYNTHESIZED_WIRE_39 = '0') THEN
DFF_inst42 <= '1';
ELSIF (RISING_EDGE(SYS_CLK)) THEN
DFF_inst42 <= SYNTHESIZED_WIRE_45;
END IF;
END PROCESS;
b2v_inst6 : lpm_compare1
PORT MAP(dataa => SYNTHESIZED_WIRE_42,
ageb => SYNTHESIZED_WIRE_32);
b2v_inst7 : lpm_compare2
PORT MAP(dataa => SYNTHESIZED_WIRE_42,
alb => SYNTHESIZED_WIRE_45);
b2v_ROW_TRANSFER_COUNTER : lpm_counter1
PORT MAP(sclr => RESET,
clock => DFF_inst18,
q => SYNTHESIZED_WIRE_0);
b2v_SRT_COL_START : lpm_constant0
PORT MAP( result => SYNTHESIZED_WIRE_1);
b2v_STATE_MACHINE : scopevram
PORT MAP(clk => SYS_CLK,
reset => RESET,
srt => SRFF_inst3,
RAS => RAS,
CAS => CAS,
TRG => TRG,
WE => WE,
ACK => SYNTHESIZED_WIRE_29,
AS => SYNTHESIZED_WIRE_2);
b2v_VERTICAL_CNT : lpm_counter3
PORT MAP(sclr => RESET,
clock => SYNTHESIZED_WIRE_44,
q => SYNTHESIZED_WIRE_43);
b2v_VRAM_CLOCK : lpm_counter0
PORT MAP(sclr => RESET,
clock => SYS_CLK,
q => SYS_COUNT);
END bdf_type;
|
mit
|
287d1cb6d689a6d1f5c4b03e1d9088a5
| 0.698269 | 2.920879 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/ddrv4-rtl-a.vhd
| 1 | 5,748 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ddrv4
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ddrv4-rtl-a.vhd,v 1.5 2006/07/05 10:01:22 wig Exp $
-- $Date: 2006/07/05 10:01:22 $
-- $Log: ddrv4-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:22 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ddrv4
--
architecture rtl of ddrv4 is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ddrv
-- No Generated Generics
port (
-- Generated Port for Entity ddrv
alarm_time : in std_ulogic_vector(3 downto 0); -- Display storage buffer 2 ls_hr
current_time : in std_ulogic_vector(3 downto 0); -- Display storage buffer 2 ls_hr
display : out std_ulogic_vector(6 downto 0); -- Display storage buffer 2 ls_hr
key_buffer : in std_ulogic_vector(3 downto 0); -- Display storage buffer 2 ls_hr
show_a : in std_ulogic;
show_new_time : in std_ulogic;
sound_alarm : out std_ulogic -- Display storage buffer 2 ls_hr __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ddrv
);
end component;
-- ---------
component and_f
-- No Generated Generics
port (
-- Generated Port for Entity and_f
out_p : out std_ulogic;
y : in std_ulogic_vector(3 downto 0) -- Display storage buffer 0 ls_min
-- End of Generated Port for Entity and_f
);
end component;
-- ---------
--
-- Generated Signal List
--
signal alarm : std_ulogic_vector(3 downto 0);
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sound_alarm : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_display_ls_hr_go <= display_ls_hr; -- __I_O_BUS_PORT
p_mix_display_ls_min_go <= display_ls_min; -- __I_O_BUS_PORT
p_mix_display_ms_hr_go <= display_ms_hr; -- __I_O_BUS_PORT
p_mix_display_ms_min_go <= display_ms_min; -- __I_O_BUS_PORT
p_mix_sound_alarm_go <= sound_alarm; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for d_ls_hr
d_ls_hr: ddrv
port map (
alarm_time => alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time => current_time_ls_hr, -- Display storage buffer 2 ls_hr
display => display_ls_hr, -- Display storage buffer 2 ls_hr
key_buffer => key_buffer_2, -- Display storage buffer 2 ls_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(2) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ls_hr
-- Generated Instance Port Map for d_ls_min
d_ls_min: ddrv
port map (
alarm_time => alarm_time_ls_min, -- Display storage buffer 0 ls_min
current_time => current_time_ls_min, -- Display storage buffer 0 ls_min
display => display_ls_min, -- Display storage buffer 0 ls_min
key_buffer => key_buffer_0, -- Display storage buffer 0 ls_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(0) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ls_min
-- Generated Instance Port Map for d_ms_hr
d_ms_hr: ddrv
port map (
alarm_time => alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time => current_time_ms_hr, -- Display storage buffer 3 ms_hr
display => display_ms_hr, -- Display storage buffer 3 ms_hr
key_buffer => key_buffer_3, -- Display storage buffer 3 ms_hr
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(3) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ms_hr
-- Generated Instance Port Map for d_ms_min
d_ms_min: ddrv
port map (
alarm_time => alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time => current_time_ms_min, -- Display storage buffer 1 ms_min
display => display_ms_min, -- Display storage buffer 1 ms_min
key_buffer => key_buffer_1, -- Display storage buffer 1 ms_min
show_a => show_a,
show_new_time => show_new_time,
sound_alarm => alarm(1) -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for d_ms_min
-- Generated Instance Port Map for u_and_f
u_and_f: and_f
port map (
out_p => sound_alarm,
y => alarm -- Display storage buffer 0 ls_minDisplay storage buffer 1 ms_minDisplay storage buffer 2 ls_hrDi...
);
-- End of Generated Instance Port Map for u_and_f
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
6fbdd34de4cce28e654456ecd66ec0d9
| 0.643006 | 3.055821 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/names/ios_e-rtl-a.vhd
| 1 | 20,410 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-rtl-a.vhd,v 1.3 2005/07/19 07:13:10 wig Exp $
-- $Date: 2005/07/19 07:13:10 $
-- $Log: ios_e-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:10 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ios_e
--
architecture rtl of ios_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioblock0_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end component;
-- ---------
component ioblock1_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock1_e
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic
-- End of Generated Port for Entity ioblock1_e
);
end component;
-- ---------
component ioblock2_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ioblock3_e --
-- No Generated Generics
port (
-- Generated Port for Entity ioblock3_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ioblock3_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
iosel_6 <= p_mix_iosel_6_gi; -- __I_I_BIT_PORT
iosel_7 <= p_mix_iosel_7_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
iosel_ms_min <= p_mix_iosel_ms_min_gi; -- __I_I_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioblock_0
ioblock_0: ioblock0_e
port map (
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_6_gi => iosel_6, -- IO_Select
p_mix_iosel_7_gi => iosel_7, -- IO_Select
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_en_2_go => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_0
-- Generated Instance Port Map for ioblock_1
ioblock_1: ioblock1_e
port map (
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_iosel_ms_min_gi => iosel_ms_min, -- IO_Select
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_1
-- Generated Instance Port Map for ioblock_2
ioblock_2: ioblock2_e
;
-- End of Generated Instance Port Map for ioblock_2
-- Generated Instance Port Map for ioblock_3
ioblock_3: ioblock3_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ioblock_3
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
86080a39ef979fb50d0029f1410bfe65
| 0.605537 | 2.24854 | false | false | false | false |
mitchsm/nvc
|
test/regress/access3.vhd
| 4 | 556 |
entity access3 is
end entity;
architecture test of access3 is
type int_ptr is access integer;
type string_ptr is access string;
begin
process is
variable i : int_ptr;
variable s : string_ptr;
begin
i := new integer;
assert i.all = integer'left;
i := new integer'(3);
assert i.all = 3;
s := new string'("");
assert s.all = "";
assert s'length = 0;
s := new string'("hello");
assert s.all = "hello";
wait;
end process;
end architecture;
|
gpl-3.0
|
9a2a3e3ff50769b2784ba7735f778ca2
| 0.544964 | 3.943262 | false | false | false | false |
blutsvente/MIX
|
test/results/logic/inst_a_e-rtl-a.vhd
| 1 | 4,768 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:28:20 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--__I_SIMPLE_LOGIC__ inst_a_and
--__I_SIMPLE_LOGIC__ inst_a_or
--__I_SIMPLE_LOGIC__ inst_a_wire
component inst_aa_e -- the aa instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
and_i1_1 : out std_ulogic;
and_i2_1 : out std_ulogic_vector(15 downto 0);
or_i1_1 : out std_ulogic;
or_i2_1 : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e -- the ab instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
and_i1_2 : out std_ulogic;
and_i1_3_p : out std_ulogic;
and_i2_2 : out std_ulogic_vector(15 downto 0);
and_i2_3_p : out std_ulogic_vector(15 downto 0);
or_i1_2 : out std_ulogic;
or_i1_3_p : out std_ulogic;
or_i2_2 : out std_ulogic_vector(15 downto 0);
or_i2_3_p : out std_ulogic_vector(15 downto 0)
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal and_i1_1 : std_ulogic;
signal and_i1_2 : std_ulogic;
signal and_i1_3 : std_ulogic;
signal and_i2_1 : std_ulogic_vector(15 downto 0);
signal and_i2_2 : std_ulogic_vector(15 downto 0);
signal and_i3_3 : std_ulogic_vector(15 downto 0);
signal or_i1_1 : std_ulogic;
signal or_i1_2 : std_ulogic;
signal or_i1_3 : std_ulogic;
signal or_i2_1 : std_ulogic_vector(15 downto 0);
signal or_i2_2 : std_ulogic_vector(15 downto 0);
signal or_i3_3 : std_ulogic_vector(15 downto 0);
signal wire_bus_si : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal wire_bus_so : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal wire_si : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal wire_so : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
wire_bus_si <= wire_bus_i; -- __I_I_BUS_PORT
wire_bus_o <= wire_bus_so; -- __I_O_BUS_PORT
wire_si <= wire_i; -- __I_I_BIT_PORT
wire_o <= wire_so; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Logic for inst_a_and
and_o1 <=
and_i1_2
AND and_i1_1
AND and_i1_3;
-- End of Generated Logic for inst_a_and
-- Generated Logic for inst_a_and_1
and_o2 <=
and_i2_2
AND and_i2_1
AND and_i3_3;
-- End of Generated Logic for inst_a_and_1
-- Generated Logic for inst_a_or
or_o1 <=
or_i1_2
OR or_i1_3
OR or_i1_1;
-- End of Generated Logic for inst_a_or
-- Generated Logic for inst_a_or_1
or_o2 <=
or_i2_2
OR or_i2_1
OR or_i3_3;
-- End of Generated Logic for inst_a_or_1
-- Generated Logic for inst_a_wire
wire_so <=
wire_si;
-- End of Generated Logic for inst_a_wire
-- Generated Logic for inst_a_wire_1
wire_bus_so <=
wire_bus_si;
-- End of Generated Logic for inst_a_wire_1
-- Generated Instance Port Map for inst_aa_i
inst_aa_i: inst_aa_e -- the aa instance
port map (
and_i1_1 => and_i1_1,
and_i2_1 => and_i2_1,
or_i1_1 => or_i1_1,
or_i2_1 => or_i2_1
);
-- End of Generated Instance Port Map for inst_aa_i
-- Generated Instance Port Map for inst_ab_i
inst_ab_i: inst_ab_e -- the ab instance
port map (
and_i1_2 => and_i1_2,
and_i1_3_p => and_i1_3,
and_i2_2 => and_i2_2,
and_i2_3_p => and_i3_3,
or_i1_2 => or_i1_2,
or_i1_3_p => or_i1_3,
or_i2_2 => or_i2_2,
or_i2_3_p => or_i3_3
);
-- End of Generated Instance Port Map for inst_ab_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
9c5ad5b312165640b5d67fd010029939
| 0.596267 | 2.504202 | false | false | false | false |
freecores/eco32
|
fpga/src/ram/sdramcntl.vhd
| 1 | 31,168 |
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS Corp
-- Tool Versions : WebPACK 6.3.03i
--
-- Description:
-- SDRAM controller
--
-- Revision:
-- n.a. (because of hacking by Hellwig Geisse)
--
-- Additional Comments:
-- 1.4.0:
-- Added generic parameter to enable/disable independent active rows in each bank.
-- 1.3.0:
-- Modified to allow independently active rows in each bank.
-- 1.2.0:
-- Modified to allow pipelining of read/write operations.
-- 1.1.0:
-- Initial release.
--
-- License:
-- This code can be freely distributed and modified as long as
-- this header is not removed.
--------------------------------------------------------------------
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity sdramCntl is
port(
-- host side
clk : in std_logic; -- master clock
clk_ok : in std_logic; -- true if clock is stable
rd : in std_logic; -- initiate read operation
wr : in std_logic; -- initiate write operation
done : out std_logic; -- read or write operation is done
hAddr : in std_logic_vector(23 downto 0); -- address from host to SDRAM
hDIn : in std_logic_vector(15 downto 0); -- data from host to SDRAM
hDOut : out std_logic_vector(15 downto 0); -- data from SDRAM to host
-- SDRAM side
cke : out std_logic; -- clock-enable to SDRAM
ce_n : out std_logic; -- chip-select to SDRAM
ras_n : out std_logic; -- SDRAM row address strobe
cas_n : out std_logic; -- SDRAM column address strobe
we_n : out std_logic; -- SDRAM write enable
ba : out std_logic_vector(1 downto 0); -- SDRAM bank address
sAddr : out std_logic_vector(12 downto 0); -- SDRAM row/column address
sDIn : in std_logic_vector(15 downto 0); -- data from SDRAM
sDOut : out std_logic_vector(15 downto 0); -- data to SDRAM
sDOutEn : out std_logic; -- true if data is output to SDRAM on sDOut
dqmh : out std_logic; -- enable upper-byte of SDRAM databus if true
dqml : out std_logic -- enable lower-byte of SDRAM databus if true
);
end sdramCntl;
architecture arch of sdramCntl is
constant YES : std_logic := '1';
constant NO : std_logic := '0';
-- select one of two integers based on a Boolean
function int_select(s : in boolean; a : in integer; b : in integer) return integer is
begin
if s then
return a;
else
return b;
end if;
return a;
end function int_select;
constant OUTPUT : std_logic := '1'; -- direction of dataflow w.r.t. this controller
constant INPUT : std_logic := '0';
constant NOP : std_logic := '0'; -- no operation
constant READ : std_logic := '1'; -- read operation
constant WRITE : std_logic := '1'; -- write operation
-- SDRAM timing parameters
constant Tinit : natural := 200; -- min initialization interval (us)
constant Tras : natural := 45; -- min interval between active to precharge commands (ns)
constant Trcd : natural := 20; -- min interval between active and R/W commands (ns)
constant Tref : natural := 64_000_000; -- maximum refresh interval (ns)
constant Trfc : natural := 66; -- duration of refresh operation (ns)
constant Trp : natural := 20; -- min precharge command duration (ns)
constant Twr : natural := 15; -- write recovery time (ns)
constant Txsr : natural := 75; -- exit self-refresh time (ns)
-- SDRAM timing parameters converted into clock cycles (based on FREQ = 50_000)
constant NORM : natural := 1_000_000; -- normalize ns * KHz
constant INIT_CYCLES : natural := 1+((Tinit*50_000)/1000); -- SDRAM power-on initialization interval
constant RAS_CYCLES : natural := 1+((Tras*50_000)/NORM); -- active-to-precharge interval
constant RCD_CYCLES : natural := 1+((Trcd*50_000)/NORM); -- active-to-R/W interval
constant REF_CYCLES : natural := 1+(((Tref/8192)*50_000)/NORM); -- interval between row refreshes
constant RFC_CYCLES : natural := 1+((Trfc*50_000)/NORM); -- refresh operation interval
constant RP_CYCLES : natural := 1+((Trp*50_000)/NORM); -- precharge operation interval
constant WR_CYCLES : natural := 1+((Twr*50_000)/NORM); -- write recovery time
constant XSR_CYCLES : natural := 1+((Txsr*50_000)/NORM); -- exit self-refresh time
constant MODE_CYCLES : natural := 2; -- mode register setup time
constant CAS_CYCLES : natural := 3; -- CAS latency
constant RFSH_OPS : natural := 8; -- number of refresh operations needed to init SDRAM
-- timer registers that count down times for various SDRAM operations
signal timer_r, timer_x : natural range 0 to INIT_CYCLES; -- current SDRAM op time
signal rasTimer_r, rasTimer_x : natural range 0 to RAS_CYCLES; -- active-to-precharge time
signal wrTimer_r, wrTimer_x : natural range 0 to WR_CYCLES; -- write-to-precharge time
signal refTimer_r, refTimer_x : natural range 0 to REF_CYCLES; -- time between row refreshes
signal rfshCntr_r, rfshCntr_x : natural range 0 to 8192; -- counts refreshes that are neede
signal nopCntr_r, nopCntr_x : natural range 0 to 10000; -- counts consecutive NOP operations
signal doSelfRfsh : std_logic; -- active when the NOP counter hits zero and self-refresh can start
-- states of the SDRAM controller state machine
type cntlState is (
INITWAIT, -- initialization - waiting for power-on initialization to complete
INITPCHG, -- initialization - initial precharge of SDRAM banks
INITSETMODE, -- initialization - set SDRAM mode
INITRFSH, -- initialization - do initial refreshes
RW, -- read/write/refresh the SDRAM
ACTIVATE, -- open a row of the SDRAM for reading/writing
REFRESHROW, -- refresh a row of the SDRAM
SELFREFRESH -- keep SDRAM in self-refresh mode with CKE low
);
signal state_r, state_x : cntlState; -- state register and next state
-- commands that are sent to the SDRAM to make it perform certain operations
-- commands use these SDRAM input pins (ce_n,ras_n,cas_n,we_n,dqmh,dqml)
subtype sdramCmd is unsigned(5 downto 0);
constant NOP_CMD : sdramCmd := "011100";
constant ACTIVE_CMD : sdramCmd := "001100";
constant READ_CMD : sdramCmd := "010100";
constant WRITE_CMD : sdramCmd := "010000";
constant PCHG_CMD : sdramCmd := "001011";
constant MODE_CMD : sdramCmd := "000011";
constant RFSH_CMD : sdramCmd := "000111";
-- SDRAM mode register
-- the SDRAM is placed in a non-burst mode (burst length = 1) with a 3-cycle CAS
subtype sdramMode is std_logic_vector(12 downto 0);
constant MODE : sdramMode := "000" & "0" & "00" & "011" & "0" & "000";
-- the host address is decomposed into these sets of SDRAM address components
constant ROW_LEN : natural := 13; -- number of row address bits
constant COL_LEN : natural := 9; -- number of column address bits
signal bank : std_logic_vector(ba'range); -- bank address bits
signal row : std_logic_vector(ROW_LEN - 1 downto 0); -- row address within bank
signal col : std_logic_vector(sAddr'range); -- column address within row
-- registers that store the currently active row in each bank of the SDRAM
constant NUM_ACTIVE_ROWS : integer := 1;
type activeRowType is array(0 to NUM_ACTIVE_ROWS-1) of std_logic_vector(row'range);
signal activeRow_r, activeRow_x : activeRowType;
signal activeFlag_r, activeFlag_x : std_logic_vector(0 to NUM_ACTIVE_ROWS-1); -- indicates that some row in a bank is active
signal bankIndex : natural range 0 to NUM_ACTIVE_ROWS-1; -- bank address bits
signal activeBank_r, activeBank_x : std_logic_vector(ba'range); -- indicates the bank with the active row
signal doActivate : std_logic; -- indicates when a new row in a bank needs to be activated
-- there is a command bit embedded within the SDRAM column address
constant CMDBIT_POS : natural := 10; -- position of command bit
constant AUTO_PCHG_ON : std_logic := '1'; -- CMDBIT value to auto-precharge the bank
constant AUTO_PCHG_OFF : std_logic := '0'; -- CMDBIT value to disable auto-precharge
constant ONE_BANK : std_logic := '0'; -- CMDBIT value to select one bank
constant ALL_BANKS : std_logic := '1'; -- CMDBIT value to select all banks
-- status signals that indicate when certain operations are in progress
signal wrInProgress : std_logic; -- write operation in progress
signal rdInProgress : std_logic; -- read operation in progress
signal activateInProgress : std_logic; -- row activation is in progress
-- these registers track the progress of read and write operations
signal rdPipeline_r, rdPipeline_x : std_logic_vector(CAS_CYCLES+1 downto 0); -- pipeline of read ops in progress
signal wrPipeline_r, wrPipeline_x : std_logic_vector(0 downto 0); -- pipeline of write ops (only need 1 cycle)
-- registered outputs to host
signal hDOut_r, hDOut_x : std_logic_vector(hDOut'range); -- holds data read from SDRAM and sent to the host
-- registered outputs to SDRAM
signal cke_r, cke_x : std_logic; -- clock enable
signal cmd_r, cmd_x : sdramCmd; -- SDRAM command bits
signal ba_r, ba_x : std_logic_vector(ba'range); -- SDRAM bank address bits
signal sAddr_r, sAddr_x : std_logic_vector(sAddr'range); -- SDRAM row/column address
signal sData_r, sData_x : std_logic_vector(sDOut'range); -- SDRAM out databus
signal sDataDir_r, sDataDir_x : std_logic; -- SDRAM databus direction control bit
begin
-----------------------------------------------------------
-- attach some internal signals to the I/O ports
-----------------------------------------------------------
-- attach registered SDRAM control signals to SDRAM input pins
(ce_n, ras_n, cas_n, we_n, dqmh, dqml) <= cmd_r; -- SDRAM operation control bits
cke <= cke_r; -- SDRAM clock enable
ba <= ba_r; -- SDRAM bank address
sAddr <= sAddr_r; -- SDRAM address
sDOut <= sData_r; -- SDRAM output data bus
sDOutEn <= YES when sDataDir_r = OUTPUT else NO; -- output databus enable
-- attach some port signals
hDOut <= hDOut_r; -- data back to host
-----------------------------------------------------------
-- compute the next state and outputs
-----------------------------------------------------------
combinatorial : process(rd, wr, hAddr, hDIn, hDOut_r, sDIn, state_r,
activeFlag_r, activeRow_r, activeBank_r,
rdPipeline_r, wrPipeline_r,
nopCntr_r, rfshCntr_r, timer_r, rasTimer_r,
wrTimer_r, refTimer_r, cmd_r, cke_r)
begin
-----------------------------------------------------------
-- setup default values for signals
-----------------------------------------------------------
cke_x <= YES; -- enable SDRAM clock
cmd_x <= NOP_CMD; -- set SDRAM command to no-operation
sDataDir_x <= INPUT; -- accept data from the SDRAM
sData_x <= hDIn(sData_x'range); -- output data from host to SDRAM
state_x <= state_r; -- reload these registers and flags
activeFlag_x <= activeFlag_r; -- with their existing values
activeRow_x <= activeRow_r;
activeBank_x <= activeBank_r;
rfshCntr_x <= rfshCntr_r;
-----------------------------------------------------------
-- setup default value for the SDRAM address
-----------------------------------------------------------
-- extract bank field from host address
ba_x <= hAddr(ba'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN);
bank <= ba_x;
bankIndex <= 0;
-- extract row, column fields from host address
row <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN);
-- extend column (if needed) until it is as large as the (SDRAM address bus - 1)
col <= (others => '0'); -- set it to all zeroes
col(COL_LEN-1 downto 0) <= hAddr(COL_LEN-1 downto 0);
-- by default, set SDRAM address to the column address with interspersed
-- command bit set to disable auto-precharge
sAddr_x <= col(col'high-1 downto CMDBIT_POS) & AUTO_PCHG_OFF
& col(CMDBIT_POS-1 downto 0);
-----------------------------------------------------------
-- manage the read and write operation pipelines
-----------------------------------------------------------
-- determine if read operations are in progress by the presence of
-- READ flags in the read pipeline
if rdPipeline_r(rdPipeline_r'high downto 1) /= 0 then
rdInProgress <= YES;
else
rdInProgress <= NO;
end if;
-- enter NOPs into the read and write pipeline shift registers by default
rdPipeline_x <= NOP & rdPipeline_r(rdPipeline_r'high downto 1);
wrPipeline_x(0) <= NOP;
-- transfer data from SDRAM to the host data register if a read flag has exited the pipeline
-- (the transfer occurs 1 cycle before we tell the host the read operation is done)
if rdPipeline_r(1) = READ then
-- get the SDRAM data for the host directly from the SDRAM if the controller and SDRAM are in-phase
hDOut_x <= sDIn(hDOut'range);
else
-- retain contents of host data registers if no data from the SDRAM has arrived yet
hDOut_x <= hDOut_r;
end if;
done <= rdPipeline_r(0) or wrPipeline_r(0); -- a read or write operation is done
-----------------------------------------------------------
-- manage row activation
-----------------------------------------------------------
-- request a row activation operation if the row of the current address
-- does not match the currently active row in the bank, or if no row
-- in the bank is currently active
if (bank /= activeBank_r) or (row /= activeRow_r(bankIndex)) or (activeFlag_r(bankIndex) = NO) then
doActivate <= YES;
else
doActivate <= NO;
end if;
-----------------------------------------------------------
-- manage self-refresh
-----------------------------------------------------------
-- enter self-refresh if neither a read or write is requested for 10000 consecutive cycles.
if (rd = YES) or (wr = YES) then
-- any read or write resets NOP counter and exits self-refresh state
nopCntr_x <= 0;
doSelfRfsh <= NO;
elsif nopCntr_r /= 10000 then
-- increment NOP counter whenever there is no read or write operation
nopCntr_x <= nopCntr_r + 1;
doSelfRfsh <= NO;
else
-- start self-refresh when counter hits maximum NOP count and leave counter unchanged
nopCntr_x <= nopCntr_r;
doSelfRfsh <= YES;
end if;
-----------------------------------------------------------
-- update the timers
-----------------------------------------------------------
-- row activation timer
if rasTimer_r /= 0 then
-- decrement a non-zero timer and set the flag
-- to indicate the row activation is still inprogress
rasTimer_x <= rasTimer_r - 1;
activateInProgress <= YES;
else
-- on timeout, keep the timer at zero and reset the flag
-- to indicate the row activation operation is done
rasTimer_x <= rasTimer_r;
activateInProgress <= NO;
end if;
-- write operation timer
if wrTimer_r /= 0 then
-- decrement a non-zero timer and set the flag
-- to indicate the write operation is still inprogress
wrTimer_x <= wrTimer_r - 1;
wrInPRogress <= YES;
else
-- on timeout, keep the timer at zero and reset the flag that
-- indicates a write operation is in progress
wrTimer_x <= wrTimer_r;
wrInPRogress <= NO;
end if;
-- refresh timer
if refTimer_r /= 0 then
refTimer_x <= refTimer_r - 1;
else
-- on timeout, reload the timer with the interval between row refreshes
-- and increment the counter for the number of row refreshes that are needed
refTimer_x <= REF_CYCLES;
rfshCntr_x <= rfshCntr_r + 1;
end if;
-- main timer for sequencing SDRAM operations
if timer_r /= 0 then
-- decrement the timer and do nothing else since the previous operation has not completed yet.
timer_x <= timer_r - 1;
else
-- the previous operation has completed once the timer hits zero
timer_x <= timer_r; -- by default, leave the timer at zero
-----------------------------------------------------------
-- compute the next state and outputs
-----------------------------------------------------------
case state_r is
-----------------------------------------------------------
-- let clock stabilize and then wait for the SDRAM to initialize
-----------------------------------------------------------
when INITWAIT =>
-- wait for SDRAM power-on initialization once the clock is stable
timer_x <= INIT_CYCLES; -- set timer for initialization duration
state_x <= INITPCHG;
-----------------------------------------------------------
-- precharge all SDRAM banks after power-on initialization
-----------------------------------------------------------
when INITPCHG =>
cmd_x <= PCHG_CMD;
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for precharge operation duration
rfshCntr_x <= RFSH_OPS; -- set counter for refresh ops needed after precharge
state_x <= INITRFSH;
-----------------------------------------------------------
-- refresh the SDRAM a number of times after initial precharge
-----------------------------------------------------------
when INITRFSH =>
cmd_x <= RFSH_CMD;
timer_x <= RFC_CYCLES; -- set timer to refresh operation duration
rfshCntr_x <= rfshCntr_r - 1; -- decrement refresh operation counter
if rfshCntr_r = 1 then
state_x <= INITSETMODE; -- set the SDRAM mode once all refresh ops are done
end if;
-----------------------------------------------------------
-- set the mode register of the SDRAM
-----------------------------------------------------------
when INITSETMODE =>
cmd_x <= MODE_CMD;
sAddr_x <= MODE; -- output mode register bits on the SDRAM address bits
timer_x <= MODE_CYCLES; -- set timer for mode setting operation duration
state_x <= RW;
-----------------------------------------------------------
-- process read/write/refresh operations after initialization is done
-----------------------------------------------------------
when RW =>
-----------------------------------------------------------
-- highest priority operation: row refresh
-- do a refresh operation if the refresh counter is non-zero
-----------------------------------------------------------
if rfshCntr_r /= 0 then
-- wait for any row activations, writes or reads to finish before doing a precharge
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation
state_x <= REFRESHROW; -- refresh the SDRAM after the precharge
end if;
-----------------------------------------------------------
-- do a host-initiated read operation
-----------------------------------------------------------
elsif rd = YES then
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
-- This gives extra time for the row activation circuitry.
if (true) then
-- activate a new row if the current read is outside the active row or bank
if doActivate = YES then
-- activate new row only if all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation
state_x <= ACTIVATE; -- activate the new row after the precharge is done
end if;
-- read from the currently active row if no previous read operation
-- is in progress or if pipeline reads are enabled
-- we can always initiate a read even if a write is already in progress
elsif (rdInProgress = NO) then
cmd_x <= READ_CMD; -- initiate a read of the SDRAM
-- insert a flag into the pipeline shift register that will exit the end
-- of the shift register when the data from the SDRAM is available
rdPipeline_x <= READ & rdPipeline_r(rdPipeline_r'high downto 1);
end if;
end if;
-----------------------------------------------------------
-- do a host-initiated write operation
-----------------------------------------------------------
elsif wr = YES then
-- Wait one clock cycle if the bank address has just changed and each bank has its own active row.
-- This gives extra time for the row activation circuitry.
if (true) then
-- activate a new row if the current write is outside the active row or bank
if doActivate = YES then
-- activate new row only if all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ONE_BANK; -- precharge this bank
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x(bankIndex) <= NO; -- rows in this bank are inactive after a precharge operation
state_x <= ACTIVATE; -- activate the new row after the precharge is done
end if;
-- write to the currently active row if no previous read operations are in progress
elsif rdInProgress = NO then
cmd_x <= WRITE_CMD; -- initiate the write operation
sDataDir_x <= OUTPUT; -- turn on drivers to send data to SDRAM
-- set timer so precharge doesn't occur too soon after write operation
wrTimer_x <= WR_CYCLES;
-- insert a flag into the 1-bit pipeline shift register that will exit on the
-- next cycle. The write into SDRAM is not actually done by that time, but
-- this doesn't matter to the host
wrPipeline_x(0) <= WRITE;
end if;
end if;
-----------------------------------------------------------
-- do a host-initiated self-refresh operation
-----------------------------------------------------------
elsif doSelfRfsh = YES then
-- wait until all previous activations, writes, reads are done
if (activateInProgress = NO) and (wrInProgress = NO) and (rdInProgress = NO) then
cmd_x <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr_x(CMDBIT_POS) <= ALL_BANKS; -- precharge all banks
timer_x <= RP_CYCLES; -- set timer for this operation
activeFlag_x <= (others => NO); -- all rows are inactive after a precharge operation
state_x <= SELFREFRESH; -- self-refresh the SDRAM after the precharge
end if;
-----------------------------------------------------------
-- no operation
-----------------------------------------------------------
else
state_x <= RW; -- continue to look for SDRAM operations to execute
end if;
-----------------------------------------------------------
-- activate a row of the SDRAM
-----------------------------------------------------------
when ACTIVATE =>
cmd_x <= ACTIVE_CMD;
sAddr_x <= (others => '0'); -- output the address for the row to be activated
sAddr_x(row'range) <= row;
activeBank_x <= bank;
activeRow_x(bankIndex) <= row; -- store the new active SDRAM row address
activeFlag_x(bankIndex) <= YES; -- the SDRAM is now active
rasTimer_x <= RAS_CYCLES; -- minimum time before another precharge can occur
timer_x <= RCD_CYCLES; -- minimum time before a read/write operation can occur
state_x <= RW; -- return to do read/write operation that initiated this activation
-----------------------------------------------------------
-- refresh a row of the SDRAM
-----------------------------------------------------------
when REFRESHROW =>
cmd_x <= RFSH_CMD;
timer_x <= RFC_CYCLES; -- refresh operation interval
rfshCntr_x <= rfshCntr_r - 1; -- decrement the number of needed row refreshes
state_x <= RW; -- process more SDRAM operations after refresh is done
-----------------------------------------------------------
-- place the SDRAM into self-refresh and keep it there until further notice
-----------------------------------------------------------
when SELFREFRESH =>
if (doSelfRfsh = YES) then
-- keep the SDRAM in self-refresh mode as long as requested and until there is a stable clock
cmd_x <= RFSH_CMD; -- output the refresh command; this is only needed on the first clock cycle
cke_x <= NO; -- disable the SDRAM clock
else
-- else exit self-refresh mode and start processing read and write operations
cke_x <= YES; -- restart the SDRAM clock
rfshCntr_x <= 0; -- no refreshes are needed immediately after leaving self-refresh
activeFlag_x <= (others => NO); -- self-refresh deactivates all rows
timer_x <= XSR_CYCLES; -- wait this long until read and write operations can resume
state_x <= RW;
end if;
-----------------------------------------------------------
-- unknown state
-----------------------------------------------------------
when others =>
state_x <= INITWAIT; -- reset state if in erroneous state
end case;
end if;
end process combinatorial;
-----------------------------------------------------------
-- update registers on the appropriate clock edge
-----------------------------------------------------------
update : process(clk_ok, clk)
begin
if clk_ok = NO then
-- asynchronous reset
state_r <= INITWAIT;
activeFlag_r <= (others => NO);
rfshCntr_r <= 0;
timer_r <= 0;
refTimer_r <= REF_CYCLES;
rasTimer_r <= 0;
wrTimer_r <= 0;
nopCntr_r <= 0;
rdPipeline_r <= (others => '0');
wrPipeline_r <= (others => '0');
cke_r <= NO;
cmd_r <= NOP_CMD;
ba_r <= (others => '0');
sAddr_r <= (others => '0');
sData_r <= (others => '0');
sDataDir_r <= INPUT;
hDOut_r <= (others => '0');
elsif rising_edge(clk) then
state_r <= state_x;
activeBank_r <= activeBank_x;
activeRow_r <= activeRow_x;
activeFlag_r <= activeFlag_x;
rfshCntr_r <= rfshCntr_x;
timer_r <= timer_x;
refTimer_r <= refTimer_x;
rasTimer_r <= rasTimer_x;
wrTimer_r <= wrTimer_x;
nopCntr_r <= nopCntr_x;
rdPipeline_r <= rdPipeline_x;
wrPipeline_r <= wrPipeline_x;
cke_r <= cke_x;
cmd_r <= cmd_x;
ba_r <= ba_x;
sAddr_r <= sAddr_x;
sData_r <= sData_x;
sDataDir_r <= sDataDir_x;
hDOut_r <= hDOut_x;
end if;
end process update;
end arch;
|
bsd-2-clause
|
42cd4bb9945989bd3472aa9392fb4ed1
| 0.511807 | 4.819545 | false | false | false | false |
mitchsm/nvc
|
test/parse/protected.vhd
| 4 | 728 |
package p is
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
procedure decrement (N: Integer := 1) is
begin
counter := counter - N;
end procedure decrement;
impure function value return Integer is
begin
return counter;
end function value;
end protected body;
end package;
|
gpl-3.0
|
0c762fffc85155b389e7f0120e048c5e
| 0.601648 | 5.473684 | false | false | false | false |
mitchsm/nvc
|
test/sem/seq.vhd
| 4 | 5,320 |
entity seq is
end entity;
architecture test of seq is
begin
-- If statements
process is
variable v : integer;
begin
if true then -- OK
report "hello";
end if;
if 1 then -- Not boolean
end if;
if false then
x := 5; -- Error in statement
end if;
if true or false then
null;
else
v := true; -- Error in else part
end if;
if false then
null;
elsif true then
null;
elsif x > 2 then
g := v; -- Error
else
v := 1;
end if;
end process;
-- Null statements
process is
begin
null;
end process;
-- Return statements
process is
begin
return 1; -- Error
end process;
-- While statements
process is
variable n : integer := 5;
begin
while n > 0 loop -- OK
n := n - 1;
end loop;
loop -- OK
null;
end loop;
loop
return 5; -- Error
end loop;
while 5 loop -- Error
null;
end loop;
end process;
-- For
process is
variable v : integer;
begin
for i in 0 to 10 loop -- OK
v := i + 1;
end loop;
for i in bit'range loop -- OK
null;
end loop;
for i in x'range loop -- Error
null;
end loop;
end process;
-- Case
process is
type letter is (A, B, C);
variable l : letter;
variable v : bit_vector(0 to 3);
constant k : bit := '1';
variable n : bit;
variable i : integer;
begin
l := A;
case l is -- OK
when a =>
null;
when b | c =>
null;
end case;
case l is -- OK
when a =>
null;
when others =>
null;
end case;
case l is -- Others not last
when others =>
null;
when a =>
null;
end case;
case l is
when l => -- Not locally static
null;
when others =>
end case;
case v is
when "0101" => -- OK
null;
when "1101" => -- OK
null;
end case;
case v is
when (0 to 3 => k) => -- OK
null;
when (0 to 3 => n) => -- Not locally static
null;
end case;
case i is
when 1 => -- OK
null;
when integer'(5) => -- OK
null;
when (1 + 5) * 7 => -- OK
null;
when i + 2 => -- Not locally static
null;
end case;
case bit is -- Error
when '1' => null;
when '0' => null;
end case;
case i is
when 1 to 6 => -- OK
null;
when 7 to 6.1612 => -- Error
null;
end case;
case i is
when n to k => -- Error
null;
end case;
case i is
when 1 to i => -- Error
null;
end case;
end process;
-- Exit
process is
begin
loop
exit when false; -- OK
exit when 1; -- Not boolean
end loop;
end process;
-- Procedure call
process is
procedure add1(x : in integer; y : out integer) is
begin
y := x + 1;
end procedure;
variable a, b : integer;
begin
add1(a, b); -- OK
add1(1, b); -- OK
add1(3, 6); -- Error
end process;
-- Next
process is
begin
loop
next when false; -- OK
next when 1; -- Not boolean
next; -- OK
end loop;
next; -- Not in loop
l1: loop
next foo; -- Not a label
end loop;
l2: loop
l3: loop
l4: loop
next l2; -- OK
end loop;
end loop;
end loop;
end process;
-- Statement labels
dup: process is begin end process;
dup: process is begin end process;
-- Loop over enumeration
process is
begin
for c in character loop -- OK
end loop;
for c in integer loop -- OK
end loop;
for c in real loop -- Error
end loop;
end process;
end architecture;
|
gpl-3.0
|
7cd0374f19ab4f8ed85c4a903dd5e1d1
| 0.353383 | 5.081184 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/srl_fifo_32_wt.vhd
| 1 | 6,712 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : srl_fifo_32_wt.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity srl_fifo_32_wt is
generic (
C_FAMILY : string := "spartan6";
WIDTH : integer := 16);
port (
rst : in std_logic;
clk : in std_logic;
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic);
end srl_fifo_32_wt;
architecture rtl of srl_fifo_32_wt is
constant ADDR_WIDTH : integer := 5;
constant CNT_MAX : integer := 2**ADDR_WIDTH;
constant FIFO_CNT_WIDTH : integer := ADDR_WIDTH+1;
signal addr : unsigned(ADDR_WIDTH-1 downto 0);
signal fifo_cnt_i : unsigned(FIFO_CNT_WIDTH-1 downto 0);
signal fifo_re : std_logic;
signal fifo_we : std_logic;
signal empty_i : std_logic;
signal mem_out : std_logic_vector(WIDTH-1 downto 0);
signal din_rdy_i : std_logic;
signal rd_en : std_logic;
signal dout_vld_i : std_logic;
begin
MEM_GEN : for i in 0 to WIDTH-1 generate
begin
SRL_I : SRLC32E
generic map (
INIT => x"00000000")
port map (
D => din(i),
CE => fifo_we,
CLK => clk,
A => std_logic_vector(addr),
Q => mem_out(i),
Q31 => open);
end generate;
process(clk)
begin
if (clk'event and clk = '1') then
if(rst = '1') then
dout <= (others => '0');
elsif(fifo_re = '1') then
dout <= mem_out;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
fifo_re <= rd_en and not(empty_i);
fifo_we <= din_vld and din_rdy_i;
process(clk)
begin
if (clk'event and clk = '1') then
if(rst = '1') then
fifo_cnt_i <= (others => '0');
addr <= (others => '1');
elsif(fifo_we = '1' and fifo_re = '0') then
fifo_cnt_i <= fifo_cnt_i + 1;
addr <= addr + 1;
elsif(fifo_we = '0' and fifo_re = '1') then
fifo_cnt_i <= fifo_cnt_i - 1;
addr <= addr - 1;
end if;
end if;
end process;
process(clk)
begin
if (clk'event and clk = '1') then
if(rst = '1') then
empty_i <= '1';
else
if(fifo_cnt_i(FIFO_CNT_WIDTH-1 downto 1) = 0) then -- cnt = 0 or 1
empty_i <= not(fifo_we) and (fifo_re or not(fifo_cnt_i(0)));
else
empty_i <= '0';
end if;
end if;
end if;
end process;
process(clk)
constant ones : unsigned(addr'range) := (others => '1');
begin
if (clk'event and clk = '1') then
if(rst = '1') then
din_rdy_i <= '0';
else
if(fifo_cnt_i(FIFO_CNT_WIDTH-1) = '1') then -- cnt = MAX
din_rdy_i <= (fifo_re);
elsif(fifo_cnt_i(addr'range) = ones) then -- cnt = MAX-1
din_rdy_i <= not(not(fifo_re) and fifo_we);
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(clk, rst)
begin
if(rst = '1') then
dout_vld_i <= '0';
elsif(clk'event and clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
end rtl;
|
mit
|
a14a68483dfabf405a317c4354bf7fcc
| 0.5514 | 3.824501 | false | false | false | false |
blutsvente/MIX
|
test/results/bitsplice/vhdportsort/inst_eb_e-rtl-a.vhd
| 1 | 4,055 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Wed Jun 7 17:05:33 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta -bak ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-rtl-a.vhd,v 1.2 2006/06/22 07:19:59 wig Exp $
-- $Date: 2006/06/22 07:19:59 $
-- $Log: inst_eb_e-rtl-a.vhd,v $
-- Revision 1.2 2006/06/22 07:19:59 wig
-- Updated testcases and extended MixTest.pl to also verify number of created files.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.89 2006/05/23 06:48:05 wig Exp
--
-- Generator: mix_0.pl Revision: 1.45 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eb_e
--
architecture rtl of inst_eb_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_eba_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_eba_e
mbist_aci_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_vcd_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
c_addr_i : in std_ulogic_vector(12 downto 0);
c_bus_i : in std_ulogic_vector(31 downto 0) -- C-Businterface
-- End of Generated Port for Entity inst_eba_e
);
end component;
-- ---------
component inst_ebb_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ebb_e
mbist_sum_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
c_addr_i : in std_ulogic_vector(12 downto 0);
c_bus_i : in std_ulogic_vector(31 downto 0) -- CPUInterface
-- End of Generated Port for Entity inst_ebb_e
);
end component;
-- ---------
component inst_ebc_e
-- No Generated Generics
-- Generated Generics for Entity inst_ebc_e
-- End of Generated Generics for Entity inst_ebc_e
port (
-- Generated Port for Entity inst_ebc_e
c_addr : in std_ulogic_vector(12 downto 0);
c_bus_in : in std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity inst_ebc_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal c_addr : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal c_bus_in : std_ulogic_vector(31 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
c_addr <= p_mix_c_addr_12_0_gi; -- __I_I_BUS_PORT
c_bus_in <= p_mix_c_bus_in_31_0_gi; -- __I_I_BUS_PORT
p_mix_tmi_sbist_fail_12_10_go(2 downto 0) <= tmi_sbist_fail(12 downto 10); -- __I_O_SLICE_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_eba
inst_eba: inst_eba_e
port map (
c_addr_i => c_addr,
c_bus_i => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
mbist_aci_fail_o => tmi_sbist_fail(10),
mbist_vcd_fail_o => tmi_sbist_fail(11)
);
-- End of Generated Instance Port Map for inst_eba
-- Generated Instance Port Map for inst_ebb
inst_ebb: inst_ebb_e
port map (
c_addr_i => c_addr,
c_bus_i => c_bus_in, -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
mbist_sum_fail_o => tmi_sbist_fail(12)
);
-- End of Generated Instance Port Map for inst_ebb
-- Generated Instance Port Map for inst_ebc
inst_ebc: inst_ebc_e
port map (
c_addr => c_addr,
c_bus_in => c_bus_in -- CBUSinterfacecpui/finputsCPUInterface (X2)C-BusinterfaceCPUinterface
);
-- End of Generated Instance Port Map for inst_ebc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
46dbe473c65683420d70c455f74c9d89
| 0.627867 | 2.975055 | false | false | false | false |
mitchsm/nvc
|
lib/synopsys/std_logic_misc.vhd
| 4 | 32,986 |
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
gpl-3.0
|
c9149984462178f2bc5715903c0c38f4
| 0.406597 | 3.366605 | false | false | false | false |
mitchsm/nvc
|
test/regress/wait2.vhd
| 5 | 904 |
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert now = 3 ns report "i";
report "done proc1";
wait;
end process;
proc2: process is
begin
wait for 1500 ps;
assert now = 1500 ps report "c";
wait for 1 ns;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "e";
wait for 500 ps;
assert now = 3 ns report "f";
wait for 0 fs;
assert now = 3000 ps report "g";
report "done proc2";
wait;
end process;
end architecture;
|
gpl-3.0
|
9745ded6e03ea5a1d8e86722aa33e9b2
| 0.52323 | 3.964912 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/ios_e-rtl-a.vhd
| 1 | 20,767 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ios_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-rtl-a.vhd,v 1.5 2006/07/05 10:01:22 wig Exp $
-- $Date: 2006/07/05 10:01:22 $
-- $Log: ios_e-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:22 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ios_e
--
architecture rtl of ios_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioblock0_e
-- No Generated Generics
port (
-- Generated Port for Entity ioblock0_e
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_go : out std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic
-- End of Generated Port for Entity ioblock0_e
);
end component;
-- ---------
component ioblock1_e
-- No Generated Generics
port (
-- Generated Port for Entity ioblock1_e
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_nand_out_2_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic
-- End of Generated Port for Entity ioblock1_e
);
end component;
-- ---------
component ioblock2_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component ioblock3_e
-- No Generated Generics
port (
-- Generated Port for Entity ioblock3_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ioblock3_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o1 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_out_2 : std_ulogic;
signal pad_di_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i1_go <= data_i1; -- __I_O_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o1 <= p_mix_data_o1_gi; -- __I_I_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_0 <= p_mix_iosel_0_gi; -- __I_I_BIT_PORT
iosel_1 <= p_mix_iosel_1_gi; -- __I_I_BIT_PORT
iosel_2 <= p_mix_iosel_2_gi; -- __I_I_BIT_PORT
iosel_3 <= p_mix_iosel_3_gi; -- __I_I_BIT_PORT
iosel_4 <= p_mix_iosel_4_gi; -- __I_I_BIT_PORT
iosel_5 <= p_mix_iosel_5_gi; -- __I_I_BIT_PORT
iosel_6 <= p_mix_iosel_6_gi; -- __I_I_BIT_PORT
iosel_7 <= p_mix_iosel_7_gi; -- __I_I_BIT_PORT
iosel_bus <= p_mix_iosel_bus_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
iosel_ms_min <= p_mix_iosel_ms_min_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
pad_di_1 <= p_mix_pad_di_1_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_do_2_go <= pad_do_2; -- __I_O_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
p_mix_pad_en_2_go <= pad_en_2; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioblock_0
ioblock_0: ioblock0_e
port map (
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_6_gi => iosel_6, -- IO_Select
p_mix_iosel_7_gi => iosel_7, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_nand_out_2_go => nand_out_2, -- Links ...
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_en_2_go => pad_en_2 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_0
-- Generated Instance Port Map for ioblock_1
ioblock_1: ioblock1_e
port map (
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_iosel_ms_min_gi => iosel_ms_min, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_nand_out_2_gi => nand_out_2, -- Links ...
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18 -- pad output enable
);
-- End of Generated Instance Port Map for ioblock_1
-- Generated Instance Port Map for ioblock_2
ioblock_2: ioblock2_e
;
-- End of Generated Instance Port Map for ioblock_2
-- Generated Instance Port Map for ioblock_3
ioblock_3: ioblock3_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ioblock_3
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
c8fa0bc858d27a16b6218c324dff3248
| 0.610343 | 2.166163 | false | false | false | false |
agural/FPGA-Oscilloscope
|
osc/altpll0.vhd
| 1 | 18,278 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll0.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll0 IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll0;
ARCHITECTURE SYN OF altpll0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 11,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
clk2_divide_by => 36,
clk2_duty_cycle => 50,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 27777,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=altpll0",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "396.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "36.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "36.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "396.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "36.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "36"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "27777"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
mit
|
884accb54f99844ae7b1c217a419cde9
| 0.699475 | 3.285637 | false | false | false | false |
mitchsm/nvc
|
test/group/issue72.vhd
| 4 | 551 |
package pack1 is
type ma_t is array(1 downto 0) of bit_vector(1 downto 0);
end pack1;
use work.pack1.all;
entity arraysub is
generic(par1: bit_vector(3 downto 0) := "1111");
end entity;
architecture test of arraysub is
signal s1, s2: ma_t;
begin
s1(1)<=par1(1 downto 0);
s1(0)<=par1(3 downto 2);
s2(1 downto 1) <= ( 0 => par1(3 downto 2) );
s2(0 downto 0) <= ( 0 => par1(1 downto 0) );
process is
begin
wait for 1 ns;
assert s1 = ( "11", "11" );
wait;
end process;
end architecture;
|
gpl-3.0
|
4b37ad13fb05b39eddb5a9d6c666d7f3
| 0.584392 | 2.915344 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_proc_sys_reset_1_0/sim/zc702_proc_sys_reset_1_0.vhd
| 1 | 5,843 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_1_0;
ARCHITECTURE zc702_proc_sys_reset_1_0_arch OF zc702_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_1_0_arch;
|
mit
|
9a81aad0d172579e949afe2c21ccaccb
| 0.706144 | 3.575887 | false | false | false | false |
blutsvente/MIX
|
test/results/udc/inst_a_e-rtl-a.vhd
| 1 | 2,933 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:33:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_xa_e -- mulitple instantiated
-- No Generated Generics
port (
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end component;
-- ---------
component inst_ab_e -- ab instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
port_ab_i : in std_ulogic_vector(7 downto 0) -- vector test bb to ab
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic0_0 : std_ulogic;
signal signal_aa_ba : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
udc: THIS GOES TO BODY of inst_a_i;
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic0_0 <= '0';
p_mix_signal_aa_ba_go <= signal_aa_ba; -- __I_O_BIT_PORT
signal_bb_ab <= p_mix_signal_bb_ab_gi; -- __I_I_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa_i
inst_aa_i: inst_xa_e -- mulitple instantiated
port map (
port_xa_i => mix_logic0_0, -- tie to low to create port
port_xa_o => signal_aa_ba -- signal test aa to ba
);
-- End of Generated Instance Port Map for inst_aa_i
-- Generated Instance Port Map for inst_ab_i
inst_ab_i: inst_ab_e -- ab instance
port map (
port_ab_i => signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_ab_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
1cab94b61062016f5ca81025b1a4eb94
| 0.603137 | 2.998978 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/common.vhd
| 2 | 13,576 |
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package common is
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
type MY_CMD is
record
ALU_OP : std_logic_vector(3 downto 0);
ALU_A_SRC : std_logic_vector(2 downto 0);
ALU_B_SRC : std_logic_vector(1 downto 0);
WRITE_REGS_DEST : std_logic_vector(1 downto 0);
WRITE_RA_OR_NOT : std_logic;
WRITE_IH_OR_NOT : std_logic;
WRITE_SP_OR_NOT : std_logic;
WRITE_T_OR_NOT : std_logic;
WRITE_T_SRC : std_logic;
DATA_MEM_READ_WRITE : std_logic_vector(1 downto 0);
WRITE_DM_DATA_SRC : std_logic_vector(1 downto 0);
REGS_WRITE_OR_NOT : std_logic;
REGS_WRITE_DATA_SRC : std_logic_vector(1 downto 0);
end record;
--
-- Declare constants
constant ZERO : std_logic_vector(15 downto 0) := "0000000000000000";
constant FFFF : std_logic_vector(15 downto 0) := "1111111111111111";
constant EIGHT : std_logic_vector(15 downto 0) := "0000000000001000";
constant ALU_ADD : std_logic_vector(3 downto 0) := "0000";
constant ALU_SUB : std_logic_vector(3 downto 0) := "0001";
constant ALU_AND : std_logic_vector(3 downto 0) := "0010";
constant ALU_OR : std_logic_vector(3 downto 0) := "0011";
constant ALU_XOR : std_logic_vector(3 downto 0) := "0100";
constant ALU_NOT : std_logic_vector(3 downto 0) := "0101";
constant ALU_SLL : std_logic_vector(3 downto 0) := "0110";
constant ALU_SRL : std_logic_vector(3 downto 0) := "0111";
constant ALU_SLA : std_logic_vector(3 downto 0) := "1000";
constant ALU_SRA : std_logic_vector(3 downto 0) := "1001";
constant ALU_ROL : std_logic_vector(3 downto 0) := "1010";
constant ALU_ROR : std_logic_vector(3 downto 0) := "1011";
constant ALU_NEG : std_logic_vector(3 downto 0) := "1100";
constant ALU_NULL : std_logic_vector(3 downto 0) := "1111";
constant ZF_TRUE : std_logic := '1';
constant ZF_FALSE : std_logic := '0';
constant SF_TRUE : std_logic := '1';
constant SF_FALSE : std_logic := '0';
constant JUMP_TRUE : std_logic := '1';
constant JUMP_FALSE : std_logic := '0';
constant REG0 : std_logic_vector(2 downto 0) := "000";
constant REG1 : std_logic_vector(2 downto 0) := "001";
constant REG2 : std_logic_vector(2 downto 0) := "010";
constant REG3 : std_logic_vector(2 downto 0) := "011";
constant REG4 : std_logic_vector(2 downto 0) := "100";
constant REG5 : std_logic_vector(2 downto 0) := "101";
constant REG6 : std_logic_vector(2 downto 0) := "110";
constant REG7 : std_logic_vector(2 downto 0) := "111";
--type 0: last 8 bit, sign_extend
constant CODE_IMM_0_0 : std_logic_vector(4 downto 0) := "00000";
constant CODE_IMM_0_1 : std_logic_vector(4 downto 0) := "00100";
constant CODE_IMM_0_2 : std_logic_vector(4 downto 0) := "00101";
constant CODE_IMM_0_3 : std_logic_vector(4 downto 0) := "01001";
constant CODE_IMM_0_4 : std_logic_vector(4 downto 0) := "01100";
constant CODE_IMM_0_5 : std_logic_vector(4 downto 0) := "01110";
constant CODE_IMM_0_6 : std_logic_vector(4 downto 0) := "10010";
constant CODE_IMM_0_7 : std_logic_vector(4 downto 0) := "11010";
--type 1: last 8 bit, zero_extend
constant CODE_IMM_1 : std_logic_vector(4 downto 0) := "01101";
--type 2: last 5 bit, sign_extend
constant CODE_IMM_2_0 : std_logic_vector(4 downto 0) := "10011";
constant CODE_IMM_2_1 : std_logic_vector(4 downto 0) := "11011";
--type 3: last 11 bit, sign_extend
constant CODE_IMM_3 : std_logic_vector(4 downto 0) := "00010";
--type 4: last 4 bit, sign_extend;
constant CODE_IMM_4 : std_logic_vector(4 downto 0) := "01000";
--type 5: from 4 downto 2 bit, zero_extend, change 0 to 8
constant CODE_IMM_5 : std_logic_vector(4 downto 0) := "00110";
--begin of xjl area
--controller command
constant ALU_A_SRC_A : std_logic_vector(2 downto 0) := "000";
constant ALU_A_SRC_IMM : std_logic_vector(2 downto 0) := "001";
constant ALU_A_SRC_ZERO : std_logic_vector(2 downto 0) := "010";
constant ALU_A_SRC_SP : std_logic_vector(2 downto 0) := "011";
constant ALU_A_SRC_PC : std_logic_vector(2 downto 0) := "100";
constant ALU_A_SRC_IH : std_logic_vector(2 downto 0) := "101";
constant ALU_B_SRC_B : std_logic_vector(1 downto 0) := "00";
constant ALU_B_SRC_IMM : std_logic_vector(1 downto 0) := "01";
constant ALU_B_SRC_ZERO : std_logic_vector(1 downto 0) := "10";
constant WRITE_REGS_DEST_RS : std_logic_vector(1 downto 0) := "00";
constant WRITE_REGS_DEST_RT : std_logic_vector(1 downto 0) := "01";
constant WRITE_REGS_DEST_RD : std_logic_vector(1 downto 0) := "10";
constant WRITE_DM_DATA_SRC_A : std_logic_vector(1 downto 0) := "00";
constant WRITE_DM_DATA_SRC_B : std_logic_vector(1 downto 0) := "01";
constant WRITE_DM_DATA_SRC_Z : std_logic_vector(1 downto 0) := "10";
constant WRITE_RA_YES : std_logic := '1';
constant WRITE_RA_NO : std_logic := '0';
constant WRITE_IH_YES : std_logic := '1';
constant WRITE_IH_NO : std_logic := '0';
constant WRITE_T_YES : std_logic := '1';
constant WRITE_T_NO : std_logic := '0';
constant T_SRC_IS_SF : std_logic := '1';
constant T_SRC_IS_NOT_ZF : std_logic := '0';
constant WRITE_SP_YES : std_logic := '1';
constant WRITE_SP_NO : std_logic := '0';
constant MEM_READ : std_logic_vector(1 downto 0) := "00";
constant MEM_WRITE : std_logic_vector(1 downto 0) := "01";
constant MEM_NONE : std_logic_vector(1 downto 0) := "10";
constant WRITE_REGS_YES : std_logic := '1';
constant WRITE_REGS_NO : std_logic := '0';
constant REGS_WRITE_DATA_SRC_ALU_RESULT : std_logic_vector(1 downto 0) := "00";
constant REGS_WRITE_DATA_SRC_DM_DATA : std_logic_vector(1 downto 0) := "01";
constant REGS_WRITE_DATA_SRC_IH_REG : std_logic_vector(1 downto 0) := "10";
constant REGS_WRITE_DATA_SRC_PC_REG : std_logic_vector(1 downto 0) := "11";
-- forward unit command
constant STALL_YES : std_logic := '1';
constant STALL_NO : std_logic := '0';
constant ALU_A_SRC_SELECT_FINAL_ORIGIN : std_logic_vector(1 downto 0) := "00";
constant ALU_A_SRC_SELECT_FINAL_EXE_MEM_REG : std_logic_vector(1 downto 0) := "01";
constant ALU_A_SRC_SELECT_FINAL_MEM_WB_REG : std_logic_vector(1 downto 0) := "10";
constant ALU_B_SRC_SELECT_FINAL_ORIGIN : std_logic_vector(1 downto 0) := "00";
constant ALU_B_SRC_SELECT_FINAL_EXE_MEM_REG : std_logic_vector(1 downto 0) := "01";
constant ALU_B_SRC_SELECT_FINAL_MEM_WB_REG : std_logic_vector(1 downto 0) := "10";
-- hazard detector command
constant WRITE_PC_YES : std_logic := '1';
constant WRITE_PC_NO : std_logic := '0';
constant NEW_PC_SRC_SELEC_PC_ADD_ONE : std_logic_vector(1 downto 0) := "00";
constant NEW_PC_SRC_SELEC_PC_ADD_IMM : std_logic_vector(1 downto 0) := "01";
constant NEW_PC_SRC_SELEC_REG_A : std_logic_vector(1 downto 0) := "10";
constant WRITE_IR_YES : std_logic := '1';
constant WRITE_IR_NO : std_logic := '0';
constant WRITE_IR_SRC_SELEC_ORIGIN : std_logic := '0';
constant WRITE_IR_SRC_SELEC_NOP : std_logic := '1';
constant COMMAND_ORIGIN : std_logic := '0';
constant COMMAND_NOP : std_logic := '1';
constant DM_DATA_RESULT_DM : std_logic := '0';
constant DM_DATA_RESULT_IM : std_logic := '1';
constant IM_ADDR_PC : std_logic := '0';
constant IM_ADDR_ALU_RESULT : std_logic := '1';
constant IM_DATA_Z : std_logic := '0';
constant IM_DATA_ALU_RESULT : std_logic := '1';
-- data constant
constant HIGH_RESIST : std_logic_vector(15 downto 0) := "ZZZZZZZZZZZZZZZZ";
constant INST_DATA_MEM_ADDR_EDGE : integer := 32768;
constant NOP_INST : std_logic_vector(15 downto 0) := "0000100000000000";
constant COM_STATUS_ADDR : std_logic_vector(15 downto 0) := "1011111100000001";
constant COM_DATA_ADDR : std_logic_vector(15 downto 0) := "1011111100000000";
constant DATA_MEM_BEGIN : std_logic_vector(15 downto 0) := "1000000000000000";
--constant DEFAULT_VALUE : std_logic_vector(15 downto 0) := "";
-- instruction type distinct constant
constant INST_CODE_ADDSP3 : std_logic_vector(4 downto 0) := "00000";
constant INST_CODE_NOP : std_logic_vector(4 downto 0) := "00001";
constant INST_CODE_B : std_logic_vector(4 downto 0) := "00010";
constant INST_CODE_BEQZ : std_logic_vector(4 downto 0) := "00100";
constant INST_CODE_BNEZ : std_logic_vector(4 downto 0) := "00101";
constant INST_CODE_SLL_SRA : std_logic_vector(4 downto 0) := "00110";
constant INST_FUNC_SLL : std_logic_vector(1 downto 0) := "00";
constant INST_FUNC_SRA : std_logic_vector(1 downto 0) := "11";
constant INST_CODE_ADDIU3 : std_logic_vector(4 downto 0) := "01000";
constant INST_CODE_ADDIU : std_logic_vector(4 downto 0) := "01001";
constant INST_CODE_ADDSP_BTEQZ_MTSP : std_logic_vector(4 downto 0) := "01100";
constant INST_RS_ADDSP : std_logic_vector(2 downto 0) := "011";
constant INST_RS_BTEQZ : std_logic_vector(2 downto 0) := "000";
constant INST_RS_MTSP : std_logic_vector(2 downto 0) := "100";
constant INST_CODE_LI : std_logic_vector(4 downto 0) := "01101";
constant INST_CODE_CMPI : std_logic_vector(4 downto 0) := "01110";
constant INST_CODE_LW_SP : std_logic_vector(4 downto 0) := "10010";
constant INST_CODE_LW : std_logic_vector(4 downto 0) := "10011";
constant INST_CODE_SW_SP : std_logic_vector(4 downto 0) := "11010";
constant INST_CODE_SW : std_logic_vector(4 downto 0) := "11011";
constant INST_CODE_ADDU_SUBU : std_logic_vector(4 downto 0) := "11100";
constant INST_FUNC_ADDU : std_logic_vector(1 downto 0) := "01";
constant INST_FUNC_SUBU : std_logic_vector(1 downto 0) := "11";
constant INST_CODE_AND_TO_SLT : std_logic_vector(4 downto 0) := "11101";
constant INST_RD_FUNC_AND : std_logic_vector(4 downto 0) := "01100";
constant INST_RD_FUNC_CMP : std_logic_vector(4 downto 0) := "01010";
constant INST_RD_FUNC_JALR_JR_MFPC : std_logic_vector(4 downto 0) := "00000";
constant INST_RT_JALR : std_logic_vector(2 downto 0) := "110";
constant INST_RT_JR : std_logic_vector(2 downto 0) := "000";
constant INST_RT_MFPC : std_logic_vector(2 downto 0) := "010";
constant INST_RD_FUNC_NEG : std_logic_vector(4 downto 0) := "01011";
constant INST_RD_FUNC_OR : std_logic_vector(4 downto 0) := "01101";
constant INST_RD_FUNC_SLT : std_logic_vector(4 downto 0) := "00010";
constant INST_CODE_MFIH_MTIH : std_logic_vector(4 downto 0) := "11110";
constant INST_FUNC_MFIH : std_logic_vector(1 downto 0) := "00";
constant INST_FUNC_MTIH : std_logic_vector(1 downto 0) := "01";
--end of xjl area
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
function get_cmd (
ALU_OP : in std_logic_vector(3 downto 0);
ALU_A_SRC : in std_logic_vector(2 downto 0);
ALU_B_SRC : in std_logic_vector(1 downto 0);
WRITE_REGS_DEST : in std_logic_vector(1 downto 0);
WRITE_RA_OR_NOT : in std_logic;
WRITE_IH_OR_NOT : in std_logic;
WRITE_SP_OR_NOT : in std_logic;
WRITE_T_OR_NOT : in std_logic;
WRITE_T_SRC : in std_logic;
DATA_MEM_READ_WRITE : in std_logic_vector(1 downto 0);
WRITE_DM_DATA_SRC : in std_logic_vector(1 downto 0);
REGS_WRITE_OR_NOT : in std_logic;
REGS_WRITE_DATA_SRC : in std_logic_vector(1 downto 0)
) return MY_CMD;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
end common;
package body common is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
function get_cmd (
ALU_OP : in std_logic_vector(3 downto 0);
ALU_A_SRC : in std_logic_vector(2 downto 0);
ALU_B_SRC : in std_logic_vector(1 downto 0);
WRITE_REGS_DEST : in std_logic_vector(1 downto 0);
WRITE_RA_OR_NOT : in std_logic;
WRITE_IH_OR_NOT : in std_logic;
WRITE_SP_OR_NOT : in std_logic;
WRITE_T_OR_NOT : in std_logic;
WRITE_T_SRC : in std_logic;
DATA_MEM_READ_WRITE : in std_logic_vector(1 downto 0);
WRITE_DM_DATA_SRC : in std_logic_vector(1 downto 0);
REGS_WRITE_OR_NOT : in std_logic;
REGS_WRITE_DATA_SRC : in std_logic_vector(1 downto 0)
) return MY_CMD is
variable cmd : MY_CMD;
begin
cmd.ALU_OP := ALU_OP;
cmd.ALU_A_SRC := ALU_A_SRC;
cmd.ALU_B_SRC := ALU_B_SRC;
cmd.WRITE_REGS_DEST := WRITE_REGS_DEST;
cmd.WRITE_RA_OR_NOT := WRITE_RA_OR_NOT;
cmd.WRITE_IH_OR_NOT := WRITE_IH_OR_NOT;
cmd.WRITE_SP_OR_NOT := WRITE_SP_OR_NOT;
cmd.WRITE_T_OR_NOT := WRITE_T_OR_NOT;
cmd.WRITE_T_SRC := WRITE_T_SRC;
cmd.DATA_MEM_READ_WRITE := DATA_MEM_READ_WRITE;
cmd.WRITE_DM_DATA_SRC := WRITE_DM_DATA_SRC;
cmd.REGS_WRITE_OR_NOT := REGS_WRITE_OR_NOT;
cmd.REGS_WRITE_DATA_SRC := REGS_WRITE_DATA_SRC;
return cmd;
end get_cmd;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
end common;
|
apache-2.0
|
49193ec23ad56379be2cfa66f4fc8e60
| 0.656674 | 2.818352 | false | false | false | false |
mitchsm/nvc
|
test/regress/func13.vhd
| 5 | 885 |
entity func13 is
end entity;
architecture test of func13 is
signal five : integer := 5;
signal zero : integer := 0;
begin
process is
variable x : integer;
variable y : bit_vector(7 downto 0);
impure function add_to_x(y : integer) return integer is
impure function do_it return integer is
begin
report integer'image(x) & " + " & integer'image(y);
return x + y;
end function;
begin
return do_it;
end function;
impure function get_bit(n : integer) return bit is
begin
return y(n);
end function;
begin
x := 2;
assert add_to_x(five) = 7;
x := 3;
assert add_to_x(five) = 8;
y := X"00";
assert get_bit(zero) = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
62f093b30a8288a1bc65423387bf45f7
| 0.514124 | 4.041096 | false | false | false | false |
HackLinux/THCO-MIPS-CPU
|
src/CPU_CORE.vhd
| 2 | 43,733 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:28:54 11/19/2013
-- Design Name:
-- Module Name: CPU_CORE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.common.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU_CORE is
Port ( CLK_IN : in STD_LOGIC;
RAM1_Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM1_EN : out STD_LOGIC;
RAM1_WE : out STD_LOGIC;
RAM1_OE : out STD_LOGIC;
RAM1_Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2_Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM2_EN : out STD_LOGIC;
RAM2_WE : out STD_LOGIC;
RAM2_OE : out STD_LOGIC;
RAM2_Data : inout STD_LOGIC_VECTOR (15 downto 0);
com_data_ready : in STD_LOGIC;
com_rdn : out STD_LOGIC;
com_tbre : in STD_LOGIC;
com_tsre : in STD_LOGIC;
com_wrn : out STD_LOGIC;
DISP1 : inout std_logic_vector(6 downto 0) := "0111111";
DISP2 : inout std_logic_vector(6 downto 0) := "0111111";
LED : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000");
end CPU_CORE;
architecture Behavioral of CPU_CORE is
COMPONENT CLK_MODULE
Port ( CLK_IN : in STD_LOGIC;
CLK : inout STD_LOGIC
);
END COMPONENT;
COMPONENT PC_Register
Port ( PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_OR_NOT : in STD_LOGIC;
CLK : in STD_LOGIC
);
END COMPONENT;
COMPONENT MUX_2
Port ( SELEC : in STD_LOGIC;
SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_3
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0);
SELEC : in STD_LOGIC_VECTOR (1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_4
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0);
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0);
SELEC : in STD_LOGIC_VECTOR (1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0));
END COMPONENT;
COMPONENT MUX_6
Port ( SRC_1 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_2 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_3 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_4 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_5 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SRC_6 : in STD_LOGIC_VECTOR (15 downto 0) := ZERO;
SELEC : in STD_LOGIC_VECTOR (2 downto 0) := "111";
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0) := ZERO
);
END COMPONENT;
COMPONENT RAM1_Visitor
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
DataReady: in std_logic;
WriteData: in std_logic_vector(15 downto 0);
TSRE: in std_logic;
TBRE: in std_logic;
---output
RAM1_Enable: out std_logic;
RAM1_ReadEnable: out std_logic;
RAM1_WriteEnable: out std_logic;
SPort_WriteEnable:out std_logic;
SPort_ReadEnable: out std_logic;
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT RAM2_Visitor
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0);
---output
RAM2_Enable: out std_logic := '1';
RAM2_ReadEnable: out std_logic := '1';
RAM2_WriteEnable: out std_logic := '1';
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT PC_Adder
Port ( OLD_PC : in STD_LOGIC_VECTOR (15 downto 0);
NEW_PC : out STD_LOGIC_VECTOR (15 downto 0)
);
END COMPONENT;
COMPONENT IF_ID_Register
Port ( NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_PC_OR_NOT : in STD_LOGIC;
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
CLK : in STD_LOGIC;
INST_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_IR_OR_NOT : in STD_LOGIC;
WRITE_IR_SRC_SELEC : in STD_LOGIC;
INST_OUT_CODE : out STD_LOGIC_VECTOR(4 downto 0);
INST_OUT_RS : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_RT : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_RD : out STD_LOGIC_VECTOR(2 downto 0);
INST_OUT_FUNC : out STD_LOGIC_VECTOR(1 downto 0));
END COMPONENT;
COMPONENT Imm_Extend
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
rd : in STD_LOGIC_VECTOR(2 downto 0);
func : in STD_LOGIC_VECTOR(1 downto 0);
imm : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT adder
port(
pc : in STD_LOGIC_VECTOR(15 downto 0);
imm : in STD_LOGIC_VECTOR(15 downto 0);
res : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Hazard_Detector
Port ( STALL_OR_NOT_FU : in STD_LOGIC;
CUR_INST_CODE : in STD_LOGIC_VECTOR (4 downto 0);
CUR_INST_RS : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_RT : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_RD : in STD_LOGIC_VECTOR (2 downto 0);
CUR_INST_FUNC : in STD_LOGIC_VECTOR (1 downto 0);
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0);
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_LAST_VISIT_DM_OR_NOT : in STD_LOGIC_VECTOR(1 downto 0);
LAST_LAST_DM_VISIT_ADDR : in STD_LOGIC_VECTOR (15 downto 0);
CUR_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0);
CUR_DM_WRITE_DATA_SRC : in STD_LOGIC_VECTOR(1 downto 0);
JUMP_OR_NOT : in STD_LOGIC;
WRITE_PC_OR_NOT : out STD_LOGIC;
NEW_PC_SRC_SELEC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_IR_OR_NOT : out STD_LOGIC;
WRITE_IR_SRC_SELEC : out STD_LOGIC;
COMMAND_ORIGIN_OR_NOP : out STD_LOGIC;
DM_DATA_RESULT_SELEC : out STD_LOGIC;
IM_ADDR_SELEC : out STD_LOGIC;
IM_DATA_SELEC : out STD_LOGIC;
IM_READ_WRITE_SELEC : out STD_LOGIC_VECTOR(1 downto 0)
);
END COMPONENT;
COMPONENT Controller
Port ( INST_CODE : in STD_LOGIC_VECTOR(4 downto 0);
INST_RS : in STD_LOGIC_VECTOR(2 downto 0);
INST_RT : in STD_LOGIC_VECTOR(2 downto 0);
INST_RD : in STD_LOGIC_VECTOR(2 downto 0);
INST_FUNC : in STD_LOGIC_VECTOR(1 downto 0);
ALU_OP : out STD_LOGIC_VECTOR (3 downto 0);
ALU_A_SRC : out STD_LOGIC_VECTOR (2 downto 0);
ALU_B_SRC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_REGS_DEST : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_DM_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0);
WRITE_RA_OR_NOT : out STD_LOGIC;
WRITE_IH_OR_NOT : out STD_LOGIC;
WRITE_T_OR_NOT : out STD_LOGIC;
WRITE_SP_OR_NOT : out STD_LOGIC;
WRITE_T_SRC : out STD_LOGIC;
DATA_MEM_READ_WRITE : out STD_LOGIC_VECTOR(1 downto 0);
REGS_WRITE_OR_NOT : out STD_LOGIC;
REGS_WRITE_DATA_SRC : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT Common_Register
port(
clk : in STD_LOGIC;
rs : in STD_LOGIC_VECTOR(2 downto 0);
rt : in STD_LOGIC_VECTOR(2 downto 0);
write_flag : in STD_LOGIC;
write_reg : in STD_LOGIC_VECTOR(2 downto 0);
write_data : in STD_LOGIC_VECTOR(15 downto 0);
a : out STD_LOGIC_VECTOR(15 downto 0);
b : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Comparator
port(
code : in STD_LOGIC_VECTOR(4 downto 0);
write_t : in STD_LOGIC;
t : in STD_LOGIC_VECTOR(15 downto 0);
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(15 downto 0);
jump : out STD_LOGIC
);
END COMPONENT;
COMPONENT ID_EXE_Register
port(
clk : in STD_LOGIC;
--cmd cmd
command_origin_or_nop : in STD_LOGIC;
--common input
in_pc : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_a : in STD_LOGIC_VECTOR(15 downto 0);
in_reg_b : in STD_LOGIC_VECTOR(15 downto 0);
in_imm : in STD_LOGIC_VECTOR(15 downto 0);
in_rs : in STD_LOGIC_VECTOR(2 downto 0);
in_rt : in STD_LOGIC_VECTOR(2 downto 0);
in_rd : in STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
in_alu : in STD_LOGIC_VECTOR(3 downto 0);
in_a_src : in STD_LOGIC_VECTOR(2 downto 0);
in_b_src : in STD_LOGIC_VECTOR(1 downto 0);
in_reg_result : in STD_LOGIC_VECTOR(1 downto 0);
in_mem_src : in STD_LOGIC_VECTOR(1 downto 0);
in_flag_RA : in STD_LOGIC;
in_flag_IH : in STD_LOGIC;
in_flag_T : in STD_LOGIC;
in_flag_SP : in STD_LOGIC;
in_T_src : in STD_LOGIC;
--mem cmd
in_mem_cmd : in STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
in_flag_reg : in STD_LOGIC;
in_reg_src : in STD_LOGIC_VECTOR(1 downto 0);
--common output
out_pc : out STD_LOGIC_VECTOR(15 downto 0);
out_imm : out STD_LOGIC_VECTOR(15 downto 0);
out_reg_a : out STD_LOGIC_VECTOR(15 downto 0);
out_reg_b : out STD_LOGIC_VECTOR(15 downto 0);
--memory data
out_mem_data : out STD_LOGIC_VECTOR(15 downto 0);
--result register
out_res_reg : out STD_LOGIC_VECTOR(2 downto 0);
--exe cmd
out_alu : out STD_LOGIC_VECTOR(3 downto 0);
out_a_src : out STD_LOGIC_VECTOR(2 downto 0);
out_b_src : out STD_LOGIC_VECTOR(1 downto 0);
out_flag_RA : out STD_LOGIC;
out_flag_IH : out STD_LOGIC;
out_flag_T : out STD_LOGIC;
out_flag_SP : out STD_LOGIC;
out_T_src : out STD_LOGIC;
--mem cmd
out_mem_cmd : out STD_LOGIC_VECTOR(1 downto 0);
--wb cmd
out_flag_reg : out STD_LOGIC;
out_reg_src : out STD_LOGIC_VECTOR(1 downto 0);
cur_rs_num : out STD_LOGIC_VECTOR(2 downto 0);
cur_rt_num : out STD_LOGIC_VECTOR(2 downto 0)
);
END COMPONENT;
COMPONENT alu
port(
a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(15 downto 0);
op : in STD_LOGIC_VECTOR(3 downto 0);
zf : out STD_LOGIC;
sf : out STD_LOGIC;
c : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Special_Register
port(
clk : in STD_LOGIC;
T_cmd_write : in STD_LOGIC;
T_cmd_src : in STD_LOGIC;
T_src_SF : in STD_LOGIC;
T_src_ZF : in STD_LOGIC;
RA_cmd_write : in STD_LOGIC;
RA_src : in STD_LOGIC_VECTOR(15 downto 0);
IH_cmd_write : in STD_LOGIC;
IH_src : in STD_LOGIC_VECTOR(15 downto 0);
SP_cmd_write : in STD_LOGIC;
SP_src : in STD_LOGIC_VECTOR(15 downto 0);
T_value : out STD_LOGIC_VECTOR(15 downto 0);
RA_value : out STD_LOGIC_VECTOR(15 downto 0);
IH_value : out STD_LOGIC_VECTOR(15 downto 0);
SP_value : out STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT;
COMPONENT Forward_Unit
Port ( -- current instruction info, if use reg as alu src, conflict may exist
CUR_RS_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0);
CUR_RT_REG_NUM : in STD_LOGIC_VECTOR (2 downto 0);
CUR_ALU_A_SRC_SELECT : in STD_LOGIC_VECTOR (2 downto 0);
CUR_ALU_B_SRC_SELECT : in STD_LOGIC_VECTOR (1 downto 0);
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
LAST_DM_READ_WRITE : in STD_LOGIC_VECTOR(1 downto 0);
-- last last instruction info, if write regs, conflict may exist
LAST_LAST_WRITE_REGS_OR_NOT : in STD_LOGIC;
LAST_LAST_WRITE_REGS_TARGET : in STD_LOGIC_VECTOR (2 downto 0);
STALL_OR_NOT : out STD_LOGIC;
ALU_A_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0);
ALU_B_SRC_SELECT_FINAL : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT EXE_MEM_Register
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_REG_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0);
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0);
DATA_MEM_READ_WRITE_IN : in STD_LOGIC_VECTOR(1 downto 0);
REGS_READ_WRITE_IN : in STD_LOGIC;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0);
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_REG_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DATA_MEM_READ_WRITE_OUT : out STD_LOGIC_VECTOR(1 downto 0);
REGS_READ_WRITE_OUT : out STD_LOGIC;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
COMPONENT MEM_WB_Register
Port ( CLK : in STD_LOGIC;
NEW_PC_IN : in STD_LOGIC_VECTOR (15 downto 0);
WRITE_REGS_NUM_IN : in STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_IN : in STD_LOGIC_VECTOR (15 downto 0);
IH_REG_IN : in STD_LOGIC_VECTOR (15 downto 0);
DM_DATA_IN : in STD_LOGIC_VECTOR (15 downto 0);
REGS_READ_WRITE_IN : in STD_LOGIC;
REGS_WRITE_DATA_SRC_IN : in STD_LOGIC_VECTOR (1 downto 0);
NEW_PC_OUT : out STD_LOGIC_VECTOR (15 downto 0);
WRITE_REGS_NUM_OUT : out STD_LOGIC_VECTOR (2 downto 0);
ALU_RESULT_OUT : out STD_LOGIC_VECTOR (15 downto 0);
IH_REG_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DM_DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0);
REGS_READ_WRITE_OUT : out STD_LOGIC;
REGS_WRITE_DATA_SRC_OUT : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
--controller, all to id/exe reg
signal alu_op_controller : std_logic_vector(3 downto 0) := ALU_NULL;
signal alu_a_src_select_controller : std_logic_vector(2 downto 0) := ALU_A_SRC_ZERO;
signal alu_b_src_select_controller : std_logic_vector(1 downto 0) := ALU_B_SRC_ZERO;
signal write_regs_dest_select_controller : std_logic_vector(1 downto 0) := WRITE_REGS_DEST_RS;
signal write_dm_data_src_select_controller : std_logic_vector(1 downto 0) := WRITE_DM_DATA_SRC_Z;
signal write_ra_or_not_select_controller : std_logic := WRITE_RA_NO;
signal write_ih_or_not_select_controller : std_logic := WRITE_IH_NO;
signal write_t_or_not_select_controller : std_logic := WRITE_T_NO;
signal write_sp_or_not_select_controller : std_logic := WRITE_SP_NO;
signal write_t_src_select_controller : std_logic := T_SRC_IS_SF;
signal data_mem_read_write_select_controller : std_logic_vector(1 downto 0) := MEM_NONE;
signal regs_read_write_select_controller : std_logic := WRITE_REGS_NO;
signal regs_write_data_src_select_controller : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- hazard detector
-- to PC reg
signal write_pc_or_not_hazard_detector : std_logic := WRITE_PC_YES;
-- to PC mux
signal new_pc_src_select_hazard_detector : std_logic_vector(1 downto 0) := NEW_PC_SRC_SELEC_PC_ADD_ONE;
-- to if/id reg
signal write_ir_or_not_hazard_detector : std_logic := WRITE_IR_YES;
signal write_ir_src_select_hazard_detector : std_logic := WRITE_IR_SRC_SELEC_ORIGIN;
-- to id/exe reg
signal command_origin_or_nop_hazard_detector : std_logic := COMMAND_ORIGIN;
-- to mem/wb reg
signal dm_visit_data_result_select_hazard_detector : std_logic := DM_DATA_RESULT_DM;
-- to im
signal im_visit_data_select_hazard_detector : std_logic :=IM_DATA_Z;
signal im_visit_addr_select_hazard_detector : std_logic := IM_ADDR_PC;
signal im_read_write_select_hazard_detector : std_logic_vector(1 downto 0) := MEM_READ;
-- forward unit
-- to hazard detector
signal stall_or_not_forward_unit : std_logic := STALL_NO;
-- to alu a src mux 2
signal alu_a_src_select_final_forward_unit : std_logic_vector(1 downto 0) := ALU_A_SRC_SELECT_FINAL_ORIGIN;
-- to alu b src mux 2
signal alu_b_src_select_final_forward_unit : std_logic_vector(1 downto 0) := ALU_B_SRC_SELECT_FINAL_ORIGIN;
-- comparator
-- to hazard detector
signal jump_or_not_comparator : std_logic := JUMP_FALSE;
-- if
-- PC to IM, PC Adder
signal pc_value_pc_reg_to_im : std_logic_vector(15 downto 0) := ZERO;
-- PC Adder to if/id reg, PC mux
signal pc_value_pc_adder_to_if_id_reg : std_logic_vector(15 downto 0) := ZERO;
-- IM to if/id reg
signal inst_im_to_if_id_reg : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- PC mux to PC
signal pc_value_pc_mux_to_pc : std_logic_vector(15 downto 0) := ZERO;
-- id
-- if/id reg to controller, imm extender, id/exe reg(rs, rt, rd),
--comparator(code), hazard detector, common regs(rs, st)
signal inst_code_if_id_reg_to_controller : std_logic_vector(4 downto 0) := NOP_INST(15 downto 11);
signal inst_rs_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(10 downto 8);
signal inst_rt_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(7 downto 5);
signal inst_rd_if_id_reg_to_controller : std_logic_vector(2 downto 0) := NOP_INST(4 downto 2);
signal inst_func_if_id_reg_to_controller : std_logic_vector(1 downto 0) := NOP_INST(1 downto 0);
-- if/id reg to id/exe reg, PC IMM Adder, to special regs(RA)
signal pc_value_if_id_reg_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- imm extender to id/exe reg, PC IMM Adder
signal imm_imm_extend_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- PC IMM Adder to PC mux
signal pc_value_pc_imm_adder_to_pc_mux : std_logic_vector(15 downto 0) := ZERO;
-- common regs to id/exe reg, comparator(A), PC mux(A)
signal a_reg_common_regs_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
signal b_reg_common_regs_to_id_exe_reg : std_logic_vector(15 downto 0) := ZERO;
-- if/id reg to im
--signal inst_if_id_reg_to_im : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- if/id reg to forward unit
signal cur_rs_num_if_id_reg_to_forward_unit : std_logic_vector(2 downto 0) := "ZZZ";
signal cur_rt_num_if_id_reg_to_forward_unit : std_logic_vector(2 downto 0) := "ZZZ";
-- exe
-- id/exe reg to alu src mux 1
signal alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(2 downto 0) := ALU_A_SRC_ZERO;
signal alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1 : std_logic_vector(1 downto 0) := ALU_B_SRC_ZERO;
signal a_reg_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
signal b_reg_id_exe_reg_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
signal imm_id_exe_reg_to_alu_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
-- id/exe reg to exe/mem reg
signal pc_value_id_exe_reg_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
signal write_dm_data_id_exe_reg_to_exe_mem_reg : std_logic_vector(15 downto 0) := HIGH_RESIST;
signal regs_read_write_select_id_exe_reg_to_exe_mem_reg : std_logic := WRITE_REGS_NO;
signal write_regs_num_id_exe_reg_to_exe_mem_reg : std_logic_vector(2 downto 0) := "ZZZ";
signal regs_write_data_src_select_id_exe_reg_to_exe_mem_reg : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
signal data_mem_read_write_select_id_exe_reg_to_exe_mem_reg : std_logic_vector(1 downto 0) := MEM_NONE;
-- id/exe reg to alu
signal alu_op_id_exe_reg_to_alu : std_logic_vector(3 downto 0) := ALU_NULL;
-- id/exe to special regs, to comparator(write t or not)
signal write_t_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_T_NO;
signal write_t_src_select_id_exe_reg_to_special_regs : std_logic := T_SRC_IS_SF;
signal write_ra_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_RA_NO;
signal write_ih_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_IH_NO;
signal write_sp_or_not_select_id_exe_reg_to_special_regs : std_logic := WRITE_SP_NO;
-- constant to alu src mux 1
signal all_zeros : std_logic_vector(15 downto 0) := ZERO;
-- special regs to alu src mux 1(SP)
signal sp_reg_special_regs_to_alu_a_src_mux_1 : std_logic_vector(15 downto 0) := ZERO;
-- special regs to exe/mem reg(IH)
signal ih_reg_special_regs_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- special regs to comparator(T)
signal t_reg_special_regs_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- alu src mux 1 to alu src mux 2
signal alu_a_src_value_mux1_to_mux2 : std_logic_vector(15 downto 0) := ZERO;
signal alu_b_src_value_mux1_to_mux2 : std_logic_vector(15 downto 0) := ZERO;
-- alu mux 2 to alu
signal alu_a_src_alu_mux2_to_alu : std_logic_vector(15 downto 0) := ZERO;
signal alu_b_src_alu_mux2_to_alu : std_logic_vector(15 downto 0) := ZERO;
-- alu to exe/mem reg
signal alu_result_alu_to_exe_mem_reg : std_logic_vector(15 downto 0) := ZERO;
-- alu to special regs(T)
signal alu_sf_alu_to_special_regs : std_logic := '0';
signal alu_zf_alu_to_special_regs : std_logic := '0';
-- mem in exe/mem reg
-- to RAM_Visitor
signal data_mem_read_write_select_exe_mem_reg_to_dm : std_logic_vector(1 downto 0) := MEM_NONE;
-- as data memory address, to mem/wb reg
signal alu_result_exe_mem_reg_to_dm : std_logic_vector(15 downto 0) := ZERO;
-- as data memory data, to mem/wb reg
signal write_dm_data_exe_mem_reg_to_dm : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- to mem/wb reg
signal regs_read_write_select_exe_mem_reg_to_mem_wb_reg : std_logic := WRITE_REGS_NO;
signal write_regs_num_exe_mem_reg_to_mem_wb_reg : std_logic_vector(2 downto 0) := "ZZZ";
signal regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
signal ih_reg_exe_mem_reg_to_mem_wb_reg : std_logic_vector(15 downto 0) := ZERO;
signal pc_value_exe_mem_reg_mem_wb_reg : std_logic_vector(15 downto 0) := ZERO;
-- lw/sw to IM
signal im_visit_addr_im_mux_to_im : std_logic_vector(15 downto 0);
signal im_visit_data_im_mux_to_im : std_logic_vector(15 downto 0);
-- DM to mem/wb reg
signal read_dm_data_dm_to_mem_wb_reg : std_logic_vector(15 downto 0);
signal dm_visit_data_dm_mux_to_mem_wb_reg : std_logic_vector(15 downto 0);
-- wb in mem/wb reg
-- to common regs write src mux
signal ih_reg_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
signal alu_result_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
--alse to special regs(IH, SP)
signal dm_data_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
-- also to alu src mux 2
signal pc_value_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(15 downto 0) := ZERO;
signal regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux : std_logic_vector(1 downto 0) := REGS_WRITE_DATA_SRC_ALU_RESULT;
-- to common regs
signal regs_read_write_select_mem_wb_reg_to_common_regs : std_logic := WRITE_REGS_NO;
signal write_regs_num_mem_wb_reg_to_common_regs : std_logic_vector(2 downto 0) := "ZZZ";
-- common regs write src mux to common regs
signal write_regs_data_src_mux_to_regs : std_logic_vector(15 downto 0) := ZERO;
-- not used
signal ra_reg_special_regs_to_where : std_logic_vector(15 downto 0) := ZERO;
signal watch_info : std_logic_vector(15 downto 0) := ZERO;
signal high_resist_port : std_logic_vector(15 downto 0) := HIGH_RESIST;
-- signal write_pc_force : std_logic := '1';
-- signal write_ir_force : std_logic := '1';
-- signal write_ir_origin_force : std_logic := '0';
-- signal write_pc_add_one_force : std_logic_vector(1 downto 0) := "00";
signal led_ram_visitor_to_cpu_core : std_logic_vector(7 downto 0) := "00000000";
signal useless_pin : std_logic_vector(4 downto 0) := "11111";
signal CLK : std_logic := '1';
-- signal step_disp1 : std_logic_vector(6 downto 0) := "0111111";
-- signal step_disp1 : std_logic_vector(6 downto 0) := "0111111";
begin
Unit_CLK_MODULE : CLK_MODULE port map (
CLK_IN => CLK_IN,
CLK => CLK
);
Unit_New_PC_Src_Mux3 : MUX_3 port map (
-- PC + 1
SRC_1 => pc_value_pc_adder_to_if_id_reg,
-- PC + IMM
SRC_2 => pc_value_pc_imm_adder_to_pc_mux,
-- A reg
SRC_3 => a_reg_common_regs_to_id_exe_reg,
SELEC => new_pc_src_select_hazard_detector, --write_pc_add_one_force,--
OUTPUT => pc_value_pc_mux_to_pc
);
Unit_PC_Register : PC_Register port map (
PC_IN => pc_value_pc_mux_to_pc,
PC_OUT => pc_value_pc_reg_to_im,
WRITE_OR_NOT => write_pc_or_not_hazard_detector, --write_pc_force,--
CLK => CLK
);
Unit_PC_Adder : PC_Adder port map (
OLD_PC => pc_value_pc_reg_to_im,
NEW_PC => pc_value_pc_adder_to_if_id_reg
);
Unit_IM_Addr_Mux : MUX_2 port map(
SELEC => im_visit_addr_select_hazard_detector,
SRC_1 => pc_value_pc_reg_to_im,
SRC_2 => alu_result_exe_mem_reg_to_dm,
OUTPUT => im_visit_addr_im_mux_to_im
);
Unit_IM_Data_Mux : MUX_2 port map(
SELEC => im_visit_data_select_hazard_detector,
SRC_1 => high_resist_port,
SRC_2 => write_dm_data_exe_mem_reg_to_dm,
OUTPUT => im_visit_data_im_mux_to_im
);
Unit_RAM1_Visitor : RAM1_Visitor port map (
---input
clk => CLK,
DMemReadWrite => data_mem_read_write_select_exe_mem_reg_to_dm,
EXandMEM_AluRes => alu_result_exe_mem_reg_to_dm,
DataReady => com_data_ready,
WriteData => write_dm_data_exe_mem_reg_to_dm,
TSRE => com_tsre,
TBRE => com_tbre,
---output
RAM1_Enable => RAM1_EN,
RAM1_ReadEnable => RAM1_OE,
RAM1_WriteEnable => RAM1_WE,
SPort_WriteEnable => com_wrn,
SPort_ReadEnable => com_rdn,
DMemData => RAM1_Data,
DMemAddr => RAM1_Addr(15 downto 0)
);
Unit_RAM2_Visitor : RAM2_Visitor port map (
---input
clk => CLK,
DMemReadWrite => im_read_write_select_hazard_detector,
EXandMEM_AluRes => im_visit_addr_im_mux_to_im,
-- DataReady => useless_pin(4),
WriteData => im_visit_data_im_mux_to_im,
-- TSRE => useless_pin(3),
-- TBRE => useless_pin(2),
---output
RAM1_Enable => RAM2_EN,
RAM1_ReadEnable => RAM2_OE,
RAM1_WriteEnable => RAM2_WE,
-- SPort_WriteEnable => useless_pin(1),
-- SPort_ReadEnable => useless_pin(0),
DMemData => RAM2_Data,
DMemAddr => RAM2_Addr(15 downto 0)
);
RAM1_Addr(17 downto 16) <= "00";
RAM2_Addr(17 downto 16) <= "00";
-- LED(15 downto 8) <= led_ram_visitor_to_cpu_core;
Unit_IF_ID_Register : IF_ID_Register port map (
NEW_PC_IN => pc_value_pc_adder_to_if_id_reg,
WRITE_PC_OR_NOT => write_pc_or_not_hazard_detector,
NEW_PC_OUT => pc_value_if_id_reg_to_id_exe_reg,
CLK => CLK,
INST_IN => inst_im_to_if_id_reg,
WRITE_IR_OR_NOT => write_ir_or_not_hazard_detector, --write_ir_force,--
WRITE_IR_SRC_SELEC => write_ir_src_select_hazard_detector, --write_ir_origin_force,--
INST_OUT_CODE => inst_code_if_id_reg_to_controller,
INST_OUT_RS => inst_rs_if_id_reg_to_controller,
INST_OUT_RT => inst_rt_if_id_reg_to_controller,
INST_OUT_RD => inst_rd_if_id_reg_to_controller,
INST_OUT_FUNC => inst_func_if_id_reg_to_controller
);
-- detect before id, just after INST could be read rightly
Unit_Hazard_Detector : Hazard_Detector port map (
STALL_OR_NOT_FU => stall_or_not_forward_unit,
CUR_INST_CODE => inst_code_if_id_reg_to_controller,
CUR_INST_RS => inst_rs_if_id_reg_to_controller,
CUR_INST_RT => inst_rt_if_id_reg_to_controller,
CUR_INST_RD => inst_rd_if_id_reg_to_controller,
CUR_INST_FUNC => inst_func_if_id_reg_to_controller,
-- in id/exe reg
LAST_WRITE_REGS_OR_NOT => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
LAST_WRITE_REGS_TARGET => write_regs_num_id_exe_reg_to_exe_mem_reg,
LAST_VISIT_DM_OR_NOT => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
-- in exe/mem reg
LAST_LAST_WRITE_REGS_OR_NOT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
LAST_LAST_WRITE_REGS_TARGET => write_regs_num_exe_mem_reg_to_mem_wb_reg,
-- in exe/mem reg
LAST_LAST_VISIT_DM_OR_NOT => data_mem_read_write_select_exe_mem_reg_to_dm,
LAST_LAST_DM_VISIT_ADDR => alu_result_exe_mem_reg_to_dm,
CUR_DM_READ_WRITE => data_mem_read_write_select_controller,
CUR_DM_WRITE_DATA_SRC => write_dm_data_src_select_controller,
JUMP_OR_NOT => jump_or_not_comparator,
WRITE_PC_OR_NOT => write_pc_or_not_hazard_detector,
NEW_PC_SRC_SELEC => new_pc_src_select_hazard_detector,
WRITE_IR_OR_NOT => write_ir_or_not_hazard_detector,
WRITE_IR_SRC_SELEC => write_ir_src_select_hazard_detector,
COMMAND_ORIGIN_OR_NOP => command_origin_or_nop_hazard_detector,
DM_DATA_RESULT_SELEC => dm_visit_data_result_select_hazard_detector,
IM_ADDR_SELEC => im_visit_addr_select_hazard_detector,
IM_DATA_SELEC => im_visit_data_select_hazard_detector,
IM_READ_WRITE_SELEC => im_read_write_select_hazard_detector
);
Unit_Controller : Controller port map (
INST_CODE => inst_code_if_id_reg_to_controller,
INST_RS => inst_rs_if_id_reg_to_controller,
INST_RT => inst_rt_if_id_reg_to_controller,
INST_RD => inst_rd_if_id_reg_to_controller,
INST_FUNC => inst_func_if_id_reg_to_controller,
ALU_OP => alu_op_controller,
ALU_A_SRC => alu_a_src_select_controller,
ALU_B_SRC => alu_b_src_select_controller,
WRITE_REGS_DEST => write_regs_dest_select_controller,
WRITE_DM_DATA_SRC => write_dm_data_src_select_controller,
WRITE_RA_OR_NOT => write_ra_or_not_select_controller,
WRITE_IH_OR_NOT => write_ih_or_not_select_controller,
WRITE_T_OR_NOT => write_t_or_not_select_controller,
WRITE_SP_OR_NOT => write_sp_or_not_select_controller,
WRITE_T_SRC => write_t_src_select_controller,
DATA_MEM_READ_WRITE => data_mem_read_write_select_controller,
REGS_WRITE_OR_NOT => regs_read_write_select_controller,
REGS_WRITE_DATA_SRC => regs_write_data_src_select_controller
);
Unit_Imm_Extend : Imm_Extend port map (
code => inst_code_if_id_reg_to_controller,
rs => inst_rs_if_id_reg_to_controller,
rt => inst_rt_if_id_reg_to_controller,
rd => inst_rd_if_id_reg_to_controller,
func => inst_func_if_id_reg_to_controller,
imm => imm_imm_extend_to_id_exe_reg
);
Unit_adder : adder port map (
pc => pc_value_if_id_reg_to_id_exe_reg,
imm => imm_imm_extend_to_id_exe_reg,
res => pc_value_pc_imm_adder_to_pc_mux
);
Unit_Common_regs_write_src_Mux4 : MUX_4 port map (
-- ALU result
SRC_1 => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
-- DM data
SRC_2 => dm_data_mem_wb_reg_to_common_regs_write_src_mux,
-- IH
SRC_3 => ih_reg_mem_wb_reg_to_common_regs_write_src_mux,
-- PC
SRC_4 => pc_value_mem_wb_reg_to_common_regs_write_src_mux,
SELEC => regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux,
OUTPUT => write_regs_data_src_mux_to_regs
);
Unit_Common_Register : Common_Register port map (
clk => CLK,
rs => inst_rs_if_id_reg_to_controller,
rt => inst_rt_if_id_reg_to_controller,
write_flag => regs_read_write_select_mem_wb_reg_to_common_regs,
write_reg => write_regs_num_mem_wb_reg_to_common_regs,
write_data => write_regs_data_src_mux_to_regs,
a => a_reg_common_regs_to_id_exe_reg,
b => b_reg_common_regs_to_id_exe_reg
);
Unit_Comparator : Comparator port map (
code => inst_code_if_id_reg_to_controller,
write_t => write_t_or_not_select_id_exe_reg_to_special_regs,
t => t_reg_special_regs_to_exe_mem_reg,
-- could not be given as one value
T_src_SF => alu_sf_alu_to_special_regs,
T_src_ZF => alu_zf_alu_to_special_regs,
T_cmd_src => write_t_src_select_id_exe_reg_to_special_regs,
a => a_reg_common_regs_to_id_exe_reg,
jump => jump_or_not_comparator
);
Unit_ID_EXE_Register : ID_EXE_Register port map (
clk => CLK,
--cmd cmd
command_origin_or_nop => command_origin_or_nop_hazard_detector,
--common input
in_pc => pc_value_if_id_reg_to_id_exe_reg,
in_reg_a => a_reg_common_regs_to_id_exe_reg,
in_reg_b => b_reg_common_regs_to_id_exe_reg,
in_imm => imm_imm_extend_to_id_exe_reg,
in_rs => inst_rs_if_id_reg_to_controller,
in_rt => inst_rt_if_id_reg_to_controller,
in_rd => inst_rd_if_id_reg_to_controller,
--exe cmd
in_alu => alu_op_controller,
in_a_src => alu_a_src_select_controller,
in_b_src => alu_b_src_select_controller,
in_reg_result => write_regs_dest_select_controller,
in_mem_src => write_dm_data_src_select_controller,
in_flag_RA => write_ra_or_not_select_controller,
in_flag_IH => write_ih_or_not_select_controller,
in_flag_T => write_t_or_not_select_controller,
in_flag_SP => write_sp_or_not_select_controller,
in_T_src => write_t_src_select_controller,
--mem cmd
in_mem_cmd => data_mem_read_write_select_controller,
--wb cmd
in_flag_reg => regs_read_write_select_controller,
in_reg_src => regs_write_data_src_select_controller,
--common output
out_pc => pc_value_id_exe_reg_to_exe_mem_reg,
out_imm => imm_id_exe_reg_to_alu_src_mux_1,
out_reg_a => a_reg_id_exe_reg_to_alu_a_src_mux_1,
out_reg_b => b_reg_id_exe_reg_to_alu_a_src_mux_1,
--memory data
out_mem_data => write_dm_data_id_exe_reg_to_exe_mem_reg,
--result register
out_res_reg => write_regs_num_id_exe_reg_to_exe_mem_reg,
--exe cmd
out_alu => alu_op_id_exe_reg_to_alu,
out_a_src => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,
out_b_src => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,
out_flag_RA => write_ra_or_not_select_id_exe_reg_to_special_regs,
out_flag_IH => write_ih_or_not_select_id_exe_reg_to_special_regs,
out_flag_T => write_t_or_not_select_id_exe_reg_to_special_regs,
out_flag_SP => write_sp_or_not_select_id_exe_reg_to_special_regs,
out_T_src => write_t_src_select_id_exe_reg_to_special_regs,
--mem cmd
out_mem_cmd => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
--wb cmd
out_flag_reg => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
out_reg_src => regs_write_data_src_select_id_exe_reg_to_exe_mem_reg,
cur_rs_num => cur_rs_num_if_id_reg_to_forward_unit,
cur_rt_num => cur_rt_num_if_id_reg_to_forward_unit
);
all_zeros <= ZERO;
Unit_ALU_A_Src_Select1_Mux6 : MUX_6 port map (
-- A
SRC_1 => a_reg_id_exe_reg_to_alu_a_src_mux_1,
-- IMM
SRC_2 => imm_id_exe_reg_to_alu_src_mux_1,
-- 0
SRC_3 => all_zeros,
-- SP
SRC_4 => sp_reg_special_regs_to_alu_a_src_mux_1,
-- PC
SRC_5 => pc_value_id_exe_reg_to_exe_mem_reg,
-- IH
SRC_6 => ih_reg_special_regs_to_exe_mem_reg,
SELEC => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,
OUTPUT => alu_a_src_value_mux1_to_mux2
);
Unit_ALU_B_Src_Select1_Mux3 : MUX_3 port map (
-- B
SRC_1 => b_reg_id_exe_reg_to_alu_a_src_mux_1,
-- IMM
SRC_2 => imm_id_exe_reg_to_alu_src_mux_1,
-- 0
SRC_3 => all_zeros,
SELEC => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,
OUTPUT => alu_b_src_value_mux1_to_mux2
);
Unit_ALU_A_Src_Select2_Mux3 : MUX_3 port map (
-- origin, regs output
SRC_1 => alu_a_src_value_mux1_to_mux2,
-- exe/mem reg, alu result
SRC_2 => alu_result_exe_mem_reg_to_dm,
-- mem/wb reg, write back value
SRC_3 => write_regs_data_src_mux_to_regs,
SELEC => alu_a_src_select_final_forward_unit,
OUTPUT => alu_a_src_alu_mux2_to_alu
);
Unit_ALU_B_Src_Select2_Mux3 : MUX_3 port map (
-- origin, regs output
SRC_1 => alu_b_src_value_mux1_to_mux2,
-- exe/mem reg, alu result
SRC_2 => alu_result_exe_mem_reg_to_dm,
-- mem/wb reg, write back value
SRC_3 => write_regs_data_src_mux_to_regs,
SELEC => alu_b_src_select_final_forward_unit,
OUTPUT => alu_b_src_alu_mux2_to_alu
);
Unit_ALU : alu port map (
a => alu_a_src_alu_mux2_to_alu,
b => alu_b_src_alu_mux2_to_alu,
op => alu_op_id_exe_reg_to_alu,
zf => alu_zf_alu_to_special_regs,
sf => alu_sf_alu_to_special_regs,
c => alu_result_alu_to_exe_mem_reg
);
Unit_Special_Register : Special_Register port map (
clk => CLK,
T_cmd_write => write_t_or_not_select_id_exe_reg_to_special_regs,
T_cmd_src => write_t_src_select_id_exe_reg_to_special_regs,
T_src_SF => alu_sf_alu_to_special_regs,
T_src_ZF => alu_zf_alu_to_special_regs,
-- from controller, id/exe reg is too late
RA_cmd_write => write_ra_or_not_select_controller,
RA_src => pc_value_if_id_reg_to_id_exe_reg,
IH_cmd_write => write_ih_or_not_select_id_exe_reg_to_special_regs,
IH_src => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
SP_cmd_write => write_sp_or_not_select_id_exe_reg_to_special_regs,
SP_src => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
T_value => t_reg_special_regs_to_exe_mem_reg,
RA_value => ra_reg_special_regs_to_where,
IH_value => ih_reg_special_regs_to_exe_mem_reg,
SP_value => sp_reg_special_regs_to_alu_a_src_mux_1
);
-- judge before update id/exe reg, to stop next inst get in
Unit_Forward_Unit : Forward_Unit port map (
-- current instruction info, if use reg as alu src, conflict may exist
-- get from if/id reg
-- detect early, stop early
CUR_RS_REG_NUM => cur_rs_num_if_id_reg_to_forward_unit,--inst_rs_if_id_reg_to_controller,
CUR_RT_REG_NUM => cur_rt_num_if_id_reg_to_forward_unit,--inst_rt_if_id_reg_to_controller,
-- get it from controller, from id/exe reg is too late
CUR_ALU_A_SRC_SELECT => alu_a_src_select_id_exe_reg_to_alu_a_src_mux_1,--alu_a_src_select_controller,
CUR_ALU_B_SRC_SELECT => alu_b_src_select_id_exe_reg_to_alu_b_src_mux_1,--alu_b_src_select_controller,
-- last instruction info, if write regs, conflict may exist, if read DM, must stall
-- from id/exe reg
--
--
LAST_WRITE_REGS_OR_NOT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,--regs_read_write_select_id_exe_reg_to_exe_mem_reg,
LAST_WRITE_REGS_TARGET => write_regs_num_exe_mem_reg_to_mem_wb_reg,--write_regs_num_id_exe_reg_to_exe_mem_reg,
LAST_DM_READ_WRITE => data_mem_read_write_select_exe_mem_reg_to_dm,--data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
-- last last instruction info, if write regs, conflict may exist
-- from exe/mem reg
LAST_LAST_WRITE_REGS_OR_NOT => regs_read_write_select_mem_wb_reg_to_common_regs, --regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
LAST_LAST_WRITE_REGS_TARGET => write_regs_num_mem_wb_reg_to_common_regs, --write_regs_num_exe_mem_reg_to_mem_wb_reg,
STALL_OR_NOT => stall_or_not_forward_unit,
ALU_A_SRC_SELECT_FINAL => alu_a_src_select_final_forward_unit,
ALU_B_SRC_SELECT_FINAL => alu_b_src_select_final_forward_unit
);
Unit_EXE_MEM_Register : EXE_MEM_Register port map (
CLK => CLK,
NEW_PC_IN => pc_value_id_exe_reg_to_exe_mem_reg,
WRITE_DM_DATA_IN => write_dm_data_id_exe_reg_to_exe_mem_reg,
WRITE_REG_NUM_IN => write_regs_num_id_exe_reg_to_exe_mem_reg,
ALU_RESULT_IN => alu_result_alu_to_exe_mem_reg,
IH_REG_IN => ih_reg_special_regs_to_exe_mem_reg,
DATA_MEM_READ_WRITE_IN => data_mem_read_write_select_id_exe_reg_to_exe_mem_reg,
REGS_READ_WRITE_IN => regs_read_write_select_id_exe_reg_to_exe_mem_reg,
REGS_WRITE_DATA_SRC_IN => regs_write_data_src_select_id_exe_reg_to_exe_mem_reg,
NEW_PC_OUT => pc_value_exe_mem_reg_mem_wb_reg,
WRITE_DM_DATA_OUT => write_dm_data_exe_mem_reg_to_dm,
WRITE_REG_NUM_OUT => write_regs_num_exe_mem_reg_to_mem_wb_reg,
ALU_RESULT_OUT => alu_result_exe_mem_reg_to_dm,
IH_REG_OUT => ih_reg_exe_mem_reg_to_mem_wb_reg,
DATA_MEM_READ_WRITE_OUT => data_mem_read_write_select_exe_mem_reg_to_dm,
REGS_READ_WRITE_OUT => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
REGS_WRITE_DATA_SRC_OUT => regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg
);
Unit_DM_Data_Result_Mux : MUX_2 port map(
SELEC => dm_visit_data_result_select_hazard_detector,
SRC_1 => read_dm_data_dm_to_mem_wb_reg,
SRC_2 => inst_im_to_if_id_reg,
OUTPUT => dm_visit_data_dm_mux_to_mem_wb_reg
);
Unit_MEM_WB_Register : MEM_WB_Register port map (
CLK => CLK,
NEW_PC_IN => pc_value_exe_mem_reg_mem_wb_reg,
WRITE_REGS_NUM_IN => write_regs_num_exe_mem_reg_to_mem_wb_reg,
ALU_RESULT_IN => alu_result_exe_mem_reg_to_dm,
IH_REG_IN => ih_reg_exe_mem_reg_to_mem_wb_reg,
DM_DATA_IN => dm_visit_data_dm_mux_to_mem_wb_reg,
-- cmd
REGS_READ_WRITE_IN => regs_read_write_select_exe_mem_reg_to_mem_wb_reg,
REGS_WRITE_DATA_SRC_IN => regs_write_data_src_select_exe_mem_reg_to_mem_wb_reg,
NEW_PC_OUT => pc_value_mem_wb_reg_to_common_regs_write_src_mux,
WRITE_REGS_NUM_OUT => write_regs_num_mem_wb_reg_to_common_regs,
ALU_RESULT_OUT => alu_result_mem_wb_reg_to_common_regs_write_src_mux,
IH_REG_OUT => ih_reg_mem_wb_reg_to_common_regs_write_src_mux,
DM_DATA_OUT => dm_data_mem_wb_reg_to_common_regs_write_src_mux,
REGS_READ_WRITE_OUT => regs_read_write_select_mem_wb_reg_to_common_regs,
REGS_WRITE_DATA_SRC_OUT => regs_write_data_src_select_mem_wb_reg_to_common_regs_write_src_mux
);
read_dm_data_dm_to_mem_wb_reg <= RAM1_Data;
inst_im_to_if_id_reg <= RAM2_Data;
process (CLK, inst_im_to_if_id_reg, pc_value_pc_reg_to_im, write_pc_or_not_hazard_detector, write_ir_or_not_hazard_detector)
--variable step : integer := 0;
begin
if (CLK'event and CLK = '0') then
-- IF
watch_info <= watch_info + "0000000000000001";
-- LED(15 downto 11) <= inst_code_if_id_reg_to_controller;
-- LED(10 downto 8) <= inst_rs_if_id_reg_to_controller;
-- LED(7 downto 5) <= inst_rt_if_id_reg_to_controller;
-- LED(4 downto 2) <= inst_rd_if_id_reg_to_controller;
-- LED(1 downto 0) <= inst_func_if_id_reg_to_controller;
LED <= pc_value_pc_reg_to_im;
case DISP1 is
when "0111111" =>
DISP1 <= "0000110";
when "0000110" =>
DISP1 <= "1011011";
when "1011011" =>
DISP1 <= "1001111";
when "1001111" =>
DISP1 <= "1100110";
when "1100110" =>
DISP1 <= "1101101";
when "1101101" =>
DISP1 <= "1111101";
when "1111101" =>
DISP1 <= "0000111";
when "0000111" =>
DISP1 <= "1111111";
when "1111111" =>
DISP1 <= "1101111";
when "1101111" =>
DISP1 <= "0111111";
case DISP2 is
when "1101111" =>
DISP2 <= "0111111";
when "0111111" =>
DISP2 <= "0000110";
when "0000110" =>
DISP2 <= "1011011";
when "1011011" =>
DISP2 <= "1001111";
when "1001111" =>
DISP2 <= "1100110";
when "1100110" =>
DISP2 <= "1101101";
when "1101101" =>
DISP2 <= "1111101";
when "1111101" =>
DISP2 <= "0000111";
when "0000111" =>
DISP2 <= "1111111";
when "1111111" =>
DISP2 <= "1101111";
when others =>
DISP2 <= "0111111";
end case;
when others =>
DISP1 <= "0111111";
end case;
elsif (CLK = '1') then
high_resist_port <= HIGH_RESIST;
end if;
end process;
end Behavioral;
|
apache-2.0
|
53f08a9e2e29d2a71519db04c6fbf56b
| 0.644525 | 2.682677 | false | false | false | false |
DacHt/CU_Droptest
|
hdl/Backup/WOLF_CONTROLLER_20170528.vhd
| 1 | 6,601 |
--------------------------------------------------------------------------------
-- Company: KTH
--
-- File: WOLF_CONTROLLER.vhd
-- File history:
-- v0.1: 2017-04-15: Initial verision for drop test only
--
-- Description:
-- Controller for the REXUS - WOLF exeriment. Handles the statemachine and status communication.
--
-- Backup version:
-- 2017-05-28: D.R: 19:20: First version, light led at 5 sec, turn off led at 10 sec.
--
-- Targeted device: <Family::ProASIC3> <Die::A3P250> <Package::100 VQFP>
-- Author: David Rozenbeek
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity WOLF_CONTROLLER is
port (
---------------------------------------------------
-- Inputs --
---------------------------------------------------
clk_main : IN std_logic; -- Main clock
clk_1hz : IN std_logic; -- 1 Hz clock
reset : IN std_logic; -- Reset (when 1)
rocket_pin : IN std_logic; -- rocket pin if mounted in RMU = 1, ejected = 0
---------------------------------------------------
-- Outputs --
---------------------------------------------------
cutter_en: OUT std_logic -- Cutter Enable (0=Off, 1=On)
);
end WOLF_CONTROLLER;
architecture architecture_WOLF_CONTROLLER of WOLF_CONTROLLER is
--####################### Constants #####################################
constant sec_cutter_enable : integer := 10; -- Seconds cutter should be enabled
constant sec_to_cutter_enable : integer := 5; -- Seconds from ejection to enable cutter.
--####################### Signals #####################################
----------------------------------------------------------------------------------------------------------------------
-- Control signals |Comments --
----------------------------------------------------------------------------------------------------------------------
signal rocket_pin_old : std_logic; --
-----------------------------------------------------------------------------------------------------------------------
-- Mission counter |Comments --
-----------------------------------------------------------------------------------------------------------------------
signal sec_since_eject : unsigned(12 downto 0) := (others => '0'); -- Variable to keep track of seconds since ejection
-----------------------------------------------------------------------------------------------------------------------
-- State Machine Signals |Comments --
-----------------------------------------------------------------------------------------------------------------------
type state is (START, IDLE, EJECTED, CUTTER_ENABLE, CUTTER_DISABLE, SLEEP); -- State declaration
signal current_state : state; -- Current state value
signal next_state : state := START; -- Next clock cycle state value
--################# Architecture Body ###########################
begin
-----------------------------------------------------------------
-- Signal/Port mapping --
-----------------------------------------------------------------
-----------------------------------------------------------------
-- Mission counter --
-- Description: --
-- Keeps track of seconds since ejected, counts up to --
-- 2^12 = 4096 seconds (68,3 min) and then overflows back to 0.--
-----------------------------------------------------------------
mission_counter: process(clk_1hz, rocket_pin, reset)
begin
if ( reset = '1' ) then
sec_since_eject <= (others => '0');
else
if ( rising_edge(clk_1hz) ) then
sec_since_eject <= sec_since_eject + 1;
end if;
end if;
end process;
-----------------------------------------------------------------
-- Main State Machine --
-- Description: --
-- Makes transitions betweens states --
-----------------------------------------------------------------
main_state_machine : process(clk_main, reset, sec_since_eject, current_state, clk_1hz)
begin
rocket_pin_old <= rocket_pin;
if(reset = '1') then
rocket_pin_old <= '0';
cutter_en <= '0';
current_state <= START;
elsif(rising_edge(clk_main)) then
current_state <= next_state;
case current_state is
-- Starting state
when START =>
rocket_pin_old <= '0';
cutter_en <= '0';
next_state <= IDLE;
-- IDLE state
when IDLE =>
-- if ('1') then --rocket_pin = '0' AND rocket_pin_old = '0') then
next_state <= EJECTED;
--else
-- next_state <= current_state;
--end if;
when EJECTED =>
-- Enable cutter after "sec_to_cutter_enable" from reset
if (sec_since_eject >= To_unsigned(sec_to_cutter_enable, sec_since_eject'length)) then
next_state <= CUTTER_ENABLE;
else
next_state <= current_state;
end if;
-- Enable cutter
when CUTTER_ENABLE =>
cutter_en <= '1';
next_state <= CUTTER_DISABLE;
--Disable cutter
when CUTTER_DISABLE =>
-- Disable cutter after "sec_to_cutter_disable" from reset
if (sec_since_eject >= To_unsigned(sec_cutter_enable, sec_since_eject'length)) then
cutter_en <= '0';
next_state <= SLEEP;
else
next_state <= current_state;
end if;
-- SLEEP state, do nothing
when SLEEP =>
next_state <= current_state;
-- Default go back to start
when others =>
next_state <= START;
end case;
end if;
end process main_state_machine;
end architecture_WOLF_CONTROLLER;
|
mit
|
ba8f1eca0b907afe6123101762bdbbb2
| 0.367672 | 5.482558 | false | false | false | false |
blutsvente/MIX
|
test/results/padio/bus/ioblock3_e-rtl-a.vhd
| 1 | 9,696 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock3_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:58:21 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\..\padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock3_e-rtl-a.vhd,v 1.1 2004/04/06 10:44:23 wig Exp $
-- $Date: 2004/04/06 10:44:23 $
-- $Log: ioblock3_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:44:23 wig
-- Adding result/padio
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock3_e
--
architecture rtl of ioblock3_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ioc_r_iou --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_iou
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
en : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
p_pu : out std_ulogic;
pu : in std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ioc_r_iou
);
end component;
-- ---------
component ioc_g_i --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_i
di : out std_ulogic_vector(7 downto 0);
p_di : in std_ulogic;
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_g_i
);
end component;
-- ---------
component ioc_g_o --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_g_o
do : in std_ulogic_vector(7 downto 0);
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity ioc_g_o
);
end component;
-- ---------
component ioc_r_io3 --
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io3
do : in std_ulogic_vector(3 downto 0);
en : in std_ulogic_vector(3 downto 0);
p_di : in std_ulogic;
p_do : out std_ulogic;
p_en : out std_ulogic;
sel : in std_ulogic_vector(2 downto 0)
-- End of Generated Port for Entity ioc_r_io3
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal d9_di : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_do : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_en : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_pu : std_ulogic_vector(1 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i33 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_i34 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o35 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal data_o36 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_bus : std_ulogic_vector(3 downto 0);
signal ioseldi_0 : std_ulogic_vector(2 downto 0);
signal pad_di_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_33 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_34 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_35 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_36 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_39 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_40 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_31 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_pu_32 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_d9_di_go <= d9_di; -- __I_O_BUS_PORT
d9_do <= p_mix_d9_do_gi; -- __I_I_BUS_PORT
d9_en <= p_mix_d9_en_gi; -- __I_I_BUS_PORT
d9_pu <= p_mix_d9_pu_gi; -- __I_I_BUS_PORT
p_mix_data_i33_go <= data_i33; -- __I_O_BUS_PORT
p_mix_data_i34_go <= data_i34; -- __I_O_BUS_PORT
data_o35 <= p_mix_data_o35_gi; -- __I_I_BUS_PORT
data_o36 <= p_mix_data_o36_gi; -- __I_I_BUS_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
pad_di_31 <= p_mix_pad_di_31_gi; -- __I_I_BIT_PORT
pad_di_32 <= p_mix_pad_di_32_gi; -- __I_I_BIT_PORT
pad_di_33 <= p_mix_pad_di_33_gi; -- __I_I_BIT_PORT
pad_di_34 <= p_mix_pad_di_34_gi; -- __I_I_BIT_PORT
pad_di_39 <= p_mix_pad_di_39_gi; -- __I_I_BIT_PORT
pad_di_40 <= p_mix_pad_di_40_gi; -- __I_I_BIT_PORT
p_mix_pad_do_31_go <= pad_do_31; -- __I_O_BIT_PORT
p_mix_pad_do_32_go <= pad_do_32; -- __I_O_BIT_PORT
p_mix_pad_do_35_go <= pad_do_35; -- __I_O_BIT_PORT
p_mix_pad_do_36_go <= pad_do_36; -- __I_O_BIT_PORT
p_mix_pad_do_39_go <= pad_do_39; -- __I_O_BIT_PORT
p_mix_pad_do_40_go <= pad_do_40; -- __I_O_BIT_PORT
p_mix_pad_en_31_go <= pad_en_31; -- __I_O_BIT_PORT
p_mix_pad_en_32_go <= pad_en_32; -- __I_O_BIT_PORT
p_mix_pad_en_35_go <= pad_en_35; -- __I_O_BIT_PORT
p_mix_pad_en_36_go <= pad_en_36; -- __I_O_BIT_PORT
p_mix_pad_en_39_go <= pad_en_39; -- __I_O_BIT_PORT
p_mix_pad_en_40_go <= pad_en_40; -- __I_O_BIT_PORT
p_mix_pad_pu_31_go <= pad_pu_31; -- __I_O_BIT_PORT
p_mix_pad_pu_32_go <= pad_pu_32; -- __I_O_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for ioc_data_10
ioc_data_10: ioc_r_iou
port map (
di => d9_di(1), -- d9io
do => d9_do(1), -- d9io
en => d9_en(1), -- d9io
p_di => pad_di_32, -- data in from pad
p_do => pad_do_32, -- data out to pad
p_en => pad_en_32, -- pad output enable
p_pu => pad_pu_32, -- pull-up control
pu => d9_pu(1) -- d9io
);
-- End of Generated Instance Port Map for ioc_data_10
-- Generated Instance Port Map for ioc_data_9
ioc_data_9: ioc_r_iou
port map (
di => d9_di(0), -- d9io
do => d9_do(0), -- d9io
en => d9_en(0), -- d9io
p_di => pad_di_31, -- data in from pad
p_do => pad_do_31, -- data out to pad
p_en => pad_en_31, -- pad output enable
p_pu => pad_pu_31, -- pull-up control
pu => d9_pu(0) -- d9io
);
-- End of Generated Instance Port Map for ioc_data_9
-- Generated Instance Port Map for ioc_data_i33
ioc_data_i33: ioc_g_i
port map (
di => data_i33, -- io data
p_di => pad_di_33, -- data in from pad
sel => iosel_bus
);
-- End of Generated Instance Port Map for ioc_data_i33
-- Generated Instance Port Map for ioc_data_i34
ioc_data_i34: ioc_g_i
port map (
di => data_i34, -- io data
p_di => pad_di_34, -- data in from pad
sel => iosel_bus
);
-- End of Generated Instance Port Map for ioc_data_i34
-- Generated Instance Port Map for ioc_data_o35
ioc_data_o35: ioc_g_o
port map (
do => data_o35, -- io data
p_do => pad_do_35, -- data out to pad
p_en => pad_en_35, -- pad output enable
sel => iosel_bus
);
-- End of Generated Instance Port Map for ioc_data_o35
-- Generated Instance Port Map for ioc_data_o36
ioc_data_o36: ioc_g_o
port map (
do => data_o36, -- io data
p_do => pad_do_36, -- data out to pad
p_en => pad_en_36, -- pad output enable
sel => iosel_bus
);
-- End of Generated Instance Port Map for ioc_data_o36
-- Generated Instance Port Map for ioc_disp_10
ioc_disp_10: ioc_r_io3
port map (
do(0) => display_ls(1),
do(1) => display_ls(3),
do(2) => display_ls(5),
do(3) => display_ls(7),
en(0) => display_ls_en,
en(1) => display_ls_en, -- io_enable
en(2) => display_ms_en,
en(3) => display_ms_en, -- io_enable
p_di => pad_di_40, -- data in from pad
p_do => pad_do_40, -- data out to pad
p_en => pad_en_40, -- pad output enable
sel => ioseldi_0
);
-- End of Generated Instance Port Map for ioc_disp_10
-- Generated Instance Port Map for ioc_disp_9
ioc_disp_9: ioc_r_io3
port map (
do(0) => display_ls(0),
do(1) => display_ls(2),
do(2) => display_ls(4),
do(3) => display_ls(6),
en(0) => display_ls_en,
en(1) => display_ls_en, -- io_enable
en(2) => display_ms_en,
en(3) => display_ms_en, -- io_enable
p_di => pad_di_39, -- data in from pad
p_do => pad_do_39, -- data out to pad
p_en => pad_en_39, -- pad output enable
sel => ioseldi_0
);
-- End of Generated Instance Port Map for ioc_disp_9
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
daed8b69a7633e361dc93548b22c00fa
| 0.590862 | 2.461538 | false | false | false | false |
mitchsm/nvc
|
test/elab/issue19.vhd
| 3 | 1,793 |
entity comp6_bot is
generic (num : integer := 2 );
port (
x : in bit_vector(7 downto 0);
y : out bit_vector(7 downto 0) );
end entity;
architecture rtl of comp6_bot is
function cfunc (constant val : integer) return integer is
variable tmp : integer;
begin tmp := 0;
for i in 0 to 3 loop
tmp := tmp + val;
end loop;
return tmp;
end function cfunc;
function cfunc2 (constant k : integer) return integer is
variable tmp : integer;
begin
tmp := 1;
for i in 0 to k loop
if tmp > k then
return i;
end if;
tmp := tmp + tmp;
end loop;
end cfunc2;
function my_cfunc2 (constant k: integer) return integer is
begin
if k > 1 then
return cfunc(k);
end if;
return 1;
end my_cfunc2;
constant cnum : integer := cfunc(num);
type m_a_t is array (cnum-1 downto 0) of bit_vector(num-1 downto 0);
signal ma : m_a_t;
signal tmp : integer := cnum;
constant cnum2 : integer := cfunc2(num);
type m_a_t2 is array (cnum2-1 downto 0) of bit_vector(num-1 downto 0);
signal ma2 : m_a_t2;
signal tmp2 : integer := cnum2;
constant cnum3 : integer := my_cfunc2(num);
type m_a_t3 is array (cnum3-1 downto 0) of bit_vector(num-1 downto 0);
signal ma3 : m_a_t3;
signal tmp3 : integer := cnum3;
begin
y <= x;
end architecture;
-------------------------------------------------------------------------------
entity comp6 is
end entity;
architecture rtl of comp6 is
signal b: bit_vector(7 downto 0);
component comp6_bot is
generic (num : integer := 2 );
port (
y : out bit_vector(7 downto 0);
x : in bit_vector(7 downto 0) );
end component;
begin
c1: component comp6_bot
generic map (num => 8)
port map ( x=>x"aa", y=>b );
end architecture;
|
gpl-3.0
|
32c16e4acd7171d4dd66b8c744572be2
| 0.59063 | 3.254083 | false | false | false | false |
mitchsm/nvc
|
test/bounds/bounds.vhd
| 2 | 6,798 |
entity bounds is
end entity;
architecture test of bounds is
type foo is range 1 to 5;
type my_vec1 is array (positive range <>) of integer;
type my_vec2 is array (foo range <>) of integer;
signal s : my_vec1(1 to 10);
signal n : my_vec1(1 downto 10);
subtype bool_true is boolean range true to true;
function fun(x : in bit_vector(7 downto 0)) return bit;
procedure proc(x : in bit_vector(7 downto 0));
function natfunc(x : in natural) return boolean;
function enumfunc(x : in bool_true) return boolean;
function realfunc(x : in real) return boolean;
type matrix is array (integer range <>, integer range <>) of integer;
procedure proc2(x : in matrix(1 to 3, 1 to 3));
begin
process is
variable a : my_vec1(0 to 10); -- Error
variable b : my_vec2(1 to 60); -- Error
begin
end process;
s(-52) <= 5; -- Error
s(1 to 11) <= (others => 0); -- Error
s(0 to 2) <= (others => 0); -- Error
process is
begin
report (0 => 'a'); -- Error
end process;
process is
variable v1 : bit_vector(3 downto 0);
variable v2 : bit_vector(8 downto 1);
variable m1 : matrix(1 to 3, 2 to 4);
variable m2 : matrix(1 to 3, 1 to 4);
begin
assert fun(v1) = '1'; -- Error
proc(v1); -- Error
proc(v2); -- OK
proc2(m1); -- OK
proc2(m2); -- Error
end process;
s <= s(1 to 9); -- Error
n <= s(1 to 2); -- Error
n <= (1, 2, 3); -- Error
process is
variable v : my_vec1(1 to 3);
begin
v := s; -- Error
end process;
process is
variable x : integer;
begin
x := s(11); -- Error!
x := s(-1); -- Error!
end process;
process is
variable a : my_vec1(1 to 3);
begin
a := (1, 2, 3); -- OK
a := (5 => 1, 1 => 2, 0 => 3); -- Error
end process;
process is
subtype alpha is character range 'a' to 'z';
variable a : alpha;
variable p : positive;
begin
a := 'c'; -- OK
a := '1'; -- Error
p := 0; -- Error
end process;
process is
begin
assert s'length(5) = 5; -- Error
end process;
process is
begin
assert natfunc(-1); -- Error
end process;
process is
subtype str is string;
constant c : str := "hello"; -- OK
begin
end process;
process is
variable a : my_vec1(1 to 3);
begin
a := (1, others => 2); -- OK
a := (5 => 1, others => 2); -- Error
end process;
process is
type mat2d is array (integer range <>, integer range <>)
of integer;
procedure p(m : in mat2d);
begin
p(((0, 1, 2, 3), (1 to 2 => 5))); -- Error
end process;
-- Reduced from Billowitch tc1374
process is
type t_rec3 is record
f1 : boolean;
end record;
subtype st_rec3 is t_rec3 ;
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype st_arr3 is t_arr3 (1 to 5, true downto false) ;
variable v_st_arr3 : st_arr3;
begin
v_st_arr3(1, true) := (f1 => false);
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
begin
assert i'a(14) = '0'; -- Error
end process;
process is
constant FPO_LOG_MAX_ITERATIONS : integer := 9;
type T_FPO_LOG_ALPHA is array (0 to FPO_LOG_MAX_ITERATIONS-1) of integer;
variable alpha : T_FPO_LOG_ALPHA;
begin
if alpha(0 to 5) = (5, 4, 6, 6, 6, 6) then -- OK
null;
end if;
end process;
process is
procedure real_proc(x : in real range 0.0 to 1.0);
begin
real_proc(0.0); -- OK
real_proc(1.0); -- OK
real_proc(2.0); -- Error
end process;
process is
type e is (one, two, three, four, five);
subtype se is e range two to four;
type t_arr is array (se range <>) of boolean;
constant c1 : t_arr(two to four) := (true, true);
constant c2 : t_arr(two to four) := (true, true, true, true);
procedure enum_proc(
arg1 : e range two to four;
arg2 : e range three downto two
) is
begin
end procedure;
begin
enum_proc(arg1 => two, arg2 => two); -- ok
enum_proc(arg1 => three, arg2 => one); -- Error
enum_proc(arg1 => four, arg2 => four); -- Error
enum_proc(arg1 => one, arg2 => three); -- Error
enum_proc(arg1 => five, arg2 => three); -- Error
end process;
process is
type e is (one, two, three, four, five);
type t_arr is array (two to four) of integer;
variable a : t_arr;
begin
a := (1, others => 2); -- OK
a := (two => 1, others => 2); -- OK
a := (one => 1, others => 2); -- Error
a := (two to four => 1, others => 2); -- OK
a := (one to five => 1, others => 2); -- Error
end process;
process is
type e is (one, two, three, four, five);
type mat2d is array (e range <>, e range <>) of integer;
procedure p(m : in mat2d);
begin
p(((0, 1, 2, 3), (one to three => 5))); -- Error
end process;
process is
type e is (one, two, three, four, five);
subtype se is e range two to three;
type arr is array (se range <>) of integer;
variable v1 : arr(two to three); -- OK
variable v2 : arr(one to four); -- Error
begin
end process;
process is
procedure phys_proc_to(a : in time range 0 ns to 10 ns) is
begin
end procedure;
procedure phys_proc_dt(a : in time range 10 sec downto 20 us) is
begin
end procedure;
begin
phys_proc_to(5 ns); -- OK
phys_proc_to(-5 ns); -- Error
phys_proc_dt(1 ms); -- OK
phys_proc_dt(5 ns); -- Error
end process;
process
variable t : time range -10 ns to 10 ns;
begin
t := 200 ns; -- Error
t := -200 ns; -- Error
t := 0 ns; -- OK
end process;
end architecture;
|
gpl-3.0
|
69937524ceb138c98ccf37fcb575157c
| 0.47514 | 3.757877 | false | false | false | false |
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_oarg_s2s_adapter.vhd
| 1 | 55,195 |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_oarg_s2s_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
-- Design note: The main issue in this module is TLAST generation, specially in
-- the case where AXI stream wisth is not the same as accelerator data width.
-- Last data beat generated by accelerator is the one generated just before
-- ap_done is generated.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt;
use axis_accelerator_adapter_v2_1_6.s2s_async_fifo_wt;
entity xd_oarg_s2s_adapter is
generic (
-- System generics:
C_FAMILY : string ; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_M_AXIS_TDATA_WIDTH : integer;
C_M_AXIS_TUSER_WIDTH : integer;
C_M_AXIS_TID_WIDTH : integer;
C_M_AXIS_TDEST_WIDTH : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer);
port (
-- Output streams
M_AXIS_ACLK : in std_logic;
M_AXIS_ARESETN : in std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TKEEP : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TID : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
M_AXIS_TDEST : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
M_AXIS_TUSER : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
---
sw_length : in std_logic_vector(31 downto 0);
sw_length_we : in std_logic;
use_sw_length : in std_logic;
host_oarg_tdest : in std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
---
ap_clk : in std_logic;
ap_rst_sync : in std_logic;
ap_rst : in std_logic;
ap_oarg_din : in std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_oarg_we : in std_logic;
ap_oarg_full_n : out std_logic;
ap_arg_rqt : out std_logic;
ap_arg_ack : in std_logic;
ap_start : in std_logic;
ap_done : in std_logic;
none : out std_logic);
end entity;
architecture rtl of xd_oarg_s2s_adapter is
signal axis_data : std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
signal axis_keep : std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
-- pragma translate_off
signal axis_start : std_logic;
signal axis_end : std_logic;
-- pragma translate_on
signal axis_last : std_logic;
signal axis_vld : std_logic;
signal axis_rdy : std_logic;
signal axis_rst : std_logic;
signal axis_rst1 : std_logic;
signal axis_rst2 : std_logic;
signal axis_trf_ok : std_logic;
signal ap_rst_vec : std_logic_vector(0 downto 0);
signal ap_rst_reg : std_logic;
-- signal ap_rst_sync : std_logic;
-- signal ap_rst_sync1 : std_logic;
signal ap_rst_axi : std_logic;
signal ap_rst_axi1 : std_logic;
-- SW_LENGTH_WIDTH is defined in xd_adapter_pkg
signal sw_length_wr : std_logic_vector(SW_LENGTH_WIDTH-1 downto 0);
signal sw_length_rd : std_logic_vector(SW_LENGTH_WIDTH-1 downto 0);
signal sw_length_we_vector : std_logic_vector(0 downto 0);
signal sw_length_we_rd : std_logic;
signal sw_length_we_rd_vector : std_logic_vector(0 downto 0);
signal xd_sw_length : std_logic_vector(SW_LENGTH_WIDTH-1 downto 0);
signal xd_sw_length_vld : std_logic;
signal xd_sw_length_rdy : std_logic;
signal sw_length_fifo_dout : std_logic_vector(SW_LENGTH_WIDTH-1 downto 0);
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF ap_rst_axi : SIGNAL IS "true";
ATTRIBUTE async_reg OF axis_rst1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF axis_rst : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ap_rst_sync1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ap_rst_sync : SIGNAL IS "true";
begin
prd0: PROCESS (M_AXIS_ACLK, M_AXIS_ARESETN)
BEGIN
-- Register Stage #1
IF (M_AXIS_ARESETN = '0') THEN
axis_rst1 <= '1';
axis_rst <= '1';
ELSIF (M_AXIS_ACLK'event and M_AXIS_ACLK = '1') THEN
axis_rst1 <= '0';
axis_rst <= axis_rst1;
END IF;
END PROCESS prd0;
M_AXIS_TVALID <= axis_vld;
M_AXIS_TDATA <= axis_data;
M_AXIS_TSTRB <= (others => '0');
M_AXIS_TKEEP <= axis_keep;
M_AXIS_TLAST <= axis_last;
M_AXIS_TID <= (others => '0');
M_AXIS_TDEST <= host_oarg_tdest;
M_AXIS_TUSER <= (others => '0');
axis_trf_ok <= axis_vld and axis_rdy;
-- PROCESS (ap_clk)
-- BEGIN
-- IF (ap_clk'event and ap_clk = '1') THEN
-- ap_rst_reg <= ap_rst;
-- END IF;
-- END PROCESS;
-- prd1: PROCESS (M_AXIS_ACLK)
-- BEGIN
-- -- Register Stage #1
-- IF (M_AXIS_ACLK'event and M_AXIS_ACLK = '1') THEN
-- ap_rst_sync1 <= ap_rst;
-- ap_rst_sync <= ap_rst_sync1;
-- END IF;
-- END PROCESS prd1;
axis_rst2 <= axis_rst or ap_rst_sync;
prd2: PROCESS (M_AXIS_ACLK, axis_rst2)
BEGIN
-- Register Stage #1
IF (axis_rst2 = '1') THEN
ap_rst_axi1 <= '1';
ap_rst_axi <= '1';
ELSIF (M_AXIS_ACLK'event and M_AXIS_ACLK = '1') THEN
ap_rst_axi1 <= '0';
ap_rst_axi <= ap_rst_axi1;
END IF;
END PROCESS prd2;
-- rst_sync : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 0,
-- C_RESET_STATE => 1,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 2
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => ap_rst,
-- prmry_vect_in => (others=>'0'),
--
-- scndry_aclk => M_AXIS_ACLK,
-- scndry_resetn => M_AXIS_ARESETN,
-- scndry_out => ap_rst_axi,
-- scndry_vect_out => open
-- );
-- SW programmable length:
-- sw_length_wr <= sw_length(SW_LENGTH_WIDTH-1 downto 0);
sw_length_rd <= sw_length(SW_LENGTH_WIDTH-1 downto 0);
sw_length_we_vector(0) <= sw_length_we;
sw_length_we_rd <= sw_length_we_rd_vector(0);
wr_stg_inst: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 1,
C_WIDTH => 1
)
PORT MAP (
RST => axis_rst,
CLK => M_AXIS_ACLK,
D => sw_length_we_vector,
Q => sw_length_we_rd_vector
);
-- SW_LENGTH_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 0,
-- C_VECTOR_WIDTH => SW_LENGTH_WIDTH,
-- C_MTBF_STAGES => 2
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => '0',
-- prmry_vect_in => sw_length_wr,
--
-- scndry_aclk => M_AXIS_ACLK,
-- scndry_resetn => axis_rst,
-- scndry_out => open,
-- scndry_vect_out => sw_length_rd
-- );
SW_LENGTH_FIFO : entity axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt
generic map (
C_FAMILY => C_FAMILY,
WIDTH => SW_LENGTH_WIDTH)
port map (
rst => axis_rst,--ap_rst,
clk => M_AXIS_ACLK,
din => sw_length_rd,
din_vld => sw_length_we_rd,
din_rdy => open,
dout => xd_sw_length,
dout_vld => xd_sw_length_vld,
dout_rdy => xd_sw_length_rdy);
-----------------------------------------------------
SAME_WIDTH_GEN : if (C_M_AXIS_TDATA_WIDTH = C_AP_ARG_DATA_WIDTH) generate
signal tap_0 : std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
signal tap_0_we : std_logic;
signal tap_0_vld : std_logic;
signal tap_0_rdy : std_logic;
signal tap_0_start : std_logic;
signal tap_0_end : std_logic;
constant FIFO_DATA_LSB : integer := 0;
constant FIFO_DATA_MSB : integer := C_AP_ARG_DATA_WIDTH-1;
constant FIFO_START_BIT : integer := FIFO_DATA_MSB+1;
constant FIFO_END_BIT : integer := FIFO_START_BIT+1;
constant FIFO_WIDTH : integer := FIFO_END_BIT+1;
signal fifo_din : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_dout : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_din_vld : std_logic;
signal fifo_din_rdy : std_logic;
type state_type is (
-- pragma translate_off
stop,
-- pragma translate_on
idle,
running,
pending_last);
signal state : state_type;
-- tap_0 is an extra position in the FIFO; substract one
constant FIFO_DEPTH : integer := (2**C_AP_ARG_ADDR_WIDTH)-1;
type axis_state_type is (
-- pragma translate_off
stop,
-- pragma translate_on
idle,
running,
discarding,
padding);
signal axis_state : axis_state_type;
signal apply_sw_length : std_logic;
-- Output FIFO signals
signal dout : std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
signal dout_start : std_logic;
signal dout_end : std_logic;
signal dout_vld : std_logic;
signal dout_rdy : std_logic;
constant AXIS_BEAT_CNT_WIDTH : integer := SW_LENGTH_WIDTH;
-- AXI stream beat counter:
signal axis_beat_cnt : unsigned(AXIS_BEAT_CNT_WIDTH-1 downto 0);
signal axis_beat_dec : std_logic;
signal axis_beat_clr : std_logic;
signal axis_beat_end : std_logic;
-- Output stage control:
signal axis_ce : std_logic;
signal axis_we : std_logic;
signal next_axis_last : std_logic;
signal axis_word_vld : std_logic;
begin
process(ap_clk)
begin
if(ap_clk'event and ap_clk = '1') then
if(tap_0_we = '1') then
tap_0 <= ap_oarg_din;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
tap_0_vld <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(tap_0_vld = '0' or (tap_0_vld and tap_0_rdy) = '1') then
tap_0_vld <= tap_0_we;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
state <= idle;
tap_0_start <= '0';
ap_arg_rqt <= '1';
elsif(ap_clk'event and ap_clk = '1') then
case state is
when idle =>
if(ap_start = '1') then
state <= running;
tap_0_start <= '1';
end if;
when running =>
if(ap_done = '1') then
if (ap_oarg_we = '0' and fifo_din_rdy = '1') then
state <= idle;
else
state <= pending_last;
ap_arg_rqt <= '0';
end if;
end if;
if((fifo_din_vld and fifo_din_rdy) = '1') then
tap_0_start <= '0';
end if;
when pending_last =>
if(tap_0_vld = '0' or (tap_0_vld and fifo_din_rdy) = '1') then
state <= idle;
ap_arg_rqt <= '1';
end if;
when others =>
end case;
end if;
end process;
process(state, ap_oarg_we, tap_0_vld, fifo_din_rdy, ap_done)
begin
ap_oarg_full_n <= '0';
tap_0_we <= '0';
tap_0_rdy <= '0';
tap_0_end <= '0';
fifo_din_vld <= '0';
case state is
when idle =>
ap_oarg_full_n <= '1';
when running =>
-- We enable writes in tap_0 when:
-- 1. it's empty or
-- 2. it's full and we can transfer the contents to the FIFO.
-- Write is efective when the above conditions are valid and a new
-- data value is received
tap_0_we <= ap_oarg_we and (not(tap_0_vld) or (tap_0_vld and fifo_din_rdy));
-- We enable receive data values if:
-- 1. tap_0 is empty
-- 2. tap_0 is full amd it's content can be transfered to the FIFO.
ap_oarg_full_n <= not(tap_0_vld) or (tap_0_vld and fifo_din_rdy);
-- We write in the FIFO when tap_0 is full and:
-- 1. arrives a new value at the input or
-- 2. finishes execution (ap_done = '1')
fifo_din_vld <= tap_0_vld and (ap_oarg_we or ap_done);
-- If the write in the fifo is efective, we take the contents of tap_0:
-- take the contents of tap_0 when the FIFO accepts the data value.
tap_0_rdy <= (tap_0_vld and (ap_oarg_we or ap_done)) and fifo_din_rdy;
-- Last data value written in the FIFO because we've received an ap_done
tap_0_end <= tap_0_vld and ap_done;
when pending_last =>
tap_0_end <= '1';
-- Write in the fifo when tap_0 is full and arrives a new data value
-- at the input
fifo_din_vld <= tap_0_vld;
-- In that moment, we take the content of tap_0
tap_0_rdy <= tap_0_vld and fifo_din_rdy;
when others =>
end case;
end process;
fifo_din(FIFO_DATA_MSB downto FIFO_DATA_LSB) <= tap_0;
fifo_din(FIFO_START_BIT) <= tap_0_start;
fifo_din(FIFO_END_BIT) <= tap_0_end;
FIFO_I : entity axis_accelerator_adapter_v2_1_6.s2s_async_fifo_wt
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
DEPTH => FIFO_DEPTH,
WIDTH => FIFO_WIDTH)
port map (
din => fifo_din,
din_vld => fifo_din_vld,
din_rdy => fifo_din_rdy,
wr_clk => ap_clk,
wr_rst => ap_rst,
dout => fifo_dout,
dout_vld => dout_vld,
dout_rdy => dout_rdy,
rd_clk => M_AXIS_ACLK,
rd_rst => axis_rst);
dout <= fifo_dout(FIFO_DATA_MSB downto FIFO_DATA_LSB);
dout_start <= fifo_dout(FIFO_START_BIT);
dout_end <= fifo_dout(FIFO_END_BIT);
process(M_AXIS_ACLK)
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_beat_clr = '1') then
axis_beat_cnt <= unsigned(xd_sw_length);
elsif(axis_beat_dec = '1') then
axis_beat_cnt <= axis_beat_cnt-1;
end if;
end if;
end process;
axis_beat_end <= '1' when (axis_beat_cnt = 1) else '0';
process(M_AXIS_ACLK, ap_rst_axi)
begin
if(ap_rst_axi = '1') then
axis_state <= idle;
apply_sw_length <= '0';
elsif(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
case axis_state is
when idle =>
-- Don't start until the first data value of a new frame
-- is available:
if((dout_vld and dout_start) = '1') then
apply_sw_length <= use_sw_length;
-- Wait for a valid SW length if it's going to be used
if(use_sw_length = '1') then
if(xd_sw_length_vld = '1') then
axis_state <= running;
end if;
else
axis_state <= running;
end if;
end if;
when running =>
if((axis_ce and dout_vld) = '1') then
if(apply_sw_length = '0') then
if(dout_end = '1') then
axis_state <= idle;
end if;
else
if(axis_beat_end = '0' and dout_end = '1') then
axis_state <= padding;
elsif(axis_beat_end = '1' and dout_end = '0') then
axis_state <= discarding;
elsif(axis_beat_end = '1' and dout_end = '1') then
axis_state <= idle;
end if;
end if;
end if;
when discarding =>
if(dout_end = '1') then
axis_state <= idle;
end if;
when padding =>
if((axis_ce and axis_beat_end) = '1') then
axis_state <= idle;
end if;
when others =>
end case;
end if;
end process;
process(axis_state, use_sw_length, dout_start, dout_vld, axis_ce, axis_beat_end, dout_end)
begin
xd_sw_length_rdy <= '0';
axis_beat_clr <= '0';
axis_beat_dec <= '0';
dout_rdy <= '0';
axis_we <= '0';
next_axis_last <= '0';
axis_word_vld <= '0';
case axis_state is
when idle =>
xd_sw_length_rdy <= use_sw_length and dout_start and dout_vld;
axis_beat_clr <= '1';
when running =>
axis_we <= dout_vld;
dout_rdy <= axis_ce and dout_vld;
axis_beat_dec <= axis_ce and dout_vld;
if(use_sw_length = '0') then
next_axis_last <= dout_end;
axis_word_vld <= '1';
else
if(axis_beat_end = '0' and dout_end = '0') then -- normal opperation
next_axis_last <= '0';
axis_word_vld <= '1';
elsif(axis_beat_end = '0' and dout_end = '1') then -- doing padding
next_axis_last <= '0';
axis_word_vld <= '1';
elsif(axis_beat_end = '1' and dout_end = '0') then -- doing discarding
next_axis_last <= '1';
axis_word_vld <= '1';
elsif(axis_beat_end = '1' and dout_end = '1') then -- sw_length = hw_length
next_axis_last <= '1';
axis_word_vld <= '1';
end if;
end if;
when discarding =>
dout_rdy <= '1';
when padding =>
axis_we <= '1';
axis_beat_dec <= axis_ce;
next_axis_last <= axis_beat_end;
axis_word_vld <= '0';
when others =>
end case;
end process;
axis_ce <= not(axis_vld) or (axis_vld and axis_rdy);
process(M_AXIS_ACLK, ap_rst_axi)
begin
if(ap_rst_axi = '1') then
axis_vld <= '0';
elsif(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_ce = '1') then
axis_vld <= axis_we;
end if;
end if;
end process;
process(M_AXIS_ACLK)
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_ce = '1') then
axis_data <= (others => '0');
if(axis_word_vld = '1') then
axis_data <= dout;
end if;
axis_last <= next_axis_last;
end if;
end if;
end process;
axis_keep <= (others => '1');
axis_rdy <= M_AXIS_TREADY;
end generate SAME_WIDTH_GEN;
AXI_WIDER_GEN : if (C_M_AXIS_TDATA_WIDTH > C_AP_ARG_DATA_WIDTH) generate
-- Notes:
-- This design is based on using a temporal register, where input data is
-- stored before pushing to the FIFO. This register is used to pack
-- received data and form an AXI-stream data beat. the last AXI-stream beat
-- (TLAST high) will be the data stored in the register when we receive an
-- ap_done. When we receive ap_done, two things could happen:
--
-- 1. New data is being written. this means ap_oarg_we = '1' and ap_oarg_full_n =
-- '1'; that is, tap_0_we = '1'. the input data value should be accepted
-- otherwise ap_done would not go high.
-- a. if the temporal register is full, this new write will push the
-- data to the fifo (fifo will always accept otherwise ap_oarg_full_n
-- would be active and ap_done will not be generated). At the same time,
-- this new data value into the temporal register. in the next cycle,
-- we're in pending_last state, we have a incomplete data beat to write
-- in the fifo (last AXI-stream beat).
-- b. If the temporal register (tap_0) is incomplete, it can complete or
-- not with this data write. In any case, the final content will be
-- available next cycle (pendign_last state). in this state, it will
-- be pushed to the FIFO labeled as last beat in stream.
--
-- 2. NO new data is being written. In this case, temporal register can be:
-- * complete (full). signal tap_0_vld = '1'
-- * partially complete. signal tap_0_strb(0)='1'. that is, at least,
-- firt ap_word has data.
-- * completely empty. This is not impossible case.
--
-- if regiter is complete or partially complete, it's content should be
-- pushed to the FIFO. these two cases can be characterized by tap_0_strb(0)='1'
-- to mantain coherence with case 1, this transfer to fifo will occur in
-- the next state (pending_last), although in theory could happen in
-- running state.
-- there is a special condition. if we receive ap_done and we're not
-- receiving new data and register is complete, we could try to transfer
-- to the fifo.
constant WORDS_PER_BEAT : integer := C_M_AXIS_TDATA_WIDTH/C_AP_ARG_DATA_WIDTH;
signal word_sel : std_logic_vector(WORDS_PER_BEAT-1 downto 0);
signal word_clr : std_logic;
type state_type is (
-- pragma translate_off
stop,
-- pragma translate_on
idle,
running,
pending_last);
signal state : state_type;
signal tap_0 : std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
signal tap_0_we : std_logic;
signal tap_0_vld : std_logic;
signal tap_0_rdy : std_logic;
signal tap_0_start : std_logic;
signal tap_0_end : std_logic;
signal tap_0_strb : std_logic_vector(WORDS_PER_BEAT-1 downto 0);
constant FIFO_DATA_LSB : integer := 0;
constant FIFO_DATA_MSB : integer := C_M_AXIS_TDATA_WIDTH-1;
constant FIFO_STRB_LSB : integer := FIFO_DATA_MSB+1;
constant FIFO_STRB_MSB : integer := FIFO_STRB_LSB+WORDS_PER_BEAT-1;
constant FIFO_START_BIT : integer := FIFO_STRB_MSB+1;
constant FIFO_END_BIT : integer := FIFO_START_BIT+1;
constant FIFO_WIDTH : integer := FIFO_END_BIT+1;
signal fifo_din : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_dout : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_din_vld : std_logic;
signal fifo_din_rdy : std_logic;
-- tap_0 is an extra position for the FIFO; substract one
constant DATA_RATIO : integer := C_M_AXIS_TDATA_WIDTH/C_AP_ARG_DATA_WIDTH;
constant FIFO_DEPTH : integer := (2**(C_AP_ARG_ADDR_WIDTH-log2(DATA_RATIO)))-1;
type axis_state_type is (
-- pragma translate_off
stop,
-- pragma translate_on
idle,
running,
discarding,
padding);
signal axis_state : axis_state_type;
signal apply_sw_length : std_logic;
-- These are the signal for the FIFO output:
signal dout : std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
signal dout_word_en : std_logic_vector(WORDS_PER_BEAT-1 downto 0);
signal dout_start : std_logic;
signal dout_end : std_logic;
signal dout_vld : std_logic;
signal dout_rdy : std_logic;
constant AXIS_BEAT_REM_WIDTH : integer := log2(DATA_RATIO);
constant AXIS_BEAT_CNT_WIDTH : integer := SW_LENGTH_WIDTH-AXIS_BEAT_REM_WIDTH;
constant AXIS_BEAT_CNT_LSB : integer := AXIS_BEAT_REM_WIDTH;
constant AXIS_BEAT_CNT_MSB : integer := SW_LENGTH_WIDTH-1;
-- AXI stream beat counter:
signal axis_beat_cnt : unsigned(AXIS_BEAT_CNT_WIDTH-1 downto 0);
signal axis_beat_dec : std_logic;
signal axis_beat_clr : std_logic;
signal axis_beat_cnt_0 : std_logic;
signal axis_beat_cnt_1 : std_logic;
signal axis_beat_end : std_logic;
-- sw_length_with_rem is set when the configured SW length is not
-- a integer multiple of C_M_AXIS_TDATA_WIDTH
signal sw_length_with_rem : std_logic;
-- In this case, sw_last_word_en provides the enabled words
-- for last AXIS beat
signal sw_last_word_en : std_logic_vector(WORDS_PER_BEAT-1 downto 0);
-- Output stage control:
signal axis_ce : std_logic;
signal axis_we : std_logic;
-- These signals are used to generate tlast and tkeep for the output
-- stage. next_axis_last marks the last beat. next_axis_word_en indicates
-- the enabled words (those which have the tkeep bits activated). It will
-- be unrolled to generate tkee. Finally, axis_word_vld indicates which
-- words are going to keep their original value. Not valid words will be
-- forced to zero during padding.
signal next_axis_last : std_logic;
signal next_axis_word_en : std_logic_vector(WORDS_PER_BEAT-1 downto 0);
signal axis_word_vld : std_logic_vector(WORDS_PER_BEAT-1 downto 0);
signal ap_oarg_full_n_i : std_logic;
begin
-- With this shift register, we select the destination word within the
-- temporal register
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
word_sel <= (others => '0');
word_sel(0) <= '1';
elsif(ap_clk'event and ap_clk = '1') then
if(word_clr = '1') then
word_sel <= (others => '0');
word_sel(0) <= '1';
elsif(tap_0_we = '1') then
word_sel <= word_sel(WORDS_PER_BEAT-2 downto 0) & word_sel(WORDS_PER_BEAT-1);
end if;
end if;
end process;
process(ap_clk)
begin
if(ap_clk'event and ap_clk = '1') then
if(tap_0_we = '1') then
for i in 0 to WORDS_PER_BEAT-1 loop
if(word_sel(i) = '1') then
tap_0(C_AP_ARG_DATA_WIDTH*(i+1)-1 downto C_AP_ARG_DATA_WIDTH*i) <= ap_oarg_din;
end if;
end loop;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
tap_0_strb <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
-- when the register value is taken, we clean strb, unless we are
-- receiving the first word of the following beat
if((fifo_din_vld and fifo_din_rdy) = '1') then
tap_0_strb <= (others => '0');
tap_0_strb(0) <= tap_0_we;
elsif(tap_0_we = '1') then
-- In the rest of cases, we activate the correct bit
tap_0_strb <= tap_0_strb or word_sel;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
tap_0_vld <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(tap_0_vld = '0' or (tap_0_vld and tap_0_rdy) = '1') then
-- The input reg has a new valid data value when:
-- 1. a new data value is written to complte the fifo word (bit width)
-- 2. a new data value is written at the same time ap_done is active
-- (fifo word might be complete/incomplete)
-- 3. we receive ap_done and there is data remaining in the register
tap_0_vld <= (tap_0_we and (word_sel(WORDS_PER_BEAT-1))) or
(tap_0_we and ap_done);
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
state <= idle;
tap_0_start <= '0';
ap_arg_rqt <= '1';
elsif(ap_clk'event and ap_clk = '1') then
case state is
when idle =>
if(ap_start = '1') then
state <= running;
tap_0_start <= '1';
end if;
when running =>
if(ap_done = '1') then
state <= pending_last;
ap_arg_rqt <= '0';
end if;
if((fifo_din_vld and fifo_din_rdy) = '1') then
tap_0_start <= '0';
end if;
when pending_last =>
if(tap_0_strb(0) = '0' or (tap_0_strb(0) and fifo_din_rdy) = '1') then
state <= idle;
ap_arg_rqt <= '1';
end if;
when others =>
end case;
end if;
end process;
process(state, ap_oarg_we, tap_0_vld, fifo_din_rdy, tap_0_strb)
begin
ap_oarg_full_n_i <= '0';
tap_0_we <= '0';
tap_0_rdy <= '0';
tap_0_end <= '0';
fifo_din_vld <= '0';
word_clr <= '0';
case state is
when idle =>
word_clr <= '1';
ap_oarg_full_n_i <= '1';
when running =>
-- We enable writting in tap_0 when:
-- 1. it's empty or
-- 2. it's full and its contents can be transfered to the FIFO
-- Write is efective when these two conditions are met and a new data
-- value is received.
tap_0_we <= ap_oarg_we and (not(tap_0_vld) or (tap_0_vld and fifo_din_rdy));
-- We enable received new data if:
-- 1. tap_0 is empty
-- 2. tap_0 is full and its contents can be transfered ot the FIFO
ap_oarg_full_n_i <= not(tap_0_vld) or (tap_0_vld and fifo_din_rdy);
-- we write in the FIFO when:
-- 1. tap_0 is full and arrives a new input value or
-- 2. finishes execution (ap_done = '1'), no new data received (ap_oarg_we = '0')
-- and tap_0 is not empty (tap_0_strb(0) = '1').
fifo_din_vld <= (tap_0_vld and ap_oarg_we);
-- If fifo write is efective, we take the contents of tap_0
tap_0_rdy <= (tap_0_vld and ap_oarg_we);
when pending_last =>
tap_0_end <= '1';
fifo_din_vld <= tap_0_strb(0);
tap_0_rdy <= fifo_din_rdy;
when others =>
end case;
end process;
ap_oarg_full_n <= ap_oarg_full_n_i;
fifo_din(FIFO_DATA_MSB downto FIFO_DATA_LSB) <= tap_0;
fifo_din(FIFO_STRB_MSB downto FIFO_STRB_LSB) <= tap_0_strb;
fifo_din(FIFO_START_BIT) <= tap_0_start;
fifo_din(FIFO_END_BIT) <= tap_0_end;
FIFO_I : entity axis_accelerator_adapter_v2_1_6.s2s_async_fifo_wt
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
DEPTH => FIFO_DEPTH,
WIDTH => FIFO_WIDTH)
port map (
din => fifo_din,
din_vld => fifo_din_vld,
din_rdy => fifo_din_rdy,
wr_clk => ap_clk,
wr_rst => ap_rst,
dout => fifo_dout,
dout_vld => dout_vld,
dout_rdy => dout_rdy,
rd_clk => M_AXIS_ACLK,
rd_rst => axis_rst);
dout <= fifo_dout(FIFO_DATA_MSB downto FIFO_DATA_LSB);
dout_word_en <= fifo_dout(FIFO_STRB_MSB downto FIFO_STRB_LSB);
dout_start <= fifo_dout(FIFO_START_BIT);
dout_end <= fifo_dout(FIFO_END_BIT);
-- This counter is used to control the number of AXIS beats set by the SW length
process(M_AXIS_ACLK)
variable aux : unsigned(AXIS_BEAT_CNT_WIDTH-1 downto 0);
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_beat_clr = '1') then
aux := unsigned(xd_sw_length(AXIS_BEAT_CNT_MSB downto AXIS_BEAT_CNT_LSB));
axis_beat_cnt <= aux;
elsif(axis_beat_dec = '1') then
axis_beat_cnt <= axis_beat_cnt-1;
end if;
end if;
end process;
-- This register is initialized when the axis_beat_cnt counter (SW length) is
-- loaded. It's used to determine if the last beat is full (no remainder)
process(M_AXIS_ACLK)
variable beat_rem : unsigned(AXIS_BEAT_REM_WIDTH-1 downto 0);
variable upper_word_en : unsigned(AXIS_BEAT_REM_WIDTH-1 downto 0);
constant BYTES_PER_WORD : integer := C_AP_ARG_DATA_WIDTH/8;
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_beat_clr = '1') then
beat_rem := unsigned(xd_sw_length(AXIS_BEAT_REM_WIDTH-1 downto 0));
if(beat_rem = 0) then
sw_length_with_rem <= '0';
else
sw_length_with_rem <= '1';
end if;
upper_word_en := unsigned(xd_sw_length(AXIS_BEAT_CNT_LSB-1 downto 0)) - 1;
for i in 0 to WORDS_PER_BEAT-1 loop
if(i > upper_word_en) then
sw_last_word_en(i) <= '0';
else
sw_last_word_en(i) <= '1';
end if;
end loop;
end if;
end if;
end process;
process(axis_beat_cnt)
begin
axis_beat_cnt_0 <= '0';
axis_beat_cnt_1 <= '0';
if(axis_beat_cnt(axis_beat_CNT_WIDTH-1 downto 1) = 0) then
axis_beat_cnt_0 <= not(axis_beat_cnt(0));
axis_beat_cnt_1 <= axis_beat_cnt(0);
end if;
end process;
axis_beat_end <= axis_beat_cnt_1 when (sw_length_with_rem = '0') else axis_beat_cnt_0;
process(M_AXIS_ACLK, ap_rst_axi)
begin
if(ap_rst_axi = '1') then
axis_state <= idle;
apply_sw_length <= '0';
elsif(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
case axis_state is
when idle =>
-- Don't start until the first data value of a new frame
-- is available:
if((dout_vld and dout_start) = '1') then
apply_sw_length <= use_sw_length;
-- Wait for a valid SW length if it's going to be used
if(use_sw_length = '1') then
if(xd_sw_length_vld = '1') then
axis_state <= running;
end if;
else
axis_state <= running;
end if;
end if;
when running =>
if((axis_ce and dout_vld) = '1') then
if(apply_sw_length = '0') then
if(dout_end = '1') then
axis_state <= idle;
end if;
else
if(axis_beat_end = '0' and dout_end = '1') then
axis_state <= padding;
elsif(axis_beat_end = '1' and dout_end = '0') then
axis_state <= discarding;
elsif(axis_beat_end = '1' and dout_end = '1') then
axis_state <= idle;
end if;
end if;
end if;
when discarding =>
if(dout_end = '1') then
axis_state <= idle;
end if;
when padding =>
if((axis_ce and axis_beat_end) = '1') then
axis_state <= idle;
end if;
when others =>
end case;
end if;
end process;
process(axis_state, use_sw_length, dout_start, dout_vld, axis_ce, dout_end, dout_word_en, axis_beat_end, sw_last_word_en)
constant BYTES_PER_WORD : integer := C_AP_ARG_DATA_WIDTH/8;
constant AXIS_KEEP_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
begin
xd_sw_length_rdy <= '0';
axis_beat_clr <= '0';
axis_beat_dec <= '0';
dout_rdy <= '0';
axis_we <= '0';
next_axis_last <= '0';
axis_word_vld <= (others => '0'); -- used during padding to fill with zeros
next_axis_word_en <= (others => '0'); -- used to generate axis_keep
case axis_state is
when idle =>
xd_sw_length_rdy <= use_sw_length and dout_start and dout_vld;
axis_beat_clr <= '1';
when running =>
axis_we <= dout_vld;
dout_rdy <= axis_ce and dout_vld;
axis_beat_dec <= axis_ce and dout_vld;
if(use_sw_length = '0') then
next_axis_last <= dout_end;
next_axis_word_en <= dout_word_en;
axis_word_vld <= dout_word_en;
else
if(axis_beat_end = '0' and dout_end = '0') then -- normal opperation
next_axis_last <= '0';
next_axis_word_en <= (others => '1');
axis_word_vld <= dout_word_en;
elsif(axis_beat_end = '0' and dout_end = '1') then -- doing padding
next_axis_last <= '0';
next_axis_word_en <= (others => '1');
axis_word_vld <= dout_word_en;
elsif(axis_beat_end = '1' and dout_end = '0') then -- doing discarding
next_axis_last <= '1';
next_axis_word_en <= sw_last_word_en;
axis_word_vld <= sw_last_word_en;
elsif(axis_beat_end = '1' and dout_end = '1') then -- sw_length = hw_length
-- We get here when the number of HW beats is equal to the number of
-- SW beats. It doesn't necessary mean that sw_length = hw_length
-- because the remainders can be different.
-- In this case the enabled words (the ones which have tkeep
-- at '1') are controled by SW. The valid words (the ones which
-- are not forced to zero) are most restrictive one because
-- padding or discarding can being carried out.
next_axis_last <= '1';
next_axis_word_en <= sw_last_word_en;
axis_word_vld <= dout_word_en and sw_last_word_en;
end if;
end if;
when discarding =>
dout_rdy <= '1';
when padding =>
axis_we <= '1';
axis_beat_dec <= axis_ce;
next_axis_last <= axis_beat_end;
if(axis_beat_end = '0') then
next_axis_word_en <= (others => '1');
else
next_axis_word_en <= sw_last_word_en;
end if;
when others =>
end case;
end process;
axis_ce <= not(axis_vld) or (axis_vld and axis_rdy);
process(M_AXIS_ACLK, ap_rst_axi)
begin
if(ap_rst_axi = '1') then
axis_vld <= '0';
elsif(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_ce = '1') then
axis_vld <= axis_we;
end if;
end if;
end process;
process(M_AXIS_ACLK)
constant BYTES_PER_WORD : integer := C_AP_ARG_DATA_WIDTH/8;
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_ce = '1') then
axis_data <= (others => '0');
for i in 0 to WORDS_PER_BEAT-1 loop
if (axis_word_vld(i) = '1') then
axis_data(C_AP_ARG_DATA_WIDTH*(i+1)-1 downto C_AP_ARG_DATA_WIDTH*i) <=
dout(C_AP_ARG_DATA_WIDTH*(i+1)-1 downto C_AP_ARG_DATA_WIDTH*i);
end if;
end loop;
axis_last <= next_axis_last;
-- unroll axis_beat_en to get axis_keep
for i in 0 to WORDS_PER_BEAT-1 loop
axis_keep(BYTES_PER_WORD*(i+1)-1 downto BYTES_PER_WORD*i) <=
(others => next_axis_word_en(i));
end loop;
end if;
end if;
end process;
axis_rdy <= M_AXIS_TREADY;
end generate AXI_WIDER_GEN;
AXI_NARROWER_GEN : if (C_M_AXIS_TDATA_WIDTH < C_AP_ARG_DATA_WIDTH) generate
signal tap_0 : std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
signal tap_0_we : std_logic;
signal tap_0_vld : std_logic;
signal tap_0_rdy : std_logic;
signal tap_0_start : std_logic;
signal tap_0_end : std_logic;
constant FIFO_DATA_LSB : integer := 0;
constant FIFO_DATA_MSB : integer := C_AP_ARG_DATA_WIDTH-1;
constant FIFO_START_BIT : integer := FIFO_DATA_MSB+1;
constant FIFO_END_BIT : integer := FIFO_START_BIT+1;
constant FIFO_WIDTH : integer := FIFO_END_BIT+1;
signal fifo_din : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_din_vld : std_logic;
signal fifo_din_rdy : std_logic;
signal fifo_dout : std_logic_vector(FIFO_WIDTH-1 downto 0);
signal fifo_dout_vld : std_logic;
signal fifo_dout_rdy : std_logic;
type state_type is (
-- pragma translate_off
stop,
-- pragma translate_on
idle,
running,
pending_last);
signal state : state_type;
-- tap_0 is an extra position for the FIFO; substract one
constant FIFO_DEPTH : integer := (2**C_AP_ARG_ADDR_WIDTH)-1;
type axis_state_type is (
-- pragma translate_off
stop,
-- pragma translate_on
idle,
running,
discarding,
padding);
signal axis_state : axis_state_type;
signal apply_sw_length : std_logic;
-- These are the signal for the FIFO output:
signal dout : std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
signal dout_start : std_logic;
signal dout_end : std_logic;
signal dout_vld : std_logic;
signal dout_rdy : std_logic;
-- Next signals are used to implement a counter to count the
-- axi beats needed to transmit each core word.
constant BEATS_PER_WORD : integer := C_AP_ARG_DATA_WIDTH/C_M_AXIS_TDATA_WIDTH;
constant BEAT_CNT_WIDTH : integer := log2(BEATS_PER_WORD);
signal beat_cnt : unsigned(BEAT_CNT_WIDTH-1 downto 0);
signal beat_inc : std_logic;
signal beat_clr : std_logic;
signal beat_end : std_logic;
constant AXIS_WORD_CNT_WIDTH : integer := SW_LENGTH_WIDTH;
-- AXI stream ap_word counter:
signal axis_word_cnt : unsigned(AXIS_WORD_CNT_WIDTH-1 downto 0);
signal axis_word_dec : std_logic;
signal axis_word_clr : std_logic;
signal axis_word_end : std_logic;
-- Output stage control:
signal axis_ce : std_logic;
signal axis_we : std_logic;
signal next_axis_last : std_logic;
signal axis_word_vld : std_logic;
begin
process(ap_clk)
begin
if(ap_clk'event and ap_clk = '1') then
if(tap_0_we = '1') then
tap_0 <= ap_oarg_din;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
tap_0_vld <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(tap_0_vld = '0' or (tap_0_vld and tap_0_rdy) = '1') then
tap_0_vld <= tap_0_we;
end if;
end if;
end process;
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
state <= idle;
tap_0_start <= '0';
ap_arg_rqt <= '1';
elsif(ap_clk'event and ap_clk = '1') then
case state is
when idle =>
if(ap_start = '1') then
state <= running;
tap_0_start <= '1';
end if;
when running =>
if(ap_done = '1') then
if (ap_oarg_we = '0' and fifo_din_rdy = '1') then
state <= idle;
else
state <= pending_last;
ap_arg_rqt <= '0';
end if;
end if;
if((fifo_din_vld and fifo_din_rdy) = '1') then
tap_0_start <= '0';
end if;
when pending_last =>
if(tap_0_vld = '0' or (tap_0_vld and fifo_din_rdy) = '1') then
state <= idle;
ap_arg_rqt <= '1';
end if;
when others =>
end case;
end if;
end process;
process(state, ap_oarg_we, tap_0_vld, fifo_din_rdy, ap_done)
begin
ap_oarg_full_n <= '0';
tap_0_we <= '0';
tap_0_rdy <= '0';
tap_0_end <= '0';
fifo_din_vld <= '0';
case state is
when idle =>
ap_oarg_full_n <= '1';
when running =>
-- We write in tap_0 when:
-- 1. it's empty or
-- 2. it's full and it's content can be transfered to the FIFO.
-- Write is efective when these two conditions are met and new data arrives.
tap_0_we <= ap_oarg_we and (not(tap_0_vld) or (tap_0_vld and fifo_din_rdy));
-- We enable receiving new data if:
-- 1. tap_0 is empty
-- 2. tap_0 is full and its contents can be transfered to the FIFO
ap_oarg_full_n <= not(tap_0_vld) or (tap_0_vld and fifo_din_rdy);
-- Write in the FIFO when tap_0 is full and:
-- 1. arrived a new data value at the input or
-- 2. we've received the last data beat (ap_done = '1')
fifo_din_vld <= tap_0_vld and (ap_oarg_we or ap_done);
-- If write in the fifo is efective, we take the contents of tap_0:
-- We take contents of tap_0 when FIFO accepts the data
tap_0_rdy <= tap_0_vld and (ap_oarg_we or ap_done) and fifo_din_rdy;
-- It's the last data if the write in the fifo is due to ap_done:
tap_0_end <= tap_0_vld and ap_done;
when pending_last =>
tap_0_end <= '1';
-- Write in the fifo when tap_0 is full and arrives a new data at the
-- input:
fifo_din_vld <= tap_0_vld;
-- At that moment, we take the contents of tap_0:
tap_0_rdy <= tap_0_vld and fifo_din_rdy;
when others =>
end case;
end process;
fifo_din(FIFO_DATA_MSB downto FIFO_DATA_LSB) <= tap_0;
fifo_din(FIFO_START_BIT) <= tap_0_start;
fifo_din(FIFO_END_BIT) <= tap_0_end;
FIFO_I : entity axis_accelerator_adapter_v2_1_6.s2s_async_fifo_wt
generic map (
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
DEPTH => FIFO_DEPTH,
WIDTH => FIFO_WIDTH)
port map (
din => fifo_din,
din_vld => fifo_din_vld,
din_rdy => fifo_din_rdy,
wr_clk => ap_clk,
wr_rst => ap_rst,
dout => fifo_dout,
dout_vld => dout_vld,
dout_rdy => dout_rdy,
rd_clk => M_AXIS_ACLK,
rd_rst => axis_rst);
dout <= fifo_dout(FIFO_DATA_MSB downto FIFO_DATA_LSB);
dout_start <= fifo_dout(FIFO_START_BIT);
dout_end <= fifo_dout(FIFO_END_BIT);
process(M_AXIS_ACLK)
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_word_clr = '1') then
axis_word_cnt <= unsigned(xd_sw_length);
elsif(axis_word_dec = '1') then
axis_word_cnt <= axis_word_cnt-1;
end if;
end if;
end process;
axis_word_end <= '1' when (axis_word_cnt = 1) else '0';
process(M_AXIS_ACLK, ap_rst_axi)
begin
if(ap_rst_axi = '1') then
axis_state <= idle;
apply_sw_length <= '0';
elsif(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
case axis_state is
when idle =>
-- Don't start until the first datum of a new frame
-- is available:
if((dout_vld and dout_start) = '1') then
apply_sw_length <= use_sw_length;
-- Wait for a valid SW length if it's going to be used
if(use_sw_length = '1') then
if(xd_sw_length_vld = '1') then
axis_state <= running;
end if;
else
axis_state <= running;
end if;
end if;
when running =>
if((axis_ce and dout_vld and beat_end) = '1') then
if(apply_sw_length = '0') then
if(dout_end = '1') then
axis_state <= idle;
end if;
else
if(axis_word_end = '0' and dout_end = '1') then
axis_state <= padding;
elsif(axis_word_end = '1' and dout_end = '0') then
axis_state <= discarding;
elsif(axis_word_end = '1' and dout_end = '1') then
axis_state <= idle;
end if;
end if;
end if;
when discarding =>
if(dout_end = '1') then
axis_state <= idle;
end if;
when padding =>
if((axis_ce and axis_word_end and beat_end) = '1') then
axis_state <= idle;
end if;
when others =>
end case;
end if;
end process;
process(axis_state, use_sw_length, dout_start, dout_vld, axis_ce, axis_word_end, dout_end, beat_end)
begin
xd_sw_length_rdy <= '0';
axis_word_clr <= '0';
axis_word_dec <= '0';
dout_rdy <= '0';
axis_we <= '0';
next_axis_last <= '0';
axis_word_vld <= '0';
beat_inc <= '0';
case axis_state is
when idle =>
xd_sw_length_rdy <= use_sw_length and dout_start and dout_vld;
axis_word_clr <= '1';
when running =>
axis_word_clr <= '0';
axis_we <= dout_vld;
-- Consume the FIFO output when the last beat of the ap_word is
-- transfered to the output reg:
dout_rdy <= axis_ce and dout_vld and beat_end;
axis_word_dec <= axis_ce and dout_vld and beat_end;
beat_inc <= axis_ce and dout_vld;
if(use_sw_length = '0') then
next_axis_last <= dout_end and beat_end;
axis_word_vld <= '1';
else
if(axis_word_end = '0' and dout_end = '0') then -- normal opperation
next_axis_last <= '0';
axis_word_vld <= '1';
elsif(axis_word_end = '0' and dout_end = '1') then -- doing padding
next_axis_last <= '0';
axis_word_vld <= '1';
elsif(axis_word_end = '1' and dout_end = '0') then -- doing discarding
next_axis_last <= beat_end;
axis_word_vld <= '1';
elsif(axis_word_end = '1' and dout_end = '1') then -- sw_length = hw_length
next_axis_last <= beat_end;
axis_word_vld <= '1';
end if;
end if;
when discarding =>
dout_rdy <= '1';
when padding =>
axis_we <= '1';
axis_word_dec <= axis_ce and beat_end;
beat_inc <= axis_ce;
next_axis_last <= axis_word_end and beat_end;
axis_word_vld <= '0';
when others =>
end case;
end process;
-- Increment beat_cnt each time a beat is transfered to the output tap:
process(M_AXIS_ACLK, axis_rst)
begin
if(axis_rst = '1') then
beat_cnt <= (others => '0');
elsif(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(beat_inc = '1') then
beat_cnt <= beat_cnt + 1;
end if;
end if;
end process;
beat_end <= '1' when (beat_cnt = BEATS_PER_WORD-1) else '0';
axis_ce <= not(axis_vld) or (axis_vld and axis_rdy);
process(M_AXIS_ACLK, axis_rst)
begin
if(axis_rst = '1') then
axis_vld <= '0';
elsif(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_ce = '1') then
axis_vld <= axis_we;
end if;
end if;
end process;
-- Output register:
process(M_AXIS_ACLK)
variable aux : std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
begin
if(M_AXIS_ACLK'event and M_AXIS_ACLK = '1') then
if(axis_ce = '1') then
axis_data <= (others => '0');
if(axis_word_vld = '1') then
aux := fifo_dout(FIFO_DATA_MSB downto FIFO_DATA_LSB);
for i in 0 to BEATS_PER_WORD-1 loop
if (i = beat_cnt) then
axis_data <= aux(C_M_AXIS_TDATA_WIDTH*(i+1)-1 downto C_M_AXIS_TDATA_WIDTH*i);
end if;
end loop;
end if;
axis_last <= next_axis_last;
end if;
end if;
end process;
axis_keep <= (others => '1');
axis_rdy <= M_AXIS_TREADY;
end generate AXI_NARROWER_GEN;
end rtl;
|
mit
|
1fec10c8e0a1db75cd9fbdac6a597260
| 0.527874 | 3.441085 | false | false | false | false |
blutsvente/MIX
|
test/results/highlow/lownobus/ent_t-rtl-a.vhd
| 1 | 3,735 |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Tue Sep 27 05:17:18 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../highlow.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.6 2005/10/25 13:31:24 wig Exp $
-- $Date: 2005/10/25 13:31:24 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.6 2005/10/25 13:31:24 wig
-- Testcase result update
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.58 2005/09/14 14:40:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a --
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_partzero2_10_9_gi : in std_ulogic_vector(1 downto 0);
p_mix_partzero2_11_11_go : out std_ulogic;
p_mix_partzero2_15_12_gi : in std_ulogic_vector(3 downto 0);
p_mix_partzero2_5_0_go : out std_ulogic_vector(5 downto 0);
p_mix_partzero2_6_6_gi : in std_ulogic;
p_mix_partzero2_8_7_go : out std_ulogic_vector(1 downto 0)
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
constant partzero2_c : std_ulogic_vector(1 downto 0) := ( others => '1' );
constant partzero2_1c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant partzero2_2c : std_ulogic_vector(3 downto 0) := ( others => '0' );
signal s_int_partzero2 : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
partzero2(10 downto 9) <= partzero2_c;
partzero2(6) <= partzero2_1c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
partzero2(15 downto 12) <= partzero2_2c;
partzero2 <= s_int_partzero2; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_partzero2_10_9_gi => s_int_partzero2(10 downto 9), -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
p_mix_partzero2_11_11_go => s_int_partzero2(11), -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
p_mix_partzero2_15_12_gi => s_int_partzero2(15 downto 12), -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
p_mix_partzero2_5_0_go => s_int_partzero2(5 downto 0), -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
p_mix_partzero2_6_6_gi => s_int_partzero2(6), -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
p_mix_partzero2_8_7_go => s_int_partzero2(8 downto 7) -- map parts to high and low, 2map partzero to inst_aa, 2map partzero to inst_aa, 2, 2
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
;
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
gpl-3.0
|
3e1597bebce07f80bafa8ff63b443442
| 0.619813 | 2.968998 | false | false | false | false |
mitchsm/nvc
|
test/group/slice1.vhd
| 4 | 390 |
entity slice1 is
end entity;
architecture test of slice1 is
signal x : bit_vector(0 to 7);
signal y : bit_vector(7 downto 0);
begin
x(0 to 3) <= "1111";
x(4 to 2) <= (others => '0');
x(4 to 5) <= "00";
x(5 to 7) <= "111";
y(3 downto 0) <= "1111";
y(2 downto 4) <= (others => '0');
y(5 downto 4) <= "00";
y(7 downto 5) <= "111";
end architecture;
|
gpl-3.0
|
a2e0867ceeadbdc42a35cde1a695f288
| 0.515385 | 2.746479 | false | true | false | false |
mitchsm/nvc
|
test/regress/counter.vhd
| 5 | 920 |
entity counter_bot is
port (
clk : in bit;
count : out integer );
end entity;
architecture behav of counter_bot is
begin
process (clk) is
variable count_var : integer := 0;
begin
if clk'event and clk = '1' then
count_var := count_var + 1;
count <= count_var;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity counter is
end entity;
architecture test of counter is
signal clk : bit := '0';
signal count : integer := 0;
begin
clkgen: process is
begin
wait for 5 ns;
clk <= not clk;
end process;
uut: entity work.counter_bot
port map (
clk => clk,
count => count );
process (count) is
begin
report integer'image(count);
end process;
end architecture;
|
gpl-3.0
|
bbdd34487ef960b12ab6687ce3419845
| 0.502174 | 4.401914 | false | false | false | false |
mitchsm/nvc
|
test/lower/issue215.vhd
| 4 | 726 |
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
begin
PROC_A(I,O);
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
|
gpl-3.0
|
75eeec6bdd02ba59a9064b32e09128ea
| 0.550964 | 3.27027 | false | false | false | false |
mitchsm/nvc
|
test/regress/elab14.vhd
| 5 | 1,086 |
entity sub is
port (
i : in bit_vector(7 downto 0);
o : out bit_vector(7 downto 0) );
end entity;
architecture test of sub is
begin
o <= not i after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity elab14 is
end entity;
architecture test of elab14 is
signal a : bit_vector(1 downto 0);
signal b : bit_vector(5 downto 0);
signal c : bit_vector(5 downto 2);
signal d : bit_vector(3 downto 0);
begin
sub_i: entity work.sub
port map (
i(1 downto 0) => a,
i(7 downto 2) => b,
o(3 downto 0) => c,
o(7 downto 4) => d );
process is
begin
assert c = "0000";
assert d = "0000";
wait for 2 ns;
assert c = "1111";
assert d = "1111";
a <= "11";
wait for 2 ns;
assert c = "1100";
assert d = "1111";
b <= "011110";
wait for 2 ns;
assert c = "0100";
assert d = "1000";
wait;
end process;
end architecture;
|
gpl-3.0
|
fc3512a2b69078acdaa5c1beea7ef29c
| 0.46593 | 3.783972 | false | false | false | false |
mbrobbel/capi-streaming-framework
|
accelerator/pkg/control_package.vhd
| 1 | 1,479 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dma_package.all;
use work.psl.all;
use work.wed.all;
use work.cu_package.all;
package control_package is
----------------------------------------------------------------------------------------------------------------------- io
type control_ca_out is record
reset : std_logic;
end record;
type control_in is record
clk : std_logic;
ha : psl_control_in;
dc : dma_dc_out;
end record;
type control_out is record
ca : control_ca_out;
ah : psl_control_out;
cd : dma_cd_in;
end record;
----------------------------------------------------------------------------------------------------------------------- internals
type control_state is (
idle,
reset,
wed,
go,
done
);
type control_int is record
state : control_state;
start : std_logic;
wed : wed_type;
o : control_out;
end record;
procedure control_reset (signal r : inout control_int);
end package control_package;
package body control_package is
procedure control_reset (signal r : inout control_int) is
begin
r.state <= reset;
r.start <= '0';
r.o.ca.reset <= '0';
r.o.ah.running <= '0';
r.o.ah.done <= '0';
end procedure control_reset;
end package body control_package;
|
bsd-2-clause
|
7deb1c2593d8adff2fb51b033a7832f8
| 0.463827 | 4.131285 | false | false | false | false |
diogodanielsoaresferreira/VHDLExercises
|
Micro-Projeto/Fase 2/cliente_em_fila.vhd
| 1 | 674 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity cliente_em_fila is
port( client : in std_logic;
reset : in std_logic;
binOut2 : out std_logic_vector(6 downto 0);
ledOut : out std_logic);
end cliente_em_fila;
architecture Behavioral of cliente_em_fila is
signal count : unsigned(6 downto 0);
begin
process(client, reset)
begin
if(reset='1') then
count <= (others => '0');
ledOut<= '0';
elsif(rising_edge(client)) then
ledOut <= '1';
if (count = "1100011") then --99
count <= count;
else
count <= count + 1;
end if;
end if;
end process;
binOut2<= std_logic_vector(count);
end Behavioral;
|
gpl-2.0
|
d66dd3b3cce3f5565c70a5d1a60876a0
| 0.645401 | 2.785124 | false | false | false | false |
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